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Import 2.1.81
[davej-history.git] / drivers / isdn / hisax / teles3.c
blob22254604c96fffb88a405734cc33a0b4ac59a8c7
1 /* $Id: teles3.c,v 1.11 1997/04/13 19:54:05 keil Exp $
2
3 * teles3.c low level stuff for Teles 16.3 & PNP isdn cards
4 *
5 * based on the teles driver from Jan den Ouden
6 *
7 * Author Karsten Keil (keil@temic-ech.spacenet.de)
8 *
9 * Thanks to Jan den Ouden
10 * Fritz Elfert
11 * Beat Doebeli
12 *
13 * $Log: teles3.c,v $
14 * Revision 1.11 1997/04/13 19:54:05 keil
15 * Change in IRQ check delay for SMP
16 *
17 * Revision 1.10 1997/04/06 22:54:05 keil
18 * Using SKB's
19 *
20 * Revision 1.9 1997/03/22 02:01:07 fritz
21 * -Reworked toplevel Makefile. From now on, no different Makefiles
22 * for standalone- and in-kernel-compilation are needed any more.
23 * -Added local Rules.make for above reason.
24 * -Experimental changes in teles3.c for enhanced IRQ-checking with
25 * 2.1.X and SMP kernels.
26 * -Removed diffstd-script, same functionality is in stddiff -r.
27 * -Enhanced scripts std2kern and stddiff.
28 *
29 * Revision 1.8 1997/02/23 18:43:55 fritz
30 * Added support for Teles-Vision.
31 *
32 * Revision 1.7 1997/01/28 22:48:33 keil
33 * fixes for Teles PCMCIA (Christof Petig)
34 *
35 * Revision 1.6 1997/01/27 15:52:55 keil
36 * SMP proof,cosmetics, PCMCIA added
37 *
38 * Revision 1.5 1997/01/21 22:28:32 keil
39 * cleanups
40 *
41 * Revision 1.4 1996/12/14 21:05:41 keil
42 * Reset for 16.3 PnP
43 *
44 * Revision 1.3 1996/11/05 19:56:54 keil
45 * debug output fixed
46 *
47 * Revision 1.2 1996/10/27 22:09:15 keil
48 * cosmetic changes
49 *
50 * Revision 1.1 1996/10/13 20:04:59 keil
51 * Initial revision
52 *
53 *
54 *
55 */
56 #define __NO_VERSION__
57 #include "siemens.h"
58 #include "hisax.h"
59 #include "teles3.h"
60 #include "isdnl1.h"
61 #include <linux/kernel_stat.h>
62
63 extern const char *CardType[];
64 const char *teles3_revision = "$Revision: 1.11 $";
65
66 #define byteout(addr,val) outb_p(val,addr)
67 #define bytein(addr) inb_p(addr)
68
69 static inline u_char
70 readreg(unsigned int adr, u_char off)
71 {
72 return (bytein(adr + off));
73 }
74
75 static inline void
76 writereg(unsigned int adr, u_char off, u_char data)
77 {
78 byteout(adr + off, data);
79 }
80
81
82 static inline void
83 read_fifo(unsigned int adr, u_char * data, int size)
84 {
85 insb(adr + 0x1e, data, size);
86 }
87
88 static void
89 write_fifo(unsigned int adr, u_char * data, int size)
90 {
91 outsb(adr + 0x1e, data, size);
92 }
93
94 static inline void
95 waitforCEC(int adr)
96 {
97 int to = 50;
98
99 while ((readreg(adr, HSCX_STAR) & 0x04) && to) {
100 udelay(1);
101 to--;
102 }
103 if (!to)
104 printk(KERN_WARNING "Teles3: waitforCEC timeout\n");
105 }
106
107
108 static inline void
109 waitforXFW(int adr)
110 {
111 int to = 50;
112
113 while ((!(readreg(adr, HSCX_STAR) & 0x44) == 0x40) && to) {
114 udelay(1);
115 to--;
116 }
117 if (!to)
118 printk(KERN_WARNING "Teles3: waitforXFW timeout\n");
119 }
120 static inline void
121 writehscxCMDR(int adr, u_char data)
122 {
123 long flags;
124
125 save_flags(flags);
126 cli();
127 waitforCEC(adr);
128 writereg(adr, HSCX_CMDR, data);
129 restore_flags(flags);
130 }
131
132 /*
133 * fast interrupt here
134 */
135
136 static void
137 hscxreport(struct IsdnCardState *sp, int hscx)
138 {
139 printk(KERN_DEBUG "HSCX %d\n", hscx);
140 printk(KERN_DEBUG "ISTA %x\n", readreg(sp->hscx[hscx], HSCX_ISTA));
141 printk(KERN_DEBUG "STAR %x\n", readreg(sp->hscx[hscx], HSCX_STAR));
142 printk(KERN_DEBUG "EXIR %x\n", readreg(sp->hscx[hscx], HSCX_EXIR));
143 }
144
145 void
146 teles3_report(struct IsdnCardState *sp)
147 {
148 printk(KERN_DEBUG "ISAC\n");
149 printk(KERN_DEBUG "ISTA %x\n", readreg(sp->isac, ISAC_ISTA));
150 printk(KERN_DEBUG "STAR %x\n", readreg(sp->isac, ISAC_STAR));
151 printk(KERN_DEBUG "EXIR %x\n", readreg(sp->isac, ISAC_EXIR));
152 hscxreport(sp, 0);
153 hscxreport(sp, 1);
154 }
155
156 /*
157 * HSCX stuff goes here
158 */
159
160 static void
161 hscx_empty_fifo(struct HscxState *hsp, int count)
162 {
163 u_char *ptr;
164 struct IsdnCardState *sp = hsp->sp;
165 long flags;
166
167 if ((sp->debug & L1_DEB_HSCX) && !(sp->debug & L1_DEB_HSCX_FIFO))
168 debugl1(sp, "hscx_empty_fifo");
169
170 if (hsp->rcvidx + count > HSCX_BUFMAX) {
171 if (sp->debug & L1_DEB_WARN)
172 debugl1(sp, "hscx_empty_fifo: incoming packet too large");
173 writehscxCMDR(sp->hscx[hsp->hscx], 0x80);
174 hsp->rcvidx = 0;
175 return;
176 }
177 ptr = hsp->rcvbuf + hsp->rcvidx;
178 hsp->rcvidx += count;
179 save_flags(flags);
180 cli();
181 read_fifo(sp->hscx[hsp->hscx], ptr, count);
182 writehscxCMDR(sp->hscx[hsp->hscx], 0x80);
183 restore_flags(flags);
184 if (sp->debug & L1_DEB_HSCX_FIFO) {
185 char tmp[128];
186 char *t = tmp;
187
188 t += sprintf(t, "hscx_empty_fifo %c cnt %d",
189 hsp->hscx ? 'B' : 'A', count);
190 QuickHex(t, ptr, count);
191 debugl1(sp, tmp);
192 }
193 }
194
195 static void
196 hscx_fill_fifo(struct HscxState *hsp)
197 {
198 struct IsdnCardState *sp = hsp->sp;
199 int more, count;
200 u_char *ptr;
201 long flags;
202
203 if ((sp->debug & L1_DEB_HSCX) && !(sp->debug & L1_DEB_HSCX_FIFO))
204 debugl1(sp, "hscx_fill_fifo");
205
206 if (!hsp->tx_skb)
207 return;
208 if (hsp->tx_skb->len <= 0)
209 return;
210
211 more = (hsp->mode == 1) ? 1 : 0;
212 if (hsp->tx_skb->len > 32) {
213 more = !0;
214 count = 32;
215 } else
216 count = hsp->tx_skb->len;
217
218 waitforXFW(sp->hscx[hsp->hscx]);
219 save_flags(flags);
220 cli();
221 ptr = hsp->tx_skb->data;
222 skb_pull(hsp->tx_skb, count);
223 hsp->tx_cnt -= count;
224 hsp->count += count;
225 write_fifo(sp->hscx[hsp->hscx], ptr, count);
226 writehscxCMDR(sp->hscx[hsp->hscx], more ? 0x8 : 0xa);
227 restore_flags(flags);
228 if (sp->debug & L1_DEB_HSCX_FIFO) {
229 char tmp[128];
230 char *t = tmp;
231
232 t += sprintf(t, "hscx_fill_fifo %c cnt %d",
233 hsp->hscx ? 'B' : 'A', count);
234 QuickHex(t, ptr, count);
235 debugl1(sp, tmp);
236 }
237 }
238
239 static inline void
240 hscx_interrupt(struct IsdnCardState *sp, u_char val, u_char hscx)
241 {
242 u_char r;
243 struct HscxState *hsp = sp->hs + hscx;
244 struct sk_buff *skb;
245 int count;
246 char tmp[32];
247
248 if (!hsp->init)
249 return;
250
251 if (val & 0x80) { /* RME */
252
253 r = readreg(sp->hscx[hsp->hscx], HSCX_RSTA);
254 if ((r & 0xf0) != 0xa0) {
255 if (!r & 0x80)
256 if (sp->debug & L1_DEB_WARN)
257 debugl1(sp, "HSCX invalid frame");
258 if ((r & 0x40) && hsp->mode)
259 if (sp->debug & L1_DEB_WARN) {
260 sprintf(tmp, "HSCX RDO mode=%d",
261 hsp->mode);
262 debugl1(sp, tmp);
263 }
264 if (!r & 0x20)
265 if (sp->debug & L1_DEB_WARN)
266 debugl1(sp, "HSCX CRC error");
267 writehscxCMDR(sp->hscx[hsp->hscx], 0x80);
268 } else {
269 count = readreg(sp->hscx[hsp->hscx], HSCX_RBCL) & 0x1f;
270 if (count == 0)
271 count = 32;
272 hscx_empty_fifo(hsp, count);
273 if ((count = hsp->rcvidx - 1) > 0) {
274 if (!(skb = dev_alloc_skb(count)))
275 printk(KERN_WARNING "AVM: receive out of memory\n");
276 else {
277 memcpy(skb_put(skb, count), hsp->rcvbuf, count);
278 skb_queue_tail(&hsp->rqueue, skb);
279 }
280 }
281 }
282 hsp->rcvidx = 0;
283 hscx_sched_event(hsp, HSCX_RCVBUFREADY);
284 }
285 if (val & 0x40) { /* RPF */
286 hscx_empty_fifo(hsp, 32);
287 if (hsp->mode == 1) {
288 /* receive audio data */
289 if (!(skb = dev_alloc_skb(32)))
290 printk(KERN_WARNING "AVM: receive out of memory\n");
291 else {
292 memcpy(skb_put(skb, 32), hsp->rcvbuf, 32);
293 skb_queue_tail(&hsp->rqueue, skb);
294 }
295 hsp->rcvidx = 0;
296 hscx_sched_event(hsp, HSCX_RCVBUFREADY);
297 }
298 }
299 if (val & 0x10) { /* XPR */
300 if (hsp->tx_skb)
301 if (hsp->tx_skb->len) {
302 hscx_fill_fifo(hsp);
303 return;
304 } else {
305 SET_SKB_FREE(hsp->tx_skb);
306 dev_kfree_skb(hsp->tx_skb, FREE_WRITE);
307 hsp->count = 0;
308 if (hsp->st->l4.l1writewakeup)
309 hsp->st->l4.l1writewakeup(hsp->st);
310 hsp->tx_skb = NULL;
311 }
312 if ((hsp->tx_skb = skb_dequeue(&hsp->squeue))) {
313 hsp->count = 0;
314 hscx_fill_fifo(hsp);
315 } else
316 hscx_sched_event(hsp, HSCX_XMTBUFREADY);
317 }
318 }
319
320 /*
321 * ISAC stuff goes here
322 */
323
324 static void
325 isac_empty_fifo(struct IsdnCardState *sp, int count)
326 {
327 u_char *ptr;
328 long flags;
329
330 if ((sp->debug & L1_DEB_ISAC) && !(sp->debug & L1_DEB_ISAC_FIFO))
331 if (sp->debug & L1_DEB_ISAC)
332 debugl1(sp, "isac_empty_fifo");
333
334 if ((sp->rcvidx + count) >= MAX_DFRAME_LEN) {
335 if (sp->debug & L1_DEB_WARN) {
336 char tmp[40];
337 sprintf(tmp, "isac_empty_fifo overrun %d",
338 sp->rcvidx + count);
339 debugl1(sp, tmp);
340 }
341 writereg(sp->isac, ISAC_CMDR, 0x80);
342 sp->rcvidx = 0;
343 return;
344 }
345 ptr = sp->rcvbuf + sp->rcvidx;
346 sp->rcvidx += count;
347 save_flags(flags);
348 cli();
349 read_fifo(sp->isac, ptr, count);
350 writereg(sp->isac, ISAC_CMDR, 0x80);
351 restore_flags(flags);
352 if (sp->debug & L1_DEB_ISAC_FIFO) {
353 char tmp[128];
354 char *t = tmp;
355
356 t += sprintf(t, "isac_empty_fifo cnt %d", count);
357 QuickHex(t, ptr, count);
358 debugl1(sp, tmp);
359 }
360 }
361
362 static void
363 isac_fill_fifo(struct IsdnCardState *sp)
364 {
365 int count, more;
366 u_char *ptr;
367 long flags;
368
369 if ((sp->debug & L1_DEB_ISAC) && !(sp->debug & L1_DEB_ISAC_FIFO))
370 debugl1(sp, "isac_fill_fifo");
371
372 if (!sp->tx_skb)
373 return;
374
375 count = sp->tx_skb->len;
376 if (count <= 0)
377 return;
378
379 more = 0;
380 if (count > 32) {
381 more = !0;
382 count = 32;
383 }
384 save_flags(flags);
385 cli();
386 ptr = sp->tx_skb->data;
387 skb_pull(sp->tx_skb, count);
388 sp->tx_cnt += count;
389 write_fifo(sp->isac, ptr, count);
390 writereg(sp->isac, ISAC_CMDR, more ? 0x8 : 0xa);
391 restore_flags(flags);
392 if (sp->debug & L1_DEB_ISAC_FIFO) {
393 char tmp[128];
394 char *t = tmp;
395
396 t += sprintf(t, "isac_fill_fifo cnt %d", count);
397 QuickHex(t, ptr, count);
398 debugl1(sp, tmp);
399 }
400 }
401
402 static void
403 ph_command(struct IsdnCardState *sp, unsigned int command)
404 {
405 if (sp->debug & L1_DEB_ISAC) {
406 char tmp[32];
407 sprintf(tmp, "ph_command %d", command);
408 debugl1(sp, tmp);
409 }
410 writereg(sp->isac, ISAC_CIX0, (command << 2) | 3);
411 }
412
413
414 static inline void
415 isac_interrupt(struct IsdnCardState *sp, u_char val)
416 {
417 u_char exval;
418 struct sk_buff *skb;
419 unsigned int count;
420 char tmp[32];
421
422 if (sp->debug & L1_DEB_ISAC) {
423 sprintf(tmp, "ISAC interrupt %x", val);
424 debugl1(sp, tmp);
425 }
426 if (val & 0x80) { /* RME */
427 exval = readreg(sp->isac, ISAC_RSTA);
428 if ((exval & 0x70) != 0x20) {
429 if (exval & 0x40)
430 if (sp->debug & L1_DEB_WARN)
431 debugl1(sp, "ISAC RDO");
432 if (!exval & 0x20)
433 if (sp->debug & L1_DEB_WARN)
434 debugl1(sp, "ISAC CRC error");
435 writereg(sp->isac, ISAC_CMDR, 0x80);
436 } else {
437 count = readreg(sp->isac, ISAC_RBCL) & 0x1f;
438 if (count == 0)
439 count = 32;
440 isac_empty_fifo(sp, count);
441 if ((count = sp->rcvidx) > 0) {
442 if (!(skb = alloc_skb(count, GFP_ATOMIC)))
443 printk(KERN_WARNING "AVM: D receive out of memory\n");
444 else {
445 memcpy(skb_put(skb, count), sp->rcvbuf, count);
446 skb_queue_tail(&sp->rq, skb);
447 }
448 }
449 }
450 sp->rcvidx = 0;
451 isac_sched_event(sp, ISAC_RCVBUFREADY);
452 }
453 if (val & 0x40) { /* RPF */
454 isac_empty_fifo(sp, 32);
455 }
456 if (val & 0x20) { /* RSC */
457 /* never */
458 if (sp->debug & L1_DEB_WARN)
459 debugl1(sp, "ISAC RSC interrupt");
460 }
461 if (val & 0x10) { /* XPR */
462 if (sp->tx_skb)
463 if (sp->tx_skb->len) {
464 isac_fill_fifo(sp);
465 goto afterXPR;
466 } else {
467 SET_SKB_FREE(sp->tx_skb);
468 dev_kfree_skb(sp->tx_skb, FREE_WRITE);
469 sp->tx_cnt = 0;
470 sp->tx_skb = NULL;
471 }
472 if ((sp->tx_skb = skb_dequeue(&sp->sq))) {
473 sp->tx_cnt = 0;
474 isac_fill_fifo(sp);
475 } else
476 isac_sched_event(sp, ISAC_XMTBUFREADY);
477 }
478 afterXPR:
479 if (val & 0x04) { /* CISQ */
480 sp->ph_state = (readreg(sp->isac, ISAC_CIX0) >> 2)
481 & 0xf;
482 if (sp->debug & L1_DEB_ISAC) {
483 sprintf(tmp, "l1state %d", sp->ph_state);
484 debugl1(sp, tmp);
485 }
486 isac_new_ph(sp);
487 }
488 if (val & 0x02) { /* SIN */
489 /* never */
490 if (sp->debug & L1_DEB_WARN)
491 debugl1(sp, "ISAC SIN interrupt");
492 }
493 if (val & 0x01) { /* EXI */
494 exval = readreg(sp->isac, ISAC_EXIR);
495 if (sp->debug & L1_DEB_WARN) {
496 sprintf(tmp, "ISAC EXIR %02x", exval);
497 debugl1(sp, tmp);
498 }
499 }
500 }
501
502 static inline void
503 hscx_int_main(struct IsdnCardState *sp, u_char val)
504 {
505
506 u_char exval;
507 struct HscxState *hsp;
508 char tmp[32];
509
510
511 if (val & 0x01) {
512 hsp = sp->hs + 1;
513 exval = readreg(sp->hscx[1], HSCX_EXIR);
514 if (exval == 0x40) {
515 if (hsp->mode == 1)
516 hscx_fill_fifo(hsp);
517 else {
518 /* Here we lost an TX interrupt, so
519 * restart transmitting the whole frame.
520 */
521 if (hsp->tx_skb) {
522 skb_push(hsp->tx_skb, hsp->count);
523 hsp->tx_cnt += hsp->count;
524 hsp->count = 0;
525 }
526 writehscxCMDR(sp->hscx[hsp->hscx], 0x01);
527 if (sp->debug & L1_DEB_WARN) {
528 sprintf(tmp, "HSCX B EXIR %x Lost TX", exval);
529 debugl1(sp, tmp);
530 }
531 }
532 } else if (sp->debug & L1_DEB_HSCX) {
533 sprintf(tmp, "HSCX B EXIR %x", exval);
534 debugl1(sp, tmp);
535 }
536 }
537 if (val & 0xf8) {
538 if (sp->debug & L1_DEB_HSCX) {
539 sprintf(tmp, "HSCX B interrupt %x", val);
540 debugl1(sp, tmp);
541 }
542 hscx_interrupt(sp, val, 1);
543 }
544 if (val & 0x02) {
545 hsp = sp->hs;
546 exval = readreg(sp->hscx[0], HSCX_EXIR);
547 if (exval == 0x40) {
548 if (hsp->mode == 1)
549 hscx_fill_fifo(hsp);
550 else {
551 /* Here we lost an TX interrupt, so
552 * restart transmitting the whole frame.
553 */
554 if (hsp->tx_skb) {
555 skb_push(hsp->tx_skb, hsp->count);
556 hsp->tx_cnt += hsp->count;
557 hsp->count = 0;
558 }
559 writehscxCMDR(sp->hscx[hsp->hscx], 0x01);
560 if (sp->debug & L1_DEB_WARN) {
561 sprintf(tmp, "HSCX A EXIR %x Lost TX", exval);
562 debugl1(sp, tmp);
563 }
564 }
565 } else if (sp->debug & L1_DEB_HSCX) {
566 sprintf(tmp, "HSCX A EXIR %x", exval);
567 debugl1(sp, tmp);
568 }
569 }
570 if (val & 0x04) {
571 exval = readreg(sp->hscx[0], HSCX_ISTA);
572 if (sp->debug & L1_DEB_HSCX) {
573 sprintf(tmp, "HSCX A interrupt %x", exval);
574 debugl1(sp, tmp);
575 }
576 hscx_interrupt(sp, exval, 0);
577 }
578 }
579
580 static void
581 teles3_interrupt(int intno, void *dev_id, struct pt_regs *regs)
582 {
583 #define MAXCOUNT 20
584 struct IsdnCardState *sp;
585 u_char val, stat = 0;
586 int count = 0;
587
588 sp = (struct IsdnCardState *) dev_id;
589
590 if (!sp) {
591 printk(KERN_WARNING "Teles: Spurious interrupt!\n");
592 return;
593 }
594 val = readreg(sp->hscx[1], HSCX_ISTA);
595 Start_HSCX:
596 if (val) {
597 hscx_int_main(sp, val);
598 stat |= 1;
599 }
600 val = readreg(sp->isac, ISAC_ISTA);
601 Start_ISAC:
602 if (val) {
603 isac_interrupt(sp, val);
604 stat |= 2;
605 }
606 count++;
607 val = readreg(sp->hscx[1], HSCX_ISTA);
608 if (val && count < MAXCOUNT) {
609 if (sp->debug & L1_DEB_HSCX)
610 debugl1(sp, "HSCX IntStat after IntRoutine");
611 goto Start_HSCX;
612 }
613 val = readreg(sp->isac, ISAC_ISTA);
614 if (val && count < MAXCOUNT) {
615 if (sp->debug & L1_DEB_ISAC)
616 debugl1(sp, "ISAC IntStat after IntRoutine");
617 goto Start_ISAC;
618 }
619 if (count >= MAXCOUNT)
620 printk(KERN_WARNING "Teles3: more than %d loops in teles3_interrupt\n", count);
621 if (stat & 1) {
622 writereg(sp->hscx[0], HSCX_MASK, 0xFF);
623 writereg(sp->hscx[1], HSCX_MASK, 0xFF);
624 writereg(sp->hscx[0], HSCX_MASK, 0x0);
625 writereg(sp->hscx[1], HSCX_MASK, 0x0);
626 }
627 if (stat & 2) {
628 writereg(sp->isac, ISAC_MASK, 0xFF);
629 writereg(sp->isac, ISAC_MASK, 0x0);
630 }
631 }
632
633
634 static void
635 initisac(struct IsdnCardState *sp)
636 {
637 unsigned int adr = sp->isac;
638
639 /* 16.3 IOM 2 Mode */
640 writereg(adr, ISAC_MASK, 0xff);
641 writereg(adr, ISAC_ADF2, 0x80);
642 writereg(adr, ISAC_SQXR, 0x2f);
643 writereg(adr, ISAC_SPCR, 0x0);
644 writereg(adr, ISAC_ADF1, 0x2);
645 writereg(adr, ISAC_STCR, 0x70);
646 writereg(adr, ISAC_MODE, 0xc9);
647 writereg(adr, ISAC_TIMR, 0x0);
648 writereg(adr, ISAC_ADF1, 0x0);
649 writereg(adr, ISAC_CMDR, 0x41);
650 writereg(adr, ISAC_CIX0, (1 << 2) | 3);
651 writereg(adr, ISAC_MASK, 0xff);
652 writereg(adr, ISAC_MASK, 0x0);
653 }
654
655 static void
656 modehscx(struct HscxState *hs, int mode, int ichan)
657 {
658 struct IsdnCardState *sp = hs->sp;
659 int hscx = hs->hscx;
660
661 if (sp->debug & L1_DEB_HSCX) {
662 char tmp[40];
663 sprintf(tmp, "hscx %c mode %d ichan %d",
664 'A' + hscx, mode, ichan);
665 debugl1(sp, tmp);
666 }
667 hs->mode = mode;
668 writereg(sp->hscx[hscx], HSCX_CCR1, 0x85);
669 writereg(sp->hscx[hscx], HSCX_XAD1, 0xFF);
670 writereg(sp->hscx[hscx], HSCX_XAD2, 0xFF);
671 writereg(sp->hscx[hscx], HSCX_RAH2, 0xFF);
672 writereg(sp->hscx[hscx], HSCX_XBCH, 0x0);
673 writereg(sp->hscx[hscx], HSCX_RLCR, 0x0);
674
675 switch (mode) {
676 case (0):
677 writereg(sp->hscx[hscx], HSCX_CCR2, 0x30);
678 writereg(sp->hscx[hscx], HSCX_TSAX, 0xff);
679 writereg(sp->hscx[hscx], HSCX_TSAR, 0xff);
680 writereg(sp->hscx[hscx], HSCX_XCCR, 7);
681 writereg(sp->hscx[hscx], HSCX_RCCR, 7);
682 writereg(sp->hscx[hscx], HSCX_MODE, 0x84);
683 break;
684 case (1):
685 if (ichan == 0) {
686 writereg(sp->hscx[hscx], HSCX_CCR2, 0x30);
687 writereg(sp->hscx[hscx], HSCX_TSAX, 0x2f);
688 writereg(sp->hscx[hscx], HSCX_TSAR, 0x2f);
689 writereg(sp->hscx[hscx], HSCX_XCCR, 7);
690 writereg(sp->hscx[hscx], HSCX_RCCR, 7);
691 } else {
692 writereg(sp->hscx[hscx], HSCX_CCR2, 0x30);
693 writereg(sp->hscx[hscx], HSCX_TSAX, 0x3);
694 writereg(sp->hscx[hscx], HSCX_TSAR, 0x3);
695 writereg(sp->hscx[hscx], HSCX_XCCR, 7);
696 writereg(sp->hscx[hscx], HSCX_RCCR, 7);
697 }
698 writereg(sp->hscx[hscx], HSCX_MODE, 0xe4);
699 writereg(sp->hscx[hscx], HSCX_CMDR, 0x41);
700 break;
701 case (2):
702 if (ichan == 0) {
703 writereg(sp->hscx[hscx], HSCX_CCR2, 0x30);
704 writereg(sp->hscx[hscx], HSCX_TSAX, 0x2f);
705 writereg(sp->hscx[hscx], HSCX_TSAR, 0x2f);
706 writereg(sp->hscx[hscx], HSCX_XCCR, 7);
707 writereg(sp->hscx[hscx], HSCX_RCCR, 7);
708 } else {
709 writereg(sp->hscx[hscx], HSCX_CCR2, 0x30);
710 writereg(sp->hscx[hscx], HSCX_TSAX, 0x3);
711 writereg(sp->hscx[hscx], HSCX_TSAR, 0x3);
712 writereg(sp->hscx[hscx], HSCX_XCCR, 7);
713 writereg(sp->hscx[hscx], HSCX_RCCR, 7);
714 }
715 writereg(sp->hscx[hscx], HSCX_MODE, 0x8c);
716 writereg(sp->hscx[hscx], HSCX_CMDR, 0x41);
717 break;
718 }
719 writereg(sp->hscx[hscx], HSCX_ISTA, 0x00);
720 }
721
722 inline static void
723 release_ioregs(struct IsdnCard *card, int mask)
724 {
725 if (mask & 1)
726 release_region(card->sp->isac, 32);
727 if (mask & 2)
728 release_region(card->sp->hscx[0], 32);
729 if (mask & 4)
730 release_region(card->sp->hscx[1], 32);
731 }
732
733 void
734 release_io_teles3(struct IsdnCard *card)
735 {
736 if (card->sp->typ == ISDN_CTYPE_TELESPCMCIA)
737 release_region(card->sp->hscx[0], 97);
738 else {
739 if (card->sp->cfg_reg)
740 release_region(card->sp->cfg_reg, 8);
741 release_ioregs(card, 0x7);
742 }
743 }
744
745 static void
746 clear_pending_ints(struct IsdnCardState *sp)
747 {
748 int val;
749 char tmp[64];
750
751 val = readreg(sp->hscx[1], HSCX_ISTA);
752 sprintf(tmp, "HSCX B ISTA %x", val);
753 debugl1(sp, tmp);
754 if (val & 0x01) {
755 val = readreg(sp->hscx[1], HSCX_EXIR);
756 sprintf(tmp, "HSCX B EXIR %x", val);
757 debugl1(sp, tmp);
758 } else if (val & 0x02) {
759 val = readreg(sp->hscx[0], HSCX_EXIR);
760 sprintf(tmp, "HSCX A EXIR %x", val);
761 debugl1(sp, tmp);
762 }
763 val = readreg(sp->hscx[0], HSCX_ISTA);
764 sprintf(tmp, "HSCX A ISTA %x", val);
765 debugl1(sp, tmp);
766 val = readreg(sp->hscx[1], HSCX_STAR);
767 sprintf(tmp, "HSCX B STAR %x", val);
768 debugl1(sp, tmp);
769 val = readreg(sp->hscx[0], HSCX_STAR);
770 sprintf(tmp, "HSCX A STAR %x", val);
771 debugl1(sp, tmp);
772 val = readreg(sp->isac, ISAC_STAR);
773 sprintf(tmp, "ISAC STAR %x", val);
774 debugl1(sp, tmp);
775 val = readreg(sp->isac, ISAC_MODE);
776 sprintf(tmp, "ISAC MODE %x", val);
777 debugl1(sp, tmp);
778 val = readreg(sp->isac, ISAC_ADF2);
779 sprintf(tmp, "ISAC ADF2 %x", val);
780 debugl1(sp, tmp);
781 val = readreg(sp->isac, ISAC_ISTA);
782 sprintf(tmp, "ISAC ISTA %x", val);
783 debugl1(sp, tmp);
784 if (val & 0x01) {
785 val = readreg(sp->isac, ISAC_EXIR);
786 sprintf(tmp, "ISAC EXIR %x", val);
787 debugl1(sp, tmp);
788 } else if (val & 0x04) {
789 val = readreg(sp->isac, ISAC_CIR0);
790 sprintf(tmp, "ISAC CIR0 %x", val);
791 debugl1(sp, tmp);
792 }
793 writereg(sp->isac, ISAC_MASK, 0);
794 writereg(sp->isac, ISAC_CMDR, 0x41);
795 }
796
797 int
798 initteles3(struct IsdnCardState *sp)
799 {
800 int ret;
801 int loop = 0;
802 char tmp[40];
803
804 sp->counter = kstat_irqs(sp->irq);
805 sprintf(tmp, "IRQ %d count %d", sp->irq, sp->counter);
806 debugl1(sp, tmp);
807 clear_pending_ints(sp);
808 ret = get_irq(sp->cardnr, &teles3_interrupt);
809 if (ret) {
810 initisac(sp);
811 sp->modehscx(sp->hs, 0, 0);
812 writereg(sp->hscx[sp->hs->hscx], HSCX_CMDR, 0x01);
813 sp->modehscx(sp->hs + 1, 0, 0);
814 writereg(sp->hscx[(sp->hs + 1)->hscx], HSCX_CMDR, 0x01);
815 while (loop++ < 10) {
816 /* At least 1-3 irqs must happen
817 * (one from HSCX A, one from HSCX B, 3rd from ISAC)
818 */
819 if (kstat_irqs(sp->irq) > sp->counter)
820 break;
821 current->state = TASK_INTERRUPTIBLE;
822 current->timeout = jiffies + 1;
823 schedule();
824 }
825 sprintf(tmp, "IRQ %d count %d loop %d", sp->irq,
826 kstat_irqs(sp->irq), loop);
827 debugl1(sp, tmp);
828 if (kstat_irqs(sp->irq) <= sp->counter) {
829 printk(KERN_WARNING
830 "Teles3: IRQ(%d) getting no interrupts during init\n",
831 sp->irq);
832 free_irq(sp->irq, sp);
833 return (0);
834 }
835 }
836 return (ret);
837 }
838
839 int
840 setup_teles3(struct IsdnCard *card)
841 {
842 u_char cfval = 0, val, verA, verB;
843 struct IsdnCardState *sp = card->sp;
844 long flags;
845 char tmp[64];
846
847 strcpy(tmp, teles3_revision);
848 printk(KERN_NOTICE "HiSax: Teles IO driver Rev. %s\n", HiSax_getrev(tmp));
849 if ((sp->typ != ISDN_CTYPE_16_3) && (sp->typ != ISDN_CTYPE_PNP)
850 && (sp->typ != ISDN_CTYPE_TELESPCMCIA))
851 return (0);
852
853 if (sp->typ == ISDN_CTYPE_16_3) {
854 sp->cfg_reg = card->para[1];
855 switch (sp->cfg_reg) {
856 case 0x180:
857 case 0x280:
858 case 0x380:
859 sp->cfg_reg |= 0xc00;
860 break;
861 }
862 sp->isac = sp->cfg_reg - 0x400;
863 sp->hscx[0] = sp->cfg_reg - 0xc00;
864 sp->hscx[1] = sp->cfg_reg - 0x800;
865 } else if (sp->typ == ISDN_CTYPE_TELESPCMCIA) {
866 sp->cfg_reg = 0;
867 sp->hscx[0] = card->para[1];
868 sp->hscx[1] = card->para[1] + 0x20;
869 sp->isac = card->para[1] + 0x40;
870 } else { /* PNP */
871 sp->cfg_reg = 0;
872 sp->isac = card->para[1];
873 sp->hscx[0] = card->para[2];
874 sp->hscx[1] = card->para[2] + 0x20;
875 }
876 sp->irq = card->para[0];
877 if (sp->typ == ISDN_CTYPE_TELESPCMCIA) {
878 if (check_region((sp->hscx[0]), 97)) {
879 printk(KERN_WARNING
880 "HiSax: %s ports %x-%x already in use\n",
881 CardType[sp->typ],
882 sp->hscx[0],
883 sp->hscx[0] + 96);
884 return (0);
885 } else
886 request_region(sp->hscx[0], 97, "HiSax Teles PCMCIA");
887 } else {
888 if (sp->cfg_reg) {
889 if (check_region((sp->cfg_reg), 8)) {
890 printk(KERN_WARNING
891 "HiSax: %s config port %x-%x already in use\n",
892 CardType[card->typ],
893 sp->cfg_reg,
894 sp->cfg_reg + 8);
895 return (0);
896 } else {
897 request_region(sp->cfg_reg, 8, "teles3 cfg");
898 }
899 }
900 if (check_region((sp->isac), 32)) {
901 printk(KERN_WARNING
902 "HiSax: %s isac ports %x-%x already in use\n",
903 CardType[sp->typ],
904 sp->isac,
905 sp->isac + 32);
906 if (sp->cfg_reg) {
907 release_region(sp->cfg_reg, 8);
908 }
909 return (0);
910 } else {
911 request_region(sp->isac, 32, "HiSax isac");
912 }
913 if (check_region((sp->hscx[0]), 32)) {
914 printk(KERN_WARNING
915 "HiSax: %s hscx A ports %x-%x already in use\n",
916 CardType[sp->typ],
917 sp->hscx[0],
918 sp->hscx[0] + 32);
919 if (sp->cfg_reg) {
920 release_region(sp->cfg_reg, 8);
921 }
922 release_ioregs(card, 1);
923 return (0);
924 } else {
925 request_region(sp->hscx[0], 32, "HiSax hscx A");
926 }
927 if (check_region((sp->hscx[1]), 32)) {
928 printk(KERN_WARNING
929 "HiSax: %s hscx B ports %x-%x already in use\n",
930 CardType[sp->typ],
931 sp->hscx[1],
932 sp->hscx[1] + 32);
933 if (sp->cfg_reg) {
934 release_region(sp->cfg_reg, 8);
935 }
936 release_ioregs(card, 3);
937 return (0);
938 } else {
939 request_region(sp->hscx[1], 32, "HiSax hscx B");
940 }
941 switch (sp->irq) {
942 case 2:
943 cfval = 0x00;
944 break;
945 case 3:
946 cfval = 0x02;
947 break;
948 case 4:
949 cfval = 0x04;
950 break;
951 case 5:
952 cfval = 0x06;
953 break;
954 case 10:
955 cfval = 0x08;
956 break;
957 case 11:
958 cfval = 0x0A;
959 break;
960 case 12:
961 cfval = 0x0C;
962 break;
963 case 15:
964 cfval = 0x0E;
965 break;
966 default:
967 cfval = 0x00;
968 break;
969 }
970 }
971 if (sp->cfg_reg) {
972 if ((val = bytein(sp->cfg_reg + 0)) != 0x51) {
973 printk(KERN_WARNING "Teles: 16.3 Byte at %x is %x\n",
974 sp->cfg_reg + 0, val);
975 release_io_teles3(card);
976 return (0);
977 }
978 if ((val = bytein(sp->cfg_reg + 1)) != 0x93) {
979 printk(KERN_WARNING "Teles: 16.3 Byte at %x is %x\n",
980 sp->cfg_reg + 1, val);
981 release_io_teles3(card);
982 return (0);
983 }
984 val = bytein(sp->cfg_reg + 2); /* 0x1e=without AB
985 * 0x1f=with AB
986 * 0x1c 16.3 ???
987 * 0x46 16.3 with AB + Video (Teles-Vision)
988 */
989 if (val != 0x46 && val != 0x1c && val != 0x1e && val != 0x1f) {
990 printk(KERN_WARNING "Teles: 16.3 Byte at %x is %x\n",
991 sp->cfg_reg + 2, val);
992 release_io_teles3(card);
993 return (0);
994 }
995 save_flags(flags);
996 byteout(sp->cfg_reg + 4, cfval);
997 sti();
998 HZDELAY(HZ / 10 + 1);
999 byteout(sp->cfg_reg + 4, cfval | 1);
1000 HZDELAY(HZ / 10 + 1);
1001 restore_flags(flags);
1002 } else {
1003 /* Reset off for 16.3 PnP , thanks to Georg Acher */
1004 save_flags(flags);
1005 byteout(sp->isac + 0x1c, 1);
1006 HZDELAY(2);
1007 restore_flags(flags);
1008 }
1009 printk(KERN_NOTICE
1010 "HiSax: %s config irq:%d isac:%x cfg:%x\n",
1011 CardType[sp->typ], sp->irq,
1012 sp->isac, sp->cfg_reg);
1013 printk(KERN_NOTICE
1014 "HiSax: hscx A:%x hscx B:%x\n",
1015 sp->hscx[0], sp->hscx[1]);
1016 verA = readreg(sp->hscx[0], HSCX_VSTR) & 0xf;
1017 verB = readreg(sp->hscx[1], HSCX_VSTR) & 0xf;
1018 printk(KERN_INFO "Teles3: HSCX version A: %s B: %s\n",
1019 HscxVersion(verA), HscxVersion(verB));
1020 val = readreg(sp->isac, ISAC_RBCH);
1021 printk(KERN_INFO "Teles3: ISAC %s\n",
1022 ISACVersion(val));
1023 if ((verA == 0) | (verA == 0xf) | (verB == 0) | (verB == 0xf)) {
1024 printk(KERN_WARNING
1025 "Teles3: wrong HSCX versions check IO address\n");
1026 release_io_teles3(card);
1027 return (0);
1028 }
1029 sp->modehscx = &modehscx;
1030 sp->ph_command = &ph_command;
1031 sp->hscx_fill_fifo = &hscx_fill_fifo;
1032 sp->isac_fill_fifo = &isac_fill_fifo;
1033 return (1);
1034 }
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