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Import 2.1.81
[davej-history.git] / drivers / isdn / hisax / teles0.c
blobe14c01c09fb80adfeec028c66116f7575cb5ba3f
1 /* $Id: teles0.c,v 1.8 1997/04/13 19:54:04 keil Exp $
2
3 * teles0.c low level stuff for Teles Memory IO isdn cards
4 * based on the teles driver from Jan den Ouden
5 *
6 * Author Karsten Keil (keil@temic-ech.spacenet.de)
7 *
8 * Thanks to Jan den Ouden
9 * Fritz Elfert
10 * Beat Doebeli
11 *
12 * $Log: teles0.c,v $
13 * Revision 1.8 1997/04/13 19:54:04 keil
14 * Change in IRQ check delay for SMP
15 *
16 * Revision 1.7 1997/04/06 22:54:04 keil
17 * Using SKB's
18 *
19 * Revision 1.6 1997/01/27 15:52:18 keil
20 * SMP proof,cosmetics
21 *
22 * Revision 1.5 1997/01/21 22:25:59 keil
23 * cleanups
24 *
25 * Revision 1.4 1996/11/05 19:41:27 keil
26 * more changes for 2.1
27 *
28 * Revision 1.3 1996/10/30 10:22:58 keil
29 * Changes for 2.1 kernels
30 *
31 * Revision 1.2 1996/10/27 22:08:34 keil
32 * cosmetic changes
33 *
34 * Revision 1.1 1996/10/13 20:04:58 keil
35 * Initial revision
36 *
37 *
38 *
39 */
40 #define __NO_VERSION__
41 #include "siemens.h"
42 #include "hisax.h"
43 #include "teles0.h"
44 #include "isdnl1.h"
45 #include <linux/kernel_stat.h>
46
47 extern const char *CardType[];
48
49 const char *teles0_revision = "$Revision: 1.8 $";
50
51 #define byteout(addr,val) outb_p(val,addr)
52 #define bytein(addr) inb_p(addr)
53
54 static inline u_char
55 readisac(unsigned int adr, u_char off)
56 {
57 return readb(adr + 0x120 + ((off & 1) ? 0x1ff : 0) + off);
58 }
59
60 static inline void
61 writeisac(unsigned int adr, u_char off, u_char data)
62 {
63 writeb(data, adr + 0x120 + ((off & 1) ? 0x1ff : 0) + off);
64 }
65
66
67 static inline u_char
68 readhscx(unsigned int adr, int hscx, u_char off)
69 {
70 return readb(adr + (hscx ? 0x1e0 : 0x1a0) +
71 ((off & 1) ? 0x1ff : 0) + off);
72 }
73
74 static inline void
75 writehscx(unsigned int adr, int hscx, u_char off, u_char data)
76 {
77 writeb(data, adr + (hscx ? 0x1e0 : 0x1a0) +
78 ((off & 1) ? 0x1ff : 0) + off);
79 }
80
81 static inline void
82 read_fifo_isac(unsigned int adr, u_char * data, int size)
83 {
84 register int i;
85 register u_char *ad = (u_char *) (adr + 0x100);
86 for (i = 0; i < size; i++)
87 data[i] = readb(ad);
88 }
89
90 static void
91 write_fifo_isac(unsigned int adr, u_char * data, int size)
92 {
93 register int i;
94 register u_char *ad = (u_char *) (adr + 0x100);
95 for (i = 0; i < size; i++)
96 writeb(data[i], ad);
97 }
98
99 static inline void
100 read_fifo_hscx(unsigned int adr, int hscx, u_char * data, int size)
101 {
102 register int i;
103 register u_char *ad = (u_char *) (adr + (hscx ? 0x1c0 : 0x180));
104 for (i = 0; i < size; i++)
105 data[i] = readb(ad);
106 }
107
108 static inline void
109 write_fifo_hscx(unsigned int adr, int hscx, u_char * data, int size)
110 {
111 int i;
112 register u_char *ad = (u_char *) (adr + (hscx ? 0x1c0 : 0x180));
113 for (i = 0; i < size; i++)
114 writeb(data[i], ad);
115 }
116 static inline void
117 waitforCEC(int adr, int hscx)
118 {
119 int to = 50;
120
121 while ((readhscx(adr, hscx, HSCX_STAR) & 0x04) && to) {
122 udelay(1);
123 to--;
124 }
125 if (!to)
126 printk(KERN_WARNING "Teles0: waitforCEC timeout\n");
127 }
128
129
130 static inline void
131 waitforXFW(int adr, int hscx)
132 {
133 int to = 50;
134
135 while ((!(readhscx(adr, hscx, HSCX_STAR) & 0x44) == 0x40) && to) {
136 udelay(1);
137 to--;
138 }
139 if (!to)
140 printk(KERN_WARNING "Teles0: waitforXFW timeout\n");
141 }
142
143 static inline void
144 writehscxCMDR(int adr, int hscx, u_char data)
145 {
146 long flags;
147
148 save_flags(flags);
149 cli();
150 waitforCEC(adr, hscx);
151 writehscx(adr, hscx, HSCX_CMDR, data);
152 restore_flags(flags);
153 }
154
155 /*
156 * fast interrupt here
157 */
158
159
160 static void
161 hscxreport(struct IsdnCardState *sp, int hscx)
162 {
163 printk(KERN_DEBUG "HSCX %d\n", hscx);
164 printk(KERN_DEBUG "ISTA %x\n", readhscx(sp->membase, hscx, HSCX_ISTA));
165 printk(KERN_DEBUG "STAR %x\n", readhscx(sp->membase, hscx, HSCX_STAR));
166 printk(KERN_DEBUG "EXIR %x\n", readhscx(sp->membase, hscx, HSCX_EXIR));
167 }
168
169 void
170 teles0_report(struct IsdnCardState *sp)
171 {
172 printk(KERN_DEBUG "ISAC\n");
173 printk(KERN_DEBUG "ISTA %x\n", readisac(sp->membase, ISAC_ISTA));
174 printk(KERN_DEBUG "STAR %x\n", readisac(sp->membase, ISAC_STAR));
175 printk(KERN_DEBUG "EXIR %x\n", readisac(sp->membase, ISAC_EXIR));
176 hscxreport(sp, 0);
177 hscxreport(sp, 1);
178 }
179
180 /*
181 * HSCX stuff goes here
182 */
183
184 static void
185 hscx_empty_fifo(struct HscxState *hsp, int count)
186 {
187 u_char *ptr;
188 struct IsdnCardState *sp = hsp->sp;
189 long flags;
190
191 if ((sp->debug & L1_DEB_HSCX) && !(sp->debug & L1_DEB_HSCX_FIFO))
192 debugl1(sp, "hscx_empty_fifo");
193
194 if (hsp->rcvidx + count > HSCX_BUFMAX) {
195 if (sp->debug & L1_DEB_WARN)
196 debugl1(sp, "hscx_empty_fifo: incoming packet too large");
197 writehscxCMDR(sp->membase, hsp->hscx, 0x80);
198 hsp->rcvidx = 0;
199 return;
200 }
201 ptr = hsp->rcvbuf + hsp->rcvidx;
202 hsp->rcvidx += count;
203 save_flags(flags);
204 cli();
205 read_fifo_hscx(sp->membase, hsp->hscx, ptr, count);
206 writehscxCMDR(sp->membase, hsp->hscx, 0x80);
207 restore_flags(flags);
208 if (sp->debug & L1_DEB_HSCX_FIFO) {
209 char tmp[128];
210 char *t = tmp;
211
212 t += sprintf(t, "hscx_empty_fifo %c cnt %d",
213 hsp->hscx ? 'B' : 'A', count);
214 QuickHex(t, ptr, count);
215 debugl1(sp, tmp);
216 }
217 }
218
219 static void
220 hscx_fill_fifo(struct HscxState *hsp)
221 {
222 struct IsdnCardState *sp = hsp->sp;
223 int more, count;
224 u_char *ptr;
225 long flags;
226
227 if ((sp->debug & L1_DEB_HSCX) && !(sp->debug & L1_DEB_HSCX_FIFO))
228 debugl1(sp, "hscx_fill_fifo");
229
230 if (!hsp->tx_skb)
231 return;
232 if (hsp->tx_skb->len <= 0)
233 return;
234
235 more = (hsp->mode == 1) ? 1 : 0;
236 if (hsp->tx_skb->len > 32) {
237 more = !0;
238 count = 32;
239 } else
240 count = hsp->tx_skb->len;
241
242 waitforXFW(sp->membase, hsp->hscx);
243 save_flags(flags);
244 cli();
245 ptr = hsp->tx_skb->data;
246 skb_pull(hsp->tx_skb, count);
247 hsp->tx_cnt -= count;
248 hsp->count += count;
249 write_fifo_hscx(sp->membase, hsp->hscx, ptr, count);
250 writehscxCMDR(sp->membase, hsp->hscx, more ? 0x8 : 0xa);
251 restore_flags(flags);
252 if (sp->debug & L1_DEB_HSCX_FIFO) {
253 char tmp[128];
254 char *t = tmp;
255
256 t += sprintf(t, "hscx_fill_fifo %c cnt %d",
257 hsp->hscx ? 'B' : 'A', count);
258 QuickHex(t, ptr, count);
259 debugl1(sp, tmp);
260 }
261 }
262
263 static inline void
264 hscx_interrupt(struct IsdnCardState *sp, u_char val, u_char hscx)
265 {
266 u_char r;
267 struct HscxState *hsp = sp->hs + hscx;
268 struct sk_buff *skb;
269 int count;
270 char tmp[32];
271
272 if (!hsp->init)
273 return;
274
275 if (val & 0x80) { /* RME */
276
277 r = readhscx(sp->membase, hsp->hscx, HSCX_RSTA);
278 if ((r & 0xf0) != 0xa0) {
279 if (!r & 0x80)
280 if (sp->debug & L1_DEB_WARN)
281 debugl1(sp, "HSCX invalid frame");
282 if ((r & 0x40) && hsp->mode)
283 if (sp->debug & L1_DEB_WARN) {
284 sprintf(tmp, "HSCX RDO mode=%d",
285 hsp->mode);
286 debugl1(sp, tmp);
287 }
288 if (!r & 0x20)
289 if (sp->debug & L1_DEB_WARN)
290 debugl1(sp, "HSCX CRC error");
291 writehscxCMDR(sp->membase, hsp->hscx, 0x80);
292 } else {
293 count = readhscx(sp->membase, hsp->hscx, HSCX_RBCL) & 0x1f;
294 if (count == 0)
295 count = 32;
296 hscx_empty_fifo(hsp, count);
297 if ((count = hsp->rcvidx - 1) > 0) {
298 if (!(skb = dev_alloc_skb(count)))
299 printk(KERN_WARNING "AVM: receive out of memory\n");
300 else {
301 memcpy(skb_put(skb, count), hsp->rcvbuf, count);
302 skb_queue_tail(&hsp->rqueue, skb);
303 }
304 }
305 }
306 hsp->rcvidx = 0;
307 hscx_sched_event(hsp, HSCX_RCVBUFREADY);
308 }
309 if (val & 0x40) { /* RPF */
310 hscx_empty_fifo(hsp, 32);
311 if (hsp->mode == 1) {
312 /* receive audio data */
313 if (!(skb = dev_alloc_skb(32)))
314 printk(KERN_WARNING "AVM: receive out of memory\n");
315 else {
316 memcpy(skb_put(skb, 32), hsp->rcvbuf, 32);
317 skb_queue_tail(&hsp->rqueue, skb);
318 }
319 hsp->rcvidx = 0;
320 hscx_sched_event(hsp, HSCX_RCVBUFREADY);
321 }
322 }
323 if (val & 0x10) { /* XPR */
324 if (hsp->tx_skb)
325 if (hsp->tx_skb->len) {
326 hscx_fill_fifo(hsp);
327 return;
328 } else {
329 SET_SKB_FREE(hsp->tx_skb);
330 dev_kfree_skb(hsp->tx_skb, FREE_WRITE);
331 hsp->count = 0;
332 if (hsp->st->l4.l1writewakeup)
333 hsp->st->l4.l1writewakeup(hsp->st);
334 hsp->tx_skb = NULL;
335 }
336 if ((hsp->tx_skb = skb_dequeue(&hsp->squeue))) {
337 hsp->count = 0;
338 hscx_fill_fifo(hsp);
339 } else
340 hscx_sched_event(hsp, HSCX_XMTBUFREADY);
341 }
342 }
343
344 /*
345 * ISAC stuff goes here
346 */
347
348 static void
349 isac_empty_fifo(struct IsdnCardState *sp, int count)
350 {
351 u_char *ptr;
352 long flags;
353
354 if ((sp->debug & L1_DEB_ISAC) && !(sp->debug & L1_DEB_ISAC_FIFO))
355 debugl1(sp, "isac_empty_fifo");
356
357 if ((sp->rcvidx + count) >= MAX_DFRAME_LEN) {
358 if (sp->debug & L1_DEB_WARN) {
359 char tmp[40];
360 sprintf(tmp, "isac_empty_fifo overrun %d",
361 sp->rcvidx + count);
362 debugl1(sp, tmp);
363 }
364 writeisac(sp->membase, ISAC_CMDR, 0x80);
365 sp->rcvidx = 0;
366 return;
367 }
368 ptr = sp->rcvbuf + sp->rcvidx;
369 sp->rcvidx += count;
370 save_flags(flags);
371 cli();
372 read_fifo_isac(sp->membase, ptr, count);
373 writeisac(sp->membase, ISAC_CMDR, 0x80);
374 restore_flags(flags);
375 if (sp->debug & L1_DEB_ISAC_FIFO) {
376 char tmp[128];
377 char *t = tmp;
378
379 t += sprintf(t, "isac_empty_fifo cnt %d", count);
380 QuickHex(t, ptr, count);
381 debugl1(sp, tmp);
382 }
383 }
384
385 static void
386 isac_fill_fifo(struct IsdnCardState *sp)
387 {
388 int count, more;
389 u_char *ptr;
390 long flags;
391
392 if ((sp->debug & L1_DEB_ISAC) && !(sp->debug & L1_DEB_ISAC_FIFO))
393 debugl1(sp, "isac_fill_fifo");
394
395 if (!sp->tx_skb)
396 return;
397
398 count = sp->tx_skb->len;
399 if (count <= 0)
400 return;
401
402 more = 0;
403 if (count > 32) {
404 more = !0;
405 count = 32;
406 }
407 save_flags(flags);
408 cli();
409 ptr = sp->tx_skb->data;
410 skb_pull(sp->tx_skb, count);
411 sp->tx_cnt += count;
412 write_fifo_isac(sp->membase, ptr, count);
413 writeisac(sp->membase, ISAC_CMDR, more ? 0x8 : 0xa);
414 restore_flags(flags);
415 if (sp->debug & L1_DEB_ISAC_FIFO) {
416 char tmp[128];
417 char *t = tmp;
418
419 t += sprintf(t, "isac_fill_fifo cnt %d", count);
420 QuickHex(t, ptr, count);
421 debugl1(sp, tmp);
422 }
423 }
424
425 static void
426 ph_command(struct IsdnCardState *sp, unsigned int command)
427 {
428 if (sp->debug & L1_DEB_ISAC) {
429 char tmp[32];
430 sprintf(tmp, "ph_command %d", command);
431 debugl1(sp, tmp);
432 }
433 writeisac(sp->membase, ISAC_CIX0, (command << 2) | 3);
434 }
435
436 static inline void
437 isac_interrupt(struct IsdnCardState *sp, u_char val)
438 {
439 u_char exval;
440 struct sk_buff *skb;
441 unsigned int count;
442 char tmp[32];
443
444 if (sp->debug & L1_DEB_ISAC) {
445 sprintf(tmp, "ISAC interrupt %x", val);
446 debugl1(sp, tmp);
447 }
448 if (val & 0x80) { /* RME */
449 exval = readisac(sp->membase, ISAC_RSTA);
450 if ((exval & 0x70) != 0x20) {
451 if (exval & 0x40)
452 if (sp->debug & L1_DEB_WARN)
453 debugl1(sp, "ISAC RDO");
454 if (!exval & 0x20)
455 if (sp->debug & L1_DEB_WARN)
456 debugl1(sp, "ISAC CRC error");
457 writeisac(sp->membase, ISAC_CMDR, 0x80);
458 } else {
459 count = readisac(sp->membase, ISAC_RBCL) & 0x1f;
460 if (count == 0)
461 count = 32;
462 isac_empty_fifo(sp, count);
463 if ((count = sp->rcvidx) > 0) {
464 if (!(skb = alloc_skb(count, GFP_ATOMIC)))
465 printk(KERN_WARNING "AVM: D receive out of memory\n");
466 else {
467 memcpy(skb_put(skb, count), sp->rcvbuf, count);
468 skb_queue_tail(&sp->rq, skb);
469 }
470 }
471 }
472 sp->rcvidx = 0;
473 isac_sched_event(sp, ISAC_RCVBUFREADY);
474 }
475 if (val & 0x40) { /* RPF */
476 isac_empty_fifo(sp, 32);
477 }
478 if (val & 0x20) { /* RSC */
479 /* never */
480 if (sp->debug & L1_DEB_WARN)
481 debugl1(sp, "ISAC RSC interrupt");
482 }
483 if (val & 0x10) { /* XPR */
484 if (sp->tx_skb)
485 if (sp->tx_skb->len) {
486 isac_fill_fifo(sp);
487 goto afterXPR;
488 } else {
489 SET_SKB_FREE(sp->tx_skb);
490 dev_kfree_skb(sp->tx_skb, FREE_WRITE);
491 sp->tx_cnt = 0;
492 sp->tx_skb = NULL;
493 }
494 if ((sp->tx_skb = skb_dequeue(&sp->sq))) {
495 sp->tx_cnt = 0;
496 isac_fill_fifo(sp);
497 } else
498 isac_sched_event(sp, ISAC_XMTBUFREADY);
499 }
500 afterXPR:
501 if (val & 0x04) { /* CISQ */
502 sp->ph_state = (readisac(sp->membase, ISAC_CIX0) >> 2)
503 & 0xf;
504 if (sp->debug & L1_DEB_ISAC) {
505 sprintf(tmp, "l1state %d", sp->ph_state);
506 debugl1(sp, tmp);
507 }
508 isac_new_ph(sp);
509 }
510 if (val & 0x02) { /* SIN */
511 /* never */
512 if (sp->debug & L1_DEB_WARN)
513 debugl1(sp, "ISAC SIN interrupt");
514 }
515 if (val & 0x01) { /* EXI */
516 exval = readisac(sp->membase, ISAC_EXIR);
517 if (sp->debug & L1_DEB_WARN) {
518 sprintf(tmp, "ISAC EXIR %02x", exval);
519 debugl1(sp, tmp);
520 }
521 }
522 }
523
524 static inline void
525 hscx_int_main(struct IsdnCardState *sp, u_char val)
526 {
527
528 u_char exval;
529 struct HscxState *hsp;
530 char tmp[32];
531
532
533 if (val & 0x01) {
534 hsp = sp->hs + 1;
535 exval = readhscx(sp->membase, 1, HSCX_EXIR);
536 if (exval == 0x40) {
537 if (hsp->mode == 1)
538 hscx_fill_fifo(hsp);
539 else {
540 /* Here we lost an TX interrupt, so
541 * restart transmitting the whole frame.
542 */
543 if (hsp->tx_skb) {
544 skb_push(hsp->tx_skb, hsp->count);
545 hsp->tx_cnt += hsp->count;
546 hsp->count = 0;
547 }
548 writehscxCMDR(sp->membase, hsp->hscx, 0x01);
549 if (sp->debug & L1_DEB_WARN) {
550 sprintf(tmp, "HSCX B EXIR %x Lost TX", exval);
551 debugl1(sp, tmp);
552 }
553 }
554 } else if (sp->debug & L1_DEB_HSCX) {
555 sprintf(tmp, "HSCX B EXIR %x", exval);
556 debugl1(sp, tmp);
557 }
558 }
559 if (val & 0xf8) {
560 if (sp->debug & L1_DEB_HSCX) {
561 sprintf(tmp, "HSCX B interrupt %x", val);
562 debugl1(sp, tmp);
563 }
564 hscx_interrupt(sp, val, 1);
565 }
566 if (val & 0x02) {
567 hsp = sp->hs;
568 exval = readhscx(sp->membase, 0, HSCX_EXIR);
569 if (exval == 0x40) {
570 if (hsp->mode == 1)
571 hscx_fill_fifo(hsp);
572 else {
573 /* Here we lost an TX interrupt, so
574 * restart transmitting the whole frame.
575 */
576 if (hsp->tx_skb) {
577 skb_push(hsp->tx_skb, hsp->count);
578 hsp->tx_cnt += hsp->count;
579 hsp->count = 0;
580 }
581 writehscxCMDR(sp->membase, hsp->hscx, 0x01);
582 if (sp->debug & L1_DEB_WARN) {
583 sprintf(tmp, "HSCX A EXIR %x Lost TX", exval);
584 debugl1(sp, tmp);
585 }
586 }
587 } else if (sp->debug & L1_DEB_HSCX) {
588 sprintf(tmp, "HSCX A EXIR %x", exval);
589 debugl1(sp, tmp);
590 }
591 }
592 if (val & 0x04) {
593 exval = readhscx(sp->membase, 0, HSCX_ISTA);
594 if (sp->debug & L1_DEB_HSCX) {
595 sprintf(tmp, "HSCX A interrupt %x", exval);
596 debugl1(sp, tmp);
597 }
598 hscx_interrupt(sp, exval, 0);
599 }
600 }
601
602 static void
603 telesS0_interrupt(int intno, void *dev_id, struct pt_regs *regs)
604 {
605 struct IsdnCardState *sp;
606 u_char val, stat = 0;
607
608 sp = (struct IsdnCardState *) dev_id;
609
610 if (!sp) {
611 printk(KERN_WARNING "Teles0: Spurious interrupt!\n");
612 return;
613 }
614 val = readhscx(sp->membase, 1, HSCX_ISTA);
615 Start_HSCX:
616 if (val) {
617 hscx_int_main(sp, val);
618 stat |= 1;
619 }
620 val = readisac(sp->membase, ISAC_ISTA);
621 Start_ISAC:
622 if (val) {
623 isac_interrupt(sp, val);
624 stat |= 2;
625 }
626 val = readhscx(sp->membase, 1, HSCX_ISTA);
627 if (val) {
628 if (sp->debug & L1_DEB_HSCX)
629 debugl1(sp, "HSCX IntStat after IntRoutine");
630 goto Start_HSCX;
631 }
632 val = readisac(sp->membase, ISAC_ISTA);
633 if (val) {
634 if (sp->debug & L1_DEB_ISAC)
635 debugl1(sp, "ISAC IntStat after IntRoutine");
636 goto Start_ISAC;
637 }
638 if (stat & 1) {
639 writehscx(sp->membase, 0, HSCX_MASK, 0xFF);
640 writehscx(sp->membase, 1, HSCX_MASK, 0xFF);
641 writehscx(sp->membase, 0, HSCX_MASK, 0x0);
642 writehscx(sp->membase, 1, HSCX_MASK, 0x0);
643 }
644 if (stat & 2) {
645 writeisac(sp->membase, ISAC_MASK, 0xFF);
646 writeisac(sp->membase, ISAC_MASK, 0x0);
647 }
648 }
649
650
651 static void
652 initisac(struct IsdnCardState *sp)
653 {
654 unsigned int adr = sp->membase;
655
656 /* 16.0 IOM 1 Mode */
657 writeisac(adr, ISAC_MASK, 0xff);
658 writeisac(adr, ISAC_ADF2, 0x0);
659 writeisac(adr, ISAC_SPCR, 0xa);
660 writeisac(adr, ISAC_ADF1, 0x2);
661 writeisac(adr, ISAC_STCR, 0x70);
662 writeisac(adr, ISAC_MODE, 0xc9);
663 writeisac(adr, ISAC_CMDR, 0x41);
664 writeisac(adr, ISAC_CIX0, (1 << 2) | 3);
665 writeisac(adr, ISAC_MASK, 0xff);
666 writeisac(adr, ISAC_MASK, 0x0);
667 }
668
669 static void
670 modehscx(struct HscxState *hs, int mode, int ichan)
671 {
672 struct IsdnCardState *sp = hs->sp;
673 int hscx = hs->hscx;
674
675 if (sp->debug & L1_DEB_HSCX) {
676 char tmp[40];
677 sprintf(tmp, "hscx %c mode %d ichan %d",
678 'A' + hscx, mode, ichan);
679 debugl1(sp, tmp);
680 }
681 hs->mode = mode;
682 writehscx(sp->membase, hscx, HSCX_CCR1, 0x85);
683 writehscx(sp->membase, hscx, HSCX_XAD1, 0xFF);
684 writehscx(sp->membase, hscx, HSCX_XAD2, 0xFF);
685 writehscx(sp->membase, hscx, HSCX_RAH2, 0xFF);
686 writehscx(sp->membase, hscx, HSCX_XBCH, 0x0);
687
688 /* Switch IOM 1 SSI */
689 if (hscx == 0)
690 ichan = 1 - ichan;
691
692 switch (mode) {
693 case (0):
694 writehscx(sp->membase, hscx, HSCX_CCR2, 0x30);
695 writehscx(sp->membase, hscx, HSCX_TSAX, 0xff);
696 writehscx(sp->membase, hscx, HSCX_TSAR, 0xff);
697 writehscx(sp->membase, hscx, HSCX_XCCR, 7);
698 writehscx(sp->membase, hscx, HSCX_RCCR, 7);
699 writehscx(sp->membase, hscx, HSCX_MODE, 0x84);
700 break;
701 case (1):
702 if (ichan == 0) {
703 writehscx(sp->membase, hscx, HSCX_CCR2, 0x30);
704 writehscx(sp->membase, hscx, HSCX_TSAX, 0x7);
705 writehscx(sp->membase, hscx, HSCX_TSAR, 0x7);
706 writehscx(sp->membase, hscx, HSCX_XCCR, 7);
707 writehscx(sp->membase, hscx, HSCX_RCCR, 7);
708 } else {
709 writehscx(sp->membase, hscx, HSCX_CCR2, 0x30);
710 writehscx(sp->membase, hscx, HSCX_TSAX, 0x3);
711 writehscx(sp->membase, hscx, HSCX_TSAR, 0x3);
712 writehscx(sp->membase, hscx, HSCX_XCCR, 7);
713 writehscx(sp->membase, hscx, HSCX_RCCR, 7);
714 }
715 writehscx(sp->membase, hscx, HSCX_MODE, 0xe4);
716 writehscx(sp->membase, hscx, HSCX_CMDR, 0x41);
717 break;
718 case (2):
719 if (ichan == 0) {
720 writehscx(sp->membase, hscx, HSCX_CCR2, 0x30);
721 writehscx(sp->membase, hscx, HSCX_TSAX, 0x7);
722 writehscx(sp->membase, hscx, HSCX_TSAR, 0x7);
723 writehscx(sp->membase, hscx, HSCX_XCCR, 7);
724 writehscx(sp->membase, hscx, HSCX_RCCR, 7);
725 } else {
726 writehscx(sp->membase, hscx, HSCX_CCR2, 0x30);
727 writehscx(sp->membase, hscx, HSCX_TSAX, 0x3);
728 writehscx(sp->membase, hscx, HSCX_TSAR, 0x3);
729 writehscx(sp->membase, hscx, HSCX_XCCR, 7);
730 writehscx(sp->membase, hscx, HSCX_RCCR, 7);
731 }
732 writehscx(sp->membase, hscx, HSCX_MODE, 0x8c);
733 writehscx(sp->membase, hscx, HSCX_CMDR, 0x41);
734 break;
735 }
736 writehscx(sp->membase, hscx, HSCX_ISTA, 0x00);
737 }
738
739 void
740 release_io_teles0(struct IsdnCard *card)
741 {
742 if (card->sp->cfg_reg)
743 release_region(card->sp->cfg_reg, 8);
744 }
745
746 static void
747 clear_pending_ints(struct IsdnCardState *sp)
748 {
749 int val;
750 char tmp[64];
751
752 val = readhscx(sp->membase, 1, HSCX_ISTA);
753 sprintf(tmp, "HSCX B ISTA %x", val);
754 debugl1(sp, tmp);
755 if (val & 0x01) {
756 val = readhscx(sp->membase, 1, HSCX_EXIR);
757 sprintf(tmp, "HSCX B EXIR %x", val);
758 debugl1(sp, tmp);
759 } else if (val & 0x02) {
760 val = readhscx(sp->membase, 0, HSCX_EXIR);
761 sprintf(tmp, "HSCX A EXIR %x", val);
762 debugl1(sp, tmp);
763 }
764 val = readhscx(sp->membase, 0, HSCX_ISTA);
765 sprintf(tmp, "HSCX A ISTA %x", val);
766 debugl1(sp, tmp);
767 val = readhscx(sp->membase, 1, HSCX_STAR);
768 sprintf(tmp, "HSCX B STAR %x", val);
769 debugl1(sp, tmp);
770 val = readhscx(sp->membase, 0, HSCX_STAR);
771 sprintf(tmp, "HSCX A STAR %x", val);
772 debugl1(sp, tmp);
773 val = readisac(sp->membase, ISAC_STAR);
774 sprintf(tmp, "ISAC STAR %x", val);
775 debugl1(sp, tmp);
776 val = readisac(sp->membase, ISAC_MODE);
777 sprintf(tmp, "ISAC MODE %x", val);
778 debugl1(sp, tmp);
779 val = readisac(sp->membase, ISAC_ADF2);
780 sprintf(tmp, "ISAC ADF2 %x", val);
781 debugl1(sp, tmp);
782 val = readisac(sp->membase, ISAC_ISTA);
783 sprintf(tmp, "ISAC ISTA %x", val);
784 debugl1(sp, tmp);
785 if (val & 0x01) {
786 val = readisac(sp->membase, ISAC_EXIR);
787 sprintf(tmp, "ISAC EXIR %x", val);
788 debugl1(sp, tmp);
789 } else if (val & 0x04) {
790 val = readisac(sp->membase, ISAC_CIR0);
791 sprintf(tmp, "ISAC CIR0 %x", val);
792 debugl1(sp, tmp);
793 }
794 writeisac(sp->membase, ISAC_MASK, 0);
795 writeisac(sp->membase, ISAC_CMDR, 0x41);
796 }
797
798 int
799 initteles0(struct IsdnCardState *sp)
800 {
801 int ret;
802 int loop = 0;
803 char tmp[40];
804
805 sp->counter = kstat_irqs(sp->irq);
806 sprintf(tmp, "IRQ %d count %d", sp->irq, sp->counter);
807 debugl1(sp, tmp);
808 clear_pending_ints(sp);
809 ret = get_irq(sp->cardnr, &telesS0_interrupt);
810 if (ret) {
811 initisac(sp);
812 sp->modehscx(sp->hs, 0, 0);
813 sp->modehscx(sp->hs + 1, 0, 0);
814 while (loop++ < 10) {
815 /* At least 1-3 irqs must happen
816 * (one from HSCX A, one from HSCX B, 3rd from ISAC)
817 */
818 if (kstat_irqs(sp->irq) > sp->counter)
819 break;
820 current->state = TASK_INTERRUPTIBLE;
821 current->timeout = jiffies + 1;
822 schedule();
823 }
824 sprintf(tmp, "IRQ %d count %d", sp->irq,
825 kstat_irqs(sp->irq));
826 debugl1(sp, tmp);
827 if (kstat_irqs(sp->irq) == sp->counter) {
828 printk(KERN_WARNING
829 "Teles0: IRQ(%d) getting no interrupts during init\n",
830 sp->irq);
831 free_irq(sp->irq, sp);
832 return (0);
833 }
834 }
835 return (ret);
836 }
837
838 int
839 setup_teles0(struct IsdnCard *card)
840 {
841 u_char cfval, val, verA, verB;
842 struct IsdnCardState *sp = card->sp;
843 long flags;
844 char tmp[64];
845
846 strcpy(tmp, teles0_revision);
847 printk(KERN_NOTICE "HiSax: Teles 8.0/16.0 driver Rev. %s\n", HiSax_getrev(tmp));
848 if ((sp->typ != ISDN_CTYPE_16_0) && (sp->typ != ISDN_CTYPE_8_0))
849 return (0);
850
851 if (sp->typ == ISDN_CTYPE_16_0)
852 sp->cfg_reg = card->para[2];
853 else /* 8.0 */
854 sp->cfg_reg = 0;
855
856 if (card->para[1] < 0x10000) {
857 card->para[1] <<= 4;
858 printk(KERN_INFO
859 "Teles0: membase configured DOSish, assuming 0x%lx\n",
860 (unsigned long) card->para[1]);
861 }
862 sp->membase = card->para[1];
863 sp->irq = card->para[0];
864 if (sp->cfg_reg) {
865 if (check_region((sp->cfg_reg), 8)) {
866 printk(KERN_WARNING
867 "HiSax: %s config port %x-%x already in use\n",
868 CardType[card->typ],
869 sp->cfg_reg,
870 sp->cfg_reg + 8);
871 return (0);
872 } else {
873 request_region(sp->cfg_reg, 8, "teles cfg");
874 }
875 }
876 switch (sp->irq) {
877 case 2:
878 cfval = 0x00;
879 break;
880 case 3:
881 cfval = 0x02;
882 break;
883 case 4:
884 cfval = 0x04;
885 break;
886 case 5:
887 cfval = 0x06;
888 break;
889 case 10:
890 cfval = 0x08;
891 break;
892 case 11:
893 cfval = 0x0A;
894 break;
895 case 12:
896 cfval = 0x0C;
897 break;
898 case 15:
899 cfval = 0x0E;
900 break;
901 default:
902 cfval = 0x00;
903 break;
904 }
905 cfval |= ((card->para[1] >> 9) & 0xF0);
906 if (sp->cfg_reg) {
907 if ((val = bytein(sp->cfg_reg + 0)) != 0x51) {
908 printk(KERN_WARNING "Teles0: 16.0 Byte at %x is %x\n",
909 sp->cfg_reg + 0, val);
910 release_region(sp->cfg_reg, 8);
911 return (0);
912 }
913 if ((val = bytein(sp->cfg_reg + 1)) != 0x93) {
914 printk(KERN_WARNING "Teles0: 16.0 Byte at %x is %x\n",
915 sp->cfg_reg + 1, val);
916 release_region(sp->cfg_reg, 8);
917 return (0);
918 }
919 val = bytein(sp->cfg_reg + 2); /* 0x1e=without AB
920 * 0x1f=with AB
921 * 0x1c 16.3 ???
922 */
923 if (val != 0x1e && val != 0x1f) {
924 printk(KERN_WARNING "Teles0: 16.0 Byte at %x is %x\n",
925 sp->cfg_reg + 2, val);
926 release_region(sp->cfg_reg, 8);
927 return (0);
928 }
929 save_flags(flags);
930 byteout(sp->cfg_reg + 4, cfval);
931 sti();
932 HZDELAY(HZ / 10 + 1);
933 byteout(sp->cfg_reg + 4, cfval | 1);
934 HZDELAY(HZ / 10 + 1);
935 restore_flags(flags);
936 }
937 printk(KERN_NOTICE
938 "HiSax: %s config irq:%d mem:%x cfg:%x\n",
939 CardType[sp->typ], sp->irq,
940 sp->membase, sp->cfg_reg);
941 verA = readhscx(sp->membase, 0, HSCX_VSTR) & 0xf;
942 verB = readhscx(sp->membase, 1, HSCX_VSTR) & 0xf;
943 printk(KERN_INFO "Teles0: HSCX version A: %s B: %s\n",
944 HscxVersion(verA), HscxVersion(verB));
945 val = readisac(sp->membase, ISAC_RBCH);
946 printk(KERN_INFO "Teles0: ISAC %s\n",
947 ISACVersion(val));
948
949 if ((verA == 0) | (verA == 0xf) | (verB == 0) | (verB == 0xf)) {
950 printk(KERN_WARNING
951 "Teles0: wrong HSCX versions check IO/MEM addresses\n");
952 release_io_teles0(card);
953 return (0);
954 }
955 save_flags(flags);
956 writeb(0, sp->membase + 0x80);
957 sti();
958 HZDELAY(HZ / 5 + 1);
959 writeb(1, sp->membase + 0x80);
960 HZDELAY(HZ / 5 + 1);
961 restore_flags(flags);
962
963 sp->modehscx = &modehscx;
964 sp->ph_command = &ph_command;
965 sp->hscx_fill_fifo = &hscx_fill_fifo;
966 sp->isac_fill_fifo = &isac_fill_fifo;
967 return (1);
968 }
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