2 * wd33c93.h - Linux device driver definitions for the
3 * Commodore Amiga A2091/590 SCSI controller card
5 * IMPORTANT: This file is for version 1.25 - 09/Jul/1997
7 * Copyright (c) 1996 John Shifflett, GeoLog Consulting
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
26 #include <linux/config.h>
28 #define PROC_INTERFACE /* add code for /proc/scsi/wd33c93/xxx interface */
30 #define PROC_STATISTICS /* add code for keeping various real time stats */
33 #define SYNC_DEBUG /* extra info on sync negotiation printed */
34 #define DEBUGGING_ON /* enable command-line debugging bitmask */
35 #define DEBUG_DEFAULTS 0 /* default debugging bitmask */
39 #define DB(f,a) if (hostdata->args & (f)) a;
44 #define uchar unsigned char
47 /* wd register names */
48 #define WD_OWN_ID 0x00
49 #define WD_CONTROL 0x01
50 #define WD_TIMEOUT_PERIOD 0x02
60 #define WD_CDB_10 0x0c
61 #define WD_CDB_11 0x0d
62 #define WD_CDB_12 0x0e
63 #define WD_TARGET_LUN 0x0f
64 #define WD_COMMAND_PHASE 0x10
65 #define WD_SYNCHRONOUS_TRANSFER 0x11
66 #define WD_TRANSFER_COUNT_MSB 0x12
67 #define WD_TRANSFER_COUNT 0x13
68 #define WD_TRANSFER_COUNT_LSB 0x14
69 #define WD_DESTINATION_ID 0x15
70 #define WD_SOURCE_ID 0x16
71 #define WD_SCSI_STATUS 0x17
72 #define WD_COMMAND 0x18
74 #define WD_QUEUE_TAG 0x1a
75 #define WD_AUXILIARY_STATUS 0x1f
78 #define WD_CMD_RESET 0x00
79 #define WD_CMD_ABORT 0x01
80 #define WD_CMD_ASSERT_ATN 0x02
81 #define WD_CMD_NEGATE_ACK 0x03
82 #define WD_CMD_DISCONNECT 0x04
83 #define WD_CMD_RESELECT 0x05
84 #define WD_CMD_SEL_ATN 0x06
85 #define WD_CMD_SEL 0x07
86 #define WD_CMD_SEL_ATN_XFER 0x08
87 #define WD_CMD_SEL_XFER 0x09
88 #define WD_CMD_RESEL_RECEIVE 0x0a
89 #define WD_CMD_RESEL_SEND 0x0b
90 #define WD_CMD_WAIT_SEL_RECEIVE 0x0c
91 #define WD_CMD_TRANS_ADDR 0x18
92 #define WD_CMD_TRANS_INFO 0x20
93 #define WD_CMD_TRANSFER_PAD 0x21
94 #define WD_CMD_SBT_MODE 0x80
97 #define ASR_INT (0x80)
98 #define ASR_LCI (0x40)
99 #define ASR_BSY (0x20)
100 #define ASR_CIP (0x10)
101 #define ASR_PE (0x02)
102 #define ASR_DBR (0x01)
104 /* SCSI Bus Phases */
105 #define PHS_DATA_OUT 0x00
106 #define PHS_DATA_IN 0x01
107 #define PHS_COMMAND 0x02
108 #define PHS_STATUS 0x03
109 #define PHS_MESS_OUT 0x06
110 #define PHS_MESS_IN 0x07
112 /* Command Status Register definitions */
114 /* reset state interrupts */
115 #define CSR_RESET 0x00
116 #define CSR_RESET_AF 0x01
118 /* successful completion interrupts */
119 #define CSR_RESELECT 0x10
120 #define CSR_SELECT 0x11
121 #define CSR_SEL_XFER_DONE 0x16
122 #define CSR_XFER_DONE 0x18
124 /* paused or aborted interrupts */
125 #define CSR_MSGIN 0x20
127 #define CSR_SEL_ABORT 0x22
128 #define CSR_RESEL_ABORT 0x25
129 #define CSR_RESEL_ABORT_AM 0x27
130 #define CSR_ABORT 0x28
132 /* terminated interrupts */
133 #define CSR_INVALID 0x40
134 #define CSR_UNEXP_DISC 0x41
135 #define CSR_TIMEOUT 0x42
136 #define CSR_PARITY 0x43
137 #define CSR_PARITY_ATN 0x44
138 #define CSR_BAD_STATUS 0x45
139 #define CSR_UNEXP 0x48
141 /* service required interrupts */
142 #define CSR_RESEL 0x80
143 #define CSR_RESEL_AM 0x81
144 #define CSR_DISC 0x85
145 #define CSR_SRV_REQ 0x88
147 /* Own ID/CDB Size register */
148 #define OWNID_EAF 0x08
149 #define OWNID_EHP 0x10
150 #define OWNID_RAF 0x20
151 #define OWNID_FS_8 0x00
152 #define OWNID_FS_12 0x40
153 #define OWNID_FS_16 0x80
155 /* define these so we don't have to change a2091.c, etc. */
156 #define WD33C93_FS_8_10 OWNID_FS_8
157 #define WD33C93_FS_12_15 OWNID_FS_12
158 #define WD33C93_FS_16_20 OWNID_FS_16
160 /* Control register */
161 #define CTRL_HSP 0x01
163 #define CTRL_IDI 0x04
164 #define CTRL_EDI 0x08
165 #define CTRL_HHP 0x10
166 #define CTRL_POLLED 0x00
167 #define CTRL_BURST 0x20
168 #define CTRL_BUS 0x40
169 #define CTRL_DMA 0x80
171 /* Timeout Period register */
172 #define TIMEOUT_PERIOD_VALUE 20 /* 20 = 200 ms */
174 /* Synchronous Transfer Register */
177 /* Destination ID register */
178 #define DSTID_DPD 0x40
179 #define DATA_OUT_DIR 0
180 #define DATA_IN_DIR 1
181 #define DSTID_SCC 0x80
183 /* Source ID register */
184 #define SRCID_MASK 0x07
185 #define SRCID_SIV 0x08
186 #define SRCID_DSP 0x20
187 #define SRCID_ES 0x40
188 #define SRCID_ER 0x80
190 /* This is what the 3393 chip looks like to us */
192 volatile unsigned char SASR
;
193 #if !defined(CONFIG_MVME147_SCSI)
196 #ifdef CONFIG_SGI_IP22
199 volatile unsigned char SCMD
;
203 typedef int (*dma_setup_t
) (Scsi_Cmnd
*SCpnt
, int dir_in
);
204 typedef void (*dma_stop_t
) (struct Scsi_Host
*instance
, Scsi_Cmnd
*SCpnt
,
208 #define ILLEGAL_STATUS_BYTE 0xff
210 #define DEFAULT_SX_PER 376 /* (ns) fairly safe */
211 #define DEFAULT_SX_OFF 0 /* aka async */
213 #define OPTIMUM_SX_PER 252 /* (ns) best we can do (mult-of-4) */
214 #define OPTIMUM_SX_OFF 12 /* size of wd3393 fifo */
217 unsigned int period_ns
;
221 /* FEF: defines for hostdata->dma_buffer_pool */
223 #define BUF_CHIP_ALLOCED 0
224 #define BUF_SCSI_ALLOCED 1
226 struct WD33C93_hostdata
{
227 struct Scsi_Host
*next
;
230 uchar chip
; /* what kind of wd33c93? */
231 uchar microcode
; /* microcode rev */
232 uchar dma_buffer_pool
; /* FEF: buffer from chip_ram? */
233 int dma_dir
; /* data transfer dir. */
234 dma_setup_t dma_setup
;
236 unsigned int dma_xfer_mask
;
237 uchar
*dma_bounce_buffer
;
238 unsigned int dma_bounce_len
;
239 volatile uchar busy
[8]; /* index = target, bit = lun */
240 volatile Scsi_Cmnd
*input_Q
; /* commands waiting to be started */
241 volatile Scsi_Cmnd
*selecting
; /* trying to select this command */
242 volatile Scsi_Cmnd
*connected
; /* currently connected command */
243 volatile Scsi_Cmnd
*disconnected_Q
;/* commands waiting for reconnect */
244 uchar state
; /* what we are currently doing */
245 uchar dma
; /* current state of DMA (on/off) */
246 uchar level2
; /* extent to which Level-2 commands are used */
247 uchar disconnect
; /* disconnect/reselect policy */
248 unsigned int args
; /* set from command-line argument */
249 uchar incoming_msg
[8]; /* filled during message_in phase */
250 int incoming_ptr
; /* mainly used with EXTENDED messages */
251 uchar outgoing_msg
[8]; /* send this during next message_out */
252 int outgoing_len
; /* length of outgoing message */
253 unsigned int default_sx_per
; /* default transfer period for SCSI bus */
254 uchar sync_xfer
[8]; /* sync_xfer reg settings per target */
255 uchar sync_stat
[8]; /* status of sync negotiation per target */
256 uchar no_sync
; /* bitmask: don't do sync on these targets */
257 uchar no_dma
; /* set this flag to disable DMA */
258 #ifdef PROC_INTERFACE
259 uchar proc
; /* bitmask: what's in proc output */
260 #ifdef PROC_STATISTICS
261 unsigned long cmd_cnt
[8]; /* # of commands issued per target */
262 unsigned long int_cnt
; /* # of interrupts serviced */
263 unsigned long pio_cnt
; /* # of pio data transfers */
264 unsigned long dma_cnt
; /* # of DMA data transfers */
265 unsigned long disc_allowed_cnt
[8]; /* # of disconnects allowed per target */
266 unsigned long disc_done_cnt
[8]; /* # of disconnects done per target*/
272 /* defines for hostdata->chip */
277 #define C_UNKNOWN_CHIP 100
279 /* defines for hostdata->state */
281 #define S_UNCONNECTED 0
282 #define S_SELECTING 1
283 #define S_RUNNING_LEVEL2 2
284 #define S_CONNECTED 3
285 #define S_PRE_TMP_DISC 4
286 #define S_PRE_CMP_DISC 5
288 /* defines for hostdata->dma */
291 #define D_DMA_RUNNING 1
293 /* defines for hostdata->level2 */
294 /* NOTE: only the first 3 are implemented so far */
296 #define L2_NONE 1 /* no combination commands - we get lots of ints */
297 #define L2_SELECT 2 /* start with SEL_ATN_XFER, but never resume it */
298 #define L2_BASIC 3 /* resume after STATUS ints & RDP messages */
299 #define L2_DATA 4 /* resume after DATA_IN/OUT ints */
300 #define L2_MOST 5 /* resume after anything except a RESELECT int */
301 #define L2_RESELECT 6 /* resume after everything, including RESELECT ints */
302 #define L2_ALL 7 /* always resume */
304 /* defines for hostdata->disconnect */
307 #define DIS_ADAPTIVE 1
310 /* defines for hostdata->args */
312 #define DB_TEST1 1<<0
313 #define DB_TEST2 1<<1
314 #define DB_QUEUE_COMMAND 1<<2
315 #define DB_EXECUTE 1<<3
317 #define DB_TRANSFER 1<<5
320 /* defines for hostdata->sync_stat[] */
327 /* defines for hostdata->proc */
329 #define PR_VERSION 1<<0
331 #define PR_STATISTICS 1<<2
332 #define PR_CONNECTED 1<<3
333 #define PR_INPUTQ 1<<4
334 #define PR_DISCQ 1<<5
339 void wd33c93_init (struct Scsi_Host
*instance
, wd33c93_regs
*regs
,
340 dma_setup_t setup
, dma_stop_t stop
, int clock_freq
);
341 int wd33c93_abort (Scsi_Cmnd
*cmd
);
342 int wd33c93_queuecommand (Scsi_Cmnd
*cmd
, void (*done
)(Scsi_Cmnd
*));
343 void wd33c93_intr (struct Scsi_Host
*instance
);
344 int wd33c93_proc_info(char *, char **, off_t
, int, int, int);
345 int wd33c93_reset (Scsi_Cmnd
*, unsigned int);
346 void wd33c93_release(void);
348 #endif /* WD33C93_H */