drivers/pci/setup-res.c

   1 /*
   2  *      drivers/pci/setup-res.c
   3  *
   4  * Extruded from code written by
   5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
   6  *      David Mosberger (davidm@cs.arizona.edu)
   7  *      David Miller (davem@redhat.com)
   8  *
   9  * Support routines for initializing a PCI subsystem.
  10  */
  11
  12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
  13
  14 /*
  15  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  16  *           Resource sorting
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/pci.h>
  22 #include <linux/errno.h>
  23 #include <linux/ioport.h>
  24 #include <linux/cache.h>
  25 #include <linux/slab.h>
  26
  27
  28 #define DEBUG_CONFIG 1
  29 #if DEBUG_CONFIG
  30 # define DBGC(args)     printk args
  31 #else
  32 # define DBGC(args)
  33 #endif
  34
  35
  36 int __init
  37 pci_claim_resource(struct pci_dev *dev, int resource)
  38 {
  39         struct resource *res = &dev->resource[resource];
  40         struct resource *root = pci_find_parent_resource(dev, res);
  41         int err;
  42
  43         err = -EINVAL;
  44         if (root != NULL) {
  45                 err = request_resource(root, res);
  46                 if (err) {
  47                         printk(KERN_ERR "PCI: Address space collision on "
  48                                "region %d of device %s [%lx:%lx]\n",
  49                                resource, dev->name, res->start, res->end);
  50                 }
  51         } else {
  52                 printk(KERN_ERR "PCI: No parent found for region %d "
  53                        "of device %s\n", resource, dev->name);
  54         }
  55
  56         return err;
  57 }
  58
  59 /*
  60  * Given the PCI bus a device resides on, try to
  61  * find an acceptable resource allocation for a
  62  * specific device resource..
  63  */
  64 static int pci_assign_bus_resource(const struct pci_bus *bus,
  65         struct pci_dev *dev,
  66         struct resource *res,
  67         unsigned long size,
  68         unsigned long min,
  69         unsigned int type_mask,
  70         int resno)
  71 {
  72         int i;
  73
  74         type_mask |= IORESOURCE_IO | IORESOURCE_MEM;
  75         for (i = 0 ; i < 4; i++) {
  76                 struct resource *r = bus->resource[i];
  77                 if (!r)
  78                         continue;
  79
  80                 /* type_mask must match */
  81                 if ((res->flags ^ r->flags) & type_mask)
  82                         continue;
  83
  84                 /* We cannot allocate a non-prefetching resource from a pre-fetching area */
  85                 if ((r->flags & IORESOURCE_PREFETCH) && !(res->flags & IORESOURCE_PREFETCH))
  86                         continue;
  87
  88                 /* Ok, try it out.. */
  89                 if (allocate_resource(r, res, size, min, -1, size, pcibios_align_resource, dev) < 0)
  90                         continue;
  91
  92                 /* Update PCI config space.  */
  93                 pcibios_update_resource(dev, r, res, resno);
  94                 return 0;
  95         }
  96         return -EBUSY;
  97 }
  98
  99 int
 100 pci_assign_resource(struct pci_dev *dev, int i)
 101 {
 102         const struct pci_bus *bus = dev->bus;
 103         struct resource *res = dev->resource + i;
 104         unsigned long size, min;
 105
 106         size = res->end - res->start + 1;
 107         min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
 108
 109         /* First, try exact prefetching match.. */
 110         if (pci_assign_bus_resource(bus, dev, res, size, min, IORESOURCE_PREFETCH, i) < 0) {
 111                 /*
 112                  * That failed.
 113                  *
 114                  * But a prefetching area can handle a non-prefetching
 115                  * window (it will just not perform as well).
 116                  */
 117                 if (!(res->flags & IORESOURCE_PREFETCH) || pci_assign_bus_resource(bus, dev, res, size, min, 0, i) < 0) {
 118                         printk(KERN_ERR "PCI: Failed to allocate resource %d for %s\n", i, dev->name);
 119                         return -EBUSY;
 120                 }
 121         }
 122
 123         DBGC(("  got res[%lx:%lx] for resource %d of %s\n", res->start,
 124                                                 res->end, i, dev->name));
 125
 126         return 0;
 127 }
 128
 129 /* Sort resources of a given type by alignment */
 130 void __init
 131 pdev_sort_resources(struct pci_dev *dev,
 132                     struct resource_list *head, u32 type_mask)
 133 {
 134         int i;
 135
 136         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 137                 struct resource *r;
 138                 struct resource_list *list, *tmp;
 139
 140                 /* PCI-PCI bridges may have I/O ports or
 141                    memory on the primary bus */
 142                 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI &&
 143                                                 i >= PCI_BRIDGE_RESOURCES)
 144                         continue;
 145
 146                 r = &dev->resource[i];
 147                 if (!(r->flags & type_mask) || r->parent)
 148                         continue;
 149                 for (list = head; ; list = list->next) {
 150                         unsigned long size = 0;
 151                         struct resource_list *ln = list->next;
 152
 153                         if (ln)
 154                                 size = ln->res->end - ln->res->start;
 155                         if (r->end - r->start > size) {
 156                                 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
 157                                 tmp->next = ln;
 158                                 tmp->res = r;
 159                                 tmp->dev = dev;
 160                                 list->next = tmp;
 161                                 break;
 162                         }
 163                 }
 164         }
 165 }
 166
 167 void __init
 168 pdev_enable_device(struct pci_dev *dev)
 169 {
 170         u32 reg;
 171         u16 cmd;
 172         int i;
 173
 174         DBGC(("PCI enable device: (%s)\n", dev->name));
 175
 176         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 177
 178         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 179                 struct resource *res = &dev->resource[i];
 180
 181                 if (res->flags & IORESOURCE_IO)
 182                         cmd |= PCI_COMMAND_IO;
 183                 else if (res->flags & IORESOURCE_MEM)
 184                         cmd |= PCI_COMMAND_MEMORY;
 185         }
 186
 187         /* Special case, disable the ROM.  Several devices act funny
 188            (ie. do not respond to memory space writes) when it is left
 189            enabled.  A good example are QlogicISP adapters.  */
 190
 191         if (dev->rom_base_reg) {
 192                 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
 193                 reg &= ~PCI_ROM_ADDRESS_ENABLE;
 194                 pci_write_config_dword(dev, dev->rom_base_reg, reg);
 195                 dev->resource[PCI_ROM_RESOURCE].flags &= ~PCI_ROM_ADDRESS_ENABLE;
 196         }
 197
 198         /* All of these (may) have I/O scattered all around and may not
 199            use I/O base address registers at all.  So we just have to
 200            always enable IO to these devices.  */
 201         if ((dev->class >> 8) == PCI_CLASS_NOT_DEFINED
 202             || (dev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA
 203             || (dev->class >> 8) == PCI_CLASS_STORAGE_IDE
 204             || (dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
 205                 cmd |= PCI_COMMAND_IO;
 206         }
 207
 208         /* ??? Always turn on bus mastering.  If the device doesn't support
 209            it, the bit will go into the bucket. */
 210         cmd |= PCI_COMMAND_MASTER;
 211
 212         /* Set the cache line and default latency (32).  */
 213         pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
 214                         (32 << 8) | (L1_CACHE_BYTES / sizeof(u32)));
 215
 216         /* Enable the appropriate bits in the PCI command register.  */
 217         pci_write_config_word(dev, PCI_COMMAND, cmd);
 218
 219         DBGC(("  cmd reg 0x%x\n", cmd));
 220 }