arch/i386/kernel/mpparse.c

   1 /*
   2  *      Intel Multiprocessor Specificiation 1.1 and 1.4
   3  *      compliant MP-table parsing routines.
   4  *
   5  *      (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
   6  *      (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
   7  *
   8  *      Fixes
   9  *              Erich Boleyn    :       MP v1.4 and additional changes.
  10  *              Alan Cox        :       Added EBDA scanning
  11  *              Ingo Molnar     :       various cleanups and rewrites
  12  *      Maciej W. Rozycki       :       Bits for default MP configurations
  13  */
  14
  15 #include <linux/mm.h>
  16 #include <linux/irq.h>
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/config.h>
  20 #include <linux/bootmem.h>
  21 #include <linux/smp_lock.h>
  22 #include <linux/kernel_stat.h>
  23 #include <linux/mc146818rtc.h>
  24
  25 #include <asm/smp.h>
  26 #include <asm/mtrr.h>
  27 #include <asm/mpspec.h>
  28 #include <asm/pgalloc.h>
  29
  30 /* Have we found an MP table */
  31 int smp_found_config;
  32
  33 /*
  34  * Various Linux-internal data structures created from the
  35  * MP-table.
  36  */
  37 int apic_version [MAX_APICS];
  38 int mp_bus_id_to_type [MAX_MP_BUSSES];
  39 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { -1, };
  40 int mp_current_pci_id;
  41 int pic_mode;
  42 unsigned long mp_lapic_addr;
  43
  44 /* Processor that is doing the boot up */
  45 unsigned int boot_cpu_id = -1U;
  46 /* Internal processor count */
  47 static unsigned int num_processors;
  48
  49 /* Bitmask of physically existing CPUs */
  50 unsigned long phys_cpu_present_map;
  51
  52 /*
  53  * Intel MP BIOS table parsing routines:
  54  */
  55
  56 #ifndef CONFIG_X86_VISWS_APIC
  57 /*
  58  * Checksum an MP configuration block.
  59  */
  60
  61 static int __init mpf_checksum(unsigned char *mp, int len)
  62 {
  63         int sum = 0;
  64
  65         while (len--)
  66                 sum += *mp++;
  67
  68         return sum & 0xFF;
  69 }
  70
  71 /*
  72  * Processor encoding in an MP configuration block
  73  */
  74
  75 static char __init *mpc_family(int family,int model)
  76 {
  77         static char n[32];
  78         static char *model_defs[]=
  79         {
  80                 "80486DX","80486DX",
  81                 "80486SX","80486DX/2 or 80487",
  82                 "80486SL","80486SX/2",
  83                 "Unknown","80486DX/2-WB",
  84                 "80486DX/4","80486DX/4-WB"
  85         };
  86
  87         switch (family) {
  88                 case 0x04:
  89                         if (model < 10)
  90                                 return model_defs[model];
  91                         break;
  92
  93                 case 0x05:
  94                         return("Pentium(tm)");
  95
  96                 case 0x06:
  97                         return("Pentium(tm) Pro");
  98
  99                 case 0x0F:
 100                         if (model == 0x00)
 101                                 return("Pentium 4(tm)");
 102                         if (model == 0x0F)
 103                                 return("Special controller");
 104         }
 105         sprintf(n,"Unknown CPU [%d:%d]",family, model);
 106         return n;
 107 }
 108
 109 static void __init MP_processor_info (struct mpc_config_processor *m)
 110 {
 111         int ver;
 112
 113         if (!(m->mpc_cpuflag & CPU_ENABLED))
 114                 return;
 115
 116         printk("Processor #%d %s APIC version %d\n",
 117                 m->mpc_apicid,
 118                 mpc_family(     (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8 ,
 119                                 (m->mpc_cpufeature & CPU_MODEL_MASK)>>4),
 120                 m->mpc_apicver);
 121
 122         if (m->mpc_featureflag&(1<<0))
 123                 Dprintk("    Floating point unit present.\n");
 124         if (m->mpc_featureflag&(1<<7))
 125                 Dprintk("    Machine Exception supported.\n");
 126         if (m->mpc_featureflag&(1<<8))
 127                 Dprintk("    64 bit compare & exchange supported.\n");
 128         if (m->mpc_featureflag&(1<<9))
 129                 Dprintk("    Internal APIC present.\n");
 130         if (m->mpc_featureflag&(1<<11))
 131                 Dprintk("    SEP present.\n");
 132         if (m->mpc_featureflag&(1<<12))
 133                 Dprintk("    MTRR  present.\n");
 134         if (m->mpc_featureflag&(1<<13))
 135                 Dprintk("    PGE  present.\n");
 136         if (m->mpc_featureflag&(1<<14))
 137                 Dprintk("    MCA  present.\n");
 138         if (m->mpc_featureflag&(1<<15))
 139                 Dprintk("    CMOV  present.\n");
 140         if (m->mpc_featureflag&(1<<16))
 141                 Dprintk("    PAT  present.\n");
 142         if (m->mpc_featureflag&(1<<17))
 143                 Dprintk("    PSE  present.\n");
 144         if (m->mpc_featureflag&(1<<18))
 145                 Dprintk("    PSN  present.\n");
 146         if (m->mpc_featureflag&(1<<19))
 147                 Dprintk("    Cache Line Flush Instruction present.\n");
 148         /* 20 Reserved */
 149         if (m->mpc_featureflag&(1<<21))
 150                 Dprintk("    Debug Trace and EMON Store present.\n");
 151         if (m->mpc_featureflag&(1<<22))
 152                 Dprintk("    ACPI Thermal Throttle Registers  present.\n");
 153         if (m->mpc_featureflag&(1<<23))
 154                 Dprintk("    MMX  present.\n");
 155         if (m->mpc_featureflag&(1<<24))
 156                 Dprintk("    FXSR  present.\n");
 157         if (m->mpc_featureflag&(1<<25))
 158                 Dprintk("    XMM  present.\n");
 159         if (m->mpc_featureflag&(1<<26))
 160                 Dprintk("    Willamette New Instructions  present.\n");
 161         if (m->mpc_featureflag&(1<<27))
 162                 Dprintk("    Self Snoop  present.\n");
 163         /* 28 Reserved */
 164         if (m->mpc_featureflag&(1<<29))
 165                 Dprintk("    Thermal Monitor present.\n");
 166         /* 30, 31 Reserved */
 167
 168
 169         if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
 170                 Dprintk("    Bootup CPU\n");
 171                 boot_cpu_id = m->mpc_apicid;
 172         }
 173         num_processors++;
 174
 175         if (m->mpc_apicid > MAX_APICS) {
 176                 printk("Processor #%d INVALID. (Max ID: %d).\n",
 177                         m->mpc_apicid, MAX_APICS);
 178                 return;
 179         }
 180         ver = m->mpc_apicver;
 181
 182         phys_cpu_present_map |= 1 << m->mpc_apicid;
 183         /*
 184          * Validate version
 185          */
 186         if (ver == 0x0) {
 187                 printk("BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
 188                 ver = 0x10;
 189         }
 190         apic_version[m->mpc_apicid] = ver;
 191 }
 192
 193 static void __init MP_bus_info (struct mpc_config_bus *m)
 194 {
 195         char str[7];
 196
 197         memcpy(str, m->mpc_bustype, 6);
 198         str[6] = 0;
 199         Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
 200
 201         if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
 202                 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
 203         } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
 204                 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
 205         } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
 206                 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
 207                 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
 208                 mp_current_pci_id++;
 209         } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
 210                 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
 211         } else {
 212                 printk("Unknown bustype %s - ignoring\n", str);
 213         }
 214 }
 215
 216 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
 217 {
 218         if (!(m->mpc_flags & MPC_APIC_USABLE))
 219                 return;
 220
 221         printk("I/O APIC #%d Version %d at 0x%lX.\n",
 222                 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
 223         if (nr_ioapics >= MAX_IO_APICS) {
 224                 printk("Max # of I/O APICs (%d) exceeded (found %d).\n",
 225                         MAX_IO_APICS, nr_ioapics);
 226                 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
 227         }
 228         mp_ioapics[nr_ioapics] = *m;
 229         nr_ioapics++;
 230 }
 231
 232 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
 233 {
 234         mp_irqs [mp_irq_entries] = *m;
 235         Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
 236                 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
 237                         m->mpc_irqtype, m->mpc_irqflag & 3,
 238                         (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
 239                         m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
 240         if (++mp_irq_entries == MAX_IRQ_SOURCES)
 241                 panic("Max # of irq sources exceeded!!\n");
 242 }
 243
 244 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
 245 {
 246         Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
 247                 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
 248                         m->mpc_irqtype, m->mpc_irqflag & 3,
 249                         (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
 250                         m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
 251         /*
 252          * Well it seems all SMP boards in existence
 253          * use ExtINT/LVT1 == LINT0 and
 254          * NMI/LVT2 == LINT1 - the following check
 255          * will show us if this assumptions is false.
 256          * Until then we do not have to add baggage.
 257          */
 258         if ((m->mpc_irqtype == mp_ExtINT) &&
 259                 (m->mpc_destapiclint != 0))
 260                         BUG();
 261         if ((m->mpc_irqtype == mp_NMI) &&
 262                 (m->mpc_destapiclint != 1))
 263                         BUG();
 264 }
 265
 266 /*
 267  * Read/parse the MPC
 268  */
 269
 270 static int __init smp_read_mpc(struct mp_config_table *mpc)
 271 {
 272         char str[16];
 273         int count=sizeof(*mpc);
 274         unsigned char *mpt=((unsigned char *)mpc)+count;
 275
 276         if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4))
 277         {
 278                 panic("SMP mptable: bad signature [%c%c%c%c]!\n",
 279                         mpc->mpc_signature[0],
 280                         mpc->mpc_signature[1],
 281                         mpc->mpc_signature[2],
 282                         mpc->mpc_signature[3]);
 283                 return 1;
 284         }
 285         if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length))
 286         {
 287                 panic("SMP mptable: checksum error!\n");
 288                 return 1;
 289         }
 290         if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04)
 291         {
 292                 printk("Bad Config Table version (%d)!!\n",mpc->mpc_spec);
 293                 return 1;
 294         }
 295         memcpy(str,mpc->mpc_oem,8);
 296         str[8]=0;
 297         printk("OEM ID: %s ",str);
 298
 299         memcpy(str,mpc->mpc_productid,12);
 300         str[12]=0;
 301         printk("Product ID: %s ",str);
 302
 303         printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
 304
 305         /* save the local APIC address, it might be non-default */
 306         mp_lapic_addr = mpc->mpc_lapic;
 307
 308         /*
 309          *      Now process the configuration blocks.
 310          */
 311         while (count < mpc->mpc_length) {
 312                 switch(*mpt) {
 313                         case MP_PROCESSOR:
 314                         {
 315                                 struct mpc_config_processor *m=
 316                                         (struct mpc_config_processor *)mpt;
 317                                 MP_processor_info(m);
 318                                 mpt += sizeof(*m);
 319                                 count += sizeof(*m);
 320                                 break;
 321                         }
 322                         case MP_BUS:
 323                         {
 324                                 struct mpc_config_bus *m=
 325                                         (struct mpc_config_bus *)mpt;
 326                                 MP_bus_info(m);
 327                                 mpt += sizeof(*m);
 328                                 count += sizeof(*m);
 329                                 break;
 330                         }
 331                         case MP_IOAPIC:
 332                         {
 333                                 struct mpc_config_ioapic *m=
 334                                         (struct mpc_config_ioapic *)mpt;
 335                                 MP_ioapic_info(m);
 336                                 mpt+=sizeof(*m);
 337                                 count+=sizeof(*m);
 338                                 break;
 339                         }
 340                         case MP_INTSRC:
 341                         {
 342                                 struct mpc_config_intsrc *m=
 343                                         (struct mpc_config_intsrc *)mpt;
 344
 345                                 MP_intsrc_info(m);
 346                                 mpt+=sizeof(*m);
 347                                 count+=sizeof(*m);
 348                                 break;
 349                         }
 350                         case MP_LINTSRC:
 351                         {
 352                                 struct mpc_config_lintsrc *m=
 353                                         (struct mpc_config_lintsrc *)mpt;
 354                                 MP_lintsrc_info(m);
 355                                 mpt+=sizeof(*m);
 356                                 count+=sizeof(*m);
 357                                 break;
 358                         }
 359                 }
 360         }
 361         return num_processors;
 362 }
 363
 364 static void __init construct_default_ioirq_mptable(int mpc_default_type)
 365 {
 366         struct mpc_config_intsrc intsrc;
 367         int i;
 368
 369         intsrc.mpc_type = MP_INTSRC;
 370         intsrc.mpc_irqflag = 0;                 /* conforming */
 371         intsrc.mpc_srcbus = 0;
 372         intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
 373
 374         intsrc.mpc_irqtype = mp_INT;
 375         for (i = 0; i < 16; i++) {
 376                 switch (mpc_default_type) {
 377                 case 2:
 378                         if (i == 0 || i == 13)
 379                                 continue;       /* IRQ0 & IRQ13 not connected */
 380                         /* fall through */
 381                 default:
 382                         if (i == 2)
 383                                 continue;       /* IRQ2 is never connected */
 384                 }
 385
 386                 intsrc.mpc_srcbusirq = i;
 387                 intsrc.mpc_dstirq = i ? i : 2;          /* IRQ0 to INTIN2 */
 388                 MP_intsrc_info(&intsrc);
 389         }
 390
 391         intsrc.mpc_irqtype = mp_ExtINT;
 392         intsrc.mpc_srcbusirq = 0;
 393         intsrc.mpc_dstirq = 0;                          /* 8259A to INTIN0 */
 394         MP_intsrc_info(&intsrc);
 395 }
 396
 397 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
 398 {
 399         struct mpc_config_processor processor;
 400         struct mpc_config_bus bus;
 401         struct mpc_config_ioapic ioapic;
 402         struct mpc_config_lintsrc lintsrc;
 403         int linttypes[2] = { mp_ExtINT, mp_NMI };
 404         int i;
 405
 406         /*
 407          * local APIC has default address
 408          */
 409         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
 410
 411         /*
 412          * 2 CPUs, numbered 0 & 1.
 413          */
 414         processor.mpc_type = MP_PROCESSOR;
 415         /* Either an integrated APIC or a discrete 82489DX. */
 416         processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
 417         processor.mpc_cpuflag = CPU_ENABLED;
 418         processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
 419                                    (boot_cpu_data.x86_model << 4) |
 420                                    boot_cpu_data.x86_mask;
 421         processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
 422         processor.mpc_reserved[0] = 0;
 423         processor.mpc_reserved[1] = 0;
 424         for (i = 0; i < 2; i++) {
 425                 processor.mpc_apicid = i;
 426                 MP_processor_info(&processor);
 427         }
 428
 429         bus.mpc_type = MP_BUS;
 430         bus.mpc_busid = 0;
 431         switch (mpc_default_type) {
 432                 default:
 433                         printk("???\nUnknown standard configuration %d\n",
 434                                 mpc_default_type);
 435                         /* fall through */
 436                 case 1:
 437                 case 5:
 438                         memcpy(bus.mpc_bustype, "ISA   ", 6);
 439                         break;
 440                 case 2:
 441                 case 6:
 442                 case 3:
 443                         memcpy(bus.mpc_bustype, "EISA  ", 6);
 444                         break;
 445                 case 4:
 446                 case 7:
 447                         memcpy(bus.mpc_bustype, "MCA   ", 6);
 448         }
 449         MP_bus_info(&bus);
 450         if (mpc_default_type > 4) {
 451                 bus.mpc_busid = 1;
 452                 memcpy(bus.mpc_bustype, "PCI   ", 6);
 453                 MP_bus_info(&bus);
 454         }
 455
 456         ioapic.mpc_type = MP_IOAPIC;
 457         ioapic.mpc_apicid = 2;
 458         ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
 459         ioapic.mpc_flags = MPC_APIC_USABLE;
 460         ioapic.mpc_apicaddr = 0xFEC00000;
 461         MP_ioapic_info(&ioapic);
 462
 463         /*
 464          * We set up most of the low 16 IO-APIC pins according to MPS rules.
 465          */
 466         construct_default_ioirq_mptable(mpc_default_type);
 467
 468         lintsrc.mpc_type = MP_LINTSRC;
 469         lintsrc.mpc_irqflag = 0;                /* conforming */
 470         lintsrc.mpc_srcbusid = 0;
 471         lintsrc.mpc_srcbusirq = 0;
 472         lintsrc.mpc_destapic = MP_APIC_ALL;
 473         for (i = 0; i < 2; i++) {
 474                 lintsrc.mpc_irqtype = linttypes[i];
 475                 lintsrc.mpc_destapiclint = i;
 476                 MP_lintsrc_info(&lintsrc);
 477         }
 478 }
 479
 480 static struct intel_mp_floating *mpf_found;
 481
 482 /*
 483  * Scan the memory blocks for an SMP configuration block.
 484  */
 485 void __init get_smp_config (void)
 486 {
 487         struct intel_mp_floating *mpf = mpf_found;
 488         printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
 489         if (mpf->mpf_feature2 & (1<<7)) {
 490                 printk("    IMCR and PIC compatibility mode.\n");
 491                 pic_mode = 1;
 492         } else {
 493                 printk("    Virtual Wire compatibility mode.\n");
 494                 pic_mode = 0;
 495         }
 496
 497         /*
 498          * Now see if we need to read further.
 499          */
 500         if (mpf->mpf_feature1 != 0) {
 501
 502                 printk("Default MP configuration #%d\n", mpf->mpf_feature1);
 503                 construct_default_ISA_mptable(mpf->mpf_feature1);
 504
 505         } else if (mpf->mpf_physptr) {
 506
 507                 /*
 508                  * Read the physical hardware table.  Anything here will
 509                  * override the defaults.
 510                  */
 511                 smp_read_mpc((void *)mpf->mpf_physptr);
 512
 513                 /*
 514                  * If there are no explicit MP IRQ entries, then we are
 515                  * broken.  We set up most of the low 16 IO-APIC pins to
 516                  * ISA defaults and hope it will work.
 517                  */
 518                 if (!mp_irq_entries) {
 519                         struct mpc_config_bus bus;
 520
 521                         printk("BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
 522
 523                         bus.mpc_type = MP_BUS;
 524                         bus.mpc_busid = 0;
 525                         memcpy(bus.mpc_bustype, "ISA   ", 6);
 526                         MP_bus_info(&bus);
 527
 528                         construct_default_ioirq_mptable(0);
 529                 }
 530
 531         } else
 532                 BUG();
 533
 534         printk("Processors: %d\n", num_processors);
 535         /*
 536          * Only use the first configuration found.
 537          */
 538 }
 539
 540 static int __init smp_scan_config (unsigned long base, unsigned long length)
 541 {
 542         unsigned long *bp = phys_to_virt(base);
 543         struct intel_mp_floating *mpf;
 544
 545         Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
 546         if (sizeof(*mpf) != 16)
 547                 printk("Error: MPF size\n");
 548
 549         while (length > 0) {
 550                 mpf = (struct intel_mp_floating *)bp;
 551                 if ((*bp == SMP_MAGIC_IDENT) &&
 552                         (mpf->mpf_length == 1) &&
 553                         !mpf_checksum((unsigned char *)bp, 16) &&
 554                         ((mpf->mpf_specification == 1)
 555                                 || (mpf->mpf_specification == 4)) ) {
 556
 557                         smp_found_config = 1;
 558                         printk("found SMP MP-table at %08lx\n",
 559                                                 virt_to_phys(mpf));
 560                         reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
 561                         if (mpf->mpf_physptr)
 562                                 reserve_bootmem(mpf->mpf_physptr, PAGE_SIZE);
 563                         mpf_found = mpf;
 564                         return 1;
 565                 }
 566                 bp += 4;
 567                 length -= 16;
 568         }
 569         return 0;
 570 }
 571
 572 void __init find_intel_smp (void)
 573 {
 574         unsigned int address;
 575
 576         /*
 577          * FIXME: Linux assumes you have 640K of base ram..
 578          * this continues the error...
 579          *
 580          * 1) Scan the bottom 1K for a signature
 581          * 2) Scan the top 1K of base RAM
 582          * 3) Scan the 64K of bios
 583          */
 584         if (smp_scan_config(0x0,0x400) ||
 585                 smp_scan_config(639*0x400,0x400) ||
 586                         smp_scan_config(0xF0000,0x10000))
 587                 return;
 588         /*
 589          * If it is an SMP machine we should know now, unless the
 590          * configuration is in an EISA/MCA bus machine with an
 591          * extended bios data area.
 592          *
 593          * there is a real-mode segmented pointer pointing to the
 594          * 4K EBDA area at 0x40E, calculate and scan it here.
 595          *
 596          * NOTE! There are Linux loaders that will corrupt the EBDA
 597          * area, and as such this kind of SMP config may be less
 598          * trustworthy, simply because the SMP table may have been
 599          * stomped on during early boot. These loaders are buggy and
 600          * should be fixed.
 601          */
 602
 603         address = *(unsigned short *)phys_to_virt(0x40E);
 604         address <<= 4;
 605         smp_scan_config(address, 0x1000);
 606         if (smp_found_config)
 607                 printk(KERN_WARNING "WARNING: MP table in the EBDA can be UNSAFE, contact linux-smp@vger.kernel.org if you experience SMP problems!\n");
 608 }
 609
 610 #else
 611
 612 /*
 613  * The Visual Workstation is Intel MP compliant in the hardware
 614  * sense, but it doesnt have a BIOS(-configuration table).
 615  * No problem for Linux.
 616  */
 617 void __init find_visws_smp(void)
 618 {
 619         smp_found_config = 1;
 620
 621         phys_cpu_present_map |= 2; /* or in id 1 */
 622         apic_version[1] |= 0x10; /* integrated APIC */
 623         apic_version[0] |= 0x10;
 624
 625         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
 626 }
 627
 628 #endif
 629
 630 /*
 631  * - Intel MP Configuration Table
 632  * - or SGI Visual Workstation configuration
 633  */
 634 void __init find_smp_config (void)
 635 {
 636 #ifdef CONFIG_X86_IO_APIC
 637         find_intel_smp();
 638 #endif
 639 #ifdef CONFIG_VISWS
 640         find_visws_smp();
 641 #endif
 642 }
 643