arch/i386/kernel/i8259.c

   1 #include <linux/config.h>
   2 #include <linux/ptrace.h>
   3 #include <linux/errno.h>
   4 #include <linux/signal.h>
   5 #include <linux/sched.h>
   6 #include <linux/ioport.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/timex.h>
   9 #include <linux/malloc.h>
  10 #include <linux/random.h>
  11 #include <linux/smp_lock.h>
  12 #include <linux/init.h>
  13 #include <linux/kernel_stat.h>
  14
  15 #include <asm/system.h>
  16 #include <asm/io.h>
  17 #include <asm/irq.h>
  18 #include <asm/bitops.h>
  19 #include <asm/pgtable.h>
  20 #include <asm/delay.h>
  21 #include <asm/desc.h>
  22
  23 #include <linux/irq.h>
  24
  25 /*
  26  * Common place to define all x86 IRQ vectors
  27  *
  28  * This builds up the IRQ handler stubs using some ugly macros in irq.h
  29  *
  30  * These macros create the low-level assembly IRQ routines that save
  31  * register context and call do_IRQ(). do_IRQ() then does all the
  32  * operations that are needed to keep the AT (or SMP IOAPIC)
  33  * interrupt-controller happy.
  34  */
  35
  36 BUILD_COMMON_IRQ()
  37
  38 #define BI(x,y) \
  39         BUILD_IRQ(x##y)
  40
  41 #define BUILD_16_IRQS(x) \
  42         BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
  43         BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
  44         BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
  45         BI(x,c) BI(x,d) BI(x,e) BI(x,f)
  46
  47 /*
  48  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  49  * (these are usually mapped to vectors 0x20-0x2f)
  50  */
  51 BUILD_16_IRQS(0x0)
  52
  53 #ifdef CONFIG_X86_IO_APIC
  54 /*
  55  * The IO-APIC gives us many more interrupt sources. Most of these
  56  * are unused but an SMP system is supposed to have enough memory ...
  57  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  58  * across the spectrum, so we really want to be prepared to get all
  59  * of these. Plus, more powerful systems might have more than 64
  60  * IO-APIC registers.
  61  *
  62  * (these are usually mapped into the 0x30-0xff vector range)
  63  */
  64                    BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
  65 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
  66 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
  67 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd)
  68 #endif
  69
  70 #undef BUILD_16_IRQS
  71 #undef BI
  72
  73
  74 /*
  75  * The following vectors are part of the Linux architecture, there
  76  * is no hardware IRQ pin equivalent for them, they are triggered
  77  * through the ICC by us (IPIs)
  78  */
  79 #ifdef CONFIG_SMP
  80 BUILD_SMP_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR)
  81 BUILD_SMP_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
  82 BUILD_SMP_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
  83 #endif
  84
  85 /*
  86  * every pentium local APIC has two 'local interrupts', with a
  87  * soft-definable vector attached to both interrupts, one of
  88  * which is a timer interrupt, the other one is error counter
  89  * overflow. Linux uses the local APIC timer interrupt to get
  90  * a much simpler SMP time architecture:
  91  */
  92 #ifdef CONFIG_X86_LOCAL_APIC
  93 BUILD_SMP_TIMER_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR)
  94 BUILD_SMP_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR)
  95 BUILD_SMP_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
  96 #endif
  97
  98 #define IRQ(x,y) \
  99         IRQ##x##y##_interrupt
 100
 101 #define IRQLIST_16(x) \
 102         IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
 103         IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
 104         IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
 105         IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
 106
 107 void (*interrupt[NR_IRQS])(void) = {
 108         IRQLIST_16(0x0),
 109
 110 #ifdef CONFIG_X86_IO_APIC
 111                          IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
 112         IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
 113         IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
 114         IRQLIST_16(0xc), IRQLIST_16(0xd)
 115 #endif
 116 };
 117
 118 #undef IRQ
 119 #undef IRQLIST_16
 120
 121 /*
 122  * This is the 'legacy' 8259A Programmable Interrupt Controller,
 123  * present in the majority of PC/AT boxes.
 124  * plus some generic x86 specific things if generic specifics makes
 125  * any sense at all.
 126  * this file should become arch/i386/kernel/irq.c when the old irq.c
 127  * moves to arch independent land
 128  */
 129
 130 spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
 131
 132 static void end_8259A_irq (unsigned int irq)
 133 {
 134         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 135                 enable_8259A_irq(irq);
 136 }
 137
 138 #define shutdown_8259A_irq      disable_8259A_irq
 139
 140 void mask_and_ack_8259A(unsigned int);
 141
 142 static unsigned int startup_8259A_irq(unsigned int irq)
 143 {
 144         enable_8259A_irq(irq);
 145         return 0; /* never anything pending */
 146 }
 147
 148 static struct hw_interrupt_type i8259A_irq_type = {
 149         "XT-PIC",
 150         startup_8259A_irq,
 151         shutdown_8259A_irq,
 152         enable_8259A_irq,
 153         disable_8259A_irq,
 154         mask_and_ack_8259A,
 155         end_8259A_irq,
 156         NULL
 157 };
 158
 159 /*
 160  * 8259A PIC functions to handle ISA devices:
 161  */
 162
 163 /*
 164  * This contains the irq mask for both 8259A irq controllers,
 165  */
 166 static unsigned int cached_irq_mask = 0xffff;
 167
 168 #define __byte(x,y)     (((unsigned char *)&(y))[x])
 169 #define cached_21       (__byte(0,cached_irq_mask))
 170 #define cached_A1       (__byte(1,cached_irq_mask))
 171
 172 /*
 173  * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 174  * boards the timer interrupt is not really connected to any IO-APIC pin,
 175  * it's fed to the master 8259A's IR0 line only.
 176  *
 177  * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 178  * this 'mixed mode' IRQ handling costs nothing because it's only used
 179  * at IRQ setup time.
 180  */
 181 unsigned long io_apic_irqs;
 182
 183 void disable_8259A_irq(unsigned int irq)
 184 {
 185         unsigned int mask = 1 << irq;
 186         unsigned long flags;
 187
 188         spin_lock_irqsave(&i8259A_lock, flags);
 189         cached_irq_mask |= mask;
 190         if (irq & 8)
 191                 outb(cached_A1,0xA1);
 192         else
 193                 outb(cached_21,0x21);
 194         spin_unlock_irqrestore(&i8259A_lock, flags);
 195 }
 196
 197 void enable_8259A_irq(unsigned int irq)
 198 {
 199         unsigned int mask = ~(1 << irq);
 200         unsigned long flags;
 201
 202         spin_lock_irqsave(&i8259A_lock, flags);
 203         cached_irq_mask &= mask;
 204         if (irq & 8)
 205                 outb(cached_A1,0xA1);
 206         else
 207                 outb(cached_21,0x21);
 208         spin_unlock_irqrestore(&i8259A_lock, flags);
 209 }
 210
 211 int i8259A_irq_pending(unsigned int irq)
 212 {
 213         unsigned int mask = 1<<irq;
 214         unsigned long flags;
 215         int ret;
 216
 217         spin_lock_irqsave(&i8259A_lock, flags);
 218         if (irq < 8)
 219                 ret = inb(0x20) & mask;
 220         else
 221                 ret = inb(0xA0) & (mask >> 8);
 222         spin_unlock_irqrestore(&i8259A_lock, flags);
 223
 224         return ret;
 225 }
 226
 227 void make_8259A_irq(unsigned int irq)
 228 {
 229         disable_irq_nosync(irq);
 230         io_apic_irqs &= ~(1<<irq);
 231         irq_desc[irq].handler = &i8259A_irq_type;
 232         enable_irq(irq);
 233 }
 234
 235 /*
 236  * This function assumes to be called rarely. Switching between
 237  * 8259A registers is slow.
 238  * This has to be protected by the irq controller spinlock
 239  * before being called.
 240  */
 241 static inline int i8259A_irq_real(unsigned int irq)
 242 {
 243         int value;
 244         int irqmask = 1<<irq;
 245
 246         if (irq < 8) {
 247                 outb(0x0B,0x20);                /* ISR register */
 248                 value = inb(0x20) & irqmask;
 249                 outb(0x0A,0x20);                /* back to the IRR register */
 250                 return value;
 251         }
 252         outb(0x0B,0xA0);                /* ISR register */
 253         value = inb(0xA0) & (irqmask >> 8);
 254         outb(0x0A,0xA0);                /* back to the IRR register */
 255         return value;
 256 }
 257
 258 /*
 259  * Careful! The 8259A is a fragile beast, it pretty
 260  * much _has_ to be done exactly like this (mask it
 261  * first, _then_ send the EOI, and the order of EOI
 262  * to the two 8259s is important!
 263  */
 264 void mask_and_ack_8259A(unsigned int irq)
 265 {
 266         unsigned int irqmask = 1 << irq;
 267         unsigned long flags;
 268
 269         spin_lock_irqsave(&i8259A_lock, flags);
 270         /*
 271          * Lightweight spurious IRQ detection. We do not want
 272          * to overdo spurious IRQ handling - it's usually a sign
 273          * of hardware problems, so we only do the checks we can
 274          * do without slowing down good hardware unnecesserily.
 275          *
 276          * Note that IRQ7 and IRQ15 (the two spurious IRQs
 277          * usually resulting from the 8259A-1|2 PICs) occur
 278          * even if the IRQ is masked in the 8259A. Thus we
 279          * can check spurious 8259A IRQs without doing the
 280          * quite slow i8259A_irq_real() call for every IRQ.
 281          * This does not cover 100% of spurious interrupts,
 282          * but should be enough to warn the user that there
 283          * is something bad going on ...
 284          */
 285         if (cached_irq_mask & irqmask)
 286                 goto spurious_8259A_irq;
 287         cached_irq_mask |= irqmask;
 288
 289 handle_real_irq:
 290         if (irq & 8) {
 291                 inb(0xA1);              /* DUMMY - (do we need this?) */
 292                 outb(cached_A1,0xA1);
 293                 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
 294                 outb(0x62,0x20);        /* 'Specific EOI' to master-IRQ2 */
 295         } else {
 296                 inb(0x21);              /* DUMMY - (do we need this?) */
 297                 outb(cached_21,0x21);
 298                 outb(0x60+irq,0x20);    /* 'Specific EOI' to master */
 299         }
 300         spin_unlock_irqrestore(&i8259A_lock, flags);
 301         return;
 302
 303 spurious_8259A_irq:
 304         /*
 305          * this is the slow path - should happen rarely.
 306          */
 307         if (i8259A_irq_real(irq))
 308                 /*
 309                  * oops, the IRQ _is_ in service according to the
 310                  * 8259A - not spurious, go handle it.
 311                  */
 312                 goto handle_real_irq;
 313
 314         {
 315                 static int spurious_irq_mask;
 316                 /*
 317                  * At this point we can be sure the IRQ is spurious,
 318                  * lets ACK and report it. [once per IRQ]
 319                  */
 320                 if (!(spurious_irq_mask & irqmask)) {
 321                         printk("spurious 8259A interrupt: IRQ%d.\n", irq);
 322                         spurious_irq_mask |= irqmask;
 323                 }
 324                 irq_err_count++;
 325                 /*
 326                  * Theoretically we do not have to handle this IRQ,
 327                  * but in Linux this does not cause problems and is
 328                  * simpler for us.
 329                  */
 330                 goto handle_real_irq;
 331         }
 332 }
 333
 334 void __init init_8259A(int auto_eoi)
 335 {
 336         unsigned long flags;
 337
 338         spin_lock_irqsave(&i8259A_lock, flags);
 339
 340         outb(0xff, 0x21);       /* mask all of 8259A-1 */
 341         outb(0xff, 0xA1);       /* mask all of 8259A-2 */
 342
 343         /*
 344          * outb_p - this has to work on a wide range of PC hardware.
 345          */
 346         outb_p(0x11, 0x20);     /* ICW1: select 8259A-1 init */
 347         outb_p(0x20 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
 348         outb_p(0x04, 0x21);     /* 8259A-1 (the master) has a slave on IR2 */
 349         if (auto_eoi)
 350                 outb_p(0x03, 0x21);     /* master does Auto EOI */
 351         else
 352                 outb_p(0x01, 0x21);     /* master expects normal EOI */
 353
 354         outb_p(0x11, 0xA0);     /* ICW1: select 8259A-2 init */
 355         outb_p(0x20 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
 356         outb_p(0x02, 0xA1);     /* 8259A-2 is a slave on master's IR2 */
 357         outb_p(0x01, 0xA1);     /* (slave's support for AEOI in flat mode
 358                                     is to be investigated) */
 359
 360         if (auto_eoi)
 361                 /*
 362                  * in AEOI mode we just have to mask the interrupt
 363                  * when acking.
 364                  */
 365                 i8259A_irq_type.ack = disable_8259A_irq;
 366         else
 367                 i8259A_irq_type.ack = mask_and_ack_8259A;
 368
 369         udelay(100);            /* wait for 8259A to initialize */
 370
 371         outb(cached_21, 0x21);  /* restore master IRQ mask */
 372         outb(cached_A1, 0xA1);  /* restore slave IRQ mask */
 373
 374         spin_unlock_irqrestore(&i8259A_lock, flags);
 375 }
 376
 377 /*
 378  * Note that on a 486, we don't want to do a SIGFPE on an irq13
 379  * as the irq is unreliable, and exception 16 works correctly
 380  * (ie as explained in the intel literature). On a 386, you
 381  * can't use exception 16 due to bad IBM design, so we have to
 382  * rely on the less exact irq13.
 383  *
 384  * Careful.. Not only is IRQ13 unreliable, but it is also
 385  * leads to races. IBM designers who came up with it should
 386  * be shot.
 387  */
 388
 389 static void math_error_irq(int cpl, void *dev_id, struct pt_regs *regs)
 390 {
 391         extern void math_error(void *);
 392         outb(0,0xF0);
 393         if (ignore_irq13 || !boot_cpu_data.hard_math)
 394                 return;
 395         math_error((void *)regs->eip);
 396 }
 397
 398 /*
 399  * New motherboards sometimes make IRQ 13 be a PCI interrupt,
 400  * so allow interrupt sharing.
 401  */
 402 static struct irqaction irq13 = { math_error_irq, 0, 0, "fpu", NULL, NULL };
 403
 404 /*
 405  * IRQ2 is cascade interrupt to second interrupt controller
 406  */
 407
 408 #ifndef CONFIG_VISWS
 409 static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL};
 410 #endif
 411
 412
 413 void __init init_ISA_irqs (void)
 414 {
 415         int i;
 416
 417         init_8259A(0);
 418
 419         for (i = 0; i < NR_IRQS; i++) {
 420                 irq_desc[i].status = IRQ_DISABLED;
 421                 irq_desc[i].action = 0;
 422                 irq_desc[i].depth = 1;
 423
 424                 if (i < 16) {
 425                         /*
 426                          * 16 old-style INTA-cycle interrupts:
 427                          */
 428                         irq_desc[i].handler = &i8259A_irq_type;
 429                 } else {
 430                         /*
 431                          * 'high' PCI IRQs filled in on demand
 432                          */
 433                         irq_desc[i].handler = &no_irq_type;
 434                 }
 435         }
 436 }
 437
 438 void __init init_IRQ(void)
 439 {
 440         int i;
 441
 442 #ifndef CONFIG_X86_VISWS_APIC
 443         init_ISA_irqs();
 444 #else
 445         init_VISWS_APIC_irqs();
 446 #endif
 447         /*
 448          * Cover the whole vector space, no vector can escape
 449          * us. (some of these will be overridden and become
 450          * 'special' SMP interrupts)
 451          */
 452         for (i = 0; i < NR_IRQS; i++) {
 453                 int vector = FIRST_EXTERNAL_VECTOR + i;
 454                 if (vector != SYSCALL_VECTOR)
 455                         set_intr_gate(vector, interrupt[i]);
 456         }
 457
 458 #ifdef CONFIG_SMP
 459         /*
 460          * IRQ0 must be given a fixed assignment and initialized,
 461          * because it's used before the IO-APIC is set up.
 462          */
 463         set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
 464
 465         /*
 466          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 467          * IPI, driven by wakeup.
 468          */
 469         set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 470
 471         /* IPI for invalidation */
 472         set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
 473
 474         /* IPI for generic function call */
 475         set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 476 #endif
 477
 478 #ifdef CONFIG_X86_LOCAL_APIC
 479         /* self generated IPI for local APIC timer */
 480         set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 481
 482         /* IPI vectors for APIC spurious and error interrupts */
 483         set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 484         set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 485 #endif
 486
 487         /*
 488          * Set the clock to HZ Hz, we already have a valid
 489          * vector now:
 490          */
 491         outb_p(0x34,0x43);              /* binary, mode 2, LSB/MSB, ch 0 */
 492         outb_p(LATCH & 0xff , 0x40);    /* LSB */
 493         outb(LATCH >> 8 , 0x40);        /* MSB */
 494
 495 #ifndef CONFIG_VISWS
 496         setup_irq(2, &irq2);
 497 #endif
 498
 499         /*
 500          * External FPU? Set up irq13 if so, for
 501          * original braindamaged IBM FERR coupling.
 502          */
 503         if (boot_cpu_data.hard_math && !cpu_has_fpu)
 504                 setup_irq(13, &irq13);
 505 }