include/asm-ppc/processor.h

   1 #ifdef __KERNEL__
   2 #ifndef __ASM_PPC_PROCESSOR_H
   3 #define __ASM_PPC_PROCESSOR_H
   4
   5 /*
   6  * Default implementation of macro that returns current
   7  * instruction pointer ("program counter").
   8  */
   9 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  10
  11 #include <linux/config.h>
  12
  13 #include <asm/ptrace.h>
  14 #include <asm/types.h>
  15
  16 /* Machine State Register (MSR) Fields */
  17
  18 #ifdef CONFIG_PPC64BRIDGE
  19 #define MSR_SF          (1<<63)
  20 #define MSR_ISF         (1<<61)
  21 #endif /* CONFIG_PPC64BRIDGE */
  22 #define MSR_VEC         (1<<25)         /* Enable AltiVec */
  23 #define MSR_POW         (1<<18)         /* Enable Power Management */
  24 #define MSR_WE          (1<<18)         /* Wait State Enable */
  25 #define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
  26 #define MSR_CE          (1<<17)         /* Critical Interrupt Enable */
  27 #define MSR_ILE         (1<<16)         /* Interrupt Little Endian */
  28 #define MSR_EE          (1<<15)         /* External Interrupt Enable */
  29 #define MSR_PR          (1<<14)         /* Problem State / Privilege Level */
  30 #define MSR_FP          (1<<13)         /* Floating Point enable */
  31 #define MSR_ME          (1<<12)         /* Machine Check Enable */
  32 #define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
  33 #define MSR_SE          (1<<10)         /* Single Step */
  34 #define MSR_BE          (1<<9)          /* Branch Trace */
  35 #define MSR_DE          (1<<9)          /* Debug Exception Enable */
  36 #define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
  37 #define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
  38 #define MSR_IR          (1<<5)          /* Instruction Relocate */
  39 #define MSR_DR          (1<<4)          /* Data Relocate */
  40 #define MSR_PE          (1<<3)          /* Protection Enable */
  41 #define MSR_PX          (1<<2)          /* Protection Exclusive Mode */
  42 #define MSR_RI          (1<<1)          /* Recoverable Exception */
  43 #define MSR_LE          (1<<0)          /* Little Endian */
  44
  45 #ifdef CONFIG_APUS_FAST_EXCEPT
  46 #define MSR_            MSR_ME|MSR_IP|MSR_RI
  47 #else
  48 #define MSR_            MSR_ME|MSR_RI
  49 #endif
  50 #define MSR_KERNEL      MSR_|MSR_IR|MSR_DR
  51 #define MSR_USER        MSR_KERNEL|MSR_PR|MSR_EE
  52
  53 /* Floating Point Status and Control Register (FPSCR) Fields */
  54
  55 #define FPSCR_FX        0x80000000      /* FPU exception summary */
  56 #define FPSCR_FEX       0x40000000      /* FPU enabled exception summary */
  57 #define FPSCR_VX        0x20000000      /* Invalid operation summary */
  58 #define FPSCR_OX        0x10000000      /* Overflow exception summary */
  59 #define FPSCR_UX        0x08000000      /* Underflow exception summary */
  60 #define FPSCR_ZX        0x04000000      /* Zero-devide exception summary */
  61 #define FPSCR_XX        0x02000000      /* Inexact exception summary */
  62 #define FPSCR_VXSNAN    0x01000000      /* Invalid op for SNaN */
  63 #define FPSCR_VXISI     0x00800000      /* Invalid op for Inv - Inv */
  64 #define FPSCR_VXIDI     0x00400000      /* Invalid op for Inv / Inv */
  65 #define FPSCR_VXZDZ     0x00200000      /* Invalid op for Zero / Zero */
  66 #define FPSCR_VXIMZ     0x00100000      /* Invalid op for Inv * Zero */
  67 #define FPSCR_VXVC      0x00080000      /* Invalid op for Compare */
  68 #define FPSCR_FR        0x00040000      /* Fraction rounded */
  69 #define FPSCR_FI        0x00020000      /* Fraction inexact */
  70 #define FPSCR_FPRF      0x0001f000      /* FPU Result Flags */
  71 #define FPSCR_FPCC      0x0000f000      /* FPU Condition Codes */
  72 #define FPSCR_VXSOFT    0x00000400      /* Invalid op for software request */
  73 #define FPSCR_VXSQRT    0x00000200      /* Invalid op for square root */
  74 #define FPSCR_VXCVI     0x00000100      /* Invalid op for integer convert */
  75 #define FPSCR_VE        0x00000080      /* Invalid op exception enable */
  76 #define FPSCR_OE        0x00000040      /* IEEE overflow exception enable */
  77 #define FPSCR_UE        0x00000020      /* IEEE underflow exception enable */
  78 #define FPSCR_ZE        0x00000010      /* IEEE zero divide exception enable */
  79 #define FPSCR_XE        0x00000008      /* FP inexact exception enable */
  80 #define FPSCR_NI        0x00000004      /* FPU non IEEE-Mode */
  81 #define FPSCR_RN        0x00000003      /* FPU rounding control */
  82
  83 /* Special Purpose Registers (SPRNs)*/
  84
  85 #define SPRN_CDBCR      0x3D7   /* Cache Debug Control Register */
  86 #define SPRN_CTR        0x009   /* Count Register */
  87 #define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
  88 #define SPRN_DAC1       0x3F6   /* Data Address Compare 1 */
  89 #define SPRN_DAC2       0x3F7   /* Data Address Compare 2 */
  90 #define SPRN_DAR        0x013   /* Data Address Register */
  91 #define SPRN_DBAT0L     0x219   /* Data BAT 0 Lower Register */
  92 #define SPRN_DBAT0U     0x218   /* Data BAT 0 Upper Register */
  93 #define SPRN_DBAT1L     0x21B   /* Data BAT 1 Lower Register */
  94 #define SPRN_DBAT1U     0x21A   /* Data BAT 1 Upper Register */
  95 #define SPRN_DBAT2L     0x21D   /* Data BAT 2 Lower Register */
  96 #define SPRN_DBAT2U     0x21C   /* Data BAT 2 Upper Register */
  97 #define SPRN_DBAT3L     0x21F   /* Data BAT 3 Lower Register */
  98 #define SPRN_DBAT3U     0x21E   /* Data BAT 3 Upper Register */
  99 #define SPRN_DBCR       0x3F2   /* Debug Control Regsiter */
 100 #define   DBCR_EDM      0x80000000
 101 #define   DBCR_IDM      0x40000000
 102 #define   DBCR_RST(x)   (((x) & 0x3) << 28)
 103 #define     DBCR_RST_NONE               0
 104 #define     DBCR_RST_CORE               1
 105 #define     DBCR_RST_CHIP               2
 106 #define     DBCR_RST_SYSTEM             3
 107 #define   DBCR_IC       0x08000000      /* Instruction Completion Debug Evnt */
 108 #define   DBCR_BT       0x04000000      /* Branch Taken Debug Event */
 109 #define   DBCR_EDE      0x02000000      /* Exception Debug Event */
 110 #define   DBCR_TDE      0x01000000      /* TRAP Debug Event */
 111 #define   DBCR_FER      0x00F80000      /* First Events Remaining Mask */
 112 #define   DBCR_FT       0x00040000      /* Freeze Timers on Debug Event */
 113 #define   DBCR_IA1      0x00020000      /* Instr. Addr. Compare 1 Enable */
 114 #define   DBCR_IA2      0x00010000      /* Instr. Addr. Compare 2 Enable */
 115 #define   DBCR_D1R      0x00008000      /* Data Addr. Compare 1 Read Enable */
 116 #define   DBCR_D1W      0x00004000      /* Data Addr. Compare 1 Write Enable */
 117 #define   DBCR_D1S(x)   (((x) & 0x3) << 12)     /* Data Adrr. Compare 1 Size */
 118 #define     DAC_BYTE    0
 119 #define     DAC_HALF    1
 120 #define     DAC_WORD    2
 121 #define     DAC_QUAD    3
 122 #define   DBCR_D2R      0x00000800      /* Data Addr. Compare 2 Read Enable */
 123 #define   DBCR_D2W      0x00000400      /* Data Addr. Compare 2 Write Enable */
 124 #define   DBCR_D2S(x)   (((x) & 0x3) << 8)      /* Data Addr. Compare 2 Size */
 125 #define   DBCR_SBT      0x00000040      /* Second Branch Taken Debug Event */
 126 #define   DBCR_SED      0x00000020      /* Second Exception Debug Event */
 127 #define   DBCR_STD      0x00000010      /* Second Trap Debug Event */
 128 #define   DBCR_SIA      0x00000008      /* Second IAC Enable */
 129 #define   DBCR_SDA      0x00000004      /* Second DAC Enable */
 130 #define   DBCR_JOI      0x00000002      /* JTAG Serial Outbound Int. Enable */
 131 #define   DBCR_JII      0x00000001      /* JTAG Serial Inbound Int. Enable */
 132 #define SPRN_DBCR0      0x3F2   /* Debug Control Register 0 */
 133 #define SPRN_DBCR1      0x3BD   /* Debug Control Register 1 */
 134 #define SPRN_DBSR       0x3F0   /* Debug Status Register */
 135 #define SPRN_DCCR       0x3FA   /* Data Cache Cacheability Register */
 136 #define   DCCR_NOCACHE          0       /* Noncacheable */
 137 #define   DCCR_CACHE            1       /* Cacheable */
 138 #define SPRN_DCMP       0x3D1   /* Data TLB Compare Register */
 139 #define SPRN_DCWR       0x3BA   /* Data Cache Write-thru Register */
 140 #define   DCWR_COPY             0       /* Copy-back */
 141 #define   DCWR_WRITE            1       /* Write-through */
 142 #define SPRN_DEAR       0x3D5   /* Data Error Address Register */
 143 #define SPRN_DEC        0x016   /* Decrement Register */
 144 #define SPRN_DMISS      0x3D0   /* Data TLB Miss Register */
 145 #define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
 146 #define SPRN_EAR        0x11A   /* External Address Register */
 147 #define SPRN_ESR        0x3D4   /* Exception Syndrome Register */
 148 #define   ESR_IMCP      0x80000000      /* Instr. Machine Check - Protection */
 149 #define   ESR_IMCN      0x40000000      /* Instr. Machine Check - Non-config */
 150 #define   ESR_IMCB      0x20000000      /* Instr. Machine Check - Bus error */
 151 #define   ESR_IMCT      0x10000000      /* Instr. Machine Check - Timeout */
 152 #define   ESR_PIL       0x08000000      /* Program Exception - Illegal */
 153 #define   ESR_PPR       0x04000000      /* Program Exception - Priveleged */
 154 #define   ESR_PTR       0x02000000      /* Program Exception - Trap */
 155 #define   ESR_DST       0x00800000      /* Storage Exception - Data miss */
 156 #define   ESR_DIZ       0x00400000      /* Storage Exception - Zone fault */
 157 #define SPRN_EVPR       0x3D6   /* Exception Vector Prefix Register */
 158 #define SPRN_HASH1      0x3D2   /* Primary Hash Address Register */
 159 #define SPRN_HASH2      0x3D3   /* Secondary Hash Address Resgister */
 160 #define SPRN_HID0       0x3F0   /* Hardware Implementation Register 0 */
 161 #define   HID0_EMCP     (1<<31)         /* Enable Machine Check pin */
 162 #define   HID0_EBA      (1<<29)         /* Enable Bus Address Parity */
 163 #define   HID0_EBD      (1<<28)         /* Enable Bus Data Parity */
 164 #define   HID0_SBCLK    (1<<27)
 165 #define   HID0_EICE     (1<<26)
 166 #define   HID0_ECLK     (1<<25)
 167 #define   HID0_PAR      (1<<24)
 168 #define   HID0_DOZE     (1<<23)
 169 #define   HID0_NAP      (1<<22)
 170 #define   HID0_SLEEP    (1<<21)
 171 #define   HID0_DPM      (1<<20)
 172 #define   HID0_ICE      (1<<15)         /* Instruction Cache Enable */
 173 #define   HID0_DCE      (1<<14)         /* Data Cache Enable */
 174 #define   HID0_ILOCK    (1<<13)         /* Instruction Cache Lock */
 175 #define   HID0_DLOCK    (1<<12)         /* Data Cache Lock */
 176 #define   HID0_ICFI     (1<<11)         /* Instr. Cache Flash Invalidate */
 177 #define   HID0_DCI      (1<<10)         /* Data Cache Invalidate */
 178 #define   HID0_SPD      (1<<9)          /* Speculative disable */
 179 #define   HID0_SGE      (1<<7)          /* Store Gathering Enable */
 180 #define   HID0_SIED     (1<<7)          /* Serial Instr. Execution [Disable] */
 181 #define   HID0_BTIC     (1<<5)          /* Branch Target Instruction Cache Enable */
 182 #define   HID0_ABE      (1<<3)          /* Address Broadcast Enable */
 183 #define   HID0_BHTE     (1<<2)          /* Branch History Table Enable */
 184 #define   HID0_BTCD     (1<<1)          /* Branch target cache disable */
 185 #define SPRN_HID1       0x3F1   /* Hardware Implementation Register 1 */
 186 #define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
 187 #define SPRN_IAC1       0x3F4   /* Instruction Address Compare 1 */
 188 #define SPRN_IAC2       0x3F5   /* Instruction Address Compare 2 */
 189 #define SPRN_IBAT0L     0x211   /* Instruction BAT 0 Lower Register */
 190 #define SPRN_IBAT0U     0x210   /* Instruction BAT 0 Upper Register */
 191 #define SPRN_IBAT1L     0x213   /* Instruction BAT 1 Lower Register */
 192 #define SPRN_IBAT1U     0x212   /* Instruction BAT 1 Upper Register */
 193 #define SPRN_IBAT2L     0x215   /* Instruction BAT 2 Lower Register */
 194 #define SPRN_IBAT2U     0x214   /* Instruction BAT 2 Upper Register */
 195 #define SPRN_IBAT3L     0x217   /* Instruction BAT 3 Lower Register */
 196 #define SPRN_IBAT3U     0x216   /* Instruction BAT 3 Upper Register */
 197 #define SPRN_ICCR       0x3FB   /* Instruction Cache Cacheability Register */
 198 #define   ICCR_NOCACHE          0       /* Noncacheable */
 199 #define   ICCR_CACHE            1       /* Cacheable */
 200 #define SPRN_ICDBDR     0x3D3   /* Instruction Cache Debug Data Register */
 201 #define SPRN_ICMP       0x3D5   /* Instruction TLB Compare Register */
 202 #define SPRN_ICTC       0x3FB   /* Instruction Cache Throttling Control Reg */
 203 #define SPRN_IMISS      0x3D4   /* Instruction TLB Miss Register */
 204 #define SPRN_IMMR       0x27E   /* Internal Memory Map Register */
 205 #define SPRN_L2CR       0x3F9   /* Level 2 Cache Control Regsiter */
 206 #define SPRN_LR         0x008   /* Link Register */
 207 #define SPRN_MMCR0      0x3B8   /* Monitor Mode Control Register 0 */
 208 #define SPRN_MMCR1      0x3BC   /* Monitor Mode Control Register 1 */
 209 #define SPRN_PBL1       0x3FC   /* Protection Bound Lower 1 */
 210 #define SPRN_PBL2       0x3FE   /* Protection Bound Lower 2 */
 211 #define SPRN_PBU1       0x3FD   /* Protection Bound Upper 1 */
 212 #define SPRN_PBU2       0x3FF   /* Protection Bound Upper 2 */
 213 #define SPRN_PID        0x3B1   /* Process ID */
 214 #define SPRN_PIR        0x3FF   /* Processor Identification Register */
 215 #define SPRN_PIT        0x3DB   /* Programmable Interval Timer */
 216 #define SPRN_PMC1       0x3B9   /* Performance Counter Register 1 */
 217 #define SPRN_PMC2       0x3BA   /* Performance Counter Register 2 */
 218 #define SPRN_PMC3       0x3BD   /* Performance Counter Register 3 */
 219 #define SPRN_PMC4       0x3BE   /* Performance Counter Register 4 */
 220 #define SPRN_PVR        0x11F   /* Processor Version Register */
 221 #define SPRN_RPA        0x3D6   /* Required Physical Address Register */
 222 #define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
 223 #define SPRN_SDR1       0x019   /* MMU Hash Base Register */
 224 #define SPRN_SGR        0x3B9   /* Storage Guarded Register */
 225 #define   SGR_NORMAL            0
 226 #define   SGR_GUARDED           1
 227 #define SPRN_SIA        0x3BB   /* Sampled Instruction Address Register */
 228 #define SPRN_SPRG0      0x110   /* Special Purpose Register General 0 */
 229 #define SPRN_SPRG1      0x111   /* Special Purpose Register General 1 */
 230 #define SPRN_SPRG2      0x112   /* Special Purpose Register General 2 */
 231 #define SPRN_SPRG3      0x113   /* Special Purpose Register General 3 */
 232 #define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
 233 #define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
 234 #define SPRN_SRR2       0x3DE   /* Save/Restore Register 2 */
 235 #define SPRN_SRR3       0x3DF   /* Save/Restore Register 3 */
 236 #define SPRN_TBHI       0x3DC   /* Time Base High */
 237 #define SPRN_TBHU       0x3CC   /* Time Base High User-mode */
 238 #define SPRN_TBLO       0x3DD   /* Time Base Low */
 239 #define SPRN_TBLU       0x3CD   /* Time Base Low User-mode */
 240 #define SPRN_TBRL       0x10D   /* Time Base Read Lower Register */
 241 #define SPRN_TBRU       0x10C   /* Time Base Read Upper Register */
 242 #define SPRN_TBWL       0x11D   /* Time Base Write Lower Register */
 243 #define SPRN_TBWU       0x11C   /* Time Base Write Upper Register */
 244 #define SPRN_TCR        0x3DA   /* Timer Control Register */
 245 #define   TCR_WP(x)             (((x)&0x3)<<30) /* WDT Period */
 246 #define     WP_2_17             0               /* 2^17 clocks */
 247 #define     WP_2_21             1               /* 2^21 clocks */
 248 #define     WP_2_25             2               /* 2^25 clocks */
 249 #define     WP_2_29             3               /* 2^29 clocks */
 250 #define   TCR_WRC(x)            (((x)&0x3)<<28) /* WDT Reset Control */
 251 #define     WRC_NONE            0               /* No reset will occur */
 252 #define     WRC_CORE            1               /* Core reset will occur */
 253 #define     WRC_CHIP            2               /* Chip reset will occur */
 254 #define     WRC_SYSTEM          3               /* System reset will occur */
 255 #define   TCR_WIE               0x08000000      /* WDT Interrupt Enable */
 256 #define   TCR_PIE               0x04000000      /* PIT Interrupt Enable */
 257 #define   TCR_FP(x)             (((x)&0x3)<<24) /* FIT Period */
 258 #define     FP_2_9              0               /* 2^9 clocks */
 259 #define     FP_2_13             1               /* 2^13 clocks */
 260 #define     FP_2_17             2               /* 2^17 clocks */
 261 #define     FP_2_21             3               /* 2^21 clocks */
 262 #define   TCR_FIE               0x00800000      /* FIT Interrupt Enable */
 263 #define   TCR_ARE               0x00400000      /* Auto Reload Enable */
 264 #define SPRN_THRM1      0x3FC   /* Thermal Management Register 1 */
 265 #define   THRM1_TIN             (1<<0)
 266 #define   THRM1_TIV             (1<<1)
 267 #define   THRM1_THRES           (0x7f<<2)
 268 #define   THRM1_TID             (1<<29)
 269 #define   THRM1_TIE             (1<<30)
 270 #define   THRM1_V               (1<<31)
 271 #define SPRN_THRM2      0x3FD   /* Thermal Management Register 2 */
 272 #define SPRN_THRM3      0x3FE   /* Thermal Management Register 3 */
 273 #define   THRM3_E               (1<<31)
 274 #define SPRN_TSR        0x3D8   /* Timer Status Register */
 275 #define   TSR_ENW               0x80000000      /* Enable Next Watchdog */
 276 #define   TSR_WIS               0x40000000      /* WDT Interrupt Status */
 277 #define   TSR_WRS(x)            (((x)&0x3)<<28) /* WDT Reset Status */
 278 #define     WRS_NONE            0               /* No WDT reset occurred */
 279 #define     WRS_CORE            1               /* WDT forced core reset */
 280 #define     WRS_CHIP            2               /* WDT forced chip reset */
 281 #define     WRS_SYSTEM          3               /* WDT forced system reset */
 282 #define   TSR_PIS               0x08000000      /* PIT Interrupt Status */
 283 #define   TSR_FIS               0x04000000      /* FIT Interrupt Status */
 284 #define SPRN_UMMCR0     0x3A8   /* User Monitor Mode Control Register 0 */
 285 #define SPRN_UMMCR1     0x3AC   /* User Monitor Mode Control Register 0 */
 286 #define SPRN_UPMC1      0x3A9   /* User Performance Counter Register 1 */
 287 #define SPRN_UPMC2      0x3AA   /* User Performance Counter Register 2 */
 288 #define SPRN_UPMC3      0x3AD   /* User Performance Counter Register 3 */
 289 #define SPRN_UPMC4      0x3AE   /* User Performance Counter Register 4 */
 290 #define SPRN_USIA       0x3AB   /* User Sampled Instruction Address Register */
 291 #define SPRN_VRSAVE     0x100   /* Vector Register Save Register */
 292 #define SPRN_XER        0x001   /* Fixed Point Exception Register */
 293 #define SPRN_ZPR        0x3B0   /* Zone Protection Register */
 294
 295 /* Short-hand versions for a number of the above SPRNs */
 296
 297 #define CTR     SPRN_CTR        /* Counter Register */
 298 #define DAR     SPRN_DAR        /* Data Address Register */
 299 #define DABR    SPRN_DABR       /* Data Address Breakpoint Register */
 300 #define DBAT0L  SPRN_DBAT0L     /* Data BAT 0 Lower Register */
 301 #define DBAT0U  SPRN_DBAT0U     /* Data BAT 0 Upper Register */
 302 #define DBAT1L  SPRN_DBAT1L     /* Data BAT 1 Lower Register */
 303 #define DBAT1U  SPRN_DBAT1U     /* Data BAT 1 Upper Register */
 304 #define DBAT2L  SPRN_DBAT2L     /* Data BAT 2 Lower Register */
 305 #define DBAT2U  SPRN_DBAT2U     /* Data BAT 2 Upper Register */
 306 #define DBAT3L  SPRN_DBAT3L     /* Data BAT 3 Lower Register */
 307 #define DBAT3U  SPRN_DBAT3U     /* Data BAT 3 Upper Register */
 308 #define DCMP    SPRN_DCMP       /* Data TLB Compare Register */
 309 #define DEC     SPRN_DEC        /* Decrement Register */
 310 #define DMISS   SPRN_DMISS      /* Data TLB Miss Register */
 311 #define DSISR   SPRN_DSISR      /* Data Storage Interrupt Status Register */
 312 #define EAR     SPRN_EAR        /* External Address Register */
 313 #define HASH1   SPRN_HASH1      /* Primary Hash Address Register */
 314 #define HASH2   SPRN_HASH2      /* Secondary Hash Address Register */
 315 #define HID0    SPRN_HID0       /* Hardware Implementation Register 0 */
 316 #define HID1    SPRN_HID1       /* Hardware Implementation Register 1 */
 317 #define IABR    SPRN_IABR       /* Instruction Address Breakpoint Register */
 318 #define IBAT0L  SPRN_IBAT0L     /* Instruction BAT 0 Lower Register */
 319 #define IBAT0U  SPRN_IBAT0U     /* Instruction BAT 0 Upper Register */
 320 #define IBAT1L  SPRN_IBAT1L     /* Instruction BAT 1 Lower Register */
 321 #define IBAT1U  SPRN_IBAT1U     /* Instruction BAT 1 Upper Register */
 322 #define IBAT2L  SPRN_IBAT2L     /* Instruction BAT 2 Lower Register */
 323 #define IBAT2U  SPRN_IBAT2U     /* Instruction BAT 2 Upper Register */
 324 #define IBAT3L  SPRN_IBAT3L     /* Instruction BAT 3 Lower Register */
 325 #define IBAT3U  SPRN_IBAT3U     /* Instruction BAT 3 Upper Register */
 326 #define ICMP    SPRN_ICMP       /* Instruction TLB Compare Register */
 327 #define IMISS   SPRN_IMISS      /* Instruction TLB Miss Register */
 328 #define IMMR    SPRN_IMMR       /* PPC 860/821 Internal Memory Map Register */
 329 #define L2CR    SPRN_L2CR       /* PPC 750 L2 control register */
 330 #define LR      SPRN_LR
 331 #define PVR     SPRN_PVR        /* Processor Version */
 332 #define RPA     SPRN_RPA        /* Required Physical Address Register */
 333 #define SDR1    SPRN_SDR1       /* MMU hash base register */
 334 #define SPR0    SPRN_SPRG0      /* Supervisor Private Registers */
 335 #define SPR1    SPRN_SPRG1
 336 #define SPR2    SPRN_SPRG2
 337 #define SPR3    SPRN_SPRG3
 338 #define SPRG0   SPRN_SPRG0
 339 #define SPRG1   SPRN_SPRG1
 340 #define SPRG2   SPRN_SPRG2
 341 #define SPRG3   SPRN_SPRG3
 342 #define SRR0    SPRN_SRR0       /* Save and Restore Register 0 */
 343 #define SRR1    SPRN_SRR1       /* Save and Restore Register 1 */
 344 #define TBRL    SPRN_TBRL       /* Time Base Read Lower Register */
 345 #define TBRU    SPRN_TBRU       /* Time Base Read Upper Register */
 346 #define TBWL    SPRN_TBWL       /* Time Base Write Lower Register */
 347 #define TBWU    SPRN_TBWU       /* Time Base Write Upper Register */
 348 #define ICTC    1019
 349 #define THRM1   SPRN_THRM1      /* Thermal Management Register 1 */
 350 #define THRM2   SPRN_THRM2      /* Thermal Management Register 2 */
 351 #define THRM3   SPRN_THRM3      /* Thermal Management Register 3 */
 352 #define XER     SPRN_XER
 353
 354
 355 /* Device Control Registers */
 356
 357 #define DCRN_BEAR       0x090   /* Bus Error Address Register */
 358 #define DCRN_BESR       0x091   /* Bus Error Syndrome Register */
 359 #define   BESR_DSES     0x80000000      /* Data-Side Error Status */
 360 #define   BESR_DMES     0x40000000      /* DMA Error Status */
 361 #define   BESR_RWS      0x20000000      /* Read/Write Status */
 362 #define   BESR_ETMASK   0x1C000000      /* Error Type */
 363 #define     ET_PROT     0
 364 #define     ET_PARITY   1
 365 #define     ET_NCFG     2
 366 #define     ET_BUSERR   4
 367 #define     ET_BUSTO    6
 368 #define DCRN_DMACC0     0x0C4   /* DMA Chained Count Register 0 */
 369 #define DCRN_DMACC1     0x0CC   /* DMA Chained Count Register 1 */
 370 #define DCRN_DMACC2     0x0D4   /* DMA Chained Count Register 2 */
 371 #define DCRN_DMACC3     0x0DC    /* DMA Chained Count Register 3 */
 372 #define DCRN_DMACR0     0x0C0    /* DMA Channel Control Register 0 */
 373 #define DCRN_DMACR1     0x0C8    /* DMA Channel Control Register 1 */
 374 #define DCRN_DMACR2     0x0D0    /* DMA Channel Control Register 2 */
 375 #define DCRN_DMACR3     0x0D8    /* DMA Channel Control Register 3 */
 376 #define DCRN_DMACT0     0x0C1    /* DMA Count Register 0 */
 377 #define DCRN_DMACT1     0x0C9    /* DMA Count Register 1 */
 378 #define DCRN_DMACT2     0x0D1    /* DMA Count Register 2 */
 379 #define DCRN_DMACT3     0x0D9    /* DMA Count Register 3 */
 380 #define DCRN_DMADA0     0x0C2    /* DMA Destination Address Register 0 */
 381 #define DCRN_DMADA1     0x0CA    /* DMA Destination Address Register 1 */
 382 #define DCRN_DMADA2     0x0D2    /* DMA Destination Address Register 2 */
 383 #define DCRN_DMADA3     0x0DA    /* DMA Destination Address Register 3 */
 384 #define DCRN_DMASA0     0x0C3    /* DMA Source Address Register 0 */
 385 #define DCRN_DMASA1     0x0CB    /* DMA Source Address Register 1 */
 386 #define DCRN_DMASA2     0x0D3    /* DMA Source Address Register 2 */
 387 #define DCRN_DMASA3     0x0DB    /* DMA Source Address Register 3 */
 388 #define DCRN_DMASR      0x0E0    /* DMA Status Register */
 389 #define DCRN_EXIER      0x042    /* External Interrupt Enable Register */
 390 #define   EXIER_CIE     0x80000000      /* Critical Interrupt Enable */
 391 #define   EXIER_SRIE    0x08000000      /* Serial Port Rx Int. Enable */
 392 #define   EXIER_STIE    0x04000000      /* Serial Port Tx Int. Enable */
 393 #define   EXIER_JRIE    0x02000000      /* JTAG Serial Port Rx Int. Enable */
 394 #define   EXIER_JTIE    0x01000000      /* JTAG Serial Port Tx Int. Enable */
 395 #define   EXIER_D0IE    0x00800000      /* DMA Channel 0 Interrupt Enable */
 396 #define   EXIER_D1IE    0x00400000      /* DMA Channel 1 Interrupt Enable */
 397 #define   EXIER_D2IE    0x00200000      /* DMA Channel 2 Interrupt Enable */
 398 #define   EXIER_D3IE    0x00100000      /* DMA Channel 3 Interrupt Enable */
 399 #define   EXIER_E0IE    0x00000010      /* External Interrupt 0 Enable */
 400 #define   EXIER_E1IE    0x00000008      /* External Interrupt 1 Enable */
 401 #define   EXIER_E2IE    0x00000004      /* External Interrupt 2 Enable */
 402 #define   EXIER_E3IE    0x00000002      /* External Interrupt 3 Enable */
 403 #define   EXIER_E4IE    0x00000001      /* External Interrupt 4 Enable */
 404 #define DCRN_EXISR      0x040    /* External Interrupt Status Register */
 405 #define DCRN_IOCR       0x0A0    /* Input/Output Configuration Register */
 406 #define   IOCR_E0TE     0x80000000
 407 #define   IOCR_E0LP     0x40000000
 408 #define   IOCR_E1TE     0x20000000
 409 #define   IOCR_E1LP     0x10000000
 410 #define   IOCR_E2TE     0x08000000
 411 #define   IOCR_E2LP     0x04000000
 412 #define   IOCR_E3TE     0x02000000
 413 #define   IOCR_E3LP     0x01000000
 414 #define   IOCR_E4TE     0x00800000
 415 #define   IOCR_E4LP     0x00400000
 416 #define   IOCR_EDT      0x00080000
 417 #define   IOCR_SOR      0x00040000
 418 #define   IOCR_EDO      0x00008000
 419 #define   IOCR_2XC      0x00004000
 420 #define   IOCR_ATC      0x00002000
 421 #define   IOCR_SPD      0x00001000
 422 #define   IOCR_BEM      0x00000800
 423 #define   IOCR_PTD      0x00000400
 424 #define   IOCR_ARE      0x00000080
 425 #define   IOCR_DRC      0x00000020
 426 #define   IOCR_RDM(x)   (((x) & 0x3) << 3)
 427 #define   IOCR_TCS      0x00000004
 428 #define   IOCR_SCS      0x00000002
 429 #define   IOCR_SPC      0x00000001
 430
 431
 432 /* Processor Version Register */
 433
 434 /* Processor Version Register (PVR) field extraction */
 435
 436 #define PVR_VER(pvr)  (((pvr) >>  16) & 0xFFFF) /* Version field */
 437 #define PVR_REV(pvr)  (((pvr) >>   0) & 0xFFFF) /* Revison field */
 438
 439 /*
 440  * IBM has further subdivided the standard PowerPC 16-bit version and
 441  * revision subfields of the PVR for the PowerPC 403s into the following:
 442  */
 443
 444 #define PVR_FAM(pvr)    (((pvr) >> 20) & 0xFFF) /* Family field */
 445 #define PVR_MEM(pvr)    (((pvr) >> 16) & 0xF)   /* Member field */
 446 #define PVR_CORE(pvr)   (((pvr) >> 12) & 0xF)   /* Core field */
 447 #define PVR_CFG(pvr)    (((pvr) >>  8) & 0xF)   /* Configuration field */
 448 #define PVR_MAJ(pvr)    (((pvr) >>  4) & 0xF)   /* Major revision field */
 449 #define PVR_MIN(pvr)    (((pvr) >>  0) & 0xF)   /* Minor revision field */
 450
 451 /* Processor Version Numbers */
 452
 453 #define PVR_403GA       0x00200000
 454 #define PVR_403GB       0x00200100
 455 #define PVR_403GC       0x00200200
 456 #define PVR_403GCX      0x00201400
 457 #define PVR_405GP       0x40110000
 458 #define PVR_601         0x00010000
 459 #define PVR_602         0x00050000
 460 #define PVR_603         0x00030000
 461 #define PVR_603e        0x00060000
 462 #define PVR_603ev       0x00070000
 463 #define PVR_603r        0x00071000
 464 #define PVR_604         0x00040000
 465 #define PVR_604e        0x00090000
 466 #define PVR_604r        0x000A0000
 467 #define PVR_620         0x00140000
 468 #define PVR_740         0x00080000
 469 #define PVR_750         PVR_740
 470 #define PVR_740P        0x10080000
 471 #define PVR_750P        PVR_740P
 472 /*
 473  * For the 8xx processors, all of them report the same PVR family for
 474  * the PowerPC core. The various versions of these processors must be
 475  * differentiated by the version number in the Communication Processor
 476  * Module (CPM).
 477  */
 478 #define PVR_821         0x00500000
 479 #define PVR_823         PVR_821
 480 #define PVR_850         PVR_821
 481 #define PVR_860         PVR_821
 482 #define PVR_7400        0x000C0000
 483 #define PVR_8240        0x00810100
 484 #define PVR_8260        PVR_8240
 485
 486
 487 /* I am just adding a single entry for 8260 boards.  I think we may be
 488  * able to combine mbx, fads, rpxlite, bseip, and classic into a single
 489  * generic 8xx as well.  The boards containing these processors are either
 490  * identical at the processor level (due to the high integration) or so
 491  * wildly different that testing _machine at run time is best replaced by
 492  * conditional compilation by board type (found in their respective .h file).
 493  *      -- Dan
 494  */
 495 #define _MACH_prep      0x00000001
 496 #define _MACH_Pmac      0x00000002      /* pmac or pmac clone (non-chrp) */
 497 #define _MACH_chrp      0x00000004      /* chrp machine */
 498 #define _MACH_mbx       0x00000008      /* Motorola MBX board */
 499 #define _MACH_apus      0x00000010      /* amiga with phase5 powerup */
 500 #define _MACH_fads      0x00000020      /* Motorola FADS board */
 501 #define _MACH_rpxlite   0x00000040      /* RPCG RPX-Lite 8xx board */
 502 #define _MACH_bseip     0x00000080      /* Bright Star Engineering ip-Engine */
 503 #define _MACH_yk        0x00000100      /* Motorola Yellowknife */
 504 #define _MACH_gemini    0x00000200      /* Synergy Microsystems gemini board */
 505 #define _MACH_classic   0x00000400      /* RPCG RPX-Classic 8xx board */
 506 #define _MACH_oak       0x00000800      /* IBM "Oak" 403 eval. board */
 507 #define _MACH_walnut    0x00001000      /* IBM "Walnut" 405GP eval. board */
 508 #define _MACH_8260      0x00002000      /* Generic 8260 */
 509 #define _MACH_tqm860    0x00004000      /* TQM860/L */
 510 #define _MACH_tqm8xxL   0x00008000      /* TQM8xxL */
 511
 512
 513 /* see residual.h for these */
 514 #define _PREP_Motorola 0x01  /* motorola prep */
 515 #define _PREP_Firm     0x02  /* firmworks prep */
 516 #define _PREP_IBM      0x00  /* ibm prep */
 517 #define _PREP_Bull     0x03  /* bull prep */
 518 #define _PREP_Radstone 0x04  /* Radstone Technology PLC prep */
 519
 520 /*
 521  * Radstone board types
 522  */
 523 #define RS_SYS_TYPE_PPC1   0
 524 #define RS_SYS_TYPE_PPC2   1
 525 #define RS_SYS_TYPE_PPC1a  2
 526 #define RS_SYS_TYPE_PPC2a  3
 527 #define RS_SYS_TYPE_PPC4   4
 528 #define RS_SYS_TYPE_PPC4a  5
 529 #define RS_SYS_TYPE_PPC2ep 6
 530
 531 /* these are arbitrary */
 532 #define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
 533 #define _CHRP_IBM      0x05  /* IBM chrp, the longtrail and longtrail 2 */
 534
 535 #define _GLOBAL(n)\
 536         .globl n;\
 537 n:
 538
 539 /* Macros for setting and retrieving special purpose registers */
 540
 541 #define stringify(s)    tostring(s)
 542 #define tostring(s)     #s
 543
 544 #define mfdcr(rn)       ({unsigned int rval; \
 545                         asm volatile("mfdcr %0," stringify(rn) \
 546                                      : "=r" (rval)); rval;})
 547 #define mtdcr(rn, v)    asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
 548
 549 #define mfmsr()         ({unsigned int rval; \
 550                         asm volatile("mfmsr %0" : "=r" (rval)); rval;})
 551 #define mtmsr(v)        asm volatile("mtmsr %0" : : "r" (v))
 552
 553 #define mfspr(rn)       ({unsigned int rval; \
 554                         asm volatile("mfspr %0," stringify(rn) \
 555                                      : "=r" (rval)); rval;})
 556 #define mtspr(rn, v)    asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
 557
 558 /* Segment Registers */
 559
 560 #define SR0     0
 561 #define SR1     1
 562 #define SR2     2
 563 #define SR3     3
 564 #define SR4     4
 565 #define SR5     5
 566 #define SR6     6
 567 #define SR7     7
 568 #define SR8     8
 569 #define SR9     9
 570 #define SR10    10
 571 #define SR11    11
 572 #define SR12    12
 573 #define SR13    13
 574 #define SR14    14
 575 #define SR15    15
 576
 577 #ifndef __ASSEMBLY__
 578 #ifndef CONFIG_MACH_SPECIFIC
 579 extern int _machine;
 580 extern int have_of;
 581 #endif /* CONFIG_MACH_SPECIFIC */
 582
 583 /* what kind of prep workstation we are */
 584 extern int _prep_type;
 585 /*
 586  * This is used to identify the board type from a given PReP board
 587  * vendor. Board revision is also made available.
 588  */
 589 extern unsigned char ucSystemType;
 590 extern unsigned char ucBoardRev;
 591 extern unsigned char ucBoardRevMaj, ucBoardRevMin;
 592
 593 struct task_struct;
 594 void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
 595 void release_thread(struct task_struct *);
 596
 597 /*
 598  * Create a new kernel thread.
 599  */
 600 extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 601
 602 /*
 603  * Bus types
 604  */
 605 #define EISA_bus 0
 606 #define EISA_bus__is_a_macro /* for versions in ksyms.c */
 607 #define MCA_bus 0
 608 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
 609
 610 /* Lazy FPU handling on uni-processor */
 611 extern struct task_struct *last_task_used_math;
 612 extern struct task_struct *last_task_used_altivec;
 613
 614 /*
 615  * this is the minimum allowable io space due to the location
 616  * of the io areas on prep (first one at 0x80000000) but
 617  * as soon as I get around to remapping the io areas with the BATs
 618  * to match the mac we can raise this. -- Cort
 619  */
 620 #define TASK_SIZE       (0x80000000UL)
 621
 622 /* This decides where the kernel will search for a free chunk of vm
 623  * space during mmap's.
 624  */
 625 #define TASK_UNMAPPED_BASE      (TASK_SIZE / 8 * 3)
 626
 627 typedef struct {
 628         unsigned long seg;
 629 } mm_segment_t;
 630
 631 struct thread_struct {
 632         unsigned long   ksp;            /* Kernel stack pointer */
 633         unsigned long   wchan;          /* Event task is sleeping on */
 634         struct pt_regs  *regs;          /* Pointer to saved register state */
 635         mm_segment_t    fs;             /* for get_fs() validation */
 636         void            *pgdir;         /* root of page-table tree */
 637         signed long     last_syscall;
 638         double          fpr[32];        /* Complete floating point set */
 639         unsigned long   fpscr_pad;      /* fpr ... fpscr must be contiguous */
 640         unsigned long   fpscr;          /* Floating point status */
 641 #ifdef CONFIG_ALTIVEC
 642         vector128       vr[32];         /* Complete AltiVec set */
 643         vector128       vscr;           /* AltiVec status */
 644         unsigned long   vrsave;
 645 #endif /* CONFIG_ALTIVEC */
 646 };
 647
 648 #define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
 649
 650 #define INIT_THREAD  { \
 651         INIT_SP, /* ksp */ \
 652         0, /* wchan */ \
 653         (struct pt_regs *)INIT_SP - 1, /* regs */ \
 654         KERNEL_DS, /*fs*/ \
 655         swapper_pg_dir, /* pgdir */ \
 656         0, /* last_syscall */ \
 657         {0}, 0, 0 \
 658 }
 659
 660 /*
 661  * Note: the vm_start and vm_end fields here should *not*
 662  * be in kernel space.  (Could vm_end == vm_start perhaps?)
 663  */
 664 #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
 665                     PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
 666                     1, NULL, NULL }
 667
 668 /*
 669  * Return saved PC of a blocked thread. For now, this is the "user" PC
 670  */
 671 static inline unsigned long thread_saved_pc(struct thread_struct *t)
 672 {
 673         return (t->regs) ? t->regs->nip : 0;
 674 }
 675
 676 unsigned long get_wchan(struct task_struct *p);
 677
 678 #define KSTK_EIP(tsk)  ((tsk)->thread.regs->nip)
 679 #define KSTK_ESP(tsk)  ((tsk)->thread.regs->gpr[1])
 680
 681 /*
 682  * NOTE! The task struct and the stack go together
 683  */
 684 #define THREAD_SIZE (2*PAGE_SIZE)
 685 #define alloc_task_struct() \
 686         ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
 687 #define free_task_struct(p)     free_pages((unsigned long)(p),1)
 688 #define get_task_struct(tsk)      atomic_inc(&virt_to_page(tsk)->count)
 689
 690 /* in process.c - for early bootup debug -- Cort */
 691 int ll_printk(const char *, ...);
 692 void ll_puts(const char *);
 693
 694 #define init_task       (init_task_union.task)
 695 #define init_stack      (init_task_union.stack)
 696
 697 /* In misc.c */
 698 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 699
 700 #endif /* ndef ASSEMBLY*/
 701
 702 #ifdef CONFIG_MACH_SPECIFIC
 703 #if defined(CONFIG_8xx)
 704 #define _machine _MACH_8xx
 705 #define have_of 0
 706 #elif defined(CONFIG_OAK)
 707 #define _machine _MACH_oak
 708 #define have_of 0
 709 #elif defined(CONFIG_WALNUT)
 710 #define _machine _MACH_walnut
 711 #define have_of 0
 712 #elif defined(CONFIG_APUS)
 713 #define _machine _MACH_apus
 714 #define have_of 0
 715 #elif defined(CONFIG_GEMINI)
 716 #define _machine _MACH_gemini
 717 #define have_of 0
 718 #elif defined(CONFIG_8260)
 719 #define _machine _MACH_8260
 720 #define have_of 0
 721 #else
 722 #error "Machine not defined correctly"
 723 #endif
 724 #endif /* CONFIG_MACH_SPECIFIC */
 725
 726 #endif /* __ASM_PPC_PROCESSOR_H */
 727 #endif /* __KERNEL__ */