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- Kai Germaschewski: ISDN update (including Makefiles)
[davej-history.git] / drivers / isdn / hisax / hfc_pci.c
blob053dd90249567461ea3d744d187dc318107f5042
1 /* $Id: hfc_pci.c,v 1.34.6.3 2000/12/10 23:39:19 kai Exp $
2
3 * hfc_pci.c low level driver for CCD´s hfc-pci based cards
4 *
5 * Author Werner Cornelius (werner@isdn4linux.de)
6 * based on existing driver for CCD hfc ISA cards
7 *
8 * Copyright 1999 by Werner Cornelius (werner@isdn4linux.de)
9 * Copyright 1999 by Karsten Keil (keil@isdn4linux.de)
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 */
26
27 #include <linux/init.h>
28 #include <linux/config.h>
29 #define __NO_VERSION__
30 #include "hisax.h"
31 #include "hfc_pci.h"
32 #include "isdnl1.h"
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
35
36 extern const char *CardType[];
37
38 static const char *hfcpci_revision = "$Revision: 1.34.6.3 $";
39
40 /* table entry in the PCI devices list */
41 typedef struct {
42 int vendor_id;
43 int device_id;
44 char *vendor_name;
45 char *card_name;
46 } PCI_ENTRY;
47
48 #define NT_T1_COUNT 20 /* number of 3.125ms interrupts for G2 timeout */
49 #define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
50 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
51
52 static const PCI_ENTRY id_list[] =
53 {
54 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_2BD0, "CCD/Billion/Asuscom", "2BD0"},
55 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B000, "Billion", "B000"},
56 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B006, "Billion", "B006"},
57 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B007, "Billion", "B007"},
58 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B008, "Billion", "B008"},
59 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B009, "Billion", "B009"},
60 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00A, "Billion", "B00A"},
61 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00B, "Billion", "B00B"},
62 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00C, "Billion", "B00C"},
63 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B100, "Seyeon", "B100"},
64 {PCI_VENDOR_ID_ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1, "Abocom/Magitek", "2BD1"},
65 {PCI_VENDOR_ID_ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675, "Asuscom/Askey", "675"},
66 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT, "German telekom", "T-Concept"},
67 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_A1T, "German telekom", "A1T"},
68 {PCI_VENDOR_ID_ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575, "Motorola MC145575", "MC145575"},
69 {PCI_VENDOR_ID_ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0, "Zoltrix", "2BD0"},
70 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E,"Digi International", "Digi DataFire Micro V IOM2 (Europe)"},
71 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E,"Digi International", "Digi DataFire Micro V (Europe)"},
72 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A,"Digi International", "Digi DataFire Micro V IOM2 (North America)"},
73 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A,"Digi International", "Digi DataFire Micro V (North America)"},
74 {0, 0, NULL, NULL},
75 };
76
77
78 #if CONFIG_PCI
79
80 /******************************************/
81 /* free hardware resources used by driver */
82 /******************************************/
83 void
84 release_io_hfcpci(struct IsdnCardState *cs)
85 {
86 int flags;
87
88 save_flags(flags);
89 cli();
90 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */
91 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
92 restore_flags(flags);
93 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */
94 sti();
95 set_current_state(TASK_UNINTERRUPTIBLE);
96 schedule_timeout((30 * HZ) / 1000); /* Timeout 30ms */
97 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */
98 #if CONFIG_PCI
99 pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, 0); /* disable memory mapped ports + busmaster */
100 #endif /* CONFIG_PCI */
101 del_timer(&cs->hw.hfcpci.timer);
102 kfree(cs->hw.hfcpci.share_start);
103 cs->hw.hfcpci.share_start = NULL;
104 vfree(cs->hw.hfcpci.pci_io);
105 }
106
107 /********************************************************************************/
108 /* function called to reset the HFC PCI chip. A complete software reset of chip */
109 /* and fifos is done. */
110 /********************************************************************************/
111 static void
112 reset_hfcpci(struct IsdnCardState *cs)
113 {
114 long flags;
115
116 save_flags(flags);
117 cli();
118 pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */
119 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */
120 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
121
122 printk(KERN_INFO "HFC_PCI: resetting card\n");
123 pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, PCI_ENA_MEMIO + PCI_ENA_MASTER); /* enable memory ports + busmaster */
124 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */
125 sti();
126 set_current_state(TASK_UNINTERRUPTIBLE);
127 schedule_timeout((30 * HZ) / 1000); /* Timeout 30ms */
128 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */
129 set_current_state(TASK_UNINTERRUPTIBLE);
130 schedule_timeout((20 * HZ) / 1000); /* Timeout 20ms */
131 if (Read_hfc(cs, HFCPCI_STATUS) & 2)
132 printk(KERN_WARNING "HFC-PCI init bit busy\n");
133
134 cs->hw.hfcpci.fifo_en = 0x30; /* only D fifos enabled */
135 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
136
137 cs->hw.hfcpci.trm = 0 + HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
138 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
139
140 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_TE); /* ST-Bit delay for TE-Mode */
141 cs->hw.hfcpci.sctrl_e = HFCPCI_AUTO_AWAKE;
142 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); /* S/T Auto awake */
143 cs->hw.hfcpci.bswapped = 0; /* no exchange */
144 cs->hw.hfcpci.nt_mode = 0; /* we are in TE mode */
145 cs->hw.hfcpci.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
146 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
147
148 cs->hw.hfcpci.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
149 HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
150 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
151
152 /* Clear already pending ints */
153 if (Read_hfc(cs, HFCPCI_INT_S1));
154
155 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 2); /* HFC ST 2 */
156 udelay(10);
157 Write_hfc(cs, HFCPCI_STATES, 2); /* HFC ST 2 */
158 cs->hw.hfcpci.mst_m = HFCPCI_MASTER; /* HFC Master Mode */
159
160 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
161 cs->hw.hfcpci.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
162 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
163 cs->hw.hfcpci.sctrl_r = 0;
164 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
165
166 /* Init GCI/IOM2 in master mode */
167 /* Slots 0 and 1 are set for B-chan 1 and 2 */
168 /* D- and monitor/CI channel are not enabled */
169 /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
170 /* STIO2 is used as data input, B1+B2 from IOM->ST */
171 /* ST B-channel send disabled -> continous 1s */
172 /* The IOM slots are always enabled */
173 cs->hw.hfcpci.conn = 0x36; /* set data flow directions */
174 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
175 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */
176 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */
177 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */
178 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */
179
180 /* Finally enable IRQ output */
181 cs->hw.hfcpci.int_m2 = HFCPCI_IRQ_ENABLE;
182 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
183 if (Read_hfc(cs, HFCPCI_INT_S2));
184 restore_flags(flags);
185 }
186
187 /***************************************************/
188 /* Timer function called when kernel timer expires */
189 /***************************************************/
190 static void
191 hfcpci_Timer(struct IsdnCardState *cs)
192 {
193 cs->hw.hfcpci.timer.expires = jiffies + 75;
194 /* WD RESET */
195 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcpci.ctmt | 0x80);
196 add_timer(&cs->hw.hfcpci.timer);
197 */
198 }
199
200
201 /*********************************/
202 /* schedule a new D-channel task */
203 /*********************************/
204 static void
205 sched_event_D_pci(struct IsdnCardState *cs, int event)
206 {
207 test_and_set_bit(event, &cs->event);
208 queue_task(&cs->tqueue, &tq_immediate);
209 mark_bh(IMMEDIATE_BH);
210 }
211
212 /*********************************/
213 /* schedule a new b_channel task */
214 /*********************************/
215 static void
216 hfcpci_sched_event(struct BCState *bcs, int event)
217 {
218 bcs->event |= 1 << event;
219 queue_task(&bcs->tqueue, &tq_immediate);
220 mark_bh(IMMEDIATE_BH);
221 }
222
223 /************************************************/
224 /* select a b-channel entry matching and active */
225 /************************************************/
226 static
227 struct BCState *
228 Sel_BCS(struct IsdnCardState *cs, int channel)
229 {
230 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
231 return (&cs->bcs[0]);
232 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
233 return (&cs->bcs[1]);
234 else
235 return (NULL);
236 }
237
238 /*********************************************/
239 /* read a complete B-frame out of the buffer */
240 /*********************************************/
241 static struct sk_buff
242 *
243 hfcpci_empty_fifo(struct BCState *bcs, bzfifo_type * bz, u_char * bdata, int count)
244 {
245 u_char *ptr, *ptr1, new_f2;
246 struct sk_buff *skb;
247 struct IsdnCardState *cs = bcs->cs;
248 int flags, total, maxlen, new_z2;
249 z_type *zp;
250
251 save_flags(flags);
252 sti();
253 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
254 debugl1(cs, "hfcpci_empty_fifo");
255 zp = &bz->za[bz->f2]; /* point to Z-Regs */
256 new_z2 = zp->z2 + count; /* new position in fifo */
257 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
258 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
259 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
260 if ((count > HSCX_BUFMAX + 3) || (count < 4) ||
261 (*(bdata + (zp->z1 - B_SUB_VAL)))) {
262 if (cs->debug & L1_DEB_WARN)
263 debugl1(cs, "hfcpci_empty_fifo: incoming packet invalid length %d or crc", count);
264 #ifdef ERROR_STATISTIC
265 bcs->err_inv++;
266 #endif
267 bz->za[new_f2].z2 = new_z2;
268 bz->f2 = new_f2; /* next buffer */
269 skb = NULL;
270 } else if (!(skb = dev_alloc_skb(count - 3)))
271 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
272 else {
273 total = count;
274 count -= 3;
275 ptr = skb_put(skb, count);
276
277 if (zp->z2 + count <= B_FIFO_SIZE + B_SUB_VAL)
278 maxlen = count; /* complete transfer */
279 else
280 maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2; /* maximum */
281
282 ptr1 = bdata + (zp->z2 - B_SUB_VAL); /* start of data */
283 memcpy(ptr, ptr1, maxlen); /* copy data */
284 count -= maxlen;
285
286 if (count) { /* rest remaining */
287 ptr += maxlen;
288 ptr1 = bdata; /* start of buffer */
289 memcpy(ptr, ptr1, count); /* rest */
290 }
291 bz->za[new_f2].z2 = new_z2;
292 bz->f2 = new_f2; /* next buffer */
293
294 }
295 restore_flags(flags);
296 return (skb);
297 }
298
299 /*******************************/
300 /* D-channel receive procedure */
301 /*******************************/
302 static
303 int
304 receive_dmsg(struct IsdnCardState *cs)
305 {
306 struct sk_buff *skb;
307 int maxlen;
308 int rcnt, total;
309 int count = 5;
310 u_char *ptr, *ptr1;
311 dfifo_type *df;
312 z_type *zp;
313
314 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_rx;
315 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
316 debugl1(cs, "rec_dmsg blocked");
317 return (1);
318 }
319 while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
320 zp = &df->za[df->f2 & D_FREG_MASK];
321 rcnt = zp->z1 - zp->z2;
322 if (rcnt < 0)
323 rcnt += D_FIFO_SIZE;
324 rcnt++;
325 if (cs->debug & L1_DEB_ISAC)
326 debugl1(cs, "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
327 df->f1, df->f2, zp->z1, zp->z2, rcnt);
328
329 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
330 (df->data[zp->z1])) {
331 if (cs->debug & L1_DEB_WARN)
332 debugl1(cs, "empty_fifo hfcpci paket inv. len %d or crc %d", rcnt, df->data[zp->z1]);
333 #ifdef ERROR_STATISTIC
334 cs->err_rx++;
335 #endif
336 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1); /* next buffer */
337 df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + rcnt) & (D_FIFO_SIZE - 1);
338 } else if ((skb = dev_alloc_skb(rcnt - 3))) {
339 total = rcnt;
340 rcnt -= 3;
341 ptr = skb_put(skb, rcnt);
342
343 if (zp->z2 + rcnt <= D_FIFO_SIZE)
344 maxlen = rcnt; /* complete transfer */
345 else
346 maxlen = D_FIFO_SIZE - zp->z2; /* maximum */
347
348 ptr1 = df->data + zp->z2; /* start of data */
349 memcpy(ptr, ptr1, maxlen); /* copy data */
350 rcnt -= maxlen;
351
352 if (rcnt) { /* rest remaining */
353 ptr += maxlen;
354 ptr1 = df->data; /* start of buffer */
355 memcpy(ptr, ptr1, rcnt); /* rest */
356 }
357 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1); /* next buffer */
358 df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + total) & (D_FIFO_SIZE - 1);
359
360 skb_queue_tail(&cs->rq, skb);
361 sched_event_D_pci(cs, D_RCVBUFREADY);
362 } else
363 printk(KERN_WARNING "HFC-PCI: D receive out of memory\n");
364 }
365 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
366 return (1);
367 }
368
369 /*******************************************************************************/
370 /* check for transparent receive data and read max one threshold size if avail */
371 /*******************************************************************************/
372 int
373 hfcpci_empty_fifo_trans(struct BCState *bcs, bzfifo_type * bz, u_char * bdata)
374 {
375 unsigned short *z1r, *z2r;
376 int new_z2, fcnt, maxlen;
377 struct sk_buff *skb;
378 u_char *ptr, *ptr1;
379
380 z1r = &bz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
381 z2r = z1r + 1;
382
383 if (!(fcnt = *z1r - *z2r))
384 return (0); /* no data avail */
385
386 if (fcnt <= 0)
387 fcnt += B_FIFO_SIZE; /* bytes actually buffered */
388 if (fcnt > HFCPCI_BTRANS_THRESHOLD)
389 fcnt = HFCPCI_BTRANS_THRESHOLD; /* limit size */
390
391 new_z2 = *z2r + fcnt; /* new position in fifo */
392 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
393 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
394
395 if (!(skb = dev_alloc_skb(fcnt)))
396 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
397 else {
398 ptr = skb_put(skb, fcnt);
399 if (*z2r + fcnt <= B_FIFO_SIZE + B_SUB_VAL)
400 maxlen = fcnt; /* complete transfer */
401 else
402 maxlen = B_FIFO_SIZE + B_SUB_VAL - *z2r; /* maximum */
403
404 ptr1 = bdata + (*z2r - B_SUB_VAL); /* start of data */
405 memcpy(ptr, ptr1, maxlen); /* copy data */
406 fcnt -= maxlen;
407
408 if (fcnt) { /* rest remaining */
409 ptr += maxlen;
410 ptr1 = bdata; /* start of buffer */
411 memcpy(ptr, ptr1, fcnt); /* rest */
412 }
413 cli();
414 skb_queue_tail(&bcs->rqueue, skb);
415 sti();
416 hfcpci_sched_event(bcs, B_RCVBUFREADY);
417 }
418
419 *z2r = new_z2; /* new position */
420 return (1);
421 } /* hfcpci_empty_fifo_trans */
422
423 /**********************************/
424 /* B-channel main receive routine */
425 /**********************************/
426 void
427 main_rec_hfcpci(struct BCState *bcs)
428 {
429 long flags;
430 struct IsdnCardState *cs = bcs->cs;
431 int rcnt;
432 int receive, count = 5;
433 struct sk_buff *skb;
434 bzfifo_type *bz;
435 u_char *bdata;
436 z_type *zp;
437
438
439 save_flags(flags);
440 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
441 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
442 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
443 } else {
444 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
445 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b1;
446 }
447 Begin:
448 count--;
449 cli();
450 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
451 debugl1(cs, "rec_data %d blocked", bcs->channel);
452 restore_flags(flags);
453 return;
454 }
455 sti();
456 if (bz->f1 != bz->f2) {
457 if (cs->debug & L1_DEB_HSCX)
458 debugl1(cs, "hfcpci rec %d f1(%d) f2(%d)",
459 bcs->channel, bz->f1, bz->f2);
460 zp = &bz->za[bz->f2];
461
462 rcnt = zp->z1 - zp->z2;
463 if (rcnt < 0)
464 rcnt += B_FIFO_SIZE;
465 rcnt++;
466 if (cs->debug & L1_DEB_HSCX)
467 debugl1(cs, "hfcpci rec %d z1(%x) z2(%x) cnt(%d)",
468 bcs->channel, zp->z1, zp->z2, rcnt);
469 if ((skb = hfcpci_empty_fifo(bcs, bz, bdata, rcnt))) {
470 cli();
471 skb_queue_tail(&bcs->rqueue, skb);
472 sti();
473 hfcpci_sched_event(bcs, B_RCVBUFREADY);
474 }
475 rcnt = bz->f1 - bz->f2;
476 if (rcnt < 0)
477 rcnt += MAX_B_FRAMES + 1;
478 if (rcnt > 1)
479 receive = 1;
480 else
481 receive = 0;
482 } else if (bcs->mode == L1_MODE_TRANS)
483 receive = hfcpci_empty_fifo_trans(bcs, bz, bdata);
484 else
485 receive = 0;
486 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
487 if (count && receive)
488 goto Begin;
489 restore_flags(flags);
490 return;
491 }
492
493 /**************************/
494 /* D-channel send routine */
495 /**************************/
496 static void
497 hfcpci_fill_dfifo(struct IsdnCardState *cs)
498 {
499 long flags;
500 int fcnt;
501 int count, new_z1, maxlen;
502 dfifo_type *df;
503 u_char *src, *dst, new_f1;
504
505 if (!cs->tx_skb)
506 return;
507 if (cs->tx_skb->len <= 0)
508 return;
509
510 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_tx;
511
512 if (cs->debug & L1_DEB_ISAC)
513 debugl1(cs, "hfcpci_fill_Dfifo f1(%d) f2(%d) z1(f1)(%x)",
514 df->f1, df->f2,
515 df->za[df->f1 & D_FREG_MASK].z1);
516 fcnt = df->f1 - df->f2; /* frame count actually buffered */
517 if (fcnt < 0)
518 fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
519 if (fcnt > (MAX_D_FRAMES - 1)) {
520 if (cs->debug & L1_DEB_ISAC)
521 debugl1(cs, "hfcpci_fill_Dfifo more as 14 frames");
522 #ifdef ERROR_STATISTIC
523 cs->err_tx++;
524 #endif
525 return;
526 }
527 /* now determine free bytes in FIFO buffer */
528 count = df->za[df->f1 & D_FREG_MASK].z2 - df->za[df->f1 & D_FREG_MASK].z1;
529 if (count <= 0)
530 count += D_FIFO_SIZE; /* count now contains available bytes */
531
532 if (cs->debug & L1_DEB_ISAC)
533 debugl1(cs, "hfcpci_fill_Dfifo count(%ld/%d)",
534 cs->tx_skb->len, count);
535 if (count < cs->tx_skb->len) {
536 if (cs->debug & L1_DEB_ISAC)
537 debugl1(cs, "hfcpci_fill_Dfifo no fifo mem");
538 return;
539 }
540 count = cs->tx_skb->len; /* get frame len */
541 new_z1 = (df->za[df->f1 & D_FREG_MASK].z1 + count) & (D_FIFO_SIZE - 1);
542 new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
543 src = cs->tx_skb->data; /* source pointer */
544 dst = df->data + df->za[df->f1 & D_FREG_MASK].z1;
545 maxlen = D_FIFO_SIZE - df->za[df->f1 & D_FREG_MASK].z1; /* end fifo */
546 if (maxlen > count)
547 maxlen = count; /* limit size */
548 memcpy(dst, src, maxlen); /* first copy */
549
550 count -= maxlen; /* remaining bytes */
551 if (count) {
552 dst = df->data; /* start of buffer */
553 src += maxlen; /* new position */
554 memcpy(dst, src, count);
555 }
556 save_flags(flags);
557 cli();
558 df->za[new_f1 & D_FREG_MASK].z1 = new_z1; /* for next buffer */
559 df->za[df->f1 & D_FREG_MASK].z1 = new_z1; /* new pos actual buffer */
560 df->f1 = new_f1; /* next frame */
561 restore_flags(flags);
562
563 dev_kfree_skb_any(cs->tx_skb);
564 cs->tx_skb = NULL;
565 return;
566 }
567
568 /**************************/
569 /* B-channel send routine */
570 /**************************/
571 static void
572 hfcpci_fill_fifo(struct BCState *bcs)
573 {
574 struct IsdnCardState *cs = bcs->cs;
575 int flags, maxlen, fcnt;
576 int count, new_z1;
577 bzfifo_type *bz;
578 u_char *bdata;
579 u_char new_f1, *src, *dst;
580 unsigned short *z1t, *z2t;
581
582 if (!bcs->tx_skb)
583 return;
584 if (bcs->tx_skb->len <= 0)
585 return;
586
587 save_flags(flags);
588 sti();
589
590 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
591 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
592 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b2;
593 } else {
594 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
595 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b1;
596 }
597
598 if (bcs->mode == L1_MODE_TRANS) {
599 z1t = &bz->za[MAX_B_FRAMES].z1;
600 z2t = z1t + 1;
601 if (cs->debug & L1_DEB_HSCX)
602 debugl1(cs, "hfcpci_fill_fifo_trans %d z1(%x) z2(%x)",
603 bcs->channel, *z1t, *z2t);
604 fcnt = *z2t - *z1t;
605 if (fcnt <= 0)
606 fcnt += B_FIFO_SIZE; /* fcnt contains available bytes in fifo */
607 fcnt = B_FIFO_SIZE - fcnt; /* remaining bytes to send */
608
609 while ((fcnt < 2 * HFCPCI_BTRANS_THRESHOLD) && (bcs->tx_skb)) {
610 if (bcs->tx_skb->len < B_FIFO_SIZE - fcnt) {
611 /* data is suitable for fifo */
612 count = bcs->tx_skb->len;
613
614 new_z1 = *z1t + count; /* new buffer Position */
615 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
616 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
617 src = bcs->tx_skb->data; /* source pointer */
618 dst = bdata + (*z1t - B_SUB_VAL);
619 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - *z1t; /* end of fifo */
620 if (maxlen > count)
621 maxlen = count; /* limit size */
622 memcpy(dst, src, maxlen); /* first copy */
623
624 count -= maxlen; /* remaining bytes */
625 if (count) {
626 dst = bdata; /* start of buffer */
627 src += maxlen; /* new position */
628 memcpy(dst, src, count);
629 }
630 bcs->tx_cnt -= bcs->tx_skb->len;
631 fcnt += bcs->tx_skb->len;
632 *z1t = new_z1; /* now send data */
633 } else if (cs->debug & L1_DEB_HSCX)
634 debugl1(cs, "hfcpci_fill_fifo_trans %d frame length %d discarded",
635 bcs->channel, bcs->tx_skb->len);
636
637 dev_kfree_skb_any(bcs->tx_skb);
638 cli();
639 bcs->tx_skb = skb_dequeue(&bcs->squeue); /* fetch next data */
640 sti();
641 }
642 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
643 restore_flags(flags);
644 return;
645 }
646 if (cs->debug & L1_DEB_HSCX)
647 debugl1(cs, "hfcpci_fill_fifo_hdlc %d f1(%d) f2(%d) z1(f1)(%x)",
648 bcs->channel, bz->f1, bz->f2,
649 bz->za[bz->f1].z1);
650
651 fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
652 if (fcnt < 0)
653 fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
654 if (fcnt > (MAX_B_FRAMES - 1)) {
655 if (cs->debug & L1_DEB_HSCX)
656 debugl1(cs, "hfcpci_fill_Bfifo more as 14 frames");
657 restore_flags(flags);
658 return;
659 }
660 /* now determine free bytes in FIFO buffer */
661 count = bz->za[bz->f1].z2 - bz->za[bz->f1].z1;
662 if (count <= 0)
663 count += B_FIFO_SIZE; /* count now contains available bytes */
664
665 if (cs->debug & L1_DEB_HSCX)
666 debugl1(cs, "hfcpci_fill_fifo %d count(%ld/%d),%lx",
667 bcs->channel, bcs->tx_skb->len,
668 count, current->state);
669
670 if (count < bcs->tx_skb->len) {
671 if (cs->debug & L1_DEB_HSCX)
672 debugl1(cs, "hfcpci_fill_fifo no fifo mem");
673 restore_flags(flags);
674 return;
675 }
676 count = bcs->tx_skb->len; /* get frame len */
677 new_z1 = bz->za[bz->f1].z1 + count; /* new buffer Position */
678 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
679 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
680
681 new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
682 src = bcs->tx_skb->data; /* source pointer */
683 dst = bdata + (bz->za[bz->f1].z1 - B_SUB_VAL);
684 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - bz->za[bz->f1].z1; /* end fifo */
685 if (maxlen > count)
686 maxlen = count; /* limit size */
687 memcpy(dst, src, maxlen); /* first copy */
688
689 count -= maxlen; /* remaining bytes */
690 if (count) {
691 dst = bdata; /* start of buffer */
692 src += maxlen; /* new position */
693 memcpy(dst, src, count);
694 }
695 bcs->tx_cnt -= bcs->tx_skb->len;
696 if (bcs->st->lli.l1writewakeup &&
697 (PACKET_NOACK != bcs->tx_skb->pkt_type))
698 bcs->st->lli.l1writewakeup(bcs->st, bcs->tx_skb->len);
699
700 cli();
701 bz->za[new_f1].z1 = new_z1; /* for next buffer */
702 bz->f1 = new_f1; /* next frame */
703 restore_flags(flags);
704
705 dev_kfree_skb_any(bcs->tx_skb);
706 bcs->tx_skb = NULL;
707 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
708 return;
709 }
710
711 /**********************************************/
712 /* D-channel l1 state call for leased NT-mode */
713 /**********************************************/
714 static void
715 dch_nt_l2l1(struct PStack *st, int pr, void *arg)
716 {
717 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
718
719 switch (pr) {
720 case (PH_DATA | REQUEST):
721 case (PH_PULL | REQUEST):
722 case (PH_PULL | INDICATION):
723 st->l1.l1hw(st, pr, arg);
724 break;
725 case (PH_ACTIVATE | REQUEST):
726 st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
727 break;
728 case (PH_TESTLOOP | REQUEST):
729 if (1 & (long) arg)
730 debugl1(cs, "PH_TEST_LOOP B1");
731 if (2 & (long) arg)
732 debugl1(cs, "PH_TEST_LOOP B2");
733 if (!(3 & (long) arg))
734 debugl1(cs, "PH_TEST_LOOP DISABLED");
735 st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
736 break;
737 default:
738 if (cs->debug)
739 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
740 break;
741 }
742 }
743
744
745
746 /***********************/
747 /* set/reset echo mode */
748 /***********************/
749 static int
750 hfcpci_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic)
751 {
752 int flags;
753 int i = *(unsigned int *) ic->parm.num;
754
755 if ((ic->arg == 98) &&
756 (!(cs->hw.hfcpci.int_m1 & (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC + HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC)))) {
757 save_flags(flags);
758 cli();
759 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_NT); /* ST-Bit delay for NT-Mode */
760 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 0); /* HFC ST G0 */
761 udelay(10);
762 cs->hw.hfcpci.sctrl |= SCTRL_MODE_NT;
763 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); /* set NT-mode */
764 udelay(10);
765 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 1); /* HFC ST G1 */
766 udelay(10);
767 Write_hfc(cs, HFCPCI_STATES, 1 | HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
768 cs->dc.hfcpci.ph_state = 1;
769 cs->hw.hfcpci.nt_mode = 1;
770 cs->hw.hfcpci.nt_timer = 0;
771 cs->stlist->l2.l2l1 = dch_nt_l2l1;
772 restore_flags(flags);
773 debugl1(cs, "NT mode activated");
774 return (0);
775 }
776 if ((cs->chanlimit > 1) || (cs->hw.hfcpci.bswapped) ||
777 (cs->hw.hfcpci.nt_mode) || (ic->arg != 12))
778 return (-EINVAL);
779
780 save_flags(flags);
781 cli();
782 if (i) {
783 cs->logecho = 1;
784 cs->hw.hfcpci.trm |= 0x20; /* enable echo chan */
785 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_B2REC;
786 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2RX;
787 } else {
788 cs->logecho = 0;
789 cs->hw.hfcpci.trm &= ~0x20; /* disable echo chan */
790 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_B2REC;
791 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2RX;
792 }
793 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
794 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
795 cs->hw.hfcpci.conn |= 0x10; /* B2-IOM -> B2-ST */
796 cs->hw.hfcpci.ctmt &= ~2;
797 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
798 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
799 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
800 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
801 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
802 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
803 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
804 restore_flags(flags);
805 return (0);
806 } /* hfcpci_auxcmd */
807
808 /*****************************/
809 /* E-channel receive routine */
810 /*****************************/
811 static void
812 receive_emsg(struct IsdnCardState *cs)
813 {
814 long flags;
815 int rcnt;
816 int receive, count = 5;
817 bzfifo_type *bz;
818 u_char *bdata;
819 z_type *zp;
820 u_char *ptr, *ptr1, new_f2;
821 int total, maxlen, new_z2;
822 u_char e_buffer[256];
823
824 save_flags(flags);
825 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
826 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
827 Begin:
828 count--;
829 cli();
830 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
831 debugl1(cs, "echo_rec_data blocked");
832 restore_flags(flags);
833 return;
834 }
835 sti();
836 if (bz->f1 != bz->f2) {
837 if (cs->debug & L1_DEB_ISAC)
838 debugl1(cs, "hfcpci e_rec f1(%d) f2(%d)",
839 bz->f1, bz->f2);
840 zp = &bz->za[bz->f2];
841
842 rcnt = zp->z1 - zp->z2;
843 if (rcnt < 0)
844 rcnt += B_FIFO_SIZE;
845 rcnt++;
846 if (cs->debug & L1_DEB_ISAC)
847 debugl1(cs, "hfcpci e_rec z1(%x) z2(%x) cnt(%d)",
848 zp->z1, zp->z2, rcnt);
849 new_z2 = zp->z2 + rcnt; /* new position in fifo */
850 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
851 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
852 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
853 if ((rcnt > 256 + 3) || (count < 4) ||
854 (*(bdata + (zp->z1 - B_SUB_VAL)))) {
855 if (cs->debug & L1_DEB_WARN)
856 debugl1(cs, "hfcpci_empty_echan: incoming packet invalid length %d or crc", rcnt);
857 bz->za[new_f2].z2 = new_z2;
858 bz->f2 = new_f2; /* next buffer */
859 } else {
860 total = rcnt;
861 rcnt -= 3;
862 ptr = e_buffer;
863
864 if (zp->z2 <= B_FIFO_SIZE + B_SUB_VAL)
865 maxlen = rcnt; /* complete transfer */
866 else
867 maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2; /* maximum */
868
869 ptr1 = bdata + (zp->z2 - B_SUB_VAL); /* start of data */
870 memcpy(ptr, ptr1, maxlen); /* copy data */
871 rcnt -= maxlen;
872
873 if (rcnt) { /* rest remaining */
874 ptr += maxlen;
875 ptr1 = bdata; /* start of buffer */
876 memcpy(ptr, ptr1, rcnt); /* rest */
877 }
878 bz->za[new_f2].z2 = new_z2;
879 bz->f2 = new_f2; /* next buffer */
880 if (cs->debug & DEB_DLOG_HEX) {
881 ptr = cs->dlog;
882 if ((total - 3) < MAX_DLOG_SPACE / 3 - 10) {
883 *ptr++ = 'E';
884 *ptr++ = 'C';
885 *ptr++ = 'H';
886 *ptr++ = 'O';
887 *ptr++ = ':';
888 ptr += QuickHex(ptr, e_buffer, total - 3);
889 ptr--;
890 *ptr++ = '\n';
891 *ptr = 0;
892 HiSax_putstatus(cs, NULL, cs->dlog);
893 } else
894 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", total - 3);
895 }
896 }
897
898 rcnt = bz->f1 - bz->f2;
899 if (rcnt < 0)
900 rcnt += MAX_B_FRAMES + 1;
901 if (rcnt > 1)
902 receive = 1;
903 else
904 receive = 0;
905 } else
906 receive = 0;
907 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
908 if (count && receive)
909 goto Begin;
910 restore_flags(flags);
911 return;
912 } /* receive_emsg */
913
914 /*********************/
915 /* Interrupt handler */
916 /*********************/
917 static void
918 hfcpci_interrupt(int intno, void *dev_id, struct pt_regs *regs)
919 {
920 struct IsdnCardState *cs = dev_id;
921 u_char exval;
922 struct BCState *bcs;
923 int count = 15;
924 long flags;
925 u_char val, stat;
926
927 if (!cs) {
928 printk(KERN_WARNING "HFC-PCI: Spurious interrupt!\n");
929 return;
930 }
931 if (!(cs->hw.hfcpci.int_m2 & 0x08))
932 return; /* not initialised */
933
934 if (HFCPCI_ANYINT & (stat = Read_hfc(cs, HFCPCI_STATUS))) {
935 val = Read_hfc(cs, HFCPCI_INT_S1);
936 if (cs->debug & L1_DEB_ISAC)
937 debugl1(cs, "HFC-PCI: stat(%02x) s1(%02x)", stat, val);
938 } else
939 return;
940
941 if (cs->debug & L1_DEB_ISAC)
942 debugl1(cs, "HFC-PCI irq %x %s", val,
943 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
944 "locked" : "unlocked");
945 val &= cs->hw.hfcpci.int_m1;
946 if (val & 0x40) { /* state machine irq */
947 exval = Read_hfc(cs, HFCPCI_STATES) & 0xf;
948 if (cs->debug & L1_DEB_ISAC)
949 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcpci.ph_state,
950 exval);
951 cs->dc.hfcpci.ph_state = exval;
952 sched_event_D_pci(cs, D_L1STATECHANGE);
953 val &= ~0x40;
954 }
955 if (val & 0x80) { /* timer irq */
956 if (cs->hw.hfcpci.nt_mode) {
957 if ((--cs->hw.hfcpci.nt_timer) < 0)
958 sched_event_D_pci(cs, D_L1STATECHANGE);
959 }
960 val &= ~0x80;
961 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
962 }
963 while (val) {
964 save_flags(flags);
965 cli();
966 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
967 cs->hw.hfcpci.int_s1 |= val;
968 restore_flags(flags);
969 return;
970 }
971 if (cs->hw.hfcpci.int_s1 & 0x18) {
972 exval = val;
973 val = cs->hw.hfcpci.int_s1;
974 cs->hw.hfcpci.int_s1 = exval;
975 }
976 if (val & 0x08) {
977 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
978 if (cs->debug)
979 debugl1(cs, "hfcpci spurious 0x08 IRQ");
980 } else
981 main_rec_hfcpci(bcs);
982 }
983 if (val & 0x10) {
984 if (cs->logecho)
985 receive_emsg(cs);
986 else if (!(bcs = Sel_BCS(cs, 1))) {
987 if (cs->debug)
988 debugl1(cs, "hfcpci spurious 0x10 IRQ");
989 } else
990 main_rec_hfcpci(bcs);
991 }
992 if (val & 0x01) {
993 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
994 if (cs->debug)
995 debugl1(cs, "hfcpci spurious 0x01 IRQ");
996 } else {
997 if (bcs->tx_skb) {
998 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
999 hfcpci_fill_fifo(bcs);
1000 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1001 } else
1002 debugl1(cs, "fill_data %d blocked", bcs->channel);
1003 } else {
1004 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
1005 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1006 hfcpci_fill_fifo(bcs);
1007 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1008 } else
1009 debugl1(cs, "fill_data %d blocked", bcs->channel);
1010 } else {
1011 hfcpci_sched_event(bcs, B_XMTBUFREADY);
1012 }
1013 }
1014 }
1015 }
1016 if (val & 0x02) {
1017 if (!(bcs = Sel_BCS(cs, 1))) {
1018 if (cs->debug)
1019 debugl1(cs, "hfcpci spurious 0x02 IRQ");
1020 } else {
1021 if (bcs->tx_skb) {
1022 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1023 hfcpci_fill_fifo(bcs);
1024 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1025 } else
1026 debugl1(cs, "fill_data %d blocked", bcs->channel);
1027 } else {
1028 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
1029 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1030 hfcpci_fill_fifo(bcs);
1031 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1032 } else
1033 debugl1(cs, "fill_data %d blocked", bcs->channel);
1034 } else {
1035 hfcpci_sched_event(bcs, B_XMTBUFREADY);
1036 }
1037 }
1038 }
1039 }
1040 if (val & 0x20) { /* receive dframe */
1041 receive_dmsg(cs);
1042 }
1043 if (val & 0x04) { /* dframe transmitted */
1044 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
1045 del_timer(&cs->dbusytimer);
1046 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
1047 sched_event_D_pci(cs, D_CLEARBUSY);
1048 if (cs->tx_skb) {
1049 if (cs->tx_skb->len) {
1050 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1051 hfcpci_fill_dfifo(cs);
1052 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1053 } else {
1054 debugl1(cs, "hfcpci_fill_dfifo irq blocked");
1055 }
1056 goto afterXPR;
1057 } else {
1058 dev_kfree_skb_irq(cs->tx_skb);
1059 cs->tx_cnt = 0;
1060 cs->tx_skb = NULL;
1061 }
1062 }
1063 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
1064 cs->tx_cnt = 0;
1065 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1066 hfcpci_fill_dfifo(cs);
1067 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1068 } else {
1069 debugl1(cs, "hfcpci_fill_dfifo irq blocked");
1070 }
1071 } else
1072 sched_event_D_pci(cs, D_XMTBUFREADY);
1073 }
1074 afterXPR:
1075 if (cs->hw.hfcpci.int_s1 && count--) {
1076 val = cs->hw.hfcpci.int_s1;
1077 cs->hw.hfcpci.int_s1 = 0;
1078 if (cs->debug & L1_DEB_ISAC)
1079 debugl1(cs, "HFC-PCI irq %x loop %d", val, 15 - count);
1080 } else
1081 val = 0;
1082 restore_flags(flags);
1083 }
1084 }
1085
1086 /********************************************************************/
1087 /* timer callback for D-chan busy resolution. Currently no function */
1088 /********************************************************************/
1089 static void
1090 hfcpci_dbusy_timer(struct IsdnCardState *cs)
1091 {
1092 }
1093
1094 /*************************************/
1095 /* Layer 1 D-channel hardware access */
1096 /*************************************/
1097 static void
1098 HFCPCI_l1hw(struct PStack *st, int pr, void *arg)
1099 {
1100 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
1101 struct sk_buff *skb = arg;
1102 int flags;
1103
1104 switch (pr) {
1105 case (PH_DATA | REQUEST):
1106 if (cs->debug & DEB_DLOG_HEX)
1107 LogFrame(cs, skb->data, skb->len);
1108 if (cs->debug & DEB_DLOG_VERBOSE)
1109 dlogframe(cs, skb, 0);
1110 if (cs->tx_skb) {
1111 skb_queue_tail(&cs->sq, skb);
1112 #ifdef L2FRAME_DEBUG /* psa */
1113 if (cs->debug & L1_DEB_LAPD)
1114 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
1115 #endif
1116 } else {
1117 cs->tx_skb = skb;
1118 cs->tx_cnt = 0;
1119 #ifdef L2FRAME_DEBUG /* psa */
1120 if (cs->debug & L1_DEB_LAPD)
1121 Logl2Frame(cs, skb, "PH_DATA", 0);
1122 #endif
1123 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1124 hfcpci_fill_dfifo(cs);
1125 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1126 } else
1127 debugl1(cs, "hfcpci_fill_dfifo blocked");
1128
1129 }
1130 break;
1131 case (PH_PULL | INDICATION):
1132 if (cs->tx_skb) {
1133 if (cs->debug & L1_DEB_WARN)
1134 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
1135 skb_queue_tail(&cs->sq, skb);
1136 break;
1137 }
1138 if (cs->debug & DEB_DLOG_HEX)
1139 LogFrame(cs, skb->data, skb->len);
1140 if (cs->debug & DEB_DLOG_VERBOSE)
1141 dlogframe(cs, skb, 0);
1142 cs->tx_skb = skb;
1143 cs->tx_cnt = 0;
1144 #ifdef L2FRAME_DEBUG /* psa */
1145 if (cs->debug & L1_DEB_LAPD)
1146 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
1147 #endif
1148 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1149 hfcpci_fill_dfifo(cs);
1150 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1151 } else
1152 debugl1(cs, "hfcpci_fill_dfifo blocked");
1153 break;
1154 case (PH_PULL | REQUEST):
1155 #ifdef L2FRAME_DEBUG /* psa */
1156 if (cs->debug & L1_DEB_LAPD)
1157 debugl1(cs, "-> PH_REQUEST_PULL");
1158 #endif
1159 if (!cs->tx_skb) {
1160 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1161 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1162 } else
1163 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1164 break;
1165 case (HW_RESET | REQUEST):
1166 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3); /* HFC ST 3 */
1167 udelay(6);
1168 Write_hfc(cs, HFCPCI_STATES, 3); /* HFC ST 2 */
1169 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1170 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1171 Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
1172 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
1173 break;
1174 case (HW_ENABLE | REQUEST):
1175 Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
1176 break;
1177 case (HW_DEACTIVATE | REQUEST):
1178 cs->hw.hfcpci.mst_m &= ~HFCPCI_MASTER;
1179 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1180 break;
1181 case (HW_INFO3 | REQUEST):
1182 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1183 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1184 break;
1185 case (HW_TESTLOOP | REQUEST):
1186 switch ((int) arg) {
1187 case (1):
1188 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* tx slot */
1189 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* rx slot */
1190 save_flags(flags);
1191 cli();
1192 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~7) | 1;
1193 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1194 restore_flags(flags);
1195 break;
1196
1197 case (2):
1198 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* tx slot */
1199 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* rx slot */
1200 save_flags(flags);
1201 cli();
1202 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~0x38) | 0x08;
1203 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1204 restore_flags(flags);
1205 break;
1206
1207 default:
1208 if (cs->debug & L1_DEB_WARN)
1209 debugl1(cs, "hfcpci_l1hw loop invalid %4x", (int) arg);
1210 return;
1211 }
1212 save_flags(flags);
1213 cli();
1214 cs->hw.hfcpci.trm |= 0x80; /* enable IOM-loop */
1215 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
1216 restore_flags(flags);
1217 break;
1218 default:
1219 if (cs->debug & L1_DEB_WARN)
1220 debugl1(cs, "hfcpci_l1hw unknown pr %4x", pr);
1221 break;
1222 }
1223 }
1224
1225 /***********************************************/
1226 /* called during init setting l1 stack pointer */
1227 /***********************************************/
1228 void
1229 setstack_hfcpci(struct PStack *st, struct IsdnCardState *cs)
1230 {
1231 st->l1.l1hw = HFCPCI_l1hw;
1232 }
1233
1234 /**************************************/
1235 /* send B-channel data if not blocked */
1236 /**************************************/
1237 static void
1238 hfcpci_send_data(struct BCState *bcs)
1239 {
1240 struct IsdnCardState *cs = bcs->cs;
1241
1242 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1243 hfcpci_fill_fifo(bcs);
1244 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1245 } else
1246 debugl1(cs, "send_data %d blocked", bcs->channel);
1247 }
1248
1249 /***************************************************************/
1250 /* activate/deactivate hardware for selected channels and mode */
1251 /***************************************************************/
1252 void
1253 mode_hfcpci(struct BCState *bcs, int mode, int bc)
1254 {
1255 struct IsdnCardState *cs = bcs->cs;
1256 bzfifo_type *bzr, *bzt;
1257 int flags, fifo2;
1258
1259 if (cs->debug & L1_DEB_HSCX)
1260 debugl1(cs, "HFCPCI bchannel mode %d bchan %d/%d",
1261 mode, bc, bcs->channel);
1262 bcs->mode = mode;
1263 bcs->channel = bc;
1264 fifo2 = bc;
1265 save_flags(flags);
1266 cli();
1267 if (cs->chanlimit > 1) {
1268 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1269 cs->hw.hfcpci.sctrl_e &= ~0x80;
1270 } else {
1271 if (bc) {
1272 if (mode != L1_MODE_NULL) {
1273 cs->hw.hfcpci.bswapped = 1; /* B1 and B2 exchanged */
1274 cs->hw.hfcpci.sctrl_e |= 0x80;
1275 } else {
1276 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1277 cs->hw.hfcpci.sctrl_e &= ~0x80;
1278 }
1279 fifo2 = 0;
1280 } else {
1281 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1282 cs->hw.hfcpci.sctrl_e &= ~0x80;
1283 }
1284 }
1285 switch (mode) {
1286 case (L1_MODE_NULL):
1287 if (bc) {
1288 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
1289 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
1290 } else {
1291 cs->hw.hfcpci.sctrl &= ~SCTRL_B1_ENA;
1292 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B1_ENA;
1293 }
1294 if (fifo2) {
1295 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1296 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1297 } else {
1298 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1299 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1300 }
1301 break;
1302 case (L1_MODE_TRANS):
1303 if (bc) {
1304 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1305 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1306 } else {
1307 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1308 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1309 }
1310 if (fifo2) {
1311 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1312 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1313 cs->hw.hfcpci.ctmt |= 2;
1314 cs->hw.hfcpci.conn &= ~0x18;
1315 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
1316 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
1317 } else {
1318 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1319 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1320 cs->hw.hfcpci.ctmt |= 1;
1321 cs->hw.hfcpci.conn &= ~0x03;
1322 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
1323 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
1324 }
1325 bzr->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
1326 bzr->za[MAX_B_FRAMES].z2 = bzr->za[MAX_B_FRAMES].z1;
1327 bzr->f1 = MAX_B_FRAMES;
1328 bzr->f2 = bzr->f1; /* init F pointers to remain constant */
1329 bzt->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
1330 bzt->za[MAX_B_FRAMES].z2 = bzt->za[MAX_B_FRAMES].z1;
1331 bzt->f1 = MAX_B_FRAMES;
1332 bzt->f2 = bzt->f1; /* init F pointers to remain constant */
1333 break;
1334 case (L1_MODE_HDLC):
1335 if (bc) {
1336 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1337 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1338 } else {
1339 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1340 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1341 }
1342 if (fifo2) {
1343 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1344 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1345 cs->hw.hfcpci.ctmt &= ~2;
1346 cs->hw.hfcpci.conn &= ~0x18;
1347 } else {
1348 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1349 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1350 cs->hw.hfcpci.ctmt &= ~1;
1351 cs->hw.hfcpci.conn &= ~0x03;
1352 }
1353 break;
1354 case (L1_MODE_EXTRN):
1355 if (bc) {
1356 cs->hw.hfcpci.conn |= 0x10;
1357 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1358 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1359 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1360 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1361 } else {
1362 cs->hw.hfcpci.conn |= 0x02;
1363 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1364 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1365 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1366 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1367 }
1368 break;
1369 }
1370 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e);
1371 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1372 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
1373 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
1374 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
1375 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
1376 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1377 restore_flags(flags);
1378 }
1379
1380 /******************************/
1381 /* Layer2 -> Layer 1 Transfer */
1382 /******************************/
1383 static void
1384 hfcpci_l2l1(struct PStack *st, int pr, void *arg)
1385 {
1386 struct sk_buff *skb = arg;
1387 long flags;
1388
1389 switch (pr) {
1390 case (PH_DATA | REQUEST):
1391 save_flags(flags);
1392 cli();
1393 if (st->l1.bcs->tx_skb) {
1394 skb_queue_tail(&st->l1.bcs->squeue, skb);
1395 restore_flags(flags);
1396 } else {
1397 st->l1.bcs->tx_skb = skb;
1398 /* test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1399 */ st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
1400 restore_flags(flags);
1401 }
1402 break;
1403 case (PH_PULL | INDICATION):
1404 if (st->l1.bcs->tx_skb) {
1405 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
1406 break;
1407 }
1408 save_flags(flags);
1409 cli();
1410 /* test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1411 */ st->l1.bcs->tx_skb = skb;
1412 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
1413 restore_flags(flags);
1414 break;
1415 case (PH_PULL | REQUEST):
1416 if (!st->l1.bcs->tx_skb) {
1417 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1418 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1419 } else
1420 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1421 break;
1422 case (PH_ACTIVATE | REQUEST):
1423 test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1424 mode_hfcpci(st->l1.bcs, st->l1.mode, st->l1.bc);
1425 l1_msg_b(st, pr, arg);
1426 break;
1427 case (PH_DEACTIVATE | REQUEST):
1428 l1_msg_b(st, pr, arg);
1429 break;
1430 case (PH_DEACTIVATE | CONFIRM):
1431 test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1432 test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1433 mode_hfcpci(st->l1.bcs, 0, st->l1.bc);
1434 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1435 break;
1436 }
1437 }
1438
1439 /******************************************/
1440 /* deactivate B-channel access and queues */
1441 /******************************************/
1442 static void
1443 close_hfcpci(struct BCState *bcs)
1444 {
1445 mode_hfcpci(bcs, 0, bcs->channel);
1446 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1447 discard_queue(&bcs->rqueue);
1448 discard_queue(&bcs->squeue);
1449 if (bcs->tx_skb) {
1450 dev_kfree_skb_any(bcs->tx_skb);
1451 bcs->tx_skb = NULL;
1452 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1453 }
1454 }
1455 }
1456
1457 /*************************************/
1458 /* init B-channel queues and control */
1459 /*************************************/
1460 static int
1461 open_hfcpcistate(struct IsdnCardState *cs, struct BCState *bcs)
1462 {
1463 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1464 skb_queue_head_init(&bcs->rqueue);
1465 skb_queue_head_init(&bcs->squeue);
1466 }
1467 bcs->tx_skb = NULL;
1468 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1469 bcs->event = 0;
1470 bcs->tx_cnt = 0;
1471 return (0);
1472 }
1473
1474 /*********************************/
1475 /* inits the stack for B-channel */
1476 /*********************************/
1477 static int
1478 setstack_2b(struct PStack *st, struct BCState *bcs)
1479 {
1480 bcs->channel = st->l1.bc;
1481 if (open_hfcpcistate(st->l1.hardware, bcs))
1482 return (-1);
1483 st->l1.bcs = bcs;
1484 st->l2.l2l1 = hfcpci_l2l1;
1485 setstack_manager(st);
1486 bcs->st = st;
1487 setstack_l1_B(st);
1488 return (0);
1489 }
1490
1491 /***************************/
1492 /* handle L1 state changes */
1493 /***************************/
1494 static void
1495 hfcpci_bh(struct IsdnCardState *cs)
1496 {
1497 int flags;
1498 /* struct PStack *stptr;
1499 */
1500 if (!cs)
1501 return;
1502 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
1503 if (!cs->hw.hfcpci.nt_mode)
1504 switch (cs->dc.hfcpci.ph_state) {
1505 case (0):
1506 l1_msg(cs, HW_RESET | INDICATION, NULL);
1507 break;
1508 case (3):
1509 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
1510 break;
1511 case (8):
1512 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
1513 break;
1514 case (6):
1515 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
1516 break;
1517 case (7):
1518 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
1519 break;
1520 default:
1521 break;
1522 } else {
1523 switch (cs->dc.hfcpci.ph_state) {
1524 case (2):
1525 save_flags(flags);
1526 cli();
1527 if (cs->hw.hfcpci.nt_timer < 0) {
1528 cs->hw.hfcpci.nt_timer = 0;
1529 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1530 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1531 /* Clear already pending ints */
1532 if (Read_hfc(cs, HFCPCI_INT_S1));
1533
1534 Write_hfc(cs, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
1535 udelay(10);
1536 Write_hfc(cs, HFCPCI_STATES, 4);
1537 cs->dc.hfcpci.ph_state = 4;
1538 } else {
1539 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_TIMER;
1540 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1541 cs->hw.hfcpci.ctmt &= ~HFCPCI_AUTO_TIMER;
1542 cs->hw.hfcpci.ctmt |= HFCPCI_TIM3_125;
1543 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1544 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1545 cs->hw.hfcpci.nt_timer = NT_T1_COUNT;
1546 Write_hfc(cs, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3); /* allow G2 -> G3 transition */
1547 }
1548 restore_flags(flags);
1549 break;
1550 case (1):
1551 case (3):
1552 case (4):
1553 save_flags(flags);
1554 cli();
1555 cs->hw.hfcpci.nt_timer = 0;
1556 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1557 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1558 restore_flags(flags);
1559 break;
1560 default:
1561 break;
1562 }
1563 }
1564 }
1565 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
1566 DChannel_proc_rcv(cs);
1567 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
1568 DChannel_proc_xmt(cs);
1569 }
1570
1571
1572 /********************************/
1573 /* called for card init message */
1574 /********************************/
1575 void __init
1576 inithfcpci(struct IsdnCardState *cs)
1577 {
1578 cs->setstack_d = setstack_hfcpci;
1579 cs->dbusytimer.function = (void *) hfcpci_dbusy_timer;
1580 cs->dbusytimer.data = (long) cs;
1581 init_timer(&cs->dbusytimer);
1582 cs->tqueue.routine = (void *) (void *) hfcpci_bh;
1583 cs->BC_Send_Data = &hfcpci_send_data;
1584 cs->bcs[0].BC_SetStack = setstack_2b;
1585 cs->bcs[1].BC_SetStack = setstack_2b;
1586 cs->bcs[0].BC_Close = close_hfcpci;
1587 cs->bcs[1].BC_Close = close_hfcpci;
1588 mode_hfcpci(cs->bcs, 0, 0);
1589 mode_hfcpci(cs->bcs + 1, 0, 1);
1590 }
1591
1592
1593
1594 /*******************************************/
1595 /* handle card messages from control layer */
1596 /*******************************************/
1597 static int
1598 hfcpci_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1599 {
1600 long flags;
1601
1602 if (cs->debug & L1_DEB_ISAC)
1603 debugl1(cs, "HFCPCI: card_msg %x", mt);
1604 switch (mt) {
1605 case CARD_RESET:
1606 reset_hfcpci(cs);
1607 return (0);
1608 case CARD_RELEASE:
1609 release_io_hfcpci(cs);
1610 return (0);
1611 case CARD_INIT:
1612 inithfcpci(cs);
1613 save_flags(flags);
1614 sti();
1615 set_current_state(TASK_UNINTERRUPTIBLE);
1616 schedule_timeout((80 * HZ) / 1000); /* Timeout 80ms */
1617 /* now switch timer interrupt off */
1618 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1619 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1620 /* reinit mode reg */
1621 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1622 restore_flags(flags);
1623 return (0);
1624 case CARD_TEST:
1625 return (0);
1626 }
1627 return (0);
1628 }
1629
1630
1631 /* this variable is used as card index when more than one cards are present */
1632 static struct pci_dev *dev_hfcpci __initdata = NULL;
1633
1634 #endif /* CONFIG_PCI */
1635
1636 int __init setup_hfcpci(struct IsdnCard *card)
1637 {
1638 struct IsdnCardState *cs = card->cs;
1639 char tmp[64];
1640 int i;
1641 struct pci_dev *tmp_hfcpci = NULL;
1642
1643 #ifdef __BIG_ENDIAN
1644 #error "not running on big endian machines now"
1645 #endif
1646 strcpy(tmp, hfcpci_revision);
1647 printk(KERN_INFO "HiSax: HFC-PCI driver Rev. %s\n", HiSax_getrev(tmp));
1648 #ifdef CONFIG_PCI
1649 cs->hw.hfcpci.int_s1 = 0;
1650 cs->dc.hfcpci.ph_state = 0;
1651 cs->hw.hfcpci.fifo = 255;
1652 if (cs->typ == ISDN_CTYPE_HFC_PCI) {
1653 i = 0;
1654 while (id_list[i].vendor_id) {
1655 tmp_hfcpci = pci_find_device(id_list[i].vendor_id,
1656 id_list[i].device_id,
1657 dev_hfcpci);
1658 i++;
1659 if (tmp_hfcpci) {
1660 if (pci_enable_device(tmp_hfcpci))
1661 continue;
1662 if ((card->para[0]) && (card->para[0] != (tmp_hfcpci->resource[ 0].start & PCI_BASE_ADDRESS_IO_MASK)))
1663 continue;
1664 else
1665 break;
1666 }
1667 }
1668
1669 if (tmp_hfcpci) {
1670 i--;
1671 dev_hfcpci = tmp_hfcpci; /* old device */
1672 cs->hw.hfcpci.pci_bus = dev_hfcpci->bus->number;
1673 cs->hw.hfcpci.pci_device_fn = dev_hfcpci->devfn;
1674 cs->irq = dev_hfcpci->irq;
1675 if (!cs->irq) {
1676 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
1677 return (0);
1678 }
1679 cs->hw.hfcpci.pci_io = (char *) dev_hfcpci->resource[ 1].start;
1680 printk(KERN_INFO "HiSax: HFC-PCI card manufacturer: %s card name: %s\n", id_list[i].vendor_name, id_list[i].card_name);
1681 } else {
1682 printk(KERN_WARNING "HFC-PCI: No PCI card found\n");
1683 return (0);
1684 }
1685 if (!cs->hw.hfcpci.pci_io) {
1686 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
1687 return (0);
1688 }
1689 /* Allocate memory for FIFOS */
1690 /* Because the HFC-PCI needs a 32K physical alignment, we */
1691 /* need to allocate the double mem and align the address */
1692 if (!((void *) cs->hw.hfcpci.share_start = kmalloc(65536, GFP_KERNEL))) {
1693 printk(KERN_WARNING "HFC-PCI: Error allocating memory for FIFO!\n");
1694 return 0;
1695 }
1696 (ulong) cs->hw.hfcpci.fifos =
1697 (((ulong) cs->hw.hfcpci.share_start) & ~0x7FFF) + 0x8000;
1698 pcibios_write_config_dword(cs->hw.hfcpci.pci_bus,
1699 cs->hw.hfcpci.pci_device_fn, 0x80,
1700 (u_int) virt_to_bus(cs->hw.hfcpci.fifos));
1701 cs->hw.hfcpci.pci_io = ioremap((ulong) cs->hw.hfcpci.pci_io, 256);
1702 printk(KERN_INFO
1703 "HFC-PCI: defined at mem %#x fifo %#x(%#x) IRQ %d HZ %d\n",
1704 (u_int) cs->hw.hfcpci.pci_io,
1705 (u_int) cs->hw.hfcpci.fifos,
1706 (u_int) virt_to_bus(cs->hw.hfcpci.fifos),
1707 cs->irq, HZ);
1708 pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */
1709 cs->hw.hfcpci.int_m2 = 0; /* disable alle interrupts */
1710 cs->hw.hfcpci.int_m1 = 0;
1711 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1712 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
1713 /* At this point the needed PCI config is done */
1714 /* fifos are still not enabled */
1715 } else
1716 return (0); /* no valid card type */
1717
1718
1719 cs->readisac = NULL;
1720 cs->writeisac = NULL;
1721 cs->readisacfifo = NULL;
1722 cs->writeisacfifo = NULL;
1723 cs->BC_Read_Reg = NULL;
1724 cs->BC_Write_Reg = NULL;
1725 cs->irq_func = &hfcpci_interrupt;
1726 cs->irq_flags |= SA_SHIRQ;
1727
1728 cs->hw.hfcpci.timer.function = (void *) hfcpci_Timer;
1729 cs->hw.hfcpci.timer.data = (long) cs;
1730 init_timer(&cs->hw.hfcpci.timer);
1731
1732 reset_hfcpci(cs);
1733 cs->cardmsg = &hfcpci_card_msg;
1734 cs->auxcmd = &hfcpci_auxcmd;
1735 return (1);
1736 #else
1737 printk(KERN_WARNING "HFC-PCI: NO_PCI_BIOS\n");
1738 return (0);
1739 #endif /* CONFIG_PCI */
1740 }
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