include/asm-sparc64/semaphore-helper.h

   1 #ifndef _SPARC64_SEMAPHORE_HELPER_H
   2 #define _SPARC64_SEMAPHORE_HELPER_H
   3
   4 /*
   5  * SMP- and interrupt-safe semaphore helper functions, sparc64 version.
   6  *
   7  * (C) Copyright 1999 David S. Miller (davem@redhat.com)
   8  * (C) Copyright 1999 Jakub Jelinek (jj@ultra.linux.cz)
   9  */
  10 #define wake_one_more(__sem)      atomic_inc(&((__sem)->waking));
  11 #define waking_non_zero(__sem)                          \
  12 ({      int __ret;                                      \
  13         __asm__ __volatile__(                           \
  14 "1:     ldsw            [%1], %%g5\n\t"                 \
  15         "brlez,pt       %%g5, 2f\n\t"                   \
  16         " mov           0, %0\n\t"                      \
  17         "sub            %%g5, 1, %%g7\n\t"              \
  18         "cas            [%1], %%g5, %%g7\n\t"           \
  19         "cmp            %%g5, %%g7\n\t"                 \
  20         "bne,pn         %%icc, 1b\n\t"                  \
  21         " mov           1, %0\n"                        \
  22 "2:"    : "=&r" (__ret)                                 \
  23         : "r" (&((__sem)->waking))                      \
  24         : "g5", "g7", "cc", "memory");                  \
  25         __ret;                                          \
  26 })
  27
  28 #define waking_non_zero_interruptible(__sem, __tsk)     \
  29 ({      int __ret;                                      \
  30         __asm__ __volatile__(                           \
  31 "1:     ldsw            [%1], %%g5\n\t"                 \
  32         "brlez,pt       %%g5, 2f\n\t"                   \
  33         " mov           0, %0\n\t"                      \
  34         "sub            %%g5, 1, %%g7\n\t"              \
  35         "cas            [%1], %%g5, %%g7\n\t"           \
  36         "cmp            %%g5, %%g7\n\t"                 \
  37         "bne,pn         %%icc, 1b\n\t"                  \
  38         " mov           1, %0\n"                        \
  39 "2:"    : "=&r" (__ret)                                 \
  40         : "r" (&((__sem)->waking))                      \
  41         : "g5", "g7", "cc", "memory");                  \
  42         if(__ret == 0 && signal_pending(__tsk)) {       \
  43                 atomic_inc(&((__sem)->count));          \
  44                 __ret = -EINTR;                         \
  45         }                                               \
  46         __ret;                                          \
  47 })
  48
  49 #define waking_non_zero_trylock(__sem)                  \
  50 ({      int __ret;                                      \
  51         __asm__ __volatile__(                           \
  52 "1:     ldsw            [%1], %%g5\n\t"                 \
  53         "brlez,pt       %%g5, 2f\n\t"                   \
  54         " mov           1, %0\n\t"                      \
  55         "sub            %%g5, 1, %%g7\n\t"              \
  56         "cas            [%1], %%g5, %%g7\n\t"           \
  57         "cmp            %%g5, %%g7\n\t"                 \
  58         "bne,pn         %%icc, 1b\n\t"                  \
  59         " mov           0, %0\n"                        \
  60 "2:"    : "=&r" (__ret)                                 \
  61         : "r" (&((__sem)->waking))                      \
  62         : "g5", "g7", "cc", "memory");                  \
  63         if(__ret == 1)                                  \
  64                 atomic_inc(&((__sem)->count));          \
  65         __ret;                                          \
  66 })
  67
  68 #endif /* !(_SPARC64_SEMAPHORE_HELPER_H) */