include/asm-sparc64/ns87303.h

   1 /* $Id: ns87303.h,v 1.2 1998/09/13 15:38:50 ecd Exp $
   2  * ns87303.h: Configuration Register Description for the
   3  *            National Semiconductor PC87303 (SuperIO).
   4  *
   5  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
   6  */
   7
   8 #ifndef _SPARC_NS87303_H
   9 #define _SPARC_NS87303_H 1
  10
  11 /*
  12  * Controll Register Index Values
  13  */
  14 #define FER     0x00
  15 #define FAR     0x01
  16 #define PTR     0x02
  17 #define FCR     0x03
  18 #define PCR     0x04
  19 #define KRR     0x05
  20 #define PMC     0x06
  21 #define TUP     0x07
  22 #define SID     0x08
  23 #define ASC     0x09
  24 #define CS0CF0  0x0a
  25 #define CS0CF1  0x0b
  26 #define CS1CF0  0x0c
  27 #define CS1CF1  0x0d
  28
  29 /* Function Enable Register (FER) bits */
  30 #define FER_EDM         0x10    /* Encoded Drive and Motor pin information   */
  31
  32 /* Function Address Register (FAR) bits */
  33 #define FAR_LPT_MASK    0x03
  34 #define FAR_LPTB        0x00
  35 #define FAR_LPTA        0x01
  36 #define FAR_LPTC        0x02
  37
  38 /* Power and Test Register (PTR) bits */
  39 #define PTR_LPTB_IRQ7   0x08
  40 #define PTR_LEVEL_IRQ   0x80    /* When not ECP/EPP: Use level IRQ           */
  41 #define PTR_LPT_REG_DIR 0x80    /* When ECP/EPP: LPT CTR controlls direction */
  42                                 /*               of the parallel port        */
  43
  44 /* Function Control Register (FCR) bits */
  45 #define FCR_LDE         0x10    /* Logical Drive Exchange                    */
  46 #define FCR_ZWS_ENA     0x20    /* Enable short host read/write in ECP/EPP   */
  47
  48 /* Printer Controll Register (PCR) bits */
  49 #define PCR_EPP_ENABLE  0x01
  50 #define PCR_EPP_IEEE    0x02    /* Enable EPP Version 1.9 (IEEE 1284)        */
  51 #define PCR_ECP_ENABLE  0x04
  52 #define PCR_ECP_CLK_ENA 0x08    /* If 0 ECP Clock is stopped on Power down   */
  53 #define PCR_IRQ_POLAR   0x20    /* If 0 IRQ is level high or negative pulse, */
  54                                 /* if 1 polarity is inverted                 */
  55 #define PCR_IRQ_ODRAIN  0x40    /* If 1, IRQ is open drain                   */
  56
  57 /* Tape UARTs and Parallel Port Config Register (TUP) bits */
  58 #define TUP_EPP_TIMO    0x02    /* Enable EPP timeout IRQ                    */
  59
  60 /* Advanced SuperIO Config Register (ASC) bits */
  61 #define ASC_LPT_IRQ7    0x01    /* Allways use IRQ7 for LPT                  */
  62 #define ASC_DRV2_SEL    0x02    /* Logical Drive Exchange controlled by TDR  */
  63
  64 #ifdef __KERNEL__
  65
  66 #include <asm/system.h>
  67 #include <asm/io.h>
  68
  69 static __inline__ void ns87303_writeb(unsigned long port, int index,
  70                                      unsigned char value)
  71 {
  72         unsigned long flags;
  73
  74         save_flags(flags); cli();
  75         outb(index, port);
  76         outb(value, port + 1);
  77         outb(value, port + 1);
  78         restore_flags(flags);
  79 }
  80
  81 static __inline__ unsigned char ns87303_readb(unsigned long port, int index)
  82 {
  83         outb(index, port);
  84         return inb(port + 1);
  85 }
  86
  87 #endif /* __KERNEL__ */
  88
  89 #endif /* !(_SPARC_NS87303_H) */