include/asm-ppc/cache.h

   1 /*
   2  * include/asm-ppc/cache.h
   3  */
   4 #ifndef __ARCH_PPC_CACHE_H
   5 #define __ARCH_PPC_CACHE_H
   6
   7 #include <linux/config.h>
   8 #include <asm/processor.h>
   9 /*#include <asm/system.h>*/
  10
  11 /* bytes per L1 cache line */
  12 #define        L1_CACHE_BYTES  32
  13 #define        L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
  14 #define L1_CACHE_PAGES          8
  15
  16 #define        SMP_CACHE_BYTES L1_CACHE_BYTES
  17
  18 #ifdef MODULE
  19 #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
  20 #else
  21 #define __cacheline_aligned                                     \
  22   __attribute__((__aligned__(L1_CACHE_BYTES),                   \
  23                  __section__(".data.cacheline_aligned")))
  24 #endif
  25
  26 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
  27 extern void flush_dcache_range(unsigned long start, unsigned long stop);
  28
  29 static inline unsigned long unlock_dcache(void)
  30 {
  31 #ifndef CONFIG_8xx
  32         ulong hid0 = 0;
  33         /* 601 doesn't do this */
  34         if ( (ulong) _get_PVR() == 1 )
  35                 return 0;
  36         asm("mfspr %0,1008 \n\t" : "=r" (hid0) );
  37         if ( !(hid0 & HID0_DLOCK) )
  38                 return 0;
  39         asm("mtspr 1008,%0 \n\t" :: "r" (hid0 & ~(HID0_DLOCK)));
  40         return (hid0 & HID0_DLOCK) ? 1 : 0;
  41 #else /* ndef CONFIG_8xx */
  42         return 0;
  43 #endif
  44 }
  45
  46 static inline void lock_dcache(unsigned long lockit)
  47 {
  48 #ifndef CONFIG_8xx
  49         /* 601 doesn't do this */
  50         if ( !lockit || ((ulong) _get_PVR() == 1) )
  51                 return;
  52         asm("mfspr      %0,1008 \n\t"
  53             "ori        %0,%0,%2 \n\t"
  54             "mtspr      1008,%0 \n\t"
  55             "sync \n\t isync \n\t"
  56             : "=r" (lockit) : "0" (lockit), "i" (HID0_DLOCK));
  57 #endif /* ndef CONFIG_8xx */
  58 }
  59
  60 #endif /* __ASSEMBLY__ */
  61
  62 /* prep registers for L2 */
  63 #define CACHECRBA       0x80000823      /* Cache configuration register address */
  64 #define L2CACHE_MASK    0x03    /* Mask for 2 L2 Cache bits */
  65 #define L2CACHE_512KB   0x00    /* 512KB */
  66 #define L2CACHE_256KB   0x01    /* 256KB */
  67 #define L2CACHE_1MB     0x02    /* 1MB */
  68 #define L2CACHE_NONE    0x03    /* NONE */
  69 #define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */
  70
  71 #ifdef CONFIG_8xx
  72 /* Cache control on the MPC8xx is provided through some additional
  73  * special purpose registers.
  74  */
  75 #define IC_CST          560     /* Instruction cache control/status */
  76 #define IC_ADR          561     /* Address needed for some commands */
  77 #define IC_DAT          562     /* Read-only data register */
  78 #define DC_CST          568     /* Data cache control/status */
  79 #define DC_ADR          569     /* Address needed for some commands */
  80 #define DC_DAT          570     /* Read-only data register */
  81
  82 /* Commands.  Only the first few are available to the instruction cache.
  83 */
  84 #define IDC_ENABLE      0x02000000      /* Cache enable */
  85 #define IDC_DISABLE     0x04000000      /* Cache disable */
  86 #define IDC_LDLCK       0x06000000      /* Load and lock */
  87 #define IDC_UNLINE      0x08000000      /* Unlock line */
  88 #define IDC_UNALL       0x0a000000      /* Unlock all */
  89 #define IDC_INVALL      0x0c000000      /* Invalidate all */
  90
  91 #define DC_FLINE        0x0e000000      /* Flush data cache line */
  92 #define DC_SFWT         0x01000000      /* Set forced writethrough mode */
  93 #define DC_CFWT         0x03000000      /* Clear forced writethrough mode */
  94 #define DC_SLES         0x05000000      /* Set little endian swap mode */
  95 #define DC_CLES         0x07000000      /* Clear little endian swap mode */
  96
  97 /* Status.
  98 */
  99 #define IDC_ENABLED     0x80000000      /* Cache is enabled */
 100 #define IDC_CERR1       0x00200000      /* Cache error 1 */
 101 #define IDC_CERR2       0x00100000      /* Cache error 2 */
 102 #define IDC_CERR3       0x00080000      /* Cache error 3 */
 103
 104 #define DC_DFWT         0x40000000      /* Data cache is forced write through */
 105 #define DC_LES          0x20000000      /* Caches are little endian mode */
 106 #endif /* CONFIG_8xx */
 107
 108 #endif