drivers/video/vga.h

   1 /*
   2  * linux/include/video/vga.h -- standard VGA chipset interaction
   3  *
   4  * Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
   5  *
   6  * Copyright history from vga16fb.c:
   7  *      Copyright 1999 Ben Pfaff and Petr Vandrovec
   8  *      Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm
   9  *      Based on VESA framebuffer (c) 1998 Gerd Knorr
  10  *
  11  * This file is subject to the terms and conditions of the GNU General
  12  * Public License.  See the file COPYING in the main directory of this
  13  * archive for more details.
  14  *
  15  */
  16
  17 #ifndef __linux_video_vga_h__
  18 #define __linux_video_vga_h__
  19
  20 #include <linux/config.h>
  21 #include <linux/types.h>
  22 #include <asm/io.h>
  23 #ifndef CONFIG_AMIGA
  24 #include <asm/vga.h>
  25 #endif
  26 #include <asm/byteorder.h>
  27
  28
  29 /* Some of the code below is taken from SVGAlib.  The original,
  30    unmodified copyright notice for that code is below. */
  31 /* VGAlib version 1.2 - (c) 1993 Tommy Frandsen                    */
  32 /*                                                                 */
  33 /* This library is free software; you can redistribute it and/or   */
  34 /* modify it without any restrictions. This library is distributed */
  35 /* in the hope that it will be useful, but without any warranty.   */
  36
  37 /* Multi-chipset support Copyright 1993 Harm Hanemaayer */
  38 /* partially copyrighted (C) 1993 by Hartmut Schirmer */
  39
  40 /* VGA data register ports */
  41 #define VGA_CRT_DC      0x3D5   /* CRT Controller Data Register - color emulation */
  42 #define VGA_CRT_DM      0x3B5   /* CRT Controller Data Register - mono emulation */
  43 #define VGA_ATT_R       0x3C1   /* Attribute Controller Data Read Register */
  44 #define VGA_ATT_W       0x3C0   /* Attribute Controller Data Write Register */
  45 #define VGA_GFX_D       0x3CF   /* Graphics Controller Data Register */
  46 #define VGA_SEQ_D       0x3C5   /* Sequencer Data Register */
  47 #define VGA_MIS_R       0x3CC   /* Misc Output Read Register */
  48 #define VGA_MIS_W       0x3C2   /* Misc Output Write Register */
  49 #define VGA_FTC_R       0x3CA   /* Feature Control Read Register */
  50 #define VGA_IS1_RC      0x3DA   /* Input Status Register 1 - color emulation */
  51 #define VGA_IS1_RM      0x3BA   /* Input Status Register 1 - mono emulation */
  52 #define VGA_PEL_D       0x3C9   /* PEL Data Register */
  53 #define VGA_PEL_MSK     0x3C6   /* PEL mask register */
  54
  55 /* EGA-specific registers */
  56 #define EGA_GFX_E0      0x3CC   /* Graphics enable processor 0 */
  57 #define EGA_GFX_E1      0x3CA   /* Graphics enable processor 1 */
  58
  59 /* VGA index register ports */
  60 #define VGA_CRT_IC      0x3D4   /* CRT Controller Index - color emulation */
  61 #define VGA_CRT_IM      0x3B4   /* CRT Controller Index - mono emulation */
  62 #define VGA_ATT_IW      0x3C0   /* Attribute Controller Index & Data Write Register */
  63 #define VGA_GFX_I       0x3CE   /* Graphics Controller Index */
  64 #define VGA_SEQ_I       0x3C4   /* Sequencer Index */
  65 #define VGA_PEL_IW      0x3C8   /* PEL Write Index */
  66 #define VGA_PEL_IR      0x3C7   /* PEL Read Index */
  67
  68 /* standard VGA indexes max counts */
  69 #define VGA_CRT_C       0x19    /* Number of CRT Controller Registers */
  70 #define VGA_ATT_C       0x15    /* Number of Attribute Controller Registers */
  71 #define VGA_GFX_C       0x09    /* Number of Graphics Controller Registers */
  72 #define VGA_SEQ_C       0x05    /* Number of Sequencer Registers */
  73 #define VGA_MIS_C       0x01    /* Number of Misc Output Register */
  74
  75 /* VGA misc register bit masks */
  76 #define VGA_MIS_COLOR           0x01
  77 #define VGA_MIS_ENB_MEM_ACCESS  0x02
  78 #define VGA_MIS_DCLK_28322_720  0x04
  79 #define VGA_MIS_ENB_PLL_LOAD    (0x04 | 0x08)
  80 #define VGA_MIS_SEL_HIGH_PAGE   0x20
  81
  82 /* VGA CRT controller register indices */
  83 #define VGA_CRTC_H_TOTAL        0
  84 #define VGA_CRTC_H_DISP         1
  85 #define VGA_CRTC_H_BLANK_START  2
  86 #define VGA_CRTC_H_BLANK_END    3
  87 #define VGA_CRTC_H_SYNC_START   4
  88 #define VGA_CRTC_H_SYNC_END     5
  89 #define VGA_CRTC_V_TOTAL        6
  90 #define VGA_CRTC_OVERFLOW       7
  91 #define VGA_CRTC_PRESET_ROW     8
  92 #define VGA_CRTC_MAX_SCAN       9
  93 #define VGA_CRTC_CURSOR_START   0x0A
  94 #define VGA_CRTC_CURSOR_END     0x0B
  95 #define VGA_CRTC_START_HI       0x0C
  96 #define VGA_CRTC_START_LO       0x0D
  97 #define VGA_CRTC_CURSOR_HI      0x0E
  98 #define VGA_CRTC_CURSOR_LO      0x0F
  99 #define VGA_CRTC_V_SYNC_START   0x10
 100 #define VGA_CRTC_V_SYNC_END     0x11
 101 #define VGA_CRTC_V_DISP_END     0x12
 102 #define VGA_CRTC_OFFSET         0x13
 103 #define VGA_CRTC_UNDERLINE      0x14
 104 #define VGA_CRTC_V_BLANK_START  0x15
 105 #define VGA_CRTC_V_BLANK_END    0x16
 106 #define VGA_CRTC_MODE           0x17
 107 #define VGA_CRTC_LINE_COMPARE   0x18
 108 #define VGA_CRTC_REGS           VGA_CRT_C
 109
 110 /* VGA CRT controller bit masks */
 111 #define VGA_CR11_LOCK_CR0_CR7   0x80 /* lock writes to CR0 - CR7 */
 112 #define VGA_CR17_H_V_SIGNALS_ENABLED 0x80
 113
 114 /* VGA attribute controller register indices */
 115 #define VGA_ATC_PALETTE0        0x00
 116 #define VGA_ATC_PALETTE1        0x01
 117 #define VGA_ATC_PALETTE2        0x02
 118 #define VGA_ATC_PALETTE3        0x03
 119 #define VGA_ATC_PALETTE4        0x04
 120 #define VGA_ATC_PALETTE5        0x05
 121 #define VGA_ATC_PALETTE6        0x06
 122 #define VGA_ATC_PALETTE7        0x07
 123 #define VGA_ATC_PALETTE8        0x08
 124 #define VGA_ATC_PALETTE9        0x09
 125 #define VGA_ATC_PALETTEA        0x0A
 126 #define VGA_ATC_PALETTEB        0x0B
 127 #define VGA_ATC_PALETTEC        0x0C
 128 #define VGA_ATC_PALETTED        0x0D
 129 #define VGA_ATC_PALETTEE        0x0E
 130 #define VGA_ATC_PALETTEF        0x0F
 131 #define VGA_ATC_MODE            0x10
 132 #define VGA_ATC_OVERSCAN        0x11
 133 #define VGA_ATC_PLANE_ENABLE    0x12
 134 #define VGA_ATC_PEL             0x13
 135 #define VGA_ATC_COLOR_PAGE      0x14
 136
 137 #define VGA_AR_ENABLE_DISPLAY   0x20
 138
 139 /* VGA sequencer register indices */
 140 #define VGA_SEQ_RESET           0x00
 141 #define VGA_SEQ_CLOCK_MODE      0x01
 142 #define VGA_SEQ_PLANE_WRITE     0x02
 143 #define VGA_SEQ_CHARACTER_MAP   0x03
 144 #define VGA_SEQ_MEMORY_MODE     0x04
 145
 146 /* VGA sequencer register bit masks */
 147 #define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */
 148 #define VGA_SR01_SCREEN_OFF     0x20 /* bit 5: Screen is off */
 149 #define VGA_SR02_ALL_PLANES     0x0F /* bits 3-0: enable access to all planes */
 150 #define VGA_SR04_EXT_MEM        0x02 /* bit 1: allows complete mem access to 256K */
 151 #define VGA_SR04_SEQ_MODE       0x04 /* bit 2: directs system to use a sequential addressing mode */
 152 #define VGA_SR04_CHN_4M         0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */
 153
 154 /* VGA graphics controller register indices */
 155 #define VGA_GFX_SR_VALUE        0x00
 156 #define VGA_GFX_SR_ENABLE       0x01
 157 #define VGA_GFX_COMPARE_VALUE   0x02
 158 #define VGA_GFX_DATA_ROTATE     0x03
 159 #define VGA_GFX_PLANE_READ      0x04
 160 #define VGA_GFX_MODE            0x05
 161 #define VGA_GFX_MISC            0x06
 162 #define VGA_GFX_COMPARE_MASK    0x07
 163 #define VGA_GFX_BIT_MASK        0x08
 164
 165 /* VGA graphics controller bit masks */
 166 #define VGA_GR06_GRAPHICS_MODE  0x01
 167
 168 /* macro for composing an 8-bit VGA register index and value
 169  * into a single 16-bit quantity */
 170 #define VGA_OUT16VAL(v, r)       (((v) << 8) | (r))
 171
 172 /* decide whether we should enable the faster 16-bit VGA register writes */
 173 #ifdef __LITTLE_ENDIAN
 174 #define VGA_OUTW_WRITE
 175 #endif
 176
 177
 178 /*
 179  * generic VGA port read/write
 180  */
 181
 182 extern inline unsigned char vga_io_r (unsigned short port)
 183 {
 184         return inb (port);
 185 }
 186
 187 extern inline void vga_io_w (unsigned short port, unsigned char val)
 188 {
 189         outb (val, port);
 190 }
 191
 192 extern inline void vga_io_w_fast (unsigned short port, unsigned char reg,
 193                                   unsigned char val)
 194 {
 195         outw (VGA_OUT16VAL (val, reg), port);
 196 }
 197
 198 extern inline unsigned char vga_mm_r (caddr_t regbase, unsigned short port)
 199 {
 200         return readb (regbase + port);
 201 }
 202
 203 extern inline void vga_mm_w (caddr_t regbase, unsigned short port, unsigned char val)
 204 {
 205         writeb (val, regbase + port);
 206 }
 207
 208 extern inline void vga_mm_w_fast (caddr_t regbase, unsigned short port,
 209                                   unsigned char reg, unsigned char val)
 210 {
 211         writew (VGA_OUT16VAL (val, reg), regbase + port);
 212 }
 213
 214 extern inline unsigned char vga_r (caddr_t regbase, unsigned short port)
 215 {
 216         if (regbase)
 217                 return vga_mm_r (regbase, port);
 218         else
 219                 return vga_io_r (port);
 220 }
 221
 222 extern inline void vga_w (caddr_t regbase, unsigned short port, unsigned char val)
 223 {
 224         if (regbase)
 225                 vga_mm_w (regbase, port, val);
 226         else
 227                 vga_io_w (port, val);
 228 }
 229
 230
 231 extern inline void vga_w_fast (caddr_t regbase, unsigned short port,
 232                                unsigned char reg, unsigned char val)
 233 {
 234         if (regbase)
 235                 vga_mm_w_fast (regbase, port, reg, val);
 236         else
 237                 vga_io_w_fast (port, reg, val);
 238 }
 239
 240
 241 /*
 242  * VGA CRTC register read/write
 243  */
 244
 245 extern inline unsigned char vga_rcrt (caddr_t regbase, unsigned char reg)
 246 {
 247         vga_w (regbase, VGA_CRT_IC, reg);
 248         return vga_r (regbase, VGA_CRT_DC);
 249 }
 250
 251 extern inline void vga_wcrt (caddr_t regbase, unsigned char reg, unsigned char val)
 252 {
 253 #ifdef VGA_OUTW_WRITE
 254         vga_w_fast (regbase, VGA_CRT_IC, reg, val);
 255 #else
 256         vga_w (regbase, VGA_CRT_IC, reg);
 257         vga_w (regbase, VGA_CRT_DC, val);
 258 #endif /* VGA_OUTW_WRITE */
 259 }
 260
 261 extern inline unsigned char vga_io_rcrt (unsigned char reg)
 262 {
 263         vga_io_w (VGA_CRT_IC, reg);
 264         return vga_io_r (VGA_CRT_DC);
 265 }
 266
 267 extern inline void vga_io_wcrt (unsigned char reg, unsigned char val)
 268 {
 269 #ifdef VGA_OUTW_WRITE
 270         vga_io_w_fast (VGA_CRT_IC, reg, val);
 271 #else
 272         vga_io_w (VGA_CRT_IC, reg);
 273         vga_io_w (VGA_CRT_DC, val);
 274 #endif /* VGA_OUTW_WRITE */
 275 }
 276
 277 extern inline unsigned char vga_mm_rcrt (caddr_t regbase, unsigned char reg)
 278 {
 279         vga_mm_w (regbase, VGA_CRT_IC, reg);
 280         return vga_mm_r (regbase, VGA_CRT_DC);
 281 }
 282
 283 extern inline void vga_mm_wcrt (caddr_t regbase, unsigned char reg, unsigned char val)
 284 {
 285 #ifdef VGA_OUTW_WRITE
 286         vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val);
 287 #else
 288         vga_mm_w (regbase, VGA_CRT_IC, reg);
 289         vga_mm_w (regbase, VGA_CRT_DC, val);
 290 #endif /* VGA_OUTW_WRITE */
 291 }
 292
 293
 294 /*
 295  * VGA sequencer register read/write
 296  */
 297
 298 extern inline unsigned char vga_rseq (caddr_t regbase, unsigned char reg)
 299 {
 300         vga_w (regbase, VGA_SEQ_I, reg);
 301         return vga_r (regbase, VGA_SEQ_D);
 302 }
 303
 304 extern inline void vga_wseq (caddr_t regbase, unsigned char reg, unsigned char val)
 305 {
 306 #ifdef VGA_OUTW_WRITE
 307         vga_w_fast (regbase, VGA_SEQ_I, reg, val);
 308 #else
 309         vga_w (regbase, VGA_SEQ_I, reg);
 310         vga_w (regbase, VGA_SEQ_D, val);
 311 #endif /* VGA_OUTW_WRITE */
 312 }
 313
 314 extern inline unsigned char vga_io_rseq (unsigned char reg)
 315 {
 316         vga_io_w (VGA_SEQ_I, reg);
 317         return vga_io_r (VGA_SEQ_D);
 318 }
 319
 320 extern inline void vga_io_wseq (unsigned char reg, unsigned char val)
 321 {
 322 #ifdef VGA_OUTW_WRITE
 323         vga_io_w_fast (VGA_SEQ_I, reg, val);
 324 #else
 325         vga_io_w (VGA_SEQ_I, reg);
 326         vga_io_w (VGA_SEQ_D, val);
 327 #endif /* VGA_OUTW_WRITE */
 328 }
 329
 330 extern inline unsigned char vga_mm_rseq (caddr_t regbase, unsigned char reg)
 331 {
 332         vga_mm_w (regbase, VGA_SEQ_I, reg);
 333         return vga_mm_r (regbase, VGA_SEQ_D);
 334 }
 335
 336 extern inline void vga_mm_wseq (caddr_t regbase, unsigned char reg, unsigned char val)
 337 {
 338 #ifdef VGA_OUTW_WRITE
 339         vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val);
 340 #else
 341         vga_mm_w (regbase, VGA_SEQ_I, reg);
 342         vga_mm_w (regbase, VGA_SEQ_D, val);
 343 #endif /* VGA_OUTW_WRITE */
 344 }
 345
 346
 347
 348 /*
 349  * VGA graphics controller register read/write
 350  */
 351
 352 extern inline unsigned char vga_rgfx (caddr_t regbase, unsigned char reg)
 353 {
 354         vga_w (regbase, VGA_GFX_I, reg);
 355         return vga_r (regbase, VGA_GFX_D);
 356 }
 357
 358 extern inline void vga_wgfx (caddr_t regbase, unsigned char reg, unsigned char val)
 359 {
 360 #ifdef VGA_OUTW_WRITE
 361         vga_w_fast (regbase, VGA_GFX_I, reg, val);
 362 #else
 363         vga_w (regbase, VGA_GFX_I, reg);
 364         vga_w (regbase, VGA_GFX_D, val);
 365 #endif /* VGA_OUTW_WRITE */
 366 }
 367
 368 extern inline unsigned char vga_io_rgfx (unsigned char reg)
 369 {
 370         vga_io_w (VGA_GFX_I, reg);
 371         return vga_io_r (VGA_GFX_D);
 372 }
 373
 374 extern inline void vga_io_wgfx (unsigned char reg, unsigned char val)
 375 {
 376 #ifdef VGA_OUTW_WRITE
 377         vga_io_w_fast (VGA_GFX_I, reg, val);
 378 #else
 379         vga_io_w (VGA_GFX_I, reg);
 380         vga_io_w (VGA_GFX_D, val);
 381 #endif /* VGA_OUTW_WRITE */
 382 }
 383
 384 extern inline unsigned char vga_mm_rgfx (caddr_t regbase, unsigned char reg)
 385 {
 386         vga_mm_w (regbase, VGA_GFX_I, reg);
 387         return vga_mm_r (regbase, VGA_GFX_D);
 388 }
 389
 390 extern inline void vga_mm_wgfx (caddr_t regbase, unsigned char reg, unsigned char val)
 391 {
 392 #ifdef VGA_OUTW_WRITE
 393         vga_mm_w_fast (regbase, VGA_GFX_I, reg, val);
 394 #else
 395         vga_mm_w (regbase, VGA_GFX_I, reg);
 396         vga_mm_w (regbase, VGA_GFX_D, val);
 397 #endif /* VGA_OUTW_WRITE */
 398 }
 399
 400
 401 /*
 402  * VGA attribute controller register read/write
 403  */
 404
 405 extern inline unsigned char vga_rattr (caddr_t regbase, unsigned char reg)
 406 {
 407         vga_w (regbase, VGA_ATT_IW, reg);
 408         return vga_r (regbase, VGA_ATT_R);
 409 }
 410
 411 extern inline void vga_wattr (caddr_t regbase, unsigned char reg, unsigned char val)
 412 {
 413         vga_w (regbase, VGA_ATT_IW, reg);
 414         vga_w (regbase, VGA_ATT_W, val);
 415 }
 416
 417 extern inline unsigned char vga_io_rattr (unsigned char reg)
 418 {
 419         vga_io_w (VGA_ATT_IW, reg);
 420         return vga_io_r (VGA_ATT_R);
 421 }
 422
 423 extern inline void vga_io_wattr (unsigned char reg, unsigned char val)
 424 {
 425         vga_io_w (VGA_ATT_IW, reg);
 426         vga_io_w (VGA_ATT_W, val);
 427 }
 428
 429 extern inline unsigned char vga_mm_rattr (caddr_t regbase, unsigned char reg)
 430 {
 431         vga_mm_w (regbase, VGA_ATT_IW, reg);
 432         return vga_mm_r (regbase, VGA_ATT_R);
 433 }
 434
 435 extern inline void vga_mm_wattr (caddr_t regbase, unsigned char reg, unsigned char val)
 436 {
 437         vga_mm_w (regbase, VGA_ATT_IW, reg);
 438         vga_mm_w (regbase, VGA_ATT_W, val);
 439 }
 440
 441
 442
 443
 444 #endif /* __linux_video_vga_h__ */