2 * Sound driver for Silicon Graphics 320 and 540 Visual Workstations'
3 * onboard audio. See notes in ../../Documentation/sound/vwsnd .
5 * Copyright 1999 Silicon Graphics, Inc. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #undef VWSND_DEBUG /* define for debugging */
28 * Rename swbuf, hwbuf, u&i, hwptr&swptr to something rational.
29 * Bug - if select() called before read(), pcm_setup() not called.
30 * Bug - output doesn't stop soon enough if process killed.
36 * Will readv/writev work? Write a test.
38 * insmod/rmmod 100 million times.
40 * Run I/O until int ptrs wrap around (roughly 6.2 hours @ DAT
43 * Concurrent threads banging on mixer simultaneously, both UP
44 * and SMP kernels. Especially, watch for thread A changing
45 * OUTSRC while thread B changes gain -- both write to the same
48 * What happens if a client opens /dev/audio then forks?
49 * Do two procs have /dev/audio open? Test.
51 * Pump audio through the CD, MIC and line inputs and verify that
52 * they mix/mute into the output.
61 * need more input apps
63 * Run tests while bombarding with signals. setitimer(2) will do it... */
66 * This driver is organized in nine sections.
67 * The nine sections are:
70 * low level lithium access
71 * high level lithium access
77 * initialization and loadable kernel module interface
79 * That is roughly the order of increasing abstraction, so forward
80 * dependencies are minimal.
86 * INC_USE_COUNT and DEC_USE_COUNT keep track of the number of
87 * open descriptors to this driver. When the driver is compiled
88 * as a module, they call MOD_{INC,DEC}_USE_COUNT; otherwise they
89 * bump vwsnd_use_count. The global device list, vwsnd_dev_list,
90 * is immutable when the IN_USE is true.
92 * devc->open_lock is a semaphore that is used to enforce the
93 * single reader/single writer rule for /dev/audio. The rule is
94 * that each device may have at most one reader and one writer.
95 * Open will block until the previous client has closed the
96 * device, unless O_NONBLOCK is specified.
98 * The semaphore devc->io_sema serializes PCM I/O syscalls. This
99 * is unnecessary in Linux 2.2, because the kernel lock
100 * serializes read, write, and ioctl globally, but it's there,
101 * ready for the brave, new post-kernel-lock world.
103 * Locking between interrupt and baselevel is handled by the
104 * "lock" spinlock in vwsnd_port (one lock each for read and
105 * write). Each half holds the lock just long enough to see what
106 * area it owns and update its pointers. See pcm_output() and
107 * pcm_input() for most of the gory stuff.
109 * devc->mix_sema serializes all mixer ioctls. This is also
110 * redundant because of the kernel lock.
112 * The lowest level lock is lith->lithium_lock. It is a
113 * spinlock which is held during the two-register tango of
114 * reading/writing an AD1843 register. See
115 * li_{read,write}_ad1843_reg().
119 * Sample Format Notes
121 * Lithium's DMA engine has two formats: 16-bit 2's complement
122 * and 8-bit unsigned . 16-bit transfers the data unmodified, 2
123 * bytes per sample. 8-bit unsigned transfers 1 byte per sample
124 * and XORs each byte with 0x80. Lithium can input or output
125 * either mono or stereo in either format.
127 * The AD1843 has four formats: 16-bit 2's complement, 8-bit
128 * unsigned, 8-bit mu-Law and 8-bit A-Law.
130 * This driver supports five formats: AFMT_S8, AFMT_U8,
131 * AFMT_MU_LAW, AFMT_A_LAW, and AFMT_S16_LE.
133 * For AFMT_U8 output, we keep the AD1843 in 16-bit mode, and
134 * rely on Lithium's XOR to translate between U8 and S8.
136 * For AFMT_S8, AFMT_MU_LAW and AFMT_A_LAW output, we have to XOR
137 * the 0x80 bit in software to compensate for Lithium's XOR.
138 * This happens in pcm_copy_{in,out}().
141 #include <linux/module.h>
142 #include <linux/stddef.h>
143 #include <linux/spinlock.h>
144 #include <asm/fixmap.h>
145 #include <asm/sgi-cobalt.h>
147 #include "sound_config.h"
149 /*****************************************************************************/
154 #include <linux/interrupt.h> /* for in_interrupt() */
156 static int shut_up
= 1;
159 * dbgassert - called when an assertion fails.
162 static void dbgassert(const char *fcn
, int line
, const char *expr
)
165 panic("ASSERTION FAILED IN INTERRUPT, %s:%s:%d %s\n",
166 __FILE__
, fcn
, line
, expr
);
169 printk(KERN_ERR
"ASSERTION FAILED, %s:%s:%d %s\n",
170 __FILE__
, fcn
, line
, expr
);
171 x
= * (volatile int *) 0; /* force proc to exit */
176 * Bunch of useful debug macros:
178 * ASSERT - print unless e nonzero (panic if in interrupt)
179 * DBGDO - include arbitrary code if debugging
180 * DBGX - debug print raw (w/o function name)
181 * DBGP - debug print w/ function name
182 * DBGE - debug print function entry
183 * DBGC - debug print function call
184 * DBGR - debug print function return
185 * DBGXV - debug print raw when verbose
186 * DBGPV - debug print when verbose
187 * DBGEV - debug print function entry when verbose
188 * DBGRV - debug print function return when verbose
191 #define ASSERT(e) ((e) ? (void) 0 : dbgassert(__FUNCTION__, __LINE__, #e))
193 #define DBGX(fmt, args...) (in_interrupt() ? 0 : printk(KERN_ERR fmt, ##args))
194 #define DBGP(fmt, args...) (DBGX(__FUNCTION__ ": " fmt, ##args))
195 #define DBGE(fmt, args...) (DBGX(__FUNCTION__ fmt, ##args))
196 #define DBGC(rtn) (DBGP("calling %s\n", rtn))
197 #define DBGR() (DBGP("returning\n"))
198 #define DBGXV(fmt, args...) (shut_up ? 0 : DBGX(fmt, ##args))
199 #define DBGPV(fmt, args...) (shut_up ? 0 : DBGP(fmt, ##args))
200 #define DBGEV(fmt, args...) (shut_up ? 0 : DBGE(fmt, ##args))
201 #define DBGCV(rtn) (shut_up ? 0 : DBGC(rtn))
202 #define DBGRV() (shut_up ? 0 : DBGR())
204 #else /* !VWSND_DEBUG */
206 #define ASSERT(e) ((void) 0)
207 #define DBGDO(x) /* don't */
208 #define DBGX(fmt, args...) ((void) 0)
209 #define DBGP(fmt, args...) ((void) 0)
210 #define DBGE(fmt, args...) ((void) 0)
211 #define DBGC(rtn) ((void) 0)
212 #define DBGR() ((void) 0)
213 #define DBGPV(fmt, args...) ((void) 0)
214 #define DBGXV(fmt, args...) ((void) 0)
215 #define DBGEV(fmt, args...) ((void) 0)
216 #define DBGCV(rtn) ((void) 0)
217 #define DBGRV() ((void) 0)
219 #endif /* !VWSND_DEBUG */
221 /*****************************************************************************/
222 /* low level lithium access */
225 * We need to talk to Lithium registers on three pages. Here are
226 * the pages' offsets from the base address (0xFF001000).
230 LI_PAGE0_OFFSET
= 0x01000 - 0x1000, /* FF001000 */
231 LI_PAGE1_OFFSET
= 0x0F000 - 0x1000, /* FF00F000 */
232 LI_PAGE2_OFFSET
= 0x10000 - 0x1000, /* FF010000 */
235 /* low-level lithium data */
237 typedef struct lithium
{
238 caddr_t page0
; /* virtual addresses */
241 spinlock_t lock
; /* protects codec and UST/MSC access */
245 * li_create initializes the lithium_t structure and sets up vm mappings
246 * to access the registers.
247 * Returns 0 on success, -errno on failure.
250 static int li_create(lithium_t
*lith
, unsigned long baseaddr
)
252 static void li_destroy(lithium_t
*);
254 lith
->lock
= SPIN_LOCK_UNLOCKED
;
255 lith
->page0
= ioremap_nocache(baseaddr
+ LI_PAGE0_OFFSET
, PAGE_SIZE
);
256 lith
->page1
= ioremap_nocache(baseaddr
+ LI_PAGE1_OFFSET
, PAGE_SIZE
);
257 lith
->page2
= ioremap_nocache(baseaddr
+ LI_PAGE2_OFFSET
, PAGE_SIZE
);
258 if (!lith
->page0
|| !lith
->page1
|| !lith
->page2
) {
266 * li_destroy destroys the lithium_t structure and vm mappings.
269 static void li_destroy(lithium_t
*lith
)
272 iounmap(lith
->page0
);
276 iounmap(lith
->page1
);
280 iounmap(lith
->page2
);
286 * basic register accessors - read/write long/byte
289 static __inline__
unsigned long li_readl(lithium_t
*lith
, int off
)
291 return * (volatile unsigned long *) (lith
->page0
+ off
);
294 static __inline__
unsigned char li_readb(lithium_t
*lith
, int off
)
296 return * (volatile unsigned char *) (lith
->page0
+ off
);
299 static __inline__
void li_writel(lithium_t
*lith
, int off
, unsigned long val
)
301 * (volatile unsigned long *) (lith
->page0
+ off
) = val
;
304 static __inline__
void li_writeb(lithium_t
*lith
, int off
, unsigned char val
)
306 * (volatile unsigned char *) (lith
->page0
+ off
) = val
;
309 /*****************************************************************************/
310 /* High Level Lithium Access */
315 * Lithium has two dedicated DMA channels for audio. They are known
316 * as comm1 and comm2 (communication areas 1 and 2). Comm1 is for
317 * input, and comm2 is for output. Each is controlled by three
318 * registers: BASE (base address), CFG (config) and CCTL
321 * Each DMA channel points to a physically contiguous ring buffer in
322 * main memory of up to 8 Kbytes. (This driver always uses 8 Kb.)
323 * There are three pointers into the ring buffer: read, write, and
324 * trigger. The pointers are 8 bits each. Each pointer points to
325 * 32-byte "chunks" of data. The DMA engine moves 32 bytes at a time,
326 * so there is no finer-granularity control.
328 * In comm1, the hardware updates the write ptr, and software updates
329 * the read ptr. In comm2, it's the opposite: hardware updates the
330 * read ptr, and software updates the write ptr. I designate the
331 * hardware-updated ptr as the hwptr, and the software-updated ptr as
334 * The trigger ptr and trigger mask are used to trigger interrupts.
335 * From the Lithium spec, section 5.6.8, revision of 12/15/1998:
339 * A three bit wide field that represents a power of two mask
340 * that is used whenever the trigger pointer is compared to its
341 * respective read or write pointer. A value of zero here
342 * implies a mask of 0xFF and a value of seven implies a mask
343 * 0x01. This value can be used to sub-divide the ring buffer
344 * into pie sections so that interrupts monitor the progress of
345 * hardware from section to section.
347 * My interpretation of that is, whenever the hw ptr is updated, it is
348 * compared with the trigger ptr, and the result is masked by the
349 * trigger mask. (Actually, by the complement of the trigger mask.)
350 * If the result is zero, an interrupt is triggered. I.e., interrupt
351 * if ((hwptr & ~mask) == (trptr & ~mask)). The mask is formed from
352 * the trigger register value as mask = (1 << (8 - tmreg)) - 1.
354 * In yet different words, setting tmreg to 0 causes an interrupt after
355 * every 256 DMA chunks (8192 bytes) or once per traversal of the
356 * ring buffer. Setting it to 7 caues an interrupt every 2 DMA chunks
357 * (64 bytes) or 128 times per traversal of the ring buffer.
360 /* Lithium register offsets and bit definitions */
362 #define LI_HOST_CONTROLLER 0x000
363 # define LI_HC_RESET 0x00008000
364 # define LI_HC_LINK_ENABLE 0x00004000
365 # define LI_HC_LINK_FAILURE 0x00000004
366 # define LI_HC_LINK_CODEC 0x00000002
367 # define LI_HC_LINK_READY 0x00000001
369 #define LI_INTR_STATUS 0x010
370 #define LI_INTR_MASK 0x014
371 # define LI_INTR_LINK_ERR 0x00008000
372 # define LI_INTR_COMM2_TRIG 0x00000008
373 # define LI_INTR_COMM2_UNDERFLOW 0x00000004
374 # define LI_INTR_COMM1_TRIG 0x00000002
375 # define LI_INTR_COMM1_OVERFLOW 0x00000001
377 #define LI_CODEC_COMMAND 0x018
378 # define LI_CC_BUSY 0x00008000
379 # define LI_CC_DIR 0x00000080
380 # define LI_CC_DIR_RD LI_CC_DIR
381 # define LI_CC_DIR_WR (!LI_CC_DIR)
382 # define LI_CC_ADDR_MASK 0x0000007F
384 #define LI_CODEC_DATA 0x01C
386 #define LI_COMM1_BASE 0x100
387 #define LI_COMM1_CTL 0x104
388 # define LI_CCTL_RESET 0x80000000
389 # define LI_CCTL_SIZE 0x70000000
390 # define LI_CCTL_DMA_ENABLE 0x08000000
391 # define LI_CCTL_TMASK 0x07000000 /* trigger mask */
392 # define LI_CCTL_TPTR 0x00FF0000 /* trigger pointer */
393 # define LI_CCTL_RPTR 0x0000FF00
394 # define LI_CCTL_WPTR 0x000000FF
395 #define LI_COMM1_CFG 0x108
396 # define LI_CCFG_LOCK 0x00008000
397 # define LI_CCFG_SLOT 0x00000070
398 # define LI_CCFG_DIRECTION 0x00000008
399 # define LI_CCFG_DIR_IN (!LI_CCFG_DIRECTION)
400 # define LI_CCFG_DIR_OUT LI_CCFG_DIRECTION
401 # define LI_CCFG_MODE 0x00000004
402 # define LI_CCFG_MODE_MONO (!LI_CCFG_MODE)
403 # define LI_CCFG_MODE_STEREO LI_CCFG_MODE
404 # define LI_CCFG_FORMAT 0x00000003
405 # define LI_CCFG_FMT_8BIT 0x00000000
406 # define LI_CCFG_FMT_16BIT 0x00000001
407 #define LI_COMM2_BASE 0x10C
408 #define LI_COMM2_CTL 0x110
409 /* bit definitions are the same as LI_COMM1_CTL */
410 #define LI_COMM2_CFG 0x114
411 /* bit definitions are the same as LI_COMM1_CFG */
413 #define LI_UST_LOW 0x200 /* 64-bit Unadjusted System Time is */
414 #define LI_UST_HIGH 0x204 /* microseconds since boot */
416 #define LI_AUDIO1_UST 0x300 /* UST-MSC pairs */
417 #define LI_AUDIO1_MSC 0x304 /* MSC (Media Stream Counter) */
418 #define LI_AUDIO2_UST 0x308 /* counts samples actually */
419 #define LI_AUDIO2_MSC 0x30C /* processed as of time UST */
422 * Lithium's DMA engine operates on chunks of 32 bytes. We call that
426 #define DMACHUNK_SHIFT 5
427 #define DMACHUNK_SIZE (1 << DMACHUNK_SHIFT)
428 #define BYTES_TO_CHUNKS(bytes) ((bytes) >> DMACHUNK_SHIFT)
429 #define CHUNKS_TO_BYTES(chunks) ((chunks) << DMACHUNK_SHIFT)
432 * Two convenient macros to shift bitfields into/out of position.
434 * Observe that (mask & -mask) is (1 << low_set_bit_of(mask)).
435 * As long as mask is constant, we trust the compiler will change the
436 * multipy and divide into shifts.
439 #define SHIFT_FIELD(val, mask) (((val) * ((mask) & -(mask))) & (mask))
440 #define UNSHIFT_FIELD(val, mask) (((val) & (mask)) / ((mask) & -(mask)))
443 * dma_chan_desc is invariant information about a Lithium
444 * DMA channel. There are two instances, li_comm1 and li_comm2.
446 * Note that the CCTL register fields are write ptr and read ptr, but what
447 * we care about are which pointer is updated by software and which by
451 typedef struct dma_chan_desc
{
459 unsigned long swptrmask
;
461 int direction
; /* LI_CCTL_DIR_IN/OUT */
464 static const dma_chan_desc_t li_comm1
= {
465 LI_COMM1_BASE
, /* base register offset */
466 LI_COMM1_CFG
, /* config register offset */
467 LI_COMM1_CTL
, /* control register offset */
468 LI_COMM1_CTL
+ 0, /* hw ptr reg offset (write ptr) */
469 LI_COMM1_CTL
+ 1, /* sw ptr reg offset (read ptr) */
470 LI_AUDIO1_UST
, /* ust reg offset */
471 LI_AUDIO1_MSC
, /* msc reg offset */
472 LI_CCTL_RPTR
, /* sw ptr bitmask in ctlval */
473 2, /* ad1843 serial slot */
474 LI_CCFG_DIR_IN
/* direction */
477 static const dma_chan_desc_t li_comm2
= {
478 LI_COMM2_BASE
, /* base register offset */
479 LI_COMM2_CFG
, /* config register offset */
480 LI_COMM2_CTL
, /* control register offset */
481 LI_COMM2_CTL
+ 1, /* hw ptr reg offset (read ptr) */
482 LI_COMM2_CTL
+ 0, /* sw ptr reg offset (writr ptr) */
483 LI_AUDIO2_UST
, /* ust reg offset */
484 LI_AUDIO2_MSC
, /* msc reg offset */
485 LI_CCTL_WPTR
, /* sw ptr bitmask in ctlval */
486 2, /* ad1843 serial slot */
487 LI_CCFG_DIR_OUT
/* direction */
491 * dma_chan is variable information about a Lithium DMA channel.
493 * The desc field points to invariant information.
494 * The lith field points to a lithium_t which is passed
495 * to li_read* and li_write* to access the registers.
496 * The *val fields shadow the lithium registers' contents.
499 typedef struct dma_chan
{
500 const dma_chan_desc_t
*desc
;
502 unsigned long baseval
;
503 unsigned long cfgval
;
504 unsigned long ctlval
;
508 * ustmsc is a UST/MSC pair (Unadjusted System Time/Media Stream Counter).
509 * UST is time in microseconds since the system booted, and MSC is a
510 * counter that increments with every audio sample.
513 typedef struct ustmsc
{
514 unsigned long long ust
;
519 * li_ad1843_wait waits until lithium says the AD1843 register
520 * exchange is not busy. Returns 0 on success, -EBUSY on timeout.
522 * Locking: must be called with lithium_lock held.
525 static int li_ad1843_wait(lithium_t
*lith
)
527 unsigned long later
= jiffies
+ 2;
528 while (li_readl(lith
, LI_CODEC_COMMAND
) & LI_CC_BUSY
)
529 if (jiffies
>= later
)
535 * li_read_ad1843_reg returns the current contents of a 16 bit AD1843 register.
537 * Returns unsigned register value on success, -errno on failure.
540 static int li_read_ad1843_reg(lithium_t
*lith
, int reg
)
544 ASSERT(!in_interrupt());
545 spin_lock(&lith
->lock
);
547 val
= li_ad1843_wait(lith
);
549 li_writel(lith
, LI_CODEC_COMMAND
, LI_CC_DIR_RD
| reg
);
550 val
= li_ad1843_wait(lith
);
553 val
= li_readl(lith
, LI_CODEC_DATA
);
555 spin_unlock(&lith
->lock
);
557 DBGXV("li_read_ad1843_reg(lith=0x%p, reg=%d) returns 0x%04x\n",
564 * li_write_ad1843_reg writes the specified value to a 16 bit AD1843 register.
567 static void li_write_ad1843_reg(lithium_t
*lith
, int reg
, int newval
)
569 spin_lock(&lith
->lock
);
571 if (li_ad1843_wait(lith
) == 0) {
572 li_writel(lith
, LI_CODEC_DATA
, newval
);
573 li_writel(lith
, LI_CODEC_COMMAND
, LI_CC_DIR_WR
| reg
);
576 spin_unlock(&lith
->lock
);
580 * li_setup_dma calculates all the register settings for DMA in a particular
581 * mode. It takes too many arguments.
584 static void li_setup_dma(dma_chan_t
*chan
,
585 const dma_chan_desc_t
*desc
,
587 unsigned long buffer_paddr
,
593 unsigned long mode
, format
;
594 unsigned long size
, tmask
;
596 DBGEV("(chan=0x%p, desc=0x%p, lith=0x%p, buffer_paddr=0x%lx, "
597 "bufshift=%d, fragshift=%d, channels=%d, sampsize=%d)\n",
598 chan
, desc
, lith
, buffer_paddr
,
599 bufshift
, fragshift
, channels
, sampsize
);
601 /* Reset the channel first. */
603 li_writel(lith
, desc
->ctlreg
, LI_CCTL_RESET
);
605 ASSERT(channels
== 1 || channels
== 2);
607 mode
= LI_CCFG_MODE_STEREO
;
609 mode
= LI_CCFG_MODE_MONO
;
610 ASSERT(sampsize
== 1 || sampsize
== 2);
612 format
= LI_CCFG_FMT_16BIT
;
614 format
= LI_CCFG_FMT_8BIT
;
619 * Lithium DMA address register takes a 40-bit physical
620 * address, right-shifted by 8 so it fits in 32 bits. Bit 37
621 * must be set -- it enables cache coherence.
624 ASSERT(!(buffer_paddr
& 0xFF));
625 chan
->baseval
= (buffer_paddr
>> 8) | 1 << (37 - 8);
627 chan
->cfgval
= (!LI_CCFG_LOCK
|
628 SHIFT_FIELD(desc
->ad1843_slot
, LI_CCFG_SLOT
) |
634 tmask
= 13 - fragshift
; /* See Lithium DMA Notes above. */
635 ASSERT(size
>= 2 && size
<= 7);
636 ASSERT(tmask
>= 1 && tmask
<= 7);
637 chan
->ctlval
= (!LI_CCTL_RESET
|
638 SHIFT_FIELD(size
, LI_CCTL_SIZE
) |
639 !LI_CCTL_DMA_ENABLE
|
640 SHIFT_FIELD(tmask
, LI_CCTL_TMASK
) |
641 SHIFT_FIELD(0, LI_CCTL_TPTR
));
643 DBGPV("basereg 0x%x = 0x%lx\n", desc
->basereg
, chan
->baseval
);
644 DBGPV("cfgreg 0x%x = 0x%lx\n", desc
->cfgreg
, chan
->cfgval
);
645 DBGPV("ctlreg 0x%x = 0x%lx\n", desc
->ctlreg
, chan
->ctlval
);
647 li_writel(lith
, desc
->basereg
, chan
->baseval
);
648 li_writel(lith
, desc
->cfgreg
, chan
->cfgval
);
649 li_writel(lith
, desc
->ctlreg
, chan
->ctlval
);
654 static void li_shutdown_dma(dma_chan_t
*chan
)
656 lithium_t
*lith
= chan
->lith
;
657 caddr_t lith1
= lith
->page1
;
659 DBGEV("(chan=0x%p)\n", chan
);
661 chan
->ctlval
&= ~LI_CCTL_DMA_ENABLE
;
662 DBGPV("ctlreg 0x%x = 0x%lx\n", chan
->desc
->ctlreg
, chan
->ctlval
);
663 li_writel(lith
, chan
->desc
->ctlreg
, chan
->ctlval
);
666 * Offset 0x500 on Lithium page 1 is an undocumented,
667 * unsupported register that holds the zero sample value.
668 * Lithium is supposed to output zero samples when DMA is
669 * inactive, and repeat the last sample when DMA underflows.
670 * But it has a bug, where, after underflow occurs, the zero
671 * sample is not reset.
673 * I expect this to break in a future rev of Lithium.
676 if (lith1
&& chan
->desc
->direction
== LI_CCFG_DIR_OUT
)
677 * (volatile unsigned long *) (lith1
+ 0x500) = 0;
681 * li_activate_dma always starts dma at the beginning of the buffer.
683 * N.B., these may be called from interrupt.
686 static __inline__
void li_activate_dma(dma_chan_t
*chan
)
688 chan
->ctlval
|= LI_CCTL_DMA_ENABLE
;
689 DBGPV("ctlval = 0x%lx\n", chan
->ctlval
);
690 li_writel(chan
->lith
, chan
->desc
->ctlreg
, chan
->ctlval
);
693 static void li_deactivate_dma(dma_chan_t
*chan
)
695 lithium_t
*lith
= chan
->lith
;
696 caddr_t lith2
= lith
->page2
;
698 chan
->ctlval
&= ~(LI_CCTL_DMA_ENABLE
| LI_CCTL_RPTR
| LI_CCTL_WPTR
);
699 DBGPV("ctlval = 0x%lx\n", chan
->ctlval
);
700 DBGPV("ctlreg 0x%x = 0x%lx\n", chan
->desc
->ctlreg
, chan
->ctlval
);
701 li_writel(lith
, chan
->desc
->ctlreg
, chan
->ctlval
);
704 * Offsets 0x98 and 0x9C on Lithium page 2 are undocumented,
705 * unsupported registers that are internal copies of the DMA
706 * read and write pointers. Because of a Lithium bug, these
707 * registers aren't zeroed correctly when DMA is shut off. So
708 * we whack them directly.
710 * I expect this to break in a future rev of Lithium.
713 if (lith2
&& chan
->desc
->direction
== LI_CCFG_DIR_OUT
) {
714 * (volatile unsigned long *) (lith2
+ 0x98) = 0;
715 * (volatile unsigned long *) (lith2
+ 0x9C) = 0;
720 * read/write the ring buffer pointers. These routines' arguments and results
721 * are byte offsets from the beginning of the ring buffer.
724 static __inline__
int li_read_swptr(dma_chan_t
*chan
)
726 const unsigned long mask
= chan
->desc
->swptrmask
;
728 return CHUNKS_TO_BYTES(UNSHIFT_FIELD(chan
->ctlval
, mask
));
731 static __inline__
int li_read_hwptr(dma_chan_t
*chan
)
733 return CHUNKS_TO_BYTES(li_readb(chan
->lith
, chan
->desc
->hwptrreg
));
736 static __inline__
void li_write_swptr(dma_chan_t
*chan
, int val
)
738 const unsigned long mask
= chan
->desc
->swptrmask
;
740 ASSERT(!(val
& ~CHUNKS_TO_BYTES(0xFF)));
741 val
= BYTES_TO_CHUNKS(val
);
742 chan
->ctlval
= (chan
->ctlval
& ~mask
) | SHIFT_FIELD(val
, mask
);
743 li_writeb(chan
->lith
, chan
->desc
->swptrreg
, val
);
746 /* li_read_USTMSC() returns a UST/MSC pair for the given channel. */
748 static void li_read_USTMSC(dma_chan_t
*chan
, ustmsc_t
*ustmsc
)
750 lithium_t
*lith
= chan
->lith
;
751 const dma_chan_desc_t
*desc
= chan
->desc
;
752 unsigned long now_low
, now_high0
, now_high1
, chan_ust
;
754 spin_lock(&lith
->lock
);
757 * retry until we do all five reads without the
758 * high word changing. (High word increments
759 * every 2^32 microseconds, i.e., not often)
762 now_high0
= li_readl(lith
, LI_UST_HIGH
);
763 now_low
= li_readl(lith
, LI_UST_LOW
);
766 * Lithium guarantees these two reads will be
767 * atomic -- ust will not increment after msc
771 ustmsc
->msc
= li_readl(lith
, desc
->mscreg
);
772 chan_ust
= li_readl(lith
, desc
->ustreg
);
774 now_high1
= li_readl(lith
, LI_UST_HIGH
);
775 } while (now_high0
!= now_high1
);
777 spin_unlock(&lith
->lock
);
778 ustmsc
->ust
= ((unsigned long long) now_high0
<< 32 | chan_ust
);
781 static void li_enable_interrupts(lithium_t
*lith
, unsigned int mask
)
783 DBGEV("(lith=0x%p, mask=0x%x)\n", lith
, mask
);
785 /* clear any already-pending interrupts. */
787 li_writel(lith
, LI_INTR_STATUS
, mask
);
789 /* enable the interrupts. */
791 mask
|= li_readl(lith
, LI_INTR_MASK
);
792 li_writel(lith
, LI_INTR_MASK
, mask
);
795 static void li_disable_interrupts(lithium_t
*lith
, unsigned int mask
)
797 unsigned int keepmask
;
799 DBGEV("(lith=0x%p, mask=0x%x)\n", lith
, mask
);
801 /* disable the interrupts */
803 keepmask
= li_readl(lith
, LI_INTR_MASK
) & ~mask
;
804 li_writel(lith
, LI_INTR_MASK
, keepmask
);
806 /* clear any pending interrupts. */
808 li_writel(lith
, LI_INTR_STATUS
, mask
);
811 /* Get the interrupt status and clear all pending interrupts. */
813 static unsigned int li_get_clear_intr_status(lithium_t
*lith
)
817 status
= li_readl(lith
, LI_INTR_STATUS
);
818 li_writel(lith
, LI_INTR_STATUS
, ~0);
819 return status
& li_readl(lith
, LI_INTR_MASK
);
822 static int li_init(lithium_t
*lith
)
824 /* 1. System power supplies stabilize. */
826 /* 2. Assert the ~RESET signal. */
828 li_writel(lith
, LI_HOST_CONTROLLER
, LI_HC_RESET
);
831 /* 3. Deassert the ~RESET signal and enter a wait period to allow
832 the AD1843 internal clocks and the external crystal oscillator
835 li_writel(lith
, LI_HOST_CONTROLLER
, LI_HC_LINK_ENABLE
);
841 /*****************************************************************************/
845 * AD1843 bitfield definitions. All are named as in the AD1843 data
846 * sheet, with ad1843_ prepended and individual bit numbers removed.
848 * E.g., bits LSS0 through LSS2 become ad1843_LSS.
850 * Only the bitfields we need are defined.
853 typedef struct ad1843_bitfield
{
859 static const ad1843_bitfield_t
860 ad1843_PDNO
= { 0, 14, 1 }, /* Converter Power-Down Flag */
861 ad1843_INIT
= { 0, 15, 1 }, /* Clock Initialization Flag */
862 ad1843_RIG
= { 2, 0, 4 }, /* Right ADC Input Gain */
863 ad1843_RMGE
= { 2, 4, 1 }, /* Right ADC Mic Gain Enable */
864 ad1843_RSS
= { 2, 5, 3 }, /* Right ADC Source Select */
865 ad1843_LIG
= { 2, 8, 4 }, /* Left ADC Input Gain */
866 ad1843_LMGE
= { 2, 12, 1 }, /* Left ADC Mic Gain Enable */
867 ad1843_LSS
= { 2, 13, 3 }, /* Left ADC Source Select */
868 ad1843_RX1M
= { 4, 0, 5 }, /* Right Aux 1 Mix Gain/Atten */
869 ad1843_RX1MM
= { 4, 7, 1 }, /* Right Aux 1 Mix Mute */
870 ad1843_LX1M
= { 4, 8, 5 }, /* Left Aux 1 Mix Gain/Atten */
871 ad1843_LX1MM
= { 4, 15, 1 }, /* Left Aux 1 Mix Mute */
872 ad1843_RX2M
= { 5, 0, 5 }, /* Right Aux 2 Mix Gain/Atten */
873 ad1843_RX2MM
= { 5, 7, 1 }, /* Right Aux 2 Mix Mute */
874 ad1843_LX2M
= { 5, 8, 5 }, /* Left Aux 2 Mix Gain/Atten */
875 ad1843_LX2MM
= { 5, 15, 1 }, /* Left Aux 2 Mix Mute */
876 ad1843_RMCM
= { 7, 0, 5 }, /* Right Mic Mix Gain/Atten */
877 ad1843_RMCMM
= { 7, 7, 1 }, /* Right Mic Mix Mute */
878 ad1843_LMCM
= { 7, 8, 5 }, /* Left Mic Mix Gain/Atten */
879 ad1843_LMCMM
= { 7, 15, 1 }, /* Left Mic Mix Mute */
880 ad1843_HPOS
= { 8, 4, 1 }, /* Headphone Output Voltage Swing */
881 ad1843_HPOM
= { 8, 5, 1 }, /* Headphone Output Mute */
882 ad1843_RDA1G
= { 9, 0, 6 }, /* Right DAC1 Analog/Digital Gain */
883 ad1843_RDA1GM
= { 9, 7, 1 }, /* Right DAC1 Analog Mute */
884 ad1843_LDA1G
= { 9, 8, 6 }, /* Left DAC1 Analog/Digital Gain */
885 ad1843_LDA1GM
= { 9, 15, 1 }, /* Left DAC1 Analog Mute */
886 ad1843_RDA1AM
= { 11, 7, 1 }, /* Right DAC1 Digital Mute */
887 ad1843_LDA1AM
= { 11, 15, 1 }, /* Left DAC1 Digital Mute */
888 ad1843_ADLC
= { 15, 0, 2 }, /* ADC Left Sample Rate Source */
889 ad1843_ADRC
= { 15, 2, 2 }, /* ADC Right Sample Rate Source */
890 ad1843_DA1C
= { 15, 8, 2 }, /* DAC1 Sample Rate Source */
891 ad1843_C1C
= { 17, 0, 16 }, /* Clock 1 Sample Rate Select */
892 ad1843_C2C
= { 20, 0, 16 }, /* Clock 1 Sample Rate Select */
893 ad1843_DAADL
= { 25, 4, 2 }, /* Digital ADC Left Source Select */
894 ad1843_DAADR
= { 25, 6, 2 }, /* Digital ADC Right Source Select */
895 ad1843_DRSFLT
= { 25, 15, 1 }, /* Digital Reampler Filter Mode */
896 ad1843_ADLF
= { 26, 0, 2 }, /* ADC Left Channel Data Format */
897 ad1843_ADRF
= { 26, 2, 2 }, /* ADC Right Channel Data Format */
898 ad1843_ADTLK
= { 26, 4, 1 }, /* ADC Transmit Lock Mode Select */
899 ad1843_SCF
= { 26, 7, 1 }, /* SCLK Frequency Select */
900 ad1843_DA1F
= { 26, 8, 2 }, /* DAC1 Data Format Select */
901 ad1843_DA1SM
= { 26, 14, 1 }, /* DAC1 Stereo/Mono Mode Select */
902 ad1843_ADLEN
= { 27, 0, 1 }, /* ADC Left Channel Enable */
903 ad1843_ADREN
= { 27, 1, 1 }, /* ADC Right Channel Enable */
904 ad1843_AAMEN
= { 27, 4, 1 }, /* Analog to Analog Mix Enable */
905 ad1843_ANAEN
= { 27, 7, 1 }, /* Analog Channel Enable */
906 ad1843_DA1EN
= { 27, 8, 1 }, /* DAC1 Enable */
907 ad1843_DA2EN
= { 27, 9, 1 }, /* DAC2 Enable */
908 ad1843_C1EN
= { 28, 11, 1 }, /* Clock Generator 1 Enable */
909 ad1843_C2EN
= { 28, 12, 1 }, /* Clock Generator 2 Enable */
910 ad1843_PDNI
= { 28, 15, 1 }; /* Converter Power Down */
913 * The various registers of the AD1843 use three different formats for
914 * specifying gain. The ad1843_gain structure parameterizes the
918 typedef struct ad1843_gain
{
920 int negative
; /* nonzero if gain is negative. */
921 const ad1843_bitfield_t
*lfield
;
922 const ad1843_bitfield_t
*rfield
;
926 static const ad1843_gain_t ad1843_gain_RECLEV
927 = { 0, &ad1843_LIG
, &ad1843_RIG
};
928 static const ad1843_gain_t ad1843_gain_LINE
929 = { 1, &ad1843_LX1M
, &ad1843_RX1M
};
930 static const ad1843_gain_t ad1843_gain_CD
931 = { 1, &ad1843_LX2M
, &ad1843_RX2M
};
932 static const ad1843_gain_t ad1843_gain_MIC
933 = { 1, &ad1843_LMCM
, &ad1843_RMCM
};
934 static const ad1843_gain_t ad1843_gain_PCM
935 = { 1, &ad1843_LDA1G
, &ad1843_RDA1G
};
937 /* read the current value of an AD1843 bitfield. */
939 static int ad1843_read_bits(lithium_t
*lith
, const ad1843_bitfield_t
*field
)
941 int w
= li_read_ad1843_reg(lith
, field
->reg
);
942 int val
= w
>> field
->lo_bit
& ((1 << field
->nbits
) - 1);
944 DBGXV("ad1843_read_bits(lith=0x%p, field->{%d %d %d}) returns 0x%x\n",
945 lith
, field
->reg
, field
->lo_bit
, field
->nbits
, val
);
951 * write a new value to an AD1843 bitfield and return the old value.
954 static int ad1843_write_bits(lithium_t
*lith
,
955 const ad1843_bitfield_t
*field
,
958 int w
= li_read_ad1843_reg(lith
, field
->reg
);
959 int mask
= ((1 << field
->nbits
) - 1) << field
->lo_bit
;
960 int oldval
= (w
& mask
) >> field
->lo_bit
;
961 int newbits
= (newval
<< field
->lo_bit
) & mask
;
962 w
= (w
& ~mask
) | newbits
;
963 (void) li_write_ad1843_reg(lith
, field
->reg
, w
);
965 DBGXV("ad1843_write_bits(lith=0x%p, field->{%d %d %d}, val=0x%x) "
967 lith
, field
->reg
, field
->lo_bit
, field
->nbits
, newval
,
974 * ad1843_read_multi reads multiple bitfields from the same AD1843
975 * register. It uses a single read cycle to do it. (Reading the
976 * ad1843 requires 256 bit times at 12.288 MHz, or nearly 20
981 * ad1843_read_multi(lith, nfields,
982 * &ad1843_FIELD1, &val1,
983 * &ad1843_FIELD2, &val2, ...);
986 static void ad1843_read_multi(lithium_t
*lith
, int argcount
, ...)
989 const ad1843_bitfield_t
*fp
;
990 int w
= 0, mask
, *value
, reg
= -1;
992 va_start(ap
, argcount
);
993 while (--argcount
>= 0) {
994 fp
= va_arg(ap
, const ad1843_bitfield_t
*);
995 value
= va_arg(ap
, int *);
998 w
= li_read_ad1843_reg(lith
, reg
);
1000 ASSERT(reg
== fp
->reg
);
1001 mask
= (1 << fp
->nbits
) - 1;
1002 *value
= w
>> fp
->lo_bit
& mask
;
1008 * ad1843_write_multi stores multiple bitfields into the same AD1843
1009 * register. It uses one read and one write cycle to do it.
1013 * ad1843_write_multi(lith, nfields,
1014 * &ad1843_FIELD1, val1,
1015 * &ad1843_FIELF2, val2, ...);
1018 static void ad1843_write_multi(lithium_t
*lith
, int argcount
, ...)
1022 const ad1843_bitfield_t
*fp
;
1024 int w
, m
, mask
, bits
;
1030 va_start(ap
, argcount
);
1031 while (--argcount
>= 0) {
1032 fp
= va_arg(ap
, const ad1843_bitfield_t
*);
1033 value
= va_arg(ap
, int);
1036 ASSERT(fp
->reg
== reg
);
1037 m
= ((1 << fp
->nbits
) - 1) << fp
->lo_bit
;
1039 bits
|= (value
<< fp
->lo_bit
) & m
;
1042 ASSERT(!(bits
& ~mask
));
1044 w
= li_read_ad1843_reg(lith
, reg
);
1047 w
= (w
& ~mask
) | bits
;
1048 (void) li_write_ad1843_reg(lith
, reg
, w
);
1052 * ad1843_get_gain reads the specified register and extracts the gain value
1053 * using the supplied gain type. It returns the gain in OSS format.
1056 static int ad1843_get_gain(lithium_t
*lith
, const ad1843_gain_t
*gp
)
1059 unsigned short mask
= (1 << gp
->lfield
->nbits
) - 1;
1061 ad1843_read_multi(lith
, 2, gp
->lfield
, &lg
, gp
->rfield
, &rg
);
1066 lg
= (lg
* 100 + (mask
>> 1)) / mask
;
1067 rg
= (rg
* 100 + (mask
>> 1)) / mask
;
1068 return lg
<< 0 | rg
<< 8;
1072 * Set an audio channel's gain. Converts from OSS format to AD1843's
1075 * Returns the new gain, which may be lower than the old gain.
1078 static int ad1843_set_gain(lithium_t
*lith
,
1079 const ad1843_gain_t
*gp
,
1082 unsigned short mask
= (1 << gp
->lfield
->nbits
) - 1;
1084 int lg
= newval
>> 0 & 0xFF;
1085 int rg
= newval
>> 8;
1086 if (lg
< 0 || lg
> 100 || rg
< 0 || rg
> 100)
1088 lg
= (lg
* mask
+ (mask
>> 1)) / 100;
1089 rg
= (rg
* mask
+ (mask
>> 1)) / 100;
1094 ad1843_write_multi(lith
, 2, gp
->lfield
, lg
, gp
->rfield
, rg
);
1095 return ad1843_get_gain(lith
, gp
);
1098 /* Returns the current recording source, in OSS format. */
1100 static int ad1843_get_recsrc(lithium_t
*lith
)
1102 int ls
= ad1843_read_bits(lith
, &ad1843_LSS
);
1106 return SOUND_MASK_MIC
;
1108 return SOUND_MASK_LINE
;
1110 return SOUND_MASK_CD
;
1112 return SOUND_MASK_PCM
;
1120 * Enable/disable digital resample mode in the AD1843.
1122 * The AD1843 requires that ADL, ADR, DA1 and DA2 be powered down
1123 * while switching modes. So we save DA1's state (DA2's state is not
1124 * interesting), power them down, switch into/out of resample mode,
1125 * power them up, and restore state.
1127 * This will cause audible glitches if D/A or A/D is going on, so the
1128 * driver disallows that (in mixer_write_ioctl()).
1130 * The open question is, is this worth doing? I'm leaving it in,
1131 * because it's written, but...
1134 static void ad1843_set_resample_mode(lithium_t
*lith
, int onoff
)
1136 /* Save DA1 mute and gain (addr 9 is DA1 analog gain/attenuation) */
1137 int save_da1
= li_read_ad1843_reg(lith
, 9);
1139 /* Power down A/D and D/A. */
1140 ad1843_write_multi(lith
, 4,
1147 ASSERT(onoff
== 0 || onoff
== 1);
1148 ad1843_write_bits(lith
, &ad1843_DRSFLT
, onoff
);
1150 /* Power up A/D and D/A. */
1151 ad1843_write_multi(lith
, 3,
1156 /* Restore DA1 mute and gain. */
1157 li_write_ad1843_reg(lith
, 9, save_da1
);
1161 * Set recording source. Arg newsrc specifies an OSS channel mask.
1163 * The complication is that when we switch into/out of loopback mode
1164 * (i.e., src = SOUND_MASK_PCM), we change the AD1843 into/out of
1165 * digital resampling mode.
1167 * Returns newsrc on success, -errno on failure.
1170 static int ad1843_set_recsrc(lithium_t
*lith
, int newsrc
)
1176 case SOUND_MASK_PCM
:
1180 case SOUND_MASK_MIC
:
1184 case SOUND_MASK_LINE
:
1195 oldbits
= ad1843_read_bits(lith
, &ad1843_LSS
);
1196 if (newsrc
== SOUND_MASK_PCM
&& oldbits
!= 6) {
1197 DBGP("enabling digital resample mode\n");
1198 ad1843_set_resample_mode(lith
, 1);
1199 ad1843_write_multi(lith
, 2,
1202 } else if (newsrc
!= SOUND_MASK_PCM
&& oldbits
== 6) {
1203 DBGP("disabling digital resample mode\n");
1204 ad1843_set_resample_mode(lith
, 0);
1205 ad1843_write_multi(lith
, 2,
1209 ad1843_write_multi(lith
, 2, &ad1843_LSS
, bits
, &ad1843_RSS
, bits
);
1214 * Return current output sources, in OSS format.
1217 static int ad1843_get_outsrc(lithium_t
*lith
)
1219 int pcm
, line
, mic
, cd
;
1221 pcm
= ad1843_read_bits(lith
, &ad1843_LDA1GM
) ? 0 : SOUND_MASK_PCM
;
1222 line
= ad1843_read_bits(lith
, &ad1843_LX1MM
) ? 0 : SOUND_MASK_LINE
;
1223 cd
= ad1843_read_bits(lith
, &ad1843_LX2MM
) ? 0 : SOUND_MASK_CD
;
1224 mic
= ad1843_read_bits(lith
, &ad1843_LMCMM
) ? 0 : SOUND_MASK_MIC
;
1226 return pcm
| line
| cd
| mic
;
1230 * Set output sources. Arg is a mask of active sources in OSS format.
1232 * Returns source mask on success, -errno on failure.
1235 static int ad1843_set_outsrc(lithium_t
*lith
, int mask
)
1237 int pcm
, line
, mic
, cd
;
1239 if (mask
& ~(SOUND_MASK_PCM
| SOUND_MASK_LINE
|
1240 SOUND_MASK_CD
| SOUND_MASK_MIC
))
1242 pcm
= (mask
& SOUND_MASK_PCM
) ? 0 : 1;
1243 line
= (mask
& SOUND_MASK_LINE
) ? 0 : 1;
1244 mic
= (mask
& SOUND_MASK_MIC
) ? 0 : 1;
1245 cd
= (mask
& SOUND_MASK_CD
) ? 0 : 1;
1247 ad1843_write_multi(lith
, 2, &ad1843_LDA1GM
, pcm
, &ad1843_RDA1GM
, pcm
);
1248 ad1843_write_multi(lith
, 2, &ad1843_LX1MM
, line
, &ad1843_RX1MM
, line
);
1249 ad1843_write_multi(lith
, 2, &ad1843_LX2MM
, cd
, &ad1843_RX2MM
, cd
);
1250 ad1843_write_multi(lith
, 2, &ad1843_LMCMM
, mic
, &ad1843_RMCMM
, mic
);
1255 /* Setup ad1843 for D/A conversion. */
1257 static void ad1843_setup_dac(lithium_t
*lith
,
1262 int ad_fmt
= 0, ad_mode
= 0;
1264 DBGEV("(lith=0x%p, framerate=%d, fmt=%d, channels=%d)\n",
1265 lith
, framerate
, fmt
, channels
);
1268 case AFMT_S8
: ad_fmt
= 1; break;
1269 case AFMT_U8
: ad_fmt
= 1; break;
1270 case AFMT_S16_LE
: ad_fmt
= 1; break;
1271 case AFMT_MU_LAW
: ad_fmt
= 2; break;
1272 case AFMT_A_LAW
: ad_fmt
= 3; break;
1277 case 2: ad_mode
= 0; break;
1278 case 1: ad_mode
= 1; break;
1282 DBGPV("ad_mode = %d, ad_fmt = %d\n", ad_mode
, ad_fmt
);
1283 ASSERT(framerate
>= 4000 && framerate
<= 49000);
1284 ad1843_write_bits(lith
, &ad1843_C1C
, framerate
);
1285 ad1843_write_multi(lith
, 2,
1286 &ad1843_DA1SM
, ad_mode
, &ad1843_DA1F
, ad_fmt
);
1289 static void ad1843_shutdown_dac(lithium_t
*lith
)
1291 ad1843_write_bits(lith
, &ad1843_DA1F
, 1);
1294 static void ad1843_setup_adc(lithium_t
*lith
, int framerate
, int fmt
, int channels
)
1298 DBGEV("(lith=0x%p, framerate=%d, fmt=%d, channels=%d)\n",
1299 lith
, framerate
, fmt
, channels
);
1302 case AFMT_S8
: da_fmt
= 1; break;
1303 case AFMT_U8
: da_fmt
= 1; break;
1304 case AFMT_S16_LE
: da_fmt
= 1; break;
1305 case AFMT_MU_LAW
: da_fmt
= 2; break;
1306 case AFMT_A_LAW
: da_fmt
= 3; break;
1310 DBGPV("da_fmt = %d\n", da_fmt
);
1311 ASSERT(framerate
>= 4000 && framerate
<= 49000);
1312 ad1843_write_bits(lith
, &ad1843_C2C
, framerate
);
1313 ad1843_write_multi(lith
, 2,
1314 &ad1843_ADLF
, da_fmt
, &ad1843_ADRF
, da_fmt
);
1317 static void ad1843_shutdown_adc(lithium_t
*lith
)
1323 * Fully initialize the ad1843. As described in the AD1843 data
1324 * sheet, section "START-UP SEQUENCE". The numbered comments are
1325 * subsection headings from the data sheet. See the data sheet, pages
1326 * 52-54, for more info.
1328 * return 0 on success, -errno on failure. */
1330 static int ad1843_init(lithium_t
*lith
)
1332 unsigned long later
;
1335 err
= li_init(lith
);
1339 if (ad1843_read_bits(lith
, &ad1843_INIT
) != 0) {
1340 printk(KERN_ERR
"vwsnd sound: AD1843 won't initialize\n");
1344 ad1843_write_bits(lith
, &ad1843_SCF
, 1);
1346 /* 4. Put the conversion resources into standby. */
1348 ad1843_write_bits(lith
, &ad1843_PDNI
, 0);
1349 later
= jiffies
+ HZ
/ 2; /* roughly half a second */
1351 while (ad1843_read_bits(lith
, &ad1843_PDNO
)) {
1352 if (jiffies
> later
) {
1354 "vwsnd audio: AD1843 won't power up\n");
1361 /* 5. Power up the clock generators and enable clock output pins. */
1363 ad1843_write_multi(lith
, 2, &ad1843_C1EN
, 1, &ad1843_C2EN
, 1);
1365 /* 6. Configure conversion resources while they are in standby. */
1367 /* DAC1 uses clock 1 as source, ADC uses clock 2. Always. */
1369 ad1843_write_multi(lith
, 3,
1374 /* 7. Enable conversion resources. */
1376 ad1843_write_bits(lith
, &ad1843_ADTLK
, 1);
1377 ad1843_write_multi(lith
, 5,
1384 /* 8. Configure conversion resources while they are enabled. */
1386 ad1843_write_bits(lith
, &ad1843_DA1C
, 1);
1388 /* Unmute all channels. */
1390 ad1843_set_outsrc(lith
,
1391 (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
1392 SOUND_MASK_MIC
| SOUND_MASK_CD
));
1393 ad1843_write_multi(lith
, 2, &ad1843_LDA1AM
, 0, &ad1843_RDA1AM
, 0);
1395 /* Set default recording source to Line In and set
1396 * mic gain to +20 dB.
1399 ad1843_set_recsrc(lith
, SOUND_MASK_LINE
);
1400 ad1843_write_multi(lith
, 2, &ad1843_LMGE
, 1, &ad1843_RMGE
, 1);
1402 /* Set Speaker Out level to +/- 4V and unmute it. */
1404 ad1843_write_multi(lith
, 2, &ad1843_HPOS
, 1, &ad1843_HPOM
, 0);
1409 /*****************************************************************************/
1412 #define READ_INTR_MASK (LI_INTR_COMM1_TRIG | LI_INTR_COMM1_OVERFLOW)
1413 #define WRITE_INTR_MASK (LI_INTR_COMM2_TRIG | LI_INTR_COMM2_UNDERFLOW)
1415 typedef enum vwsnd_port_swstate
{ /* software state */
1420 } vwsnd_port_swstate_t
;
1422 typedef enum vwsnd_port_hwstate
{ /* hardware state */
1425 } vwsnd_port_hwstate_t
;
1428 * These flags are read by ISR, but only written at baseline.
1431 typedef enum vwsnd_port_flags
{
1433 ERFLOWN
= 1 << 1, /* overflown or underflown */
1435 } vwsnd_port_flags_t
;
1438 * vwsnd_port is the per-port data structure. Each device has two
1439 * ports, one for input and one for output.
1443 * port->lock protects: hwstate, flags, swb_[iu]_avail.
1445 * devc->io_sema protects: swstate, sw_*, swb_[iu]_idx.
1447 * everything else is only written by open/release or
1448 * pcm_{setup,shutdown}(), which are serialized by a
1449 * combination of devc->open_sema and devc->io_sema.
1452 typedef struct vwsnd_port
{
1455 wait_queue_head_t queue
;
1456 vwsnd_port_swstate_t swstate
;
1457 vwsnd_port_hwstate_t hwstate
;
1458 vwsnd_port_flags_t flags
;
1465 unsigned int zero_word
; /* zero for the sample format */
1471 unsigned int hw_fragshift
;
1472 unsigned int hw_fragsize
;
1473 unsigned int hw_fragcount
;
1476 unsigned long hwbuf_paddr
;
1477 unsigned long hwbuf_vaddr
;
1478 caddr_t hwbuf
; /* hwbuf == hwbuf_vaddr */
1479 int hwbuf_max
; /* max bytes to preload */
1482 unsigned int swbuf_size
; /* size in bytes */
1483 unsigned int swb_u_idx
; /* index of next user byte */
1484 unsigned int swb_i_idx
; /* index of next intr byte */
1485 unsigned int swb_u_avail
; /* # bytes avail to user */
1486 unsigned int swb_i_avail
; /* # bytes avail to intr */
1498 /* vwsnd_dev is the per-device data structure. */
1500 typedef struct vwsnd_dev
{
1501 struct vwsnd_dev
*next_dev
;
1502 int audio_minor
; /* minor number of audio device */
1503 int mixer_minor
; /* minor number of mixer device */
1505 struct semaphore open_sema
;
1506 struct semaphore io_sema
;
1507 struct semaphore mix_sema
;
1509 wait_queue_head_t open_wait
;
1517 static vwsnd_dev_t
*vwsnd_dev_list
; /* linked list of all devices */
1521 # define INC_USE_COUNT MOD_INC_USE_COUNT
1522 # define DEC_USE_COUNT MOD_DEC_USE_COUNT
1523 # define IN_USE MOD_IN_USE
1527 static atomic_t vwsnd_use_count
= ATOMIC_INIT(0);
1529 # define INC_USE_COUNT (atomic_inc(&vwsnd_use_count))
1530 # define DEC_USE_COUNT (atomic_dec(&vwsnd_use_count))
1531 # define IN_USE (atomic_read(&vwsnd_use_count) != 0)
1536 * Lithium can only DMA multiples of 32 bytes. Its DMA buffer may
1537 * be up to 8 Kb. This driver always uses 8 Kb.
1539 * Memory bug workaround -- I'm not sure what's going on here, but
1540 * somehow pcm_copy_out() was triggering segv's going on to the next
1541 * page of the hw buffer. So, I make the hw buffer one size bigger
1542 * than we actually use. That way, the following page is allocated
1543 * and mapped, and no error. I suspect that something is broken
1544 * in Cobalt, but haven't really investigated. HBO is the actual
1545 * size of the buffer, and HWBUF_ORDER is what we allocate.
1548 #define HWBUF_SHIFT 13
1549 #define HWBUF_SIZE (1 << HWBUF_SHIFT)
1550 # define HBO (HWBUF_SHIFT > PAGE_SHIFT ? HWBUF_SHIFT - PAGE_SHIFT : 0)
1551 # define HWBUF_ORDER (HBO + 1) /* next size bigger */
1552 #define MIN_SPEED 4000
1553 #define MAX_SPEED 49000
1555 #define MIN_FRAGSHIFT (DMACHUNK_SHIFT + 1)
1556 #define MAX_FRAGSHIFT (PAGE_SHIFT)
1557 #define MIN_FRAGSIZE (1 << MIN_FRAGSHIFT)
1558 #define MAX_FRAGSIZE (1 << MAX_FRAGSHIFT)
1559 #define MIN_FRAGCOUNT(fragsize) 3
1560 #define MAX_FRAGCOUNT(fragsize) (32 * PAGE_SIZE / (fragsize))
1561 #define DEFAULT_FRAGSHIFT 12
1562 #define DEFAULT_FRAGCOUNT 16
1563 #define DEFAULT_SUBDIVSHIFT 0
1566 * The software buffer (swbuf) is a ring buffer shared between user
1567 * level and interrupt level. Each level owns some of the bytes in
1568 * the buffer, and may give bytes away by calling swb_inc_{u,i}().
1569 * User level calls _u for user, and interrupt level calls _i for
1572 * port->swb_{u,i}_avail is the number of bytes available to that level.
1574 * port->swb_{u,i}_idx is the index of the first available byte in the
1577 * Each level calls swb_inc_{u,i}() to atomically increment its index,
1578 * recalculate the number of bytes available for both sides, and
1579 * return the number of bytes available. Since each side can only
1580 * give away bytes, the other side can only increase the number of
1581 * bytes available to this side. Each side updates its own index
1582 * variable, swb_{u,i}_idx, so no lock is needed to read it.
1584 * To query the number of bytes available, call swb_inc_{u,i} with an
1585 * increment of zero.
1588 static __inline__
unsigned int __swb_inc_u(vwsnd_port_t
*port
, int inc
)
1591 port
->swb_u_idx
+= inc
;
1592 port
->swb_u_idx
%= port
->swbuf_size
;
1593 port
->swb_u_avail
-= inc
;
1594 port
->swb_i_avail
+= inc
;
1596 return port
->swb_u_avail
;
1599 static __inline__
unsigned int swb_inc_u(vwsnd_port_t
*port
, int inc
)
1601 unsigned long flags
;
1604 spin_lock_irqsave(&port
->lock
, flags
);
1606 ret
= __swb_inc_u(port
, inc
);
1608 spin_unlock_irqrestore(&port
->lock
, flags
);
1612 static __inline__
unsigned int __swb_inc_i(vwsnd_port_t
*port
, int inc
)
1615 port
->swb_i_idx
+= inc
;
1616 port
->swb_i_idx
%= port
->swbuf_size
;
1617 port
->swb_i_avail
-= inc
;
1618 port
->swb_u_avail
+= inc
;
1620 return port
->swb_i_avail
;
1623 static __inline__
unsigned int swb_inc_i(vwsnd_port_t
*port
, int inc
)
1625 unsigned long flags
;
1628 spin_lock_irqsave(&port
->lock
, flags
);
1630 ret
= __swb_inc_i(port
, inc
);
1632 spin_unlock_irqrestore(&port
->lock
, flags
);
1637 * pcm_setup - this routine initializes all port state after
1638 * mode-setting ioctls have been done, but before the first I/O is
1641 * Locking: called with devc->io_sema held.
1643 * Returns 0 on success, -errno on failure.
1646 static int pcm_setup(vwsnd_dev_t
*devc
,
1647 vwsnd_port_t
*rport
,
1648 vwsnd_port_t
*wport
)
1650 vwsnd_port_t
*aport
= rport
? rport
: wport
;
1652 unsigned int zero_word
;
1654 DBGEV("(devc=0x%p, rport=0x%p, wport=0x%p)\n", devc
, rport
, wport
);
1656 ASSERT(aport
!= NULL
);
1657 if (aport
->swbuf
!= NULL
)
1659 switch (aport
->sw_samplefmt
) {
1662 zero_word
= 0xFFFFFFFF ^ 0x80808080;
1667 zero_word
= 0xD5D5D5D5 ^ 0x80808080;
1672 zero_word
= 0x80808080;
1677 zero_word
= 0x00000000;
1682 zero_word
= 0x00000000;
1686 sample_size
= 0; /* prevent compiler warning */
1690 aport
->sample_size
= sample_size
;
1691 aport
->zero_word
= zero_word
;
1692 aport
->frame_size
= aport
->sw_channels
* aport
->sample_size
;
1693 aport
->hw_fragshift
= aport
->sw_fragshift
- aport
->sw_subdivshift
;
1694 aport
->hw_fragsize
= 1 << aport
->hw_fragshift
;
1695 aport
->hw_fragcount
= aport
->sw_fragcount
<< aport
->sw_subdivshift
;
1696 ASSERT(aport
->hw_fragsize
>= MIN_FRAGSIZE
);
1697 ASSERT(aport
->hw_fragsize
<= MAX_FRAGSIZE
);
1698 ASSERT(aport
->hw_fragcount
>= MIN_FRAGCOUNT(aport
->hw_fragsize
));
1699 ASSERT(aport
->hw_fragcount
<= MAX_FRAGCOUNT(aport
->hw_fragsize
));
1701 int hwfrags
, swfrags
;
1702 rport
->hwbuf_max
= aport
->hwbuf_size
- DMACHUNK_SIZE
;
1703 hwfrags
= rport
->hwbuf_max
>> aport
->hw_fragshift
;
1704 swfrags
= aport
->hw_fragcount
- hwfrags
;
1707 rport
->swbuf_size
= swfrags
* aport
->hw_fragsize
;
1708 DBGPV("hwfrags = %d, swfrags = %d\n", hwfrags
, swfrags
);
1709 DBGPV("read hwbuf_max = %d, swbuf_size = %d\n",
1710 rport
->hwbuf_max
, rport
->swbuf_size
);
1713 int hwfrags
, swfrags
;
1714 int total_bytes
= aport
->hw_fragcount
* aport
->hw_fragsize
;
1715 wport
->hwbuf_max
= aport
->hwbuf_size
- DMACHUNK_SIZE
;
1716 if (wport
->hwbuf_max
> total_bytes
)
1717 wport
->hwbuf_max
= total_bytes
;
1718 hwfrags
= wport
->hwbuf_max
>> aport
->hw_fragshift
;
1719 DBGPV("hwfrags = %d\n", hwfrags
);
1720 swfrags
= aport
->hw_fragcount
- hwfrags
;
1723 wport
->swbuf_size
= swfrags
* aport
->hw_fragsize
;
1724 DBGPV("hwfrags = %d, swfrags = %d\n", hwfrags
, swfrags
);
1725 DBGPV("write hwbuf_max = %d, swbuf_size = %d\n",
1726 wport
->hwbuf_max
, wport
->swbuf_size
);
1729 aport
->swb_u_idx
= 0;
1730 aport
->swb_i_idx
= 0;
1731 aport
->byte_count
= 0;
1734 * Is this a Cobalt bug? We need to make this buffer extend
1735 * one page further than we actually use -- somehow memcpy
1736 * causes an exceptoin otherwise. I suspect there's a bug in
1737 * Cobalt (or somewhere) where it's generating a fault on a
1738 * speculative load or something. Obviously, I haven't taken
1739 * the time to track it down.
1742 aport
->swbuf
= vmalloc(aport
->swbuf_size
+ PAGE_SIZE
);
1745 if (rport
&& wport
) {
1746 ASSERT(aport
== rport
);
1747 ASSERT(wport
->swbuf
== NULL
);
1748 /* One extra page - see comment above. */
1749 wport
->swbuf
= vmalloc(aport
->swbuf_size
+ PAGE_SIZE
);
1750 if (!wport
->swbuf
) {
1751 vfree(aport
->swbuf
);
1752 aport
->swbuf
= NULL
;
1755 wport
->sample_size
= rport
->sample_size
;
1756 wport
->zero_word
= rport
->zero_word
;
1757 wport
->frame_size
= rport
->frame_size
;
1758 wport
->hw_fragshift
= rport
->hw_fragshift
;
1759 wport
->hw_fragsize
= rport
->hw_fragsize
;
1760 wport
->hw_fragcount
= rport
->hw_fragcount
;
1761 wport
->swbuf_size
= rport
->swbuf_size
;
1762 wport
->hwbuf_max
= rport
->hwbuf_max
;
1763 wport
->swb_u_idx
= rport
->swb_u_idx
;
1764 wport
->swb_i_idx
= rport
->swb_i_idx
;
1765 wport
->byte_count
= rport
->byte_count
;
1768 rport
->swb_u_avail
= 0;
1769 rport
->swb_i_avail
= rport
->swbuf_size
;
1770 rport
->swstate
= SW_RUN
;
1771 li_setup_dma(&rport
->chan
,
1776 rport
->hw_fragshift
,
1778 rport
->sample_size
);
1779 ad1843_setup_adc(&devc
->lith
,
1780 rport
->sw_framerate
,
1781 rport
->sw_samplefmt
,
1782 rport
->sw_channels
);
1783 li_enable_interrupts(&devc
->lith
, READ_INTR_MASK
);
1784 if (!(rport
->flags
& DISABLED
)) {
1786 rport
->hwstate
= HW_RUNNING
;
1787 li_activate_dma(&rport
->chan
);
1788 li_read_USTMSC(&rport
->chan
, &ustmsc
);
1789 rport
->MSC_offset
= ustmsc
.msc
;
1793 if (wport
->hwbuf_max
> wport
->swbuf_size
)
1794 wport
->hwbuf_max
= wport
->swbuf_size
;
1795 wport
->flags
&= ~ERFLOWN
;
1796 wport
->swb_u_avail
= wport
->swbuf_size
;
1797 wport
->swb_i_avail
= 0;
1798 wport
->swstate
= SW_RUN
;
1799 li_setup_dma(&wport
->chan
,
1804 wport
->hw_fragshift
,
1806 wport
->sample_size
);
1807 ad1843_setup_dac(&devc
->lith
,
1808 wport
->sw_framerate
,
1809 wport
->sw_samplefmt
,
1810 wport
->sw_channels
);
1811 li_enable_interrupts(&devc
->lith
, WRITE_INTR_MASK
);
1818 * pcm_shutdown_port - shut down one port (direction) for PCM I/O.
1819 * Only called from pcm_shutdown.
1822 static void pcm_shutdown_port(vwsnd_dev_t
*devc
,
1823 vwsnd_port_t
*aport
,
1826 unsigned long flags
;
1827 vwsnd_port_hwstate_t hwstate
;
1828 DECLARE_WAITQUEUE(wait
, current
);
1830 aport
->swstate
= SW_INITIAL
;
1831 add_wait_queue(&aport
->queue
, &wait
);
1832 current
->state
= TASK_UNINTERRUPTIBLE
;
1834 spin_lock_irqsave(&aport
->lock
, flags
);
1836 hwstate
= aport
->hwstate
;
1838 spin_unlock_irqrestore(&aport
->lock
, flags
);
1839 if (hwstate
== HW_STOPPED
)
1843 current
->state
= TASK_RUNNING
;
1844 remove_wait_queue(&aport
->queue
, &wait
);
1845 li_disable_interrupts(&devc
->lith
, mask
);
1846 if (aport
== &devc
->rport
)
1847 ad1843_shutdown_adc(&devc
->lith
);
1848 else /* aport == &devc->wport) */
1849 ad1843_shutdown_dac(&devc
->lith
);
1850 li_shutdown_dma(&aport
->chan
);
1851 vfree(aport
->swbuf
);
1852 aport
->swbuf
= NULL
;
1853 aport
->byte_count
= 0;
1857 * pcm_shutdown undoes what pcm_setup did.
1858 * Also sets the ports' swstate to newstate.
1861 static void pcm_shutdown(vwsnd_dev_t
*devc
,
1862 vwsnd_port_t
*rport
,
1863 vwsnd_port_t
*wport
)
1865 DBGEV("(devc=0x%p, rport=0x%p, wport=0x%p)\n", devc
, rport
, wport
);
1867 if (rport
&& rport
->swbuf
) {
1868 DBGPV("shutting down rport\n");
1869 pcm_shutdown_port(devc
, rport
, READ_INTR_MASK
);
1871 if (wport
&& wport
->swbuf
) {
1872 DBGPV("shutting down wport\n");
1873 pcm_shutdown_port(devc
, wport
, WRITE_INTR_MASK
);
1878 static void pcm_copy_in(vwsnd_port_t
*rport
, int swidx
, int hwidx
, int nb
)
1880 char *src
= rport
->hwbuf
+ hwidx
;
1881 char *dst
= rport
->swbuf
+ swidx
;
1882 int fmt
= rport
->sw_samplefmt
;
1884 DBGPV("swidx = %d, hwidx = %d\n", swidx
, hwidx
);
1885 ASSERT(rport
->hwbuf
!= NULL
);
1886 ASSERT(rport
->swbuf
!= NULL
);
1887 ASSERT(nb
> 0 && (nb
% 32) == 0);
1888 ASSERT(swidx
% 32 == 0 && hwidx
% 32 == 0);
1889 ASSERT(swidx
>= 0 && swidx
+ nb
<= rport
->swbuf_size
);
1890 ASSERT(hwidx
>= 0 && hwidx
+ nb
<= rport
->hwbuf_size
);
1892 if (fmt
== AFMT_MU_LAW
|| fmt
== AFMT_A_LAW
|| fmt
== AFMT_S8
) {
1894 /* See Sample Format Notes above. */
1896 char *end
= src
+ nb
;
1898 *dst
++ = *src
++ ^ 0x80;
1900 memcpy(dst
, src
, nb
);
1903 static void pcm_copy_out(vwsnd_port_t
*wport
, int swidx
, int hwidx
, int nb
)
1905 char *src
= wport
->swbuf
+ swidx
;
1906 char *dst
= wport
->hwbuf
+ hwidx
;
1907 int fmt
= wport
->sw_samplefmt
;
1909 ASSERT(nb
> 0 && (nb
% 32) == 0);
1910 ASSERT(wport
->hwbuf
!= NULL
);
1911 ASSERT(wport
->swbuf
!= NULL
);
1912 ASSERT(swidx
% 32 == 0 && hwidx
% 32 == 0);
1913 ASSERT(swidx
>= 0 && swidx
+ nb
<= wport
->swbuf_size
);
1914 ASSERT(hwidx
>= 0 && hwidx
+ nb
<= wport
->hwbuf_size
);
1915 if (fmt
== AFMT_MU_LAW
|| fmt
== AFMT_A_LAW
|| fmt
== AFMT_S8
) {
1917 /* See Sample Format Notes above. */
1919 char *end
= src
+ nb
;
1921 *dst
++ = *src
++ ^ 0x80;
1923 memcpy(dst
, src
, nb
);
1927 * pcm_output() is called both from baselevel and from interrupt level.
1928 * This is where audio frames are copied into the hardware-accessible
1931 * Locking note: The part of this routine that figures out what to do
1932 * holds wport->lock. The longer part releases wport->lock, but sets
1933 * wport->flags & HW_BUSY. Afterward, it reacquires wport->lock, and
1934 * checks for more work to do.
1936 * If another thread calls pcm_output() while HW_BUSY is set, it
1937 * returns immediately, knowing that the thread that set HW_BUSY will
1938 * look for more work to do before returning.
1940 * This has the advantage that port->lock is held for several short
1941 * periods instead of one long period. Also, when pcm_output is
1942 * called from base level, it reenables interrupts.
1945 static void pcm_output(vwsnd_dev_t
*devc
, int erflown
, int nb
)
1947 vwsnd_port_t
*wport
= &devc
->wport
;
1948 const int hwmax
= wport
->hwbuf_max
;
1949 const int hwsize
= wport
->hwbuf_size
;
1950 const int swsize
= wport
->swbuf_size
;
1951 const int fragsize
= wport
->hw_fragsize
;
1952 unsigned long iflags
;
1954 DBGEV("(devc=0x%p, erflown=%d, nb=%d)\n", devc
, erflown
, nb
);
1955 spin_lock_irqsave(&wport
->lock
, iflags
);
1957 wport
->flags
|= ERFLOWN
;
1958 (void) __swb_inc_u(wport
, nb
);
1959 if (wport
->flags
& HW_BUSY
) {
1960 spin_unlock_irqrestore(&wport
->lock
, iflags
);
1961 DBGPV("returning: HW BUSY\n");
1964 if (wport
->flags
& DISABLED
) {
1965 spin_unlock_irqrestore(&wport
->lock
, iflags
);
1966 DBGPV("returning: DISABLED\n");
1969 wport
->flags
|= HW_BUSY
;
1971 int swptr
, hwptr
, hw_avail
, sw_avail
, swidx
;
1972 vwsnd_port_hwstate_t hwstate
= wport
->hwstate
;
1973 vwsnd_port_swstate_t swstate
= wport
->swstate
;
1977 hwptr
= li_read_hwptr(&wport
->chan
);
1978 swptr
= li_read_swptr(&wport
->chan
);
1979 hw_unavail
= (swptr
- hwptr
+ hwsize
) % hwsize
;
1980 hw_avail
= (hwmax
- hw_unavail
) & -fragsize
;
1981 sw_avail
= wport
->swb_i_avail
& -fragsize
;
1982 if (sw_avail
&& swstate
== SW_RUN
) {
1983 if (wport
->flags
& ERFLOWN
) {
1984 wport
->flags
&= ~ERFLOWN
;
1986 } else if (swstate
== SW_INITIAL
||
1987 swstate
== SW_OFF
||
1988 (swstate
== SW_DRAIN
&&
1990 (wport
->flags
& ERFLOWN
))) {
1991 DBGP("stopping. hwstate = %d\n", hwstate
);
1992 if (hwstate
!= HW_STOPPED
) {
1993 li_deactivate_dma(&wport
->chan
);
1994 wport
->hwstate
= HW_STOPPED
;
1996 wake_up(&wport
->queue
);
1999 if (!sw_avail
|| !hw_avail
)
2001 spin_unlock_irqrestore(&wport
->lock
, iflags
);
2004 * We gave up the port lock, but we have the HW_BUSY flag.
2005 * Proceed without accessing any nonlocal state.
2006 * Do not exit the loop -- must check for more work.
2009 swidx
= wport
->swb_i_idx
;
2013 if (nb
> hwsize
- swptr
)
2014 nb
= hwsize
- swptr
; /* don't overflow hwbuf */
2015 if (nb
> swsize
- swidx
)
2016 nb
= swsize
- swidx
; /* don't overflow swbuf */
2018 if (nb
% fragsize
) {
2019 DBGP("nb = %d, fragsize = %d\n", nb
, fragsize
);
2020 DBGP("hw_avail = %d\n", hw_avail
);
2021 DBGP("sw_avail = %d\n", sw_avail
);
2022 DBGP("hwsize = %d, swptr = %d\n", hwsize
, swptr
);
2023 DBGP("swsize = %d, swidx = %d\n", swsize
, swidx
);
2025 ASSERT(!(nb
% fragsize
));
2026 DBGPV("copying swb[%d..%d] to hwb[%d..%d]\n",
2027 swidx
, swidx
+ nb
, swptr
, swptr
+ nb
);
2028 pcm_copy_out(wport
, swidx
, swptr
, nb
);
2029 li_write_swptr(&wport
->chan
, (swptr
+ nb
) % hwsize
);
2030 spin_lock_irqsave(&wport
->lock
, iflags
);
2031 if (hwstate
== HW_STOPPED
) {
2032 DBGPV("starting\n");
2033 li_activate_dma(&wport
->chan
);
2034 wport
->hwstate
= HW_RUNNING
;
2035 li_read_USTMSC(&wport
->chan
, &ustmsc
);
2036 ASSERT(wport
->byte_count
% wport
->frame_size
== 0);
2037 wport
->MSC_offset
= ustmsc
.msc
- wport
->byte_count
/ wport
->frame_size
;
2039 __swb_inc_i(wport
, nb
);
2040 wport
->byte_count
+= nb
;
2041 wport
->frag_count
+= nb
/ fragsize
;
2042 ASSERT(nb
% fragsize
== 0);
2043 wake_up(&wport
->queue
);
2045 wport
->flags
&= ~HW_BUSY
;
2046 spin_unlock_irqrestore(&wport
->lock
, iflags
);
2051 * pcm_input() is called both from baselevel and from interrupt level.
2052 * This is where audio frames are copied out of the hardware-accessible
2055 * Locking note: The part of this routine that figures out what to do
2056 * holds rport->lock. The longer part releases rport->lock, but sets
2057 * rport->flags & HW_BUSY. Afterward, it reacquires rport->lock, and
2058 * checks for more work to do.
2060 * If another thread calls pcm_input() while HW_BUSY is set, it
2061 * returns immediately, knowing that the thread that set HW_BUSY will
2062 * look for more work to do before returning.
2064 * This has the advantage that port->lock is held for several short
2065 * periods instead of one long period. Also, when pcm_input is
2066 * called from base level, it reenables interrupts.
2069 static void pcm_input(vwsnd_dev_t
*devc
, int erflown
, int nb
)
2071 vwsnd_port_t
*rport
= &devc
->rport
;
2072 const int hwmax
= rport
->hwbuf_max
;
2073 const int hwsize
= rport
->hwbuf_size
;
2074 const int swsize
= rport
->swbuf_size
;
2075 const int fragsize
= rport
->hw_fragsize
;
2076 unsigned long iflags
;
2078 DBGEV("(devc=0x%p, erflown=%d, nb=%d)\n", devc
, erflown
, nb
);
2080 spin_lock_irqsave(&rport
->lock
, iflags
);
2082 rport
->flags
|= ERFLOWN
;
2083 (void) __swb_inc_u(rport
, nb
);
2084 if (rport
->flags
& HW_BUSY
|| !rport
->swbuf
) {
2085 spin_unlock_irqrestore(&rport
->lock
, iflags
);
2086 DBGPV("returning: HW BUSY or !swbuf\n");
2089 if (rport
->flags
& DISABLED
) {
2090 spin_unlock_irqrestore(&rport
->lock
, iflags
);
2091 DBGPV("returning: DISABLED\n");
2094 rport
->flags
|= HW_BUSY
;
2096 int swptr
, hwptr
, hw_avail
, sw_avail
, swidx
;
2097 vwsnd_port_hwstate_t hwstate
= rport
->hwstate
;
2098 vwsnd_port_swstate_t swstate
= rport
->swstate
;
2100 hwptr
= li_read_hwptr(&rport
->chan
);
2101 swptr
= li_read_swptr(&rport
->chan
);
2102 hw_avail
= (hwptr
- swptr
+ hwsize
) % hwsize
& -fragsize
;
2103 if (hw_avail
> hwmax
)
2105 sw_avail
= rport
->swb_i_avail
& -fragsize
;
2106 if (swstate
!= SW_RUN
) {
2107 DBGP("stopping. hwstate = %d\n", hwstate
);
2108 if (hwstate
!= HW_STOPPED
) {
2109 li_deactivate_dma(&rport
->chan
);
2110 rport
->hwstate
= HW_STOPPED
;
2112 wake_up(&rport
->queue
);
2115 if (!sw_avail
|| !hw_avail
)
2117 spin_unlock_irqrestore(&rport
->lock
, iflags
);
2120 * We gave up the port lock, but we have the HW_BUSY flag.
2121 * Proceed without accessing any nonlocal state.
2122 * Do not exit the loop -- must check for more work.
2125 swidx
= rport
->swb_i_idx
;
2129 if (nb
> hwsize
- swptr
)
2130 nb
= hwsize
- swptr
; /* don't overflow hwbuf */
2131 if (nb
> swsize
- swidx
)
2132 nb
= swsize
- swidx
; /* don't overflow swbuf */
2134 if (nb
% fragsize
) {
2135 DBGP("nb = %d, fragsize = %d\n", nb
, fragsize
);
2136 DBGP("hw_avail = %d\n", hw_avail
);
2137 DBGP("sw_avail = %d\n", sw_avail
);
2138 DBGP("hwsize = %d, swptr = %d\n", hwsize
, swptr
);
2139 DBGP("swsize = %d, swidx = %d\n", swsize
, swidx
);
2141 ASSERT(!(nb
% fragsize
));
2142 DBGPV("copying hwb[%d..%d] to swb[%d..%d]\n",
2143 swptr
, swptr
+ nb
, swidx
, swidx
+ nb
);
2144 pcm_copy_in(rport
, swidx
, swptr
, nb
);
2145 li_write_swptr(&rport
->chan
, (swptr
+ nb
) % hwsize
);
2146 spin_lock_irqsave(&rport
->lock
, iflags
);
2147 __swb_inc_i(rport
, nb
);
2148 rport
->byte_count
+= nb
;
2149 rport
->frag_count
+= nb
/ fragsize
;
2150 ASSERT(nb
% fragsize
== 0);
2151 wake_up(&rport
->queue
);
2153 rport
->flags
&= ~HW_BUSY
;
2154 spin_unlock_irqrestore(&rport
->lock
, iflags
);
2159 * pcm_flush_frag() writes zero samples to fill the current fragment,
2160 * then flushes it to the hardware.
2162 * It is only meaningful to flush output, not input.
2165 static void pcm_flush_frag(vwsnd_dev_t
*devc
)
2167 vwsnd_port_t
*wport
= &devc
->wport
;
2169 DBGPV("swstate = %d\n", wport
->swstate
);
2170 if (wport
->swstate
== SW_RUN
) {
2171 int idx
= wport
->swb_u_idx
;
2172 int end
= (idx
+ wport
->hw_fragsize
- 1)
2173 >> wport
->hw_fragshift
2174 << wport
->hw_fragshift
;
2176 DBGPV("clearing %d bytes\n", nb
);
2178 memset(wport
->swbuf
+ idx
,
2179 (char) wport
->zero_word
,
2181 wport
->swstate
= SW_DRAIN
;
2182 pcm_output(devc
, 0, nb
);
2188 * Wait for output to drain. This sleeps uninterruptibly because
2189 * there is nothing intelligent we can do if interrupted. This
2190 * means the process will be delayed in responding to the signal.
2193 static void pcm_write_sync(vwsnd_dev_t
*devc
)
2195 vwsnd_port_t
*wport
= &devc
->wport
;
2196 DECLARE_WAITQUEUE(wait
, current
);
2197 unsigned long flags
;
2198 vwsnd_port_hwstate_t hwstate
;
2200 DBGEV("(devc=0x%p)\n", devc
);
2201 add_wait_queue(&wport
->queue
, &wait
);
2202 current
->state
= TASK_UNINTERRUPTIBLE
;
2204 spin_lock_irqsave(&wport
->lock
, flags
);
2206 hwstate
= wport
->hwstate
;
2208 spin_unlock_irqrestore(&wport
->lock
, flags
);
2209 if (hwstate
== HW_STOPPED
)
2213 current
->state
= TASK_RUNNING
;
2214 remove_wait_queue(&wport
->queue
, &wait
);
2215 DBGPV("swstate = %d, hwstate = %d\n", wport
->swstate
, wport
->hwstate
);
2219 /*****************************************************************************/
2223 * seek on an audio device always fails.
2226 static void vwsnd_audio_read_intr(vwsnd_dev_t
*devc
, unsigned int status
)
2228 int overflown
= status
& LI_INTR_COMM1_OVERFLOW
;
2230 if (status
& READ_INTR_MASK
)
2231 pcm_input(devc
, overflown
, 0);
2234 static void vwsnd_audio_write_intr(vwsnd_dev_t
*devc
, unsigned int status
)
2236 int underflown
= status
& LI_INTR_COMM2_UNDERFLOW
;
2238 if (status
& WRITE_INTR_MASK
)
2239 pcm_output(devc
, underflown
, 0);
2242 static void vwsnd_audio_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2244 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) dev_id
;
2245 unsigned int status
;
2247 DBGEV("(irq=%d, dev_id=0x%p, regs=0x%p)\n", irq
, dev_id
, regs
);
2249 status
= li_get_clear_intr_status(&devc
->lith
);
2250 vwsnd_audio_read_intr(devc
, status
);
2251 vwsnd_audio_write_intr(devc
, status
);
2254 static loff_t
vwsnd_audio_llseek(struct file
*file
, loff_t offset
, int whence
)
2256 DBGEV("(file=0x%p, offset=%Ld, whence=%d)\n", file
, offset
, whence
);
2260 static ssize_t
vwsnd_audio_do_read(struct file
*file
,
2265 vwsnd_dev_t
*devc
= file
->private_data
;
2266 vwsnd_port_t
*rport
= ((file
->f_mode
& FMODE_READ
) ?
2267 &devc
->rport
: NULL
);
2270 DBGEV("(file=0x%p, buffer=0x%p, count=%d, ppos=0x%p)\n",
2271 file
, buffer
, count
, ppos
);
2276 if (rport
->swbuf
== NULL
) {
2277 vwsnd_port_t
*wport
= (file
->f_mode
& FMODE_WRITE
) ?
2278 &devc
->wport
: NULL
;
2279 ret
= pcm_setup(devc
, rport
, wport
);
2284 if (!access_ok(VERIFY_READ
, buffer
, count
))
2288 DECLARE_WAITQUEUE(wait
, current
);
2289 add_wait_queue(&rport
->queue
, &wait
);
2290 current
->state
= TASK_INTERRUPTIBLE
;
2291 while ((nb
= swb_inc_u(rport
, 0)) == 0) {
2292 DBGPV("blocking\n");
2293 if (rport
->flags
& DISABLED
||
2294 file
->f_flags
& O_NONBLOCK
) {
2295 current
->state
= TASK_RUNNING
;
2296 remove_wait_queue(&rport
->queue
, &wait
);
2297 return ret
? ret
: -EAGAIN
;
2300 if (signal_pending(current
)) {
2301 current
->state
= TASK_RUNNING
;
2302 remove_wait_queue(&rport
->queue
, &wait
);
2303 return ret
? ret
: -ERESTARTSYS
;
2306 current
->state
= TASK_RUNNING
;
2307 remove_wait_queue(&rport
->queue
, &wait
);
2308 pcm_input(devc
, 0, 0);
2309 /* nb bytes are available in userbuf. */
2312 DBGPV("nb = %d\n", nb
);
2313 copy_to_user(buffer
, rport
->swbuf
+ rport
->swb_u_idx
, nb
);
2314 (void) swb_inc_u(rport
, nb
);
2319 DBGPV("returning %d\n", ret
);
2323 static ssize_t
vwsnd_audio_read(struct file
*file
,
2328 vwsnd_dev_t
*devc
= file
->private_data
;
2331 down(&devc
->io_sema
);
2332 ret
= vwsnd_audio_do_read(file
, buffer
, count
, ppos
);
2337 static ssize_t
vwsnd_audio_do_write(struct file
*file
,
2342 vwsnd_dev_t
*devc
= file
->private_data
;
2343 vwsnd_port_t
*wport
= ((file
->f_mode
& FMODE_WRITE
) ?
2344 &devc
->wport
: NULL
);
2347 DBGEV("(file=0x%p, buffer=0x%p, count=%d, ppos=0x%p)\n",
2348 file
, buffer
, count
, ppos
);
2353 if (wport
->swbuf
== NULL
) {
2354 vwsnd_port_t
*rport
= (file
->f_mode
& FMODE_READ
) ?
2355 &devc
->rport
: NULL
;
2356 ret
= pcm_setup(devc
, rport
, wport
);
2360 if (!access_ok(VERIFY_WRITE
, buffer
, count
))
2364 DECLARE_WAITQUEUE(wait
, current
);
2365 add_wait_queue(&wport
->queue
, &wait
);
2366 current
->state
= TASK_INTERRUPTIBLE
;
2367 while ((nb
= swb_inc_u(wport
, 0)) == 0) {
2368 if (wport
->flags
& DISABLED
||
2369 file
->f_flags
& O_NONBLOCK
) {
2370 current
->state
= TASK_RUNNING
;
2371 remove_wait_queue(&wport
->queue
, &wait
);
2372 return ret
? ret
: -EAGAIN
;
2375 if (signal_pending(current
)) {
2376 current
->state
= TASK_RUNNING
;
2377 remove_wait_queue(&wport
->queue
, &wait
);
2378 return ret
? ret
: -ERESTARTSYS
;
2381 current
->state
= TASK_RUNNING
;
2382 remove_wait_queue(&wport
->queue
, &wait
);
2383 /* nb bytes are available in userbuf. */
2386 DBGPV("nb = %d\n", nb
);
2387 copy_from_user(wport
->swbuf
+ wport
->swb_u_idx
, buffer
, nb
);
2388 pcm_output(devc
, 0, nb
);
2393 DBGPV("returning %d\n", ret
);
2397 static ssize_t
vwsnd_audio_write(struct file
*file
,
2402 vwsnd_dev_t
*devc
= file
->private_data
;
2405 down(&devc
->io_sema
);
2406 ret
= vwsnd_audio_do_write(file
, buffer
, count
, ppos
);
2411 static unsigned int vwsnd_audio_poll(struct file
*file
,
2412 struct poll_table_struct
*wait
)
2414 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
2415 vwsnd_port_t
*rport
= (file
->f_mode
& FMODE_READ
) ?
2416 &devc
->rport
: NULL
;
2417 vwsnd_port_t
*wport
= (file
->f_mode
& FMODE_WRITE
) ?
2418 &devc
->wport
: NULL
;
2419 unsigned int mask
= 0;
2421 DBGEV("(file=0x%p, wait=0x%p)\n", file
, wait
);
2423 ASSERT(rport
|| wport
);
2425 poll_wait(file
, &rport
->queue
, wait
);
2426 if (swb_inc_u(rport
, 0))
2427 mask
|= (POLLIN
| POLLRDNORM
);
2430 poll_wait(file
, &wport
->queue
, wait
);
2431 if (wport
->swbuf
== NULL
|| swb_inc_u(wport
, 0))
2432 mask
|= (POLLOUT
| POLLWRNORM
);
2435 DBGPV("returning 0x%x\n", mask
);
2439 static int vwsnd_audio_do_ioctl(struct inode
*inode
,
2444 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
2445 vwsnd_port_t
*rport
= (file
->f_mode
& FMODE_READ
) ?
2446 &devc
->rport
: NULL
;
2447 vwsnd_port_t
*wport
= (file
->f_mode
& FMODE_WRITE
) ?
2448 &devc
->wport
: NULL
;
2449 vwsnd_port_t
*aport
= rport
? rport
: wport
;
2450 struct audio_buf_info buf_info
;
2451 struct count_info info
;
2452 unsigned long flags
;
2456 DBGEV("(inode=0x%p, file=0x%p, cmd=0x%x, arg=0x%lx)\n",
2457 inode
, file
, cmd
, arg
);
2459 case OSS_GETVERSION
: /* _SIOR ('M', 118, int) */
2460 DBGX("OSS_GETVERSION\n");
2461 ival
= SOUND_VERSION
;
2462 return put_user(ival
, (int *) arg
);
2464 case SNDCTL_DSP_GETCAPS
: /* _SIOR ('P',15, int) */
2465 DBGX("SNDCTL_DSP_GETCAPS\n");
2466 ival
= DSP_CAP_DUPLEX
| DSP_CAP_REALTIME
| DSP_CAP_TRIGGER
;
2467 return put_user(ival
, (int *) arg
);
2469 case SNDCTL_DSP_GETFMTS
: /* _SIOR ('P',11, int) */
2470 DBGX("SNDCTL_DSP_GETFMTS\n");
2471 ival
= (AFMT_S16_LE
| AFMT_MU_LAW
| AFMT_A_LAW
|
2473 return put_user(ival
, (int *) arg
);
2476 case SOUND_PCM_READ_RATE
: /* _SIOR ('P', 2, int) */
2477 DBGX("SOUND_PCM_READ_RATE\n");
2478 ival
= aport
->sw_framerate
;
2479 return put_user(ival
, (int *) arg
);
2481 case SOUND_PCM_READ_CHANNELS
: /* _SIOR ('P', 6, int) */
2482 DBGX("SOUND_PCM_READ_CHANNELS\n");
2483 ival
= aport
->sw_channels
;
2484 return put_user(ival
, (int *) arg
);
2486 case SNDCTL_DSP_SPEED
: /* _SIOWR('P', 2, int) */
2487 get_user_ret(ival
, (int *) arg
, -EFAULT
);
2488 DBGX("SNDCTL_DSP_SPEED %d\n", ival
);
2490 if (aport
->swstate
!= SW_INITIAL
) {
2491 DBGX("SNDCTL_DSP_SPEED failed: swstate = %d\n",
2495 if (ival
< MIN_SPEED
)
2497 if (ival
> MAX_SPEED
)
2500 rport
->sw_framerate
= ival
;
2502 wport
->sw_framerate
= ival
;
2504 ival
= aport
->sw_framerate
;
2505 return put_user(ival
, (int *) arg
);
2507 case SNDCTL_DSP_STEREO
: /* _SIOWR('P', 3, int) */
2508 get_user_ret(ival
, (int *) arg
, -EFAULT
);
2509 DBGX("SNDCTL_DSP_STEREO %d\n", ival
);
2510 if (ival
!= 0 && ival
!= 1)
2512 if (aport
->swstate
!= SW_INITIAL
)
2515 rport
->sw_channels
= ival
+ 1;
2517 wport
->sw_channels
= ival
+ 1;
2518 return put_user(ival
, (int *) arg
);
2520 case SNDCTL_DSP_CHANNELS
: /* _SIOWR('P', 6, int) */
2521 get_user_ret(ival
, (int *) arg
, -EFAULT
);
2522 DBGX("SNDCTL_DSP_CHANNELS %d\n", ival
);
2523 if (ival
!= 1 && ival
!= 2)
2525 if (aport
->swstate
!= SW_INITIAL
)
2528 rport
->sw_channels
= ival
;
2530 wport
->sw_channels
= ival
;
2531 return put_user(ival
, (int *) arg
);
2533 case SNDCTL_DSP_GETBLKSIZE
: /* _SIOWR('P', 4, int) */
2534 ival
= pcm_setup(devc
, rport
, wport
);
2536 DBGX("SNDCTL_DSP_GETBLKSIZE failed, errno %d\n", ival
);
2539 ival
= 1 << aport
->sw_fragshift
;
2540 DBGX("SNDCTL_DSP_GETBLKSIZE returning %d\n", ival
);
2541 return put_user(ival
, (int *) arg
);
2543 case SNDCTL_DSP_SETFRAGMENT
: /* _SIOWR('P',10, int) */
2544 get_user_ret(ival
, (int *) arg
, -EFAULT
);
2545 DBGX("SNDCTL_DSP_SETFRAGMENT %d:%d\n",
2546 ival
>> 16, ival
& 0xFFFF);
2547 if (aport
->swstate
!= SW_INITIAL
)
2550 int sw_fragshift
= ival
& 0xFFFF;
2551 int sw_subdivshift
= aport
->sw_subdivshift
;
2552 int hw_fragshift
= sw_fragshift
- sw_subdivshift
;
2553 int sw_fragcount
= (ival
>> 16) & 0xFFFF;
2555 if (hw_fragshift
< MIN_FRAGSHIFT
)
2556 hw_fragshift
= MIN_FRAGSHIFT
;
2557 if (hw_fragshift
> MAX_FRAGSHIFT
)
2558 hw_fragshift
= MAX_FRAGSHIFT
;
2559 sw_fragshift
= hw_fragshift
+ aport
->sw_subdivshift
;
2560 hw_fragsize
= 1 << hw_fragshift
;
2561 if (sw_fragcount
< MIN_FRAGCOUNT(hw_fragsize
))
2562 sw_fragcount
= MIN_FRAGCOUNT(hw_fragsize
);
2563 if (sw_fragcount
> MAX_FRAGCOUNT(hw_fragsize
))
2564 sw_fragcount
= MAX_FRAGCOUNT(hw_fragsize
);
2565 DBGPV("sw_fragshift = %d\n", sw_fragshift
);
2566 DBGPV("rport = 0x%p, wport = 0x%p\n", rport
, wport
);
2568 rport
->sw_fragshift
= sw_fragshift
;
2569 rport
->sw_fragcount
= sw_fragcount
;
2572 wport
->sw_fragshift
= sw_fragshift
;
2573 wport
->sw_fragcount
= sw_fragcount
;
2575 ival
= sw_fragcount
<< 16 | sw_fragshift
;
2577 DBGX("SNDCTL_DSP_SETFRAGMENT returns %d:%d\n",
2578 ival
>> 16, ival
& 0xFFFF);
2579 return put_user(ival
, (int *) arg
);
2581 case SNDCTL_DSP_SUBDIVIDE
: /* _SIOWR('P', 9, int) */
2582 get_user_ret(ival
, (int *) arg
, -EFAULT
);
2583 DBGX("SNDCTL_DSP_SUBDIVIDE %d\n", ival
);
2584 if (aport
->swstate
!= SW_INITIAL
)
2588 int hw_fragshift
, hw_fragsize
, hw_fragcount
;
2590 case 1: subdivshift
= 0; break;
2591 case 2: subdivshift
= 1; break;
2592 case 4: subdivshift
= 2; break;
2593 default: return -EINVAL
;
2595 hw_fragshift
= aport
->sw_fragshift
- subdivshift
;
2596 if (hw_fragshift
< MIN_FRAGSHIFT
||
2597 hw_fragshift
> MAX_FRAGSHIFT
)
2599 hw_fragsize
= 1 << hw_fragshift
;
2600 hw_fragcount
= aport
->sw_fragcount
>> subdivshift
;
2601 if (hw_fragcount
< MIN_FRAGCOUNT(hw_fragsize
) ||
2602 hw_fragcount
> MAX_FRAGCOUNT(hw_fragsize
))
2605 rport
->sw_subdivshift
= subdivshift
;
2607 wport
->sw_subdivshift
= subdivshift
;
2611 case SNDCTL_DSP_SETFMT
: /* _SIOWR('P',5, int) */
2612 get_user_ret(ival
, (int *) arg
, -EFAULT
);
2613 DBGX("SNDCTL_DSP_SETFMT %d\n", ival
);
2614 if (ival
!= AFMT_QUERY
) {
2615 if (aport
->swstate
!= SW_INITIAL
) {
2616 DBGP("SETFMT failed, swstate = %d\n",
2627 rport
->sw_samplefmt
= ival
;
2629 wport
->sw_samplefmt
= ival
;
2635 ival
= aport
->sw_samplefmt
;
2636 return put_user(ival
, (int *) arg
);
2638 case SNDCTL_DSP_GETOSPACE
: /* _SIOR ('P',12, audio_buf_info) */
2639 DBGXV("SNDCTL_DSP_GETOSPACE\n");
2642 ival
= pcm_setup(devc
, rport
, wport
);
2645 ival
= swb_inc_u(wport
, 0);
2646 buf_info
.fragments
= ival
>> wport
->sw_fragshift
;
2647 buf_info
.fragstotal
= wport
->sw_fragcount
;
2648 buf_info
.fragsize
= 1 << wport
->sw_fragshift
;
2649 buf_info
.bytes
= ival
;
2650 DBGXV("SNDCTL_DSP_GETOSPACE returns { %d %d %d %d }\n",
2651 buf_info
.fragments
, buf_info
.fragstotal
,
2652 buf_info
.fragsize
, buf_info
.bytes
);
2653 return copy_to_user((void *) arg
, &buf_info
, sizeof buf_info
);
2655 case SNDCTL_DSP_GETISPACE
: /* _SIOR ('P',13, audio_buf_info) */
2656 DBGX("SNDCTL_DSP_GETISPACE\n");
2659 ival
= pcm_setup(devc
, rport
, wport
);
2662 ival
= swb_inc_u(rport
, 0);
2663 buf_info
.fragments
= ival
>> rport
->sw_fragshift
;
2664 buf_info
.fragstotal
= rport
->sw_fragcount
;
2665 buf_info
.fragsize
= 1 << rport
->sw_fragshift
;
2666 buf_info
.bytes
= ival
;
2667 DBGX("SNDCTL_DSP_GETISPACE returns { %d %d %d %d }\n",
2668 buf_info
.fragments
, buf_info
.fragstotal
,
2669 buf_info
.fragsize
, buf_info
.bytes
);
2670 return copy_to_user((void *) arg
, &buf_info
, sizeof buf_info
);
2672 case SNDCTL_DSP_NONBLOCK
: /* _SIO ('P',14) */
2673 DBGX("SNDCTL_DSP_NONBLOCK\n");
2674 file
->f_flags
|= O_NONBLOCK
;
2677 case SNDCTL_DSP_RESET
: /* _SIO ('P', 0) */
2678 DBGX("SNDCTL_DSP_RESET\n");
2680 * Nothing special needs to be done for input. Input
2681 * samples sit in swbuf, but it will be reinitialized
2682 * to empty when pcm_setup() is called.
2684 if (wport
&& wport
->swbuf
) {
2685 wport
->swstate
= SW_INITIAL
;
2686 pcm_output(devc
, 0, 0);
2687 pcm_write_sync(devc
);
2689 pcm_shutdown(devc
, rport
, wport
);
2692 case SNDCTL_DSP_SYNC
: /* _SIO ('P', 1) */
2693 DBGX("SNDCTL_DSP_SYNC\n");
2695 pcm_flush_frag(devc
);
2696 pcm_write_sync(devc
);
2698 pcm_shutdown(devc
, rport
, wport
);
2701 case SNDCTL_DSP_POST
: /* _SIO ('P', 8) */
2702 DBGX("SNDCTL_DSP_POST\n");
2705 pcm_flush_frag(devc
);
2708 case SNDCTL_DSP_GETIPTR
: /* _SIOR ('P', 17, count_info) */
2709 DBGX("SNDCTL_DSP_GETIPTR\n");
2712 spin_lock_irqsave(&rport
->lock
, flags
);
2715 if (rport
->hwstate
== HW_RUNNING
) {
2716 ASSERT(rport
->swstate
== SW_RUN
);
2717 li_read_USTMSC(&rport
->chan
, &ustmsc
);
2718 info
.bytes
= ustmsc
.msc
- rport
->MSC_offset
;
2719 info
.bytes
*= rport
->frame_size
;
2721 info
.bytes
= rport
->byte_count
;
2723 info
.blocks
= rport
->frag_count
;
2724 info
.ptr
= 0; /* not implemented */
2725 rport
->frag_count
= 0;
2727 spin_unlock_irqrestore(&rport
->lock
, flags
);
2728 return copy_to_user((void *) arg
, &info
, sizeof info
);
2730 case SNDCTL_DSP_GETOPTR
: /* _SIOR ('P',18, count_info) */
2731 DBGX("SNDCTL_DSP_GETOPTR\n");
2734 spin_lock_irqsave(&wport
->lock
, flags
);
2737 if (wport
->hwstate
== HW_RUNNING
) {
2738 ASSERT(wport
->swstate
== SW_RUN
);
2739 li_read_USTMSC(&wport
->chan
, &ustmsc
);
2740 info
.bytes
= ustmsc
.msc
- wport
->MSC_offset
;
2741 info
.bytes
*= wport
->frame_size
;
2743 info
.bytes
= wport
->byte_count
;
2745 info
.blocks
= wport
->frag_count
;
2746 info
.ptr
= 0; /* not implemented */
2747 wport
->frag_count
= 0;
2749 spin_unlock_irqrestore(&wport
->lock
, flags
);
2750 return copy_to_user((void *) arg
, &info
, sizeof info
);
2752 case SNDCTL_DSP_GETODELAY
: /* _SIOR ('P', 23, int) */
2753 DBGX("SNDCTL_DSP_GETODELAY\n");
2756 spin_lock_irqsave(&wport
->lock
, flags
);
2758 int fsize
= wport
->frame_size
;
2759 ival
= wport
->swb_i_avail
/ fsize
;
2760 if (wport
->hwstate
== HW_RUNNING
) {
2761 int swptr
, hwptr
, hwframes
, hwbytes
, hwsize
;
2765 hwsize
= wport
->hwbuf_size
;
2766 swptr
= li_read_swptr(&wport
->chan
);
2767 li_read_USTMSC(&wport
->chan
, &ustmsc
);
2768 hwframes
= ustmsc
.msc
- wport
->MSC_offset
;
2769 totalhwbytes
= hwframes
* fsize
;
2770 hwptr
= totalhwbytes
% hwsize
;
2771 hwbytes
= (swptr
- hwptr
+ hwsize
) % hwsize
;
2772 ival
+= hwbytes
/ fsize
;
2775 spin_unlock_irqrestore(&wport
->lock
, flags
);
2776 return put_user(ival
, (int *) arg
);
2778 case SNDCTL_DSP_PROFILE
: /* _SIOW ('P', 23, int) */
2779 DBGX("SNDCTL_DSP_PROFILE\n");
2782 * Thomas Sailer explains SNDCTL_DSP_PROFILE
2783 * (private email, March 24, 1999):
2785 * This gives the sound driver a hint on what it
2786 * should do with partial fragments
2787 * (i.e. fragments partially filled with write).
2788 * This can direct the driver to zero them or
2789 * leave them alone. But don't ask me what this
2790 * is good for, my driver just zeroes the last
2791 * fragment before the receiver stops, no idea
2792 * what good for any other behaviour could
2793 * be. Implementing it as NOP seems safe.
2798 case SNDCTL_DSP_GETTRIGGER
: /* _SIOR ('P',16, int) */
2799 DBGX("SNDCTL_DSP_GETTRIGGER\n");
2802 spin_lock_irqsave(&rport
->lock
, flags
);
2804 if (!(rport
->flags
& DISABLED
))
2805 ival
|= PCM_ENABLE_INPUT
;
2807 spin_unlock_irqrestore(&rport
->lock
, flags
);
2810 spin_lock_irqsave(&wport
->lock
, flags
);
2812 if (!(wport
->flags
& DISABLED
))
2813 ival
|= PCM_ENABLE_OUTPUT
;
2815 spin_unlock_irqrestore(&wport
->lock
, flags
);
2817 return put_user(ival
, (int *) arg
);
2819 case SNDCTL_DSP_SETTRIGGER
: /* _SIOW ('P',16, int) */
2820 get_user_ret(ival
, (int *) arg
, -EFAULT
);
2821 DBGX("SNDCTL_DSP_SETTRIGGER %d\n", ival
);
2824 * If user is disabling I/O and port is not in initial
2825 * state, fail with EINVAL.
2828 if (((rport
&& !(ival
& PCM_ENABLE_INPUT
)) ||
2829 (wport
&& !(ival
& PCM_ENABLE_OUTPUT
))) &&
2830 aport
->swstate
!= SW_INITIAL
)
2834 vwsnd_port_hwstate_t hwstate
;
2835 spin_lock_irqsave(&rport
->lock
, flags
);
2837 hwstate
= rport
->hwstate
;
2838 if (ival
& PCM_ENABLE_INPUT
)
2839 rport
->flags
&= ~DISABLED
;
2841 rport
->flags
|= DISABLED
;
2843 spin_unlock_irqrestore(&rport
->lock
, flags
);
2844 if (hwstate
!= HW_RUNNING
&& ival
& PCM_ENABLE_INPUT
) {
2846 if (rport
->swstate
== SW_INITIAL
)
2847 pcm_setup(devc
, rport
, wport
);
2849 li_activate_dma(&rport
->chan
);
2853 vwsnd_port_flags_t pflags
;
2854 spin_lock_irqsave(&wport
->lock
, flags
);
2856 pflags
= wport
->flags
;
2857 if (ival
& PCM_ENABLE_OUTPUT
)
2858 wport
->flags
&= ~DISABLED
;
2860 wport
->flags
|= DISABLED
;
2862 spin_unlock_irqrestore(&wport
->lock
, flags
);
2863 if (pflags
& DISABLED
&& ival
& PCM_ENABLE_OUTPUT
) {
2864 if (wport
->swstate
== SW_RUN
)
2865 pcm_output(devc
, 0, 0);
2871 DBGP("unknown ioctl 0x%x\n", cmd
);
2874 DBGP("unimplemented ioctl 0x%x\n", cmd
);
2878 static int vwsnd_audio_ioctl(struct inode
*inode
,
2883 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
2886 down(&devc
->io_sema
);
2887 ret
= vwsnd_audio_do_ioctl(inode
, file
, cmd
, arg
);
2894 static int vwsnd_audio_mmap(struct file
*file
, struct vm_area_struct
*vma
)
2896 DBGE("(file=0x%p, vma=0x%p)\n", file
, vma
);
2901 * Open the audio device for read and/or write.
2903 * Returns 0 on success, -errno on failure.
2906 static int vwsnd_audio_open(struct inode
*inode
, struct file
*file
)
2909 dev_t minor
= MINOR(inode
->i_rdev
);
2912 DBGE("(inode=0x%p, file=0x%p)\n", inode
, file
);
2915 for (devc
= vwsnd_dev_list
; devc
; devc
= devc
->next_dev
)
2916 if ((devc
->audio_minor
& ~0x0F) == (minor
& ~0x0F))
2924 down(&devc
->open_sema
);
2925 while (devc
->open_mode
& file
->f_mode
) {
2926 up(&devc
->open_sema
);
2927 if (file
->f_flags
& O_NONBLOCK
) {
2931 interruptible_sleep_on(&devc
->open_wait
);
2932 if (signal_pending(current
)) {
2934 return -ERESTARTSYS
;
2936 down(&devc
->open_sema
);
2938 devc
->open_mode
|= file
->f_mode
& (FMODE_READ
| FMODE_WRITE
);
2939 up(&devc
->open_sema
);
2941 /* get default sample format from minor number. */
2944 if ((minor
& 0xF) == SND_DEV_DSP
)
2945 sw_samplefmt
= AFMT_U8
;
2946 else if ((minor
& 0xF) == SND_DEV_AUDIO
)
2947 sw_samplefmt
= AFMT_MU_LAW
;
2948 else if ((minor
& 0xF) == SND_DEV_DSP16
)
2949 sw_samplefmt
= AFMT_S16_LE
;
2953 /* Initialize vwsnd_ports. */
2955 down(&devc
->io_sema
);
2957 if (file
->f_mode
& FMODE_READ
) {
2958 devc
->rport
.swstate
= SW_INITIAL
;
2959 devc
->rport
.flags
= 0;
2960 devc
->rport
.sw_channels
= 1;
2961 devc
->rport
.sw_samplefmt
= sw_samplefmt
;
2962 devc
->rport
.sw_framerate
= 8000;
2963 devc
->rport
.sw_fragshift
= DEFAULT_FRAGSHIFT
;
2964 devc
->rport
.sw_fragcount
= DEFAULT_FRAGCOUNT
;
2965 devc
->rport
.sw_subdivshift
= DEFAULT_SUBDIVSHIFT
;
2966 devc
->rport
.byte_count
= 0;
2967 devc
->rport
.frag_count
= 0;
2969 if (file
->f_mode
& FMODE_WRITE
) {
2970 devc
->wport
.swstate
= SW_INITIAL
;
2971 devc
->wport
.flags
= 0;
2972 devc
->wport
.sw_channels
= 1;
2973 devc
->wport
.sw_samplefmt
= sw_samplefmt
;
2974 devc
->wport
.sw_framerate
= 8000;
2975 devc
->wport
.sw_fragshift
= DEFAULT_FRAGSHIFT
;
2976 devc
->wport
.sw_fragcount
= DEFAULT_FRAGCOUNT
;
2977 devc
->wport
.sw_subdivshift
= DEFAULT_SUBDIVSHIFT
;
2978 devc
->wport
.byte_count
= 0;
2979 devc
->wport
.frag_count
= 0;
2984 file
->private_data
= devc
;
2990 * Release (close) the audio device.
2993 static int vwsnd_audio_release(struct inode
*inode
, struct file
*file
)
2995 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
2996 vwsnd_port_t
*wport
= NULL
, *rport
= NULL
;
2999 down(&devc
->io_sema
);
3001 DBGEV("(inode=0x%p, file=0x%p)\n", inode
, file
);
3003 if (file
->f_mode
& FMODE_READ
)
3004 rport
= &devc
->rport
;
3005 if (file
->f_mode
& FMODE_WRITE
) {
3006 wport
= &devc
->wport
;
3007 pcm_flush_frag(devc
);
3008 pcm_write_sync(devc
);
3010 pcm_shutdown(devc
, rport
, wport
);
3012 rport
->swstate
= SW_OFF
;
3014 wport
->swstate
= SW_OFF
;
3018 down(&devc
->open_sema
);
3020 devc
->open_mode
&= ~file
->f_mode
;
3022 up(&devc
->open_sema
);
3023 wake_up(&devc
->open_wait
);
3024 DBGDO(if (IN_USE
)) /* see hack in vwsnd_mixer_release() */
3030 static struct file_operations vwsnd_audio_fops
= {
3031 &vwsnd_audio_llseek
,
3040 &vwsnd_audio_release
,
3043 NULL
, /* check_media_change */
3044 NULL
, /* revalidate */
3048 /*****************************************************************************/
3051 /* open the mixer device. */
3053 static int vwsnd_mixer_open(struct inode
*inode
, struct file
*file
)
3057 DBGEV("(inode=0x%p, file=0x%p)\n", inode
, file
);
3060 for (devc
= vwsnd_dev_list
; devc
; devc
= devc
->next_dev
)
3061 if (devc
->mixer_minor
== MINOR(inode
->i_rdev
))
3068 file
->private_data
= devc
;
3072 /* release (close) the mixer device. */
3074 static int vwsnd_mixer_release(struct inode
*inode
, struct file
*file
)
3076 DBGEV("(inode=0x%p, file=0x%p)\n", inode
, file
);
3079 * hack -- opening/closing the mixer device zeroes use count
3080 * so driver can be unloaded.
3081 * Use only while debugging module, and then use it carefully.
3084 DBGDO(while (IN_USE
))
3089 /* seek is illegal on mixer. */
3091 static loff_t
vwsnd_mixer_llseek(struct file
*file
, loff_t offset
, int whence
)
3096 /* mixer_read_ioctl handles all read ioctls on the mixer device. */
3098 static int mixer_read_ioctl(vwsnd_dev_t
*devc
, unsigned int nr
, caddr_t arg
)
3102 DBGEV("(devc=0x%p, nr=0x%x, arg=0x%p)\n", devc
, nr
, arg
);
3105 case SOUND_MIXER_CAPS
:
3106 val
= SOUND_CAP_EXCL_INPUT
;
3109 case SOUND_MIXER_DEVMASK
:
3110 val
= (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
3111 SOUND_MASK_MIC
| SOUND_MASK_CD
| SOUND_MASK_RECLEV
);
3114 case SOUND_MIXER_STEREODEVS
:
3115 val
= (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
3116 SOUND_MASK_MIC
| SOUND_MASK_CD
| SOUND_MASK_RECLEV
);
3119 case SOUND_MIXER_OUTMASK
:
3120 val
= (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
3121 SOUND_MASK_MIC
| SOUND_MASK_CD
);
3124 case SOUND_MIXER_RECMASK
:
3125 val
= (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
3126 SOUND_MASK_MIC
| SOUND_MASK_CD
);
3129 case SOUND_MIXER_PCM
:
3130 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_PCM
);
3133 case SOUND_MIXER_LINE
:
3134 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_LINE
);
3137 case SOUND_MIXER_MIC
:
3138 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_MIC
);
3141 case SOUND_MIXER_CD
:
3142 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_CD
);
3145 case SOUND_MIXER_RECLEV
:
3146 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_RECLEV
);
3149 case SOUND_MIXER_RECSRC
:
3150 val
= ad1843_get_recsrc(&devc
->lith
);
3153 case SOUND_MIXER_OUTSRC
:
3154 val
= ad1843_get_outsrc(&devc
->lith
);
3160 return put_user(val
, (int *) arg
);
3163 /* mixer_write_ioctl handles all write ioctls on the mixer device. */
3165 static int mixer_write_ioctl(vwsnd_dev_t
*devc
, unsigned int nr
, caddr_t arg
)
3170 DBGEV("(devc=0x%p, nr=0x%x, arg=0x%p)\n", devc
, nr
, arg
);
3172 err
= get_user(val
, (int *) arg
);
3176 case SOUND_MIXER_PCM
:
3177 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_PCM
, val
);
3180 case SOUND_MIXER_LINE
:
3181 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_LINE
, val
);
3184 case SOUND_MIXER_MIC
:
3185 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_MIC
, val
);
3188 case SOUND_MIXER_CD
:
3189 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_CD
, val
);
3192 case SOUND_MIXER_RECLEV
:
3193 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_RECLEV
, val
);
3196 case SOUND_MIXER_RECSRC
:
3197 if (devc
->rport
.swbuf
|| devc
->wport
.swbuf
)
3198 return -EBUSY
; /* can't change recsrc while running */
3199 val
= ad1843_set_recsrc(&devc
->lith
, val
);
3202 case SOUND_MIXER_OUTSRC
:
3203 val
= ad1843_set_outsrc(&devc
->lith
, val
);
3211 return put_user(val
, (int *) arg
);
3214 /* This is the ioctl entry to the mixer driver. */
3216 static int vwsnd_mixer_ioctl(struct inode
*ioctl
,
3221 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
3222 const unsigned int nrmask
= _IOC_NRMASK
<< _IOC_NRSHIFT
;
3223 const unsigned int nr
= (cmd
& nrmask
) >> _IOC_NRSHIFT
;
3226 DBGEV("(devc=0x%p, cmd=0x%x, arg=0x%lx)\n", devc
, cmd
, arg
);
3228 down(&devc
->mix_sema
);
3230 if ((cmd
& ~nrmask
) == MIXER_READ(0))
3231 retval
= mixer_read_ioctl(devc
, nr
, (caddr_t
) arg
);
3232 else if ((cmd
& ~nrmask
) == MIXER_WRITE(0))
3233 retval
= mixer_write_ioctl(devc
, nr
, (caddr_t
) arg
);
3237 up(&devc
->mix_sema
);
3241 static struct file_operations vwsnd_mixer_fops
= {
3242 &vwsnd_mixer_llseek
,
3251 &vwsnd_mixer_release
,
3254 NULL
, /* check_media_change */
3255 NULL
, /* revalidate */
3259 /*****************************************************************************/
3260 /* probe/attach/unload */
3262 /* driver probe routine. Return nonzero if hardware is found. */
3264 static int probe_vwsnd(struct address_info
*hw_config
)
3268 unsigned long later
;
3270 DBGEV("(hw_config=0x%p)\n", hw_config
);
3272 /* XXX verify lithium present (to prevent crash on non-vw) */
3274 if (li_create(&lith
, hw_config
->io_base
) != 0) {
3275 printk(KERN_WARNING
"probe_vwsnd: can't map lithium\n");
3278 later
= jiffies
+ 2;
3279 li_writel(&lith
, LI_HOST_CONTROLLER
, LI_HC_LINK_ENABLE
);
3281 w
= li_readl(&lith
, LI_HOST_CONTROLLER
);
3282 } while (w
== LI_HC_LINK_ENABLE
&& jiffies
< later
);
3286 DBGPV("HC = 0x%04x\n", w
);
3288 if ((w
== LI_HC_LINK_ENABLE
) || (w
& LI_HC_LINK_CODEC
)) {
3290 /* This may indicate a beta machine with no audio,
3291 * or a future machine with different audio.
3292 * On beta-release 320 w/ no audio, HC == 0x4000 */
3294 printk(KERN_WARNING
"probe_vwsnd: audio codec not found\n");
3298 if (w
& LI_HC_LINK_FAILURE
) {
3299 printk(KERN_WARNING
"probe_vwsnd: can't init audio codec\n");
3303 printk(KERN_INFO
"probe_vwsnd: lithium audio found\n");
3309 * driver attach routine. Initialize driver data structures and
3310 * initialize hardware. A new vwsnd_dev_t is allocated and put
3311 * onto the global list, vwsnd_dev_list.
3313 * Return +minor_dev on success, -errno on failure.
3316 static int attach_vwsnd(struct address_info
*hw_config
)
3318 vwsnd_dev_t
*devc
= NULL
;
3321 DBGEV("(hw_config=0x%p)\n", hw_config
);
3323 devc
= kmalloc(sizeof (vwsnd_dev_t
), GFP_KERNEL
);
3327 err
= li_create(&devc
->lith
, hw_config
->io_base
);
3331 init_waitqueue(&devc
->open_wait
);
3333 devc
->rport
.hwbuf_size
= HWBUF_SIZE
;
3334 devc
->rport
.hwbuf_vaddr
= __get_free_pages(GFP_KERNEL
, HWBUF_ORDER
);
3335 if (!devc
->rport
.hwbuf_vaddr
)
3337 devc
->rport
.hwbuf
= (caddr_t
) devc
->rport
.hwbuf_vaddr
;
3338 devc
->rport
.hwbuf_paddr
= virt_to_phys(devc
->rport
.hwbuf
);
3341 * Quote from the NT driver:
3343 * // WARNING!!! HACK to setup output dma!!!
3344 * // This is required because even on output there is some data
3345 * // trickling into the input DMA channel. This is a bug in the
3346 * // Lithium microcode.
3349 * We set the input side's DMA base address here. It will remain
3350 * valid until the driver is unloaded.
3353 li_writel(&devc
->lith
, LI_COMM1_BASE
,
3354 devc
->rport
.hwbuf_paddr
>> 8 | 1 << (37 - 8));
3356 devc
->wport
.hwbuf_size
= HWBUF_SIZE
;
3357 devc
->wport
.hwbuf_vaddr
= __get_free_pages(GFP_KERNEL
, HWBUF_ORDER
);
3358 if (!devc
->wport
.hwbuf_vaddr
)
3360 devc
->wport
.hwbuf
= (caddr_t
) devc
->wport
.hwbuf_vaddr
;
3361 devc
->wport
.hwbuf_paddr
= virt_to_phys(devc
->wport
.hwbuf
);
3362 DBGP("wport hwbuf = 0x%p\n", devc
->wport
.hwbuf
);
3365 err
= ad1843_init(&devc
->lith
);
3370 /* install interrupt handler */
3372 err
= request_irq(hw_config
->irq
, vwsnd_audio_intr
, 0, "vwsnd", devc
);
3376 /* register this device's drivers. */
3378 devc
->audio_minor
= register_sound_dsp(&vwsnd_audio_fops
, -1);
3379 if ((err
= devc
->audio_minor
) < 0) {
3380 DBGDO(printk(KERN_WARNING
3381 "attach_vwsnd: register_sound_dsp error %d\n",
3385 devc
->mixer_minor
= register_sound_mixer(&vwsnd_mixer_fops
,
3386 devc
->audio_minor
>> 4);
3387 if ((err
= devc
->mixer_minor
) < 0) {
3388 DBGDO(printk(KERN_WARNING
3389 "attach_vwsnd: register_sound_mixer error %d\n",
3394 /* Squirrel away device indices for unload routine. */
3396 hw_config
->slots
[0] = devc
->audio_minor
;
3398 /* Initialize as much of *devc as possible */
3400 devc
->open_sema
= MUTEX
;
3401 devc
->io_sema
= MUTEX
;
3402 devc
->mix_sema
= MUTEX
;
3403 devc
->open_mode
= 0;
3404 devc
->rport
.lock
= SPIN_LOCK_UNLOCKED
;
3405 init_waitqueue(&devc
->rport
.queue
);
3406 devc
->rport
.swstate
= SW_OFF
;
3407 devc
->rport
.hwstate
= HW_STOPPED
;
3408 devc
->rport
.flags
= 0;
3409 devc
->rport
.swbuf
= NULL
;
3410 devc
->wport
.lock
= SPIN_LOCK_UNLOCKED
;
3411 init_waitqueue(&devc
->wport
.queue
);
3412 devc
->wport
.swstate
= SW_OFF
;
3413 devc
->wport
.hwstate
= HW_STOPPED
;
3414 devc
->wport
.flags
= 0;
3415 devc
->wport
.swbuf
= NULL
;
3417 /* Success. Link us onto the local device list. */
3419 devc
->next_dev
= vwsnd_dev_list
;
3420 vwsnd_dev_list
= devc
;
3421 return devc
->audio_minor
;
3423 /* So many ways to fail. Undo what we did. */
3426 unregister_sound_dsp(devc
->audio_minor
);
3428 free_irq(hw_config
->irq
, devc
);
3431 free_pages(devc
->wport
.hwbuf_vaddr
, HWBUF_ORDER
);
3433 free_pages(devc
->rport
.hwbuf_vaddr
, HWBUF_ORDER
);
3435 li_destroy(&devc
->lith
);
3442 static int unload_vwsnd(struct address_info
*hw_config
)
3444 vwsnd_dev_t
*devc
, **devcp
;
3450 devcp
= &vwsnd_dev_list
;
3451 while ((devc
= *devcp
)) {
3452 if (devc
->audio_minor
== hw_config
->slots
[0]) {
3453 *devcp
= devc
->next_dev
;
3456 devcp
= &devc
->next_dev
;
3462 unregister_sound_mixer(devc
->mixer_minor
);
3463 unregister_sound_dsp(devc
->audio_minor
);
3464 free_irq(hw_config
->irq
, devc
);
3465 free_pages(devc
->wport
.hwbuf_vaddr
, HWBUF_ORDER
);
3466 free_pages(devc
->rport
.hwbuf_vaddr
, HWBUF_ORDER
);
3467 li_destroy(&devc
->lith
);
3473 /*****************************************************************************/
3474 /* initialization and loadable kernel module interface */
3476 static struct address_info the_hw_config
= {
3477 0xFF001000, /* lithium phys addr */
3478 CO_IRQ(CO_APIC_LI_AUDIO
) /* irq */
3483 MODULE_DESCRIPTION("SGI Visual Workstation sound module");
3484 MODULE_AUTHOR("Bob Miller <kbob@sgi.com>");
3486 extern int init_module(void)
3491 DBGXV("sound::vwsnd::init_module()\n");
3493 if(!probe_vwsnd(&the_hw_config
))
3495 err
= attach_vwsnd(&the_hw_config
);
3501 extern void cleanup_module(void)
3503 DBGX("sound::vwsnd::cleanup_module()\n");
3505 unload_vwsnd(&the_hw_config
);
3510 extern void init_vwsnd(void)
3512 DBGX("sound::vwsnd::init_vwsnd()\n");
3513 if (probe_vwsnd(&the_hw_config
))
3514 (void) attach_vwsnd(&the_hw_config
);
3517 #endif /* !MODULE */
3521 * compile-command: "cd ../..; make modules SUBDIRS=drivers/sound"