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Import 2.3.18pre1
[davej-history.git] / drivers / scsi / sym53c8xx_defs.h
blob3b30e1bb5179b4624593b497dc9525cc9c1e83e8
1 /******************************************************************************
2 ** High Performance device driver for the Symbios 53C896 controller.
3 **
4 ** Copyright (C) 1998 Gerard Roudier <groudier@club-internet.fr>
5 **
6 ** This driver also supports all the Symbios 53C8XX controller family,
7 ** except 53C810 revisions < 16, 53C825 revisions < 16 and all
8 ** revisions of 53C815 controllers.
9 **
10 ** This driver is based on the Linux port of the FreeBSD ncr driver.
11 **
12 ** Copyright (C) 1994 Wolfgang Stanglmeier
13 **
14 **-----------------------------------------------------------------------------
15 **
16 ** This program is free software; you can redistribute it and/or modify
17 ** it under the terms of the GNU General Public License as published by
18 ** the Free Software Foundation; either version 2 of the License, or
19 ** (at your option) any later version.
20 **
21 ** This program is distributed in the hope that it will be useful,
22 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
23 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 ** GNU General Public License for more details.
25 **
26 ** You should have received a copy of the GNU General Public License
27 ** along with this program; if not, write to the Free Software
28 ** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 **
30 **-----------------------------------------------------------------------------
31 **
32 ** The Linux port of the FreeBSD ncr driver has been achieved in
33 ** november 1995 by:
34 **
35 ** Gerard Roudier <groudier@club-internet.fr>
36 **
37 ** Being given that this driver originates from the FreeBSD version, and
38 ** in order to keep synergy on both, any suggested enhancements and corrections
39 ** received on Linux are automatically a potential candidate for the FreeBSD
40 ** version.
41 **
42 ** The original driver has been written for 386bsd and FreeBSD by
43 ** Wolfgang Stanglmeier <wolf@cologne.de>
44 ** Stefan Esser <se@mi.Uni-Koeln.de>
45 **
46 **-----------------------------------------------------------------------------
47 **
48 ** Major contributions:
49 ** --------------------
50 **
51 ** NVRAM detection and reading.
52 ** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
53 **
54 *******************************************************************************
55 */
56
57 #ifndef SYM53C8XX_DEFS_H
58 #define SYM53C8XX_DEFS_H
59
60 /*
61 ** Check supported Linux versions
62 */
63
64 #if !defined(LINUX_VERSION_CODE)
65 #include <linux/version.h>
66 #endif
67 #include <linux/config.h>
68
69 #define LinuxVersionCode(v, p, s) (((v)<<16)+((p)<<8)+(s))
70
71 /*
72 * NCR PQS/PDS special device support.
73 */
74 #ifdef CONFIG_SCSI_NCR53C8XX_PQS_PDS
75 #define SCSI_NCR_PQS_PDS_SUPPORT
76 #endif
77
78 /*
79 * No more an option, enabled by default.
80 */
81 #ifndef CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
82 #define CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
83 #endif
84
85 /*
86 ** These options are not tunable from 'make config'
87 */
88 #define SCSI_NCR_PROC_INFO_SUPPORT
89
90 /*
91 ** If you want a driver as small as possible, donnot define the
92 ** following options.
93 */
94 #define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
95 #define SCSI_NCR_DEBUG_INFO_SUPPORT
96 #define SCSI_NCR_PCI_FIX_UP_SUPPORT
97 #ifdef SCSI_NCR_PROC_INFO_SUPPORT
98 # ifdef CONFIG_SCSI_NCR53C8XX_PROFILE
99 # define SCSI_NCR_PROFILE_SUPPORT
100 # endif
101 # define SCSI_NCR_USER_COMMAND_SUPPORT
102 # define SCSI_NCR_USER_INFO_SUPPORT
103 #endif
104
105 /*==========================================================
106 **
107 ** nvram settings - #define SCSI_NCR_NVRAM_SUPPORT to enable
108 **
109 **==========================================================
110 */
111
112 #ifdef CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
113 #define SCSI_NCR_NVRAM_SUPPORT
114 /* #define SCSI_NCR_DEBUG_NVRAM */
115 #endif
116
117 /* ---------------------------------------------------------------------
118 ** Take into account kernel configured parameters.
119 ** Most of these options can be overridden at startup by a command line.
120 ** ---------------------------------------------------------------------
121 */
122
123 /*
124 * For Ultra2 SCSI support option, use special features and allow 40Mhz
125 * synchronous data transfers.
126 *
127 * Value 5 (default) means:
128 * bit 0 : all features enabled, except:
129 * bit 1 : PCI Write And Invalidate.
130 * bit 2 : Data Phase Mismatch handling from SCRIPTS.
131 *
132 * Use boot options ncr53c8xx=specf:1 if you want all chip features to be
133 * enabled by the driver.
134 */
135 #define SCSI_NCR_SETUP_SPECIAL_FEATURES (3)
136 #define SCSI_NCR_SETUP_ULTRA_SCSI (2)
137 #define SCSI_NCR_MAX_SYNC (40)
138
139 /*
140 * Allow tags from 2 to 64, default 8
141 */
142 #ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS
143 #if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
144 #define SCSI_NCR_MAX_TAGS (2)
145 #elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 64
146 #define SCSI_NCR_MAX_TAGS (64)
147 #else
148 #define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS
149 #endif
150 #else
151 #define SCSI_NCR_MAX_TAGS (8)
152 #endif
153
154 /*
155 * Allow tagged command queuing support if configured with default number
156 * of tags set to max (see above).
157 */
158 #ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
159 #define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
160 #elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
161 #define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS
162 #else
163 #define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
164 #endif
165
166 /*
167 * Use normal IO if configured. Forced for alpha and ppc.
168 */
169 #if defined(CONFIG_SCSI_NCR53C8XX_IOMAPPED)
170 #define SCSI_NCR_IOMAPPED
171 #elif defined(__alpha__) || defined(__powerpc__)
172 #define SCSI_NCR_IOMAPPED
173 #elif defined(__sparc__)
174 #undef SCSI_NCR_IOMAPPED
175 #endif
176
177 /*
178 * Sync transfer frequency at startup.
179 * Allow from 5Mhz to 40Mhz default 20 Mhz.
180 */
181 #ifndef CONFIG_SCSI_NCR53C8XX_SYNC
182 #define CONFIG_SCSI_NCR53C8XX_SYNC (20)
183 #elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
184 #undef CONFIG_SCSI_NCR53C8XX_SYNC
185 #define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC
186 #endif
187
188 #if CONFIG_SCSI_NCR53C8XX_SYNC == 0
189 #define SCSI_NCR_SETUP_DEFAULT_SYNC (255)
190 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5
191 #define SCSI_NCR_SETUP_DEFAULT_SYNC (50)
192 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20
193 #define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
194 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33
195 #define SCSI_NCR_SETUP_DEFAULT_SYNC (11)
196 #else
197 #define SCSI_NCR_SETUP_DEFAULT_SYNC (10)
198 #endif
199
200 /*
201 * Disallow disconnections at boot-up
202 */
203 #ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
204 #define SCSI_NCR_SETUP_DISCONNECTION (0)
205 #else
206 #define SCSI_NCR_SETUP_DISCONNECTION (1)
207 #endif
208
209 /*
210 * Force synchronous negotiation for all targets
211 */
212 #ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
213 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1)
214 #else
215 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
216 #endif
217
218 /*
219 * Disable master parity checking (flawed hardwares need that)
220 */
221 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
222 #define SCSI_NCR_SETUP_MASTER_PARITY (0)
223 #else
224 #define SCSI_NCR_SETUP_MASTER_PARITY (1)
225 #endif
226
227 /*
228 * Disable scsi parity checking (flawed devices may need that)
229 */
230 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
231 #define SCSI_NCR_SETUP_SCSI_PARITY (0)
232 #else
233 #define SCSI_NCR_SETUP_SCSI_PARITY (1)
234 #endif
235
236 /*
237 * Vendor specific stuff
238 */
239 #ifdef CONFIG_SCSI_NCR53C8XX_SYMBIOS_COMPAT
240 #define SCSI_NCR_SETUP_LED_PIN (1)
241 #define SCSI_NCR_SETUP_DIFF_SUPPORT (3)
242 #else
243 #define SCSI_NCR_SETUP_LED_PIN (0)
244 #define SCSI_NCR_SETUP_DIFF_SUPPORT (0)
245 #endif
246
247 /*
248 * Settle time after reset at boot-up
249 */
250 #define SCSI_NCR_SETUP_SETTLE_TIME (2)
251
252 /*
253 ** Other parameters not configurable with "make config"
254 ** Avoid to change these constants, unless you know what you are doing.
255 */
256
257 #define SCSI_NCR_ALWAYS_SIMPLE_TAG
258 #define SCSI_NCR_MAX_SCATTER (127)
259 #define SCSI_NCR_MAX_TARGET (16)
260
261 /* No need to use a too large adapter queue */
262 #if SCSI_NCR_MAX_TAGS <= 32
263 #define SCSI_NCR_CAN_QUEUE (7*SCSI_NCR_MAX_TAGS)
264 #else
265 #define SCSI_NCR_CAN_QUEUE (250)
266 #endif
267
268 #define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS)
269 #define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER)
270
271 #define SCSI_NCR_TIMER_INTERVAL (HZ)
272
273 #if 1 /* defined CONFIG_SCSI_MULTI_LUN */
274 #define SCSI_NCR_MAX_LUN (8)
275 #else
276 #define SCSI_NCR_MAX_LUN (1)
277 #endif
278
279 #ifndef HOSTS_C
280
281 /*
282 ** IO functions definition for big/little endian support.
283 ** For now, the NCR is only supported in little endian addressing mode,
284 ** and big endian byte ordering is only supported for the PPC.
285 ** MMIO is not used on PPC.
286 */
287
288 #ifdef __BIG_ENDIAN
289
290 #if LINUX_VERSION_CODE < LinuxVersionCode(2,1,0)
291 #error "BIG ENDIAN byte ordering needs kernel version >= 2.1.0"
292 #endif
293
294 #if defined(__powerpc__)
295 #define inw_l2b inw
296 #define inl_l2b inl
297 #define outw_b2l outw
298 #define outl_b2l outl
299 #elif defined(__sparc__)
300 #define readw_l2b readw
301 #define readl_l2b readl
302 #define writew_b2l writew
303 #define writel_b2l writel
304 #else
305 #error "Support for BIG ENDIAN is only available for PowerPC and SPARC"
306 #endif
307
308 #else /* little endian */
309
310 #if defined(__i386__) /* i386 implements full FLAT memory/MMIO model */
311 #define inw_raw inw
312 #define inl_raw inl
313 #define outw_raw outw
314 #define outl_raw outl
315 #define readb_raw(a) (*(volatile unsigned char *) (a))
316 #define readw_raw(a) (*(volatile unsigned short *) (a))
317 #define readl_raw(a) (*(volatile unsigned int *) (a))
318 #define writeb_raw(b,a) ((*(volatile unsigned char *) (a)) = (b))
319 #define writew_raw(b,a) ((*(volatile unsigned short *) (a)) = (b))
320 #define writel_raw(b,a) ((*(volatile unsigned int *) (a)) = (b))
321
322 #else /* Other little-endian (for now alpha) */
323 #define inw_raw inw
324 #define inl_raw inl
325 #define outw_raw outw
326 #define outl_raw outl
327 #define readw_raw readw
328 #define readl_raw readl
329 #define writew_raw writew
330 #define writel_raw writel
331
332 #endif
333 #endif
334
335 #ifdef SCSI_NCR_BIG_ENDIAN
336 #error "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
337 #endif
338
339 /*
340 ** NCR53C8XX Device Ids
341 */
342
343 #ifndef PCI_DEVICE_ID_NCR_53C810
344 #define PCI_DEVICE_ID_NCR_53C810 1
345 #endif
346
347 #ifndef PCI_DEVICE_ID_NCR_53C810AP
348 #define PCI_DEVICE_ID_NCR_53C810AP 5
349 #endif
350
351 #ifndef PCI_DEVICE_ID_NCR_53C815
352 #define PCI_DEVICE_ID_NCR_53C815 4
353 #endif
354
355 #ifndef PCI_DEVICE_ID_NCR_53C820
356 #define PCI_DEVICE_ID_NCR_53C820 2
357 #endif
358
359 #ifndef PCI_DEVICE_ID_NCR_53C825
360 #define PCI_DEVICE_ID_NCR_53C825 3
361 #endif
362
363 #ifndef PCI_DEVICE_ID_NCR_53C860
364 #define PCI_DEVICE_ID_NCR_53C860 6
365 #endif
366
367 #ifndef PCI_DEVICE_ID_NCR_53C875
368 #define PCI_DEVICE_ID_NCR_53C875 0xf
369 #endif
370
371 #ifndef PCI_DEVICE_ID_NCR_53C875J
372 #define PCI_DEVICE_ID_NCR_53C875J 0x8f
373 #endif
374
375 #ifndef PCI_DEVICE_ID_NCR_53C885
376 #define PCI_DEVICE_ID_NCR_53C885 0xd
377 #endif
378
379 #ifndef PCI_DEVICE_ID_NCR_53C895
380 #define PCI_DEVICE_ID_NCR_53C895 0xc
381 #endif
382
383 #ifndef PCI_DEVICE_ID_NCR_53C896
384 #define PCI_DEVICE_ID_NCR_53C896 0xb
385 #endif
386
387 /*
388 ** NCR53C8XX devices features table.
389 */
390 typedef struct {
391 unsigned short device_id;
392 unsigned short revision_id;
393 char *name;
394 unsigned char burst_max;
395 unsigned char offset_max;
396 unsigned char nr_divisor;
397 unsigned int features;
398 #define FE_LED0 (1<<0)
399 #define FE_WIDE (1<<1)
400 #define FE_ULTRA (1<<2)
401 #define FE_ULTRA2 (1<<3)
402 #define FE_DBLR (1<<4)
403 #define FE_QUAD (1<<5)
404 #define FE_ERL (1<<6)
405 #define FE_CLSE (1<<7)
406 #define FE_WRIE (1<<8)
407 #define FE_ERMP (1<<9)
408 #define FE_BOF (1<<10)
409 #define FE_DFS (1<<11)
410 #define FE_PFEN (1<<12)
411 #define FE_LDSTR (1<<13)
412 #define FE_RAM (1<<14)
413 #define FE_CLK80 (1<<15)
414 #define FE_RAM8K (1<<16)
415 #define FE_64BIT (1<<17)
416 #define FE_IO256 (1<<18)
417 #define FE_NOPM (1<<19)
418 #define FE_LEDC (1<<20)
419 #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
420 #define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_ULTRA2|FE_DBLR|FE_QUAD|F_CLK80)
421 #define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
422 } ncr_chip;
423
424 /*
425 ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 3.
426 ** Memory Read transaction terminated by a retry followed by
427 ** Memory Read Line command.
428 */
429 #define FE_CACHE0_SET (FE_CACHE_SET & ~FE_ERL)
430
431 /*
432 ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 5.
433 ** On paper, this errata is harmless. But it is a good reason for
434 ** using a shorter programmed burst length (64 DWORDS instead of 128).
435 */
436
437 #define SCSI_NCR_CHIP_TABLE \
438 { \
439 {PCI_DEVICE_ID_NCR_53C810, 0x0f, "810", 4, 8, 4, \
440 FE_ERL} \
441 , \
442 {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, \
443 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF} \
444 , \
445 {PCI_DEVICE_ID_NCR_53C815, 0xff, "815", 4, 8, 4, \
446 FE_ERL|FE_BOF} \
447 , \
448 {PCI_DEVICE_ID_NCR_53C820, 0xff, "820", 4, 8, 4, \
449 FE_WIDE|FE_ERL} \
450 , \
451 {PCI_DEVICE_ID_NCR_53C825, 0x0f, "825", 4, 8, 4, \
452 FE_WIDE|FE_ERL|FE_BOF} \
453 , \
454 {PCI_DEVICE_ID_NCR_53C825, 0xff, "825a", 6, 8, 4, \
455 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM} \
456 , \
457 {PCI_DEVICE_ID_NCR_53C860, 0xff, "860", 4, 8, 5, \
458 FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN} \
459 , \
460 {PCI_DEVICE_ID_NCR_53C875, 0x01, "875", 6, 16, 5, \
461 FE_WIDE|FE_ULTRA|FE_CLK80|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}\
462 , \
463 {PCI_DEVICE_ID_NCR_53C875, 0x0f, "875", 6, 16, 5, \
464 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}\
465 , \
466 {PCI_DEVICE_ID_NCR_53C875, 0xff, "876", 6, 16, 5, \
467 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}\
468 , \
469 {PCI_DEVICE_ID_NCR_53C875J,0xff, "875J", 6, 16, 5, \
470 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}\
471 , \
472 {PCI_DEVICE_ID_NCR_53C885, 0xff, "885", 6, 16, 5, \
473 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}\
474 , \
475 {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, \
476 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM}\
477 , \
478 {PCI_DEVICE_ID_NCR_53C896, 0xff, "896", 7, 31, 7, \
479 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|\
480 FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC}\
481 }
482
483 /*
484 * List of supported NCR chip ids
485 */
486 #define SCSI_NCR_CHIP_IDS \
487 { \
488 PCI_DEVICE_ID_NCR_53C810, \
489 PCI_DEVICE_ID_NCR_53C815, \
490 PCI_DEVICE_ID_NCR_53C820, \
491 PCI_DEVICE_ID_NCR_53C825, \
492 PCI_DEVICE_ID_NCR_53C860, \
493 PCI_DEVICE_ID_NCR_53C875, \
494 PCI_DEVICE_ID_NCR_53C875J, \
495 PCI_DEVICE_ID_NCR_53C885, \
496 PCI_DEVICE_ID_NCR_53C895, \
497 PCI_DEVICE_ID_NCR_53C896 \
498 }
499
500 /*
501 ** Initial setup.
502 ** Can be overriden at startup by a command line.
503 */
504 #define SCSI_NCR_DRIVER_SETUP \
505 { \
506 SCSI_NCR_SETUP_MASTER_PARITY, \
507 SCSI_NCR_SETUP_SCSI_PARITY, \
508 SCSI_NCR_SETUP_DISCONNECTION, \
509 SCSI_NCR_SETUP_SPECIAL_FEATURES, \
510 SCSI_NCR_SETUP_ULTRA_SCSI, \
511 SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \
512 0, \
513 0, \
514 1, \
515 1, \
516 SCSI_NCR_SETUP_DEFAULT_TAGS, \
517 SCSI_NCR_SETUP_DEFAULT_SYNC, \
518 0x00, \
519 7, \
520 SCSI_NCR_SETUP_LED_PIN, \
521 1, \
522 SCSI_NCR_SETUP_SETTLE_TIME, \
523 SCSI_NCR_SETUP_DIFF_SUPPORT, \
524 0, \
525 1, \
526 0, \
527 0 \
528 }
529
530 /*
531 ** Boot fail safe setup.
532 ** Override initial setup from boot command line:
533 ** ncr53c8xx=safe:y
534 */
535 #define SCSI_NCR_DRIVER_SAFE_SETUP \
536 { \
537 0, \
538 1, \
539 0, \
540 0, \
541 0, \
542 0, \
543 0, \
544 0, \
545 1, \
546 2, \
547 0, \
548 255, \
549 0x00, \
550 255, \
551 0, \
552 0, \
553 10, \
554 1, \
555 1, \
556 1, \
557 0, \
558 0 \
559 }
560
561 /**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
562
563 /*-----------------------------------------------------------------
564 **
565 ** The ncr 53c810 register structure.
566 **
567 **-----------------------------------------------------------------
568 */
569
570 struct ncr_reg {
571 /*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */
572
573 /*01*/ u_char nc_scntl1; /* no reset */
574 #define ISCON 0x10 /* connected to scsi */
575 #define CRST 0x08 /* force reset */
576
577 /*02*/ u_char nc_scntl2; /* no disconnect expected */
578 #define SDU 0x80 /* cmd: disconnect will raise error */
579 #define CHM 0x40 /* sta: chained mode */
580 #define WSS 0x08 /* sta: wide scsi send [W]*/
581 #define WSR 0x01 /* sta: wide scsi received [W]*/
582
583 /*03*/ u_char nc_scntl3; /* cnf system clock dependent */
584 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
585 #define ULTRA 0x80 /* cmd: ULTRA enable */
586
587 /*04*/ u_char nc_scid; /* cnf host adapter scsi address */
588 #define RRE 0x40 /* r/w:e enable response to resel. */
589 #define SRE 0x20 /* r/w:e enable response to select */
590
591 /*05*/ u_char nc_sxfer; /* ### Sync speed and count */
592
593 /*06*/ u_char nc_sdid; /* ### Destination-ID */
594
595 /*07*/ u_char nc_gpreg; /* ??? IO-Pins */
596
597 /*08*/ u_char nc_sfbr; /* ### First byte in phase */
598
599 /*09*/ u_char nc_socl;
600 #define CREQ 0x80 /* r/w: SCSI-REQ */
601 #define CACK 0x40 /* r/w: SCSI-ACK */
602 #define CBSY 0x20 /* r/w: SCSI-BSY */
603 #define CSEL 0x10 /* r/w: SCSI-SEL */
604 #define CATN 0x08 /* r/w: SCSI-ATN */
605 #define CMSG 0x04 /* r/w: SCSI-MSG */
606 #define CC_D 0x02 /* r/w: SCSI-C_D */
607 #define CI_O 0x01 /* r/w: SCSI-I_O */
608
609 /*0a*/ u_char nc_ssid;
610
611 /*0b*/ u_char nc_sbcl;
612
613 /*0c*/ u_char nc_dstat;
614 #define DFE 0x80 /* sta: dma fifo empty */
615 #define MDPE 0x40 /* int: master data parity error */
616 #define BF 0x20 /* int: script: bus fault */
617 #define ABRT 0x10 /* int: script: command aborted */
618 #define SSI 0x08 /* int: script: single step */
619 #define SIR 0x04 /* int: script: interrupt instruct. */
620 #define IID 0x01 /* int: script: illegal instruct. */
621
622 /*0d*/ u_char nc_sstat0;
623 #define ILF 0x80 /* sta: data in SIDL register lsb */
624 #define ORF 0x40 /* sta: data in SODR register lsb */
625 #define OLF 0x20 /* sta: data in SODL register lsb */
626 #define AIP 0x10 /* sta: arbitration in progress */
627 #define LOA 0x08 /* sta: arbitration lost */
628 #define WOA 0x04 /* sta: arbitration won */
629 #define IRST 0x02 /* sta: scsi reset signal */
630 #define SDP 0x01 /* sta: scsi parity signal */
631
632 /*0e*/ u_char nc_sstat1;
633 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
634
635 /*0f*/ u_char nc_sstat2;
636 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
637 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
638 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
639 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
640 #define LDSC 0x02 /* sta: disconnect & reconnect */
641
642 /*10*/ u_int32 nc_dsa; /* --> Base page */
643
644 /*14*/ u_char nc_istat; /* --> Main Command and status */
645 #define CABRT 0x80 /* cmd: abort current operation */
646 #define SRST 0x40 /* mod: reset chip */
647 #define SIGP 0x20 /* r/w: message from host to ncr */
648 #define SEM 0x10 /* r/w: message between host + ncr */
649 #define CON 0x08 /* sta: connected to scsi */
650 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
651 #define SIP 0x02 /* sta: scsi-interrupt */
652 #define DIP 0x01 /* sta: host/script interrupt */
653
654 /*15*/ u_char nc_istat1; /* 896 only */
655 /*16*/ u_char nc_mbox0; /* 896 only */
656 /*17*/ u_char nc_mbox1; /* 896 only */
657
658 /*18*/ u_char nc_ctest0;
659 /*19*/ u_char nc_ctest1;
660
661 /*1a*/ u_char nc_ctest2;
662 #define CSIGP 0x40
663
664 /*1b*/ u_char nc_ctest3;
665 #define FLF 0x08 /* cmd: flush dma fifo */
666 #define CLF 0x04 /* cmd: clear dma fifo */
667 #define FM 0x02 /* mod: fetch pin mode */
668 #define WRIE 0x01 /* mod: write and invalidate enable */
669
670 /*1c*/ u_int32 nc_temp; /* ### Temporary stack */
671
672 /*20*/ u_char nc_dfifo;
673 /*21*/ u_char nc_ctest4;
674 #define BDIS 0x80 /* mod: burst disable */
675 #define MPEE 0x08 /* mod: master parity error enable */
676
677 /*22*/ u_char nc_ctest5;
678 #define DFS 0x20 /* mod: dma fifo size */
679 /*23*/ u_char nc_ctest6;
680
681 /*24*/ u_int32 nc_dbc; /* ### Byte count and command */
682 /*28*/ u_int32 nc_dnad; /* ### Next command register */
683 /*2c*/ u_int32 nc_dsp; /* --> Script Pointer */
684 /*30*/ u_int32 nc_dsps; /* --> Script pointer save/opcode#2 */
685
686 /*34*/ u_char nc_scratcha; /* Temporary register a */
687 /*35*/ u_char nc_scratcha1;
688 /*36*/ u_char nc_scratcha2;
689 /*37*/ u_char nc_scratcha3;
690
691 /*38*/ u_char nc_dmode;
692 #define BL_2 0x80 /* mod: burst length shift value +2 */
693 #define BL_1 0x40 /* mod: burst length shift value +1 */
694 #define ERL 0x08 /* mod: enable read line */
695 #define ERMP 0x04 /* mod: enable read multiple */
696 #define BOF 0x02 /* mod: burst op code fetch */
697
698 /*39*/ u_char nc_dien;
699 /*3a*/ u_char nc_dwt;
700
701 /*3b*/ u_char nc_dcntl; /* --> Script execution control */
702 #define CLSE 0x80 /* mod: cache line size enable */
703 #define PFF 0x40 /* cmd: pre-fetch flush */
704 #define PFEN 0x20 /* mod: pre-fetch enable */
705 #define SSM 0x10 /* mod: single step mode */
706 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
707 #define STD 0x04 /* cmd: start dma mode */
708 #define IRQD 0x02 /* mod: irq disable */
709 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
710
711 /*3c*/ u_int32 nc_adder;
712
713 /*40*/ u_short nc_sien; /* -->: interrupt enable */
714 /*42*/ u_short nc_sist; /* <--: interrupt status */
715 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
716 #define STO 0x0400/* sta: timeout (select) */
717 #define GEN 0x0200/* sta: timeout (general) */
718 #define HTH 0x0100/* sta: timeout (handshake) */
719 #define MA 0x80 /* sta: phase mismatch */
720 #define CMP 0x40 /* sta: arbitration complete */
721 #define SEL 0x20 /* sta: selected by another device */
722 #define RSL 0x10 /* sta: reselected by another device*/
723 #define SGE 0x08 /* sta: gross error (over/underflow)*/
724 #define UDC 0x04 /* sta: unexpected disconnect */
725 #define RST 0x02 /* sta: scsi bus reset detected */
726 #define PAR 0x01 /* sta: scsi parity error */
727
728 /*44*/ u_char nc_slpar;
729 /*45*/ u_char nc_swide;
730 /*46*/ u_char nc_macntl;
731 /*47*/ u_char nc_gpcntl;
732 /*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/
733 /*49*/ u_char nc_stime1; /* cmd: timeout user defined */
734 /*4a*/ u_short nc_respid; /* sta: Reselect-IDs */
735
736 /*4c*/ u_char nc_stest0;
737
738 /*4d*/ u_char nc_stest1;
739 #define DBLEN 0x08 /* clock doubler running */
740 #define DBLSEL 0x04 /* clock doubler selected */
741
742
743 /*4e*/ u_char nc_stest2;
744 #define ROF 0x40 /* reset scsi offset (after gross error!) */
745 #define EXT 0x02 /* extended filtering */
746
747 /*4f*/ u_char nc_stest3;
748 #define TE 0x80 /* c: tolerAnt enable */
749 #define HSC 0x20 /* c: Halt SCSI Clock */
750 #define CSF 0x02 /* c: clear scsi fifo */
751
752 /*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */
753 /*52*/ u_char nc_stest4;
754 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
755 #define SMODE_HVD 0x40 /* High Voltage Differential */
756 #define SMODE_SE 0x80 /* Single Ended */
757 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
758 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
759
760 /*53*/ u_char nc_53_;
761 /*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */
762 /*56*/ u_char nc_ccntl0; /* Chip Control 0 (896) */
763 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
764 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
765 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
766 #define DISFC 0x10 /* Disable Auto FIFO Clear */
767 #define DILS 0x02 /* Disable Internal Load/Store */
768 #define DPR 0x01 /* Disable Pipe Req */
769
770 /*57*/ u_char nc_ccntl1; /* Chip Control 1 (896) */
771 #define ZMOD 0x80 /* High Impedance Mode */
772 #define DDAC 0x08 /* Disable Dual Address Cycle */
773 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
774 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
775 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
776
777 /*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */
778 /*5a*/ u_short nc_5a_;
779
780 /*5c*/ u_char nc_scr0; /* Working register B */
781 /*5d*/ u_char nc_scr1; /* */
782 /*5e*/ u_char nc_scr2; /* */
783 /*5f*/ u_char nc_scr3; /* */
784
785 /*60*/ u_char nc_scrx[64]; /* Working register C-R */
786 /*a0*/ u_int32 nc_mmrs; /* Memory Move Read Selector */
787 /*a4*/ u_int32 nc_mmws; /* Memory Move Write Selector */
788 /*a8*/ u_int32 nc_sfs; /* Script Fetch Selector */
789 /*ac*/ u_int32 nc_drs; /* DSA Relative Selector */
790 /*b0*/ u_int32 nc_sbms; /* Static Block Move Selector */
791 /*b4*/ u_int32 nc_dbms; /* Dynamic Block Move Selector */
792 /*b8*/ u_int32 nc_dnad64; /* DMA Next Address 64 */
793 /*bc*/ u_int32 nc_bc_;
794
795 /*c0*/ u_int32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
796 /*c4*/ u_int32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
797 /*c8*/ u_int32 nc_rbc; /* Remaining Byte Count */
798 /*cc*/ u_int32 nc_ua; /* Updated Address */
799 /*d0*/ u_int32 nc_esa; /* Entry Storage Address */
800 /*d4*/ u_char nc_ia; /* Instruction Address */
801 /*d5*/ u_char nc_ia1;
802 /*d6*/ u_char nc_ia2;
803 /*d7*/ u_char nc_ia3;
804 /*d8*/ u_int32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
805 /*dc*/ u_int32 nc_csbc; /* Cumulative SCSI Byte Count */
806 };
807
808 /*-----------------------------------------------------------
809 **
810 ** Utility macros for the script.
811 **
812 **-----------------------------------------------------------
813 */
814
815 #define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
816 #define REG(r) REGJ (nc_, r)
817
818 #ifndef TARGET_MODE
819 #define TARGET_MODE 0
820 #endif
821
822 typedef u_int32 ncrcmd;
823
824 /*-----------------------------------------------------------
825 **
826 ** SCSI phases
827 **
828 **-----------------------------------------------------------
829 */
830
831 #define SCR_DATA_OUT 0x00000000
832 #define SCR_DATA_IN 0x01000000
833 #define SCR_COMMAND 0x02000000
834 #define SCR_STATUS 0x03000000
835 #define SCR_ILG_OUT 0x04000000
836 #define SCR_ILG_IN 0x05000000
837 #define SCR_MSG_OUT 0x06000000
838 #define SCR_MSG_IN 0x07000000
839
840 /*-----------------------------------------------------------
841 **
842 ** Data transfer via SCSI.
843 **
844 **-----------------------------------------------------------
845 **
846 ** MOVE_ABS (LEN)
847 ** <<start address>>
848 **
849 ** MOVE_IND (LEN)
850 ** <<dnad_offset>>
851 **
852 ** MOVE_TBL
853 ** <<dnad_offset>>
854 **
855 **-----------------------------------------------------------
856 */
857
858 #define SCR_MOVE_ABS(l) ((0x08000000 ^ (TARGET_MODE << 1ul)) | (l))
859 #define SCR_MOVE_IND(l) ((0x28000000 ^ (TARGET_MODE << 1ul)) | (l))
860 #define SCR_MOVE_TBL (0x18000000 ^ (TARGET_MODE << 1ul))
861
862 struct scr_tblmove {
863 u_int32 size;
864 u_int32 addr;
865 };
866
867 /*-----------------------------------------------------------
868 **
869 ** Selection
870 **
871 **-----------------------------------------------------------
872 **
873 ** SEL_ABS | SCR_ID (0..7) [ | REL_JMP]
874 ** <<alternate_address>>
875 **
876 ** SEL_TBL | << dnad_offset>> [ | REL_JMP]
877 ** <<alternate_address>>
878 **
879 **-----------------------------------------------------------
880 */
881
882 #define SCR_SEL_ABS 0x40000000
883 #define SCR_SEL_ABS_ATN 0x41000000
884 #define SCR_SEL_TBL 0x42000000
885 #define SCR_SEL_TBL_ATN 0x43000000
886
887 struct scr_tblsel {
888 u_char sel_0;
889 u_char sel_sxfer;
890 u_char sel_id;
891 u_char sel_scntl3;
892 };
893
894 #define SCR_JMP_REL 0x04000000
895 #define SCR_ID(id) (((u_int32)(id)) << 16)
896
897 /*-----------------------------------------------------------
898 **
899 ** Waiting for Disconnect or Reselect
900 **
901 **-----------------------------------------------------------
902 **
903 ** WAIT_DISC
904 ** dummy: <<alternate_address>>
905 **
906 ** WAIT_RESEL
907 ** <<alternate_address>>
908 **
909 **-----------------------------------------------------------
910 */
911
912 #define SCR_WAIT_DISC 0x48000000
913 #define SCR_WAIT_RESEL 0x50000000
914
915 /*-----------------------------------------------------------
916 **
917 ** Bit Set / Reset
918 **
919 **-----------------------------------------------------------
920 **
921 ** SET (flags {|.. })
922 **
923 ** CLR (flags {|.. })
924 **
925 **-----------------------------------------------------------
926 */
927
928 #define SCR_SET(f) (0x58000000 | (f))
929 #define SCR_CLR(f) (0x60000000 | (f))
930
931 #define SCR_CARRY 0x00000400
932 #define SCR_TRG 0x00000200
933 #define SCR_ACK 0x00000040
934 #define SCR_ATN 0x00000008
935
936
937
938
939 /*-----------------------------------------------------------
940 **
941 ** Memory to memory move
942 **
943 **-----------------------------------------------------------
944 **
945 ** COPY (bytecount)
946 ** << source_address >>
947 ** << destination_address >>
948 **
949 ** SCR_COPY sets the NO FLUSH option by default.
950 ** SCR_COPY_F does not set this option.
951 **
952 ** For chips which do not support this option,
953 ** ncr_copy_and_bind() will remove this bit.
954 **-----------------------------------------------------------
955 */
956
957 #define SCR_NO_FLUSH 0x01000000
958
959 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
960 #define SCR_COPY_F(n) (0xc0000000 | (n))
961
962 /*-----------------------------------------------------------
963 **
964 ** Register move and binary operations
965 **
966 **-----------------------------------------------------------
967 **
968 ** SFBR_REG (reg, op, data) reg = SFBR op data
969 ** << 0 >>
970 **
971 ** REG_SFBR (reg, op, data) SFBR = reg op data
972 ** << 0 >>
973 **
974 ** REG_REG (reg, op, data) reg = reg op data
975 ** << 0 >>
976 **
977 **-----------------------------------------------------------
978 ** On 810A, 860, 825A, 875, 895 and 896 chips the content
979 ** of SFBR register can be used as data (SCR_SFBR_DATA).
980 ** The 896 has additionnal IO registers starting at
981 ** offset 0x80. Bit 7 of register offset is stored in
982 ** bit 7 of the SCRIPTS instruction first DWORD.
983 **-----------------------------------------------------------
984 */
985
986 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
987
988 #define SCR_SFBR_REG(reg,op,data) \
989 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
990
991 #define SCR_REG_SFBR(reg,op,data) \
992 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
993
994 #define SCR_REG_REG(reg,op,data) \
995 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
996
997
998 #define SCR_LOAD 0x00000000
999 #define SCR_SHL 0x01000000
1000 #define SCR_OR 0x02000000
1001 #define SCR_XOR 0x03000000
1002 #define SCR_AND 0x04000000
1003 #define SCR_SHR 0x05000000
1004 #define SCR_ADD 0x06000000
1005 #define SCR_ADDC 0x07000000
1006
1007 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
1008
1009 /*-----------------------------------------------------------
1010 **
1011 ** FROM_REG (reg) SFBR = reg
1012 ** << 0 >>
1013 **
1014 ** TO_REG (reg) reg = SFBR
1015 ** << 0 >>
1016 **
1017 ** LOAD_REG (reg, data) reg = <data>
1018 ** << 0 >>
1019 **
1020 ** LOAD_SFBR(data) SFBR = <data>
1021 ** << 0 >>
1022 **
1023 **-----------------------------------------------------------
1024 */
1025
1026 #define SCR_FROM_REG(reg) \
1027 SCR_REG_SFBR(reg,SCR_OR,0)
1028
1029 #define SCR_TO_REG(reg) \
1030 SCR_SFBR_REG(reg,SCR_OR,0)
1031
1032 #define SCR_LOAD_REG(reg,data) \
1033 SCR_REG_REG(reg,SCR_LOAD,data)
1034
1035 #define SCR_LOAD_SFBR(data) \
1036 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
1037
1038 /*-----------------------------------------------------------
1039 **
1040 ** LOAD from memory to register.
1041 ** STORE from register to memory.
1042 **
1043 ** Only supported by 810A, 860, 825A, 875, 895 and 896.
1044 **
1045 **-----------------------------------------------------------
1046 **
1047 ** LOAD_ABS (LEN)
1048 ** <<start address>>
1049 **
1050 ** LOAD_REL (LEN) (DSA relative)
1051 ** <<dsa_offset>>
1052 **
1053 **-----------------------------------------------------------
1054 */
1055
1056 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
1057 #define SCR_NO_FLUSH2 0x02000000
1058 #define SCR_DSA_REL2 0x10000000
1059
1060 #define SCR_LOAD_R(reg, how, n) \
1061 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1062
1063 #define SCR_STORE_R(reg, how, n) \
1064 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1065
1066 #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
1067 #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
1068 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
1069 #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
1070
1071 #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
1072 #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
1073 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
1074 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
1075
1076
1077 /*-----------------------------------------------------------
1078 **
1079 ** Waiting for Disconnect or Reselect
1080 **
1081 **-----------------------------------------------------------
1082 **
1083 ** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
1084 ** <<address>>
1085 **
1086 ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
1087 ** <<distance>>
1088 **
1089 ** CALL [ | IFTRUE/IFFALSE ( ... ) ]
1090 ** <<address>>
1091 **
1092 ** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
1093 ** <<distance>>
1094 **
1095 ** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
1096 ** <<dummy>>
1097 **
1098 ** INT [ | IFTRUE/IFFALSE ( ... ) ]
1099 ** <<ident>>
1100 **
1101 ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
1102 ** <<ident>>
1103 **
1104 ** Conditions:
1105 ** WHEN (phase)
1106 ** IF (phase)
1107 ** CARRY
1108 ** DATA (data, mask)
1109 **
1110 **-----------------------------------------------------------
1111 */
1112
1113 #define SCR_NO_OP 0x80000000
1114 #define SCR_JUMP 0x80080000
1115 #define SCR_JUMP64 0x80480000
1116 #define SCR_JUMPR 0x80880000
1117 #define SCR_CALL 0x88080000
1118 #define SCR_CALLR 0x88880000
1119 #define SCR_RETURN 0x90080000
1120 #define SCR_INT 0x98080000
1121 #define SCR_INT_FLY 0x98180000
1122
1123 #define IFFALSE(arg) (0x00080000 | (arg))
1124 #define IFTRUE(arg) (0x00000000 | (arg))
1125
1126 #define WHEN(phase) (0x00030000 | (phase))
1127 #define IF(phase) (0x00020000 | (phase))
1128
1129 #define DATA(D) (0x00040000 | ((D) & 0xff))
1130 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
1131
1132 #define CARRYSET (0x00200000)
1133
1134 /*-----------------------------------------------------------
1135 **
1136 ** SCSI constants.
1137 **
1138 **-----------------------------------------------------------
1139 */
1140
1141 /*
1142 ** Messages
1143 */
1144
1145 #define M_COMPLETE (0x00)
1146 #define M_EXTENDED (0x01)
1147 #define M_SAVE_DP (0x02)
1148 #define M_RESTORE_DP (0x03)
1149 #define M_DISCONNECT (0x04)
1150 #define M_ID_ERROR (0x05)
1151 #define M_ABORT (0x06)
1152 #define M_REJECT (0x07)
1153 #define M_NOOP (0x08)
1154 #define M_PARITY (0x09)
1155 #define M_LCOMPLETE (0x0a)
1156 #define M_FCOMPLETE (0x0b)
1157 #define M_RESET (0x0c)
1158 #define M_ABORT_TAG (0x0d)
1159 #define M_CLEAR_QUEUE (0x0e)
1160 #define M_INIT_REC (0x0f)
1161 #define M_REL_REC (0x10)
1162 #define M_TERMINATE (0x11)
1163 #define M_SIMPLE_TAG (0x20)
1164 #define M_HEAD_TAG (0x21)
1165 #define M_ORDERED_TAG (0x22)
1166 #define M_IGN_RESIDUE (0x23)
1167 #define M_IDENTIFY (0x80)
1168
1169 #define M_X_MODIFY_DP (0x00)
1170 #define M_X_SYNC_REQ (0x01)
1171 #define M_X_WIDE_REQ (0x03)
1172
1173 /*
1174 ** Status
1175 */
1176
1177 #define S_GOOD (0x00)
1178 #define S_CHECK_COND (0x02)
1179 #define S_COND_MET (0x04)
1180 #define S_BUSY (0x08)
1181 #define S_INT (0x10)
1182 #define S_INT_COND_MET (0x14)
1183 #define S_CONFLICT (0x18)
1184 #define S_TERMINATED (0x20)
1185 #define S_QUEUE_FULL (0x28)
1186 #define S_ILLEGAL (0xff)
1187 #define S_SENSE (0x80)
1188
1189 /*
1190 * End of ncrreg from FreeBSD
1191 */
1192
1193 #endif /* !defined HOSTS_C */
1194
1195 #endif /* defined SYM53C8XX_DEFS_H */
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