drivers/scsi/mesh.h

   1 /*
   2  * mesh.h: definitions for the driver for the MESH SCSI bus adaptor
   3  * (Macintosh Enhanced SCSI Hardware) found on Power Macintosh computers.
   4  *
   5  * Copyright (C) 1996 Paul Mackerras.
   6  */
   7 #ifndef _MESH_H
   8 #define _MESH_H
   9
  10 extern struct proc_dir_entry proc_scsi_mesh;
  11
  12 int mesh_detect(Scsi_Host_Template *);
  13 int mesh_command(Scsi_Cmnd *);
  14 int mesh_queue(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
  15 int mesh_abort(Scsi_Cmnd *);
  16 int mesh_reset(Scsi_Cmnd *, unsigned int);
  17
  18 #define SCSI_MESH {                                     \
  19         proc_dir:       &proc_scsi_mesh,                \
  20         name:           "MESH",                         \
  21         detect:         mesh_detect,                    \
  22         command:        mesh_command,                   \
  23         queuecommand:   mesh_queue,                     \
  24         abort:          mesh_abort,                     \
  25         reset:          mesh_reset,                     \
  26         can_queue:      20,                             \
  27         this_id:        7,                              \
  28         sg_tablesize:   SG_ALL,                         \
  29         cmd_per_lun:    2,                              \
  30         use_clustering: DISABLE_CLUSTERING,             \
  31         use_new_eh_code: 1,                             \
  32 }
  33
  34 /*
  35  * Registers in the MESH controller.
  36  */
  37
  38 struct mesh_regs {
  39         unsigned char   count_lo;
  40         char pad0[15];
  41         unsigned char   count_hi;
  42         char pad1[15];
  43         unsigned char   fifo;
  44         char pad2[15];
  45         unsigned char   sequence;
  46         char pad3[15];
  47         unsigned char   bus_status0;
  48         char pad4[15];
  49         unsigned char   bus_status1;
  50         char pad5[15];
  51         unsigned char   fifo_count;
  52         char pad6[15];
  53         unsigned char   exception;
  54         char pad7[15];
  55         unsigned char   error;
  56         char pad8[15];
  57         unsigned char   intr_mask;
  58         char pad9[15];
  59         unsigned char   interrupt;
  60         char pad10[15];
  61         unsigned char   source_id;
  62         char pad11[15];
  63         unsigned char   dest_id;
  64         char pad12[15];
  65         unsigned char   sync_params;
  66         char pad13[15];
  67         unsigned char   mesh_id;
  68         char pad14[15];
  69         unsigned char   sel_timeout;
  70         char pad15[15];
  71 };
  72
  73 /* Bits in the sequence register. */
  74 #define SEQ_DMA_MODE    0x80    /* use DMA for data transfer */
  75 #define SEQ_TARGET      0x40    /* put the controller into target mode */
  76 #define SEQ_ATN         0x20    /* assert ATN signal */
  77 #define SEQ_ACTIVE_NEG  0x10    /* use active negation on REQ/ACK */
  78 #define SEQ_CMD         0x0f    /* command bits: */
  79 #define SEQ_ARBITRATE   1       /*  get the bus */
  80 #define SEQ_SELECT      2       /*  select a target */
  81 #define SEQ_COMMAND     3       /*  send a command */
  82 #define SEQ_STATUS      4       /*  receive status */
  83 #define SEQ_DATAOUT     5       /*  send data */
  84 #define SEQ_DATAIN      6       /*  receive data */
  85 #define SEQ_MSGOUT      7       /*  send a message */
  86 #define SEQ_MSGIN       8       /*  receive a message */
  87 #define SEQ_BUSFREE     9       /*  look for bus free */
  88 #define SEQ_ENBPARITY   0x0a    /*  enable parity checking */
  89 #define SEQ_DISPARITY   0x0b    /*  disable parity checking */
  90 #define SEQ_ENBRESEL    0x0c    /*  enable reselection */
  91 #define SEQ_DISRESEL    0x0d    /*  disable reselection */
  92 #define SEQ_RESETMESH   0x0e    /*  reset the controller */
  93 #define SEQ_FLUSHFIFO   0x0f    /*  clear out the FIFO */
  94
  95 /* Bits in the bus_status0 and bus_status1 registers:
  96    these correspond directly to the SCSI bus control signals. */
  97 #define BS0_REQ         0x20
  98 #define BS0_ACK         0x10
  99 #define BS0_ATN         0x08
 100 #define BS0_MSG         0x04
 101 #define BS0_CD          0x02
 102 #define BS0_IO          0x01
 103 #define BS1_RST         0x80
 104 #define BS1_BSY         0x40
 105 #define BS1_SEL         0x20
 106
 107 /* Bus phases defined by the bits in bus_status0 */
 108 #define BS0_PHASE       (BS0_MSG+BS0_CD+BS0_IO)
 109 #define BP_DATAOUT      0
 110 #define BP_DATAIN       BS0_IO
 111 #define BP_COMMAND      BS0_CD
 112 #define BP_STATUS       (BS0_CD+BS0_IO)
 113 #define BP_MSGOUT       (BS0_MSG+BS0_CD)
 114 #define BP_MSGIN        (BS0_MSG+BS0_CD+BS0_IO)
 115
 116 /* Bits in the exception register. */
 117 #define EXC_SELWATN     0x20    /* (as target) we were selected with ATN */
 118 #define EXC_SELECTED    0x10    /* (as target) we were selected w/o ATN */
 119 #define EXC_RESELECTED  0x08    /* (as initiator) we were reselected */
 120 #define EXC_ARBLOST     0x04    /* we lost arbitration */
 121 #define EXC_PHASEMM     0x02    /* SCSI phase mismatch */
 122 #define EXC_SELTO       0x01    /* selection timeout */
 123
 124 /* Bits in the error register */
 125 #define ERR_UNEXPDISC   0x40    /* target unexpectedly disconnected */
 126 #define ERR_SCSIRESET   0x20    /* SCSI bus got reset on us */
 127 #define ERR_SEQERR      0x10    /* we did something the chip didn't like */
 128 #define ERR_PARITY      0x01    /* parity error was detected */
 129
 130 /* Bits in the interrupt and intr_mask registers */
 131 #define INT_ERROR       0x04    /* error interrupt */
 132 #define INT_EXCEPTION   0x02    /* exception interrupt */
 133 #define INT_CMDDONE     0x01    /* command done interrupt */
 134
 135 /* Fields in the sync_params register */
 136 #define SYNC_OFF(x)     ((x) >> 4)      /* offset field */
 137 #define SYNC_PER(x)     ((x) & 0xf)     /* period field */
 138 #define SYNC_PARAMS(o, p)       (((o) << 4) | (p))
 139 #define ASYNC_PARAMS    2       /* sync_params value for async xfers */
 140
 141 /*
 142  * Assuming a clock frequency of 50MHz:
 143  *
 144  * The transfer period with SYNC_PER(sync_params) == x
 145  * is (x + 2) * 40ns, except that x == 0 gives 100ns.
 146  *
 147  * The units of the sel_timeout register are 10ms.
 148  */
 149
 150
 151 #endif /* _MESH_H */