drivers/scsi/fastlane.c

   1 /* fastlane.c: Driver for Phase5's Fastlane SCSI Controller.
   2  *
   3  * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
   4  *
   5  * This driver is based on the CyberStorm driver, hence the occasional
   6  * reference to CyberStorm.
   7  *
   8  * Betatesting & crucial adjustments by
   9  *        Patrik Rak (prak3264@ss1000.ms.mff.cuni.cz)
  10  *
  11  */
  12
  13 /* TODO:
  14  *
  15  * o According to the doc from laire, it is required to reset the DMA when
  16  *   the transfer is done. ATM we reset DMA just before every new
  17  *   dma_init_(read|write).
  18  *
  19  * 1) Figure out how to make a cleaner merge with the sparc driver with regard
  20  *    to the caches and the Sparc MMU mapping.
  21  * 2) Make as few routines required outside the generic driver. A lot of the
  22  *    routines in this file used to be inline!
  23  */
  24
  25 #include <linux/module.h>
  26
  27 #include <linux/kernel.h>
  28 #include <linux/delay.h>
  29 #include <linux/types.h>
  30 #include <linux/string.h>
  31 #include <linux/malloc.h>
  32 #include <linux/blk.h>
  33 #include <linux/proc_fs.h>
  34 #include <linux/stat.h>
  35
  36 #include "scsi.h"
  37 #include "hosts.h"
  38 #include "NCR53C9x.h"
  39 #include "fastlane.h"
  40
  41 #include <linux/zorro.h>
  42 #include <asm/irq.h>
  43 #include <asm/io.h>
  44 #include <asm/amigaints.h>
  45 #include <asm/amigahw.h>
  46
  47 #include <asm/pgtable.h>
  48
  49 /* Such day has just come... */
  50 #if 0
  51 /* Let this defined unless you really need to enable DMA IRQ one day */
  52 #define NODMAIRQ
  53 #endif
  54
  55 static int  dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
  56 static int  dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
  57 static inline void dma_clear(struct NCR_ESP *esp);
  58 static void dma_dump_state(struct NCR_ESP *esp);
  59 static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
  60 static void dma_init_write(struct NCR_ESP *esp, __u32 vaddr, int length);
  61 static void dma_ints_off(struct NCR_ESP *esp);
  62 static void dma_ints_on(struct NCR_ESP *esp);
  63 static int  dma_irq_p(struct NCR_ESP *esp);
  64 static void dma_irq_exit(struct NCR_ESP *esp);
  65 static void dma_led_off(struct NCR_ESP *esp);
  66 static void dma_led_on(struct NCR_ESP *esp);
  67 static int  dma_ports_p(struct NCR_ESP *esp);
  68 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
  69
  70 static unsigned char ctrl_data = 0;     /* Keep backup of the stuff written
  71                                  * to ctrl_reg. Always write a copy
  72                                  * to this register when writing to
  73                                  * the hardware register!
  74                                  */
  75
  76 volatile unsigned char cmd_buffer[16];
  77                                 /* This is where all commands are put
  78                                  * before they are transfered to the ESP chip
  79                                  * via PIO.
  80                                  */
  81
  82 /***************************************************************** Detection */
  83 int __init fastlane_esp_detect(Scsi_Host_Template *tpnt)
  84 {
  85         struct NCR_ESP *esp;
  86         const struct ConfigDev *esp_dev;
  87         unsigned int key;
  88         unsigned long address;
  89
  90         if ((key = zorro_find(ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060, 0, 0))){
  91
  92                 esp_dev = zorro_get_board(key);
  93
  94                 /* Check if this is really a fastlane controller. The problem
  95                  * is that also the cyberstorm and blizzard controllers use
  96                  * this ID value. Fortunately only Fastlane maps in Z3 space
  97                  */
  98                 if((unsigned long)esp_dev->cd_BoardAddr < 0x1000000)
  99                         return 0;
 100
 101                 esp = esp_allocate(tpnt, (void *) esp_dev);
 102
 103                 /* Do command transfer with programmed I/O */
 104                 esp->do_pio_cmds = 1;
 105
 106                 /* Required functions */
 107                 esp->dma_bytes_sent = &dma_bytes_sent;
 108                 esp->dma_can_transfer = &dma_can_transfer;
 109                 esp->dma_dump_state = &dma_dump_state;
 110                 esp->dma_init_read = &dma_init_read;
 111                 esp->dma_init_write = &dma_init_write;
 112                 esp->dma_ints_off = &dma_ints_off;
 113                 esp->dma_ints_on = &dma_ints_on;
 114                 esp->dma_irq_p = &dma_irq_p;
 115                 esp->dma_ports_p = &dma_ports_p;
 116                 esp->dma_setup = &dma_setup;
 117
 118                 /* Optional functions */
 119                 esp->dma_barrier = 0;
 120                 esp->dma_drain = 0;
 121                 esp->dma_invalidate = 0;
 122                 esp->dma_irq_entry = 0;
 123                 esp->dma_irq_exit = &dma_irq_exit;
 124                 esp->dma_led_on = &dma_led_on;
 125                 esp->dma_led_off = &dma_led_off;
 126                 esp->dma_poll = 0;
 127                 esp->dma_reset = 0;
 128
 129                 /* Initialize the portBits (enable IRQs) */
 130                 ctrl_data = (FASTLANE_DMA_FCODE |
 131 #ifndef NODMAIRQ
 132                              FASTLANE_DMA_EDI |
 133 #endif
 134                              FASTLANE_DMA_ESI);
 135
 136
 137                 /* SCSI chip clock */
 138                 esp->cfreq = 40000000;
 139
 140
 141                 /* Map the physical address space into virtual kernel space */
 142                 address = (unsigned long)
 143                         ioremap_nocache((unsigned long)esp_dev->cd_BoardAddr,
 144                                         esp_dev->cd_BoardSize);
 145
 146                 if(!address){
 147                         printk("Could not remap Fastlane controller memory!");
 148                         scsi_unregister (esp->ehost);
 149                         return 0;
 150                 }
 151
 152
 153                 /* The DMA registers on the Fastlane are mapped
 154                  * relative to the device (i.e. in the same Zorro
 155                  * I/O block).
 156                  */
 157                 esp->dregs = (void *)(address + FASTLANE_DMA_ADDR);
 158
 159                 /* ESP register base */
 160                 esp->eregs = (struct ESP_regs *)(address + FASTLANE_ESP_ADDR);
 161
 162                 /* Board base */
 163                 esp->edev = (void *) address;
 164
 165                 /* Set the command buffer */
 166                 esp->esp_command = (volatile unsigned char*) cmd_buffer;
 167                 esp->esp_command_dvma = virt_to_bus(cmd_buffer);
 168
 169                 esp->irq = IRQ_AMIGA_PORTS;
 170                 esp->slot = key;
 171                 request_irq(IRQ_AMIGA_PORTS, esp_intr, SA_SHIRQ,
 172                             "Fastlane SCSI", esp_intr);
 173
 174                 /* Controller ID */
 175                 esp->scsi_id = 7;
 176
 177                 /* We don't have a differential SCSI-bus. */
 178                 esp->diff = 0;
 179
 180                 dma_clear(esp);
 181                 esp_initialize(esp);
 182
 183                 zorro_config_board(key, 0);
 184
 185                 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
 186                 esps_running = esps_in_use;
 187                 return esps_in_use;
 188         }
 189         return 0;
 190 }
 191
 192
 193 /************************************************************* DMA Functions */
 194 static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
 195 {
 196         /* Since the Fastlane DMA is fully dedicated to the ESP chip,
 197          * the number of bytes sent (to the ESP chip) equals the number
 198          * of bytes in the FIFO - there is no buffering in the DMA controller.
 199          * XXXX Do I read this right? It is from host to ESP, right?
 200          */
 201         return fifo_count;
 202 }
 203
 204 static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
 205 {
 206         unsigned long sz = sp->SCp.this_residual;
 207         if(sz > 0xfffc)
 208                 sz = 0xfffc;
 209         return sz;
 210 }
 211
 212 static void dma_dump_state(struct NCR_ESP *esp)
 213 {
 214         ESPLOG(("esp%d: dma -- cond_reg<%02x>\n",
 215                 esp->esp_id, ((struct fastlane_dma_registers *)
 216                               (esp->dregs))->cond_reg));
 217         ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
 218                 custom.intreqr, custom.intenar));
 219 }
 220
 221 static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
 222 {
 223         struct fastlane_dma_registers *dregs =
 224                 (struct fastlane_dma_registers *) (esp->dregs);
 225         unsigned long *t;
 226
 227         cache_clear(addr, length);
 228
 229         dma_clear(esp);
 230
 231         t = (unsigned long *)((addr & 0x00ffffff) + esp->edev);
 232
 233         dregs->clear_strobe = 0;
 234         *t = addr;
 235
 236         ctrl_data = (ctrl_data & FASTLANE_DMA_MASK) | FASTLANE_DMA_ENABLE;
 237         dregs->ctrl_reg = ctrl_data;
 238 }
 239
 240 static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
 241 {
 242         struct fastlane_dma_registers *dregs =
 243                 (struct fastlane_dma_registers *) (esp->dregs);
 244         unsigned long *t;
 245
 246         cache_push(addr, length);
 247
 248         dma_clear(esp);
 249
 250         t = (unsigned long *)((addr & 0x00ffffff) + (esp->edev));
 251
 252         dregs->clear_strobe = 0;
 253         *t = addr;
 254
 255         ctrl_data = ((ctrl_data & FASTLANE_DMA_MASK) |
 256                      FASTLANE_DMA_ENABLE |
 257                      FASTLANE_DMA_WRITE);
 258         dregs->ctrl_reg = ctrl_data;
 259 }
 260
 261 static inline void dma_clear(struct NCR_ESP *esp)
 262 {
 263         struct fastlane_dma_registers *dregs =
 264                 (struct fastlane_dma_registers *) (esp->dregs);
 265         unsigned long *t;
 266
 267         ctrl_data = (ctrl_data & FASTLANE_DMA_MASK);
 268         dregs->ctrl_reg = ctrl_data;
 269
 270         t = (unsigned long *)(esp->edev);
 271
 272         dregs->clear_strobe = 0;
 273         *t = 0 ;
 274 }
 275
 276
 277 static void dma_ints_off(struct NCR_ESP *esp)
 278 {
 279         disable_irq(esp->irq);
 280 }
 281
 282 static void dma_ints_on(struct NCR_ESP *esp)
 283 {
 284         enable_irq(esp->irq);
 285 }
 286
 287 static void dma_irq_exit(struct NCR_ESP *esp)
 288 {
 289         struct fastlane_dma_registers *dregs =
 290                 (struct fastlane_dma_registers *) (esp->dregs);
 291
 292         dregs->ctrl_reg = ctrl_data & ~(FASTLANE_DMA_EDI|FASTLANE_DMA_ESI);
 293 #ifdef __mc68000__
 294         nop();
 295 #endif
 296         dregs->ctrl_reg = ctrl_data;
 297 }
 298
 299 static int dma_irq_p(struct NCR_ESP *esp)
 300 {
 301         struct fastlane_dma_registers *dregs =
 302                 (struct fastlane_dma_registers *) (esp->dregs);
 303         unsigned char dma_status;
 304
 305         dma_status = dregs->cond_reg;
 306
 307         if(dma_status & FASTLANE_DMA_IACT)
 308                 return 0;       /* not our IRQ */
 309
 310         /* Return non-zero if ESP requested IRQ */
 311         return (
 312 #ifndef NODMAIRQ
 313            (dma_status & FASTLANE_DMA_CREQ) &&
 314 #endif
 315            (!(dma_status & FASTLANE_DMA_MINT)) &&
 316            (esp_read(((struct ESP_regs *) (esp->eregs))->esp_status) & ESP_STAT_INTR));
 317 }
 318
 319 static void dma_led_off(struct NCR_ESP *esp)
 320 {
 321         ctrl_data &= ~FASTLANE_DMA_LED;
 322         ((struct fastlane_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
 323 }
 324
 325 static void dma_led_on(struct NCR_ESP *esp)
 326 {
 327         ctrl_data |= FASTLANE_DMA_LED;
 328         ((struct fastlane_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
 329 }
 330
 331 static int dma_ports_p(struct NCR_ESP *esp)
 332 {
 333         return ((custom.intenar) & IF_PORTS);
 334 }
 335
 336 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
 337 {
 338         /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
 339          * so when (write) is true, it actually means READ!
 340          */
 341         if(write){
 342                 dma_init_read(esp, addr, count);
 343         } else {
 344                 dma_init_write(esp, addr, count);
 345         }
 346 }
 347
 348 #ifdef MODULE
 349
 350 #define HOSTS_C
 351
 352 #include "fastlane.h"
 353
 354 Scsi_Host_Template driver_template = SCSI_FASTLANE;
 355
 356 #include "scsi_module.c"
 357
 358 #endif
 359
 360 int fastlane_esp_release(struct Scsi_Host *instance)
 361 {
 362 #ifdef MODULE
 363         unsigned int key;
 364
 365         key = ((struct NCR_ESP *)instance->hostdata)->slot;
 366         esp_deallocate((struct NCR_ESP *)instance->hostdata);
 367         esp_release();
 368         zorro_unconfig_board(key, 0);
 369         free_irq(IRQ_AMIGA_PORTS, esp_intr);
 370 #endif
 371         return 1;
 372 }