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Import 2.3.18pre1
[davej-history.git] / drivers / scsi / eata_dma.c
blob6c55199503a3bdd4c0497ec5aadaa5c026d2a008
1 /************************************************************
2 * *
3 * Linux EATA SCSI driver *
4 * *
5 * based on the CAM document CAM/89-004 rev. 2.0c, *
6 * DPT's driver kit, some internal documents and source, *
7 * and several other Linux scsi drivers and kernel docs. *
8 * *
9 * The driver currently: *
10 * -supports all ISA based EATA-DMA boards *
11 * like PM2011, PM2021, PM2041, PM3021 *
12 * -supports all EISA based EATA-DMA boards *
13 * like PM2012B, PM2022, PM2122, PM2322, PM2042, *
14 * PM3122, PM3222, PM3332 *
15 * -supports all PCI based EATA-DMA boards *
16 * like PM2024, PM2124, PM2044, PM2144, PM3224, *
17 * PM3334 *
18 * -supports the Wide, Ultra Wide and Differential *
19 * versions of the boards *
20 * -supports multiple HBAs with & without IRQ sharing *
21 * -supports all SCSI channels on multi channel boards *
22 * -supports ix86 and MIPS, untested on ALPHA *
23 * -needs identical IDs on all channels of a HBA *
24 * -can be loaded as module *
25 * -displays statistical and hardware information *
26 * in /proc/scsi/eata_dma *
27 * -provides rudimentary latency measurement *
28 * possibilities via /proc/scsi/eata_dma/<hostnum> *
29 * *
30 * (c)1993-96 Michael Neuffer *
31 * mike@i-Connect.Net *
32 * neuffer@mail.uni-mainz.de *
33 * *
34 * This program is free software; you can redistribute it *
35 * and/or modify it under the terms of the GNU General *
36 * Public License as published by the Free Software *
37 * Foundation; either version 2 of the License, or *
38 * (at your option) any later version. *
39 * *
40 * This program is distributed in the hope that it will be *
41 * useful, but WITHOUT ANY WARRANTY; without even the *
42 * implied warranty of MERCHANTABILITY or FITNESS FOR A *
43 * PARTICULAR PURPOSE. See the GNU General Public License *
44 * for more details. *
45 * *
46 * You should have received a copy of the GNU General *
47 * Public License along with this kernel; if not, write to *
48 * the Free Software Foundation, Inc., 675 Mass Ave, *
49 * Cambridge, MA 02139, USA. *
50 * *
51 * I have to thank DPT for their excellent support. I took *
52 * me almost a year and a stopover at their HQ, on my first *
53 * trip to the USA, to get it, but since then they've been *
54 * very helpful and tried to give me all the infos and *
55 * support I need. *
56 * *
57 * Thanks also to Simon Shapiro, Greg Hosler and Mike *
58 * Jagdis who did a lot of testing and found quite a number *
59 * of bugs during the development. *
60 ************************************************************
61 * last change: 96/10/21 OS: Linux 2.0.23 *
62 ************************************************************/
63
64 /* Look in eata_dma.h for configuration and revision information */
65
66 #include <linux/module.h>
67 #include <linux/kernel.h>
68 #include <linux/sched.h>
69 #include <linux/string.h>
70 #include <linux/ioport.h>
71 #include <linux/malloc.h>
72 #include <linux/in.h>
73 #include <linux/pci.h>
74 #include <linux/proc_fs.h>
75 #include <linux/delay.h>
76 #include <asm/byteorder.h>
77 #include <asm/types.h>
78 #include <asm/io.h>
79 #include <asm/dma.h>
80 #include <asm/pgtable.h>
81 #ifdef __mips__
82 #include <asm/cachectl.h>
83 #include <linux/spinlock.h>
84 #endif
85 #include <linux/blk.h>
86 #include "scsi.h"
87 #include "sd.h"
88 #include "hosts.h"
89 #include "eata_dma.h"
90 #include "eata_dma_proc.h"
91
92 #include <linux/stat.h>
93 #include <linux/config.h> /* for CONFIG_PCI */
94
95 struct proc_dir_entry proc_scsi_eata_dma = {
96 PROC_SCSI_EATA, 8, "eata_dma",
97 S_IFDIR | S_IRUGO | S_IXUGO, 2
98 };
99
100 static u32 ISAbases[] =
101 {0x1F0, 0x170, 0x330, 0x230};
102 static unchar EISAbases[] =
103 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
104 static uint registered_HBAs = 0;
105 static struct Scsi_Host *last_HBA = NULL;
106 static struct Scsi_Host *first_HBA = NULL;
107 static unchar reg_IRQ[] =
108 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
109 static unchar reg_IRQL[] =
110 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
111 static struct eata_sp *status = 0; /* Statuspacket array */
112 static void *dma_scratch = 0;
113
114 static struct eata_register *fake_int_base;
115 static int fake_int_result;
116 static int fake_int_happened;
117
118 static ulong int_counter = 0;
119 static ulong queue_counter = 0;
120
121 void eata_scsi_done (Scsi_Cmnd * scmd)
122 {
123 scmd->request.rq_status = RQ_SCSI_DONE;
124
125 if (scmd->request.sem != NULL)
126 up(scmd->request.sem);
127
128 return;
129 }
130
131 void eata_fake_int_handler(s32 irq, void *dev_id, struct pt_regs * regs)
132 {
133 fake_int_result = inb((ulong)fake_int_base + HA_RSTATUS);
134 fake_int_happened = TRUE;
135 DBG(DBG_INTR3, printk("eata_fake_int_handler called irq%d base %p"
136 " res %#x\n", irq, fake_int_base, fake_int_result));
137 return;
138 }
139
140 #include "eata_dma_proc.c"
141
142 #ifdef MODULE
143 int eata_release(struct Scsi_Host *sh)
144 {
145 uint i;
146 if (sh->irq && reg_IRQ[sh->irq] == 1) free_irq(sh->irq, NULL);
147 else reg_IRQ[sh->irq]--;
148
149 scsi_init_free((void *)status, 512);
150 scsi_init_free((void *)dma_scratch - 4, 1024);
151 for (i = 0; i < sh->can_queue; i++){ /* Free all SG arrays */
152 if(SD(sh)->ccb[i].sg_list != NULL)
153 scsi_init_free((void *) SD(sh)->ccb[i].sg_list,
154 sh->sg_tablesize * sizeof(struct eata_sg_list));
155 }
156
157 if (SD(sh)->channel == 0) {
158 if (sh->dma_channel != BUSMASTER) free_dma(sh->dma_channel);
159 if (sh->io_port && sh->n_io_port)
160 release_region(sh->io_port, sh->n_io_port);
161 }
162 return(TRUE);
163 }
164 #endif
165
166
167 inline void eata_latency_in(struct eata_ccb *cp, hostdata *hd)
168 {
169 uint time;
170 time = jiffies - cp->timestamp;
171 if(hd->all_lat[1] > time)
172 hd->all_lat[1] = time;
173 if(hd->all_lat[2] < time)
174 hd->all_lat[2] = time;
175 hd->all_lat[3] += time;
176 hd->all_lat[0]++;
177 if((cp->rw_latency) == WRITE) { /* was WRITE */
178 if(hd->writes_lat[cp->sizeindex][1] > time)
179 hd->writes_lat[cp->sizeindex][1] = time;
180 if(hd->writes_lat[cp->sizeindex][2] < time)
181 hd->writes_lat[cp->sizeindex][2] = time;
182 hd->writes_lat[cp->sizeindex][3] += time;
183 hd->writes_lat[cp->sizeindex][0]++;
184 } else if((cp->rw_latency) == READ) {
185 if(hd->reads_lat[cp->sizeindex][1] > time)
186 hd->reads_lat[cp->sizeindex][1] = time;
187 if(hd->reads_lat[cp->sizeindex][2] < time)
188 hd->reads_lat[cp->sizeindex][2] = time;
189 hd->reads_lat[cp->sizeindex][3] += time;
190 hd->reads_lat[cp->sizeindex][0]++;
191 }
192 }
193
194 inline void eata_latency_out(struct eata_ccb *cp, Scsi_Cmnd *cmd)
195 {
196 int x, z;
197 short *sho;
198 long *lon;
199 x = 0; /* just to keep GCC quiet */
200 cp->timestamp = jiffies; /* For latency measurements */
201 switch(cmd->cmnd[0]) {
202 case WRITE_6:
203 x = cmd->cmnd[4]/2;
204 cp->rw_latency = WRITE;
205 break;
206 case READ_6:
207 x = cmd->cmnd[4]/2;
208 cp->rw_latency = READ;
209 break;
210 case WRITE_10:
211 sho = (short *) &cmd->cmnd[7];
212 x = ntohs(*sho)/2;
213 cp->rw_latency = WRITE;
214 break;
215 case READ_10:
216 sho = (short *) &cmd->cmnd[7];
217 x = ntohs(*sho)/2;
218 cp->rw_latency = READ;
219 break;
220 case WRITE_12:
221 lon = (long *) &cmd->cmnd[6];
222 x = ntohl(*lon)/2;
223 cp->rw_latency = WRITE;
224 break;
225 case READ_12:
226 lon = (long *) &cmd->cmnd[6];
227 x = ntohl(*lon)/2;
228 cp->rw_latency = READ;
229 break;
230 default:
231 cp->rw_latency = OTHER;
232 break;
233 }
234 if (cmd->cmnd[0] == WRITE_6 || cmd->cmnd[0] == WRITE_10 ||
235 cmd->cmnd[0] == WRITE_12 || cmd->cmnd[0] == READ_6 ||
236 cmd->cmnd[0] == READ_10 || cmd->cmnd[0] == READ_12) {
237 for(z = 0; (x > (1 << z)) && (z <= 11); z++)
238 /* nothing */;
239 cp->sizeindex = z;
240 }
241 }
242
243 void eata_int_handler(int, void *, struct pt_regs *);
244
245 void do_eata_int_handler(int irq, void *dev_id, struct pt_regs * regs)
246 {
247 unsigned long flags;
248
249 spin_lock_irqsave(&io_request_lock, flags);
250 eata_int_handler(irq, dev_id, regs);
251 spin_unlock_irqrestore(&io_request_lock, flags);
252 }
253
254 void eata_int_handler(int irq, void *dev_id, struct pt_regs * regs)
255 {
256 uint i, result = 0;
257 uint hba_stat, scsi_stat, eata_stat;
258 Scsi_Cmnd *cmd;
259 struct eata_ccb *ccb;
260 struct eata_sp *sp;
261 uint base;
262 uint x;
263 struct Scsi_Host *sh;
264
265 for (x = 1, sh = first_HBA; x <= registered_HBAs; x++, sh = SD(sh)->next) {
266 if (sh->irq != irq)
267 continue;
268
269 while(inb((uint)sh->base + HA_RAUXSTAT) & HA_AIRQ) {
270
271 int_counter++;
272
273 sp = &SD(sh)->sp;
274 #ifdef __mips__
275 sys_cacheflush(sp, sizeof(struct eata_sp), 2);
276 #endif
277 ccb = sp->ccb;
278
279 if(ccb == NULL) {
280 eata_stat = inb((uint)sh->base + HA_RSTATUS);
281 printk("eata_dma: int_handler, Spurious IRQ %d "
282 "received. CCB pointer not set.\n", irq);
283 break;
284 }
285
286 cmd = ccb->cmd;
287 base = (uint) cmd->host->base;
288 hba_stat = sp->hba_stat;
289
290 scsi_stat = (sp->scsi_stat >> 1) & 0x1f;
291
292 if (sp->EOC == FALSE) {
293 eata_stat = inb(base + HA_RSTATUS);
294 printk(KERN_WARNING "eata_dma: int_handler, board: %x cmd %lx "
295 "returned unfinished.\n"
296 "EATA: %x HBA: %x SCSI: %x spadr %lx spadrirq %lx, "
297 "irq%d\n", base, (long)ccb, eata_stat, hba_stat,
298 scsi_stat,(long)&status, (long)&status[irq], irq);
299 cmd->result = DID_ERROR << 16;
300 ccb->status = FREE;
301 cmd->scsi_done(cmd);
302 break;
303 }
304
305 sp->EOC = FALSE; /* Clean out this flag */
306
307 if (ccb->status == LOCKED || ccb->status == RESET) {
308 printk("eata_dma: int_handler, reseted command pid %ld returned"
309 "\n", cmd->pid);
310 DBG(DBG_INTR && DBG_DELAY, DELAY(1));
311 }
312
313 eata_stat = inb(base + HA_RSTATUS);
314 DBG(DBG_INTR, printk("IRQ %d received, base %#.4x, pid %ld, "
315 "target: %x, lun: %x, ea_s: %#.2x, hba_s: "
316 "%#.2x \n", irq, base, cmd->pid, cmd->target,
317 cmd->lun, eata_stat, hba_stat));
318
319 switch (hba_stat) {
320 case HA_NO_ERROR: /* NO Error */
321 if(HD(cmd)->do_latency == TRUE && ccb->timestamp)
322 eata_latency_in(ccb, HD(cmd));
323 result = DID_OK << 16;
324 break;
325 case HA_ERR_SEL_TO: /* Selection Timeout */
326 case HA_ERR_CMD_TO: /* Command Timeout */
327 result = DID_TIME_OUT << 16;
328 break;
329 case HA_BUS_RESET: /* SCSI Bus Reset Received */
330 result = DID_RESET << 16;
331 DBG(DBG_STATUS, printk(KERN_WARNING "scsi%d: BUS RESET "
332 "received on cmd %ld\n",
333 HD(cmd)->HBA_number, cmd->pid));
334 break;
335 case HA_INIT_POWERUP: /* Initial Controller Power-up */
336 if (cmd->device->type != TYPE_TAPE)
337 result = DID_BUS_BUSY << 16;
338 else
339 result = DID_ERROR << 16;
340
341 for (i = 0; i < MAXTARGET; i++)
342 DBG(DBG_STATUS, printk(KERN_DEBUG "scsi%d: cmd pid %ld "
343 "returned with INIT_POWERUP\n",
344 HD(cmd)->HBA_number, cmd->pid));
345 break;
346 case HA_CP_ABORT_NA:
347 case HA_CP_ABORTED:
348 result = DID_ABORT << 16;
349 DBG(DBG_STATUS, printk(KERN_WARNING "scsi%d: aborted cmd "
350 "returned\n", HD(cmd)->HBA_number));
351 break;
352 case HA_CP_RESET_NA:
353 case HA_CP_RESET:
354 HD(cmd)->resetlevel[cmd->channel] = 0;
355 result = DID_RESET << 16;
356 DBG(DBG_STATUS, printk(KERN_WARNING "scsi%d: reseted cmd "
357 "pid %ldreturned\n",
358 HD(cmd)->HBA_number, cmd->pid));
359 case HA_SCSI_HUNG: /* SCSI Hung */
360 printk(KERN_ERR "scsi%d: SCSI hung\n", HD(cmd)->HBA_number);
361 result = DID_ERROR << 16;
362 break;
363 case HA_RSENSE_FAIL: /* Auto Request-Sense Failed */
364 DBG(DBG_STATUS, printk(KERN_ERR "scsi%d: Auto Request Sense "
365 "Failed\n", HD(cmd)->HBA_number));
366 result = DID_ERROR << 16;
367 break;
368 case HA_UNX_BUSPHASE: /* Unexpected Bus Phase */
369 case HA_UNX_BUS_FREE: /* Unexpected Bus Free */
370 case HA_BUS_PARITY: /* Bus Parity Error */
371 case HA_UNX_MSGRJCT: /* Unexpected Message Reject */
372 case HA_RESET_STUCK: /* SCSI Bus Reset Stuck */
373 case HA_PARITY_ERR: /* Controller Ram Parity */
374 default:
375 result = DID_ERROR << 16;
376 break;
377 }
378 cmd->result = result | (scsi_stat << 1);
379
380 #if DBG_INTR2
381 if (scsi_stat || result || hba_stat || eata_stat != 0x50
382 || cmd->scsi_done == NULL || cmd->device->id == 7)
383 printk("HBA: %d, channel %d, id: %d, lun %d, pid %ld:\n"
384 "eata_stat %#x, hba_stat %#.2x, scsi_stat %#.2x, "
385 "sense_key: %#x, result: %#.8x\n", x,
386 cmd->device->channel, cmd->device->id, cmd->device->lun,
387 cmd->pid, eata_stat, hba_stat, scsi_stat,
388 cmd->sense_buffer[2] & 0xf, cmd->result);
389 DBG(DBG_INTR&&DBG_DELAY,DELAY(1));
390 #endif
391
392 ccb->status = FREE; /* now we can release the slot */
393 cmd->scsi_done(cmd);
394 }
395 }
396
397 return;
398 }
399
400 inline int eata_send_command(u32 addr, u32 base, u8 command)
401 {
402 long loop = R_LIMIT;
403
404 while (inb(base + HA_RAUXSTAT) & HA_ABUSY)
405 if (--loop == 0)
406 return(FALSE);
407
408 if(addr != (u32) NULL)
409 addr = virt_to_bus((void *)addr);
410
411 /*
412 * This is overkill.....but the MIPSen seem to need this
413 * and it will be optimized away for i86 and ALPHA machines.
414 */
415 flush_cache_all();
416
417 /* And now the address in nice little byte chunks */
418 #ifdef __LITTLE_ENDIAN
419 outb(addr, base + HA_WDMAADDR);
420 outb(addr >> 8, base + HA_WDMAADDR + 1);
421 outb(addr >> 16, base + HA_WDMAADDR + 2);
422 outb(addr >> 24, base + HA_WDMAADDR + 3);
423 #else
424 outb(addr >> 24, base + HA_WDMAADDR);
425 outb(addr >> 16, base + HA_WDMAADDR + 1);
426 outb(addr >> 8, base + HA_WDMAADDR + 2);
427 outb(addr, base + HA_WDMAADDR + 3);
428 #endif
429 outb(command, base + HA_WCOMMAND);
430 return(TRUE);
431 }
432
433 inline int eata_send_immediate(u32 base, u32 addr, u8 ifc, u8 code, u8 code2)
434 {
435 if(addr != (u32) NULL)
436 addr = virt_to_bus((void *)addr);
437
438 /*
439 * This is overkill.....but the MIPSen seem to need this
440 * and it will be optimized away for i86 and ALPHA machines.
441 */
442 flush_cache_all();
443
444 outb(0x0, base + HA_WDMAADDR - 1);
445 if(addr){
446 #ifdef __LITTLE_ENDIAN
447 outb(addr, base + HA_WDMAADDR);
448 outb(addr >> 8, base + HA_WDMAADDR + 1);
449 outb(addr >> 16, base + HA_WDMAADDR + 2);
450 outb(addr >> 24, base + HA_WDMAADDR + 3);
451 #else
452 outb(addr >> 24, base + HA_WDMAADDR);
453 outb(addr >> 16, base + HA_WDMAADDR + 1);
454 outb(addr >> 8, base + HA_WDMAADDR + 2);
455 outb(addr, base + HA_WDMAADDR + 3);
456 #endif
457 } else {
458 outb(0x0, base + HA_WDMAADDR);
459 outb(0x0, base + HA_WDMAADDR + 1);
460 outb(code2, base + HA_WCODE2);
461 outb(code, base + HA_WCODE);
462 }
463
464 outb(ifc, base + HA_WIFC);
465 outb(EATA_CMD_IMMEDIATE, base + HA_WCOMMAND);
466 return(TRUE);
467 }
468
469 int eata_queue(Scsi_Cmnd * cmd, void (* done) (Scsi_Cmnd *))
470 {
471 unsigned int i, x, y;
472 ulong flags;
473 hostdata *hd;
474 struct Scsi_Host *sh;
475 struct eata_ccb *ccb;
476 struct scatterlist *sl;
477
478
479 save_flags(flags);
480 cli();
481
482 #if 0
483 for (x = 1, sh = first_HBA; x <= registered_HBAs; x++, sh = SD(sh)->next) {
484 if(inb((uint)sh->base + HA_RAUXSTAT) & HA_AIRQ) {
485 printk("eata_dma: scsi%d interrupt pending in eata_queue.\n"
486 " Calling interrupt handler.\n", sh->host_no);
487 eata_int_handler(sh->irq, 0, 0);
488 }
489 }
490 #endif
491
492 queue_counter++;
493
494 hd = HD(cmd);
495 sh = cmd->host;
496
497 if (cmd->cmnd[0] == REQUEST_SENSE && cmd->sense_buffer[0] != 0) {
498 DBG(DBG_REQSENSE, printk(KERN_DEBUG "Tried to REQUEST SENSE\n"));
499 cmd->result = DID_OK << 16;
500 done(cmd);
501
502 return(0);
503 }
504
505 /* check for free slot */
506 for (y = hd->last_ccb + 1, x = 0; x < sh->can_queue; x++, y++) {
507 if (y >= sh->can_queue)
508 y = 0;
509 if (hd->ccb[y].status == FREE)
510 break;
511 }
512
513 hd->last_ccb = y;
514
515 if (x >= sh->can_queue) {
516 cmd->result = DID_BUS_BUSY << 16;
517 DBG(DBG_QUEUE && DBG_ABNORM,
518 printk(KERN_CRIT "eata_queue pid %ld, HBA QUEUE FULL..., "
519 "returning DID_BUS_BUSY\n", cmd->pid));
520 done(cmd);
521 restore_flags(flags);
522 return(0);
523 }
524 ccb = &hd->ccb[y];
525
526 memset(ccb, 0, sizeof(struct eata_ccb) - sizeof(struct eata_sg_list *));
527
528 ccb->status = USED; /* claim free slot */
529
530 restore_flags(flags);
531
532 DBG(DBG_QUEUE, printk("eata_queue pid %ld, target: %x, lun: %x, y %d\n",
533 cmd->pid, cmd->target, cmd->lun, y));
534 DBG(DBG_QUEUE && DBG_DELAY, DELAY(1));
535
536 if(hd->do_latency == TRUE)
537 eata_latency_out(ccb, cmd);
538
539 cmd->scsi_done = (void *)done;
540
541 switch (cmd->cmnd[0]) {
542 case CHANGE_DEFINITION: case COMPARE: case COPY:
543 case COPY_VERIFY: case LOG_SELECT: case MODE_SELECT:
544 case MODE_SELECT_10: case SEND_DIAGNOSTIC: case WRITE_BUFFER:
545 case FORMAT_UNIT: case REASSIGN_BLOCKS: case RESERVE:
546 case SEARCH_EQUAL: case SEARCH_HIGH: case SEARCH_LOW:
547 case WRITE_6: case WRITE_10: case WRITE_VERIFY:
548 case UPDATE_BLOCK: case WRITE_LONG: case WRITE_SAME:
549 case SEARCH_HIGH_12: case SEARCH_EQUAL_12: case SEARCH_LOW_12:
550 case WRITE_12: case WRITE_VERIFY_12: case SET_WINDOW:
551 case MEDIUM_SCAN: case SEND_VOLUME_TAG:
552 case 0xea: /* alternate number for WRITE LONG */
553 ccb->DataOut = TRUE; /* Output mode */
554 break;
555 case TEST_UNIT_READY:
556 default:
557 ccb->DataIn = TRUE; /* Input mode */
558 }
559
560 /* FIXME: This will will have to be changed once the midlevel driver
561 * allows different HBA IDs on every channel.
562 */
563 if (cmd->target == sh->this_id)
564 ccb->Interpret = TRUE; /* Interpret command */
565
566 if (cmd->use_sg) {
567 ccb->scatter = TRUE; /* SG mode */
568 if (ccb->sg_list == NULL) {
569 ccb->sg_list = kmalloc(sh->sg_tablesize * sizeof(struct eata_sg_list),
570 GFP_ATOMIC | GFP_DMA);
571 }
572 if (ccb->sg_list == NULL)
573 panic("eata_dma: Run out of DMA memory for SG lists !\n");
574 ccb->cp_dataDMA = htonl(virt_to_bus(ccb->sg_list));
575
576 ccb->cp_datalen = htonl(cmd->use_sg * sizeof(struct eata_sg_list));
577 sl=(struct scatterlist *)cmd->request_buffer;
578 for(i = 0; i < cmd->use_sg; i++, sl++){
579 ccb->sg_list[i].data = htonl(virt_to_bus(sl->address));
580 ccb->sg_list[i].len = htonl((u32) sl->length);
581 }
582 } else {
583 ccb->scatter = FALSE;
584 ccb->cp_datalen = htonl(cmd->request_bufflen);
585 ccb->cp_dataDMA = htonl(virt_to_bus(cmd->request_buffer));
586 }
587
588 ccb->Auto_Req_Sen = TRUE;
589 ccb->cp_reqDMA = htonl(virt_to_bus(cmd->sense_buffer));
590 ccb->reqlen = sizeof(cmd->sense_buffer);
591
592 ccb->cp_id = cmd->target;
593 ccb->cp_channel = cmd->channel;
594 ccb->cp_lun = cmd->lun;
595 ccb->cp_dispri = TRUE;
596 ccb->cp_identify = TRUE;
597 memcpy(ccb->cp_cdb, cmd->cmnd, cmd->cmd_len);
598
599 ccb->cp_statDMA = htonl(virt_to_bus(&(hd->sp)));
600
601 ccb->cp_viraddr = ccb; /* This will be passed thru, so we don't need to
602 * convert it */
603 ccb->cmd = cmd;
604 cmd->host_scribble = (char *)&hd->ccb[y];
605
606 if(eata_send_command((u32) ccb, (u32) sh->base, EATA_CMD_DMA_SEND_CP) == FALSE) {
607 cmd->result = DID_BUS_BUSY << 16;
608 DBG(DBG_QUEUE && DBG_ABNORM,
609 printk("eata_queue target %d, pid %ld, HBA busy, "
610 "returning DID_BUS_BUSY\n",cmd->target, cmd->pid));
611 ccb->status = FREE;
612 done(cmd);
613 return(0);
614 }
615 DBG(DBG_QUEUE, printk("Queued base %#.4x pid: %ld target: %x lun: %x "
616 "slot %d irq %d\n", (s32)sh->base, cmd->pid,
617 cmd->target, cmd->lun, y, sh->irq));
618 DBG(DBG_QUEUE && DBG_DELAY, DELAY(1));
619
620 return(0);
621 }
622
623
624 int eata_abort(Scsi_Cmnd * cmd)
625 {
626 ulong loop = HZ / 2;
627 ulong flags;
628 int x;
629 struct Scsi_Host *sh;
630
631 save_flags(flags);
632 cli();
633
634 DBG(DBG_ABNORM, printk("eata_abort called pid: %ld target: %x lun: %x"
635 " reason %x\n", cmd->pid, cmd->target, cmd->lun,
636 cmd->abort_reason));
637 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
638
639 /* Some interrupt controllers seem to loose interrupts */
640 for (x = 1, sh = first_HBA; x <= registered_HBAs; x++, sh = SD(sh)->next) {
641 if(inb((uint)sh->base + HA_RAUXSTAT) & HA_AIRQ) {
642 printk("eata_dma: scsi%d interrupt pending in eata_abort.\n"
643 " Calling interrupt handler.\n", sh->host_no);
644 eata_int_handler(sh->irq, 0, 0);
645 }
646 }
647
648 while (inb((u32)(cmd->host->base) + HA_RAUXSTAT) & HA_ABUSY) {
649 if (--loop == 0) {
650 printk("eata_dma: abort, timeout error.\n");
651 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
652 restore_flags(flags);
653 return (SCSI_ABORT_ERROR);
654 }
655 }
656 if (CD(cmd)->status == RESET) {
657 printk("eata_dma: abort, command reset error.\n");
658 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
659 restore_flags(flags);
660 return (SCSI_ABORT_ERROR);
661 }
662 if (CD(cmd)->status == LOCKED) {
663 DBG(DBG_ABNORM, printk("eata_dma: abort, queue slot locked.\n"));
664 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
665 restore_flags(flags);
666 return (SCSI_ABORT_NOT_RUNNING);
667 }
668 if (CD(cmd)->status == USED) {
669 DBG(DBG_ABNORM, printk("Returning: SCSI_ABORT_BUSY\n"));
670 restore_flags(flags);
671 return (SCSI_ABORT_BUSY); /* SNOOZE */
672 }
673 if (CD(cmd)->status == FREE) {
674 DBG(DBG_ABNORM, printk("Returning: SCSI_ABORT_NOT_RUNNING\n"));
675 restore_flags(flags);
676 return (SCSI_ABORT_NOT_RUNNING);
677 }
678 restore_flags(flags);
679 panic("eata_dma: abort: invalid slot status\n");
680 }
681
682 int eata_reset(Scsi_Cmnd * cmd, unsigned int resetflags)
683 {
684 uint x;
685 ulong loop = loops_per_sec / 3;
686 ulong flags;
687 unchar success = FALSE;
688 Scsi_Cmnd *sp;
689 struct Scsi_Host *sh;
690
691 save_flags(flags);
692 cli();
693
694 DBG(DBG_ABNORM, printk("eata_reset called pid:%ld target: %x lun: %x"
695 " reason %x\n", cmd->pid, cmd->target, cmd->lun,
696 cmd->abort_reason));
697
698 for (x = 1, sh = first_HBA; x <= registered_HBAs; x++, sh = SD(sh)->next) {
699 if(inb((uint)sh->base + HA_RAUXSTAT) & HA_AIRQ) {
700 printk("eata_dma: scsi%d interrupt pending in eata_reset.\n"
701 " Calling interrupt handler.\n", sh->host_no);
702 eata_int_handler(sh->irq, 0, 0);
703 }
704 }
705
706 if (HD(cmd)->state == RESET) {
707 printk("eata_reset: exit, already in reset.\n");
708 restore_flags(flags);
709 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
710 return (SCSI_RESET_ERROR);
711 }
712
713 while (inb((u32)(cmd->host->base) + HA_RAUXSTAT) & HA_ABUSY)
714 if (--loop == 0) {
715 printk("eata_reset: exit, timeout error.\n");
716 restore_flags(flags);
717 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
718 return (SCSI_RESET_ERROR);
719 }
720
721 for (x = 0; x < cmd->host->can_queue; x++) {
722 if (HD(cmd)->ccb[x].status == FREE)
723 continue;
724
725 if (HD(cmd)->ccb[x].status == LOCKED) {
726 HD(cmd)->ccb[x].status = FREE;
727 printk("eata_reset: locked slot %d forced free.\n", x);
728 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
729 continue;
730 }
731
732
733 sp = HD(cmd)->ccb[x].cmd;
734 HD(cmd)->ccb[x].status = RESET;
735
736 if (sp == NULL)
737 panic("eata_reset: slot %d, sp==NULL.\n", x);
738
739 printk("eata_reset: slot %d in reset, pid %ld.\n", x, sp->pid);
740
741 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
742
743 if (sp == cmd)
744 success = TRUE;
745 }
746
747 /* hard reset the HBA */
748 inb((u32) (cmd->host->base) + HA_RSTATUS); /* This might cause trouble */
749 eata_send_command(0, (u32) cmd->host->base, EATA_CMD_RESET);
750
751 HD(cmd)->state = RESET;
752
753 DBG(DBG_ABNORM, printk("eata_reset: board reset done, enabling "
754 "interrupts.\n"));
755
756 DELAY(2); /* In theorie we should get interrupts and set free all
757 * used queueslots */
758
759 DBG(DBG_ABNORM, printk("eata_reset: interrupts disabled again.\n"));
760 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
761
762 for (x = 0; x < cmd->host->can_queue; x++) {
763
764 /* Skip slots already set free by interrupt and those that
765 * are still LOCKED from the last reset */
766 if (HD(cmd)->ccb[x].status != RESET)
767 continue;
768
769 sp = HD(cmd)->ccb[x].cmd;
770 sp->result = DID_RESET << 16;
771
772 /* This mailbox is still waiting for its interrupt */
773 HD(cmd)->ccb[x].status = LOCKED;
774
775 printk("eata_reset: slot %d locked, DID_RESET, pid %ld done.\n",
776 x, sp->pid);
777 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
778
779 sp->scsi_done(sp);
780 }
781
782 HD(cmd)->state = FALSE;
783 restore_flags(flags);
784
785 if (success) {
786 DBG(DBG_ABNORM, printk("eata_reset: exit, pending.\n"));
787 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
788 return (SCSI_RESET_PENDING);
789 } else {
790 DBG(DBG_ABNORM, printk("eata_reset: exit, wakeup.\n"));
791 DBG(DBG_ABNORM && DBG_DELAY, DELAY(1));
792 return (SCSI_RESET_PUNT);
793 }
794 }
795
796 /* Here we try to determine the optimum queue depth for
797 * each attached device.
798 *
799 * At the moment the algorithm is rather simple
800 */
801 static void eata_select_queue_depths(struct Scsi_Host *host,
802 Scsi_Device *devicelist)
803 {
804 Scsi_Device *device;
805 int devcount = 0;
806 int factor = 0;
807
808 #if CRIPPLE_QUEUE
809 for(device = devicelist; device != NULL; device = device->next) {
810 if(device->host == host)
811 device->queue_depth = 2;
812 }
813 #else
814 /* First we do a sample run go find out what we have */
815 for(device = devicelist; device != NULL; device = device->next) {
816 if (device->host == host) {
817 devcount++;
818 switch(device->type) {
819 case TYPE_DISK:
820 case TYPE_MOD:
821 factor += TYPE_DISK_QUEUE;
822 break;
823 case TYPE_TAPE:
824 factor += TYPE_TAPE_QUEUE;
825 break;
826 case TYPE_WORM:
827 case TYPE_ROM:
828 factor += TYPE_ROM_QUEUE;
829 break;
830 case TYPE_PROCESSOR:
831 case TYPE_SCANNER:
832 default:
833 factor += TYPE_OTHER_QUEUE;
834 break;
835 }
836 }
837 }
838
839 DBG(DBG_REGISTER, printk(KERN_DEBUG "scsi%d: needed queueslots %d\n",
840 host->host_no, factor));
841
842 if(factor == 0) /* We don't want to get a DIV BY ZERO error */
843 factor = 1;
844
845 factor = (SD(host)->queuesize * 10) / factor;
846
847 DBG(DBG_REGISTER, printk(KERN_DEBUG "scsi%d: using factor %dE-1\n",
848 host->host_no, factor));
849
850 /* Now that have the factor we can set the individual queuesizes */
851 for(device = devicelist; device != NULL; device = device->next) {
852 if(device->host == host) {
853 if(SD(device->host)->bustype != IS_ISA){
854 switch(device->type) {
855 case TYPE_DISK:
856 case TYPE_MOD:
857 device->queue_depth = (TYPE_DISK_QUEUE * factor) / 10;
858 break;
859 case TYPE_TAPE:
860 device->queue_depth = (TYPE_TAPE_QUEUE * factor) / 10;
861 break;
862 case TYPE_WORM:
863 case TYPE_ROM:
864 device->queue_depth = (TYPE_ROM_QUEUE * factor) / 10;
865 break;
866 case TYPE_PROCESSOR:
867 case TYPE_SCANNER:
868 default:
869 device->queue_depth = (TYPE_OTHER_QUEUE * factor) / 10;
870 break;
871 }
872 } else /* ISA forces us to limit the queue depth because of the
873 * bounce buffer memory overhead. I know this is cruel */
874 device->queue_depth = 2;
875
876 /*
877 * It showed that we need to set an upper limit of commands
878 * we can allow to queue for a single device on the bus.
879 * If we get above that limit, the broken midlevel SCSI code
880 * will produce bogus timeouts and aborts en masse. :-(
881 */
882 if(device->queue_depth > UPPER_DEVICE_QUEUE_LIMIT)
883 device->queue_depth = UPPER_DEVICE_QUEUE_LIMIT;
884 if(device->queue_depth == 0)
885 device->queue_depth = 1;
886
887 printk(KERN_INFO "scsi%d: queue depth for target %d on channel %d "
888 "set to %d\n", host->host_no, device->id, device->channel,
889 device->queue_depth);
890 }
891 }
892 #endif
893 }
894
895 #if CHECK_BLINK
896 int check_blink_state(long base)
897 {
898 ushort loops = 10;
899 u32 blinkindicator;
900 u32 state = 0x12345678;
901 u32 oldstate = 0;
902
903 blinkindicator = htonl(0x54504442);
904 while ((loops--) && (state != oldstate)) {
905 oldstate = state;
906 state = inl((uint) base + 1);
907 }
908
909 DBG(DBG_BLINK, printk("Did Blink check. Status: %d\n",
910 (state == oldstate) && (state == blinkindicator)));
911
912 if ((state == oldstate) && (state == blinkindicator))
913 return(TRUE);
914 else
915 return (FALSE);
916 }
917 #endif
918
919 char * get_board_data(u32 base, u32 irq, u32 id)
920 {
921 struct eata_ccb *cp;
922 struct eata_sp *sp;
923 static char *buff;
924 ulong i;
925
926 cp = (struct eata_ccb *) scsi_init_malloc(sizeof(struct eata_ccb),
927 GFP_ATOMIC | GFP_DMA);
928 sp = (struct eata_sp *) scsi_init_malloc(sizeof(struct eata_sp),
929 GFP_ATOMIC | GFP_DMA);
930
931 buff = dma_scratch;
932
933 memset(cp, 0, sizeof(struct eata_ccb));
934 memset(sp, 0, sizeof(struct eata_sp));
935 memset(buff, 0, 256);
936
937 cp->DataIn = TRUE;
938 cp->Interpret = TRUE; /* Interpret command */
939 cp->cp_dispri = TRUE;
940 cp->cp_identify = TRUE;
941
942 cp->cp_datalen = htonl(56);
943 cp->cp_dataDMA = htonl(virt_to_bus(buff));
944 cp->cp_statDMA = htonl(virt_to_bus(sp));
945 cp->cp_viraddr = cp;
946
947 cp->cp_id = id;
948 cp->cp_lun = 0;
949
950 cp->cp_cdb[0] = INQUIRY;
951 cp->cp_cdb[1] = 0;
952 cp->cp_cdb[2] = 0;
953 cp->cp_cdb[3] = 0;
954 cp->cp_cdb[4] = 56;
955 cp->cp_cdb[5] = 0;
956
957 fake_int_base = (struct eata_register *) base;
958 fake_int_result = FALSE;
959 fake_int_happened = FALSE;
960
961 eata_send_command((u32) cp, (u32) base, EATA_CMD_DMA_SEND_CP);
962
963 i = jiffies + (3 * HZ);
964 while (fake_int_happened == FALSE && time_before_eq(jiffies, i))
965 barrier();
966
967 DBG(DBG_INTR3, printk(KERN_DEBUG "fake_int_result: %#x hbastat %#x "
968 "scsistat %#x, buff %p sp %p\n",
969 fake_int_result, (u32) (sp->hba_stat /*& 0x7f*/),
970 (u32) sp->scsi_stat, buff, sp));
971
972 scsi_init_free((void *)cp, sizeof(struct eata_ccb));
973 scsi_init_free((void *)sp, sizeof(struct eata_sp));
974
975 if ((fake_int_result & HA_SERROR) || time_after(jiffies, i)){
976 printk(KERN_WARNING "eata_dma: trying to reset HBA at %x to clear "
977 "possible blink state\n", base);
978 /* hard reset the HBA */
979 inb((u32) (base) + HA_RSTATUS);
980 eata_send_command(0, base, EATA_CMD_RESET);
981 DELAY(1);
982 return (NULL);
983 } else
984 return (buff);
985 }
986
987
988 int get_conf_PIO(u32 base, struct get_conf *buf)
989 {
990 ulong loop = R_LIMIT;
991 u16 *p;
992
993 if(check_region(base, 9))
994 return (FALSE);
995
996 memset(buf, 0, sizeof(struct get_conf));
997
998 while (inb(base + HA_RSTATUS) & HA_SBUSY)
999 if (--loop == 0)
1000 return (FALSE);
1001
1002 fake_int_base = (struct eata_register *) base;
1003 fake_int_result = FALSE;
1004 fake_int_happened = FALSE;
1005
1006 DBG(DBG_PIO && DBG_PROBE,
1007 printk("Issuing PIO READ CONFIG to HBA at %#x\n", base));
1008 eata_send_command(0, base, EATA_CMD_PIO_READ_CONFIG);
1009
1010 loop = R_LIMIT;
1011 for (p = (u16 *) buf;
1012 (long)p <= ((long)buf + (sizeof(struct get_conf) / 2)); p++) {
1013 while (!(inb(base + HA_RSTATUS) & HA_SDRQ))
1014 if (--loop == 0)
1015 return (FALSE);
1016
1017 loop = R_LIMIT;
1018 *p = inw(base + HA_RDATA);
1019 }
1020
1021 if (!(inb(base + HA_RSTATUS) & HA_SERROR)) { /* Error ? */
1022 if (htonl(EATA_SIGNATURE) == buf->signature) {
1023 DBG(DBG_PIO&&DBG_PROBE, printk("EATA Controller found at %x "
1024 "EATA Level: %x\n", (uint) base,
1025 (uint) (buf->version)));
1026
1027 while (inb(base + HA_RSTATUS) & HA_SDRQ)
1028 inw(base + HA_RDATA);
1029 return (TRUE);
1030 }
1031 } else {
1032 DBG(DBG_PROBE, printk("eata_dma: get_conf_PIO, error during transfer "
1033 "for HBA at %lx\n", (long)base));
1034 }
1035 return (FALSE);
1036 }
1037
1038
1039 void print_config(struct get_conf *gc)
1040 {
1041 printk("LEN: %d ver:%d OCS:%d TAR:%d TRNXFR:%d MORES:%d DMAS:%d\n",
1042 (u32) ntohl(gc->len), gc->version,
1043 gc->OCS_enabled, gc->TAR_support, gc->TRNXFR, gc->MORE_support,
1044 gc->DMA_support);
1045 printk("DMAV:%d HAAV:%d SCSIID0:%d ID1:%d ID2:%d QUEUE:%d SG:%d SEC:%d\n",
1046 gc->DMA_valid, gc->HAA_valid, gc->scsi_id[3], gc->scsi_id[2],
1047 gc->scsi_id[1], ntohs(gc->queuesiz), ntohs(gc->SGsiz), gc->SECOND);
1048 printk("IRQ:%d IRQT:%d DMAC:%d FORCADR:%d SG_64K:%d SG_UAE:%d MID:%d "
1049 "MCH:%d MLUN:%d\n",
1050 gc->IRQ, gc->IRQ_TR, (8 - gc->DMA_channel) & 7, gc->FORCADR,
1051 gc->SG_64K, gc->SG_UAE, gc->MAX_ID, gc->MAX_CHAN, gc->MAX_LUN);
1052 printk("RIDQ:%d PCI:%d EISA:%d\n",
1053 gc->ID_qest, gc->is_PCI, gc->is_EISA);
1054 DBG(DPT_DEBUG, DELAY(14));
1055 }
1056
1057 short register_HBA(u32 base, struct get_conf *gc, Scsi_Host_Template * tpnt,
1058 u8 bustype)
1059 {
1060 ulong size = 0;
1061 unchar dma_channel = 0;
1062 char *buff = 0;
1063 unchar bugs = 0;
1064 struct Scsi_Host *sh;
1065 hostdata *hd;
1066 int x;
1067
1068
1069 DBG(DBG_REGISTER, print_config(gc));
1070
1071 if (gc->DMA_support == FALSE) {
1072 printk("The EATA HBA at %#.4x does not support DMA.\n"
1073 "Please use the EATA-PIO driver.\n", base);
1074 return (FALSE);
1075 }
1076 if(gc->HAA_valid == FALSE || ntohl(gc->len) < 0x22)
1077 gc->MAX_CHAN = 0;
1078
1079 if (reg_IRQ[gc->IRQ] == FALSE) { /* Interrupt already registered ? */
1080 if (!request_irq(gc->IRQ, (void *) eata_fake_int_handler, SA_INTERRUPT,
1081 "eata_dma", NULL)){
1082 reg_IRQ[gc->IRQ]++;
1083 if (!gc->IRQ_TR)
1084 reg_IRQL[gc->IRQ] = TRUE; /* IRQ is edge triggered */
1085 } else {
1086 printk("Couldn't allocate IRQ %d, Sorry.", gc->IRQ);
1087 return (FALSE);
1088 }
1089 } else { /* More than one HBA on this IRQ */
1090 if (reg_IRQL[gc->IRQ] == TRUE) {
1091 printk("Can't support more than one HBA on this IRQ,\n"
1092 " if the IRQ is edge triggered. Sorry.\n");
1093 return (FALSE);
1094 } else
1095 reg_IRQ[gc->IRQ]++;
1096 }
1097
1098
1099 /* If DMA is supported but DMA_valid isn't set to indicate that
1100 * the channel number is given we must have pre 2.0 firmware (1.7?)
1101 * which leaves us to guess since the "newer ones" also don't set the
1102 * DMA_valid bit.
1103 */
1104 if (gc->DMA_support && !gc->DMA_valid && gc->DMA_channel) {
1105 printk(KERN_WARNING "eata_dma: If you are using a pre 2.0 firmware "
1106 "please update it !\n"
1107 " You can get new firmware releases from ftp.dpt.com\n");
1108 gc->DMA_channel = (base == 0x1f0 ? 3 /* DMA=5 */ : 2 /* DMA=6 */);
1109 gc->DMA_valid = TRUE;
1110 }
1111
1112 /* if gc->DMA_valid it must be an ISA HBA and we have to register it */
1113 dma_channel = BUSMASTER;
1114 if (gc->DMA_valid) {
1115 if (request_dma(dma_channel = (8 - gc->DMA_channel) & 7, "eata_dma")) {
1116 printk(KERN_WARNING "Unable to allocate DMA channel %d for ISA HBA"
1117 " at %#.4x.\n", dma_channel, base);
1118 reg_IRQ[gc->IRQ]--;
1119 if (reg_IRQ[gc->IRQ] == 0)
1120 free_irq(gc->IRQ, NULL);
1121 if (gc->IRQ_TR == FALSE)
1122 reg_IRQL[gc->IRQ] = FALSE;
1123 return (FALSE);
1124 }
1125 }
1126
1127 if (dma_channel != BUSMASTER) {
1128 disable_dma(dma_channel);
1129 clear_dma_ff(dma_channel);
1130 set_dma_mode(dma_channel, DMA_MODE_CASCADE);
1131 enable_dma(dma_channel);
1132 }
1133
1134 if (bustype != IS_EISA && bustype != IS_ISA)
1135 buff = get_board_data(base, gc->IRQ, gc->scsi_id[3]);
1136
1137 if (buff == NULL) {
1138 if (bustype == IS_EISA || bustype == IS_ISA) {
1139 bugs = bugs || BROKEN_INQUIRY;
1140 } else {
1141 if (gc->DMA_support == FALSE)
1142 printk(KERN_WARNING "HBA at %#.4x doesn't support DMA. "
1143 "Sorry\n", base);
1144 else
1145 printk(KERN_WARNING "HBA at %#.4x does not react on INQUIRY. "
1146 "Sorry.\n", base);
1147 if (gc->DMA_valid)
1148 free_dma(dma_channel);
1149 reg_IRQ[gc->IRQ]--;
1150 if (reg_IRQ[gc->IRQ] == 0)
1151 free_irq(gc->IRQ, NULL);
1152 if (gc->IRQ_TR == FALSE)
1153 reg_IRQL[gc->IRQ] = FALSE;
1154 return (FALSE);
1155 }
1156 }
1157
1158 if (gc->DMA_support == FALSE && buff != NULL)
1159 printk(KERN_WARNING "HBA %.12sat %#.4x doesn't set the DMA_support "
1160 "flag correctly.\n", &buff[16], base);
1161
1162 request_region(base, 9, "eata_dma"); /* We already checked the
1163 * availability, so this
1164 * should not fail.
1165 */
1166
1167 if(ntohs(gc->queuesiz) == 0) {
1168 gc->queuesiz = ntohs(64);
1169 printk(KERN_WARNING "Warning: Queue size has to be corrected. Assuming"
1170 " 64 queueslots\n"
1171 " This might be a PM2012B with a defective Firmware\n"
1172 " Contact DPT support@dpt.com for an upgrade\n");
1173 }
1174
1175 size = sizeof(hostdata) + ((sizeof(struct eata_ccb) + sizeof(long))
1176 * ntohs(gc->queuesiz));
1177
1178 DBG(DBG_REGISTER, printk("scsi_register size: %ld\n", size));
1179
1180 sh = scsi_register(tpnt, size);
1181
1182 if(sh != NULL) {
1183
1184 hd = SD(sh);
1185
1186 memset(hd->reads, 0, sizeof(u32) * 26);
1187
1188 sh->select_queue_depths = eata_select_queue_depths;
1189
1190 hd->bustype = bustype;
1191
1192 /*
1193 * If we are using a ISA board, we can't use extended SG,
1194 * because we would need excessive amounts of memory for
1195 * bounce buffers.
1196 */
1197 if (gc->SG_64K==TRUE && ntohs(gc->SGsiz)==64 && hd->bustype!=IS_ISA){
1198 sh->sg_tablesize = SG_SIZE_BIG;
1199 } else {
1200 sh->sg_tablesize = ntohs(gc->SGsiz);
1201 if (sh->sg_tablesize > SG_SIZE || sh->sg_tablesize == 0) {
1202 if (sh->sg_tablesize == 0)
1203 printk(KERN_WARNING "Warning: SG size had to be fixed.\n"
1204 "This might be a PM2012 with a defective Firmware"
1205 "\nContact DPT support@dpt.com for an upgrade\n");
1206 sh->sg_tablesize = SG_SIZE;
1207 }
1208 }
1209 hd->sgsize = sh->sg_tablesize;
1210 }
1211
1212 if(sh != NULL) {
1213 sh->can_queue = hd->queuesize = ntohs(gc->queuesiz);
1214 sh->cmd_per_lun = 0;
1215 }
1216
1217 if(sh == NULL) {
1218 DBG(DBG_REGISTER, printk(KERN_NOTICE "eata_dma: couldn't register HBA"
1219 " at%x \n", base));
1220 scsi_unregister(sh);
1221 if (gc->DMA_valid)
1222 free_dma(dma_channel);
1223
1224 reg_IRQ[gc->IRQ]--;
1225 if (reg_IRQ[gc->IRQ] == 0)
1226 free_irq(gc->IRQ, NULL);
1227 if (gc->IRQ_TR == FALSE)
1228 reg_IRQL[gc->IRQ] = FALSE;
1229 return (FALSE);
1230 }
1231
1232
1233 hd->broken_INQUIRY = (bugs & BROKEN_INQUIRY);
1234
1235 if(hd->broken_INQUIRY == TRUE) {
1236 strcpy(hd->vendor, "DPT");
1237 strcpy(hd->name, "??????????");
1238 strcpy(hd->revision, "???.?");
1239 hd->firmware_revision = 0;
1240 } else {
1241 strncpy(hd->vendor, &buff[8], 8);
1242 hd->vendor[8] = 0;
1243 strncpy(hd->name, &buff[16], 17);
1244 hd->name[17] = 0;
1245 hd->revision[0] = buff[32];
1246 hd->revision[1] = buff[33];
1247 hd->revision[2] = buff[34];
1248 hd->revision[3] = '.';
1249 hd->revision[4] = buff[35];
1250 hd->revision[5] = 0;
1251 hd->firmware_revision = (buff[32] << 24) + (buff[33] << 16)
1252 + (buff[34] << 8) + buff[35];
1253 }
1254
1255 if (hd->firmware_revision >= (('0'<<24) + ('7'<<16) + ('G'<< 8) + '0'))
1256 hd->immediate_support = 1;
1257 else
1258 hd->immediate_support = 0;
1259
1260 switch (ntohl(gc->len)) {
1261 case 0x1c:
1262 hd->EATA_revision = 'a';
1263 break;
1264 case 0x1e:
1265 hd->EATA_revision = 'b';
1266 break;
1267 case 0x22:
1268 hd->EATA_revision = 'c';
1269 break;
1270 case 0x24:
1271 hd->EATA_revision = 'z';
1272 default:
1273 hd->EATA_revision = '?';
1274 }
1275
1276
1277 if(ntohl(gc->len) >= 0x22) {
1278 sh->max_id = gc->MAX_ID + 1;
1279 sh->max_lun = gc->MAX_LUN + 1;
1280 } else {
1281 sh->max_id = 8;
1282 sh->max_lun = 8;
1283 }
1284
1285 hd->HBA_number = sh->host_no;
1286 hd->channel = gc->MAX_CHAN;
1287 sh->max_channel = gc->MAX_CHAN;
1288 sh->unique_id = base;
1289 sh->base = (char *) base;
1290 sh->io_port = base;
1291 sh->n_io_port = 9;
1292 sh->irq = gc->IRQ;
1293 sh->dma_channel = dma_channel;
1294
1295 /* FIXME:
1296 * SCSI midlevel code should support different HBA ids on every channel
1297 */
1298 sh->this_id = gc->scsi_id[3];
1299
1300 if (gc->SECOND)
1301 hd->primary = FALSE;
1302 else
1303 hd->primary = TRUE;
1304
1305 sh->wish_block = FALSE;
1306
1307 if (hd->bustype != IS_ISA) {
1308 sh->unchecked_isa_dma = FALSE;
1309 } else {
1310 sh->unchecked_isa_dma = TRUE; /* We're doing ISA DMA */
1311 }
1312
1313 for(x = 0; x <= 11; x++){ /* Initialize min. latency */
1314 hd->writes_lat[x][1] = 0xffffffff;
1315 hd->reads_lat[x][1] = 0xffffffff;
1316 }
1317 hd->all_lat[1] = 0xffffffff;
1318
1319 hd->next = NULL; /* build a linked list of all HBAs */
1320 hd->prev = last_HBA;
1321 if(hd->prev != NULL)
1322 SD(hd->prev)->next = sh;
1323 last_HBA = sh;
1324 if (first_HBA == NULL)
1325 first_HBA = sh;
1326 registered_HBAs++;
1327
1328 return (TRUE);
1329 }
1330
1331
1332
1333 void find_EISA(struct get_conf *buf, Scsi_Host_Template * tpnt)
1334 {
1335 u32 base;
1336 int i;
1337
1338 #if CHECKPAL
1339 u8 pal1, pal2, pal3;
1340 #endif
1341
1342 for (i = 0; i < MAXEISA; i++) {
1343 if (EISAbases[i] == TRUE) { /* Still a possibility ? */
1344
1345 base = 0x1c88 + (i * 0x1000);
1346 #if CHECKPAL
1347 pal1 = inb((u16)base - 8);
1348 pal2 = inb((u16)base - 7);
1349 pal3 = inb((u16)base - 6);
1350
1351 if (((pal1 == DPT_ID1) && (pal2 == DPT_ID2)) ||
1352 ((pal1 == NEC_ID1) && (pal2 == NEC_ID2) && (pal3 == NEC_ID3))||
1353 ((pal1 == ATT_ID1) && (pal2 == ATT_ID2) && (pal3 == ATT_ID3))){
1354 DBG(DBG_PROBE, printk("EISA EATA id tags found: %x %x %x \n",
1355 (int)pal1, (int)pal2, (int)pal3));
1356 #endif
1357 if (get_conf_PIO(base, buf) == TRUE) {
1358 if (buf->IRQ) {
1359 DBG(DBG_EISA, printk("Registering EISA HBA\n"));
1360 register_HBA(base, buf, tpnt, IS_EISA);
1361 } else
1362 printk("eata_dma: No valid IRQ. HBA removed from list\n");
1363 }
1364 #if CHECK_BLINK
1365 else {
1366 if (check_blink_state(base))
1367 printk("HBA is in BLINK state. Consult your HBAs "
1368 "Manual to correct this.\n");
1369 }
1370 #endif
1371 /* Nothing found here so we take it from the list */
1372 EISAbases[i] = 0;
1373 #if CHECKPAL
1374 }
1375 #endif
1376 }
1377 }
1378 return;
1379 }
1380
1381 void find_ISA(struct get_conf *buf, Scsi_Host_Template * tpnt)
1382 {
1383 int i;
1384
1385 for (i = 0; i < MAXISA; i++) {
1386 if (ISAbases[i]) {
1387 if (get_conf_PIO(ISAbases[i],buf) == TRUE){
1388 DBG(DBG_ISA, printk("Registering ISA HBA\n"));
1389 register_HBA(ISAbases[i], buf, tpnt, IS_ISA);
1390 }
1391 #if CHECK_BLINK
1392 else {
1393 if (check_blink_state(ISAbases[i]))
1394 printk("HBA is in BLINK state. Consult your HBAs "
1395 "Manual to correct this.\n");
1396 }
1397 #endif
1398 ISAbases[i] = 0;
1399 }
1400 }
1401 return;
1402 }
1403
1404 void find_PCI(struct get_conf *buf, Scsi_Host_Template * tpnt)
1405 {
1406 #ifndef CONFIG_PCI
1407 printk("eata_dma: kernel PCI support not enabled. Skipping scan for PCI HBAs.\n");
1408 #else
1409 struct pci_dev *dev;
1410 u32 base, x;
1411 u8 pal1, pal2, pal3;
1412
1413 for(dev=NULL; dev = pci_find_device(PCI_VENDOR_ID_DPT, PCI_DEVICE_ID_DPT, dev);) {
1414 DBG(DBG_PROBE && DBG_PCI,
1415 printk("eata_dma: find_PCI, HBA at %s\n", dev->name));
1416 pci_set_master(dev);
1417 base = dev->resource[0].flags;
1418 if (!(base & PCI_BASE_ADDRESS_SPACE_IO)) {
1419 printk("eata_dma: invalid base address of device %s\n", dev->name);
1420 continue;
1421 }
1422 base = dev->resource[0].start;
1423 /* EISA tag there ? */
1424 pal1 = inb(base);
1425 pal2 = inb(base + 1);
1426 pal3 = inb(base + 2);
1427 if (((pal1 == DPT_ID1) && (pal2 == DPT_ID2)) ||
1428 ((pal1 == NEC_ID1) && (pal2 == NEC_ID2) &&
1429 (pal3 == NEC_ID3)) ||
1430 ((pal1 == ATT_ID1) && (pal2 == ATT_ID2) &&
1431 (pal3 == ATT_ID3)))
1432 base += 0x08;
1433 else
1434 base += 0x10; /* Now, THIS is the real address */
1435 if (base != 0x1f8) {
1436 /* We didn't find it in the primary search */
1437 if (get_conf_PIO(base, buf) == TRUE) {
1438 /* OK. We made it till here, so we can go now
1439 * and register it. We only have to check and
1440 * eventually remove it from the EISA and ISA list
1441 */
1442 DBG(DBG_PCI, printk("Registering PCI HBA\n"));
1443 register_HBA(base, buf, tpnt, IS_PCI);
1444
1445 if (base < 0x1000) {
1446 for (x = 0; x < MAXISA; ++x) {
1447 if (ISAbases[x] == base) {
1448 ISAbases[x] = 0;
1449 break;
1450 }
1451 }
1452 } else if ((base & 0x0fff) == 0x0c88)
1453 EISAbases[(base >> 12) & 0x0f] = 0;
1454 }
1455 #if CHECK_BLINK
1456 else if (check_blink_state(base) == TRUE) {
1457 printk("eata_dma: HBA is in BLINK state.\n"
1458 "Consult your HBAs manual to correct this.\n");
1459 }
1460 #endif
1461 }
1462 }
1463 #endif /* #ifndef CONFIG_PCI */
1464 }
1465
1466 int eata_detect(Scsi_Host_Template * tpnt)
1467 {
1468 struct Scsi_Host *HBA_ptr;
1469 struct get_conf gc;
1470 int i;
1471
1472 DBG((DBG_PROBE && DBG_DELAY) || DPT_DEBUG,
1473 printk("Using lots of delays to let you read the debugging output\n"));
1474
1475 tpnt->proc_dir = &proc_scsi_eata_dma;
1476
1477 status = scsi_init_malloc(512, GFP_ATOMIC | GFP_DMA);
1478 dma_scratch = scsi_init_malloc(1024, GFP_ATOMIC | GFP_DMA);
1479
1480 if(status == NULL || dma_scratch == NULL) {
1481 printk("eata_dma: can't allocate enough memory to probe for hosts !\n");
1482 return(0);
1483 }
1484
1485 dma_scratch += 4;
1486
1487 find_PCI(&gc, tpnt);
1488
1489 find_EISA(&gc, tpnt);
1490
1491 find_ISA(&gc, tpnt);
1492
1493 for (i = 0; i <= MAXIRQ; i++) { /* Now that we know what we have, we */
1494 if (reg_IRQ[i] >= 1){ /* exchange the interrupt handler which */
1495 free_irq(i, NULL); /* we used for probing with the real one */
1496 request_irq(i, (void *)(do_eata_int_handler), SA_INTERRUPT|SA_SHIRQ,
1497 "eata_dma", NULL);
1498 }
1499 }
1500
1501 HBA_ptr = first_HBA;
1502
1503 if (registered_HBAs != 0) {
1504 printk("EATA (Extended Attachment) driver version: %d.%d%s"
1505 "\ndeveloped in co-operation with DPT\n"
1506 "(c) 1993-96 Michael Neuffer, mike@i-Connect.Net\n",
1507 VER_MAJOR, VER_MINOR, VER_SUB);
1508 printk("Registered HBAs:");
1509 printk("\nHBA no. Boardtype Revis EATA Bus BaseIO IRQ"
1510 " DMA Ch ID Pr QS S/G IS\n");
1511 for (i = 1; i <= registered_HBAs; i++) {
1512 printk("scsi%-2d: %.12s v%s 2.0%c %s %#.4x %2d",
1513 HBA_ptr->host_no, SD(HBA_ptr)->name, SD(HBA_ptr)->revision,
1514 SD(HBA_ptr)->EATA_revision, (SD(HBA_ptr)->bustype == 'P')?
1515 "PCI ":(SD(HBA_ptr)->bustype == 'E')?"EISA":"ISA ",
1516 (u32) HBA_ptr->base, HBA_ptr->irq);
1517 if(HBA_ptr->dma_channel != BUSMASTER)
1518 printk(" %2x ", HBA_ptr->dma_channel);
1519 else
1520 printk(" %s", "BMST");
1521 printk(" %d %d %c %3d %3d %c\n",
1522 SD(HBA_ptr)->channel+1, HBA_ptr->this_id,
1523 (SD(HBA_ptr)->primary == TRUE)?'Y':'N',
1524 HBA_ptr->can_queue, HBA_ptr->sg_tablesize,
1525 (SD(HBA_ptr)->immediate_support == TRUE)?'Y':'N');
1526 HBA_ptr = SD(HBA_ptr)->next;
1527 }
1528 } else {
1529 scsi_init_free((void *)status, 512);
1530 }
1531
1532 scsi_init_free((void *)dma_scratch - 4, 1024);
1533
1534 DBG(DPT_DEBUG, DELAY(12));
1535
1536 return(registered_HBAs);
1537 }
1538
1539 #ifdef MODULE
1540 /* Eventually this will go into an include file, but this will be later */
1541 Scsi_Host_Template driver_template = EATA_DMA;
1542 #include "scsi_module.c"
1543 #endif
1544
1545 /*
1546 * Overrides for Emacs so that we almost follow Linus's tabbing style.
1547 * Emacs will notice this stuff at the end of the file and automatically
1548 * adjust the settings for this buffer only. This must remain at the end
1549 * of the file.
1550 * ---------------------------------------------------------------------------
1551 * Local variables:
1552 * c-indent-level: 4
1553 * c-brace-imaginary-offset: 0
1554 * c-brace-offset: -4
1555 * c-argdecl-indent: 4
1556 * c-label-offset: -4
1557 * c-continued-statement-offset: 4
1558 * c-continued-brace-offset: 0
1559 * tab-width: 8
1560 * End:
1561 */
Copy of Dave Jones history.git as used by http://archive.org/details/git-history-of-linux