4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
18 #include <asm/cache.h>
22 #define DEBUG_CONFIG 0
24 # define DBGC(args) printk args
30 pci_claim_resource(struct pci_dev
*dev
, int resource
)
32 struct resource
*res
= &dev
->resource
[resource
];
33 struct resource
*root
= pci_find_parent_resource(dev
, res
);
38 /* If `dev' is on a secondary pci bus, `root' may not be
39 at the origin. In that case, adjust the resource into
41 res
->start
+= root
->start
;
42 res
->end
+= root
->start
;
44 err
= request_resource(root
, res
);
47 printk(KERN_ERR
"PCI: Address space collision on region %d "
48 "of device %s\n", resource
, dev
->name
);
55 pdev_assign_unassigned_resources(struct pci_dev
*dev
, u32 min_io
, u32 min_mem
)
61 DBGC(("PCI assign unassigned: (%s)\n", dev
->name
));
63 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
65 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
66 struct resource
*root
, *res
;
67 unsigned long size
, min
;
69 res
= &dev
->resource
[i
];
71 if (res
->flags
& IORESOURCE_IO
)
72 cmd
|= PCI_COMMAND_IO
;
73 else if (res
->flags
& IORESOURCE_MEM
)
74 cmd
|= PCI_COMMAND_MEMORY
;
76 /* If it is already assigned or the resource does
77 not exist, there is nothing to do. */
78 if (res
->parent
!= NULL
|| res
->flags
== 0)
81 /* Determine the root we allocate from. */
82 root
= pci_find_parent_resource(dev
, res
);
86 min
= (res
->flags
& IORESOURCE_IO
? min_io
: min_mem
);
88 size
= res
->end
- res
->start
+ 1;
90 DBGC((" for root[%lx:%lx] min[%lx] size[%lx]\n",
91 root
->start
, root
->end
, min
, size
));
93 if (allocate_resource(root
, res
, size
, min
, -1, size
) < 0) {
95 "PCI: Failed to allocate resource %d for %s\n",
100 DBGC((" got res[%lx:%lx] for resource %d\n",
101 res
->start
, res
->end
, i
));
103 /* Update PCI config space. */
104 pcibios_update_resource(dev
, root
, res
, i
);
107 /* Special case, disable the ROM. Several devices act funny
108 (ie. do not respond to memory space writes) when it is left
109 enabled. A good example are QlogicISP adapters. */
111 pci_read_config_dword(dev
, PCI_ROM_ADDRESS
, ®
);
112 reg
&= ~PCI_ROM_ADDRESS_ENABLE
;
113 pci_write_config_dword(dev
, PCI_ROM_ADDRESS
, reg
);
115 /* All of these (may) have I/O scattered all around and may not
116 use I/O base address registers at all. So we just have to
117 always enable IO to these devices. */
118 if ((dev
->class >> 8) == PCI_CLASS_NOT_DEFINED
119 || (dev
->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA
120 || (dev
->class >> 8) == PCI_CLASS_STORAGE_IDE
121 || (dev
->class >> 16) == PCI_BASE_CLASS_DISPLAY
) {
122 cmd
|= PCI_COMMAND_IO
;
125 /* ??? Always turn on bus mastering. If the device doesn't support
126 it, the bit will go into the bucket. */
127 cmd
|= PCI_COMMAND_MASTER
;
129 /* Enable the appropriate bits in the PCI command register. */
130 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
132 DBGC((" cmd reg 0x%x\n", cmd
));
134 /* If this is a PCI bridge, set the cache line correctly. */
135 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
136 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
,
137 (L1_CACHE_BYTES
/ sizeof(u32
)));
142 pci_assign_unassigned_resources(u32 min_io
, u32 min_mem
)
145 for (dev
= pci_devices
; dev
; dev
= dev
->next
)
146 pdev_assign_unassigned_resources(dev
, min_io
, min_mem
);
149 struct pbus_set_ranges_data
152 unsigned int io_start
, io_end
;
153 unsigned int mem_start
, mem_end
;
156 #define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1))
157 #define ROUND_DOWN(x, a) ((x) & ~((a) - 1))
160 pbus_set_ranges(struct pci_bus
*bus
, struct pbus_set_ranges_data
*outer
)
162 struct pbus_set_ranges_data inner
;
163 struct pci_bus
*child
;
167 inner
.mem_start
= inner
.io_start
= ~0;
168 inner
.mem_end
= inner
.io_end
= 0;
170 /* Collect information about how our direct children are layed out. */
171 for (dev
= bus
->devices
; dev
; dev
= dev
->sibling
) {
173 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
174 struct resource
*res
= &dev
->resource
[i
];
175 if (res
->flags
& IORESOURCE_IO
) {
176 if (res
->start
< inner
.io_start
)
177 inner
.io_start
= res
->start
;
178 if (res
->end
> inner
.io_end
)
179 inner
.io_end
= res
->end
;
180 } else if (res
->flags
& IORESOURCE_MEM
) {
181 if (res
->start
< inner
.mem_start
)
182 inner
.mem_start
= res
->start
;
183 if (res
->end
> inner
.mem_end
)
184 inner
.mem_end
= res
->end
;
187 if ((dev
->class >> 8) == PCI_CLASS_DISPLAY_VGA
)
191 /* And for all of the sub-busses. */
192 for (child
= bus
->children
; child
; child
= child
->next
)
193 pbus_set_ranges(child
, &inner
);
195 /* Align the values. */
196 inner
.io_start
= ROUND_DOWN(inner
.io_start
, 4*1024);
197 inner
.io_end
= ROUND_UP(inner
.io_end
, 4*1024);
199 inner
.mem_start
= ROUND_DOWN(inner
.mem_start
, 1*1024*1024);
200 inner
.mem_end
= ROUND_UP(inner
.mem_end
, 1*1024*1024);
202 /* Configure the bridge, if possible. */
204 struct pci_dev
*bridge
= bus
->self
;
207 /* Set up the top and bottom of the PCI I/O segment
209 pci_read_config_dword(bridge
, PCI_IO_BASE
, &l
);
211 l
|= (inner
.io_start
>> 8) & 0x00f0;
212 l
|= (inner
.io_end
- 1) & 0xf000;
213 pci_write_config_dword(bridge
, PCI_IO_BASE
, l
);
216 * Clear out the upper 16 bits of IO base/limit.
217 * Clear out the upper 32 bits of PREF base/limit.
219 pci_write_config_dword(bridge
, PCI_IO_BASE_UPPER16
, 0);
220 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, 0);
221 pci_write_config_dword(bridge
, PCI_PREF_LIMIT_UPPER32
, 0);
223 /* Set up the top and bottom of the PCI Memory segment
225 l
= (inner
.mem_start
& 0xfff00000) >> 16;
226 l
|= (inner
.mem_end
- 1) & 0xfff00000;
227 pci_write_config_dword(bridge
, PCI_MEMORY_BASE
, l
);
230 * Turn off downstream PF memory address range, unless
231 * there is a VGA behind this bridge, in which case, we
232 * enable the PREFETCH range to include BIOS ROM at C0000.
234 * NOTE: this is a bit of a hack, done with PREFETCH for
235 * simplicity, rather than having to add it into the above
236 * non-PREFETCH range, which could then be bigger than we want.
237 * We might assume that we could relocate the BIOS ROM, but
238 * that would depend on having it found by those who need it
239 * (the DEC BIOS emulator would find it, but I do not know
240 * about the Xservers). So, we do it this way for now... ;-)
242 l
= (inner
.found_vga
) ? 0 : 0x0000ffff;
243 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, l
);
246 * Tell bridge that there is an ISA bus in the system,
247 * and (possibly) a VGA as well.
249 l
= (inner
.found_vga
) ? 0x0c : 0x04;
250 pci_write_config_byte(bridge
, PCI_BRIDGE_CONTROL
, l
);
254 * turn on I/O enable (for downstream I/O),
255 * turn on memory enable (for downstream memory),
256 * turn on master enable (for upstream memory and I/O).
258 pci_write_config_dword(bridge
, PCI_COMMAND
, 0xffff0007);
262 outer
->found_vga
|= inner
.found_vga
;
263 if (inner
.io_start
< outer
->io_start
)
264 outer
->io_start
= inner
.io_start
;
265 if (inner
.io_end
> outer
->io_end
)
266 outer
->io_end
= inner
.io_end
;
267 if (inner
.mem_start
< outer
->mem_start
)
268 outer
->mem_start
= inner
.mem_start
;
269 if (inner
.mem_end
> outer
->mem_end
)
270 outer
->mem_end
= inner
.mem_end
;
275 pci_set_bus_ranges(void)
278 for (bus
= pci_root
; bus
; bus
= bus
->next
)
279 pbus_set_ranges(bus
, NULL
);
283 pdev_fixup_irq(struct pci_dev
*dev
,
284 u8 (*swizzle
)(struct pci_dev
*, u8
*),
285 int (*map_irq
)(struct pci_dev
*, u8
, u8
))
290 /* If this device is not on the primary bus, we need to figure out
291 which interrupt pin it will come in on. We know which slot it
292 will come in on 'cos that slot is where the bridge is. Each
293 time the interrupt line passes through a PCI-PCI bridge we must
294 apply the swizzle function. */
296 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
297 /* Cope with 0 and illegal. */
298 if (pin
== 0 || pin
> 4)
301 /* Follow the chain of bridges, swizzling as we go. */
302 slot
= (*swizzle
)(dev
, &pin
);
304 irq
= (*map_irq
)(dev
, slot
, pin
);
309 DBGC(("PCI fixup irq: (%s) got %d\n", dev
->name
, dev
->irq
));
311 /* Always tell the device, so the driver knows what is
312 the real IRQ to use; the device does not use it. */
313 pcibios_update_irq(dev
, irq
);
317 pci_fixup_irqs(u8 (*swizzle
)(struct pci_dev
*, u8
*),
318 int (*map_irq
)(struct pci_dev
*, u8
, u8
))
321 for (dev
= pci_devices
; dev
; dev
= dev
->next
)
322 pdev_fixup_irq(dev
, swizzle
, map_irq
);