drivers/net/z85230.c

   1 /*
   2  *      This program is free software; you can redistribute it and/or
   3  *      modify it under the terms of the GNU General Public License
   4  *      as published by the Free Software Foundation; either version
   5  *      2 of the License, or (at your option) any later version.
   6  *
   7  *      (c) Copyright 1998 Building Number Three Ltd
   8  *
   9  *      Development of this driver was funded by Equiinet Ltd
  10  *                      http://www.equiinet.com
  11  *
  12  *      ChangeLog:
  13  *
  14  *      Asynchronous mode dropped for 2.2. For 2.3 we will attempt the
  15  *      unification of all the Z85x30 asynchronous drivers for real.
  16  *
  17  *      To Do:
  18  *
  19  *      Finish DMA mode support.
  20  *
  21  *      Performance
  22  *
  23  *      Z85230:
  24  *      Non DMA you want a 486DX50 or better to do 64Kbits. 9600 baud
  25  *      X.25 is not unrealistic on all machines. DMA mode can in theory
  26  *      handle T1/E1 quite nicely. In practice the limit seems to be about
  27  *      512Kbit->1Mbit depending on motherboard.
  28  *
  29  *      Z85C30:
  30  *      64K will take DMA, 9600 baud X.25 should be ok.
  31  *
  32  *      Z8530:
  33  *      Synchronous mode without DMA is unlikely to pass about 2400 baud.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/kernel.h>
  38 #include <linux/mm.h>
  39 #include <linux/net.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/if_arp.h>
  43 #include <linux/delay.h>
  44 #include <linux/ioport.h>
  45 #include <asm/dma.h>
  46 #include <asm/io.h>
  47 #define RT_LOCK
  48 #define RT_UNLOCK
  49 #include <linux/spinlock.h>
  50
  51 #include "z85230.h"
  52 #include "syncppp.h"
  53
  54
  55 static spinlock_t z8530_buffer_lock = SPIN_LOCK_UNLOCKED;
  56
  57 /*
  58  *      Provided port access methods. The Comtrol SV11 requires no delays
  59  *      between accesses and uses PC I/O. Some drivers may need a 5uS delay
  60  */
  61
  62 extern __inline__ int z8530_read_port(int p)
  63 {
  64         u8 r=inb(Z8530_PORT_OF(p));
  65         if(p&Z8530_PORT_SLEEP)  /* gcc should figure this out efficiently ! */
  66                 udelay(5);
  67         return r;
  68 }
  69
  70 extern __inline__ void z8530_write_port(int p, u8 d)
  71 {
  72         outb(d,Z8530_PORT_OF(p));
  73         if(p&Z8530_PORT_SLEEP)
  74                 udelay(5);
  75 }
  76
  77
  78
  79 static void z8530_rx_done(struct z8530_channel *c);
  80 static void z8530_tx_done(struct z8530_channel *c);
  81
  82
  83 /*
  84  *      Port accesses
  85  */
  86
  87 extern inline u8 read_zsreg(struct z8530_channel *c, u8 reg)
  88 {
  89         u8 r;
  90         unsigned long flags;
  91         save_flags(flags);
  92         cli();
  93         if(reg)
  94                 z8530_write_port(c->ctrlio, reg);
  95         r=z8530_read_port(c->ctrlio);
  96         restore_flags(flags);
  97         return r;
  98 }
  99
 100 extern inline u8 read_zsdata(struct z8530_channel *c)
 101 {
 102         u8 r;
 103         r=z8530_read_port(c->dataio);
 104         return r;
 105 }
 106
 107 extern inline void write_zsreg(struct z8530_channel *c, u8 reg, u8 val)
 108 {
 109         unsigned long flags;
 110         save_flags(flags);
 111         cli();
 112         if(reg)
 113                 z8530_write_port(c->ctrlio, reg);
 114         z8530_write_port(c->ctrlio, val);
 115         restore_flags(flags);
 116 }
 117
 118 extern inline void write_zsctrl(struct z8530_channel *c, u8 val)
 119 {
 120         z8530_write_port(c->ctrlio, val);
 121 }
 122
 123 extern inline void write_zsdata(struct z8530_channel *c, u8 val)
 124 {
 125         z8530_write_port(c->dataio, val);
 126 }
 127
 128 /*
 129  *      Register loading parameters for a dead port
 130  */
 131
 132 u8 z8530_dead_port[]=
 133 {
 134         255
 135 };
 136
 137 EXPORT_SYMBOL(z8530_dead_port);
 138
 139 /*
 140  *      Register loading parameters for currently supported circuit types
 141  */
 142
 143
 144 /*
 145  *      Data clocked by telco end. This is the correct data for the UK
 146  *      "kilostream" service, and most other similar services.
 147  */
 148
 149 u8 z8530_hdlc_kilostream[]=
 150 {
 151         4,      SYNC_ENAB|SDLC|X1CLK,
 152         2,      0,      /* No vector */
 153         1,      0,
 154         3,      ENT_HM|RxCRC_ENAB|Rx8,
 155         5,      TxCRC_ENAB|RTS|TxENAB|Tx8|DTR,
 156         9,      0,              /* Disable interrupts */
 157         6,      0xFF,
 158         7,      FLAG,
 159         10,     ABUNDER|NRZ|CRCPS,/*MARKIDLE ??*/
 160         11,     TCTRxCP,
 161         14,     DISDPLL,
 162         15,     DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE,
 163         1,      EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
 164         9,      NV|MIE|NORESET,
 165         255
 166 };
 167
 168 EXPORT_SYMBOL(z8530_hdlc_kilostream);
 169
 170 /*
 171  *      As above but for enhanced chips.
 172  */
 173
 174 u8 z8530_hdlc_kilostream_85230[]=
 175 {
 176         4,      SYNC_ENAB|SDLC|X1CLK,
 177         2,      0,      /* No vector */
 178         1,      0,
 179         3,      ENT_HM|RxCRC_ENAB|Rx8,
 180         5,      TxCRC_ENAB|RTS|TxENAB|Tx8|DTR,
 181         9,      0,              /* Disable interrupts */
 182         6,      0xFF,
 183         7,      FLAG,
 184         10,     ABUNDER|NRZ|CRCPS,      /* MARKIDLE?? */
 185         11,     TCTRxCP,
 186         14,     DISDPLL,
 187         15,     DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE,
 188         1,      EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
 189         9,      NV|MIE|NORESET,
 190         23,     3,              /* Extended mode AUTO TX and EOM*/
 191
 192         255
 193 };
 194
 195 EXPORT_SYMBOL(z8530_hdlc_kilostream_85230);
 196
 197 /*
 198  *      Flush the FIFO
 199  */
 200
 201 static void z8530_flush_fifo(struct z8530_channel *c)
 202 {
 203         read_zsreg(c, R1);
 204         read_zsreg(c, R1);
 205         read_zsreg(c, R1);
 206         read_zsreg(c, R1);
 207         if(c->dev->type==Z85230)
 208         {
 209                 read_zsreg(c, R1);
 210                 read_zsreg(c, R1);
 211                 read_zsreg(c, R1);
 212                 read_zsreg(c, R1);
 213         }
 214 }
 215
 216 /* Sets or clears DTR/RTS on the requested line */
 217
 218 static void z8530_rtsdtr(struct z8530_channel *c, int set)
 219 {
 220         if (set)
 221                 c->regs[5] |= (RTS | DTR);
 222         else
 223                 c->regs[5] &= ~(RTS | DTR);
 224         write_zsreg(c, R5, c->regs[5]);
 225 }
 226
 227 /*
 228  *      Receive handler. This is much like the async one but not quite the
 229  *      same or as complex
 230  *
 231  *      Note: Its intended that this handler can easily be separated from
 232  *      the main code to run realtime. That'll be needed for some machines
 233  *      (eg to ever clock 64kbits on a sparc ;)).
 234  *
 235  *      The RT_LOCK macros don't do anything now. Keep the code covered
 236  *      by them as short as possible in all circumstances - clocks cost
 237  *      baud. The interrupt handler is assumed to be atomic w.r.t. to
 238  *      other code - this is true in the RT case too.
 239  *
 240  *      We only cover the sync cases for this. If you want 2Mbit async
 241  *      do it yourself but consider medical assistance first.
 242  *
 243  *      This non DMA synchronous mode is portable code.
 244  */
 245
 246 static void z8530_rx(struct z8530_channel *c)
 247 {
 248         u8 ch,stat;
 249
 250         while(1)
 251         {
 252                 /* FIFO empty ? */
 253                 if(!(read_zsreg(c, R0)&1))
 254                         break;
 255                 ch=read_zsdata(c);
 256                 stat=read_zsreg(c, R1);
 257
 258                 /*
 259                  *      Overrun ?
 260                  */
 261                 if(c->count < c->max)
 262                 {
 263                         *c->dptr++=ch;
 264                         c->count++;
 265                 }
 266
 267                 if(stat&END_FR)
 268                 {
 269
 270                         /*
 271                          *      Error ?
 272                          */
 273                         if(stat&(Rx_OVR|CRC_ERR))
 274                         {
 275                                 /* Rewind the buffer and return */
 276                                 if(c->skb)
 277                                         c->dptr=c->skb->data;
 278                                 c->count=0;
 279                                 if(stat&Rx_OVR)
 280                                 {
 281                                         printk(KERN_WARNING "%s: overrun\n", c->dev->name);
 282                                         c->rx_overrun++;
 283                                 }
 284                                 if(stat&CRC_ERR)
 285                                 {
 286                                         c->rx_crc_err++;
 287                                         /* printk("crc error\n"); */
 288                                 }
 289                                 /* Shove the frame upstream */
 290                         }
 291                         else
 292                         {
 293                                 z8530_rx_done(c);
 294                                 write_zsctrl(c, RES_Rx_CRC);
 295                         }
 296                 }
 297         }
 298         /*
 299          *      Clear irq
 300          */
 301         write_zsctrl(c, ERR_RES);
 302         write_zsctrl(c, RES_H_IUS);
 303 }
 304
 305
 306 /*
 307  *      Z8530 transmit interrupt handler
 308  */
 309
 310 static void z8530_tx(struct z8530_channel *c)
 311 {
 312         while(c->txcount)
 313         {
 314                 /* FIFO full ? */
 315                 if(!(read_zsreg(c, R0)&4))
 316                         break;
 317                 c->txcount--;
 318                 /*
 319                  *      Shovel out the byte
 320                  */
 321                 write_zsreg(c, R8, *c->tx_ptr++);
 322                 write_zsctrl(c, RES_H_IUS);
 323                 /* We are about to underflow */
 324                 if(c->txcount==0)
 325                 {
 326                         write_zsctrl(c, RES_EOM_L);
 327                         write_zsreg(c, R10, c->regs[10]&~ABUNDER);
 328                 }
 329                 return;
 330         }
 331
 332         /*
 333          *      End of frame TX - fire another one
 334          */
 335
 336         write_zsctrl(c, RES_Tx_P);
 337
 338         z8530_tx_done(c);
 339 /*      write_zsreg(c, R8, *c->tx_ptr++); */
 340         write_zsctrl(c, RES_H_IUS);
 341 }
 342
 343 static void z8530_status(struct z8530_channel *chan)
 344 {
 345         u8 status=read_zsreg(chan, R0);
 346         u8 altered=chan->status^status;
 347
 348         chan->status=status;
 349
 350         if(status&TxEOM)
 351         {
 352 /*              printk("%s: Tx underrun.\n", chan->dev->name); */
 353                 chan->stats.tx_fifo_errors++;
 354                 write_zsctrl(chan, ERR_RES);
 355                 z8530_tx_done(chan);
 356         }
 357
 358         if(altered&DCD)
 359         {
 360                 if(status&DCD)
 361                 {
 362                         printk(KERN_INFO "%s: DCD raised\n", chan->dev->name);
 363                         write_zsreg(chan, R3, chan->regs[3]|RxENABLE);
 364                         if(chan->netdevice)
 365                                 sppp_reopen(chan->netdevice);
 366                 }
 367                 else
 368                 {
 369                         printk(KERN_INFO "%s: DCD lost\n", chan->dev->name);
 370                         write_zsreg(chan, R3, chan->regs[3]&~RxENABLE);
 371                         z8530_flush_fifo(chan);
 372                 }
 373
 374         }
 375         write_zsctrl(chan, RES_EXT_INT);
 376         write_zsctrl(chan, RES_H_IUS);
 377 }
 378
 379 struct z8530_irqhandler z8530_sync=
 380 {
 381         z8530_rx,
 382         z8530_tx,
 383         z8530_status
 384 };
 385
 386 EXPORT_SYMBOL(z8530_sync);
 387
 388 /*
 389  *      Non bus mastering DMA interfaces for the Z8x30 devices. This
 390  *      is really pretty PC specific.
 391  */
 392
 393 static void z8530_dma_rx(struct z8530_channel *chan)
 394 {
 395         if(chan->rxdma_on)
 396         {
 397                 /* Special condition check only */
 398                 u8 status;
 399
 400                 read_zsreg(chan, R7);
 401                 read_zsreg(chan, R6);
 402
 403                 status=read_zsreg(chan, R1);
 404                 if(status&END_FR)
 405                 {
 406                         z8530_rx_done(chan);    /* Fire up the next one */
 407                 }
 408                 write_zsctrl(chan, ERR_RES);
 409                 write_zsctrl(chan, RES_H_IUS);
 410         }
 411         else
 412         {
 413                 /* DMA is off right now, drain the slow way */
 414                 z8530_rx(chan);
 415         }
 416 }
 417
 418 static void z8530_dma_tx(struct z8530_channel *chan)
 419 {
 420         if(!chan->dma_tx)
 421         {
 422                 printk("Hey who turned the DMA off?\n");
 423                 z8530_tx(chan);
 424                 return;
 425         }
 426         /* This shouldnt occur in DMA mode */
 427         printk(KERN_ERR "DMA tx ??\n");
 428         z8530_tx(chan);
 429 }
 430
 431 static void z8530_dma_status(struct z8530_channel *chan)
 432 {
 433         unsigned long flags;
 434         u8 status=read_zsreg(chan, R0);
 435         u8 altered=chan->status^status;
 436
 437         chan->status=status;
 438
 439         if(chan->dma_tx)
 440         {
 441                 if(status&TxEOM)
 442                 {
 443                         flags=claim_dma_lock();
 444                         /* Transmit underrun */
 445                         disable_dma(chan->txdma);
 446                         clear_dma_ff(chan->txdma);
 447                         chan->txdma_on=0;
 448                         release_dma_lock(flags);
 449                         z8530_tx_done(chan);
 450                 }
 451         }
 452         if(altered&DCD)
 453         {
 454                 if(status&DCD)
 455                 {
 456                         printk(KERN_INFO "%s: DCD raised\n", chan->dev->name);
 457                         write_zsreg(chan, R3, chan->regs[3]|RxENABLE);
 458                         if(chan->netdevice)
 459                                 sppp_reopen(chan->netdevice);
 460                 }
 461                 else
 462                 {
 463                         printk(KERN_INFO "%s:DCD lost\n", chan->dev->name);
 464                         write_zsreg(chan, R3, chan->regs[3]&~RxENABLE);
 465                         z8530_flush_fifo(chan);
 466                 }
 467         }
 468         write_zsctrl(chan, RES_EXT_INT);
 469         write_zsctrl(chan, RES_H_IUS);
 470 }
 471
 472 struct z8530_irqhandler z8530_dma_sync=
 473 {
 474         z8530_dma_rx,
 475         z8530_dma_tx,
 476         z8530_dma_status
 477 };
 478
 479 EXPORT_SYMBOL(z8530_dma_sync);
 480
 481 struct z8530_irqhandler z8530_txdma_sync=
 482 {
 483         z8530_rx,
 484         z8530_dma_tx,
 485         z8530_dma_status
 486 };
 487
 488 EXPORT_SYMBOL(z8530_txdma_sync);
 489
 490 /*
 491  *      Interrupt vectors for a Z8530 that is in 'parked' mode.
 492  *      For machines with PCI Z85x30 cards, or level triggered interrupts
 493  *      (eg the MacII) we must clear the interrupt cause or die.
 494  */
 495
 496
 497 static void z8530_rx_clear(struct z8530_channel *c)
 498 {
 499         /*
 500          *      Data and status bytes
 501          */
 502         u8 stat;
 503
 504         read_zsdata(c);
 505         stat=read_zsreg(c, R1);
 506
 507         if(stat&END_FR)
 508                 write_zsctrl(c, RES_Rx_CRC);
 509         /*
 510          *      Clear irq
 511          */
 512         write_zsctrl(c, ERR_RES);
 513         write_zsctrl(c, RES_H_IUS);
 514 }
 515
 516 static void z8530_tx_clear(struct z8530_channel *c)
 517 {
 518         write_zsctrl(c, RES_Tx_P);
 519         write_zsctrl(c, RES_H_IUS);
 520 }
 521
 522 static void z8530_status_clear(struct z8530_channel *chan)
 523 {
 524         u8 status=read_zsreg(chan, R0);
 525         if(status&TxEOM)
 526                 write_zsctrl(chan, ERR_RES);
 527         write_zsctrl(chan, RES_EXT_INT);
 528         write_zsctrl(chan, RES_H_IUS);
 529 }
 530
 531 struct z8530_irqhandler z8530_nop=
 532 {
 533         z8530_rx_clear,
 534         z8530_tx_clear,
 535         z8530_status_clear
 536 };
 537
 538
 539 EXPORT_SYMBOL(z8530_nop);
 540
 541 /*
 542  *      A Z85[2]30 device has stuck its hand in the air for attention
 543  */
 544
 545 void z8530_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 546 {
 547         struct z8530_dev *dev=dev_id;
 548         u8 intr;
 549         static volatile int locker=0;
 550         int work=0;
 551
 552         if(locker)
 553         {
 554                 printk(KERN_ERR "IRQ re-enter\n");
 555                 return;
 556         }
 557         locker=1;
 558
 559         while(++work<5000)
 560         {
 561                 struct z8530_irqhandler *irqs=dev->chanA.irqs;
 562
 563                 intr = read_zsreg(&dev->chanA, R3);
 564                 if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT)))
 565                         break;
 566
 567                 /* This holds the IRQ status. On the 8530 you must read it from chan
 568                    A even though it applies to the whole chip */
 569
 570                 /* Now walk the chip and see what it is wanting - it may be
 571                    an IRQ for someone else remember */
 572
 573                 if(intr & (CHARxIP|CHATxIP|CHAEXT))
 574                 {
 575                         if(intr&CHARxIP)
 576                                 irqs->rx(&dev->chanA);
 577                         if(intr&CHATxIP)
 578                                 irqs->tx(&dev->chanA);
 579                         if(intr&CHAEXT)
 580                                 irqs->status(&dev->chanA);
 581                 }
 582
 583                 irqs=dev->chanB.irqs;
 584
 585                 if(intr & (CHBRxIP|CHBTxIP|CHBEXT))
 586                 {
 587                         if(intr&CHBRxIP)
 588                                 irqs->rx(&dev->chanB);
 589                         if(intr&CHBTxIP)
 590                                 irqs->tx(&dev->chanB);
 591                         if(intr&CHBEXT)
 592                                 irqs->status(&dev->chanB);
 593                 }
 594         }
 595         if(work==5000)
 596                 printk(KERN_ERR "%s: interrupt jammed - abort(0x%X)!\n", dev->name, intr);
 597         /* Ok all done */
 598         locker=0;
 599 }
 600
 601 EXPORT_SYMBOL(z8530_interrupt);
 602
 603 static char reg_init[16]=
 604 {
 605         0,0,0,0,
 606         0,0,0,0,
 607         0,0,0,0,
 608         0x55,0,0,0
 609 };
 610
 611
 612 int z8530_sync_open(struct net_device *dev, struct z8530_channel *c)
 613 {
 614         c->sync = 1;
 615         c->mtu = dev->mtu+64;
 616         c->count = 0;
 617         c->skb = NULL;
 618         c->skb2 = NULL;
 619         c->irqs = &z8530_sync;
 620         /* This loads the double buffer up */
 621         z8530_rx_done(c);       /* Load the frame ring */
 622         z8530_rx_done(c);       /* Load the backup frame */
 623         z8530_rtsdtr(c,1);
 624         c->dma_tx = 0;
 625         c->regs[R1]|=TxINT_ENAB;
 626         write_zsreg(c, R1, c->regs[R1]);
 627         write_zsreg(c, R3, c->regs[R3]|RxENABLE);
 628         return 0;
 629 }
 630
 631
 632 EXPORT_SYMBOL(z8530_sync_open);
 633
 634 int z8530_sync_close(struct net_device *dev, struct z8530_channel *c)
 635 {
 636         u8 chk;
 637         c->irqs = &z8530_nop;
 638         c->max = 0;
 639         c->sync = 0;
 640
 641         chk=read_zsreg(c,R0);
 642         write_zsreg(c, R3, c->regs[R3]);
 643         z8530_rtsdtr(c,0);
 644         return 0;
 645 }
 646
 647 EXPORT_SYMBOL(z8530_sync_close);
 648
 649 int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c)
 650 {
 651         unsigned long flags;
 652
 653         c->sync = 1;
 654         c->mtu = dev->mtu+64;
 655         c->count = 0;
 656         c->skb = NULL;
 657         c->skb2 = NULL;
 658         /*
 659          *      Load the DMA interfaces up
 660          */
 661         c->rxdma_on = 0;
 662         c->txdma_on = 0;
 663
 664         /*
 665          *      Allocate the DMA flip buffers
 666          */
 667
 668         c->rx_buf[0]=kmalloc(c->mtu, GFP_KERNEL|GFP_DMA);
 669         if(c->rx_buf[0]==NULL)
 670                 return -ENOBUFS;
 671         c->rx_buf[1]=kmalloc(c->mtu, GFP_KERNEL|GFP_DMA);
 672         if(c->rx_buf[1]==NULL)
 673         {
 674                 kfree(c->rx_buf[0]);
 675                 c->rx_buf[0]=NULL;
 676                 return -ENOBUFS;
 677         }
 678
 679         c->tx_dma_buf[0]=kmalloc(c->mtu, GFP_KERNEL|GFP_DMA);
 680         if(c->tx_dma_buf[0]==NULL)
 681         {
 682                 kfree(c->rx_buf[0]);
 683                 kfree(c->rx_buf[1]);
 684                 c->rx_buf[0]=NULL;
 685                 return -ENOBUFS;
 686         }
 687         c->tx_dma_buf[1]=kmalloc(c->mtu, GFP_KERNEL|GFP_DMA);
 688         if(c->tx_dma_buf[1]==NULL)
 689         {
 690                 kfree(c->tx_dma_buf[0]);
 691                 kfree(c->rx_buf[0]);
 692                 kfree(c->rx_buf[1]);
 693                 c->rx_buf[0]=NULL;
 694                 c->rx_buf[1]=NULL;
 695                 c->tx_dma_buf[0]=NULL;
 696                 return -ENOBUFS;
 697         }
 698         c->tx_dma_used=0;
 699         c->dma_tx = 1;
 700         c->dma_num=0;
 701         c->dma_ready=1;
 702
 703         /*
 704          *      Enable DMA control mode
 705          */
 706
 707         /*
 708          *      TX DMA via DIR/REQ
 709          */
 710
 711         c->regs[R14]|= DTRREQ;
 712         write_zsreg(c, R14, c->regs[R14]);
 713
 714         c->regs[R1]&= ~TxINT_ENAB;
 715         write_zsreg(c, R1, c->regs[R1]);
 716
 717         /*
 718          *      RX DMA via W/Req
 719          */
 720
 721         c->regs[R1]|= WT_FN_RDYFN;
 722         c->regs[R1]|= WT_RDY_RT;
 723         c->regs[R1]|= INT_ERR_Rx;
 724         c->regs[R1]&= ~TxINT_ENAB;
 725         write_zsreg(c, R1, c->regs[R1]);
 726         c->regs[R1]|= WT_RDY_ENAB;
 727         write_zsreg(c, R1, c->regs[R1]);
 728
 729         /*
 730          *      DMA interrupts
 731          */
 732
 733         /*
 734          *      Set up the DMA configuration
 735          */
 736
 737         flags=claim_dma_lock();
 738
 739         disable_dma(c->rxdma);
 740         clear_dma_ff(c->rxdma);
 741         set_dma_mode(c->rxdma, DMA_MODE_READ|0x10);
 742         set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[0]));
 743         set_dma_count(c->rxdma, c->mtu);
 744         enable_dma(c->rxdma);
 745
 746         disable_dma(c->txdma);
 747         clear_dma_ff(c->txdma);
 748         set_dma_mode(c->txdma, DMA_MODE_WRITE);
 749         disable_dma(c->txdma);
 750
 751         release_dma_lock(flags);
 752
 753         /*
 754          *      Select the DMA interrupt handlers
 755          */
 756
 757         c->rxdma_on = 1;
 758         c->txdma_on = 1;
 759         c->tx_dma_used = 1;
 760
 761         c->irqs = &z8530_dma_sync;
 762         z8530_rtsdtr(c,1);
 763         write_zsreg(c, R3, c->regs[R3]|RxENABLE);
 764         return 0;
 765 }
 766
 767 EXPORT_SYMBOL(z8530_sync_dma_open);
 768
 769 int z8530_sync_dma_close(struct net_device *dev, struct z8530_channel *c)
 770 {
 771         u8 chk;
 772         unsigned long flags;
 773
 774         c->irqs = &z8530_nop;
 775         c->max = 0;
 776         c->sync = 0;
 777
 778         /*
 779          *      Disable the PC DMA channels
 780          */
 781
 782         flags=claim_dma_lock();
 783         disable_dma(c->rxdma);
 784         clear_dma_ff(c->rxdma);
 785
 786         c->rxdma_on = 0;
 787
 788         disable_dma(c->txdma);
 789         clear_dma_ff(c->txdma);
 790         release_dma_lock(flags);
 791
 792         c->txdma_on = 0;
 793         c->tx_dma_used = 0;
 794
 795         /*
 796          *      Disable DMA control mode
 797          */
 798
 799         c->regs[R1]&= ~WT_RDY_ENAB;
 800         write_zsreg(c, R1, c->regs[R1]);
 801         c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx);
 802         c->regs[R1]|= INT_ALL_Rx;
 803         write_zsreg(c, R1, c->regs[R1]);
 804         c->regs[R14]&= ~DTRREQ;
 805         write_zsreg(c, R14, c->regs[R14]);
 806
 807         if(c->rx_buf[0])
 808         {
 809                 kfree(c->rx_buf[0]);
 810                 c->rx_buf[0]=NULL;
 811         }
 812         if(c->rx_buf[1])
 813         {
 814                 kfree(c->rx_buf[1]);
 815                 c->rx_buf[1]=NULL;
 816         }
 817         if(c->tx_dma_buf[0])
 818         {
 819                 kfree(c->tx_dma_buf[0]);
 820                 c->tx_dma_buf[0]=NULL;
 821         }
 822         if(c->tx_dma_buf[1])
 823         {
 824                 kfree(c->tx_dma_buf[1]);
 825                 c->tx_dma_buf[1]=NULL;
 826         }
 827         chk=read_zsreg(c,R0);
 828         write_zsreg(c, R3, c->regs[R3]);
 829         z8530_rtsdtr(c,0);
 830         return 0;
 831 }
 832
 833 EXPORT_SYMBOL(z8530_sync_dma_close);
 834
 835 int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c)
 836 {
 837         unsigned long flags;
 838
 839         printk("Opening sync interface for TX-DMA\n");
 840         c->sync = 1;
 841         c->mtu = dev->mtu+64;
 842         c->count = 0;
 843         c->skb = NULL;
 844         c->skb2 = NULL;
 845
 846         /*
 847          *      Load the PIO receive ring
 848          */
 849
 850         z8530_rx_done(c);
 851         z8530_rx_done(c);
 852
 853         /*
 854          *      Load the DMA interfaces up
 855          */
 856
 857         c->rxdma_on = 0;
 858         c->txdma_on = 0;
 859
 860         c->tx_dma_buf[0]=kmalloc(c->mtu, GFP_KERNEL|GFP_DMA);
 861         if(c->tx_dma_buf[0]==NULL)
 862         {
 863                 kfree(c->rx_buf[0]);
 864                 kfree(c->rx_buf[1]);
 865                 c->rx_buf[0]=NULL;
 866                 return -ENOBUFS;
 867         }
 868         c->tx_dma_buf[1]=kmalloc(c->mtu, GFP_KERNEL|GFP_DMA);
 869         if(c->tx_dma_buf[1]==NULL)
 870         {
 871                 kfree(c->tx_dma_buf[0]);
 872                 kfree(c->rx_buf[0]);
 873                 kfree(c->rx_buf[1]);
 874                 c->rx_buf[0]=NULL;
 875                 c->rx_buf[1]=NULL;
 876                 c->tx_dma_buf[0]=NULL;
 877                 return -ENOBUFS;
 878         }
 879         c->tx_dma_used=0;
 880         c->dma_num=0;
 881         c->dma_ready=1;
 882         c->dma_tx = 1;
 883
 884         /*
 885          *      Enable DMA control mode
 886          */
 887
 888         /*
 889          *      TX DMA via DIR/REQ
 890          */
 891         c->regs[R14]|= DTRREQ;
 892         write_zsreg(c, R14, c->regs[R14]);
 893
 894         c->regs[R1]&= ~TxINT_ENAB;
 895         write_zsreg(c, R1, c->regs[R1]);
 896
 897         /*
 898          *      Set up the DMA configuration
 899          */
 900
 901         flags = claim_dma_lock();
 902
 903         disable_dma(c->txdma);
 904         clear_dma_ff(c->txdma);
 905         set_dma_mode(c->txdma, DMA_MODE_WRITE);
 906         disable_dma(c->txdma);
 907
 908         release_dma_lock(flags);
 909
 910         /*
 911          *      Select the DMA interrupt handlers
 912          */
 913
 914         c->rxdma_on = 0;
 915         c->txdma_on = 1;
 916         c->tx_dma_used = 1;
 917
 918         c->irqs = &z8530_txdma_sync;
 919         printk("Loading RX\n");
 920         z8530_rtsdtr(c,1);
 921         printk("Rx interrupts ON\n");
 922         write_zsreg(c, R3, c->regs[R3]|RxENABLE);
 923         return 0;
 924 }
 925
 926 EXPORT_SYMBOL(z8530_sync_txdma_open);
 927
 928 int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c)
 929 {
 930         unsigned long flags;
 931         u8 chk;
 932         c->irqs = &z8530_nop;
 933         c->max = 0;
 934         c->sync = 0;
 935
 936         /*
 937          *      Disable the PC DMA channels
 938          */
 939
 940         flags = claim_dma_lock();
 941
 942         disable_dma(c->txdma);
 943         clear_dma_ff(c->txdma);
 944         c->txdma_on = 0;
 945         c->tx_dma_used = 0;
 946
 947         release_dma_lock(flags);
 948
 949         /*
 950          *      Disable DMA control mode
 951          */
 952
 953         c->regs[R1]&= ~WT_RDY_ENAB;
 954         write_zsreg(c, R1, c->regs[R1]);
 955         c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx);
 956         c->regs[R1]|= INT_ALL_Rx;
 957         write_zsreg(c, R1, c->regs[R1]);
 958         c->regs[R14]&= ~DTRREQ;
 959         write_zsreg(c, R14, c->regs[R14]);
 960
 961         if(c->tx_dma_buf[0])
 962         {
 963                 kfree(c->tx_dma_buf[0]);
 964                 c->tx_dma_buf[0]=NULL;
 965         }
 966         if(c->tx_dma_buf[1])
 967         {
 968                 kfree(c->tx_dma_buf[1]);
 969                 c->tx_dma_buf[1]=NULL;
 970         }
 971         chk=read_zsreg(c,R0);
 972         write_zsreg(c, R3, c->regs[R3]);
 973         z8530_rtsdtr(c,0);
 974         return 0;
 975 }
 976
 977
 978 EXPORT_SYMBOL(z8530_sync_txdma_close);
 979
 980 /*
 981  *      Describe a Z8530 in a standard format. We must pass the I/O as
 982  *      the port offset isnt predictable. The main reason for this function
 983  *      is to try and get a common format of report.
 984  */
 985
 986 static char *z8530_type_name[]={
 987         "Z8530",
 988         "Z85C30",
 989         "Z85230"
 990 };
 991
 992 void z8530_describe(struct z8530_dev *dev, char *mapping, int io)
 993 {
 994         printk(KERN_INFO "%s: %s found at %s 0x%X, IRQ %d.\n",
 995                 dev->name,
 996                 z8530_type_name[dev->type],
 997                 mapping,
 998                 Z8530_PORT_OF(io),
 999                 dev->irq);
1000 }
1001
1002 EXPORT_SYMBOL(z8530_describe);
1003
1004 /*
1005  *      Configure up a Z8530
1006  */
1007
1008
1009 int z8530_init(struct z8530_dev *dev)
1010 {
1011         /* NOP the interrupt handlers first - we might get a
1012            floating IRQ transition when we reset the chip */
1013         dev->chanA.irqs=&z8530_nop;
1014         dev->chanB.irqs=&z8530_nop;
1015         /* Reset the chip */
1016         write_zsreg(&dev->chanA, R9, 0xC0);
1017         udelay(200);
1018         /* Now check its valid */
1019         write_zsreg(&dev->chanA, R12, 0xAA);
1020         if(read_zsreg(&dev->chanA, R12)!=0xAA)
1021                 return -ENODEV;
1022         write_zsreg(&dev->chanA, R12, 0x55);
1023         if(read_zsreg(&dev->chanA, R12)!=0x55)
1024                 return -ENODEV;
1025
1026         dev->type=Z8530;
1027
1028         /*
1029          *      See the application note.
1030          */
1031
1032         write_zsreg(&dev->chanA, R15, 0x01);
1033
1034         /*
1035          *      If we can set the low bit of R15 then
1036          *      the chip is enhanced.
1037          */
1038
1039         if(read_zsreg(&dev->chanA, R15)==0x01)
1040         {
1041                 /* This C30 versus 230 detect is from Klaus Kudielka's dmascc */
1042                 /* Put a char in the fifo */
1043                 write_zsreg(&dev->chanA, R8, 0);
1044                 if(read_zsreg(&dev->chanA, R0)&Tx_BUF_EMP)
1045                         dev->type = Z85230;     /* Has a FIFO */
1046                 else
1047                         dev->type = Z85C30;     /* Z85C30, 1 byte FIFO */
1048         }
1049
1050         /*
1051          *      The code assumes R7' and friends are
1052          *      off. Use write_zsext() for these and keep
1053          *      this bit clear.
1054          */
1055
1056         write_zsreg(&dev->chanA, R15, 0);
1057
1058         /*
1059          *      At this point it looks like the chip is behaving
1060          */
1061
1062         memcpy(dev->chanA.regs, reg_init, 16);
1063         memcpy(dev->chanB.regs, reg_init ,16);
1064
1065         return 0;
1066 }
1067
1068
1069 EXPORT_SYMBOL(z8530_init);
1070
1071 int z8530_shutdown(struct z8530_dev *dev)
1072 {
1073         /* Reset the chip */
1074         dev->chanA.irqs=&z8530_nop;
1075         dev->chanB.irqs=&z8530_nop;
1076         write_zsreg(&dev->chanA, R9, 0xC0);
1077         udelay(100);
1078         return 0;
1079 }
1080
1081 EXPORT_SYMBOL(z8530_shutdown);
1082
1083 /*
1084  *      Load a Z8530 channel up from the system data
1085  *      We use +16 to indicate the 'prime' registers
1086  */
1087
1088 int z8530_channel_load(struct z8530_channel *c, u8 *rtable)
1089 {
1090         while(*rtable!=255)
1091         {
1092                 int reg=*rtable++;
1093                 if(reg>0x0F)
1094                         write_zsreg(c, R15, c->regs[15]|1);
1095                 write_zsreg(c, reg&0x0F, *rtable);
1096                 if(reg>0x0F)
1097                         write_zsreg(c, R15, c->regs[15]&~1);
1098                 c->regs[reg]=*rtable++;
1099         }
1100         c->rx_function=z8530_null_rx;
1101         c->skb=NULL;
1102         c->tx_skb=NULL;
1103         c->tx_next_skb=NULL;
1104         c->mtu=1500;
1105         c->max=0;
1106         c->count=0;
1107         c->status=0;    /* Fixme - check DCD now */
1108         c->sync=1;
1109         write_zsreg(c, R3, c->regs[R3]|RxENABLE);
1110         return 0;
1111 }
1112
1113 EXPORT_SYMBOL(z8530_channel_load);
1114
1115
1116 /*
1117  *      Higher level shovelling - transmit chains
1118  */
1119
1120 static void z8530_tx_begin(struct z8530_channel *c)
1121 {
1122         unsigned long flags;
1123         if(c->tx_skb)
1124                 return;
1125
1126         c->tx_skb=c->tx_next_skb;
1127         c->tx_next_skb=NULL;
1128         c->tx_ptr=c->tx_next_ptr;
1129
1130         mark_bh(NET_BH);
1131         if(c->tx_skb==NULL)
1132         {
1133                 /* Idle on */
1134                 if(c->dma_tx)
1135                 {
1136                         flags=claim_dma_lock();
1137                         disable_dma(c->txdma);
1138                         /*
1139                          *      Check if we crapped out.
1140                          */
1141                         if(get_dma_residue(c->txdma))
1142                         {
1143                                 c->stats.tx_dropped++;
1144                                 c->stats.tx_fifo_errors++;
1145                         }
1146                         release_dma_lock(flags);
1147                 }
1148                 c->txcount=0;
1149         }
1150         else
1151         {
1152                 c->txcount=c->tx_skb->len;
1153
1154
1155                 if(c->dma_tx)
1156                 {
1157                         /*
1158                          *      FIXME. DMA is broken for the original 8530,
1159                          *      on the older parts we need to set a flag and
1160                          *      wait for a further TX interrupt to fire this
1161                          *      stage off
1162                          */
1163
1164                         flags=claim_dma_lock();
1165                         disable_dma(c->txdma);
1166
1167                         /*
1168                          *      These two are needed by the 8530/85C30
1169                          *      and must be issued when idling.
1170                          */
1171
1172                         if(c->dev->type!=Z85230)
1173                         {
1174                                 write_zsctrl(c, RES_Tx_CRC);
1175                                 write_zsctrl(c, RES_EOM_L);
1176                         }
1177                         write_zsreg(c, R10, c->regs[10]&~ABUNDER);
1178                         clear_dma_ff(c->txdma);
1179                         set_dma_addr(c->txdma, virt_to_bus(c->tx_ptr));
1180                         set_dma_count(c->txdma, c->txcount);
1181                         enable_dma(c->txdma);
1182                         release_dma_lock(flags);
1183                         write_zsctrl(c, RES_EOM_L);
1184                         write_zsreg(c, R5, c->regs[R5]|TxENAB);
1185                 }
1186                 else
1187                 {
1188                         save_flags(flags);
1189                         cli();
1190                         /* ABUNDER off */
1191                         write_zsreg(c, R10, c->regs[10]);
1192                         write_zsctrl(c, RES_Tx_CRC);
1193 //???                   write_zsctrl(c, RES_EOM_L);
1194
1195                         while(c->txcount && (read_zsreg(c,R0)&Tx_BUF_EMP))
1196                         {
1197                                 write_zsreg(c, R8, *c->tx_ptr++);
1198                                 c->txcount--;
1199                         }
1200                         restore_flags(flags);
1201                 }
1202         }
1203 }
1204
1205
1206 static void z8530_tx_done(struct z8530_channel *c)
1207 {
1208         unsigned long flags;
1209         struct sk_buff *skb;
1210
1211         spin_lock_irqsave(&z8530_buffer_lock, flags);
1212         c->netdevice->tbusy=0;
1213         /* Actually this can happen.*/
1214         if(c->tx_skb==NULL)
1215         {
1216                 spin_unlock_irqrestore(&z8530_buffer_lock, flags);
1217                 return;
1218         }
1219         skb=c->tx_skb;
1220         c->tx_skb=NULL;
1221         z8530_tx_begin(c);
1222         spin_unlock_irqrestore(&z8530_buffer_lock, flags);
1223         c->stats.tx_packets++;
1224         c->stats.tx_bytes+=skb->len;
1225         dev_kfree_skb(skb);
1226 }
1227
1228 /*
1229  *      Higher level shovelling - receive chains
1230  */
1231
1232 void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb)
1233 {
1234         kfree_skb(skb);
1235 }
1236
1237 EXPORT_SYMBOL(z8530_null_rx);
1238
1239 static void z8530_rx_done(struct z8530_channel *c)
1240 {
1241         struct sk_buff *skb;
1242         int ct;
1243
1244         /*
1245          *      Is our receive engine in DMA mode
1246          */
1247
1248         if(c->rxdma_on)
1249         {
1250                 /*
1251                  *      Save the ready state and the buffer currently
1252                  *      being used as the DMA target
1253                  */
1254
1255                 int ready=c->dma_ready;
1256                 unsigned char *rxb=c->rx_buf[c->dma_num];
1257                 unsigned long flags;
1258
1259                 /*
1260                  *      Complete this DMA. Neccessary to find the length
1261                  */
1262
1263                 flags=claim_dma_lock();
1264
1265                 disable_dma(c->rxdma);
1266                 clear_dma_ff(c->rxdma);
1267                 c->rxdma_on=0;
1268                 ct=c->mtu-get_dma_residue(c->rxdma);
1269                 if(ct<0)
1270                         ct=2;   /* Shit happens.. */
1271                 c->dma_ready=0;
1272
1273                 /*
1274                  *      Normal case: the other slot is free, start the next DMA
1275                  *      into it immediately.
1276                  */
1277
1278                 if(ready)
1279                 {
1280                         c->dma_num^=1;
1281                         set_dma_mode(c->rxdma, DMA_MODE_READ|0x10);
1282                         set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[c->dma_num]));
1283                         set_dma_count(c->rxdma, c->mtu);
1284                         c->rxdma_on = 1;
1285                         enable_dma(c->rxdma);
1286                         /* Stop any frames that we missed the head of
1287                            from passing */
1288                         write_zsreg(c, R0, RES_Rx_CRC);
1289                 }
1290                 else
1291                         /* Can't occur as we dont reenable the DMA irq until
1292                            after the flip is done */
1293                         printk("DMA flip overrun!\n");
1294
1295                 release_dma_lock(flags);
1296
1297                 /*
1298                  *      Shove the old buffer into an sk_buff. We can't DMA
1299                  *      directly into one on a PC - it might be above the 16Mb
1300                  *      boundary. Optimisation - we could check to see if we
1301                  *      can avoid the copy. Optimisation 2 - make the memcpy
1302                  *      a copychecksum.
1303                  */
1304
1305                 skb=dev_alloc_skb(ct);
1306                 if(skb==NULL)
1307                 {
1308                         c->stats.rx_dropped++;
1309                         printk(KERN_WARNING "%s: Memory squeeze.\n", c->netdevice->name);
1310                 }
1311                 else
1312                 {
1313                         skb_put(skb, ct);
1314                         memcpy(skb->data, rxb, ct);
1315                         c->stats.rx_packets++;
1316                         c->stats.rx_bytes+=ct;
1317                 }
1318                 c->dma_ready=1;
1319         }
1320         else
1321         {
1322                 RT_LOCK;
1323                 skb=c->skb;
1324
1325                 /*
1326                  *      The game we play for non DMA is similar. We want to
1327                  *      get the controller set up for the next packet as fast
1328                  *      as possible. We potentially only have one byte + the
1329                  *      fifo length for this. Thus we want to flip to the new
1330                  *      buffer and then mess around copying and allocating
1331                  *      things. For the current case it doesn't matter but
1332                  *      if you build a system where the sync irq isnt blocked
1333                  *      by the kernel IRQ disable then you need only block the
1334                  *      sync IRQ for the RT_LOCK area.
1335                  *
1336                  */
1337                 ct=c->count;
1338
1339                 c->skb = c->skb2;
1340                 c->count = 0;
1341                 c->max = c->mtu;
1342                 if(c->skb)
1343                 {
1344                         c->dptr = c->skb->data;
1345                         c->max = c->mtu;
1346                 }
1347                 else
1348                 {
1349                         c->count= 0;
1350                         c->max = 0;
1351                 }
1352                 RT_UNLOCK;
1353
1354                 c->skb2 = dev_alloc_skb(c->mtu);
1355                 if(c->skb2==NULL)
1356                         printk(KERN_WARNING "%s: memory squeeze.\n",
1357                                 c->netdevice->name);
1358                 else
1359                 {
1360                         skb_put(c->skb2,c->mtu);
1361                 }
1362                 c->stats.rx_packets++;
1363                 c->stats.rx_bytes+=ct;
1364
1365         }
1366         /*
1367          *      If we received a frame we must now process it.
1368          */
1369         if(skb)
1370         {
1371                 skb_trim(skb, ct);
1372                 c->rx_function(c,skb);
1373         }
1374         else
1375         {
1376                 c->stats.rx_dropped++;
1377                 printk(KERN_ERR "%s: Lost a frame\n", c->netdevice->name);
1378         }
1379 }
1380
1381 /*
1382  *      Cannot DMA over a 64K boundary on a PC
1383  */
1384
1385 extern inline int spans_boundary(struct sk_buff *skb)
1386 {
1387         unsigned long a=(unsigned long)skb->data;
1388         a^=(a+skb->len);
1389         if(a&0x00010000)        /* If the 64K bit is different.. */
1390         {
1391                 printk("spanner\n");
1392                 return 1;
1393         }
1394         return 0;
1395 }
1396
1397 /*
1398  *      Queue a packet for transmission. Because we have rather
1399  *      hard to hit interrupt latencies for the Z85230 per packet
1400  *      even in DMA mode we do the flip to DMA buffer if needed here
1401  *      not in the IRQ.
1402  */
1403
1404 int z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb)
1405 {
1406         unsigned long flags;
1407         if(c->tx_next_skb)
1408         {
1409                 skb->dev->tbusy=1;
1410                 return 1;
1411         }
1412
1413         /* PC SPECIFIC - DMA limits */
1414
1415         /*
1416          *      If we will DMA the transmit and its gone over the ISA bus
1417          *      limit, then copy to the flip buffer
1418          */
1419
1420         if(c->dma_tx && ((unsigned long)(virt_to_bus(skb->data+skb->len))>=16*1024*1024 || spans_boundary(skb)))
1421         {
1422                 /*
1423                  *      Send the flip buffer, and flip the flippy bit.
1424                  *      We don't care which is used when just so long as
1425                  *      we never use the same buffer twice in a row. Since
1426                  *      only one buffer can be going out at a time the other
1427                  *      has to be safe.
1428                  */
1429                 c->tx_next_ptr=c->tx_dma_buf[c->tx_dma_used];
1430                 c->tx_dma_used^=1;      /* Flip temp buffer */
1431                 memcpy(c->tx_next_ptr, skb->data, skb->len);
1432         }
1433         else
1434                 c->tx_next_ptr=skb->data;
1435         RT_LOCK;
1436         c->tx_next_skb=skb;
1437         RT_UNLOCK;
1438
1439         spin_lock_irqsave(&z8530_buffer_lock, flags);
1440         z8530_tx_begin(c);
1441         spin_unlock_irqrestore(&z8530_buffer_lock, flags);
1442         return 0;
1443 }
1444
1445 EXPORT_SYMBOL(z8530_queue_xmit);
1446
1447 struct net_device_stats *z8530_get_stats(struct z8530_channel *c)
1448 {
1449         return &c->stats;
1450 }
1451
1452 EXPORT_SYMBOL(z8530_get_stats);
1453
1454 #ifdef MODULE
1455
1456 /*
1457  *      Module support
1458  */
1459
1460 int init_module(void)
1461 {
1462         printk(KERN_INFO "Generic Z85C30/Z85230 interface driver v0.02\n");
1463         return 0;
1464 }
1465
1466 void cleanup_module(void)
1467 {
1468 }
1469
1470 #endif