1 /* $Id: itlb_base.S,v 1.7 1999/03/02 15:42:12 jj Exp $
2 * itlb_base.S: Front end to ITLB miss replacement strategy.
3 * This is included directly into the trap table.
5 * Copyright (C) 1996,1998 David S. Miller (davem@dm.cobaltmicro.com)
6 * Copyright (C) 1997,1998 Jakub Jelinek (jj@ultra.linux.cz)
9 #define TAG_CONTEXT_BITS 0x3ff
10 #define VPTE_SHIFT (PAGE_SHIFT - 3)
12 /* Ways we can get here:
14 * 1) Nucleus instruction misses from module code.
15 * 2) All user instruction misses.
17 * All real page faults merge their code paths to the
18 * sparc64_realfault_common label below.
21 /* ITLB ** ICACHE line 1: Quick user TLB misses */
22 ldxa [%g1 + %g1] ASI_IMMU, %g4 ! Get TAG_ACCESS
23 srax %g4, VPTE_SHIFT, %g6 ! Create VPTE offset
24 ldxa [%g3 + %g6] ASI_P, %g5 ! Load VPTE
25 1: brgez,pn %g5, 3f ! Not valid, branch out
26 and %g5, (_PAGE_PRESENT|_PAGE_READ), %g4 ! Mask readable bits
27 2: stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load PTE into TLB
29 3: cmp %g4, (_PAGE_PRESENT|_PAGE_READ) ! Readable page?
31 /* ITLB ** ICACHE line 2: Quick user ref updates */
32 bne,pn %xcc, 4f ! Nope, real missing page
33 sllx %g1, 60, %g4 ! Sliiickkk...
34 or %g5, _PAGE_ACCESSED, %g5 ! Mark as touched
35 or %g5, %g4, %g5 ! Allow user to see it
36 ba,pt %xcc, 2b ! Branch to load TLB
37 stxa %g5, [%g3 + %g6] ASI_S ! Update PTE table
38 4: rdpr %pstate, %g4 ! Move into alternate globals
39 wrpr %g4, PSTATE_AG|PSTATE_MG, %pstate
41 /* ITLB ** ICACHE line 3: Real faults */
42 rdpr %tpc, %g5 ! And load faulting VA
44 sparc64_realfault_common: ! Called by TL0 dtlb_miss too
45 sethi %hi(1f), %g7 ! Save state
46 ba,pt %xcc, etrap ! ...
47 1: or %g7, %lo(1b), %g7 ! ...
48 mov %l4, %o2 ! Read/Write/No idea
49 srlx %l5, PAGE_SHIFT, %o1 ! Page align faulting VA
50 add %sp, STACK_BIAS + REGWIN_SZ, %o0! Compute pt_regs arg
52 /* ITLB ** ICACHE line 4: Call fault processing code */
53 call do_sparc64_fault ! Call fault handler
54 sllx %o1, PAGE_SHIFT, %o1 ! Finish page alignment
55 ba,a,pt %xcc, rtrap_clr_l6 ! Restore cpu state
58 rdpr %tpc, %g3 ! Prepare winfixup TNPC
59 or %g3, 0x7c, %g3 ! Compute offset to branch
60 wrpr %g3, %tnpc ! Write it into TNPC
63 #undef TAG_CONTEXT_BITS