2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@suse.cz>
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/malloc.h>
20 #include <linux/ioport.h>
21 #include <linux/spinlock.h>
23 #include <linux/slab.h>
24 #include <linux/kmod.h> /* for hotplug_path */
27 #include <asm/dma.h> /* isa_dma_bridge_buggy */
32 #define DBG(x...) printk(x)
37 LIST_HEAD(pci_root_buses
);
38 LIST_HEAD(pci_devices
);
41 * pci_find_slot - locate PCI device from a given PCI slot
42 * @bus: number of PCI bus on which desired PCI device resides
43 * @devfn: number of PCI slot in which desired PCI device resides
45 * Given a PCI bus and slot number, the desired PCI device is
46 * located in system global list of PCI devices. If the device
47 * is found, a pointer to its data structure is returned. If no
48 * device is found, %NULL is returned.
51 pci_find_slot(unsigned int bus
, unsigned int devfn
)
55 pci_for_each_dev(dev
) {
56 if (dev
->bus
->number
== bus
&& dev
->devfn
== devfn
)
64 pci_find_subsys(unsigned int vendor
, unsigned int device
,
65 unsigned int ss_vendor
, unsigned int ss_device
,
66 const struct pci_dev
*from
)
68 struct list_head
*n
= from
? from
->global_list
.next
: pci_devices
.next
;
70 while (n
!= &pci_devices
) {
71 struct pci_dev
*dev
= pci_dev_g(n
);
72 if ((vendor
== PCI_ANY_ID
|| dev
->vendor
== vendor
) &&
73 (device
== PCI_ANY_ID
|| dev
->device
== device
) &&
74 (ss_vendor
== PCI_ANY_ID
|| dev
->subsystem_vendor
== ss_vendor
) &&
75 (ss_device
== PCI_ANY_ID
|| dev
->subsystem_device
== ss_device
))
84 * pci_find_device - begin or continue searching for a PCI device by vendor/device id
85 * @vendor: PCI vendor id to match, or %PCI_ANY_ID to match all vendor ids
86 * @device: PCI device id to match, or %PCI_ANY_ID to match all vendor ids
87 * @from: Previous PCI device found in search, or %NULL for new search.
89 * Iterates through the list of known PCI devices. If a PCI device is
90 * found with a matching @vendor and @device, a pointer to its device structure is
91 * returned. Otherwise, %NULL is returned.
93 * A new search is initiated by passing %NULL to the @from argument.
94 * Otherwise if @from is not null, searches continue from that point.
97 pci_find_device(unsigned int vendor
, unsigned int device
, const struct pci_dev
*from
)
99 return pci_find_subsys(vendor
, device
, PCI_ANY_ID
, PCI_ANY_ID
, from
);
104 * pci_find_class - begin or continue searching for a PCI device by class
105 * @class: search for a PCI device with this class designation
106 * @from: Previous PCI device found in search, or %NULL for new search.
108 * Iterates through the list of known PCI devices. If a PCI device is
109 * found with a matching @class, a pointer to its device structure is
110 * returned. Otherwise, %NULL is returned.
112 * A new search is initiated by passing %NULL to the @from argument.
113 * Otherwise if @from is not null, searches continue from that point.
116 pci_find_class(unsigned int class, const struct pci_dev
*from
)
118 struct list_head
*n
= from
? from
->global_list
.next
: pci_devices
.next
;
120 while (n
!= &pci_devices
) {
121 struct pci_dev
*dev
= pci_dev_g(n
);
122 if (dev
->class == class)
131 pci_find_capability(struct pci_dev
*dev
, int cap
)
137 pci_read_config_word(dev
, PCI_STATUS
, &status
);
138 if (!(status
& PCI_STATUS_CAP_LIST
))
140 switch (dev
->hdr_type
) {
141 case PCI_HEADER_TYPE_NORMAL
:
142 case PCI_HEADER_TYPE_BRIDGE
:
143 pci_read_config_byte(dev
, PCI_CAPABILITY_LIST
, &pos
);
145 case PCI_HEADER_TYPE_CARDBUS
:
146 pci_read_config_byte(dev
, PCI_CB_CAPABILITY_LIST
, &pos
);
151 while (ttl
-- && pos
>= 0x40) {
153 pci_read_config_byte(dev
, pos
+ PCI_CAP_LIST_ID
, &id
);
158 pci_read_config_byte(dev
, pos
+ PCI_CAP_LIST_NEXT
, &pos
);
165 * pci_find_parent_resource - return resource region of parent bus of given region
166 * @dev: PCI device structure contains resources to be searched
167 * @res: child resource record for which parent is sought
169 * For given resource region of given device, return the resource
170 * region of parent bus the given region is contained in or where
171 * it should be allocated from.
174 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
176 const struct pci_bus
*bus
= dev
->bus
;
178 struct resource
*best
= NULL
;
181 struct resource
*r
= bus
->resource
[i
];
184 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
185 continue; /* Not contained */
186 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
187 continue; /* Wrong type */
188 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
189 return r
; /* Exact match */
190 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
191 best
= r
; /* Approximating prefetchable by non-prefetchable */
197 * pci_set_power_state - Set power management state of a device.
198 * @dev: PCI device for which PM is set
199 * @new_state: new power management statement (0 == D0, 3 == D3, etc.)
201 * Set power management state of a device. For transitions from state D3
202 * it isn't as straightforward as one could assume since many devices forget
203 * their configuration space during wakeup. Returns old power state.
206 pci_set_power_state(struct pci_dev
*dev
, int new_state
)
208 u32 base
[5], romaddr
;
209 u16 pci_command
, pwr_command
;
210 u8 pci_latency
, pci_cacheline
;
212 int pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
216 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pwr_command
);
217 old_state
= pwr_command
& PCI_PM_CTRL_STATE_MASK
;
218 if (old_state
== new_state
)
220 DBG("PCI: %s goes from D%d to D%d\n", dev
->slot_name
, old_state
, new_state
);
221 if (old_state
== 3) {
222 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
223 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
& ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
));
224 for (i
= 0; i
< 5; i
++)
225 pci_read_config_dword(dev
, PCI_BASE_ADDRESS_0
+ i
*4, &base
[i
]);
226 pci_read_config_dword(dev
, PCI_ROM_ADDRESS
, &romaddr
);
227 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &pci_latency
);
228 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &pci_cacheline
);
229 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, new_state
);
230 for (i
= 0; i
< 5; i
++)
231 pci_write_config_dword(dev
, PCI_BASE_ADDRESS_0
+ i
*4, base
[i
]);
232 pci_write_config_dword(dev
, PCI_ROM_ADDRESS
, romaddr
);
233 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, dev
->irq
);
234 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cacheline
);
235 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, pci_latency
);
236 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
238 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, (pwr_command
& ~PCI_PM_CTRL_STATE_MASK
) | new_state
);
243 * pci_enable_device - Initialize device before it's used by a driver.
244 * @dev: PCI device to be initialized
246 * Initialize device before it's used by a driver. Ask low-level code
247 * to enable I/O and memory. Wake up the device if it was suspended.
248 * Beware, this function can fail.
251 pci_enable_device(struct pci_dev
*dev
)
255 if ((err
= pcibios_enable_device(dev
)) < 0)
257 pci_set_power_state(dev
, 0);
262 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
266 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
270 while (dev
->bus
->self
) {
271 pin
= (pin
+ PCI_SLOT(dev
->devfn
)) % 4;
272 dev
= dev
->bus
->self
;
279 * Registration of PCI drivers and handling of hot-pluggable devices.
282 static LIST_HEAD(pci_drivers
);
284 const struct pci_device_id
*
285 pci_match_device(const struct pci_device_id
*ids
, const struct pci_dev
*dev
)
287 while (ids
->vendor
|| ids
->subvendor
|| ids
->class_mask
) {
288 if ((ids
->vendor
== PCI_ANY_ID
|| ids
->vendor
== dev
->vendor
) &&
289 (ids
->device
== PCI_ANY_ID
|| ids
->device
== dev
->device
) &&
290 (ids
->subvendor
== PCI_ANY_ID
|| ids
->subvendor
== dev
->subsystem_vendor
) &&
291 (ids
->subdevice
== PCI_ANY_ID
|| ids
->subdevice
== dev
->subsystem_device
) &&
292 !((ids
->class ^ dev
->class) & ids
->class_mask
))
300 pci_announce_device(struct pci_driver
*drv
, struct pci_dev
*dev
)
302 const struct pci_device_id
*id
;
305 id
= pci_match_device(drv
->id_table
, dev
);
310 if (drv
->probe(dev
, id
) >= 0) {
318 pci_register_driver(struct pci_driver
*drv
)
323 list_add_tail(&drv
->node
, &pci_drivers
);
324 pci_for_each_dev(dev
) {
325 if (!pci_dev_driver(dev
))
326 count
+= pci_announce_device(drv
, dev
);
332 pci_unregister_driver(struct pci_driver
*drv
)
336 list_del(&drv
->node
);
337 pci_for_each_dev(dev
) {
338 if (dev
->driver
== drv
) {
346 #ifdef CONFIG_HOTPLUG
350 #define TRUE (!FALSE)
354 run_sbin_hotplug(struct pci_dev
*pdev
, int insert
)
357 char *argv
[3], *envp
[8];
358 char id
[20], sub_id
[24], bus_id
[24], class_id
[20];
360 if (!hotplug_path
[0])
363 sprintf(class_id
, "PCI_CLASS=%X", pdev
->class);
364 sprintf(id
, "PCI_ID=%X/%X", pdev
->vendor
, pdev
->device
);
365 sprintf(sub_id
, "PCI_SUBSYS_ID=%X/%X", pdev
->subsystem_vendor
, pdev
->subsystem_device
);
366 sprintf(bus_id
, "PCI_SLOT_NAME=%s", pdev
->slot_name
);
369 argv
[i
++] = hotplug_path
;
374 /* minimal command environment */
375 envp
[i
++] = "HOME=/";
376 envp
[i
++] = "PATH=/sbin:/bin:/usr/sbin:/usr/bin";
378 /* other stuff we want to pass to /sbin/hotplug */
379 envp
[i
++] = class_id
;
384 envp
[i
++] = "ACTION=add";
386 envp
[i
++] = "ACTION=remove";
389 call_usermodehelper (argv
[0], argv
, envp
);
393 pci_insert_device(struct pci_dev
*dev
, struct pci_bus
*bus
)
395 struct list_head
*ln
;
397 list_add_tail(&dev
->bus_list
, &bus
->devices
);
398 list_add_tail(&dev
->global_list
, &pci_devices
);
399 #ifdef CONFIG_PROC_FS
400 pci_proc_attach_device(dev
);
402 for(ln
=pci_drivers
.next
; ln
!= &pci_drivers
; ln
=ln
->next
) {
403 struct pci_driver
*drv
= list_entry(ln
, struct pci_driver
, node
);
404 if (drv
->remove
&& pci_announce_device(drv
, dev
))
408 /* notify userspace of new hotplug device */
409 run_sbin_hotplug(dev
, TRUE
);
413 pci_free_resources(struct pci_dev
*dev
)
417 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
418 struct resource
*res
= dev
->resource
+ i
;
420 release_resource(res
);
425 pci_remove_device(struct pci_dev
*dev
)
428 if (dev
->driver
->remove
)
429 dev
->driver
->remove(dev
);
432 list_del(&dev
->bus_list
);
433 list_del(&dev
->global_list
);
434 pci_free_resources(dev
);
435 #ifdef CONFIG_PROC_FS
436 pci_proc_detach_device(dev
);
439 /* notify userspace of hotplug device removal */
440 run_sbin_hotplug(dev
, FALSE
);
445 static struct pci_driver pci_compat_driver
= {
450 pci_dev_driver(const struct pci_dev
*dev
)
456 for(i
=0; i
<=PCI_ROM_RESOURCE
; i
++)
457 if (dev
->resource
[i
].flags
& IORESOURCE_BUSY
)
458 return &pci_compat_driver
;
465 * This interrupt-safe spinlock protects all accesses to PCI
466 * configuration space.
469 static spinlock_t pci_lock
= SPIN_LOCK_UNLOCKED
;
472 * Wrappers for all PCI configuration access functions. They just check
473 * alignment, do locking and call the low-level functions pointed to
477 #define PCI_byte_BAD 0
478 #define PCI_word_BAD (pos & 1)
479 #define PCI_dword_BAD (pos & 3)
481 #define PCI_OP(rw,size,type) \
482 int pci_##rw##_config_##size (struct pci_dev *dev, int pos, type value) \
485 unsigned long flags; \
486 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
487 spin_lock_irqsave(&pci_lock, flags); \
488 res = dev->bus->ops->rw##_##size(dev, pos, value); \
489 spin_unlock_irqrestore(&pci_lock, flags); \
493 PCI_OP(read
, byte
, u8
*)
494 PCI_OP(read
, word
, u16
*)
495 PCI_OP(read
, dword
, u32
*)
496 PCI_OP(write
, byte
, u8
)
497 PCI_OP(write
, word
, u16
)
498 PCI_OP(write
, dword
, u32
)
502 pci_set_master(struct pci_dev
*dev
)
506 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
507 if (! (cmd
& PCI_COMMAND_MASTER
)) {
508 DBG("PCI: Enabling bus mastering for device %s\n", dev
->slot_name
);
509 cmd
|= PCI_COMMAND_MASTER
;
510 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
512 pcibios_set_master(dev
);
516 * Translate the low bits of the PCI base
517 * to the resource type
519 static inline unsigned int pci_calc_resource_flags(unsigned int flags
)
521 if (flags
& PCI_BASE_ADDRESS_SPACE_IO
)
522 return IORESOURCE_IO
;
524 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
525 return IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
527 return IORESOURCE_MEM
;
531 * Find the extent of a PCI decode..
533 static u32
pci_size(u32 base
, unsigned long mask
)
535 u32 size
= mask
& base
; /* Find the significant bits */
536 size
= size
& ~(size
-1); /* Get the lowest of them to find the decode size */
537 return size
-1; /* extent = size - 1 */
540 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
542 unsigned int pos
, reg
, next
;
544 struct resource
*res
;
546 for(pos
=0; pos
<howmany
; pos
= next
) {
548 res
= &dev
->resource
[pos
];
549 res
->name
= dev
->name
;
550 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
551 pci_read_config_dword(dev
, reg
, &l
);
552 pci_write_config_dword(dev
, reg
, ~0);
553 pci_read_config_dword(dev
, reg
, &sz
);
554 pci_write_config_dword(dev
, reg
, l
);
555 if (!sz
|| sz
== 0xffffffff)
559 if ((l
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_MEMORY
) {
560 res
->start
= l
& PCI_BASE_ADDRESS_MEM_MASK
;
561 sz
= pci_size(sz
, PCI_BASE_ADDRESS_MEM_MASK
);
563 res
->start
= l
& PCI_BASE_ADDRESS_IO_MASK
;
564 sz
= pci_size(sz
, PCI_BASE_ADDRESS_IO_MASK
& 0xffff);
566 res
->end
= res
->start
+ (unsigned long) sz
;
567 res
->flags
|= (l
& 0xf) | pci_calc_resource_flags(l
);
568 if ((l
& (PCI_BASE_ADDRESS_SPACE
| PCI_BASE_ADDRESS_MEM_TYPE_MASK
))
569 == (PCI_BASE_ADDRESS_SPACE_MEMORY
| PCI_BASE_ADDRESS_MEM_TYPE_64
)) {
570 pci_read_config_dword(dev
, reg
+4, &l
);
572 #if BITS_PER_LONG == 64
573 res
->start
|= ((unsigned long) l
) << 32;
574 res
->end
= res
->start
+ sz
;
575 pci_write_config_dword(dev
, reg
+4, ~0);
576 pci_read_config_dword(dev
, reg
+4, &tmp
);
577 pci_write_config_dword(dev
, reg
+4, l
);
579 res
->end
= res
->start
+ (((unsigned long) ~l
) << 32);
582 printk(KERN_ERR
"PCI: Unable to handle 64-bit address for device %s\n", dev
->slot_name
);
591 dev
->rom_base_reg
= rom
;
592 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
593 pci_read_config_dword(dev
, rom
, &l
);
594 pci_write_config_dword(dev
, rom
, ~PCI_ROM_ADDRESS_ENABLE
);
595 pci_read_config_dword(dev
, rom
, &sz
);
596 pci_write_config_dword(dev
, rom
, l
);
599 if (sz
&& sz
!= 0xffffffff) {
600 res
->flags
= (l
& PCI_ROM_ADDRESS_ENABLE
) |
601 IORESOURCE_MEM
| IORESOURCE_PREFETCH
| IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
602 res
->start
= l
& PCI_ROM_ADDRESS_MASK
;
603 sz
= pci_size(sz
, PCI_ROM_ADDRESS_MASK
);
604 res
->end
= res
->start
+ (unsigned long) sz
;
606 res
->name
= dev
->name
;
610 void __init
pci_read_bridge_bases(struct pci_bus
*child
)
612 struct pci_dev
*dev
= child
->self
;
613 u8 io_base_lo
, io_limit_lo
;
614 u16 mem_base_lo
, mem_limit_lo
, io_base_hi
, io_limit_hi
;
615 u32 mem_base_hi
, mem_limit_hi
;
616 unsigned long base
, limit
;
617 struct resource
*res
;
620 if (!dev
) /* It's a host bus, nothing to read */
624 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
626 res
= child
->resource
[0];
627 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
628 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
629 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
630 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
631 base
= ((io_base_lo
& PCI_IO_RANGE_MASK
) << 8) | (io_base_hi
<< 16);
632 limit
= ((io_limit_lo
& PCI_IO_RANGE_MASK
) << 8) | (io_limit_hi
<< 16);
633 if (base
&& base
<= limit
) {
634 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
636 res
->end
= limit
+ 0xfff;
637 res
->name
= child
->name
;
640 * Ugh. We don't know enough about this bridge. Just assume
641 * that it's entirely transparent.
643 printk("Unknown bridge resource %d: assuming transparent\n", 0);
644 child
->resource
[0] = child
->parent
->resource
[0];
647 res
= child
->resource
[1];
648 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
649 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
650 base
= (mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
651 limit
= (mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
652 if (base
&& base
<= limit
) {
653 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
655 res
->end
= limit
+ 0xfffff;
656 res
->name
= child
->name
;
658 /* See comment above. Same thing */
659 printk("Unknown bridge resource %d: assuming transparent\n", 1);
660 child
->resource
[1] = child
->parent
->resource
[1];
663 res
= child
->resource
[2];
664 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
665 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
666 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
667 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
668 base
= (mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
669 limit
= (mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
670 #if BITS_PER_LONG == 64
671 base
|= ((long) mem_base_hi
) << 32;
672 limit
|= ((long) mem_limit_hi
) << 32;
674 if (mem_base_hi
|| mem_limit_hi
) {
675 printk(KERN_ERR
"PCI: Unable to handle 64-bit address space for %s\n", child
->name
);
679 if (base
&& base
<= limit
) {
680 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
682 res
->end
= limit
+ 0xfffff;
683 res
->name
= child
->name
;
685 /* See comments above */
686 printk("Unknown bridge resource %d: assuming transparent\n", 2);
687 child
->resource
[2] = child
->parent
->resource
[2];
691 static struct pci_bus
* __init
pci_alloc_bus(void)
695 b
= kmalloc(sizeof(*b
), GFP_KERNEL
);
697 memset(b
, 0, sizeof(*b
));
698 INIT_LIST_HEAD(&b
->children
);
699 INIT_LIST_HEAD(&b
->devices
);
704 static struct pci_bus
* __init
pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
, int busnr
)
706 struct pci_bus
*child
;
709 * Allocate a new bus, and inherit stuff from the parent..
711 child
= pci_alloc_bus();
713 list_add_tail(&child
->node
, &parent
->children
);
715 dev
->subordinate
= child
;
716 child
->parent
= parent
;
717 child
->ops
= parent
->ops
;
718 child
->sysdata
= parent
->sysdata
;
721 * Set up the primary, secondary and subordinate
724 child
->number
= child
->secondary
= busnr
;
725 child
->primary
= parent
->secondary
;
726 child
->subordinate
= 0xff;
731 static unsigned int __init
pci_do_scan_bus(struct pci_bus
*bus
);
734 * If it's a bridge, configure it and scan the bus behind it.
735 * For CardBus bridges, we don't scan behind as the devices will
736 * be handled by the bridge driver itself.
738 * We need to process bridges in two passes -- first we scan those
739 * already configured by the BIOS and after we are done with all of
740 * them, we proceed to assigning numbers to the remaining buses in
741 * order to avoid overlaps between old and new bus numbers.
743 static int __init
pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
* dev
, int max
, int pass
)
747 struct pci_bus
*child
;
748 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
750 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
751 DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n", dev
->slot_name
, buses
& 0xffffff, pass
);
752 if ((buses
& 0xffff00) && !pcibios_assign_all_busses()) {
754 * Bus already configured by firmware, process it in the first
755 * pass and just note the configuration.
759 child
= pci_add_new_bus(bus
, dev
, 0);
760 child
->primary
= buses
& 0xFF;
761 child
->secondary
= (buses
>> 8) & 0xFF;
762 child
->subordinate
= (buses
>> 16) & 0xFF;
763 child
->number
= child
->secondary
;
765 unsigned int cmax
= pci_do_scan_bus(child
);
766 if (cmax
> max
) max
= cmax
;
769 unsigned int cmax
= child
->subordinate
;
770 for (i
= 0; i
< 4; i
++)
771 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
772 if (cmax
> max
) max
= cmax
;
776 * We need to assign a number to this bus which we always
777 * do in the second pass. We also keep all address decoders
778 * on the bridge disabled during scanning. FIXME: Why?
782 pci_read_config_word(dev
, PCI_COMMAND
, &cr
);
783 pci_write_config_word(dev
, PCI_COMMAND
, 0x0000);
784 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
785 child
= pci_add_new_bus(bus
, dev
, ++max
);
786 buses
= (buses
& 0xff000000)
787 | ((unsigned int)(child
->primary
) << 0)
788 | ((unsigned int)(child
->secondary
) << 8)
789 | ((unsigned int)(child
->subordinate
) << 16);
791 * We need to blast all three values with a single write.
793 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
795 /* Now we can scan all subordinate buses... */
796 max
= pci_do_scan_bus(child
);
800 * For CardBus bridges, we leave 4 bus numbers
801 * as cards with a PCI-to-PCI bridge can be
805 for (i
= 0; i
< 4; i
++)
806 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
809 * Set the subordinate bus number to its real value.
811 child
->subordinate
= max
;
812 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
813 pci_write_config_word(dev
, PCI_COMMAND
, cr
);
815 sprintf(child
->name
, (is_cardbus
? "PCI CardBus #%02x" : "PCI Bus #%02x"), child
->number
);
820 * Read interrupt line and base address registers.
821 * The architecture-dependent code can tweak these, of course.
823 static void pci_read_irq(struct pci_dev
*dev
)
827 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
829 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
834 * Fill in class and map information of a device
836 int pci_setup_device(struct pci_dev
* dev
)
840 sprintf(dev
->slot_name
, "%02x:%02x.%d", dev
->bus
->number
, PCI_SLOT(dev
->devfn
), PCI_FUNC(dev
->devfn
));
841 sprintf(dev
->name
, "PCI device %04x:%04x", dev
->vendor
, dev
->device
);
843 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
844 class >>= 8; /* upper 3 bytes */
848 DBG("Found %02x:%02x [%04x/%04x] %06x %02x\n", dev
->bus
->number
, dev
->devfn
, dev
->vendor
, dev
->device
, class, dev
->hdr_type
);
850 switch (dev
->hdr_type
) { /* header type */
851 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
852 if (class == PCI_CLASS_BRIDGE_PCI
)
855 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
856 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
857 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
860 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
861 if (class != PCI_CLASS_BRIDGE_PCI
)
863 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
866 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
867 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
870 pci_read_bases(dev
, 1, 0);
871 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
872 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
875 default: /* unknown header */
876 printk(KERN_ERR
"PCI: device %s has unknown header type %02x, ignoring.\n",
877 dev
->slot_name
, dev
->hdr_type
);
881 printk(KERN_ERR
"PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
882 dev
->slot_name
, class, dev
->hdr_type
);
883 dev
->class = PCI_CLASS_NOT_DEFINED
;
886 /* We found a fine healthy device, go go go... */
891 * Read the config data for a PCI device, sanity-check it
892 * and fill in the dev structure...
894 static struct pci_dev
* __init
pci_scan_device(struct pci_dev
*temp
)
899 if (pci_read_config_dword(temp
, PCI_VENDOR_ID
, &l
))
902 /* some broken boards return 0 or ~0 if a slot is empty: */
903 if (l
== 0xffffffff || l
== 0x00000000 || l
== 0x0000ffff || l
== 0xffff0000)
906 dev
= kmalloc(sizeof(*dev
), GFP_KERNEL
);
910 memcpy(dev
, temp
, sizeof(*dev
));
911 dev
->vendor
= l
& 0xffff;
912 dev
->device
= (l
>> 16) & 0xffff;
914 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
915 set this higher, assuming the system even supports it. */
916 dev
->dma_mask
= 0xffffffff;
917 if (pci_setup_device(dev
) < 0) {
924 struct pci_dev
* __init
pci_scan_slot(struct pci_dev
*temp
)
926 struct pci_bus
*bus
= temp
->bus
;
928 struct pci_dev
*first_dev
= NULL
;
933 for (func
= 0; func
< 8; func
++, temp
->devfn
++) {
934 if (func
&& !is_multi
) /* not a multi-function device */
936 if (pci_read_config_byte(temp
, PCI_HEADER_TYPE
, &hdr_type
))
938 temp
->hdr_type
= hdr_type
& 0x7f;
940 dev
= pci_scan_device(temp
);
943 pci_name_device(dev
);
945 is_multi
= hdr_type
& 0x80;
950 * Link the device to both the global PCI device chain and
951 * the per-bus list of devices.
953 list_add_tail(&dev
->global_list
, &pci_devices
);
954 list_add_tail(&dev
->bus_list
, &bus
->devices
);
956 /* Fix up broken headers */
957 pci_fixup_device(PCI_FIXUP_HEADER
, dev
);
962 static unsigned int __init
pci_do_scan_bus(struct pci_bus
*bus
)
964 unsigned int devfn
, max
, pass
;
965 struct list_head
*ln
;
966 struct pci_dev
*dev
, dev0
;
968 DBG("Scanning bus %02x\n", bus
->number
);
969 max
= bus
->secondary
;
971 /* Create a device template */
972 memset(&dev0
, 0, sizeof(dev0
));
974 dev0
.sysdata
= bus
->sysdata
;
976 /* Go find them, Rover! */
977 for (devfn
= 0; devfn
< 0x100; devfn
+= 8) {
979 pci_scan_slot(&dev0
);
983 * After performing arch-dependent fixup of the bus, look behind
984 * all PCI-to-PCI bridges on this bus.
986 DBG("Fixups for bus %02x\n", bus
->number
);
987 pcibios_fixup_bus(bus
);
988 for (pass
=0; pass
< 2; pass
++)
989 for (ln
=bus
->devices
.next
; ln
!= &bus
->devices
; ln
=ln
->next
) {
991 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
|| dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
992 max
= pci_scan_bridge(bus
, dev
, max
, pass
);
996 * We've scanned the bus and so we know all about what's on
997 * the other side of any bridges that may be on this bus plus
1000 * Return how far we've got finding sub-buses.
1002 DBG("Bus scan for %02x returning with max=%02x\n", bus
->number
, max
);
1006 int __init
pci_bus_exists(const struct list_head
*list
, int nr
)
1008 const struct list_head
*l
;
1010 for(l
=list
->next
; l
!= list
; l
= l
->next
) {
1011 const struct pci_bus
*b
= pci_bus_b(l
);
1012 if (b
->number
== nr
|| pci_bus_exists(&b
->children
, nr
))
1018 struct pci_bus
* __init
pci_alloc_primary_bus(int bus
)
1022 if (pci_bus_exists(&pci_root_buses
, bus
)) {
1023 /* If we already got to this bus through a different bridge, ignore it */
1024 DBG("PCI: Bus %02x already known\n", bus
);
1028 b
= pci_alloc_bus();
1029 list_add_tail(&b
->node
, &pci_root_buses
);
1031 b
->number
= b
->secondary
= bus
;
1032 b
->resource
[0] = &ioport_resource
;
1033 b
->resource
[1] = &iomem_resource
;
1037 struct pci_bus
* __init
pci_scan_bus(int bus
, struct pci_ops
*ops
, void *sysdata
)
1039 struct pci_bus
*b
= pci_alloc_primary_bus(bus
);
1041 b
->sysdata
= sysdata
;
1043 b
->subordinate
= pci_do_scan_bus(b
);
1051 * PCI Power management..
1053 * This needs to be done centralized, so that we power manage PCI
1054 * devices in the right order: we should not shut down PCI bridges
1055 * before we've shut down the devices behind them, and we should
1056 * not wake up devices before we've woken up the bridge to the
1059 * We do not touch devices that don't have a driver that exports
1060 * a suspend/resume function. That is just too dangerous. If the default
1061 * PCI suspend/resume functions work for a device, the driver can
1062 * easily implement them (ie just have a suspend function that calls
1063 * the pci_set_power_state() function).
1065 static int pci_pm_suspend_device(struct pci_dev
*dev
)
1068 struct pci_driver
*driver
= dev
->driver
;
1069 if (driver
&& driver
->suspend
)
1070 driver
->suspend(dev
);
1075 static int pci_pm_resume_device(struct pci_dev
*dev
)
1078 struct pci_driver
*driver
= dev
->driver
;
1079 if (driver
&& driver
->resume
)
1080 driver
->resume(dev
);
1085 static int pci_pm_suspend_bus(struct pci_bus
*bus
)
1087 struct list_head
*list
;
1089 /* Walk the bus children list */
1090 list_for_each(list
, &bus
->children
)
1091 pci_pm_suspend_bus(pci_bus_b(list
));
1093 /* Walk the device children list */
1094 list_for_each(list
, &bus
->devices
)
1095 pci_pm_suspend_device(pci_dev_b(list
));
1097 /* Suspend the bus controller.. */
1098 pci_pm_suspend_device(bus
->self
);
1102 static int pci_pm_resume_bus(struct pci_bus
*bus
)
1104 struct list_head
*list
;
1106 pci_pm_resume_device(bus
->self
);
1108 /* Walk the device children list */
1109 list_for_each(list
, &bus
->devices
)
1110 pci_pm_resume_device(pci_dev_b(list
));
1112 /* And then walk the bus children */
1113 list_for_each(list
, &bus
->children
)
1114 pci_pm_resume_bus(pci_bus_b(list
));
1118 static int pci_pm_suspend(void)
1120 struct list_head
*list
;
1122 list_for_each(list
, &pci_root_buses
)
1123 pci_pm_suspend_bus(pci_bus_b(list
));
1127 static int pci_pm_resume(void)
1129 struct list_head
*list
;
1131 list_for_each(list
, &pci_root_buses
)
1132 pci_pm_resume_bus(pci_bus_b(list
));
1136 static int pci_pm_callback(struct pm_dev
*dev
, pm_request_t rqst
, void *data
)
1140 return pci_pm_suspend();
1142 return pci_pm_resume();
1148 void __init
pci_init(void)
1150 struct pci_dev
*dev
;
1154 pci_for_each_dev(dev
) {
1155 pci_fixup_device(PCI_FIXUP_FINAL
, dev
);
1159 pm_register(PM_PCI_DEV
, 0, pci_pm_callback
);
1163 static int __init
pci_setup(char *str
)
1166 char *k
= strchr(str
, ',');
1169 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
1170 /* PCI layer options should be handled here */
1171 printk(KERN_ERR
"PCI: Unknown option `%s'\n", str
);
1178 __setup("pci=", pci_setup
);
1181 EXPORT_SYMBOL(pci_read_config_byte
);
1182 EXPORT_SYMBOL(pci_read_config_word
);
1183 EXPORT_SYMBOL(pci_read_config_dword
);
1184 EXPORT_SYMBOL(pci_write_config_byte
);
1185 EXPORT_SYMBOL(pci_write_config_word
);
1186 EXPORT_SYMBOL(pci_write_config_dword
);
1187 EXPORT_SYMBOL(pci_devices
);
1188 EXPORT_SYMBOL(pci_root_buses
);
1189 EXPORT_SYMBOL(pci_enable_device
);
1190 EXPORT_SYMBOL(pci_find_capability
);
1191 EXPORT_SYMBOL(pci_find_class
);
1192 EXPORT_SYMBOL(pci_find_device
);
1193 EXPORT_SYMBOL(pci_find_slot
);
1194 EXPORT_SYMBOL(pci_find_subsys
);
1195 EXPORT_SYMBOL(pci_set_master
);
1196 EXPORT_SYMBOL(pci_set_power_state
);
1197 EXPORT_SYMBOL(pci_assign_resource
);
1198 EXPORT_SYMBOL(pci_register_driver
);
1199 EXPORT_SYMBOL(pci_unregister_driver
);
1200 EXPORT_SYMBOL(pci_dev_driver
);
1201 EXPORT_SYMBOL(pci_match_device
);
1202 EXPORT_SYMBOL(pci_find_parent_resource
);
1204 #ifdef CONFIG_HOTPLUG
1205 EXPORT_SYMBOL(pci_setup_device
);
1206 EXPORT_SYMBOL(pci_insert_device
);
1207 EXPORT_SYMBOL(pci_remove_device
);
1210 /* Obsolete functions */
1212 EXPORT_SYMBOL(pcibios_present
);
1213 EXPORT_SYMBOL(pcibios_read_config_byte
);
1214 EXPORT_SYMBOL(pcibios_read_config_word
);
1215 EXPORT_SYMBOL(pcibios_read_config_dword
);
1216 EXPORT_SYMBOL(pcibios_write_config_byte
);
1217 EXPORT_SYMBOL(pcibios_write_config_word
);
1218 EXPORT_SYMBOL(pcibios_write_config_dword
);
1219 EXPORT_SYMBOL(pcibios_find_class
);
1220 EXPORT_SYMBOL(pcibios_find_device
);
1224 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
1225 EXPORT_SYMBOL(pci_pci_problems
);