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- David Miller: sparc and net updates. Fix merge_segments.
[davej-history.git] / drivers / ieee1394 / ohci1394.c
blob3b41afb55a2968a27a67be914476aeb602f6b4ed
1 /*
2 * ohci1394.c - driver for OHCI 1394 boards
3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
4 * Gord Peters <GordPeters@smarttech.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 * Things known to be working:
23 * . Async Request Transmit
24 * . Async Response Receive
25 * . Async Request Receive
26 * . Async Response Transmit
27 * . Iso Receive
28 * . DMA mmap for iso receive
29 *
30 * Things not implemented:
31 * . Iso Transmit
32 * . DMA error recovery
33 *
34 * Things to be fixed:
35 * . Config ROM
36 *
37 * Known bugs:
38 * . Self-id are sometimes not received properly
39 * if card is initialized with no other nodes
40 * on the bus
41 * . Apple PowerBook detected but not working yet
42 */
43
44 /*
45 * Acknowledgments:
46 *
47 * Emilie Chung <emilie.chung@axis.com>
48 * . Tip on Async Request Filter
49 * Pascal Drolet <pascal.drolet@informission.ca>
50 * . Various tips for optimization and functionnalities
51 * Robert Ficklin <rficklin@westengineering.com>
52 * . Loop in irq_handler
53 * James Goodwin <jamesg@Filanet.com>
54 * . Various tips on initialization, self-id reception, etc.
55 * Albrecht Dress <ad@mpifr-bonn.mpg.de>
56 * . Apple PowerBook detection
57 * Daniel Kobras <daniel.kobras@student.uni-tuebingen.de>
58 * . Reset the board properly before leaving + misc cleanups
59 * Leon van Stuivenberg <leonvs@iae.nl>
60 * . Bug fixes
61 */
62
63 #include <linux/config.h>
64 #include <linux/kernel.h>
65 #include <linux/slab.h>
66 #include <linux/interrupt.h>
67 #include <linux/wait.h>
68 #include <linux/errno.h>
69 #include <linux/module.h>
70 #include <linux/pci.h>
71 #include <linux/fs.h>
72 #include <linux/poll.h>
73 #include <asm/byteorder.h>
74 #include <asm/atomic.h>
75 #include <asm/io.h>
76 #include <asm/uaccess.h>
77 #include <linux/proc_fs.h>
78 #include <linux/tqueue.h>
79 #include <linux/delay.h>
80
81 #include <asm/pgtable.h>
82 #include <asm/page.h>
83 #include <linux/sched.h>
84 #include <asm/segment.h>
85 #include <linux/types.h>
86 #include <linux/wrapper.h>
87 #include <linux/vmalloc.h>
88
89 #include "ieee1394.h"
90 #include "ieee1394_types.h"
91 #include "hosts.h"
92 #include "ieee1394_core.h"
93 #include "ohci1394.h"
94
95 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
96 #define OHCI1394_DEBUG
97 #endif
98
99 #ifdef DBGMSG
100 #undef DBGMSG
101 #endif
102
103 #ifdef OHCI1394_DEBUG
104 #define DBGMSG(card, fmt, args...) \
105 printk(KERN_INFO "ohci1394_%d: " fmt "\n" , card , ## args)
106 #else
107 #define DBGMSG(card, fmt, args...)
108 #endif
109
110 /* print general (card independent) information */
111 #define PRINT_G(level, fmt, args...) \
112 printk(level "ohci1394: " fmt "\n" , ## args)
113
114 /* print card specific information */
115 #define PRINT(level, card, fmt, args...) \
116 printk(level "ohci1394_%d: " fmt "\n" , card , ## args)
117
118 #define FAIL(fmt, args...) \
119 PRINT_G(KERN_ERR, fmt , ## args); \
120 num_of_cards--; \
121 remove_card(ohci); \
122 return 1;
123
124 int supported_chips[][2] = {
125 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_OHCI1394_LV22 },
126 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_OHCI1394_LV23 },
127 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_OHCI1394_LV26 },
128 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_OHCI1394 },
129 { PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_CXD3222 },
130 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_UPD72862 },
131 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_UPD72870 },
132 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_UPD72871 },
133 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW },
134 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_ALI_OHCI1394_M5251 },
135 { PCI_VENDOR_ID_LUCENT, PCI_DEVICE_ID_LUCENT_FW323 },
136 { -1, -1 }
137 };
138
139 static struct ti_ohci cards[MAX_OHCI1394_CARDS];
140 static int num_of_cards = 0;
141
142 static int add_card(struct pci_dev *dev);
143 static void remove_card(struct ti_ohci *ohci);
144 static int init_driver(void);
145 static void dma_trm_bh(void *data);
146 static void dma_rcv_bh(void *data);
147 static void dma_trm_reset(struct dma_trm_ctx *d);
148
149 /***********************************
150 * IEEE-1394 functionality section *
151 ***********************************/
152
153 #if 0 /* not needed at this time */
154 static int get_phy_reg(struct ti_ohci *ohci, int addr)
155 {
156 int timeout=10000;
157 static quadlet_t r;
158
159 if ((addr < 1) || (addr > 15)) {
160 PRINT(KERN_ERR, ohci->id, __FUNCTION__
161 ": PHY register address %d out of range", addr);
162 return -EFAULT;
163 }
164
165 spin_lock(&ohci->phy_reg_lock);
166
167 /* initiate read request */
168 reg_write(ohci, OHCI1394_PhyControl,
169 ((addr<<8)&0x00000f00) | 0x00008000);
170
171 /* wait */
172 while (!(reg_read(ohci, OHCI1394_PhyControl)&0x80000000) && timeout)
173 timeout--;
174
175
176 if (!timeout) {
177 PRINT(KERN_ERR, ohci->id, "get_phy_reg timeout !!!\n");
178 spin_unlock(&ohci->phy_reg_lock);
179 return -EFAULT;
180 }
181 r = reg_read(ohci, OHCI1394_PhyControl);
182
183 spin_unlock(&ohci->phy_reg_lock);
184
185 return (r&0x00ff0000)>>16;
186 }
187
188 static int set_phy_reg(struct ti_ohci *ohci, int addr, unsigned char data) {
189 int timeout=10000;
190 u32 r;
191
192 if ((addr < 1) || (addr > 15)) {
193 PRINT(KERN_ERR, ohci->id, __FUNCTION__
194 ": PHY register address %d out of range", addr);
195 return -EFAULT;
196 }
197
198 r = ((addr<<8)&0x00000f00) | 0x00004000 | ((u32)data & 0x000000ff);
199
200 spin_lock(&ohci->phy_reg_lock);
201
202 reg_write(ohci, OHCI1394_PhyControl, r);
203
204 /* wait */
205 while (!(reg_read(ohci, OHCI1394_PhyControl)&0x80000000) && timeout)
206 timeout--;
207
208 spin_unlock(&ohci->phy_reg_lock);
209
210 if (!timeout) {
211 PRINT(KERN_ERR, ohci->id, "set_phy_reg timeout !!!\n");
212 return -EFAULT;
213 }
214
215 return 0;
216 }
217 #endif /* unneeded functions */
218
219 inline static int handle_selfid(struct ti_ohci *ohci, struct hpsb_host *host,
220 int phyid, int isroot)
221 {
222 quadlet_t *q = ohci->selfid_buf_cpu;
223 quadlet_t self_id_count=reg_read(ohci, OHCI1394_SelfIDCount);
224 size_t size;
225 quadlet_t lsid;
226
227 /* Self-id handling seems much easier than for the aic5800 chip.
228 All the self-id packets, including this device own self-id,
229 should be correctly arranged in the selfid buffer at this
230 stage */
231
232 /* Check status of self-id reception */
233 if ((self_id_count&0x80000000) ||
234 ((self_id_count&0x00FF0000) != (q[0]&0x00FF0000))) {
235 PRINT(KERN_ERR, ohci->id,
236 "Error in reception of self-id packets"
237 "Self-id count: %08x q[0]: %08x",
238 self_id_count, q[0]);
239
240 /*
241 * Tip by James Goodwin <jamesg@Filanet.com>:
242 * We had an error, generate another bus reset in response.
243 * TODO. Actually read the current value in the phy before
244 * generating a bus reset (read modify write). This way
245 * we don't stomp any current gap count settings, etc.
246 */
247 if (ohci->self_id_errors<OHCI1394_MAX_SELF_ID_ERRORS) {
248 reg_write(ohci, OHCI1394_PhyControl, 0x000041ff);
249 ohci->self_id_errors++;
250 }
251 else {
252 PRINT(KERN_ERR, ohci->id,
253 "Timeout on self-id error reception");
254 }
255 return -1;
256 }
257
258 size = ((self_id_count&0x00001FFC)>>2) - 1;
259 q++;
260
261 while (size > 0) {
262 if (q[0] == ~q[1]) {
263 PRINT(KERN_INFO, ohci->id, "selfid packet 0x%x rcvd",
264 q[0]);
265 hpsb_selfid_received(host, cpu_to_be32(q[0]));
266 if (((q[0]&0x3f000000)>>24)==phyid) {
267 lsid=q[0];
268 PRINT(KERN_INFO, ohci->id,
269 "This node self-id is 0x%08x", lsid);
270 }
271 } else {
272 PRINT(KERN_ERR, ohci->id,
273 "inconsistent selfid 0x%x/0x%x", q[0], q[1]);
274 }
275 q += 2;
276 size -= 2;
277 }
278
279 PRINT(KERN_INFO, ohci->id, "calling self-id complete");
280
281 hpsb_selfid_complete(host, phyid, isroot);
282 return 0;
283 }
284
285 static int ohci_detect(struct hpsb_host_template *tmpl)
286 {
287 struct hpsb_host *host;
288 int i;
289
290 init_driver();
291
292 for (i = 0; i < num_of_cards; i++) {
293 host = hpsb_get_host(tmpl, 0);
294 if (host == NULL) {
295 /* simply don't init more after out of mem */
296 return i;
297 }
298 host->hostdata = &cards[i];
299 cards[i].host = host;
300 }
301
302 return num_of_cards;
303 }
304
305 static int ohci_soft_reset(struct ti_ohci *ohci) {
306 int timeout=10000;
307
308 reg_write(ohci, OHCI1394_HCControlSet, 0x00010000);
309
310 while ((reg_read(ohci, OHCI1394_HCControlSet)&0x00010000) && timeout)
311 timeout--;
312 if (!timeout) {
313 PRINT(KERN_ERR, ohci->id, "soft reset timeout !!!");
314 return -EFAULT;
315 }
316 else PRINT(KERN_INFO, ohci->id, "soft reset finished");
317 return 0;
318 }
319
320 static int run_context(struct ti_ohci *ohci, int reg, char *msg)
321 {
322 u32 nodeId;
323
324 /* check that the node id is valid */
325 nodeId = reg_read(ohci, OHCI1394_NodeID);
326 if (!(nodeId&0x80000000)) {
327 PRINT(KERN_ERR, ohci->id,
328 "Running dma failed because Node ID not valid");
329 return -1;
330 }
331
332 /* check that the node number != 63 */
333 if ((nodeId&0x3f)==63) {
334 PRINT(KERN_ERR, ohci->id,
335 "Running dma failed because Node ID == 63");
336 return -1;
337 }
338
339 /* Run the dma context */
340 reg_write(ohci, reg, 0x8000);
341
342 if (msg) PRINT(KERN_INFO, ohci->id, "%s", msg);
343
344 return 0;
345 }
346
347 /* Generate the dma receive prgs and start the context */
348 static void initialize_dma_rcv_ctx(struct dma_rcv_ctx *d)
349 {
350 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
351 int i;
352
353 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
354
355 for (i=0; i<d->num_desc; i++) {
356
357 /* end of descriptor list? */
358 if ((i+1) < d->num_desc) {
359 d->prg_cpu[i]->control = (0x283C << 16) | d->buf_size;
360 d->prg_cpu[i]->branchAddress =
361 (d->prg_bus[i+1] & 0xfffffff0) | 0x1;
362 } else {
363 d->prg_cpu[i]->control = (0x283C << 16) | d->buf_size;
364 d->prg_cpu[i]->branchAddress =
365 d->prg_bus[0] & 0xfffffff0;
366 }
367
368 d->prg_cpu[i]->address = d->buf_bus[i];
369 d->prg_cpu[i]->status = d->buf_size;
370 }
371
372 d->buf_ind = 0;
373 d->buf_offset = 0;
374
375 /* Tell the controller where the first AR program is */
376 reg_write(ohci, d->cmdPtr, d->prg_bus[0] | 0x1);
377
378 /* Run AR context */
379 reg_write(ohci, d->ctrlSet, 0x00008000);
380
381 PRINT(KERN_INFO, ohci->id, "Receive DMA ctx=%d initialized", d->ctx);
382 }
383
384 /* Initialize the dma transmit context */
385 static void initialize_dma_trm_ctx(struct dma_trm_ctx *d)
386 {
387 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
388
389 /* Stop the context */
390 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
391
392 d->prg_ind = 0;
393 d->sent_ind = 0;
394 d->free_prgs = d->num_desc;
395 d->branchAddrPtr = NULL;
396 d->fifo_first = NULL;
397 d->fifo_last = NULL;
398 d->pending_first = NULL;
399 d->pending_last = NULL;
400
401 PRINT(KERN_INFO, ohci->id, "AT dma ctx=%d initialized", d->ctx);
402 }
403
404 /* Count the number of available iso contexts */
405 static int get_nb_iso_ctx(struct ti_ohci *ohci, int reg)
406 {
407 int i,ctx=0;
408 u32 tmp;
409
410 reg_write(ohci, reg, 0xffffffff);
411 tmp = reg_read(ohci, reg);
412
413 DBGMSG(ohci->id,"Iso contexts reg: %08x implemented: %08x", reg, tmp);
414
415 /* Count the number of contexts */
416 for(i=0; i<32; i++) {
417 if(tmp & 1) ctx++;
418 tmp >>= 1;
419 }
420 return ctx;
421 }
422
423 /* Global initialization */
424 static int ohci_initialize(struct hpsb_host *host)
425 {
426 struct ti_ohci *ohci=host->hostdata;
427 int retval, i;
428
429 spin_lock_init(&ohci->phy_reg_lock);
430
431 /*
432 * Tip by James Goodwin <jamesg@Filanet.com>:
433 * We need to add delays after the soft reset, setting LPS, and
434 * enabling our link. This might fixes the self-id reception
435 * problem at initialization.
436 */
437
438 /* Soft reset */
439 if ((retval=ohci_soft_reset(ohci))<0) return retval;
440
441 /*
442 * Delay after soft reset to make sure everything has settled
443 * down (sanity)
444 */
445 mdelay(100);
446
447 /* Set Link Power Status (LPS) */
448 reg_write(ohci, OHCI1394_HCControlSet, 0x00080000);
449
450 /*
451 * Delay after setting LPS in order to make sure link/phy
452 * communication is established
453 */
454 mdelay(100);
455
456 /* Set the bus number */
457 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
458
459 /* Enable posted writes */
460 reg_write(ohci, OHCI1394_HCControlSet, 0x00040000);
461
462 /* Clear link control register */
463 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
464
465 /* Enable cycle timer and cycle master */
466 reg_write(ohci, OHCI1394_LinkControlSet, 0x00300000);
467
468 /* Clear interrupt registers */
469 reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
470 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
471
472 /* Set up self-id dma buffer */
473 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus);
474
475 /* enable self-id dma */
476 reg_write(ohci, OHCI1394_LinkControlSet, 0x00000200);
477
478 /* Set the configuration ROM mapping register */
479 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus);
480
481 /* Set bus options */
482 reg_write(ohci, OHCI1394_BusOptions,
483 cpu_to_be32(ohci->csr_config_rom_cpu[2]));
484
485 #if 0
486 /* Write the GUID into the csr config rom */
487 ohci->csr_config_rom_cpu[3] =
488 be32_to_cpu(reg_read(ohci, OHCI1394_GUIDHi));
489 ohci->csr_config_rom_cpu[4] =
490 be32_to_cpu(reg_read(ohci, OHCI1394_GUIDLo));
491 #endif
492
493 /* Write the config ROM header */
494 reg_write(ohci, OHCI1394_ConfigROMhdr,
495 cpu_to_be32(ohci->csr_config_rom_cpu[0]));
496
497 ohci->max_packet_size =
498 1<<(((reg_read(ohci, OHCI1394_BusOptions)>>12)&0xf)+1);
499 PRINT(KERN_INFO, ohci->id, "max packet size = %d bytes",
500 ohci->max_packet_size);
501
502 /* Don't accept phy packets into AR request context */
503 reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);
504
505 /* Initialize IR dma */
506 ohci->nb_iso_rcv_ctx =
507 get_nb_iso_ctx(ohci, OHCI1394_IsoRecvIntMaskSet);
508 PRINT(KERN_INFO, ohci->id, "%d iso receive contexts available",
509 ohci->nb_iso_rcv_ctx);
510 for (i=0;i<ohci->nb_iso_rcv_ctx;i++) {
511 reg_write(ohci, OHCI1394_IsoRcvContextControlClear+32*i,
512 0xffffffff);
513 reg_write(ohci, OHCI1394_IsoRcvContextMatch+32*i, 0);
514 reg_write(ohci, OHCI1394_IsoRcvCommandPtr+32*i, 0);
515 }
516
517 /* Set bufferFill, isochHeader, multichannel for IR context */
518 reg_write(ohci, OHCI1394_IsoRcvContextControlSet, 0xd0000000);
519
520 /* Set the context match register to match on all tags */
521 reg_write(ohci, OHCI1394_IsoRcvContextMatch, 0xf0000000);
522
523 /* Clear the interrupt mask */
524 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
525 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
526
527 /* Initialize IT dma */
528 ohci->nb_iso_xmit_ctx =
529 get_nb_iso_ctx(ohci, OHCI1394_IsoXmitIntMaskSet);
530 PRINT(KERN_INFO, ohci->id, "%d iso transmit contexts available",
531 ohci->nb_iso_xmit_ctx);
532 for (i=0;i<ohci->nb_iso_xmit_ctx;i++) {
533 reg_write(ohci, OHCI1394_IsoXmitContextControlClear+32*i,
534 0xffffffff);
535 reg_write(ohci, OHCI1394_IsoXmitCommandPtr+32*i, 0);
536 }
537
538 /* Clear the interrupt mask */
539 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
540 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
541
542 /* Clear the multi channel mask high and low registers */
543 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 0xffffffff);
544 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 0xffffffff);
545
546 /* Initialize AR dma */
547 initialize_dma_rcv_ctx(ohci->ar_req_context);
548 initialize_dma_rcv_ctx(ohci->ar_resp_context);
549
550 /* Initialize AT dma */
551 initialize_dma_trm_ctx(ohci->at_req_context);
552 initialize_dma_trm_ctx(ohci->at_resp_context);
553
554 /* Initialize IR dma */
555 initialize_dma_rcv_ctx(ohci->ir_context);
556
557 /* Set up isoRecvIntMask to generate interrupts for context 0
558 (thanks to Michael Greger for seeing that I forgot this) */
559 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 0x00000001);
560
561 /*
562 * Accept AT requests from all nodes. This probably
563 * will have to be controlled from the subsystem
564 * on a per node basis.
565 */
566 reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0x80000000);
567
568 /* Specify AT retries */
569 reg_write(ohci, OHCI1394_ATRetries,
570 OHCI1394_MAX_AT_REQ_RETRIES |
571 (OHCI1394_MAX_AT_RESP_RETRIES<<4) |
572 (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
573
574 #ifndef __BIG_ENDIAN
575 reg_write(ohci, OHCI1394_HCControlClear, 0x40000000);
576 #else
577 reg_write(ohci, OHCI1394_HCControlSet, 0x40000000);
578 #endif
579
580 /* Enable interrupts */
581 reg_write(ohci, OHCI1394_IntMaskSet,
582 OHCI1394_masterIntEnable |
583 OHCI1394_phyRegRcvd |
584 OHCI1394_busReset |
585 OHCI1394_selfIDComplete |
586 OHCI1394_RSPkt |
587 OHCI1394_RQPkt |
588 OHCI1394_ARRS |
589 OHCI1394_ARRQ |
590 OHCI1394_respTxComplete |
591 OHCI1394_reqTxComplete |
592 OHCI1394_isochRx |
593 OHCI1394_isochTx
594 );
595
596 /* Enable link */
597 reg_write(ohci, OHCI1394_HCControlSet, 0x00020000);
598
599 return 1;
600 }
601
602 static void ohci_remove(struct hpsb_host *host)
603 {
604 struct ti_ohci *ohci;
605
606 if (host != NULL) {
607 ohci = host->hostdata;
608 remove_card(ohci);
609 }
610 }
611
612 /*
613 * Insert a packet in the AT DMA fifo and generate the DMA prg
614 * FIXME: rewrite the program in order to accept packets crossing
615 * page boundaries.
616 * check also that a single dma descriptor doesn't cross a
617 * page boundary.
618 */
619 static void insert_packet(struct ti_ohci *ohci,
620 struct dma_trm_ctx *d, struct hpsb_packet *packet)
621 {
622 u32 cycleTimer;
623 int idx = d->prg_ind;
624
625 d->prg_cpu[idx]->begin.address = 0;
626 d->prg_cpu[idx]->begin.branchAddress = 0;
627 if (d->ctx==1) {
628 /*
629 * For response packets, we need to put a timeout value in
630 * the 16 lower bits of the status... let's try 1 sec timeout
631 */
632 cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
633 d->prg_cpu[idx]->begin.status =
634 (((((cycleTimer>>25)&0x7)+1)&0x7)<<13) |
635 ((cycleTimer&0x01fff000)>>12);
636
637 DBGMSG(ohci->id, "cycleTimer: %08x timeStamp: %08x",
638 cycleTimer, d->prg_cpu[idx]->begin.status);
639 }
640 else
641 d->prg_cpu[idx]->begin.status = 0;
642
643 d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
644 (packet->header[0] & 0xFFFF);
645 d->prg_cpu[idx]->data[1] = (packet->header[1] & 0xFFFF) |
646 (packet->header[0] & 0xFFFF0000);
647 d->prg_cpu[idx]->data[2] = packet->header[2];
648 d->prg_cpu[idx]->data[3] = packet->header[3];
649
650 if (packet->data_size) { /* block transmit */
651 d->prg_cpu[idx]->begin.control = OUTPUT_MORE_IMMEDIATE | 0x10;
652 d->prg_cpu[idx]->end.control = OUTPUT_LAST | packet->data_size;
653 /*
654 * FIXME: check that the packet data buffer
655 * do not cross a page boundary
656 */
657 if (cross_bound((unsigned long)packet->data,
658 packet->data_size)>0) {
659 /* FIXME: do something about it */
660 PRINT(KERN_ERR, ohci->id, __FUNCTION__
661 ": packet data addr: %p size %d bytes "
662 "cross page boundary",
663 packet->data, packet->data_size);
664 }
665
666 d->prg_cpu[idx]->end.address =
667 pci_map_single(ohci->dev, packet->data,
668 packet->data_size, PCI_DMA_TODEVICE);
669 d->prg_cpu[idx]->end.branchAddress = 0;
670 d->prg_cpu[idx]->end.status = 0;
671 if (d->branchAddrPtr)
672 *(d->branchAddrPtr) = d->prg_bus[idx] | 0x3;
673 d->branchAddrPtr = &(d->prg_cpu[idx]->end.branchAddress);
674 }
675 else { /* quadlet transmit */
676 d->prg_cpu[idx]->begin.control =
677 OUTPUT_LAST_IMMEDIATE | packet->header_size;
678 if (d->branchAddrPtr)
679 *(d->branchAddrPtr) = d->prg_bus[idx] | 0x2;
680 d->branchAddrPtr = &(d->prg_cpu[idx]->begin.branchAddress);
681 }
682 d->free_prgs--;
683
684 /* queue the packet in the appropriate context queue */
685 if (d->fifo_last) {
686 d->fifo_last->xnext = packet;
687 d->fifo_last = packet;
688 }
689 else {
690 d->fifo_first = packet;
691 d->fifo_last = packet;
692 }
693 d->prg_ind = (d->prg_ind+1)%d->num_desc;
694 }
695
696 /*
697 * This function fills the AT FIFO with the (eventual) pending packets
698 * and runs or wake up the AT DMA prg if necessary.
699 * The function MUST be called with the d->lock held.
700 */
701 static int dma_trm_flush(struct ti_ohci *ohci, struct dma_trm_ctx *d)
702 {
703 int idx,z;
704
705 if (d->pending_first == NULL || d->free_prgs == 0)
706 return 0;
707
708 idx = d->prg_ind;
709 z = (d->pending_first->data_size) ? 3 : 2;
710
711 /* insert the packets into the at dma fifo */
712 while (d->free_prgs>0 && d->pending_first) {
713 insert_packet(ohci, d, d->pending_first);
714 d->pending_first = d->pending_first->xnext;
715 }
716 if (d->pending_first == NULL)
717 d->pending_last = NULL;
718 else
719 PRINT(KERN_INFO, ohci->id,
720 "AT DMA FIFO ctx=%d full... waiting",d->ctx);
721
722 /* Is the context running ? (should be unless it is
723 the first packet to be sent in this context) */
724 if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) {
725 DBGMSG(ohci->id,"Starting AT DMA ctx=%d",d->ctx);
726 reg_write(ohci, d->cmdPtr, d->prg_bus[idx]|z);
727 run_context(ohci, d->ctrlSet, NULL);
728 }
729 else {
730 DBGMSG(ohci->id,"Waking AT DMA ctx=%d",d->ctx);
731 /* wake up the dma context if necessary */
732 if (!(reg_read(ohci, d->ctrlSet) & 0x400))
733 reg_write(ohci, d->ctrlSet, 0x1000);
734 }
735 return 1;
736 }
737
738 /*
739 * Transmission of an async packet
740 */
741 static int ohci_transmit(struct hpsb_host *host, struct hpsb_packet *packet)
742 {
743 struct ti_ohci *ohci = host->hostdata;
744 struct dma_trm_ctx *d;
745 unsigned char tcode;
746 unsigned long flags;
747
748 if (packet->data_size > ohci->max_packet_size) {
749 PRINT(KERN_ERR, ohci->id,
750 "transmit packet size = %d too big",
751 packet->data_size);
752 return 0;
753 }
754 packet->xnext = NULL;
755
756 /* Decide wether we have a request or a response packet */
757 tcode = (packet->header[0]>>4)&0xf;
758 if (tcode & 0x02) d = ohci->at_resp_context;
759 else d = ohci->at_req_context;
760
761 spin_lock_irqsave(&d->lock,flags);
762
763 /* queue the packet for later insertion into to dma fifo */
764 if (d->pending_last) {
765 d->pending_last->xnext = packet;
766 d->pending_last = packet;
767 }
768 else {
769 d->pending_first = packet;
770 d->pending_last = packet;
771 }
772
773 dma_trm_flush(ohci, d);
774
775 spin_unlock_irqrestore(&d->lock,flags);
776
777 return 1;
778 }
779
780 static int ohci_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg)
781 {
782 struct ti_ohci *ohci = host->hostdata;
783 int retval = 0;
784 unsigned long flags;
785
786 switch (cmd) {
787 case RESET_BUS:
788 /*
789 * FIXME: this flag might be necessary in some case
790 */
791 /* host->attempt_root = 1; */
792 PRINT(KERN_INFO, ohci->id, "resetting bus on request%s",
793 (host->attempt_root ? " and attempting to become root"
794 : ""));
795 reg_write(ohci, OHCI1394_PhyControl,
796 (host->attempt_root) ? 0x000041ff : 0x0000417f);
797 break;
798
799 case GET_CYCLE_COUNTER:
800 retval = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
801 break;
802
803 case SET_CYCLE_COUNTER:
804 reg_write(ohci, OHCI1394_IsochronousCycleTimer, arg);
805 break;
806
807 case SET_BUS_ID:
808 PRINT(KERN_ERR, ohci->id, "devctl command SET_BUS_ID err");
809 break;
810
811 case ACT_CYCLE_MASTER:
812 if (arg) {
813 /* check if we are root and other nodes are present */
814 u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
815 if ((nodeId & (1<<30)) && (nodeId & 0x3f)) {
816 /*
817 * enable cycleTimer, cycleMaster
818 */
819 DBGMSG(ohci->id, "Cycle master enabled");
820 reg_write(ohci, OHCI1394_LinkControlSet,
821 0x00300000);
822 }
823 } else {
824 /* disable cycleTimer, cycleMaster, cycleSource */
825 reg_write(ohci, OHCI1394_LinkControlClear, 0x00700000);
826 }
827 break;
828
829 case CANCEL_REQUESTS:
830 DBGMSG(ohci->id, "Cancel request received");
831 dma_trm_reset(ohci->at_req_context);
832 dma_trm_reset(ohci->at_resp_context);
833 break;
834
835 case MODIFY_USAGE:
836 if (arg) {
837 MOD_INC_USE_COUNT;
838 } else {
839 MOD_DEC_USE_COUNT;
840 }
841 break;
842
843 case ISO_LISTEN_CHANNEL:
844 {
845 int *isochannels, offset= OHCI1394_IRMultiChanMaskLoSet;
846 unsigned int channel= (unsigned int)arg;
847 unsigned int channelbit= channel;
848 u32 setMask= 0x00000001;
849
850 /* save people from themselves */
851 if (channel > 63)
852 break;
853
854 if (channel > 31) {
855 isochannels= &(((int*)&ohci->IR_channel_usage)[0]);
856 channelbit-= 32;
857 offset= OHCI1394_IRMultiChanMaskHiSet;
858 }
859 else
860 isochannels= &(((int*)&ohci->IR_channel_usage)[1]);
861
862 while(channelbit--) setMask= setMask << 1;
863
864 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
865
866 if (!test_and_set_bit(channelbit, isochannels))
867 reg_write(ohci, offset, setMask);
868
869 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
870 DBGMSG(ohci->id, "listening enabled on channel %u", channel);
871 break;
872 }
873 case ISO_UNLISTEN_CHANNEL:
874 {
875 int *isochannels, offset= OHCI1394_IRMultiChanMaskLoClear;
876 unsigned int channel= (unsigned int)arg;
877 unsigned int channelbit= channel;
878 u32 clearMask= 0x00000001;
879
880 /* save people from themselves */
881 if (channel > 63)
882 break;
883
884 if (channel > 31) {
885 isochannels= &(((int*)&ohci->IR_channel_usage)[0]);
886 channelbit-= 32;
887 offset= OHCI1394_IRMultiChanMaskHiClear;
888 }
889 else
890 isochannels= &(((int*)&ohci->IR_channel_usage)[1]);
891
892 while(channelbit--) clearMask= clearMask << 1;
893
894 spin_lock_irqsave(&ohci->IR_channel_lock, flags);
895
896 if (!test_and_clear_bit(channelbit, isochannels))
897 reg_write(ohci, offset, clearMask);
898
899 spin_unlock_irqrestore(&ohci->IR_channel_lock, flags);
900 DBGMSG(ohci->id, "listening disabled on channel %u", channel);
901 break;
902 }
903 default:
904 PRINT_G(KERN_ERR, "ohci_devctl cmd %d not implemented yet",
905 cmd);
906 break;
907 }
908 return retval;
909 }
910
911 /***************************************
912 * IEEE-1394 functionality section END *
913 ***************************************/
914
915
916 /********************************************************
917 * Global stuff (interrupt handler, init/shutdown code) *
918 ********************************************************/
919
920 static void dma_trm_reset(struct dma_trm_ctx *d)
921 {
922 struct ti_ohci *ohci;
923 unsigned long flags;
924 struct hpsb_packet *nextpacket;
925
926 if (d==NULL) {
927 PRINT_G(KERN_ERR, "dma_trm_reset called with NULL arg");
928 return;
929 }
930 ohci = (struct ti_ohci *)(d->ohci);
931 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
932
933 spin_lock_irqsave(&d->lock,flags);
934
935 /* is there still any packet pending in the fifo ? */
936 while(d->fifo_first) {
937 PRINT(KERN_INFO, ohci->id,
938 "AT dma reset ctx=%d, aborting transmission",
939 d->ctx);
940 nextpacket = d->fifo_first->xnext;
941 hpsb_packet_sent(ohci->host, d->fifo_first, ACKX_ABORTED);
942 d->fifo_first = nextpacket;
943 }
944 d->fifo_first = d->fifo_last = NULL;
945
946 /* is there still any packet pending ? */
947 while(d->pending_first) {
948 PRINT(KERN_INFO, ohci->id,
949 "AT dma reset ctx=%d, aborting transmission",
950 d->ctx);
951 nextpacket = d->pending_first->xnext;
952 hpsb_packet_sent(ohci->host, d->pending_first,
953 ACKX_ABORTED);
954 d->pending_first = nextpacket;
955 }
956 d->pending_first = d->pending_last = NULL;
957
958 d->branchAddrPtr=NULL;
959 d->sent_ind = d->prg_ind;
960 d->free_prgs = d->num_desc;
961 spin_unlock_irqrestore(&d->lock,flags);
962 }
963
964 static void ohci_irq_handler(int irq, void *dev_id,
965 struct pt_regs *regs_are_unused)
966 {
967 quadlet_t event,node_id;
968 struct ti_ohci *ohci = (struct ti_ohci *)dev_id;
969 struct hpsb_host *host = ohci->host;
970 int phyid = -1, isroot = 0;
971 int timeout = 255;
972
973 do {
974 /* read the interrupt event register */
975 event=reg_read(ohci, OHCI1394_IntEventClear);
976
977 if (!event) return;
978
979 DBGMSG(ohci->id, "IntEvent: %08x",event);
980
981 /* clear the interrupt event register */
982 reg_write(ohci, OHCI1394_IntEventClear, event);
983
984 if (event & OHCI1394_busReset) {
985 if (!host->in_bus_reset) {
986 PRINT(KERN_INFO, ohci->id, "Bus reset");
987
988 /* Wait for the AT fifo to be flushed */
989 dma_trm_reset(ohci->at_req_context);
990 dma_trm_reset(ohci->at_resp_context);
991
992 /* Subsystem call */
993 hpsb_bus_reset(ohci->host);
994
995 ohci->NumBusResets++;
996 }
997 }
998 /*
999 * Problem: How can I ensure that the AT bottom half will be
1000 * executed before the AR bottom half (both events may have
1001 * occured within a single irq event)
1002 * Quick hack: just launch it within the IRQ handler
1003 */
1004 if (event & OHCI1394_reqTxComplete) {
1005 struct dma_trm_ctx *d = ohci->at_req_context;
1006 DBGMSG(ohci->id, "Got reqTxComplete interrupt "
1007 "status=0x%08X", reg_read(ohci, d->ctrlSet));
1008 if (reg_read(ohci, d->ctrlSet) & 0x800)
1009 ohci1394_stop_context(ohci, d->ctrlClear,
1010 "reqTxComplete");
1011 else
1012 dma_trm_bh((void *)d);
1013 }
1014 if (event & OHCI1394_respTxComplete) {
1015 struct dma_trm_ctx *d = ohci->at_resp_context;
1016 DBGMSG(ohci->id, "Got respTxComplete interrupt "
1017 "status=0x%08X", reg_read(ohci, d->ctrlSet));
1018 if (reg_read(ohci, d->ctrlSet) & 0x800)
1019 ohci1394_stop_context(ohci, d->ctrlClear,
1020 "respTxComplete");
1021 else
1022 dma_trm_bh((void *)d);
1023 }
1024 if (event & OHCI1394_RQPkt) {
1025 struct dma_rcv_ctx *d = ohci->ar_req_context;
1026 DBGMSG(ohci->id, "Got RQPkt interrupt status=0x%08X",
1027 reg_read(ohci, d->ctrlSet));
1028 if (reg_read(ohci, d->ctrlSet) & 0x800)
1029 ohci1394_stop_context(ohci, d->ctrlClear, "RQPkt");
1030 else {
1031 #if IEEE1394_USE_BOTTOM_HALVES
1032 queue_task(&d->task, &tq_immediate);
1033 mark_bh(IMMEDIATE_BH);
1034 #else
1035 dma_rcv_bh((void *)d);
1036 #endif
1037 }
1038 }
1039 if (event & OHCI1394_RSPkt) {
1040 struct dma_rcv_ctx *d = ohci->ar_resp_context;
1041 DBGMSG(ohci->id, "Got RSPkt interrupt status=0x%08X",
1042 reg_read(ohci, d->ctrlSet));
1043 if (reg_read(ohci, d->ctrlSet) & 0x800)
1044 ohci1394_stop_context(ohci, d->ctrlClear, "RSPkt");
1045 else {
1046 #if IEEE1394_USE_BOTTOM_HALVES
1047 queue_task(&d->task, &tq_immediate);
1048 mark_bh(IMMEDIATE_BH);
1049 #else
1050 dma_rcv_bh((void *)d);
1051 #endif
1052 }
1053 }
1054 if (event & OHCI1394_isochRx) {
1055 quadlet_t isoRecvIntEvent;
1056 struct dma_rcv_ctx *d = ohci->ir_context;
1057 isoRecvIntEvent =
1058 reg_read(ohci, OHCI1394_IsoRecvIntEventSet);
1059 reg_write(ohci, OHCI1394_IsoRecvIntEventClear,
1060 isoRecvIntEvent);
1061 DBGMSG(ohci->id, "Got isochRx interrupt "
1062 "status=0x%08X isoRecvIntEvent=%08x",
1063 reg_read(ohci, d->ctrlSet), isoRecvIntEvent);
1064 if (isoRecvIntEvent & 0x1) {
1065 if (reg_read(ohci, d->ctrlSet) & 0x800)
1066 ohci1394_stop_context(ohci, d->ctrlClear,
1067 "isochRx");
1068 else {
1069 #if IEEE1394_USE_BOTTOM_HALVES
1070 queue_task(&d->task, &tq_immediate);
1071 mark_bh(IMMEDIATE_BH);
1072 #else
1073 dma_rcv_bh((void *)d);
1074 #endif
1075 }
1076 }
1077 if (ohci->video_tmpl)
1078 ohci->video_tmpl->irq_handler(ohci->id,
1079 isoRecvIntEvent,
1080 0);
1081 }
1082 if (event & OHCI1394_isochTx) {
1083 quadlet_t isoXmitIntEvent;
1084 isoXmitIntEvent =
1085 reg_read(ohci, OHCI1394_IsoXmitIntEventSet);
1086 reg_write(ohci, OHCI1394_IsoXmitIntEventClear,
1087 isoXmitIntEvent);
1088 DBGMSG(ohci->id, "Got isochTx interrupt");
1089 if (ohci->video_tmpl)
1090 ohci->video_tmpl->irq_handler(ohci->id, 0,
1091 isoXmitIntEvent);
1092 }
1093 if (event & OHCI1394_selfIDComplete) {
1094 if (host->in_bus_reset) {
1095 /*
1096 * Begin Fix (JSG): Check to make sure our
1097 * node id is valid
1098 */
1099 node_id = reg_read(ohci, OHCI1394_NodeID);
1100 if (!(node_id & 0x80000000)) {
1101 mdelay(1); /* phy is upset -
1102 * this happens once in
1103 * a while on hot-plugs...
1104 * give it a ms to recover
1105 */
1106 }
1107 /* End Fix (JSG) */
1108
1109 node_id = reg_read(ohci, OHCI1394_NodeID);
1110 if (node_id & 0x80000000) { /* NodeID valid */
1111 phyid = node_id & 0x0000003f;
1112 isroot = (node_id & 0x40000000) != 0;
1113
1114 PRINT(KERN_INFO, ohci->id,
1115 "SelfID process finished "
1116 "(phyid %d, %s)", phyid,
1117 (isroot ? "root" : "not root"));
1118
1119 handle_selfid(ohci, host,
1120 phyid, isroot);
1121 }
1122 else
1123 PRINT(KERN_ERR, ohci->id,
1124 "SelfID process finished but "
1125 "NodeID not valid: %08X",
1126 node_id);
1127
1128 /* Accept Physical requests from all nodes. */
1129 reg_write(ohci,OHCI1394_AsReqFilterHiSet,
1130 0xffffffff);
1131 reg_write(ohci,OHCI1394_AsReqFilterLoSet,
1132 0xffffffff);
1133 /*
1134 * Tip by James Goodwin <jamesg@Filanet.com>
1135 * Turn on phys dma reception. We should
1136 * probably manage the filtering somehow,
1137 * instead of blindly turning it on.
1138 */
1139 reg_write(ohci,OHCI1394_PhyReqFilterHiSet,
1140 0xffffffff);
1141 reg_write(ohci,OHCI1394_PhyReqFilterLoSet,
1142 0xffffffff);
1143 reg_write(ohci,OHCI1394_PhyUpperBound,
1144 0xffff0000);
1145 }
1146 else PRINT(KERN_ERR, ohci->id,
1147 "self-id received outside of bus reset"
1148 "sequence");
1149 }
1150 if (event & OHCI1394_phyRegRcvd) {
1151 #if 1
1152 if (host->in_bus_reset) {
1153 PRINT(KERN_INFO, ohci->id, "PhyControl: %08X",
1154 reg_read(ohci, OHCI1394_PhyControl));
1155 }
1156 else PRINT(KERN_ERR, ohci->id,
1157 "phy reg received outside of bus reset"
1158 "sequence");
1159 #endif
1160 }
1161 } while (--timeout);
1162
1163 PRINT(KERN_ERR, ohci->id, "irq_handler timeout event=0x%08x", event);
1164 }
1165
1166 /* Put the buffer back into the dma context */
1167 static void insert_dma_buffer(struct dma_rcv_ctx *d, int idx)
1168 {
1169 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
1170 DBGMSG(ohci->id, "Inserting dma buf ctx=%d idx=%d", d->ctx, idx);
1171
1172 d->prg_cpu[idx]->status = d->buf_size;
1173 d->prg_cpu[idx]->branchAddress &= 0xfffffff0;
1174 idx = (idx + d->num_desc - 1 ) % d->num_desc;
1175 d->prg_cpu[idx]->branchAddress |= 0x1;
1176
1177 /* wake up the dma context if necessary */
1178 if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
1179 PRINT(KERN_INFO, ohci->id,
1180 "Waking dma cxt=%d ... processing is probably too slow",
1181 d->ctx);
1182 reg_write(ohci, d->ctrlSet, 0x1000);
1183 }
1184 }
1185
1186 static int block_length(struct dma_rcv_ctx *d, int idx,
1187 quadlet_t *buf_ptr, int offset)
1188 {
1189 int length=0;
1190
1191 /* Where is the data length ? */
1192 if (offset+12>=d->buf_size)
1193 length = (d->buf_cpu[(idx+1)%d->num_desc]
1194 [3-(d->buf_size-offset)/4]>>16);
1195 else
1196 length = (buf_ptr[3]>>16);
1197 if (length % 4) length += 4 - (length % 4);
1198 return length;
1199 }
1200
1201 const int TCODE_SIZE[16] = {20, 0, 16, -1, 16, 20, 20, 0,
1202 -1, 0, -1, 0, -1, -1, 16, -1};
1203
1204 /*
1205 * Determine the length of a packet in the buffer
1206 * Optimization suggested by Pascal Drolet <pascal.drolet@informission.ca>
1207 */
1208 static int packet_length(struct dma_rcv_ctx *d, int idx, quadlet_t *buf_ptr,
1209 int offset)
1210 {
1211 unsigned char tcode;
1212 int length = -1;
1213
1214 /* Let's see what kind of packet is in there */
1215 tcode = (buf_ptr[0] >> 4) & 0xf;
1216
1217 if (d->ctx < 2) { /* Async Receive Response/Request */
1218 length = TCODE_SIZE[tcode];
1219 if (length == 0)
1220 length = block_length(d, idx, buf_ptr, offset) + 20;
1221 }
1222 else if (d->ctx==2) { /* Iso receive */
1223 /* Assumption: buffer fill mode with header/trailer */
1224 length = (buf_ptr[0]>>16);
1225 if (length % 4) length += 4 - (length % 4);
1226 length+=8;
1227 }
1228 return length;
1229 }
1230
1231 /* Bottom half that processes dma receive buffers */
1232 static void dma_rcv_bh(void *data)
1233 {
1234 struct dma_rcv_ctx *d = (struct dma_rcv_ctx*)data;
1235 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
1236 unsigned int split_left, idx, offset, rescount;
1237 unsigned char tcode;
1238 int length, bytes_left, ack;
1239 quadlet_t *buf_ptr;
1240 char *split_ptr;
1241 char msg[256];
1242
1243 spin_lock(&d->lock);
1244
1245 idx = d->buf_ind;
1246 offset = d->buf_offset;
1247 buf_ptr = d->buf_cpu[idx] + offset/4;
1248
1249 rescount = d->prg_cpu[idx]->status&0xffff;
1250 bytes_left = d->buf_size - rescount - offset;
1251
1252 while (bytes_left>0) {
1253 tcode = (buf_ptr[0]>>4)&0xf;
1254 length = packet_length(d, idx, buf_ptr, offset);
1255
1256 if (length<4) { /* something is wrong */
1257 sprintf(msg,"unexpected tcode 0x%X in AR ctx=%d",
1258 tcode, d->ctx);
1259 ohci1394_stop_context(ohci, d->ctrlClear, msg);
1260 spin_unlock(&d->lock);
1261 return;
1262 }
1263
1264 if ((offset+length)>d->buf_size) { /* Split packet */
1265 if (length>d->split_buf_size) {
1266 ohci1394_stop_context(ohci, d->ctrlClear,
1267 "split packet size exceeded");
1268 d->buf_ind = idx;
1269 d->buf_offset = offset;
1270 spin_unlock(&d->lock);
1271 return;
1272 }
1273 if (d->prg_cpu[(idx+1)%d->num_desc]->status
1274 ==d->buf_size) {
1275 /* other part of packet not written yet */
1276 /* this should never happen I think */
1277 /* anyway we'll get it on the next call */
1278 PRINT(KERN_INFO, ohci->id,
1279 "Got only half a packet !!!");
1280 d->buf_ind = idx;
1281 d->buf_offset = offset;
1282 spin_unlock(&d->lock);
1283 return;
1284 }
1285 split_left = length;
1286 split_ptr = (char *)d->spb;
1287 memcpy(split_ptr,buf_ptr,d->buf_size-offset);
1288 split_left -= d->buf_size-offset;
1289 split_ptr += d->buf_size-offset;
1290 insert_dma_buffer(d, idx);
1291 idx = (idx+1) % d->num_desc;
1292 buf_ptr = d->buf_cpu[idx];
1293 offset=0;
1294 while (split_left >= d->buf_size) {
1295 memcpy(split_ptr,buf_ptr,d->buf_size);
1296 split_ptr += d->buf_size;
1297 split_left -= d->buf_size;
1298 insert_dma_buffer(d, idx);
1299 idx = (idx+1) % d->num_desc;
1300 buf_ptr = d->buf_cpu[idx];
1301 }
1302 if (split_left>0) {
1303 memcpy(split_ptr, buf_ptr, split_left);
1304 offset = split_left;
1305 buf_ptr += offset/4;
1306 }
1307
1308 /*
1309 * We get one phy packet for each bus reset.
1310 * we know that from now on the bus topology may
1311 * have changed. Just ignore it for the moment
1312 */
1313 if (tcode != 0xE) {
1314 DBGMSG(ohci->id, "Split packet received from"
1315 " node %d ack=0x%02X spd=%d tcode=0x%X"
1316 " length=%d data=0x%08x ctx=%d",
1317 (d->spb[1]>>16)&0x3f,
1318 (d->spb[length/4-1]>>16)&0x1f,
1319 (d->spb[length/4-1]>>21)&0x3,
1320 tcode, length, d->spb[3], d->ctx);
1321
1322 ack = (((d->spb[length/4-1]>>16)&0x1f)
1323 == 0x11) ? 1 : 0;
1324
1325 hpsb_packet_received(ohci->host, d->spb,
1326 length, ack);
1327 }
1328 else
1329 PRINT(KERN_INFO, ohci->id,
1330 "Got phy packet ctx=%d ... discarded",
1331 d->ctx);
1332 }
1333 else {
1334 /*
1335 * We get one phy packet for each bus reset.
1336 * we know that from now on the bus topology may
1337 * have changed. Just ignore it for the moment
1338 */
1339 if (tcode != 0xE) {
1340 DBGMSG(ohci->id, "Packet received from node"
1341 " %d ack=0x%02X spd=%d tcode=0x%X"
1342 " length=%d data=0x%08x ctx=%d",
1343 (buf_ptr[1]>>16)&0x3f,
1344 (buf_ptr[length/4-1]>>16)&0x1f,
1345 (buf_ptr[length/4-1]>>21)&0x3,
1346 tcode, length, buf_ptr[3], d->ctx);
1347
1348 ack = (((buf_ptr[length/4-1]>>16)&0x1f)
1349 == 0x11) ? 1 : 0;
1350
1351 hpsb_packet_received(ohci->host, buf_ptr,
1352 length, ack);
1353 }
1354 else
1355 PRINT(KERN_INFO, ohci->id,
1356 "Got phy packet ctx=%d ... discarded",
1357 d->ctx);
1358 offset += length;
1359 buf_ptr += length/4;
1360 if (offset==d->buf_size) {
1361 insert_dma_buffer(d, idx);
1362 idx = (idx+1) % d->num_desc;
1363 buf_ptr = d->buf_cpu[idx];
1364 offset=0;
1365 }
1366 }
1367 rescount = d->prg_cpu[idx]->status & 0xffff;
1368 bytes_left = d->buf_size - rescount - offset;
1369
1370 }
1371
1372 d->buf_ind = idx;
1373 d->buf_offset = offset;
1374
1375 spin_unlock(&d->lock);
1376 }
1377
1378 /* Bottom half that processes sent packets */
1379 static void dma_trm_bh(void *data)
1380 {
1381 struct dma_trm_ctx *d = (struct dma_trm_ctx*)data;
1382 struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
1383 struct hpsb_packet *packet, *nextpacket;
1384 unsigned long flags;
1385 u32 ack;
1386 size_t datasize;
1387
1388 spin_lock_irqsave(&d->lock, flags);
1389
1390 if (d->fifo_first==NULL) {
1391 #if 0
1392 ohci1394_stop_context(ohci, d->ctrlClear,
1393 "Packet sent ack received but queue is empty");
1394 #endif
1395 spin_unlock_irqrestore(&d->lock, flags);
1396 return;
1397 }
1398
1399 while (d->fifo_first) {
1400 packet = d->fifo_first;
1401 datasize = d->fifo_first->data_size;
1402 if (datasize)
1403 ack = d->prg_cpu[d->sent_ind]->end.status>>16;
1404 else
1405 ack = d->prg_cpu[d->sent_ind]->begin.status>>16;
1406
1407 if (ack==0)
1408 /* this packet hasn't been sent yet*/
1409 break;
1410
1411 #ifdef OHCI1394_DEBUG
1412 if (datasize)
1413 DBGMSG(ohci->id,
1414 "Packet sent to node %d tcode=0x%X tLabel="
1415 "0x%02X ack=0x%X spd=%d dataLength=%d ctx=%d",
1416 (d->prg_cpu[d->sent_ind]->data[1]>>16)&0x3f,
1417 (d->prg_cpu[d->sent_ind]->data[0]>>4)&0xf,
1418 (d->prg_cpu[d->sent_ind]->data[0]>>10)&0x3f,
1419 ack&0x1f, (ack>>5)&0x3,
1420 d->prg_cpu[d->sent_ind]->data[3]>>16,
1421 d->ctx);
1422 else
1423 DBGMSG(ohci->id,
1424 "Packet sent to node %d tcode=0x%X tLabel="
1425 "0x%02X ack=0x%X spd=%d data=0x%08X ctx=%d",
1426 (d->prg_cpu[d->sent_ind]->data[1]>>16)&0x3f,
1427 (d->prg_cpu[d->sent_ind]->data[0]>>4)&0xf,
1428 (d->prg_cpu[d->sent_ind]->data[0]>>10)&0x3f,
1429 ack&0x1f, (ack>>5)&0x3,
1430 d->prg_cpu[d->sent_ind]->data[3],
1431 d->ctx);
1432 #endif
1433
1434 nextpacket = packet->xnext;
1435 hpsb_packet_sent(ohci->host, packet, ack&0xf);
1436
1437 if (datasize)
1438 pci_unmap_single(ohci->dev,
1439 d->prg_cpu[d->sent_ind]->end.address,
1440 datasize, PCI_DMA_TODEVICE);
1441
1442 d->sent_ind = (d->sent_ind+1)%d->num_desc;
1443 d->free_prgs++;
1444 d->fifo_first = nextpacket;
1445 }
1446 if (d->fifo_first==NULL) d->fifo_last=NULL;
1447
1448 dma_trm_flush(ohci, d);
1449
1450 spin_unlock_irqrestore(&d->lock, flags);
1451 }
1452
1453 static int free_dma_rcv_ctx(struct dma_rcv_ctx **d)
1454 {
1455 int i;
1456 struct ti_ohci *ohci;
1457
1458 if (*d==NULL) return -1;
1459
1460 ohci = (struct ti_ohci *)(*d)->ohci;
1461
1462 DBGMSG(ohci->id, "Freeing dma_rcv_ctx %d",(*d)->ctx);
1463
1464 ohci1394_stop_context(ohci, (*d)->ctrlClear, NULL);
1465
1466 if ((*d)->buf_cpu) {
1467 for (i=0; i<(*d)->num_desc; i++)
1468 if ((*d)->buf_cpu[i] && (*d)->buf_bus[i])
1469 pci_free_consistent(
1470 ohci->dev, (*d)->buf_size,
1471 (*d)->buf_cpu[i], (*d)->buf_bus[i]);
1472 kfree((*d)->buf_cpu);
1473 kfree((*d)->buf_bus);
1474 }
1475 if ((*d)->prg_cpu) {
1476 for (i=0; i<(*d)->num_desc; i++)
1477 if ((*d)->prg_cpu[i] && (*d)->prg_bus[i])
1478 pci_free_consistent(
1479 ohci->dev, sizeof(struct dma_cmd),
1480 (*d)->prg_cpu[i], (*d)->prg_bus[i]);
1481 kfree((*d)->prg_cpu);
1482 kfree((*d)->prg_bus);
1483 }
1484 if ((*d)->spb) kfree((*d)->spb);
1485
1486 kfree(*d);
1487 *d = NULL;
1488
1489 return 0;
1490 }
1491
1492 static struct dma_rcv_ctx *
1493 alloc_dma_rcv_ctx(struct ti_ohci *ohci, int ctx, int num_desc,
1494 int buf_size, int split_buf_size,
1495 int ctrlSet, int ctrlClear, int cmdPtr)
1496 {
1497 struct dma_rcv_ctx *d=NULL;
1498 int i;
1499
1500 d = (struct dma_rcv_ctx *)kmalloc(sizeof(struct dma_rcv_ctx),
1501 GFP_KERNEL);
1502
1503 if (d==NULL) {
1504 PRINT(KERN_ERR, ohci->id, "failed to allocate dma_rcv_ctx");
1505 return NULL;
1506 }
1507
1508 d->ohci = (void *)ohci;
1509 d->ctx = ctx;
1510
1511 d->num_desc = num_desc;
1512 d->buf_size = buf_size;
1513 d->split_buf_size = split_buf_size;
1514 d->ctrlSet = ctrlSet;
1515 d->ctrlClear = ctrlClear;
1516 d->cmdPtr = cmdPtr;
1517
1518 d->buf_cpu = NULL;
1519 d->buf_bus = NULL;
1520 d->prg_cpu = NULL;
1521 d->prg_bus = NULL;
1522 d->spb = NULL;
1523
1524 d->buf_cpu = kmalloc(d->num_desc * sizeof(quadlet_t*), GFP_KERNEL);
1525 d->buf_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_KERNEL);
1526
1527 if (d->buf_cpu == NULL || d->buf_bus == NULL) {
1528 PRINT(KERN_ERR, ohci->id, "failed to allocate dma buffer");
1529 free_dma_rcv_ctx(&d);
1530 return NULL;
1531 }
1532 memset(d->buf_cpu, 0, d->num_desc * sizeof(quadlet_t*));
1533 memset(d->buf_bus, 0, d->num_desc * sizeof(dma_addr_t));
1534
1535 d->prg_cpu = kmalloc(d->num_desc * sizeof(struct dma_cmd*),
1536 GFP_KERNEL);
1537 d->prg_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_KERNEL);
1538
1539 if (d->prg_cpu == NULL || d->prg_bus == NULL) {
1540 PRINT(KERN_ERR, ohci->id, "failed to allocate dma prg");
1541 free_dma_rcv_ctx(&d);
1542 return NULL;
1543 }
1544 memset(d->prg_cpu, 0, d->num_desc * sizeof(struct dma_cmd*));
1545 memset(d->prg_bus, 0, d->num_desc * sizeof(dma_addr_t));
1546
1547 d->spb = kmalloc(d->split_buf_size, GFP_KERNEL);
1548
1549 if (d->spb == NULL) {
1550 PRINT(KERN_ERR, ohci->id, "failed to allocate split buffer");
1551 free_dma_rcv_ctx(&d);
1552 return NULL;
1553 }
1554
1555 for (i=0; i<d->num_desc; i++) {
1556 d->buf_cpu[i] = pci_alloc_consistent(ohci->dev,
1557 d->buf_size,
1558 d->buf_bus+i);
1559
1560 if (d->buf_cpu[i] != NULL) {
1561 memset(d->buf_cpu[i], 0, d->buf_size);
1562 } else {
1563 PRINT(KERN_ERR, ohci->id,
1564 "failed to allocate dma buffer");
1565 free_dma_rcv_ctx(&d);
1566 return NULL;
1567 }
1568
1569
1570 d->prg_cpu[i] = pci_alloc_consistent(ohci->dev,
1571 sizeof(struct dma_cmd),
1572 d->prg_bus+i);
1573
1574 if (d->prg_cpu[i] != NULL) {
1575 memset(d->prg_cpu[i], 0, sizeof(struct dma_cmd));
1576 } else {
1577 PRINT(KERN_ERR, ohci->id,
1578 "failed to allocate dma prg");
1579 free_dma_rcv_ctx(&d);
1580 return NULL;
1581 }
1582 }
1583
1584 spin_lock_init(&d->lock);
1585
1586 /* initialize bottom handler */
1587 d->task.sync = 0;
1588 INIT_LIST_HEAD(&d->task.list);
1589 d->task.routine = dma_rcv_bh;
1590 d->task.data = (void*)d;
1591
1592 return d;
1593 }
1594
1595 static int free_dma_trm_ctx(struct dma_trm_ctx **d)
1596 {
1597 struct ti_ohci *ohci;
1598 int i;
1599
1600 if (*d==NULL) return -1;
1601
1602 ohci = (struct ti_ohci *)(*d)->ohci;
1603
1604 DBGMSG(ohci->id, "Freeing dma_trm_ctx %d",(*d)->ctx);
1605
1606 ohci1394_stop_context(ohci, (*d)->ctrlClear, NULL);
1607
1608 if ((*d)->prg_cpu) {
1609 for (i=0; i<(*d)->num_desc; i++)
1610 if ((*d)->prg_cpu[i] && (*d)->prg_bus[i])
1611 pci_free_consistent(
1612 ohci->dev, sizeof(struct at_dma_prg),
1613 (*d)->prg_cpu[i], (*d)->prg_bus[i]);
1614 kfree((*d)->prg_cpu);
1615 kfree((*d)->prg_bus);
1616 }
1617
1618 kfree(*d);
1619 *d = NULL;
1620 return 0;
1621 }
1622
1623 static struct dma_trm_ctx *
1624 alloc_dma_trm_ctx(struct ti_ohci *ohci, int ctx, int num_desc,
1625 int ctrlSet, int ctrlClear, int cmdPtr)
1626 {
1627 struct dma_trm_ctx *d=NULL;
1628 int i;
1629
1630 d = (struct dma_trm_ctx *)kmalloc(sizeof(struct dma_trm_ctx),
1631 GFP_KERNEL);
1632
1633 if (d==NULL) {
1634 PRINT(KERN_ERR, ohci->id, "failed to allocate dma_trm_ctx");
1635 return NULL;
1636 }
1637
1638 d->ohci = (void *)ohci;
1639 d->ctx = ctx;
1640 d->num_desc = num_desc;
1641 d->ctrlSet = ctrlSet;
1642 d->ctrlClear = ctrlClear;
1643 d->cmdPtr = cmdPtr;
1644 d->prg_cpu = NULL;
1645 d->prg_bus = NULL;
1646
1647 d->prg_cpu = kmalloc(d->num_desc * sizeof(struct at_dma_prg*),
1648 GFP_KERNEL);
1649 d->prg_bus = kmalloc(d->num_desc * sizeof(dma_addr_t), GFP_KERNEL);
1650
1651 if (d->prg_cpu == NULL || d->prg_bus == NULL) {
1652 PRINT(KERN_ERR, ohci->id, "failed to allocate at dma prg");
1653 free_dma_trm_ctx(&d);
1654 return NULL;
1655 }
1656 memset(d->prg_cpu, 0, d->num_desc * sizeof(struct at_dma_prg*));
1657 memset(d->prg_bus, 0, d->num_desc * sizeof(dma_addr_t));
1658
1659 for (i=0; i<d->num_desc; i++) {
1660 d->prg_cpu[i] = pci_alloc_consistent(ohci->dev,
1661 sizeof(struct at_dma_prg),
1662 d->prg_bus+i);
1663
1664 if (d->prg_cpu[i] != NULL) {
1665 memset(d->prg_cpu[i], 0, sizeof(struct at_dma_prg));
1666 } else {
1667 PRINT(KERN_ERR, ohci->id,
1668 "failed to allocate at dma prg");
1669 free_dma_trm_ctx(&d);
1670 return NULL;
1671 }
1672 }
1673
1674 spin_lock_init(&d->lock);
1675
1676 /* initialize bottom handler */
1677 d->task.routine = dma_trm_bh;
1678 d->task.data = (void*)d;
1679
1680 return d;
1681 }
1682
1683 static u32 ohci_crc16(unsigned *data, int length)
1684 {
1685 int check=0, i;
1686 int shift, sum, next=0;
1687
1688 for (i = length; i; i--) {
1689 for (next = check, shift = 28; shift >= 0; shift -= 4 ) {
1690 sum = ((next >> 12) ^ (*data >> shift)) & 0xf;
1691 next = (next << 4) ^ (sum << 12) ^ (sum << 5) ^ (sum);
1692 }
1693 check = next & 0xffff;
1694 data++;
1695 }
1696
1697 return check;
1698 }
1699
1700 static void ohci_init_config_rom(struct ti_ohci *ohci)
1701 {
1702 int i;
1703
1704 ohci_csr_rom[3] = reg_read(ohci, OHCI1394_GUIDHi);
1705 ohci_csr_rom[4] = reg_read(ohci, OHCI1394_GUIDLo);
1706
1707 ohci_csr_rom[0] = 0x04040000 | ohci_crc16(ohci_csr_rom+1, 4);
1708
1709 for (i=0;i<sizeof(ohci_csr_rom)/4;i++)
1710 ohci->csr_config_rom_cpu[i] = cpu_to_be32(ohci_csr_rom[i]);
1711 }
1712
1713 static int add_card(struct pci_dev *dev)
1714 {
1715 struct ti_ohci *ohci; /* shortcut to currently handled device */
1716
1717 if (num_of_cards == MAX_OHCI1394_CARDS) {
1718 PRINT_G(KERN_WARNING, "cannot handle more than %d cards. "
1719 "Adjust MAX_OHCI1394_CARDS in ti_ohci1394.h.",
1720 MAX_OHCI1394_CARDS);
1721 return 1;
1722 }
1723
1724 if (pci_enable_device(dev)) {
1725 PRINT_G(KERN_NOTICE, "failed to enable OHCI hardware %d",
1726 num_of_cards);
1727 return 1;
1728 }
1729 pci_set_master(dev);
1730
1731 ohci = &cards[num_of_cards++];
1732
1733 ohci->id = num_of_cards-1;
1734 ohci->dev = dev;
1735
1736 ohci->state = 0;
1737
1738 /* csr_config rom allocation */
1739 ohci->csr_config_rom_cpu =
1740 pci_alloc_consistent(ohci->dev, sizeof(ohci_csr_rom),
1741 &ohci->csr_config_rom_bus);
1742 if (ohci->csr_config_rom_cpu == NULL) {
1743 FAIL("failed to allocate buffer config rom");
1744 }
1745
1746 /*
1747 * self-id dma buffer allocation
1748 * FIXME: some early chips may need 8KB alignment for the
1749 * selfid buffer... if you have problems a temporary fic
1750 * is to allocate 8192 bytes instead of 2048
1751 */
1752 ohci->selfid_buf_cpu =
1753 pci_alloc_consistent(ohci->dev, 2048, &ohci->selfid_buf_bus);
1754 if (ohci->selfid_buf_cpu == NULL) {
1755 FAIL("failed to allocate DMA buffer for self-id packets");
1756 }
1757 if ((unsigned long)ohci->selfid_buf_cpu & 0x1fff)
1758 PRINT(KERN_INFO, ohci->id, "Selfid buffer %p not aligned on "
1759 "8Kb boundary... may cause pb on some CXD3222 chip",
1760 ohci->selfid_buf_cpu);
1761
1762 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13)
1763 ohci->registers = ioremap_nocache(dev->base_address[0],
1764 OHCI1394_REGISTER_SIZE);
1765 #else
1766 ohci->registers = ioremap_nocache(dev->resource[0].start,
1767 OHCI1394_REGISTER_SIZE);
1768 #endif
1769
1770 if (ohci->registers == NULL) {
1771 FAIL("failed to remap registers - card not accessible");
1772 }
1773
1774 PRINT(KERN_INFO, ohci->id, "remapped memory spaces reg 0x%p",
1775 ohci->registers);
1776
1777 ohci->ar_req_context =
1778 alloc_dma_rcv_ctx(ohci, 0, AR_REQ_NUM_DESC,
1779 AR_REQ_BUF_SIZE, AR_REQ_SPLIT_BUF_SIZE,
1780 OHCI1394_AsReqRcvContextControlSet,
1781 OHCI1394_AsReqRcvContextControlClear,
1782 OHCI1394_AsReqRcvCommandPtr);
1783
1784 if (ohci->ar_req_context == NULL) {
1785 FAIL("failed to allocate AR Req context");
1786 }
1787
1788 ohci->ar_resp_context =
1789 alloc_dma_rcv_ctx(ohci, 1, AR_RESP_NUM_DESC,
1790 AR_RESP_BUF_SIZE, AR_RESP_SPLIT_BUF_SIZE,
1791 OHCI1394_AsRspRcvContextControlSet,
1792 OHCI1394_AsRspRcvContextControlClear,
1793 OHCI1394_AsRspRcvCommandPtr);
1794
1795 if (ohci->ar_resp_context == NULL) {
1796 FAIL("failed to allocate AR Resp context");
1797 }
1798
1799 ohci->at_req_context =
1800 alloc_dma_trm_ctx(ohci, 0, AT_REQ_NUM_DESC,
1801 OHCI1394_AsReqTrContextControlSet,
1802 OHCI1394_AsReqTrContextControlClear,
1803 OHCI1394_AsReqTrCommandPtr);
1804
1805 if (ohci->at_req_context == NULL) {
1806 FAIL("failed to allocate AT Req context");
1807 }
1808
1809 ohci->at_resp_context =
1810 alloc_dma_trm_ctx(ohci, 1, AT_RESP_NUM_DESC,
1811 OHCI1394_AsRspTrContextControlSet,
1812 OHCI1394_AsRspTrContextControlClear,
1813 OHCI1394_AsRspTrCommandPtr);
1814
1815 if (ohci->at_resp_context == NULL) {
1816 FAIL("failed to allocate AT Resp context");
1817 }
1818
1819 ohci->ir_context =
1820 alloc_dma_rcv_ctx(ohci, 2, IR_NUM_DESC,
1821 IR_BUF_SIZE, IR_SPLIT_BUF_SIZE,
1822 OHCI1394_IsoRcvContextControlSet,
1823 OHCI1394_IsoRcvContextControlClear,
1824 OHCI1394_IsoRcvCommandPtr);
1825
1826 if (ohci->ir_context == NULL) {
1827 FAIL("failed to allocate IR context");
1828 }
1829
1830 ohci->IR_channel_usage= 0x0000000000000000;
1831 spin_lock_init(&ohci->IR_channel_lock);
1832
1833 if (!request_irq(dev->irq, ohci_irq_handler, SA_SHIRQ,
1834 OHCI1394_DRIVER_NAME, ohci)) {
1835 PRINT(KERN_INFO, ohci->id, "allocated interrupt %d", dev->irq);
1836 } else {
1837 FAIL("failed to allocate shared interrupt %d", dev->irq);
1838 }
1839
1840 ohci_init_config_rom(ohci);
1841
1842 DBGMSG(ohci->id, "The 1st byte at offset 0x404 is: 0x%02x",
1843 *((char *)ohci->csr_config_rom_cpu+4));
1844
1845 return 0;
1846 #undef FAIL
1847 }
1848
1849 #ifdef CONFIG_PROC_FS
1850
1851 #define SR(fmt, reg0, reg1, reg2)\
1852 p += sprintf(p,fmt,reg_read(ohci, reg0),\
1853 reg_read(ohci, reg1),reg_read(ohci, reg2));
1854
1855 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,0)
1856 static int ohci_get_status(char *buf)
1857 #else
1858 int ohci_get_info(char *buf, char **start, off_t fpos,
1859 int length, int dummy)
1860 #endif
1861 {
1862 struct ti_ohci *ohci=&cards[0];
1863 struct hpsb_host *host=ohci->host;
1864 char *p=buf;
1865 //unsigned char phyreg;
1866 //int i, nports;
1867 int i;
1868
1869 struct dma_rcv_ctx *d=NULL;
1870 struct dma_trm_ctx *dt=NULL;
1871
1872 p += sprintf(p,"IEEE-1394 OHCI Driver status report:\n");
1873 p += sprintf(p," bus number: 0x%x Node ID: 0x%x\n",
1874 (reg_read(ohci, OHCI1394_NodeID) & 0xFFC0) >> 6,
1875 reg_read(ohci, OHCI1394_NodeID)&0x3f);
1876 #if 0
1877 p += sprintf(p," hardware version %d.%d GUID_ROM is %s\n\n",
1878 (reg_read(ohci, OHCI1394_Version) & 0xFF0000) >>16,
1879 reg_read(ohci, OHCI1394_Version) & 0xFF,
1880 (reg_read(ohci, OHCI1394_Version) & 0x01000000)
1881 ? "set" : "clear");
1882 #endif
1883 p += sprintf(p,"\n### Host data ###\n");
1884 p += sprintf(p,"node_count: %8d ",host->node_count);
1885 p += sprintf(p,"node_id : %08X\n",host->node_id);
1886 p += sprintf(p,"irm_id : %08X ",host->irm_id);
1887 p += sprintf(p,"busmgr_id : %08X\n",host->busmgr_id);
1888 p += sprintf(p,"%s %s %s\n",
1889 host->initialized ? "initialized" : "",
1890 host->in_bus_reset ? "in_bus_reset" : "",
1891 host->attempt_root ? "attempt_root" : "");
1892 p += sprintf(p,"%s %s %s %s\n",
1893 host->is_root ? "root" : "",
1894 host->is_cycmst ? "cycle_master" : "",
1895 host->is_irm ? "iso_res_mgr" : "",
1896 host->is_busmgr ? "bus_mgr" : "");
1897
1898 p += sprintf(p,"\n---Iso Receive DMA---\n");
1899
1900 d = ohci->ir_context;
1901 #if 0
1902 for (i=0; i<d->num_desc; i++) {
1903 p += sprintf(p, "IR buf[%d] : %p prg[%d]: %p\n",
1904 i, d->buf[i], i, d->prg[i]);
1905 }
1906 #endif
1907 p += sprintf(p, "Current buf: %d offset: %d\n",
1908 d->buf_ind,d->buf_offset);
1909
1910 p += sprintf(p,"\n---Async Receive DMA---\n");
1911 d = ohci->ar_req_context;
1912 #if 0
1913 for (i=0; i<d->num_desc; i++) {
1914 p += sprintf(p, "AR req buf[%d] : %p prg[%d]: %p\n",
1915 i, d->buf[i], i, d->prg[i]);
1916 }
1917 #endif
1918 p += sprintf(p, "Ar req current buf: %d offset: %d\n",
1919 d->buf_ind,d->buf_offset);
1920
1921 d = ohci->ar_resp_context;
1922 #if 0
1923 for (i=0; i<d->num_desc; i++) {
1924 p += sprintf(p, "AR resp buf[%d] : %p prg[%d]: %p\n",
1925 i, d->buf[i], i, d->prg[i]);
1926 }
1927 #endif
1928 p += sprintf(p, "AR resp current buf: %d offset: %d\n",
1929 d->buf_ind,d->buf_offset);
1930
1931 p += sprintf(p,"\n---Async Transmit DMA---\n");
1932 dt = ohci->at_req_context;
1933 p += sprintf(p, "AT req prg: %d sent: %d free: %d branchAddrPtr: %p\n",
1934 dt->prg_ind, dt->sent_ind, dt->free_prgs,
1935 dt->branchAddrPtr);
1936 p += sprintf(p, "AT req queue: first: %p last: %p\n",
1937 dt->fifo_first, dt->fifo_last);
1938 dt = ohci->at_resp_context;
1939 #if 0
1940 for (i=0; i<dt->num_desc; i++) {
1941 p += sprintf(p, "------- AT resp prg[%02d] ------\n",i);
1942 p += sprintf(p, "%p: control : %08x\n",
1943 &(dt->prg[i].begin.control),
1944 dt->prg[i].begin.control);
1945 p += sprintf(p, "%p: address : %08x\n",
1946 &(dt->prg[i].begin.address),
1947 dt->prg[i].begin.address);
1948 p += sprintf(p, "%p: brancAddr: %08x\n",
1949 &(dt->prg[i].begin.branchAddress),
1950 dt->prg[i].begin.branchAddress);
1951 p += sprintf(p, "%p: status : %08x\n",
1952 &(dt->prg[i].begin.status),
1953 dt->prg[i].begin.status);
1954 p += sprintf(p, "%p: header[0]: %08x\n",
1955 &(dt->prg[i].data[0]),
1956 dt->prg[i].data[0]);
1957 p += sprintf(p, "%p: header[1]: %08x\n",
1958 &(dt->prg[i].data[1]),
1959 dt->prg[i].data[1]);
1960 p += sprintf(p, "%p: header[2]: %08x\n",
1961 &(dt->prg[i].data[2]),
1962 dt->prg[i].data[2]);
1963 p += sprintf(p, "%p: header[3]: %08x\n",
1964 &(dt->prg[i].data[3]),
1965 dt->prg[i].data[3]);
1966 p += sprintf(p, "%p: control : %08x\n",
1967 &(dt->prg[i].end.control),
1968 dt->prg[i].end.control);
1969 p += sprintf(p, "%p: address : %08x\n",
1970 &(dt->prg[i].end.address),
1971 dt->prg[i].end.address);
1972 p += sprintf(p, "%p: brancAddr: %08x\n",
1973 &(dt->prg[i].end.branchAddress),
1974 dt->prg[i].end.branchAddress);
1975 p += sprintf(p, "%p: status : %08x\n",
1976 &(dt->prg[i].end.status),
1977 dt->prg[i].end.status);
1978 }
1979 #endif
1980 p += sprintf(p, "AR resp prg: %d sent: %d free: %d"
1981 " branchAddrPtr: %p\n",
1982 dt->prg_ind, dt->sent_ind, dt->free_prgs,
1983 dt->branchAddrPtr);
1984 p += sprintf(p, "AT resp queue: first: %p last: %p\n",
1985 dt->fifo_first, dt->fifo_last);
1986
1987 /* ----- Register Dump ----- */
1988 p += sprintf(p,"\n### HC Register dump ###\n");
1989 SR("Version : %08x GUID_ROM : %08x ATRetries : %08x\n",
1990 OHCI1394_Version, OHCI1394_GUID_ROM, OHCI1394_ATRetries);
1991 SR("CSRData : %08x CSRCompData : %08x CSRControl : %08x\n",
1992 OHCI1394_CSRData, OHCI1394_CSRCompareData, OHCI1394_CSRControl);
1993 SR("ConfigROMhdr: %08x BusID : %08x BusOptions : %08x\n",
1994 OHCI1394_ConfigROMhdr, OHCI1394_BusID, OHCI1394_BusOptions);
1995 SR("GUIDHi : %08x GUIDLo : %08x ConfigROMmap: %08x\n",
1996 OHCI1394_GUIDHi, OHCI1394_GUIDLo, OHCI1394_ConfigROMmap);
1997 SR("PtdWrAddrLo : %08x PtdWrAddrHi : %08x VendorID : %08x\n",
1998 OHCI1394_PostedWriteAddressLo, OHCI1394_PostedWriteAddressHi,
1999 OHCI1394_VendorID);
2000 SR("HCControl : %08x SelfIDBuffer: %08x SelfIDCount : %08x\n",
2001 OHCI1394_HCControlSet, OHCI1394_SelfIDBuffer, OHCI1394_SelfIDCount);
2002 SR("IRMuChMaskHi: %08x IRMuChMaskLo: %08x IntEvent : %08x\n",
2003 OHCI1394_IRMultiChanMaskHiSet, OHCI1394_IRMultiChanMaskLoSet,
2004 OHCI1394_IntEventSet);
2005 SR("IntMask : %08x IsoXmIntEvnt: %08x IsoXmIntMask: %08x\n",
2006 OHCI1394_IntMaskSet, OHCI1394_IsoXmitIntEventSet,
2007 OHCI1394_IsoXmitIntMaskSet);
2008 SR("IsoRcvIntEvt: %08x IsoRcvIntMsk: %08x FairnessCtrl: %08x\n",
2009 OHCI1394_IsoRecvIntEventSet, OHCI1394_IsoRecvIntMaskSet,
2010 OHCI1394_FairnessControl);
2011 SR("LinkControl : %08x NodeID : %08x PhyControl : %08x\n",
2012 OHCI1394_LinkControlSet, OHCI1394_NodeID, OHCI1394_PhyControl);
2013 SR("IsoCyclTimer: %08x AsRqFilterHi: %08x AsRqFilterLo: %08x\n",
2014 OHCI1394_IsochronousCycleTimer,
2015 OHCI1394_AsReqFilterHiSet, OHCI1394_AsReqFilterLoSet);
2016 SR("PhyReqFiltHi: %08x PhyReqFiltLo: %08x PhyUpperBnd : %08x\n",
2017 OHCI1394_PhyReqFilterHiSet, OHCI1394_PhyReqFilterLoSet,
2018 OHCI1394_PhyUpperBound);
2019 SR("AsRqTrCxtCtl: %08x AsRqTrCmdPtr: %08x AsRsTrCtxCtl: %08x\n",
2020 OHCI1394_AsReqTrContextControlSet, OHCI1394_AsReqTrCommandPtr,
2021 OHCI1394_AsRspTrContextControlSet);
2022 SR("AsRsTrCmdPtr: %08x AsRqRvCtxCtl: %08x AsRqRvCmdPtr: %08x\n",
2023 OHCI1394_AsRspTrCommandPtr, OHCI1394_AsReqRcvContextControlSet,
2024 OHCI1394_AsReqRcvCommandPtr);
2025 SR("AsRsRvCtxCtl: %08x AsRsRvCmdPtr: %08x IntEvent : %08x\n",
2026 OHCI1394_AsRspRcvContextControlSet, OHCI1394_AsRspRcvCommandPtr,
2027 OHCI1394_IntEventSet);
2028 for (i=0;i<ohci->nb_iso_rcv_ctx;i++) {
2029 p += sprintf(p,"IsoRCtxCtl%02d: %08x IsoRCmdPtr%02d: %08x"
2030 " IsoRCxtMch%02d: %08x\n", i,
2031 reg_read(ohci,
2032 OHCI1394_IsoRcvContextControlSet+32*i),
2033 i,reg_read(ohci, OHCI1394_IsoRcvCommandPtr+32*i),
2034 i,reg_read(ohci,
2035 OHCI1394_IsoRcvContextMatch+32*i));
2036 }
2037 for (i=0;i<ohci->nb_iso_xmit_ctx;i++) {
2038 p += sprintf(p,"IsoTCtxCtl%02d: %08x IsoTCmdPtr%02d: %08x\n",
2039 i,
2040 reg_read(ohci,
2041 OHCI1394_IsoXmitContextControlSet+32*i),
2042 i,reg_read(ohci,OHCI1394_IsoXmitCommandPtr+32*i));
2043 }
2044
2045 #if 0
2046 p += sprintf(p,"\n### Phy Register dump ###\n");
2047 phyreg=get_phy_reg(ohci,1);
2048 p += sprintf(p,"offset: %d val: 0x%02x -> RHB: %d"
2049 "IBR: %d Gap_count: %d\n",
2050 1,phyreg,(phyreg&0x80) != 0,
2051 (phyreg&0x40) !=0, phyreg&0x3f);
2052 phyreg=get_phy_reg(ohci,2);
2053 nports=phyreg&0x1f;
2054 p += sprintf(p,"offset: %d val: 0x%02x -> SPD: %d"
2055 " E : %d Ports : %2d\n",
2056 2,phyreg, (phyreg&0xC0)>>6, (phyreg&0x20) !=0, nports);
2057 for (i=0;i<nports;i++) {
2058 phyreg=get_phy_reg(ohci,3+i);
2059 p += sprintf(p,"offset: %d val: 0x%02x -> [port %d]"
2060 " TPA: %d TPB: %d | %s %s\n",
2061 3+i,phyreg,
2062 i, (phyreg&0xC0)>>6, (phyreg&0x30)>>4,
2063 (phyreg&0x08) ? "child" : "parent",
2064 (phyreg&0x04) ? "connected" : "disconnected");
2065 }
2066 phyreg=get_phy_reg(ohci,3+i);
2067 p += sprintf(p,"offset: %d val: 0x%02x -> ENV: %s Reg_count: %d\n",
2068 3+i,phyreg,
2069 (((phyreg&0xC0)>>6)==0) ? "backplane" :
2070 (((phyreg&0xC0)>>6)==1) ? "cable" : "reserved",
2071 phyreg&0x3f);
2072 #endif
2073
2074 return p - buf;
2075 }
2076
2077 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,0)
2078 static int ohci1394_read_proc(char *page, char **start, off_t off,
2079 int count, int *eof, void *data)
2080 {
2081 int len = ohci_get_status(page);
2082 if (len <= off+count) *eof = 1;
2083 *start = page + off;
2084 len -= off;
2085 if (len>count) len = count;
2086 if (len<0) len = 0;
2087 return len;
2088 }
2089 #else
2090 struct proc_dir_entry ohci_proc_entry =
2091 {
2092 0, /* Inode number - dynamic */
2093 8, /* Length of the file name */
2094 "ohci1394", /* The file name */
2095 S_IFREG | S_IRUGO, /* File mode */
2096 1, /* Number of links */
2097 0, 0, /* The uid and gid for the file */
2098 0, /* The size of the file reported by ls. */
2099 NULL, /* functions which can be done on the inode */
2100 ohci_get_info, /* The read function for this file */
2101 NULL
2102 };
2103 #endif /* LINUX_VERSION_CODE */
2104 #endif /* CONFIG_PROC_FS */
2105
2106 static void remove_card(struct ti_ohci *ohci)
2107 {
2108 /*
2109 * Reset the board properly before leaving
2110 * Daniel Kobras <daniel.kobras@student.uni-tuebingen.de>
2111 */
2112 ohci_soft_reset(ohci);
2113
2114 /* Free AR dma */
2115 free_dma_rcv_ctx(&ohci->ar_req_context);
2116 free_dma_rcv_ctx(&ohci->ar_resp_context);
2117
2118 /* Free AT dma */
2119 free_dma_trm_ctx(&ohci->at_req_context);
2120 free_dma_trm_ctx(&ohci->at_resp_context);
2121
2122 /* Free IR dma */
2123 free_dma_rcv_ctx(&ohci->ir_context);
2124
2125 /* Free self-id buffer */
2126 if (ohci->selfid_buf_cpu)
2127 pci_free_consistent(ohci->dev, 2048,
2128 ohci->selfid_buf_cpu,
2129 ohci->selfid_buf_bus);
2130
2131 /* Free config rom */
2132 if (ohci->csr_config_rom_cpu)
2133 pci_free_consistent(ohci->dev, sizeof(ohci_csr_rom),
2134 ohci->csr_config_rom_cpu,
2135 ohci->csr_config_rom_bus);
2136
2137 /* Free the IRQ */
2138 free_irq(ohci->dev->irq, ohci);
2139
2140 if (ohci->registers)
2141 iounmap(ohci->registers);
2142
2143 ohci->state = 0;
2144 }
2145
2146 static int init_driver()
2147 {
2148 struct pci_dev *dev = NULL;
2149 int success = 0;
2150 int i;
2151
2152 if (num_of_cards) {
2153 PRINT_G(KERN_DEBUG, __PRETTY_FUNCTION__ " called again");
2154 return 0;
2155 }
2156
2157 PRINT_G(KERN_INFO, "looking for Ohci1394 cards");
2158
2159 for (i = 0; supported_chips[i][0] != -1; i++) {
2160 while ((dev = pci_find_device(supported_chips[i][0],
2161 supported_chips[i][1], dev))
2162 != NULL) {
2163 if (add_card(dev) == 0) {
2164 success = 1;
2165 }
2166 }
2167 }
2168
2169 if (success == 0) {
2170 PRINT_G(KERN_WARNING, "no operable Ohci1394 cards found");
2171 return -ENXIO;
2172 }
2173
2174 #ifdef CONFIG_PROC_FS
2175 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,0)
2176 create_proc_read_entry ("ohci1394", 0, NULL, ohci1394_read_proc, NULL);
2177 #else
2178 if (proc_register(&proc_root, &ohci_proc_entry)) {
2179 PRINT_G(KERN_ERR, "unable to register proc file");
2180 return -EIO;
2181 }
2182 #endif
2183 #endif
2184 return 0;
2185 }
2186
2187 static size_t get_ohci_rom(struct hpsb_host *host, const quadlet_t **ptr)
2188 {
2189 struct ti_ohci *ohci=host->hostdata;
2190
2191 DBGMSG(ohci->id, "request csr_rom address: %08X",
2192 (u32)ohci->csr_config_rom_cpu);
2193
2194 *ptr = ohci->csr_config_rom_cpu;
2195 return sizeof(ohci_csr_rom);
2196 }
2197
2198 struct hpsb_host_template *get_ohci_template(void)
2199 {
2200 static struct hpsb_host_template tmpl;
2201 static int initialized = 0;
2202
2203 if (!initialized) {
2204 /* Initialize by field names so that a template structure
2205 * reorganization does not influence this code. */
2206 tmpl.name = "ohci1394";
2207
2208 tmpl.detect_hosts = ohci_detect;
2209 tmpl.initialize_host = ohci_initialize;
2210 tmpl.release_host = ohci_remove;
2211 tmpl.get_rom = get_ohci_rom;
2212 tmpl.transmit_packet = ohci_transmit;
2213 tmpl.devctl = ohci_devctl;
2214
2215 initialized = 1;
2216 }
2217
2218 return &tmpl;
2219 }
2220
2221 void ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg)
2222 {
2223 int i=0;
2224
2225 /* stop the channel program if it's still running */
2226 reg_write(ohci, reg, 0x8000);
2227
2228 /* Wait until it effectively stops */
2229 while (reg_read(ohci, reg) & 0x400) {
2230 i++;
2231 if (i>5000) {
2232 PRINT(KERN_ERR, ohci->id,
2233 "runaway loop while stopping context...");
2234 break;
2235 }
2236 }
2237 if (msg) PRINT(KERN_ERR, ohci->id, "%s\n dma prg stopped\n", msg);
2238 }
2239
2240 struct ti_ohci *ohci1394_get_struct(int card_num)
2241 {
2242 if (card_num>=0 && card_num<num_of_cards)
2243 return &cards[card_num];
2244 return NULL;
2245 }
2246
2247 int ohci1394_register_video(struct ti_ohci *ohci,
2248 struct video_template *tmpl)
2249 {
2250 if (ohci->video_tmpl)
2251 return -ENFILE;
2252 ohci->video_tmpl = tmpl;
2253 MOD_INC_USE_COUNT;
2254 return 0;
2255 }
2256
2257 void ohci1394_unregister_video(struct ti_ohci *ohci,
2258 struct video_template *tmpl)
2259 {
2260 if (ohci->video_tmpl != tmpl) {
2261 PRINT(KERN_ERR, ohci->id,
2262 "Trying to unregister wrong video device");
2263 }
2264 else {
2265 ohci->video_tmpl = NULL;
2266 MOD_DEC_USE_COUNT;
2267 }
2268 }
2269
2270 #if 0
2271 int ohci_compare_swap(struct ti_ohci *ohci, quadlet_t *data,
2272 quadlet_t compare, int sel)
2273 {
2274 int timeout = 255;
2275 reg_write(ohci, OHCI1394_CSRData, *data);
2276 reg_write(ohci, OHCI1394_CSRCompareData, compare);
2277 reg_write(ohci, OHCI1394_CSRControl, sel);
2278 while(!(reg_read(ohci, OHCI1394_CSRControl)&0x80000000)) {
2279 if (timeout--) {
2280 PRINT(KERN_INFO, ohci->id, "request_channel timeout");
2281 return -1;
2282 }
2283 }
2284 *data = reg_read(ohci, OHCI1394_CSRData);
2285 return 0;
2286 }
2287
2288 int ohci1394_request_channel(struct ti_ohci *ohci, int channel)
2289 {
2290 int csrSel;
2291 quadlet_t chan, data1=0, data2=0;
2292 int timeout = 32;
2293
2294 if (channel<32) {
2295 chan = 1<<channel;
2296 csrSel = 2;
2297 }
2298 else {
2299 chan = 1<<(channel-32);
2300 csrSel = 3;
2301 }
2302 if (ohci_compare_swap(ohci, &data1, 0, csrSel)<0) {
2303 PRINT(KERN_INFO, ohci->id, "request_channel timeout");
2304 return -1;
2305 }
2306 while (timeout--) {
2307 if (data1 & chan) {
2308 PRINT(KERN_INFO, ohci->id,
2309 "request channel %d failed", channel);
2310 return -1;
2311 }
2312 data2 = data1;
2313 data1 |= chan;
2314 if (ohci_compare_swap(ohci, &data1, data2, csrSel)<0) {
2315 PRINT(KERN_INFO, ohci->id, "request_channel timeout");
2316 return -1;
2317 }
2318 if (data1==data2) {
2319 PRINT(KERN_INFO, ohci->id,
2320 "request channel %d succeded", channel);
2321 return 0;
2322 }
2323 }
2324 PRINT(KERN_INFO, ohci->id, "request channel %d failed", channel);
2325 return -1;
2326 }
2327 #endif
2328
2329 EXPORT_SYMBOL(ohci1394_stop_context);
2330 EXPORT_SYMBOL(ohci1394_get_struct);
2331 EXPORT_SYMBOL(ohci1394_register_video);
2332 EXPORT_SYMBOL(ohci1394_unregister_video);
2333
2334 #ifdef MODULE
2335
2336 /* EXPORT_NO_SYMBOLS; */
2337
2338 MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
2339 MODULE_DESCRIPTION("driver for PCI Ohci IEEE-1394 controller");
2340 MODULE_SUPPORTED_DEVICE("ohci1394");
2341
2342 void cleanup_module(void)
2343 {
2344 hpsb_unregister_lowlevel(get_ohci_template());
2345 #ifdef CONFIG_PROC_FS
2346 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,3,0)
2347 remove_proc_entry ("ohci1394", NULL);
2348 #else
2349 proc_unregister(&proc_root, ohci_proc_entry.low_ino);
2350 #endif
2351 #endif
2352
2353 PRINT_G(KERN_INFO, "removed " OHCI1394_DRIVER_NAME " module");
2354 }
2355
2356 int init_module(void)
2357 {
2358 memset(cards, 0, MAX_OHCI1394_CARDS * sizeof (struct ti_ohci));
2359
2360 if (hpsb_register_lowlevel(get_ohci_template())) {
2361 PRINT_G(KERN_ERR, "registering failed");
2362 return -ENXIO;
2363 }
2364 return 0;
2365 }
2366
2367 #endif /* MODULE */
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