include/net/irda/uircc.h

   1 /*********************************************************************
   2  *
   3  * Filename:      uircc.h
   4  * Version:       0.1
   5  * Description:   Driver for the Sharp Universal Infrared
   6  *                Communications Controller (UIRCC)
   7  * Status:        Experimental.
   8  * Author:        Dag Brattli <dagb@cs.uit.no>
   9  * Created at:    Sat Dec 26 11:00:49 1998
  10  * Modified at:   Tue Jan 19 23:52:46 1999
  11  * Modified by:   Dag Brattli <dagb@cs.uit.no>
  12  *
  13  *     Copyright (c) 1998 Dag Brattli, All Rights Reserved.
  14  *
  15  *     This program is free software; you can redistribute it and/or
  16  *     modify it under the terms of the GNU General Public License as
  17  *     published by the Free Software Foundation; either version 2 of
  18  *     the License, or (at your option) any later version.
  19  *
  20  *     Neither Dag Brattli nor University of Tromsø admit liability nor
  21  *     provide warranty for any of this software. This material is
  22  *     provided "AS-IS" and at no charge.
  23  *
  24  ********************************************************************/
  25
  26 #ifndef UIRCC_H
  27 #define UIRCC_H
  28
  29 /* Control registers (write only) */
  30 #define UIRCC_CR0           0x00 /* Control register 0 */
  31 #define UIRCC_CR0_XMIT_RST  0x20 /* Transmit reset */
  32 #define UIRCC_CR0_RECV_RST  0x10 /* Receive reset */
  33 #define UIRCC_CR0_TMR_RST   0x08 /* Timer reset */
  34 #define UIRCC_CR0_SYS_RST   0x04 /* System reset */
  35 #define UIRCC_CR0_CARR_RST  0x02 /* Carrier latch reset */
  36 #define UIRCC_CR0_CNT_SWT   0x01 /* Transmit/receive length counter reset */
  37
  38 #define UIRCC_CR1           0x01 /* Transmit/receive mode setting register */
  39 #define UIRCC_CR1_RX_DMA    0x80 /* Rx DMA mode */
  40 #define UIRCC_CR1_TX_DMA    0x20 /* Tx DMA mode */
  41 #define UIRCC_CR1_DMA_BRST  0x10 /* DMA burst mode */
  42 #define UIRCC_CR1_MUST_SET  0x0c /* Must be set */
  43
  44 #define UIRCC_CR2           0x02 /* Interrupt mask register */
  45 #define UIRCC_CR2_RECV_OVR  0x40 /* Receive overrun error */
  46 #define UIRCC_CR2_RECV_FRM  0x20 /* Receive frame error */
  47 #define UIRCC_CR2_RECV_END  0x10 /* Receive end */
  48 #define UIRCC_CR2_TMR_OUT   0x08 /* Timer time-out */
  49 #define UIRCC_CR2_XMIT_UNR  0x04 /* Transmit under-run error */
  50 #define UIRCC_CR2_XMIT_END  0x01 /* Transmit end */
  51 #define UIRCC_CR2_RECV_MASK 0x70
  52 #define UIRCC_CR2_XMIT_MASK 0x05
  53
  54 #define UIRCC_CR3           0x03 /* Transmit/receive control */
  55 #define UIRCC_CR3_XMIT_EN   0x80 /* Transmit enable */
  56 #define UIRCC_CR3_TX_CRC_EN 0x40 /* Transmit UIRCC_CRC enable */
  57 #define UIRCC_CR3_RECV_EN   0x20 /* Receive enable */
  58 #define UIRCC_CR3_RX_CRC_EN 0x10 /* Receive CRC enable */
  59 #define UIRCC_CR3_ADDR_CMP  0x08 /* Address comparison enable */
  60 #define UIRCC_CR3_MCAST_EN  0x04 /* Multicast enable */
  61
  62 #define UIRCC_CR4           0x04 /* Transmit data length low byte */
  63 #define UIRCC_CR5           0x05 /* Transmit data length high byte */
  64 #define UIRCC_CR6           0x06 /* Transmit data writing low byte */
  65 #define UIRCC_CR7           0x07 /* Transmit data writing high byte */
  66
  67 #define UIRCC_CR8           0x08 /* Self pole address */
  68
  69 #define UIRCC_CR9           0x09 /* System control 1 */
  70
  71 #define UIRCC_CR10          0x0a /* Modem selection */
  72 #define UIRCC_CR10_SIR      0x22 /* Set SIR mode */
  73 #define UIRCC_CR10_FIR      0x88 /* Set FIR mode */
  74
  75 #define UIRCC_CR11          0x0b /* System control 2 (same as SR11) */
  76 #define UIRCC_CR11_TMR_EN   0x08
  77
  78 #define UIRCC_CR12          0x0c /* Timer counter initial value (low byte) */
  79 #define UIRCC_CR13          0x0d /* Timer counter initial value (high byte) */
  80
  81 /* Status registers (read only) */
  82 #define UIRCC_SR0           0x00 /* Transmit/receive status register */
  83 #define UIRCC_SR0_RX_RDY    0x80 /* Received data ready */
  84 #define UIRCC_SR0_RX_OVR    0x40 /* Receive overrun error */
  85 #define UIRCC_SR0_RX_CRCFRM 0x20 /* Receive CRC or framing error */
  86
  87 #define UIRCC_SR2           0x02 /* Interrupt mask status */
  88
  89 #define UIRCC_SR3           0x03 /* Interrupt factor register */
  90 #define UIRCC_SR3_RX_OVR_ER 0x40 /* Receive overrun error */
  91 #define UIRCC_SR3_RX_FRM_ER 0x20 /* Receive frameing error */
  92 #define UIRCC_SR3_RX_EOF    0x10 /* Receive end of frame */
  93 #define UIRCC_SR3_TMR_OUT   0x08 /* Timer timeout */
  94 #define UIRCC_SR3_TXUR      0x04 /* Transmit underrun */
  95 #define UIRCC_SR3_TX_DONE   0x01 /* Transmit all sent */
  96
  97 #define UIRCC_SR4           0x04 /* TX/RX data length counter low byte */
  98 #define UIRCC_SR5           0x05 /* TX/RX data length counter high byte */
  99
 100 #define UIRCC_SR8           0x08 /* Chip version */
 101
 102 #define UIRCC_SR9           0x09 /* System status 1 */
 103
 104 #define UIRCC_SR10          0x0a /* Modem select status */
 105
 106 #define UIRCC_SR12          0x0c /* Timer counter status (low byte) */
 107 #define UIRCC_SR13          0x0d /* Timer counter status (high byte) */
 108
 109 /* Private data for each instance */
 110 struct uircc_cb {
 111         struct irda_device idev;
 112
 113         __u8 cr3;                 /* Copy of register sr3 */
 114 };
 115
 116 #define CR3_SET
 117
 118 #endif
 119
 120
 121