?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
2.2.0-final
[davej-history.git] / drivers / video / atyfb.c
blob6a3625d23aa4d864ddd4bdd5834577a0228f0bb6
1 /* $Id: atyfb.c,v 1.98 1999/01/14 08:50:53 geert Exp $
2 * linux/drivers/video/atyfb.c -- Frame buffer device for ATI Mach64
3 *
4 * Copyright (C) 1997-1998 Geert Uytterhoeven
5 * Copyright (C) 1998 Bernd Harries
6 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
7 *
8 * This driver is partly based on the PowerMac console driver:
9 *
10 * Copyright (C) 1996 Paul Mackerras
11 *
12 * and on the PowerMac ATI/mach64 display driver:
13 *
14 * Copyright (C) 1997 Michael AK Tesch
15 *
16 * with work by Jon Howell
17 * Harry AC Eaton
18 * Anthony Tong <atong@uiuc.edu>
19 *
20 * This file is subject to the terms and conditions of the GNU General Public
21 * License. See the file COPYING in the main directory of this archive for
22 * more details.
23 */
24
25 /******************************************************************************
26
27 TODO:
28
29 - cursor support on all cards and all ramdacs.
30 - cursor parameters controlable via ioctl()s.
31 - guess PLL and MCLK based on the original PLL register values initialized
32 by the BIOS or Open Firmware (if they are initialized).
33
34 (Anyone to help with this?)
35
36 ******************************************************************************/
37
38
39 #include <linux/config.h>
40 #include <linux/module.h>
41 #include <linux/kernel.h>
42 #include <linux/errno.h>
43 #include <linux/string.h>
44 #include <linux/mm.h>
45 #include <linux/tty.h>
46 #include <linux/malloc.h>
47 #include <linux/vmalloc.h>
48 #include <linux/delay.h>
49 #include <linux/interrupt.h>
50 #include <linux/fb.h>
51 #include <linux/selection.h>
52 #include <linux/console.h>
53 #include <linux/init.h>
54 #include <linux/pci.h>
55 #include <linux/nvram.h>
56 #include <linux/kd.h>
57 #include <linux/vt_kern.h>
58
59 #ifdef CONFIG_FB_COMPAT_XPMAC
60 #include <asm/vc_ioctl.h>
61 #endif
62
63 #include <asm/io.h>
64
65 #if defined(CONFIG_PPC)
66 #include <asm/prom.h>
67 #include <asm/pci-bridge.h>
68 #include <video/macmodes.h>
69 #endif
70 #ifdef __sparc__
71 #include <asm/pbm.h>
72 #include <asm/fbio.h>
73 #include <asm/uaccess.h>
74 #endif
75
76 #include <video/fbcon.h>
77 #include <video/fbcon-cfb8.h>
78 #include <video/fbcon-cfb16.h>
79 #include <video/fbcon-cfb24.h>
80 #include <video/fbcon-cfb32.h>
81
82 #include "aty.h"
83
84
85 /*
86 * Debug flags.
87 */
88 #undef DEBUG
89
90
91 #define GUI_RESERVE 0x00001000
92
93
94 #ifndef __powerpc__
95 #define eieio() /* Enforce In-order Execution of I/O */
96 #endif
97
98 /* FIXME: remove the FAIL definition */
99 #define FAIL(x) do { printk(x "\n"); return -EINVAL; } while (0)
100
101
102 /*
103 * Elements of the Hardware specific atyfb_par structure
104 */
105
106 struct crtc {
107 u32 vxres;
108 u32 vyres;
109 u32 xoffset;
110 u32 yoffset;
111 u32 bpp;
112 u32 h_tot_disp;
113 u32 h_sync_strt_wid;
114 u32 v_tot_disp;
115 u32 v_sync_strt_wid;
116 u32 off_pitch;
117 u32 gen_cntl;
118 u32 dp_pix_width; /* acceleration */
119 u32 dp_chain_mask; /* acceleration */
120 };
121
122 struct pll_gx {
123 u8 m;
124 u8 n;
125 };
126
127 struct pll_ct {
128 u8 pll_ref_div;
129 u8 pll_gen_cntl;
130 u8 mclk_fb_div;
131 u8 pll_vclk_cntl;
132 u8 vclk_post_div;
133 u8 vclk_fb_div;
134 u8 pll_ext_cntl;
135 u32 dsp_config; /* Mach64 GTB DSP */
136 u32 dsp_on_off; /* Mach64 GTB DSP */
137 };
138
139
140 /*
141 * The Hardware parameters for each card
142 */
143
144 struct atyfb_par {
145 struct crtc crtc;
146 union {
147 struct pll_gx gx;
148 struct pll_ct ct;
149 } pll;
150 u32 accel_flags;
151 };
152
153 struct aty_cmap_regs {
154 u8 windex;
155 u8 lut;
156 u8 mask;
157 u8 rindex;
158 u8 cntl;
159 };
160
161 struct pci_mmap_map {
162 unsigned long voff;
163 unsigned long poff;
164 unsigned long size;
165 unsigned long prot_flag;
166 unsigned long prot_mask;
167 };
168
169 #define DEFAULT_CURSOR_BLINK_RATE (20)
170 #define CURSOR_DRAW_DELAY (2)
171
172 struct aty_cursor {
173 int enable;
174 int on;
175 int vbl_cnt;
176 int blink_rate;
177 u32 offset;
178 struct {
179 u16 x, y;
180 } pos, hot, size;
181 u32 color[2];
182 u8 bits[8][64];
183 u8 mask[8][64];
184 u8 *ram;
185 struct timer_list *timer;
186 };
187
188 struct fb_info_aty {
189 struct fb_info fb_info;
190 unsigned long ati_regbase_phys;
191 unsigned long ati_regbase;
192 unsigned long frame_buffer_phys;
193 unsigned long frame_buffer;
194 struct pci_mmap_map *mmap_map;
195 struct aty_cursor *cursor;
196 struct aty_cmap_regs *aty_cmap_regs;
197 struct { u8 red, green, blue, pad; } palette[256];
198 struct atyfb_par default_par;
199 struct atyfb_par current_par;
200 u32 total_vram;
201 u32 pll_per;
202 u32 mclk_per;
203 u16 chip_type;
204 #define Gx info->chip_type
205 u8 chip_rev;
206 #define Rev info->chip_rev
207 u8 bus_type;
208 u8 ram_type;
209 u8 dac_type;
210 u8 clk_type;
211 u8 mem_refresh_rate;
212 struct display disp;
213 struct display_switch dispsw;
214 union {
215 #ifdef FBCON_HAS_CFB16
216 u16 cfb16[16];
217 #endif
218 #ifdef FBCON_HAS_CFB24
219 u32 cfb24[16];
220 #endif
221 #ifdef FBCON_HAS_CFB32
222 u32 cfb32[16];
223 #endif
224 } fbcon_cmap;
225 u8 blitter_may_be_busy;
226 #ifdef __sparc__
227 u8 open;
228 u8 mmaped;
229 int vtconsole;
230 int consolecnt;
231 #endif
232 };
233
234
235 /*
236 * Frame buffer device API
237 */
238
239 static int atyfb_open(struct fb_info *info, int user);
240 static int atyfb_release(struct fb_info *info, int user);
241 static int atyfb_get_fix(struct fb_fix_screeninfo *fix, int con,
242 struct fb_info *fb);
243 static int atyfb_get_var(struct fb_var_screeninfo *var, int con,
244 struct fb_info *fb);
245 static int atyfb_set_var(struct fb_var_screeninfo *var, int con,
246 struct fb_info *fb);
247 static int atyfb_pan_display(struct fb_var_screeninfo *var, int con,
248 struct fb_info *fb);
249 static int atyfb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
250 struct fb_info *info);
251 static int atyfb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
252 struct fb_info *info);
253 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
254 u_long arg, int con, struct fb_info *info);
255 #ifdef __sparc__
256 static int atyfb_mmap(struct fb_info *info, struct file *file,
257 struct vm_area_struct *vma);
258 #endif
259
260
261 /*
262 * Interface to the low level console driver
263 */
264
265 static int atyfbcon_switch(int con, struct fb_info *fb);
266 static int atyfbcon_updatevar(int con, struct fb_info *fb);
267 static void atyfbcon_blank(int blank, struct fb_info *fb);
268
269
270 /*
271 * Text console acceleration
272 */
273
274 static void fbcon_aty_bmove(struct display *p, int sy, int sx, int dy, int dx,
275 int height, int width);
276 static void fbcon_aty_clear(struct vc_data *conp, struct display *p, int sy,
277 int sx, int height, int width);
278 #ifdef FBCON_HAS_CFB8
279 static struct display_switch fbcon_aty8;
280 static void fbcon_aty8_putc(struct vc_data *conp, struct display *p, int c,
281 int yy, int xx);
282 static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p,
283 const unsigned short *s, int count, int yy,
284 int xx);
285 #endif
286 #ifdef FBCON_HAS_CFB16
287 static struct display_switch fbcon_aty16;
288 static void fbcon_aty16_putc(struct vc_data *conp, struct display *p, int c,
289 int yy, int xx);
290 static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p,
291 const unsigned short *s, int count, int yy,
292 int xx);
293 #endif
294 #ifdef FBCON_HAS_CFB24
295 static struct display_switch fbcon_aty24;
296 static void fbcon_aty24_putc(struct vc_data *conp, struct display *p, int c,
297 int yy, int xx);
298 static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p,
299 const unsigned short *s, int count, int yy,
300 int xx);
301 #endif
302 #ifdef FBCON_HAS_CFB32
303 static struct display_switch fbcon_aty32;
304 static void fbcon_aty32_putc(struct vc_data *conp, struct display *p, int c,
305 int yy, int xx);
306 static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p,
307 const unsigned short *s, int count, int yy,
308 int xx);
309 #endif
310
311
312 /*
313 * Internal routines
314 */
315
316 static int aty_init(struct fb_info_aty *info, const char *name);
317 static struct aty_cursor *aty_init_cursor(struct fb_info_aty *fb);
318 #ifdef CONFIG_ATARI
319 static int store_video_par(char *videopar, unsigned char m64_num);
320 static char *strtoke(char *s, const char *ct);
321 #endif
322
323 static void reset_engine(const struct fb_info_aty *info);
324 static void init_engine(const struct atyfb_par *par, struct fb_info_aty *info);
325 static void aty_st_514(int offset, u8 val, const struct fb_info_aty *info);
326 static void aty_st_pll(int offset, u8 val, const struct fb_info_aty *info);
327 #if defined(__sparc__) || defined(DEBUG)
328 static u8 aty_ld_pll(int offset, const struct fb_info_aty *info);
329 #endif
330 static void aty_set_crtc(const struct fb_info_aty *info,
331 const struct crtc *crtc);
332 static int aty_var_to_crtc(const struct fb_info_aty *info,
333 const struct fb_var_screeninfo *var,
334 struct crtc *crtc);
335 static void aty_set_dac_514(const struct fb_info_aty *info, u32 bpp);
336 static int aty_crtc_to_var(const struct crtc *crtc,
337 struct fb_var_screeninfo *var);
338 static void aty_set_pll_gx(const struct fb_info_aty *info,
339 const struct pll_gx *pll);
340 static int aty_var_to_pll_18818(u32 vclk_per, struct pll_gx *pll);
341 static int aty_var_to_pll_514(u32 vclk_per, struct pll_gx *pll);
342 static int aty_pll_gx_to_var(const struct pll_gx *pll, u32 *vclk_per);
343 static void aty_set_pll_ct(const struct fb_info_aty *info,
344 const struct pll_ct *pll);
345 static int aty_dsp_gt(const struct fb_info_aty *info, u8 mclk_fb_div,
346 u8 mclk_post_div, u8 vclk_fb_div, u8 vclk_post_div,
347 u8 bpp, struct pll_ct *pll);
348 static int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
349 u8 bpp, struct pll_ct *pll);
350 static int aty_pll_ct_to_var(const struct pll_ct *pll, u32 *vclk_per);
351 static void atyfb_set_par(const struct atyfb_par *par,
352 struct fb_info_aty *info);
353 static int atyfb_decode_var(const struct fb_var_screeninfo *var,
354 struct atyfb_par *par,
355 const struct fb_info_aty *info);
356 static int atyfb_encode_var(struct fb_var_screeninfo *var,
357 const struct atyfb_par *par,
358 const struct fb_info_aty *info);
359 static void set_off_pitch(struct atyfb_par *par,
360 const struct fb_info_aty *info);
361 static int encode_fix(struct fb_fix_screeninfo *fix,
362 const struct atyfb_par *par,
363 const struct fb_info_aty *info);
364 static void atyfb_set_disp(struct display *disp, struct fb_info_aty *info,
365 int bpp, int accel);
366 static int atyfb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
367 u_int *transp, struct fb_info *fb);
368 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
369 u_int transp, struct fb_info *fb);
370 static void do_install_cmap(int con, struct fb_info *info);
371 #if defined(CONFIG_PPC)
372 static int read_aty_sense(const struct fb_info_aty *info);
373 #endif
374
375
376 /*
377 * Interface used by the world
378 */
379
380 void atyfb_init(void);
381 #ifdef CONFIG_FB_OF
382 void atyfb_of_init(struct device_node *dp);
383 #endif
384 void atyfb_setup(char *options, int *ints);
385
386
387 static int currcon = 0;
388
389 static struct fb_ops atyfb_ops = {
390 atyfb_open, atyfb_release, atyfb_get_fix, atyfb_get_var, atyfb_set_var,
391 atyfb_get_cmap, atyfb_set_cmap, atyfb_pan_display, atyfb_ioctl,
392 #ifdef __sparc__
393 atyfb_mmap
394 #else
395 NULL
396 #endif
397 };
398
399 static char atyfb_name[16] = "ATY Mach64";
400 static char fontname[40] __initdata = { 0 };
401 static char curblink __initdata = 1;
402 static char noaccel __initdata = 0;
403 static u32 default_vram __initdata = 0;
404 static int default_pll __initdata = 0;
405 static int default_mclk __initdata = 0;
406
407 static const u32 ref_clk_per = 1000000000000ULL/14318180;
408
409 #if defined(CONFIG_PPC)
410 static int default_vmode __initdata = VMODE_NVRAM;
411 static int default_cmode __initdata = CMODE_NVRAM;
412 #endif
413
414 #ifdef CONFIG_ATARI
415 static unsigned int mach64_count __initdata = 0;
416 static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
417 static unsigned long phys_size[FB_MAX] __initdata = { 0, };
418 static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
419 #endif
420
421
422 static struct aty_features {
423 u16 pci_id;
424 u16 chip_type;
425 const char *name;
426 } aty_features[] __initdata = {
427 /* mach64GX family */
428 { 0x4758, 0x00d7, "mach64GX (ATI888GX00)" },
429 { 0x4358, 0x0057, "mach64CX (ATI888CX00)" },
430
431 /* mach64CT family */
432 { 0x4354, 0x4354, "mach64CT (ATI264CT)" },
433 { 0x4554, 0x4554, "mach64ET (ATI264ET)" },
434
435 /* mach64CT family / mach64VT class */
436 { 0x5654, 0x5654, "mach64VT (ATI264VT)" },
437 { 0x5655, 0x5655, "mach64VTB (ATI264VTB)" },
438 { 0x5656, 0x5656, "mach64VT4 (ATI264VT4)" },
439
440 /* mach64CT family / mach64GT (3D RAGE) class */
441 { 0x4c42, 0x4c42, "3D RAGE LT PRO (AGP)" },
442 { 0x4c42, 0x4c44, "3D RAGE LT PRO" },
443 { 0x4c42, 0x4c47, "3D RAGE LT PRO" },
444 { 0x4c42, 0x4c49, "3D RAGE LT PRO" },
445 { 0x4c42, 0x4c50, "3D RAGE LT PRO" },
446 { 0x4c54, 0x4c54, "3D RAGE LT" },
447 { 0x4754, 0x4754, "3D RAGE (GT)" },
448 { 0x4755, 0x4755, "3D RAGE II+ (GTB)" },
449 { 0x4756, 0x4756, "3D RAGE IIC (PCI)" },
450 { 0x4757, 0x4757, "3D RAGE IIC (AGP)" },
451 { 0x475a, 0x475a, "3D RAGE IIC (AGP)" },
452 { 0x4742, 0x4742, "3D RAGE PRO (BGA, AGP)" },
453 { 0x4744, 0x4744, "3D RAGE PRO (BGA, AGP, 1x only)" },
454 { 0x4749, 0x4749, "3D RAGE PRO (BGA, PCI)" },
455 { 0x4750, 0x4750, "3D RAGE PRO (PQFP, PCI)" },
456 { 0x4751, 0x4751, "3D RAGE PRO (PQFP, PCI, limited 3D)" },
457 };
458
459 static const char *aty_gx_ram[8] __initdata = {
460 "DRAM", "VRAM", "VRAM", "DRAM", "DRAM", "VRAM", "VRAM", "RESV"
461 };
462
463 static const char *aty_ct_ram[8] __initdata = {
464 "OFF", "DRAM", "EDO", "EDO", "SDRAM", "SGRAM", "WRAM", "RESV"
465 };
466
467
468 static inline u32 aty_ld_le32(volatile unsigned int regindex,
469 const struct fb_info_aty *info)
470 {
471 unsigned long temp;
472 u32 val;
473
474 #if defined(__powerpc__)
475 temp = info->ati_regbase;
476 asm("lwbrx %0,%1,%2" : "=r"(val) : "r" (regindex), "r" (temp));
477 #elif defined(__sparc_v9__)
478 temp = info->ati_regbase + regindex;
479 asm("lduwa [%1] %2, %0" : "=r" (val) : "r" (temp), "i" (ASI_PL));
480 #else
481 temp = info->ati_regbase+regindex;
482 val = le32_to_cpu(*((volatile u32 *)(temp)));
483 #endif
484 return val;
485 }
486
487 static inline void aty_st_le32(volatile unsigned int regindex, u32 val,
488 const struct fb_info_aty *info)
489 {
490 unsigned long temp;
491
492 #if defined(__powerpc__)
493 temp = info->ati_regbase;
494 asm("stwbrx %0,%1,%2" : : "r" (val), "r" (regindex), "r" (temp) :
495 "memory");
496 #elif defined(__sparc_v9__)
497 temp = info->ati_regbase + regindex;
498 asm("stwa %0, [%1] %2" : : "r" (val), "r" (temp), "i" (ASI_PL) : "memory");
499 #else
500 temp = info->ati_regbase+regindex;
501 *((volatile u32 *)(temp)) = cpu_to_le32(val);
502 #endif
503 }
504
505 static inline u8 aty_ld_8(volatile unsigned int regindex,
506 const struct fb_info_aty *info)
507 {
508 return *(volatile u8 *)(info->ati_regbase+regindex);
509 }
510
511 static inline void aty_st_8(volatile unsigned int regindex, u8 val,
512 const struct fb_info_aty *info)
513 {
514 *(volatile u8 *)(info->ati_regbase+regindex) = val;
515 }
516
517
518 /*
519 * Generic Mach64 routines
520 */
521
522 /*
523 * All writes to draw engine registers are automatically routed through a
524 * 32-bit-wide, 16-entry-deep command FIFO ...
525 * Register writes to registers with DWORD offsets less than 40h are not
526 * FIFOed.
527 * (from Chapter 5 of the Mach64 Programmer's Guide)
528 */
529
530 static inline void wait_for_fifo(u16 entries, const struct fb_info_aty *info)
531 {
532 while ((aty_ld_le32(FIFO_STAT, info) & 0xffff) >
533 ((u32)(0x8000 >> entries)));
534 }
535
536 static inline void wait_for_idle(struct fb_info_aty *info)
537 {
538 wait_for_fifo(16, info);
539 while ((aty_ld_le32(GUI_STAT, info) & 1)!= 0);
540 info->blitter_may_be_busy = 0;
541 }
542
543 static void reset_engine(const struct fb_info_aty *info)
544 {
545 /* reset engine */
546 aty_st_le32(GEN_TEST_CNTL,
547 aty_ld_le32(GEN_TEST_CNTL, info) & ~GUI_ENGINE_ENABLE, info);
548 /* enable engine */
549 aty_st_le32(GEN_TEST_CNTL,
550 aty_ld_le32(GEN_TEST_CNTL, info) | GUI_ENGINE_ENABLE, info);
551 /* ensure engine is not locked up by clearing any FIFO or */
552 /* HOST errors */
553 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, info) | BUS_HOST_ERR_ACK |
554 BUS_FIFO_ERR_ACK, info);
555 }
556
557 static void init_engine(const struct atyfb_par *par, struct fb_info_aty *info)
558 {
559 u32 pitch_value;
560
561 /* determine modal information from global mode structure */
562 pitch_value = par->crtc.vxres;
563
564 if (par->crtc.bpp == 24) {
565 /* In 24 bpp, the engine is in 8 bpp - this requires that all */
566 /* horizontal coordinates and widths must be adjusted */
567 pitch_value = pitch_value * 3;
568 }
569
570 /* Reset engine, enable, and clear any engine errors */
571 reset_engine(info);
572 /* Ensure that vga page pointers are set to zero - the upper */
573 /* page pointers are set to 1 to handle overflows in the */
574 /* lower page */
575 aty_st_le32(MEM_VGA_WP_SEL, 0x00010000, info);
576 aty_st_le32(MEM_VGA_RP_SEL, 0x00010000, info);
577
578 /* ---- Setup standard engine context ---- */
579
580 /* All GUI registers here are FIFOed - therefore, wait for */
581 /* the appropriate number of empty FIFO entries */
582 wait_for_fifo(14, info);
583
584 /* enable all registers to be loaded for context loads */
585 aty_st_le32(CONTEXT_MASK, 0xFFFFFFFF, info);
586
587 /* set destination pitch to modal pitch, set offset to zero */
588 aty_st_le32(DST_OFF_PITCH, (pitch_value / 8) << 22, info);
589
590 /* zero these registers (set them to a known state) */
591 aty_st_le32(DST_Y_X, 0, info);
592 aty_st_le32(DST_HEIGHT, 0, info);
593 aty_st_le32(DST_BRES_ERR, 0, info);
594 aty_st_le32(DST_BRES_INC, 0, info);
595 aty_st_le32(DST_BRES_DEC, 0, info);
596
597 /* set destination drawing attributes */
598 aty_st_le32(DST_CNTL, DST_LAST_PEL | DST_Y_TOP_TO_BOTTOM |
599 DST_X_LEFT_TO_RIGHT, info);
600
601 /* set source pitch to modal pitch, set offset to zero */
602 aty_st_le32(SRC_OFF_PITCH, (pitch_value / 8) << 22, info);
603
604 /* set these registers to a known state */
605 aty_st_le32(SRC_Y_X, 0, info);
606 aty_st_le32(SRC_HEIGHT1_WIDTH1, 1, info);
607 aty_st_le32(SRC_Y_X_START, 0, info);
608 aty_st_le32(SRC_HEIGHT2_WIDTH2, 1, info);
609
610 /* set source pixel retrieving attributes */
611 aty_st_le32(SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT, info);
612
613 /* set host attributes */
614 wait_for_fifo(13, info);
615 aty_st_le32(HOST_CNTL, 0, info);
616
617 /* set pattern attributes */
618 aty_st_le32(PAT_REG0, 0, info);
619 aty_st_le32(PAT_REG1, 0, info);
620 aty_st_le32(PAT_CNTL, 0, info);
621
622 /* set scissors to modal size */
623 aty_st_le32(SC_LEFT, 0, info);
624 aty_st_le32(SC_TOP, 0, info);
625 aty_st_le32(SC_BOTTOM, par->crtc.vyres-1, info);
626 aty_st_le32(SC_RIGHT, pitch_value-1, info);
627
628 /* set background color to minimum value (usually BLACK) */
629 aty_st_le32(DP_BKGD_CLR, 0, info);
630
631 /* set foreground color to maximum value (usually WHITE) */
632 aty_st_le32(DP_FRGD_CLR, 0xFFFFFFFF, info);
633
634 /* set write mask to effect all pixel bits */
635 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF, info);
636
637 /* set foreground mix to overpaint and background mix to */
638 /* no-effect */
639 aty_st_le32(DP_MIX, FRGD_MIX_S | BKGD_MIX_D, info);
640
641 /* set primary source pixel channel to foreground color */
642 /* register */
643 aty_st_le32(DP_SRC, FRGD_SRC_FRGD_CLR, info);
644
645 /* set compare functionality to false (no-effect on */
646 /* destination) */
647 wait_for_fifo(3, info);
648 aty_st_le32(CLR_CMP_CLR, 0, info);
649 aty_st_le32(CLR_CMP_MASK, 0xFFFFFFFF, info);
650 aty_st_le32(CLR_CMP_CNTL, 0, info);
651
652 /* set pixel depth */
653 wait_for_fifo(2, info);
654 aty_st_le32(DP_PIX_WIDTH, par->crtc.dp_pix_width, info);
655 aty_st_le32(DP_CHAIN_MASK, par->crtc.dp_chain_mask, info);
656
657 wait_for_fifo(5, info);
658 aty_st_le32(SCALE_3D_CNTL, 0, info);
659 aty_st_le32(Z_CNTL, 0, info);
660 aty_st_le32(CRTC_INT_CNTL, aty_ld_le32(CRTC_INT_CNTL, info) & ~0x20, info);
661 aty_st_le32(GUI_TRAJ_CNTL, 0x100023, info);
662
663 /* insure engine is idle before leaving */
664 wait_for_idle(info);
665 }
666
667 static void aty_st_514(int offset, u8 val, const struct fb_info_aty *info)
668 {
669 aty_st_8(DAC_CNTL, 1, info);
670 /* right addr byte */
671 aty_st_8(DAC_W_INDEX, offset & 0xff, info);
672 /* left addr byte */
673 aty_st_8(DAC_DATA, (offset >> 8) & 0xff, info);
674 eieio();
675 aty_st_8(DAC_MASK, val, info);
676 eieio();
677 aty_st_8(DAC_CNTL, 0, info);
678 }
679
680 static void aty_st_pll(int offset, u8 val, const struct fb_info_aty *info)
681 {
682 /* write addr byte */
683 aty_st_8(CLOCK_CNTL + 1, (offset << 2) | PLL_WR_EN, info);
684 eieio();
685 /* write the register value */
686 aty_st_8(CLOCK_CNTL + 2, val, info);
687 eieio();
688 aty_st_8(CLOCK_CNTL + 1, (offset << 2) & ~PLL_WR_EN, info);
689 }
690
691 #if defined(__sparc__) || defined(DEBUG)
692 static u8 aty_ld_pll(int offset, const struct fb_info_aty *info)
693 {
694 u8 res;
695
696 /* write addr byte */
697 aty_st_8(CLOCK_CNTL + 1, (offset << 2), info);
698 eieio();
699 /* read the register value */
700 res = aty_ld_8(CLOCK_CNTL + 2, info);
701 eieio();
702 return res;
703 }
704 #endif
705
706 #if defined(CONFIG_PPC)
707
708 /*
709 * Apple monitor sense
710 */
711
712 static int read_aty_sense(const struct fb_info_aty *info)
713 {
714 int sense, i;
715
716 aty_st_le32(GP_IO, 0x31003100, info); /* drive outputs high */
717 __delay(200);
718 aty_st_le32(GP_IO, 0, info); /* turn off outputs */
719 __delay(2000);
720 i = aty_ld_le32(GP_IO, info); /* get primary sense value */
721 sense = ((i & 0x3000) >> 3) | (i & 0x100);
722
723 /* drive each sense line low in turn and collect the other 2 */
724 aty_st_le32(GP_IO, 0x20000000, info); /* drive A low */
725 __delay(2000);
726 i = aty_ld_le32(GP_IO, info);
727 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
728 aty_st_le32(GP_IO, 0x20002000, info); /* drive A high again */
729 __delay(200);
730
731 aty_st_le32(GP_IO, 0x10000000, info); /* drive B low */
732 __delay(2000);
733 i = aty_ld_le32(GP_IO, info);
734 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
735 aty_st_le32(GP_IO, 0x10001000, info); /* drive B high again */
736 __delay(200);
737
738 aty_st_le32(GP_IO, 0x01000000, info); /* drive C low */
739 __delay(2000);
740 sense |= (aty_ld_le32(GP_IO, info) & 0x3000) >> 12;
741 aty_st_le32(GP_IO, 0, info); /* turn off outputs */
742
743 return sense;
744 }
745
746 #endif /* defined(CONFIG_PPC) */
747
748 /* ------------------------------------------------------------------------- */
749
750 /*
751 * Hardware Cursor support.
752 */
753
754 static u8 cursor_pixel_map[2] = { 0, 15 };
755 static u8 cursor_color_map[2] = { 0, 0xff };
756
757 static u8 cursor_bits_lookup[16] =
758 {
759 0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54,
760 0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55
761 };
762
763 static u8 cursor_mask_lookup[16] =
764 {
765 0xaa, 0x2a, 0x8a, 0x0a, 0xa2, 0x22, 0x82, 0x02,
766 0xa8, 0x28, 0x88, 0x08, 0xa0, 0x20, 0x80, 0x00
767 };
768
769 static void
770 aty_set_cursor_color(struct fb_info_aty *fb, u8 *pixel,
771 u8 *red, u8 *green, u8 *blue)
772 {
773 struct aty_cursor *c = fb->cursor;
774 int i;
775
776 if (!c)
777 return;
778
779 #ifdef __sparc__
780 if (fb->mmaped && currcon == fb->vtconsole)
781 return;
782 #endif
783
784 for (i = 0; i < 2; i++) {
785 c->color[i] = (u32)red[i] << 24;
786 c->color[i] |= (u32)green[i] << 16;
787 c->color[i] |= (u32)blue[i] << 8;
788 c->color[i] |= (u32)pixel[i];
789 }
790
791 wait_for_fifo(2, fb);
792 aty_st_le32(CUR_CLR0, c->color[0], fb);
793 aty_st_le32(CUR_CLR1, c->color[1], fb);
794 }
795
796 static void
797 aty_set_cursor_shape(struct fb_info_aty *fb)
798 {
799 struct aty_cursor *c = fb->cursor;
800 u8 *ram, m, b;
801 int x, y;
802
803 if (!c)
804 return;
805
806 #ifdef __sparc__
807 if (fb->mmaped && currcon == fb->vtconsole)
808 return;
809 #endif
810
811 ram = c->ram;
812 for (y = 0; y < c->size.y; y++) {
813 for (x = 0; x < c->size.x >> 2; x++) {
814 m = c->mask[x][y];
815 b = c->bits[x][y];
816 *ram++ = cursor_mask_lookup[m >> 4] |
817 cursor_bits_lookup[(b & m) >> 4];
818 *ram++ = cursor_mask_lookup[m & 0x0f] |
819 cursor_bits_lookup[(b & m) & 0x0f];
820 }
821 for ( ; x < 8; x++) {
822 *ram++ = 0xaa;
823 *ram++ = 0xaa;
824 }
825 }
826 memset(ram, 0xaa, (64 - c->size.y) * 16);
827 }
828
829 static void
830 aty_set_cursor(struct fb_info_aty *fb, int on)
831 {
832 struct atyfb_par *par = &fb->current_par;
833 struct aty_cursor *c = fb->cursor;
834 u16 xoff, yoff;
835 int x, y;
836
837 if (!c)
838 return;
839
840 #ifdef __sparc__
841 if (fb->mmaped && currcon == fb->vtconsole)
842 return;
843 #endif
844
845 if (on) {
846 x = c->pos.x - c->hot.x - par->crtc.xoffset;
847 if (x < 0) {
848 xoff = -x;
849 x = 0;
850 } else {
851 xoff = 0;
852 }
853
854 y = c->pos.y - c->hot.y - par->crtc.yoffset;
855 if (y < 0) {
856 yoff = -y;
857 y = 0;
858 } else {
859 yoff = 0;
860 }
861
862 wait_for_fifo(4, fb);
863 aty_st_le32(CUR_OFFSET, (c->offset >> 3) + (yoff << 1), fb);
864 aty_st_le32(CUR_HORZ_VERT_OFF,
865 ((u32)(64 - c->size.y + yoff) << 16) | xoff, fb);
866 aty_st_le32(CUR_HORZ_VERT_POSN, ((u32)y << 16) | x, fb);
867 aty_st_le32(GEN_TEST_CNTL, aty_ld_le32(GEN_TEST_CNTL, fb)
868 | HWCURSOR_ENABLE, fb);
869 } else {
870 wait_for_fifo(1, fb);
871 aty_st_le32(GEN_TEST_CNTL,
872 aty_ld_le32(GEN_TEST_CNTL, fb) & ~HWCURSOR_ENABLE,
873 fb);
874 }
875 if (fb->blitter_may_be_busy)
876 wait_for_idle(fb);
877 }
878
879 static void
880 aty_cursor_timer_handler(unsigned long dev_addr)
881 {
882 struct fb_info_aty *fb = (struct fb_info_aty *)dev_addr;
883
884 if (!fb->cursor)
885 return;
886
887 if (!fb->cursor->enable)
888 goto out;
889
890 if (fb->cursor->vbl_cnt && --fb->cursor->vbl_cnt == 0) {
891 fb->cursor->on ^= 1;
892 aty_set_cursor(fb, fb->cursor->on);
893 fb->cursor->vbl_cnt = fb->cursor->blink_rate;
894 }
895
896 out:
897 fb->cursor->timer->expires = jiffies + (HZ / 50);
898 add_timer(fb->cursor->timer);
899 }
900
901 static void
902 atyfb_cursor(struct display *p, int mode, int x, int y)
903 {
904 struct fb_info_aty *fb = (struct fb_info_aty *)p->fb_info;
905 struct aty_cursor *c = fb->cursor;
906
907 if (!c)
908 return;
909
910 #ifdef __sparc__
911 if (fb->mmaped && currcon == fb->vtconsole)
912 return;
913 #endif
914
915 x *= fontwidth(p);
916 y *= fontheight(p);
917 if (c->pos.x == x && c->pos.y == y && (mode == CM_ERASE) == !c->enable)
918 return;
919
920 c->enable = 0;
921 if (c->on)
922 aty_set_cursor(fb, 0);
923 c->pos.x = x;
924 c->pos.y = y;
925
926 switch (mode) {
927 case CM_ERASE:
928 c->on = 0;
929 break;
930
931 case CM_DRAW:
932 case CM_MOVE:
933 if (c->on)
934 aty_set_cursor(fb, 1);
935 else
936 c->vbl_cnt = CURSOR_DRAW_DELAY;
937 c->enable = 1;
938 break;
939 }
940 }
941
942 __initfunc(static struct aty_cursor *
943 aty_init_cursor(struct fb_info_aty *fb))
944 {
945 struct aty_cursor *cursor;
946 unsigned long addr;
947
948 cursor = kmalloc(sizeof(struct aty_cursor), GFP_ATOMIC);
949 if (!cursor)
950 return 0;
951 memset(cursor, 0, sizeof(*cursor));
952
953 cursor->timer = kmalloc(sizeof(*cursor->timer), GFP_KERNEL);
954 if (!cursor->timer) {
955 kfree(cursor);
956 return 0;
957 }
958 memset(cursor->timer, 0, sizeof(*cursor->timer));
959
960 cursor->blink_rate = DEFAULT_CURSOR_BLINK_RATE;
961 fb->total_vram -= PAGE_SIZE;
962 cursor->offset = fb->total_vram;
963
964 #ifdef __sparc__
965 addr = fb->frame_buffer - 0x800000 + cursor->offset;
966 cursor->ram = (u8 *)addr;
967 #else
968 #ifdef __BIG_ENDIAN
969 addr = fb->frame_buffer_phys - 0x800000 + cursor->offset;
970 cursor->ram = (u8 *)ioremap(addr, 1024);
971 #else
972 addr = fb->frame_buffer + cursor->offset;
973 cursor->ram = (u8 *)addr;
974 #endif
975 #endif
976
977 if (! cursor->ram) {
978 kfree(cursor);
979 return NULL;
980 }
981
982 if (curblink) {
983 init_timer(cursor->timer);
984 cursor->timer->expires = jiffies + (HZ / 50);
985 cursor->timer->data = (unsigned long)fb;
986 cursor->timer->function = aty_cursor_timer_handler;
987 add_timer(cursor->timer);
988 }
989
990 return cursor;
991 }
992
993 static int
994 atyfb_set_font(struct display *d, int width, int height)
995 {
996 struct fb_info_aty *fb = (struct fb_info_aty *)d->fb_info;
997 struct aty_cursor *c = fb->cursor;
998 int i, j;
999
1000 if (c) {
1001 if (!width || !height) {
1002 width = 8;
1003 height = 16;
1004 }
1005
1006 c->hot.x = 0;
1007 c->hot.y = 0;
1008 c->size.x = width;
1009 c->size.y = height;
1010
1011 memset(c->bits, 0xff, sizeof(c->bits));
1012 memset(c->mask, 0, sizeof(c->mask));
1013
1014 for (i = 0, j = width; j >= 0; j -= 8, i++) {
1015 c->mask[i][height-2] = (j >= 8) ? 0xff : (0xff << (8 - j));
1016 c->mask[i][height-1] = (j >= 8) ? 0xff : (0xff << (8 - j));
1017 }
1018
1019 aty_set_cursor_color(fb, cursor_pixel_map, cursor_color_map,
1020 cursor_color_map, cursor_color_map);
1021 aty_set_cursor_shape(fb);
1022 }
1023 return 1;
1024 }
1025
1026
1027
1028
1029 /* ------------------------------------------------------------------------- */
1030
1031 /*
1032 * CRTC programming
1033 */
1034
1035 static void aty_set_crtc(const struct fb_info_aty *info,
1036 const struct crtc *crtc)
1037 {
1038 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, info);
1039 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, info);
1040 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, info);
1041 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, info);
1042 aty_st_le32(CRTC_VLINE_CRNT_VLINE, 0, info);
1043 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, info);
1044 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, info);
1045 }
1046
1047 static int aty_var_to_crtc(const struct fb_info_aty *info,
1048 const struct fb_var_screeninfo *var,
1049 struct crtc *crtc)
1050 {
1051 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
1052 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1053 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1054 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1055 u32 pix_width, dp_pix_width, dp_chain_mask;
1056
1057 /* input */
1058 xres = var->xres;
1059 yres = var->yres;
1060 vxres = var->xres_virtual;
1061 vyres = var->yres_virtual;
1062 xoffset = var->xoffset;
1063 yoffset = var->yoffset;
1064 bpp = var->bits_per_pixel;
1065 left = var->left_margin;
1066 right = var->right_margin;
1067 upper = var->upper_margin;
1068 lower = var->lower_margin;
1069 hslen = var->hsync_len;
1070 vslen = var->vsync_len;
1071 sync = var->sync;
1072 vmode = var->vmode;
1073
1074 /* convert (and round up) and validate */
1075 xres = (xres+7) & ~7;
1076 xoffset = (xoffset+7) & ~7;
1077 vxres = (vxres+7) & ~7;
1078 if (vxres < xres+xoffset)
1079 vxres = xres+xoffset;
1080 h_disp = xres/8-1;
1081 if (h_disp > 0xff)
1082 FAIL("h_disp too large");
1083 h_sync_strt = h_disp+(right/8);
1084 if (h_sync_strt > 0x1ff)
1085 FAIL("h_sync_start too large");
1086 h_sync_dly = right & 7;
1087 h_sync_wid = (hslen+7)/8;
1088 if (h_sync_wid > 0x1f)
1089 FAIL("h_sync_wid too large");
1090 h_total = h_sync_strt+h_sync_wid+(h_sync_dly+left+7)/8;
1091 if (h_total > 0x1ff)
1092 FAIL("h_total too large");
1093 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1094
1095 if (vyres < yres+yoffset)
1096 vyres = yres+yoffset;
1097 v_disp = yres-1;
1098 if (v_disp > 0x7ff)
1099 FAIL("v_disp too large");
1100 v_sync_strt = v_disp+lower;
1101 if (v_sync_strt > 0x7ff)
1102 FAIL("v_sync_strt too large");
1103 v_sync_wid = vslen;
1104 if (v_sync_wid > 0x1f)
1105 FAIL("v_sync_wid too large");
1106 v_total = v_sync_strt+v_sync_wid+upper;
1107 if (v_total > 0x7ff)
1108 FAIL("v_total too large");
1109 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1110
1111 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
1112
1113 if (bpp <= 8) {
1114 bpp = 8;
1115 pix_width = CRTC_PIX_WIDTH_8BPP;
1116 dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;
1117 dp_chain_mask = 0x8080;
1118 } else if (bpp <= 16) {
1119 bpp = 16;
1120 pix_width = CRTC_PIX_WIDTH_15BPP;
1121 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
1122 BYTE_ORDER_LSB_TO_MSB;
1123 dp_chain_mask = 0x4210;
1124 } else if ((bpp <= 24) && (Gx != GX_CHIP_ID) && (Gx != CX_CHIP_ID)) {
1125 bpp = 24;
1126 pix_width = CRTC_PIX_WIDTH_24BPP;
1127 dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;
1128 dp_chain_mask = 0x8080;
1129 } else if (bpp <= 32) {
1130 bpp = 32;
1131 pix_width = CRTC_PIX_WIDTH_32BPP;
1132 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
1133 BYTE_ORDER_LSB_TO_MSB;
1134 dp_chain_mask = 0x8080;
1135 } else
1136 FAIL("invalid bpp");
1137
1138 if (vxres*vyres*bpp/8 > info->total_vram)
1139 FAIL("not enough video RAM");
1140
1141 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1142 FAIL("invalid vmode");
1143
1144 /* output */
1145 crtc->vxres = vxres;
1146 crtc->vyres = vyres;
1147 crtc->xoffset = xoffset;
1148 crtc->yoffset = yoffset;
1149 crtc->bpp = bpp;
1150 crtc->h_tot_disp = h_total | (h_disp<<16);
1151 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
1152 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) |
1153 (h_sync_pol<<21);
1154 crtc->v_tot_disp = v_total | (v_disp<<16);
1155 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
1156 crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
1157 crtc->gen_cntl = pix_width | c_sync | CRTC_EXT_DISP_EN | CRTC_ENABLE;
1158 if ((Gx == CT_CHIP_ID) || (Gx == ET_CHIP_ID) ||
1159 ((Gx == VT_CHIP_ID || Gx == GT_CHIP_ID) && !(Rev & 0x07))) {
1160 /* Not VTB/GTB */
1161 /* FIXME: magic FIFO values */
1162 crtc->gen_cntl |= aty_ld_le32(CRTC_GEN_CNTL, info) & 0x000e0000;
1163 }
1164 crtc->dp_pix_width = dp_pix_width;
1165 crtc->dp_chain_mask = dp_chain_mask;
1166
1167 return 0;
1168 }
1169
1170 static void aty_set_dac_514(const struct fb_info_aty *info, u32 bpp)
1171 {
1172 static struct {
1173 u8 pixel_dly;
1174 u8 misc2_cntl;
1175 u8 pixel_rep;
1176 u8 pixel_cntl_index;
1177 u8 pixel_cntl_v1;
1178 } tab[3] = {
1179 { 0, 0x41, 0x03, 0x71, 0x45 }, /* 8 bpp */
1180 { 0, 0x45, 0x04, 0x0c, 0x01 }, /* 555 */
1181 { 0, 0x45, 0x06, 0x0e, 0x00 }, /* XRGB */
1182 };
1183 int i;
1184
1185 switch (bpp) {
1186 case 8:
1187 default:
1188 i = 0;
1189 break;
1190 case 16:
1191 i = 1;
1192 break;
1193 case 32:
1194 i = 2;
1195 break;
1196 }
1197 aty_st_514(0x90, 0x00, info); /* VRAM Mask Low */
1198 aty_st_514(0x04, tab[i].pixel_dly, info); /* Horizontal Sync Control */
1199 aty_st_514(0x05, 0x00, info); /* Power Management */
1200 aty_st_514(0x02, 0x01, info); /* Misc Clock Control */
1201 aty_st_514(0x71, tab[i].misc2_cntl, info); /* Misc Control 2 */
1202 aty_st_514(0x0a, tab[i].pixel_rep, info); /* Pixel Format */
1203 aty_st_514(tab[i].pixel_cntl_index, tab[i].pixel_cntl_v1, info);
1204 /* Misc Control 2 / 16 BPP Control / 32 BPP Control */
1205 }
1206
1207 static int aty_crtc_to_var(const struct crtc *crtc,
1208 struct fb_var_screeninfo *var)
1209 {
1210 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1211 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1212 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1213 u32 pix_width;
1214
1215 /* input */
1216 h_total = crtc->h_tot_disp & 0x1ff;
1217 h_disp = (crtc->h_tot_disp>>16) & 0xff;
1218 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) |
1219 ((crtc->h_sync_strt_wid>>4) & 0x100);
1220 h_sync_dly = (crtc->h_sync_strt_wid>>8) & 0x7;
1221 h_sync_wid = (crtc->h_sync_strt_wid>>16) & 0x1f;
1222 h_sync_pol = (crtc->h_sync_strt_wid>>21) & 0x1;
1223 v_total = crtc->v_tot_disp & 0x7ff;
1224 v_disp = (crtc->v_tot_disp>>16) & 0x7ff;
1225 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1226 v_sync_wid = (crtc->v_sync_strt_wid>>16) & 0x1f;
1227 v_sync_pol = (crtc->v_sync_strt_wid>>21) & 0x1;
1228 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1229 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1230
1231 /* convert */
1232 xres = (h_disp+1)*8;
1233 yres = v_disp+1;
1234 left = (h_total-h_sync_strt-h_sync_wid)*8-h_sync_dly;
1235 right = (h_sync_strt-h_disp)*8+h_sync_dly;
1236 hslen = h_sync_wid*8;
1237 upper = v_total-v_sync_strt-v_sync_wid;
1238 lower = v_sync_strt-v_disp;
1239 vslen = v_sync_wid;
1240 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1241 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1242 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1243
1244 switch (pix_width) {
1245 #if 0
1246 case CRTC_PIX_WIDTH_4BPP:
1247 bpp = 4;
1248 var->red.offset = 0;
1249 var->red.length = 8;
1250 var->green.offset = 0;
1251 var->green.length = 8;
1252 var->blue.offset = 0;
1253 var->blue.length = 8;
1254 var->transp.offset = 0;
1255 var->transp.length = 0;
1256 break;
1257 #endif
1258 case CRTC_PIX_WIDTH_8BPP:
1259 bpp = 8;
1260 var->red.offset = 0;
1261 var->red.length = 8;
1262 var->green.offset = 0;
1263 var->green.length = 8;
1264 var->blue.offset = 0;
1265 var->blue.length = 8;
1266 var->transp.offset = 0;
1267 var->transp.length = 0;
1268 break;
1269 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1270 bpp = 16;
1271 var->red.offset = 10;
1272 var->red.length = 5;
1273 var->green.offset = 5;
1274 var->green.length = 5;
1275 var->blue.offset = 0;
1276 var->blue.length = 5;
1277 var->transp.offset = 0;
1278 var->transp.length = 0;
1279 break;
1280 #if 0
1281 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1282 bpp = 16;
1283 var->red.offset = 11;
1284 var->red.length = 5;
1285 var->green.offset = 6;
1286 var->green.length = 6;
1287 var->blue.offset = 0;
1288 var->blue.length = 5;
1289 var->transp.offset = 0;
1290 var->transp.length = 0;
1291 break;
1292 #endif
1293 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1294 bpp = 24;
1295 var->red.offset = 16;
1296 var->red.length = 8;
1297 var->green.offset = 8;
1298 var->green.length = 8;
1299 var->blue.offset = 0;
1300 var->blue.length = 8;
1301 var->transp.offset = 0;
1302 var->transp.length = 0;
1303 break;
1304 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1305 bpp = 32;
1306 var->red.offset = 16;
1307 var->red.length = 8;
1308 var->green.offset = 8;
1309 var->green.length = 8;
1310 var->blue.offset = 0;
1311 var->blue.length = 8;
1312 var->transp.offset = 24;
1313 var->transp.length = 8;
1314 break;
1315 default:
1316 FAIL("Invalid pixel width");
1317 }
1318
1319 /* output */
1320 var->xres = xres;
1321 var->yres = yres;
1322 var->xres_virtual = crtc->vxres;
1323 var->yres_virtual = crtc->vyres;
1324 var->bits_per_pixel = bpp;
1325 var->xoffset = crtc->xoffset;
1326 var->yoffset = crtc->yoffset;
1327 var->left_margin = left;
1328 var->right_margin = right;
1329 var->upper_margin = upper;
1330 var->lower_margin = lower;
1331 var->hsync_len = hslen;
1332 var->vsync_len = vslen;
1333 var->sync = sync;
1334 var->vmode = FB_VMODE_NONINTERLACED;
1335
1336 return 0;
1337 }
1338
1339 /* ------------------------------------------------------------------------- */
1340
1341 /*
1342 * PLL programming (Mach64 GX family)
1343 *
1344 * FIXME: use function pointer tables instead of switch statements
1345 */
1346
1347 static void aty_set_pll_gx(const struct fb_info_aty *info,
1348 const struct pll_gx *pll)
1349 {
1350 switch (info->clk_type) {
1351 case CLK_ATI18818_1:
1352 aty_st_8(CLOCK_CNTL, pll->m, info);
1353 break;
1354 case CLK_IBMRGB514:
1355 aty_st_514(0x06, 0x02, info); /* DAC Operation */
1356 aty_st_514(0x10, 0x01, info); /* PLL Control 1 */
1357 aty_st_514(0x70, 0x01, info); /* Misc Control 1 */
1358 aty_st_514(0x8f, 0x1f, info); /* PLL Ref. Divider Input */
1359 aty_st_514(0x03, 0x00, info); /* Sync Control */
1360 aty_st_514(0x05, 0x00, info); /* Power Management */
1361 aty_st_514(0x20, pll->m, info); /* F0 / M0 */
1362 aty_st_514(0x21, pll->n, info); /* F1 / N0 */
1363 break;
1364 }
1365 }
1366
1367 static int aty_var_to_pll_18818(u32 vclk_per, struct pll_gx *pll)
1368 {
1369 /*
1370 * FIXME: use real calculations instead of using fixed values from the old
1371 * driver
1372 */
1373 static struct {
1374 u32 ps_lim; /* pixclock period rounding limit (arbitrary) */
1375 u8 mode; /* (prescsaler << 4) | Select */
1376 u8 prog; /* ref_div_count */
1377 } ATI18818_clocks[] = {
1378 { 7500, 0x0B, 1 }, /* 7407.4 ps = 135.00 MHz */
1379 { 9000, 0x0A, 1 }, /* 7936.5 ps = 126.00 MHz */
1380 { 11000, 0x09, 1 }, /* 10000.0 ps = 100.00 MHz */
1381 { 12800, 0x0D, 1 }, /* 12500.0 ps = 80.00 MHz */
1382 { 13500, 0x0E, 1 }, /* 13333.3 ps = 75.00 MHz */
1383 /* { 14000, 0x03, 2 },*/ /* 13888.8 ps = 72.00 MHz */
1384 { 15000, 0x1B, 1 }, /* 14814.8 ps = 67.50 MHz */
1385 { 15500, 0x0F, 1 }, /* 15384.6 ps = 65.00 MHz */
1386 { 16000, 0x1A, 1 }, /* 15873.0 ps = 63.00 MHz */
1387 /* { 16000, 0x02, 2 },*/ /* 15873.0 ps = 63.00 MHz */
1388 /* { 18000, 0x01, 2 },*/ /* 17655.4 ps = 56.64 MHz */
1389 /* { 19900, 0x00, 2 },*/ /* 19860.9 ps = 50.35 MHz */
1390 { 20000, 0x07, 1 }, /* 20000.0 ps = 50.00 MHz */
1391 { 20300, 0x06, 1 }, /* 20202.0 ps = 49.50 MHz */
1392 { 22500, 0x05, 1 }, /* 22271.2 ps = 44.90 MHz */
1393 { 25000, 0x04, 1 }, /* 25000.0 ps = 40.00 MHz */
1394 /* { 28000, 0x03, 1 },*/ /* 27777.8 ps = 36.00 MHz */
1395 { 30000, 0x2B, 1 }, /* 29629,6 ps = 33.75 MHz */
1396 { 31000, 0x1F, 1 }, /* 30769.2 ps = 32.50 MHz */
1397 { 32000, 0x2A, 1 }, /* 31746.0 ps = 31.50 MHz */
1398 /* { 32000, 0x02, 1 },*/ /* 31746.0 ps = 31.50 MHz */
1399 /* { 36000, 0x01, 1 },*/ /* 35310.7 ps = 28.32 MHz */
1400 /* { 39900, 0x00, 1 },*/ /* 39714.1 ps = 25.18 MHz */
1401 { 40000, 0x17, 1 }, /* 40000.0 ps = 25.00 MHz */
1402 { 40600, 0x16, 1 }, /* 40404.0 ps = 24.75 MHz */
1403 { 45000, 0x15, 1 }, /* 44543.4 ps = 22.45 MHz */
1404 { 50000, 0x14, 1 }, /* 50000.0 ps = 20.00 MHz */
1405 /* { 56000, 0x13, 1 },*/ /* 55555.5 ps = 18.00 MHz */
1406 { 62000, 0x2F, 1 }, /* 61538.8 ps = 16.25 MHz */
1407 /* { 64000, 0x12, 1 },*/ /* 63492.0 ps = 15.75 MHz */
1408 };
1409 int set;
1410
1411 for (set = 0; set < sizeof(ATI18818_clocks)/sizeof(*ATI18818_clocks);
1412 set++)
1413 if (vclk_per <= ATI18818_clocks[set].ps_lim) {
1414 pll->m = ATI18818_clocks[set].mode;
1415 pll->n = ATI18818_clocks[set].prog;
1416 return 0;
1417 }
1418 return -EINVAL;
1419 }
1420
1421 static int aty_var_to_pll_514(u32 vclk_per, struct pll_gx *pll)
1422 {
1423 /*
1424 * FIXME: use real calculations instead of using fixed values from the old
1425 * driver
1426 */
1427 static struct {
1428 u32 limit; /* pixlock rounding limit (arbitrary) */
1429 u8 m; /* (df<<6) | vco_div_count */
1430 u8 n; /* ref_div_count */
1431 } RGB514_clocks[7] = {
1432 { 8000, (3<<6) | 20, 9 }, /* 7395 ps / 135.2273 MHz */
1433 { 10000, (1<<6) | 19, 3 }, /* 9977 ps / 100.2273 MHz */
1434 { 13000, (1<<6) | 2, 3 }, /* 12509 ps / 79.9432 MHz */
1435 { 14000, (2<<6) | 8, 7 }, /* 13394 ps / 74.6591 MHz */
1436 { 16000, (1<<6) | 44, 6 }, /* 15378 ps / 65.0284 MHz */
1437 { 25000, (1<<6) | 15, 5 }, /* 17460 ps / 57.2727 MHz */
1438 { 50000, (0<<6) | 53, 7 }, /* 33145 ps / 30.1705 MHz */
1439 };
1440 int i;
1441
1442 for (i = 0; i < sizeof(RGB514_clocks)/sizeof(*RGB514_clocks); i++)
1443 if (vclk_per <= RGB514_clocks[i].limit) {
1444 pll->m = RGB514_clocks[i].m;
1445 pll->n = RGB514_clocks[i].n;
1446 return 0;
1447 }
1448 return -EINVAL;
1449 }
1450
1451 /* FIXME: ATI18818?? */
1452
1453 static int aty_pll_gx_to_var(const struct pll_gx *pll, u32 *vclk_per)
1454 {
1455 u8 df, vco_div_count, ref_div_count;
1456
1457 df = pll->m >> 6;
1458 vco_div_count = pll->m & 0x3f;
1459 ref_div_count = pll->n;
1460
1461 *vclk_per = ((ref_clk_per*ref_div_count)<<(3-df))/(vco_div_count+65);
1462
1463 return 0;
1464 }
1465
1466
1467 /*
1468 * PLL programming (Mach64 CT family)
1469 */
1470
1471 static void aty_set_pll_ct(const struct fb_info_aty *info,
1472 const struct pll_ct *pll)
1473 {
1474 aty_st_pll(PLL_REF_DIV, pll->pll_ref_div, info);
1475 aty_st_pll(PLL_GEN_CNTL, pll->pll_gen_cntl, info);
1476 aty_st_pll(MCLK_FB_DIV, pll->mclk_fb_div, info);
1477 aty_st_pll(PLL_VCLK_CNTL, pll->pll_vclk_cntl, info);
1478 aty_st_pll(VCLK_POST_DIV, pll->vclk_post_div, info);
1479 aty_st_pll(VCLK0_FB_DIV, pll->vclk_fb_div, info);
1480 aty_st_pll(PLL_EXT_CNTL, pll->pll_ext_cntl, info);
1481
1482 if (!(Gx == GX_CHIP_ID || Gx == CX_CHIP_ID || Gx == CT_CHIP_ID ||
1483 Gx == ET_CHIP_ID ||
1484 ((Gx == VT_CHIP_ID || Gx == GT_CHIP_ID) && !(Rev & 0x07)))) {
1485 if (info->ram_type >= SDRAM)
1486 aty_st_pll(DLL_CNTL, 0xa6, info);
1487 else
1488 aty_st_pll(DLL_CNTL, 0xa0, info);
1489 aty_st_pll(VFC_CNTL, 0x1b, info);
1490 aty_st_le32(DSP_CONFIG, pll->dsp_config, info);
1491 aty_st_le32(DSP_ON_OFF, pll->dsp_on_off, info);
1492 }
1493 }
1494
1495 static int aty_dsp_gt(const struct fb_info_aty *info, u8 mclk_fb_div,
1496 u8 mclk_post_div, u8 vclk_fb_div, u8 vclk_post_div,
1497 u8 bpp, struct pll_ct *pll)
1498 {
1499 u32 dsp_xclks_per_row, dsp_loop_latency, dsp_precision, dsp_off, dsp_on;
1500 u32 xclks_per_row, fifo_off, fifo_on, y, fifo_size, page_size;
1501
1502 /* xclocks_per_row<<11 */
1503 xclks_per_row = (mclk_fb_div*vclk_post_div*64<<11)/
1504 (vclk_fb_div*mclk_post_div*bpp);
1505 if (xclks_per_row < (1<<11))
1506 FAIL("Dotclock to high");
1507 if (Gx == GT_CHIP_ID || Gx == GU_CHIP_ID || Gx == VT_CHIP_ID ||
1508 Gx == VU_CHIP_ID || Gx == GV_CHIP_ID || Gx == GW_CHIP_ID ||
1509 Gx == GZ_CHIP_ID) {
1510 fifo_size = 24;
1511 dsp_loop_latency = 0;
1512 } else {
1513 fifo_size = 32;
1514 dsp_loop_latency = 2;
1515 }
1516 dsp_precision = 0;
1517 y = (xclks_per_row*fifo_size)>>11;
1518 while (y) {
1519 y >>= 1;
1520 dsp_precision++;
1521 }
1522 dsp_precision -= 5;
1523 /* fifo_off<<6 */
1524 fifo_off = ((xclks_per_row*(fifo_size-1))>>5)+(1<<6);
1525
1526 if (info->total_vram > 1*1024*1024) {
1527 if (info->ram_type >= SDRAM) {
1528 /* >1 MB SDRAM */
1529 dsp_loop_latency += 8;
1530 page_size = 8;
1531 } else {
1532 /* >1 MB DRAM */
1533 dsp_loop_latency += 6;
1534 page_size = 9;
1535 }
1536 } else {
1537 if (info->ram_type >= SDRAM) {
1538 /* <2 MB SDRAM */
1539 dsp_loop_latency += 9;
1540 page_size = 10;
1541 } else {
1542 /* <2 MB DRAM */
1543 dsp_loop_latency += 8;
1544 page_size = 10;
1545 }
1546 }
1547 /* fifo_on<<6 */
1548 if (xclks_per_row >= (page_size<<11))
1549 fifo_on = ((2*page_size+1)<<6)+(xclks_per_row>>5);
1550 else
1551 fifo_on = (3*page_size)<<6;
1552
1553 dsp_xclks_per_row = xclks_per_row>>dsp_precision;
1554 dsp_on = fifo_on>>dsp_precision;
1555 dsp_off = fifo_off>>dsp_precision;
1556
1557 pll->dsp_config = (dsp_xclks_per_row & 0x3fff) |
1558 ((dsp_loop_latency & 0xf)<<16) |
1559 ((dsp_precision & 7)<<20);
1560 pll->dsp_on_off = (dsp_on & 0x7ff) | ((dsp_off & 0x7ff)<<16);
1561 return 0;
1562 }
1563
1564 static int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
1565 u8 bpp, struct pll_ct *pll)
1566 {
1567 u32 q, x; /* x is a workaround for sparc64-linux-gcc */
1568 u8 pll_ref_div, pll_gen_cntl, pll_ext_cntl;
1569 u8 mclk_fb_div, mclk_post_div, mpostdiv = 0;
1570 u8 vclk_fb_div, vclk_post_div, vpostdiv = 0;
1571 int err;
1572
1573 x = x; /* x is a workaround for sparc64-linux-gcc */
1574
1575 pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */
1576
1577 pll_ref_div = info->pll_per*2*255/ref_clk_per;
1578
1579 /* FIXME: use the VTB/GTB /3 post divider if it's better suited */
1580 q = ref_clk_per*pll_ref_div*4/info->mclk_per; /* actually 8*q */
1581 if (q < 16*8 || q > 255*8)
1582 FAIL("mclk out of range");
1583 else if (q < 32*8)
1584 mclk_post_div = 8;
1585 else if (q < 64*8)
1586 mclk_post_div = 4;
1587 else if (q < 128*8)
1588 mclk_post_div = 2;
1589 else
1590 mclk_post_div = 1;
1591 mclk_fb_div = q*mclk_post_div/8;
1592
1593 /* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */
1594 q = ref_clk_per*pll_ref_div*4/vclk_per; /* actually 8*q */
1595 if (q < 16*8 || q > 255*8)
1596 FAIL("vclk out of range");
1597 else if (q < 32*8)
1598 vclk_post_div = 8;
1599 else if (q < 64*8)
1600 vclk_post_div = 4;
1601 else if (q < 128*8)
1602 vclk_post_div = 2;
1603 else
1604 vclk_post_div = 1;
1605 vclk_fb_div = q*vclk_post_div/8;
1606
1607 if ((err = aty_dsp_gt(info, mclk_fb_div, mclk_post_div, vclk_fb_div,
1608 vclk_post_div, bpp, pll)))
1609 return err;
1610
1611 if ((((Gx == GT_CHIP_ID) && (Rev & 0x03)) || (Gx == GU_CHIP_ID) ||
1612 (Gx == GV_CHIP_ID) || (Gx == GW_CHIP_ID) || (Gx == GZ_CHIP_ID) ||
1613 (Gx == LG_CHIP_ID) || (Gx == GB_CHIP_ID) || (Gx == GD_CHIP_ID) ||
1614 (Gx == GI_CHIP_ID) || (Gx == GP_CHIP_ID) || (Gx == GQ_CHIP_ID) ||
1615 (Gx == VU_CHIP_ID)) && (info->ram_type >= SDRAM))
1616 pll_gen_cntl = 0x04;
1617 else
1618 pll_gen_cntl = 0x84;
1619
1620 switch (mclk_post_div) {
1621 case 1:
1622 mpostdiv = 0;
1623 break;
1624 case 2:
1625 mpostdiv = 1;
1626 break;
1627 case 3:
1628 mpostdiv = 4;
1629 break;
1630 case 4:
1631 mpostdiv = 2;
1632 break;
1633 case 8:
1634 mpostdiv = 3;
1635 break;
1636 }
1637 pll_gen_cntl |= mpostdiv<<4; /* mclk */
1638
1639 if (Gx == VT_CHIP_ID && (Rev == 0x40 || Rev == 0x48))
1640 pll_ext_cntl = 0;
1641 else
1642 pll_ext_cntl = mpostdiv; /* xclk == mclk */
1643
1644 switch (vclk_post_div) {
1645 case 1:
1646 vpostdiv = 0;
1647 break;
1648 case 2:
1649 vpostdiv = 1;
1650 break;
1651 case 3:
1652 vpostdiv = 0;
1653 pll_ext_cntl |= 0x10;
1654 break;
1655 case 4:
1656 vpostdiv = 2;
1657 break;
1658 case 6:
1659 vpostdiv = 2;
1660 pll_ext_cntl |= 0x10;
1661 break;
1662 case 8:
1663 vpostdiv = 3;
1664 break;
1665 case 12:
1666 vpostdiv = 3;
1667 pll_ext_cntl |= 0x10;
1668 break;
1669 }
1670 vclk_post_div = vpostdiv;
1671
1672 pll->pll_ref_div = pll_ref_div;
1673 pll->pll_gen_cntl = pll_gen_cntl;
1674 pll->mclk_fb_div = mclk_fb_div;
1675 pll->vclk_post_div = vclk_post_div;
1676 pll->vclk_fb_div = vclk_fb_div;
1677 pll->pll_ext_cntl = pll_ext_cntl;
1678 return 0;
1679 }
1680
1681 static int aty_pll_ct_to_var(const struct pll_ct *pll, u32 *vclk_per)
1682 {
1683 u8 pll_ref_div = pll->pll_ref_div;
1684 u8 vclk_fb_div = pll->vclk_fb_div;
1685 u8 vclk_post_div = pll->vclk_post_div;
1686 u8 pll_ext_cntl = pll->pll_ext_cntl;
1687 static u8 vclk_post_div_tab[] = {
1688 1, 2, 4, 8,
1689 3, 0, 6, 12
1690 };
1691 u8 vpostdiv = vclk_post_div_tab[((pll_ext_cntl & 0x10) >> 1) |
1692 (vclk_post_div & 3)];
1693 if (vpostdiv == 0)
1694 return -EINVAL;
1695 *vclk_per = pll_ref_div*vpostdiv*ref_clk_per/vclk_fb_div/2;
1696 return 0;
1697 }
1698
1699 /* ------------------------------------------------------------------------- */
1700
1701 static void atyfb_set_par(const struct atyfb_par *par,
1702 struct fb_info_aty *info)
1703 {
1704 u32 i;
1705
1706 info->current_par = *par;
1707
1708 if (info->blitter_may_be_busy)
1709 wait_for_idle(info);
1710 aty_set_crtc(info, &par->crtc);
1711 aty_st_8(CLOCK_CNTL, 0, info);
1712 aty_st_8(CLOCK_CNTL, CLOCK_STROBE, info);
1713
1714 if ((Gx == GX_CHIP_ID) || (Gx == CX_CHIP_ID)) {
1715 switch (info->dac_type) {
1716 case DAC_IBMRGB514:
1717 aty_set_dac_514(info, par->crtc.bpp);
1718 break;
1719 case DAC_ATI68860_B:
1720 /* FIXME */
1721 break;
1722 }
1723 aty_set_pll_gx(info, &par->pll.gx);
1724 aty_st_le32(BUS_CNTL, 0x590e10ff, info);
1725 aty_st_le32(DAC_CNTL, 0x47012100, info);
1726
1727 /* Don't forget MEM_CNTL */
1728 i = aty_ld_le32(MEM_CNTL, info) & 0xf0ffffff;
1729 switch (par->crtc.bpp) {
1730 case 8:
1731 i |= 0x02000000;
1732 break;
1733 case 16:
1734 i |= 0x03000000;
1735 break;
1736 case 32:
1737 i |= 0x06000000;
1738 break;
1739 }
1740 aty_st_le32(MEM_CNTL, i, info);
1741
1742 } else {
1743 aty_set_pll_ct(info, &par->pll.ct);
1744 i = aty_ld_le32(MEM_CNTL, info) & 0xf30fffff;
1745 if (!(Gx == VT_CHIP_ID && (Rev == 0x40 || Rev == 0x48)))
1746 i |= info->mem_refresh_rate << 20;
1747 switch (par->crtc.bpp) {
1748 case 8:
1749 case 24:
1750 i |= 0x00000000;
1751 break;
1752 case 16:
1753 i |= 0x04000000;
1754 break;
1755 case 32:
1756 i |= 0x08000000;
1757 break;
1758 }
1759 if ((Gx == CT_CHIP_ID) || (Gx == ET_CHIP_ID)) {
1760 aty_st_le32(DAC_CNTL, 0x87010184, info);
1761 aty_st_le32(BUS_CNTL, 0x680000f9, info);
1762 } else if ((Gx == VT_CHIP_ID) || (Gx == VU_CHIP_ID)) {
1763 aty_st_le32(DAC_CNTL, 0x87010184, info);
1764 aty_st_le32(BUS_CNTL, 0x680000f9, info);
1765 } else {
1766 /* GT */
1767 aty_st_le32(DAC_CNTL, 0x86010102, info);
1768 aty_st_le32(BUS_CNTL, 0x7b23a040, info);
1769 aty_st_le32(EXT_MEM_CNTL,
1770 aty_ld_le32(EXT_MEM_CNTL, info) | 0x5000001, info);
1771 }
1772 aty_st_le32(MEM_CNTL, i, info);
1773 }
1774 aty_st_8(DAC_MASK, 0xff, info);
1775
1776 /* Initialize the graphics engine */
1777 if (par->accel_flags & FB_ACCELF_TEXT)
1778 init_engine(par, info);
1779
1780 #ifdef CONFIG_FB_COMPAT_XPMAC
1781 if (console_fb_info == &info->fb_info) {
1782 struct fb_var_screeninfo var;
1783 int vmode, cmode;
1784 display_info.height = ((par->crtc.v_tot_disp>>16) & 0x7ff)+1;
1785 display_info.width = (((par->crtc.h_tot_disp>>16) & 0xff)+1)*8;
1786 display_info.depth = par->crtc.bpp;
1787 display_info.pitch = par->crtc.vxres*par->crtc.bpp/8;
1788 atyfb_encode_var(&var, par, info);
1789 if (mac_var_to_vmode(&var, &vmode, &cmode))
1790 display_info.mode = 0;
1791 else
1792 display_info.mode = vmode;
1793 strcpy(display_info.name, atyfb_name);
1794 display_info.fb_address = info->frame_buffer_phys;
1795 display_info.cmap_adr_address = info->ati_regbase_phys+0xc0;
1796 display_info.cmap_data_address = info->ati_regbase_phys+0xc1;
1797 display_info.disp_reg_address = info->ati_regbase_phys;
1798 }
1799 #endif /* CONFIG_FB_COMPAT_XPMAC */
1800 }
1801
1802 static int atyfb_decode_var(const struct fb_var_screeninfo *var,
1803 struct atyfb_par *par,
1804 const struct fb_info_aty *info)
1805 {
1806 int err;
1807
1808 if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1809 return err;
1810 if ((Gx == GX_CHIP_ID) || (Gx == CX_CHIP_ID))
1811 switch (info->clk_type) {
1812 case CLK_ATI18818_1:
1813 err = aty_var_to_pll_18818(var->pixclock, &par->pll.gx);
1814 break;
1815 case CLK_IBMRGB514:
1816 err = aty_var_to_pll_514(var->pixclock, &par->pll.gx);
1817 break;
1818 }
1819 else
1820 err = aty_var_to_pll_ct(info, var->pixclock, par->crtc.bpp,
1821 &par->pll.ct);
1822 if (err)
1823 return err;
1824
1825 if (var->accel_flags & FB_ACCELF_TEXT)
1826 par->accel_flags = FB_ACCELF_TEXT;
1827 else
1828 par->accel_flags = 0;
1829
1830 #if 0
1831 if (!fbmon_valid_timings(var->pixclock, htotal, vtotal, info))
1832 return -EINVAL;
1833 #endif
1834
1835 return 0;
1836 }
1837
1838 static int atyfb_encode_var(struct fb_var_screeninfo *var,
1839 const struct atyfb_par *par,
1840 const struct fb_info_aty *info)
1841 {
1842 int err;
1843
1844 memset(var, 0, sizeof(struct fb_var_screeninfo));
1845
1846 if ((err = aty_crtc_to_var(&par->crtc, var)))
1847 return err;
1848 if ((Gx == GX_CHIP_ID) || (Gx == CX_CHIP_ID))
1849 err = aty_pll_gx_to_var(&par->pll.gx, &var->pixclock);
1850 else
1851 err = aty_pll_ct_to_var(&par->pll.ct, &var->pixclock);
1852 if (err)
1853 return err;
1854
1855 var->height = -1;
1856 var->width = -1;
1857 var->accel_flags = par->accel_flags;
1858
1859 return 0;
1860 }
1861
1862
1863
1864 static void set_off_pitch(struct atyfb_par *par,
1865 const struct fb_info_aty *info)
1866 {
1867 u32 xoffset = par->crtc.xoffset;
1868 u32 yoffset = par->crtc.yoffset;
1869 u32 vxres = par->crtc.vxres;
1870 u32 bpp = par->crtc.bpp;
1871
1872 par->crtc.off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
1873 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, info);
1874 }
1875
1876
1877 /*
1878 * Open/Release the frame buffer device
1879 */
1880
1881 static int atyfb_open(struct fb_info *info, int user)
1882
1883 {
1884 #ifdef __sparc__
1885 struct fb_info_aty *fb = (struct fb_info_aty *)info;
1886
1887 if (user) {
1888 if (fb->open)
1889 return -EBUSY;
1890 fb->mmaped = 0;
1891 fb->open = 1;
1892 fb->vtconsole = -1;
1893 } else {
1894 fb->consolecnt++;
1895 }
1896 #endif
1897 MOD_INC_USE_COUNT;
1898 return(0);
1899 }
1900
1901 static int atyfb_release(struct fb_info *info, int user)
1902 {
1903 #ifdef __sparc__
1904 struct fb_info_aty *fb = (struct fb_info_aty *)info;
1905
1906 if (user) {
1907 if (fb->vtconsole != -1)
1908 vt_cons[fb->vtconsole]->vc_mode = KD_TEXT;
1909 fb->open = 0;
1910 fb->mmaped = 0;
1911 fb->vtconsole = -1;
1912 } else {
1913 fb->consolecnt--;
1914 }
1915 #endif
1916 MOD_DEC_USE_COUNT;
1917 return(0);
1918 }
1919
1920
1921 static int encode_fix(struct fb_fix_screeninfo *fix,
1922 const struct atyfb_par *par,
1923 const struct fb_info_aty *info)
1924 {
1925 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1926
1927 strcpy(fix->id, atyfb_name);
1928 fix->smem_start = (char *)info->frame_buffer_phys;
1929 fix->smem_len = (u32)info->total_vram;
1930
1931 #ifdef __LITTLE_ENDIAN
1932 /*
1933 * Last page of 8 MB little-endian aperture is MMIO
1934 * FIXME: we should use the auxiliary aperture instead so we can acces the
1935 * full 8 MB of video RAM on 8 MB boards
1936 */
1937 if (fix->smem_len > 0x800000-GUI_RESERVE)
1938 fix->smem_len = 0x800000-GUI_RESERVE;
1939 #endif
1940 /*
1941 * Reg Block 0 (CT-compatible block) is at ati_regbase_phys
1942 * Reg Block 1 (multimedia extensions) is at ati_regbase_phys-0x400
1943 */
1944 if (Gx == GX_CHIP_ID || Gx == CX_CHIP_ID) {
1945 fix->mmio_start = (char *)info->ati_regbase_phys;
1946 fix->mmio_len = 0x400;
1947 fix->accel = FB_ACCEL_ATI_MACH64GX;
1948 } else if (Gx == CT_CHIP_ID || Gx == ET_CHIP_ID) {
1949 fix->mmio_start = (char *)info->ati_regbase_phys;
1950 fix->mmio_len = 0x400;
1951 fix->accel = FB_ACCEL_ATI_MACH64CT;
1952 } else if (Gx == VT_CHIP_ID || Gx == VU_CHIP_ID || Gx == VV_CHIP_ID) {
1953 fix->mmio_start = (char *)(info->ati_regbase_phys-0x400);
1954 fix->mmio_len = 0x800;
1955 fix->accel = FB_ACCEL_ATI_MACH64VT;
1956 } else {
1957 fix->mmio_start = (char *)(info->ati_regbase_phys-0x400);
1958 fix->mmio_len = 0x800;
1959 fix->accel = FB_ACCEL_ATI_MACH64GT;
1960 }
1961 fix->type = FB_TYPE_PACKED_PIXELS;
1962 fix->type_aux = 0;
1963 fix->line_length = par->crtc.vxres*par->crtc.bpp/8;
1964 fix->visual = par->crtc.bpp <= 8 ? FB_VISUAL_PSEUDOCOLOR
1965 : FB_VISUAL_DIRECTCOLOR;
1966 fix->ywrapstep = 0;
1967 fix->xpanstep = 8;
1968 fix->ypanstep = 1;
1969
1970 return 0;
1971 }
1972
1973
1974 struct fb_var_screeninfo default_var = {
1975 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
1976 640, 480, 640, 480, 0, 0, 8, 0,
1977 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
1978 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
1979 0, FB_VMODE_NONINTERLACED
1980 };
1981
1982
1983 /*
1984 * Get the Fixed Part of the Display
1985 */
1986
1987 static int atyfb_get_fix(struct fb_fix_screeninfo *fix, int con,
1988 struct fb_info *fb)
1989 {
1990 const struct fb_info_aty *info = (struct fb_info_aty *)fb;
1991 struct atyfb_par par;
1992
1993 if (con == -1)
1994 par = info->default_par;
1995 else
1996 atyfb_decode_var(&fb_display[con].var, &par, info);
1997 encode_fix(fix, &par, info);
1998 return 0;
1999 }
2000
2001
2002 /*
2003 * Get the User Defined Part of the Display
2004 */
2005
2006 static int atyfb_get_var(struct fb_var_screeninfo *var, int con,
2007 struct fb_info *fb)
2008 {
2009 const struct fb_info_aty *info = (struct fb_info_aty *)fb;
2010
2011 if (con == -1)
2012 atyfb_encode_var(var, &info->default_par, info);
2013 else
2014 *var = fb_display[con].var;
2015 return 0;
2016 }
2017
2018
2019 static void atyfb_set_disp(struct display *disp, struct fb_info_aty *info,
2020 int bpp, int accel)
2021 {
2022 switch (bpp) {
2023 #ifdef FBCON_HAS_CFB8
2024 case 8:
2025 info->dispsw = accel ? fbcon_aty8 : fbcon_cfb8;
2026 disp->dispsw = &info->dispsw;
2027 break;
2028 #endif
2029 #ifdef FBCON_HAS_CFB16
2030 case 16:
2031 info->dispsw = accel ? fbcon_aty16 : fbcon_cfb16;
2032 disp->dispsw = &info->dispsw;
2033 disp->dispsw_data = info->fbcon_cmap.cfb16;
2034 break;
2035 #endif
2036 #ifdef FBCON_HAS_CFB24
2037 case 24:
2038 info->dispsw = accel ? fbcon_aty24 : fbcon_cfb24;
2039 disp->dispsw = &info->dispsw;
2040 disp->dispsw_data = info->fbcon_cmap.cfb24;
2041 break;
2042 #endif
2043 #ifdef FBCON_HAS_CFB32
2044 case 32:
2045 info->dispsw = accel ? fbcon_aty32 : fbcon_cfb32;
2046 disp->dispsw = &info->dispsw;
2047 disp->dispsw_data = info->fbcon_cmap.cfb32;
2048 break;
2049 #endif
2050 default:
2051 disp->dispsw = &fbcon_dummy;
2052 }
2053 if (info->cursor) {
2054 info->dispsw.cursor = atyfb_cursor;
2055 info->dispsw.set_font = atyfb_set_font;
2056 }
2057 }
2058
2059
2060 /*
2061 * Set the User Defined Part of the Display
2062 */
2063
2064 static int atyfb_set_var(struct fb_var_screeninfo *var, int con,
2065 struct fb_info *fb)
2066 {
2067 struct fb_info_aty *info = (struct fb_info_aty *)fb;
2068 struct atyfb_par par;
2069 struct display *display;
2070 int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel, accel, err;
2071 int activate = var->activate;
2072
2073 if (con >= 0)
2074 display = &fb_display[con];
2075 else
2076 display = fb->disp; /* used during initialization */
2077
2078 if ((err = atyfb_decode_var(var, &par, info)))
2079 return err;
2080
2081 atyfb_encode_var(var, &par, (struct fb_info_aty *)info);
2082
2083 if ((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
2084 oldxres = display->var.xres;
2085 oldyres = display->var.yres;
2086 oldvxres = display->var.xres_virtual;
2087 oldvyres = display->var.yres_virtual;
2088 oldbpp = display->var.bits_per_pixel;
2089 oldaccel = display->var.accel_flags;
2090 display->var = *var;
2091 if (oldxres != var->xres || oldyres != var->yres ||
2092 oldvxres != var->xres_virtual || oldvyres != var->yres_virtual ||
2093 oldbpp != var->bits_per_pixel || oldaccel != var->accel_flags) {
2094 struct fb_fix_screeninfo fix;
2095
2096 encode_fix(&fix, &par, info);
2097 display->screen_base = (char *)info->frame_buffer;
2098 display->visual = fix.visual;
2099 display->type = fix.type;
2100 display->type_aux = fix.type_aux;
2101 display->ypanstep = fix.ypanstep;
2102 display->ywrapstep = fix.ywrapstep;
2103 display->line_length = fix.line_length;
2104 display->can_soft_blank = 1;
2105 display->inverse = 0;
2106 accel = var->accel_flags & FB_ACCELF_TEXT;
2107 atyfb_set_disp(display, info, par.crtc.bpp, accel);
2108 if (accel)
2109 display->scrollmode = (info->bus_type == PCI) ? SCROLL_YNOMOVE : 0;
2110 else
2111 display->scrollmode = SCROLL_YREDRAW;
2112 if (info->fb_info.changevar)
2113 (*info->fb_info.changevar)(con);
2114 }
2115 if (con == currcon)
2116 atyfb_set_par(&par, info);
2117 if (oldbpp != var->bits_per_pixel) {
2118 if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))
2119 return err;
2120 do_install_cmap(con, &info->fb_info);
2121 }
2122 }
2123
2124 return 0;
2125 }
2126
2127
2128 /*
2129 * Pan or Wrap the Display
2130 *
2131 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
2132 */
2133
2134 static int atyfb_pan_display(struct fb_var_screeninfo *var, int con,
2135 struct fb_info *fb)
2136 {
2137 struct fb_info_aty *info = (struct fb_info_aty *)fb;
2138 u32 xres, yres, xoffset, yoffset;
2139 struct atyfb_par *par = &info->current_par;
2140
2141 xres = (((par->crtc.h_tot_disp>>16) & 0xff)+1)*8;
2142 yres = ((par->crtc.v_tot_disp>>16) & 0x7ff)+1;
2143 xoffset = (var->xoffset+7) & ~7;
2144 yoffset = var->yoffset;
2145 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
2146 return -EINVAL;
2147 par->crtc.xoffset = xoffset;
2148 par->crtc.yoffset = yoffset;
2149 set_off_pitch(par, info);
2150 return 0;
2151 }
2152
2153 /*
2154 * Get the Colormap
2155 */
2156
2157 static int atyfb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
2158 struct fb_info *info)
2159 {
2160 if (con == currcon) /* current console? */
2161 return fb_get_cmap(cmap, kspc, atyfb_getcolreg, info);
2162 else if (fb_display[con].cmap.len) /* non default colormap? */
2163 fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2);
2164 else {
2165 int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256;
2166 fb_copy_cmap(fb_default_cmap(size), cmap, kspc ? 0 : 2);
2167 }
2168 return 0;
2169 }
2170
2171 /*
2172 * Set the Colormap
2173 */
2174
2175 static int atyfb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
2176 struct fb_info *info)
2177 {
2178 int err;
2179
2180 if (!fb_display[con].cmap.len) { /* no colormap allocated? */
2181 int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256;
2182 if ((err = fb_alloc_cmap(&fb_display[con].cmap, size, 0)))
2183 return err;
2184 }
2185 if (con == currcon) /* current console? */
2186 return fb_set_cmap(cmap, kspc, atyfb_setcolreg, info);
2187 else
2188 fb_copy_cmap(cmap, &fb_display[con].cmap, kspc ? 0 : 1);
2189 return 0;
2190 }
2191
2192
2193 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
2194 u_long arg, int con, struct fb_info *info)
2195 {
2196 #ifdef __sparc__
2197 struct fb_info_aty *fb = (struct fb_info_aty *)info;
2198 struct fbtype fbtyp;
2199
2200 switch (cmd) {
2201 case FBIOGTYPE:
2202 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
2203 fbtyp.fb_width = fb->current_par.crtc.vxres;
2204 fbtyp.fb_height = fb->current_par.crtc.vyres;
2205 fbtyp.fb_depth = fb->current_par.crtc.bpp;
2206 fbtyp.fb_cmsize = fb_display[con].cmap.len;
2207 fbtyp.fb_size = fb->total_vram;
2208 copy_to_user_ret((struct fbtype *)arg, &fbtyp, sizeof(fbtyp), -EFAULT);
2209 break;
2210 default:
2211 return -EINVAL;
2212 }
2213 return 0;
2214 #else
2215 return -EINVAL;
2216 #endif
2217 }
2218
2219 #ifdef __sparc__
2220 static int atyfb_mmap(struct fb_info *info, struct file *file,
2221 struct vm_area_struct *vma)
2222 {
2223 struct fb_info_aty *fb = (struct fb_info_aty *)info;
2224 unsigned int size, page, map_size = 0;
2225 unsigned long map_offset = 0;
2226 int i;
2227
2228 if (!fb->mmap_map)
2229 return -ENXIO;
2230
2231 size = vma->vm_end - vma->vm_start;
2232 if (vma->vm_offset & ~PAGE_MASK)
2233 return -ENXIO;
2234
2235 /* To stop the swapper from even considering these pages. */
2236 vma->vm_flags |= (VM_SHM | VM_LOCKED);
2237
2238 if (((vma->vm_offset == 0) && (size == fb->total_vram)) ||
2239 ((vma->vm_offset == fb->total_vram) && (size == PAGE_SIZE)))
2240 vma->vm_offset += 0x8000000000000000UL;
2241
2242 #ifdef __sparc_v9__
2243 /* Align it as much as desirable */
2244 {
2245 unsigned long j, align;
2246 int max = -1;
2247
2248 map_offset = vma->vm_offset+size;
2249 for (i = 0; fb->mmap_map[i].size; i++) {
2250 if (fb->mmap_map[i].voff < vma->vm_offset)
2251 continue;
2252 if (fb->mmap_map[i].voff >= map_offset)
2253 break;
2254 if (max < 0 ||
2255 fb->mmap_map[i].size > fb->mmap_map[max].size)
2256 max = i;
2257 }
2258 if (max >= 0) {
2259 j = fb->mmap_map[max].size;
2260 if (fb->mmap_map[max].voff + j > map_offset)
2261 j = map_offset - fb->mmap_map[max].voff;
2262 for (align = 0x400000; align > PAGE_SIZE; align >>= 3)
2263 if (j >= align &&
2264 !(fb->mmap_map[max].poff & (align - 1)))
2265 break;
2266 if (align > PAGE_SIZE) {
2267 j = align;
2268 align = j - ((vma->vm_start
2269 + fb->mmap_map[max].voff
2270 - vma->vm_offset) & (j - 1));
2271 if (align != j) {
2272 struct vm_area_struct *vmm;
2273
2274 vmm = find_vma(current->mm,
2275 vma->vm_start);
2276 if (!vmm || vmm->vm_start
2277 >= vma->vm_end + align) {
2278 vma->vm_start += align;
2279 vma->vm_end += align;
2280 }
2281 }
2282 }
2283 }
2284 }
2285 #endif
2286
2287 /* Each page, see which map applies */
2288 for (page = 0; page < size; ) {
2289 map_size = 0;
2290 for (i = 0; fb->mmap_map[i].size; i++) {
2291 unsigned long start = fb->mmap_map[i].voff;
2292 unsigned long end = start + fb->mmap_map[i].size;
2293 unsigned long offset = vma->vm_offset + page;
2294
2295 if (start > offset)
2296 continue;
2297 if (offset >= end)
2298 continue;
2299
2300 map_size = fb->mmap_map[i].size - (offset - start);
2301 map_offset = fb->mmap_map[i].poff + (offset - start);
2302 break;
2303 }
2304 if (!map_size) {
2305 page += PAGE_SIZE;
2306 continue;
2307 }
2308 if (page + map_size > size)
2309 map_size = size - page;
2310
2311 pgprot_val(vma->vm_page_prot) &= ~(fb->mmap_map[i].prot_mask);
2312 pgprot_val(vma->vm_page_prot) |= fb->mmap_map[i].prot_flag;
2313
2314 if (remap_page_range(vma->vm_start + page, map_offset,
2315 map_size, vma->vm_page_prot))
2316 return -EAGAIN;
2317
2318 page += map_size;
2319 }
2320
2321 if (!map_size)
2322 return -EINVAL;
2323
2324 vma->vm_file = file;
2325 file->f_count++;
2326 vma->vm_flags |= VM_IO;
2327
2328 if (!fb->mmaped) {
2329 int lastconsole = 0;
2330
2331 if (info->display_fg)
2332 lastconsole = info->display_fg->vc_num;
2333 fb->mmaped = 1;
2334 if (fb->consolecnt && fb_display[lastconsole].fb_info == info) {
2335 fb->vtconsole = lastconsole;
2336 vt_cons[lastconsole]->vc_mode = KD_GRAPHICS;
2337 }
2338 }
2339 return 0;
2340 }
2341
2342 static struct {
2343 u32 yoffset;
2344 u8 r[2][256];
2345 u8 g[2][256];
2346 u8 b[2][256];
2347 } atyfb_save;
2348
2349 static void atyfb_save_palette(struct fb_info *fb, int enter)
2350 {
2351 struct fb_info_aty *info = (struct fb_info_aty *)fb;
2352 int i, tmp, scale;
2353
2354 for (i = 0; i < 256; i++) {
2355 tmp = aty_ld_8(DAC_CNTL, info) & 0xfc;
2356 if ((Gx == GT_CHIP_ID) || (Gx == GU_CHIP_ID) ||
2357 (Gx == LG_CHIP_ID) || (Gx == GB_CHIP_ID) ||
2358 (Gx == GD_CHIP_ID) || (Gx == GI_CHIP_ID) ||
2359 (Gx == GP_CHIP_ID) || (Gx == GQ_CHIP_ID))
2360 tmp |= 0x2;
2361 aty_st_8(DAC_CNTL, tmp, info);
2362 aty_st_8(DAC_MASK, 0xff, info);
2363 eieio();
2364 scale = ((Gx != GX_CHIP_ID) && (Gx != CX_CHIP_ID) &&
2365 (info->current_par.crtc.bpp == 16)) ? 3 : 0;
2366 info->aty_cmap_regs->rindex = i << scale;
2367 eieio();
2368 atyfb_save.r[enter][i] = info->aty_cmap_regs->lut;
2369 eieio();
2370 atyfb_save.g[enter][i] = info->aty_cmap_regs->lut;
2371 eieio();
2372 atyfb_save.b[enter][i] = info->aty_cmap_regs->lut;
2373 eieio();
2374 info->aty_cmap_regs->windex = i << scale;
2375 eieio();
2376 info->aty_cmap_regs->lut = atyfb_save.r[1-enter][i];
2377 eieio();
2378 info->aty_cmap_regs->lut = atyfb_save.g[1-enter][i];
2379 eieio();
2380 info->aty_cmap_regs->lut = atyfb_save.b[1-enter][i];
2381 eieio();
2382 }
2383 }
2384
2385 static void atyfb_palette(int enter)
2386 {
2387 struct fb_info_aty *info;
2388 struct atyfb_par *par;
2389 struct display *d;
2390 int i;
2391
2392 for (i = 0; i < MAX_NR_CONSOLES; i++) {
2393 d = &fb_display[i];
2394 if (d->fb_info &&
2395 d->fb_info->fbops == &atyfb_ops &&
2396 d->fb_info->display_fg &&
2397 d->fb_info->display_fg->vc_num == i) {
2398 atyfb_save_palette(d->fb_info, enter);
2399 info = (struct fb_info_aty *)d->fb_info;
2400 par = &info->current_par;
2401 if (enter) {
2402 atyfb_save.yoffset = par->crtc.yoffset;
2403 par->crtc.yoffset = 0;
2404 set_off_pitch(par, info);
2405 } else {
2406 par->crtc.yoffset = atyfb_save.yoffset;
2407 set_off_pitch(par, info);
2408 }
2409 break;
2410 }
2411 }
2412 }
2413 #endif /* __sparc__ */
2414
2415 /*
2416 * Initialisation
2417 */
2418
2419 __initfunc(static int aty_init(struct fb_info_aty *info, const char *name))
2420 {
2421 u32 chip_id;
2422 u32 i;
2423 int j, k;
2424 struct fb_var_screeninfo var;
2425 struct display *disp;
2426 const char *chipname = NULL, *ramname = NULL;
2427 int pll, mclk, gtb_memsize;
2428 #if defined(CONFIG_PPC)
2429 int sense;
2430 #endif
2431
2432 info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0);
2433 chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
2434 Gx = chip_id & CFG_CHIP_TYPE;
2435 Rev = (chip_id & CFG_CHIP_REV)>>24;
2436 for (j = 0; j < (sizeof(aty_features)/sizeof(*aty_features)); j++)
2437 if (aty_features[j].chip_type == Gx) {
2438 chipname = aty_features[j].name;
2439 break;
2440 }
2441 if (!chipname) {
2442 printk("atyfb: Unknown mach64 0x%04x\n", Gx);
2443 return 0;
2444 } else
2445 printk("atyfb: %s [0x%04x rev 0x%02x] ", chipname, Gx, Rev);
2446 if ((Gx == GX_CHIP_ID) || (Gx == CX_CHIP_ID)) {
2447 info->bus_type = (aty_ld_le32(CONFIG_STAT0, info) >> 0) & 0x07;
2448 info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) >> 3) & 0x07;
2449 ramname = aty_gx_ram[info->ram_type];
2450 /* FIXME: clockchip/RAMDAC probing? */
2451 #ifdef CONFIG_ATARI
2452 info->dac_type = DAC_ATI68860_B;
2453 info->clk_type = CLK_ATI18818_1;
2454 #else
2455 info->dac_type = DAC_IBMRGB514;
2456 info->clk_type = CLK_IBMRGB514;
2457 #endif
2458 /* FIXME */
2459 pll = 135;
2460 mclk = 50;
2461 } else {
2462 info->bus_type = PCI;
2463 info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07);
2464 ramname = aty_ct_ram[info->ram_type];
2465 info->dac_type = DAC_INTERNAL;
2466 info->clk_type = CLK_INTERNAL;
2467 if ((Gx == CT_CHIP_ID) || (Gx == ET_CHIP_ID)) {
2468 pll = 135;
2469 mclk = 60;
2470 } else {
2471 mclk = info->ram_type >= SDRAM ? 67 : 63;
2472 if ((Gx == VT_CHIP_ID) && (Rev == 0x08)) {
2473 /* VTA3 */
2474 pll = 170;
2475 } else if (((Gx == VT_CHIP_ID) && ((Rev == 0x40) ||
2476 (Rev == 0x48))) ||
2477 ((Gx == VT_CHIP_ID) && ((Rev == 0x01) ||
2478 (Rev == 0x9a))) ||
2479 Gx == VU_CHIP_ID) {
2480 /* VTA4 or VTB */
2481 pll = 200;
2482 } else if (Gx == VV_CHIP_ID) {
2483 /* VT4 */
2484 pll = 230;
2485 mclk = 83;
2486 } else if (Gx == VT_CHIP_ID) {
2487 /* other VT */
2488 pll = 135;
2489 mclk = 63;
2490 } else if ((Gx == GT_CHIP_ID) && (Rev & 0x01)) {
2491 /* RAGE II */
2492 pll = 170;
2493 } else if (((Gx == GT_CHIP_ID) && (Rev & 0x02)) ||
2494 (Gx == GU_CHIP_ID)) {
2495 /* RAGE II+ */
2496 pll = 200;
2497 } else if (Gx == GV_CHIP_ID || Gx == GW_CHIP_ID ||
2498 Gx == GZ_CHIP_ID) {
2499 /* RAGE IIC */
2500 pll = 230;
2501 mclk = 83;
2502 } else if (Gx == GB_CHIP_ID || Gx == GD_CHIP_ID ||
2503 Gx == GI_CHIP_ID || Gx == GP_CHIP_ID ||
2504 Gx == GQ_CHIP_ID || Gx == LB_CHIP_ID ||
2505 Gx == LD_CHIP_ID || Gx == LG_CHIP_ID ||
2506 Gx == LI_CHIP_ID || Gx == LP_CHIP_ID) {
2507 /* RAGE PRO or LT PRO */
2508 pll = 230;
2509 mclk = 100;
2510 } else {
2511 /* other RAGE */
2512 pll = 135;
2513 mclk = 63;
2514 }
2515 }
2516 }
2517
2518 i = aty_ld_le32(MEM_CNTL, info);
2519 gtb_memsize = !(Gx == GX_CHIP_ID || Gx == CX_CHIP_ID || Gx == CT_CHIP_ID ||
2520 Gx == ET_CHIP_ID ||
2521 ((Gx == VT_CHIP_ID || Gx == GT_CHIP_ID) && !(Rev & 0x07)));
2522 if (gtb_memsize)
2523 switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
2524 case MEM_SIZE_512K:
2525 info->total_vram = 0x80000;
2526 break;
2527 case MEM_SIZE_1M:
2528 info->total_vram = 0x100000;
2529 break;
2530 case MEM_SIZE_2M_GTB:
2531 info->total_vram = 0x200000;
2532 break;
2533 case MEM_SIZE_4M_GTB:
2534 info->total_vram = 0x400000;
2535 break;
2536 case MEM_SIZE_6M_GTB:
2537 info->total_vram = 0x600000;
2538 break;
2539 case MEM_SIZE_8M_GTB:
2540 info->total_vram = 0x800000;
2541 break;
2542 default:
2543 info->total_vram = 0x80000;
2544 }
2545 else
2546 switch (i & MEM_SIZE_ALIAS) {
2547 case MEM_SIZE_512K:
2548 info->total_vram = 0x80000;
2549 break;
2550 case MEM_SIZE_1M:
2551 info->total_vram = 0x100000;
2552 break;
2553 case MEM_SIZE_2M:
2554 info->total_vram = 0x200000;
2555 break;
2556 case MEM_SIZE_4M:
2557 info->total_vram = 0x400000;
2558 break;
2559 case MEM_SIZE_6M:
2560 info->total_vram = 0x600000;
2561 break;
2562 case MEM_SIZE_8M:
2563 info->total_vram = 0x800000;
2564 break;
2565 default:
2566 info->total_vram = 0x80000;
2567 }
2568
2569 if (Gx == GI_CHIP_ID) {
2570 if (aty_ld_le32(CONFIG_STAT1, info) & 0x40000000)
2571 info->total_vram += 0x400000;
2572 }
2573
2574 if (default_vram) {
2575 info->total_vram = default_vram*1024;
2576 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2577 if (info->total_vram <= 0x80000)
2578 i |= MEM_SIZE_512K;
2579 else if (info->total_vram <= 0x100000)
2580 i |= MEM_SIZE_1M;
2581 else if (info->total_vram <= 0x200000)
2582 i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2583 else if (info->total_vram <= 0x400000)
2584 i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2585 else if (info->total_vram <= 0x600000)
2586 i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2587 else
2588 i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2589 aty_st_le32(MEM_CNTL, i, info);
2590 }
2591 if (default_pll)
2592 pll = default_pll;
2593 if (default_mclk)
2594 mclk = default_mclk;
2595
2596 printk("%d%c %s, %d MHz PLL, %d Mhz MCLK\n",
2597 info->total_vram == 0x80000 ? 512 : (info->total_vram >> 20),
2598 info->total_vram == 0x80000 ? 'K' : 'M', ramname, pll, mclk);
2599
2600 if (mclk < 44)
2601 info->mem_refresh_rate = 0; /* 000 = 10 Mhz - 43 Mhz */
2602 else if (mclk < 50)
2603 info->mem_refresh_rate = 1; /* 001 = 44 Mhz - 49 Mhz */
2604 else if (mclk < 55)
2605 info->mem_refresh_rate = 2; /* 010 = 50 Mhz - 54 Mhz */
2606 else if (mclk < 66)
2607 info->mem_refresh_rate = 3; /* 011 = 55 Mhz - 65 Mhz */
2608 else if (mclk < 75)
2609 info->mem_refresh_rate = 4; /* 100 = 66 Mhz - 74 Mhz */
2610 else if (mclk < 80)
2611 info->mem_refresh_rate = 5; /* 101 = 75 Mhz - 79 Mhz */
2612 else if (mclk < 100)
2613 info->mem_refresh_rate = 6; /* 110 = 80 Mhz - 100 Mhz */
2614 else
2615 info->mem_refresh_rate = 7; /* 111 = 100 Mhz and above */
2616 info->pll_per = 1000000/pll;
2617 info->mclk_per = 1000000/mclk;
2618
2619 #ifdef DEBUG
2620 if ((Gx != GX_CHIP_ID) && (Gx != CX_CHIP_ID)) {
2621 int i;
2622 printk("BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2623 "DSP_CONFIG DSP_ON_OFF\n"
2624 "%08x %08x %08x %08x %08x %08x %08x\n"
2625 "PLL",
2626 aty_ld_le32(BUS_CNTL, info), aty_ld_le32(DAC_CNTL, info),
2627 aty_ld_le32(MEM_CNTL, info), aty_ld_le32(EXT_MEM_CNTL, info),
2628 aty_ld_le32(CRTC_GEN_CNTL, info), aty_ld_le32(DSP_CONFIG, info),
2629 aty_ld_le32(DSP_ON_OFF, info));
2630 for (i = 0; i < 16; i++)
2631 printk(" %02x", aty_ld_pll(i, info));
2632 printk("\n");
2633 }
2634 #endif
2635
2636 if (info->bus_type == ISA)
2637 if ((info->total_vram == 0x400000) || (info->total_vram == 0x800000)) {
2638 /* protect GUI-regs if complete Aperture is VRAM */
2639 info->total_vram -= GUI_RESERVE;
2640 }
2641
2642 #if defined(CONFIG_PPC)
2643 if (default_vmode == VMODE_NVRAM) {
2644 default_vmode = nvram_read_byte(NV_VMODE);
2645 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2646 default_vmode = VMODE_CHOOSE;
2647 }
2648 if (default_vmode == VMODE_CHOOSE) {
2649 if (Gx == LG_CHIP_ID)
2650 /* G3 PowerBook with 1024x768 LCD */
2651 default_vmode = VMODE_1024_768_60;
2652 else {
2653 sense = read_aty_sense(info);
2654 default_vmode = mac_map_monitor_sense(sense);
2655 }
2656 }
2657 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2658 default_vmode = VMODE_640_480_60;
2659 if (default_cmode == CMODE_NVRAM)
2660 default_cmode = nvram_read_byte(NV_CMODE);
2661 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2662 default_cmode = CMODE_8;
2663 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
2664 var = default_var;
2665 #else /* !CONFIG_PPC */
2666 var = default_var;
2667 #endif /* !CONFIG_PPC */
2668 if (noaccel)
2669 var.accel_flags &= ~FB_ACCELF_TEXT;
2670 else
2671 var.accel_flags |= FB_ACCELF_TEXT;
2672
2673 if (var.yres == var.yres_virtual) {
2674 u32 vram = (info->total_vram - (PAGE_SIZE << 2));
2675 var.yres_virtual = ((vram * 8) / var.bits_per_pixel) / var.xres_virtual;
2676 if (var.yres_virtual < var.yres)
2677 var.yres_virtual = var.yres;
2678 }
2679
2680 if (atyfb_decode_var(&var, &info->default_par, info)) {
2681 printk("atyfb: can't set default video mode\n");
2682 return 0;
2683 }
2684
2685 disp = &info->disp;
2686
2687 strcpy(info->fb_info.modename, atyfb_name);
2688 info->fb_info.node = -1;
2689 info->fb_info.fbops = &atyfb_ops;
2690 info->fb_info.disp = disp;
2691 strcpy(info->fb_info.fontname, fontname);
2692 info->fb_info.changevar = NULL;
2693 info->fb_info.switch_con = &atyfbcon_switch;
2694 info->fb_info.updatevar = &atyfbcon_updatevar;
2695 info->fb_info.blank = &atyfbcon_blank;
2696 info->fb_info.flags = FBINFO_FLAG_DEFAULT;
2697
2698 #ifdef __sparc__
2699 atyfb_save_palette(&info->fb_info, 0);
2700 #endif
2701 for (j = 0; j < 16; j++) {
2702 k = color_table[j];
2703 info->palette[j].red = default_red[k];
2704 info->palette[j].green = default_grn[k];
2705 info->palette[j].blue = default_blu[k];
2706 }
2707
2708 if (Gx != GX_CHIP_ID && Gx != CX_CHIP_ID) {
2709 info->cursor = aty_init_cursor(info);
2710 if (info->cursor) {
2711 info->dispsw.cursor = atyfb_cursor;
2712 info->dispsw.set_font = atyfb_set_font;
2713 }
2714 }
2715
2716 atyfb_set_var(&var, -1, &info->fb_info);
2717
2718 if (register_framebuffer(&info->fb_info) < 0)
2719 return 0;
2720
2721 printk("fb%d: %s frame buffer device on %s\n",
2722 GET_FB_IDX(info->fb_info.node), atyfb_name, name);
2723 return 1;
2724 }
2725
2726 __initfunc(void atyfb_init(void))
2727 {
2728 #if defined(CONFIG_FB_OF)
2729 /* We don't want to be called like this. */
2730 /* We rely on Open Firmware (offb) instead. */
2731 #elif defined(CONFIG_PCI)
2732 struct pci_dev *pdev;
2733 struct fb_info_aty *info;
2734 unsigned long addr;
2735 #ifdef __sparc__
2736 extern void (*prom_palette) (int);
2737 extern int con_is_present(void);
2738 struct pcidev_cookie *pcp;
2739 char prop[128];
2740 int node, len;
2741 u32 mem, chip_id;
2742 int i, j;
2743
2744 /* Do not attach when we have a serial console. */
2745 if (!con_is_present())
2746 return;
2747 #else
2748 u16 tmp;
2749 #endif
2750
2751 for (pdev = pci_devices; pdev; pdev = pdev->next) {
2752 if (((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
2753 (pdev->vendor == PCI_VENDOR_ID_ATI)) {
2754
2755 info = kmalloc(sizeof(struct fb_info_aty), GFP_ATOMIC);
2756 if (!info) {
2757 printk("atyfb_init: can't alloc fb_info_aty\n");
2758 return;
2759 }
2760 memset(info, 0, sizeof(struct fb_info_aty));
2761
2762 addr = pdev->base_address[0];
2763 if ((addr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
2764 addr = pdev->base_address[1];
2765 if (!addr)
2766 continue;
2767 addr &= PCI_BASE_ADDRESS_MEM_MASK;
2768
2769 #ifdef __sparc__
2770 /*
2771 * Map memory-mapped registers.
2772 */
2773 info->ati_regbase = addr + 0x7ffc00;
2774 info->ati_regbase_phys = __pa(addr + 0x7ffc00);
2775
2776 /*
2777 * Map in big-endian aperture.
2778 */
2779 info->frame_buffer = (unsigned long)(addr + 0x800000);
2780 info->frame_buffer_phys = __pa(addr + 0x800000);
2781
2782 /*
2783 * Figure mmap addresses from PCI config space.
2784 * Split Framebuffer in big- and little-endian halfs.
2785 */
2786 for (i = 0; i < 6 && pdev->base_address[i]; i++)
2787 /* nothing */;
2788 j = i + 3;
2789
2790 info->mmap_map = kmalloc(j * sizeof(*info->mmap_map), GFP_ATOMIC);
2791 if (!info->mmap_map) {
2792 printk("atyfb_init: can't alloc mmap_map\n");
2793 kfree(info);
2794 return;
2795 }
2796 memset(info->mmap_map, 0, j * sizeof(*info->mmap_map));
2797
2798 for (i = 0, j = 2; i < 6 && pdev->base_address[i]; i++) {
2799 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2800 unsigned long base;
2801 u32 size, pbase;
2802
2803 base = pdev->base_address[i];
2804
2805 io = (base & PCI_BASE_ADDRESS_SPACE)==PCI_BASE_ADDRESS_SPACE_IO;
2806
2807 pci_read_config_dword(pdev, breg, &pbase);
2808 pci_write_config_dword(pdev, breg, 0xffffffff);
2809 pci_read_config_dword(pdev, breg, &size);
2810 pci_write_config_dword(pdev, breg, pbase);
2811
2812 if (io)
2813 size &= ~1;
2814 size = ~(size) + 1;
2815
2816 if (base == addr) {
2817 info->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2818 info->mmap_map[j].poff = __pa((base + 0x800000)
2819 & PAGE_MASK);
2820 info->mmap_map[j].size = 0x800000;
2821 info->mmap_map[j].prot_mask = _PAGE_CACHE;
2822 info->mmap_map[j].prot_flag = _PAGE_E|_PAGE_IE;
2823 size -= 0x800000;
2824 j++;
2825 }
2826
2827 info->mmap_map[j].voff = pbase & PAGE_MASK;
2828 info->mmap_map[j].poff = __pa(base & PAGE_MASK);
2829 info->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2830 info->mmap_map[j].prot_mask = _PAGE_CACHE;
2831 info->mmap_map[j].prot_flag = _PAGE_E;
2832 j++;
2833 }
2834
2835 /*
2836 * Fix PROMs idea of MEM_CNTL settings...
2837 */
2838 mem = aty_ld_le32(MEM_CNTL, info);
2839 chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
2840 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) &&
2841 !((chip_id >> 24) & 1)) {
2842 switch (mem & 0x0f) {
2843 case 3:
2844 mem = (mem & ~(0x0f)) | 2;
2845 break;
2846 case 7:
2847 mem = (mem & ~(0x0f)) | 3;
2848 break;
2849 case 9:
2850 mem = (mem & ~(0x0f)) | 4;
2851 break;
2852 case 11:
2853 mem = (mem & ~(0x0f)) | 5;
2854 break;
2855 default:
2856 break;
2857 }
2858 if ((aty_ld_le32(CONFIG_STAT0, info) & 7) >= SDRAM)
2859 mem &= ~(0x00700000);
2860 }
2861 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
2862 aty_st_le32(MEM_CNTL, mem, info);
2863
2864 /*
2865 * If this is the console device, we will set default video
2866 * settings to what the PROM left us with.
2867 */
2868 node = prom_getchild(prom_root_node);
2869 node = prom_searchsiblings(node, "aliases");
2870 if (node) {
2871 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2872 if (len > 0) {
2873 prop[len] = '\0';
2874 node = prom_finddevice(prop);
2875 } else {
2876 node = 0;
2877 }
2878 }
2879
2880 pcp = pdev->sysdata;
2881 if (node == pcp->prom_node) {
2882
2883 struct fb_var_screeninfo *var = &default_var;
2884 unsigned int N, P, Q, M, T;
2885 u32 v_total, h_total;
2886 struct crtc crtc;
2887 u8 pll_regs[16];
2888 u8 clock_cntl;
2889
2890 crtc.vxres = prom_getintdefault(node, "width", 1024);
2891 crtc.vyres = prom_getintdefault(node, "height", 768);
2892 crtc.bpp = prom_getintdefault(node, "depth", 8);
2893 crtc.xoffset = crtc.yoffset = 0;
2894 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, info);
2895 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, info);
2896 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, info);
2897 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, info);
2898 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, info);
2899 aty_crtc_to_var(&crtc, var);
2900
2901 h_total = var->xres + var->right_margin +
2902 var->hsync_len + var->left_margin;
2903 v_total = var->yres + var->lower_margin +
2904 var->vsync_len + var->upper_margin;
2905
2906 /*
2907 * Read the PLL to figure actual Refresh Rate.
2908 */
2909 clock_cntl = aty_ld_8(CLOCK_CNTL, info);
2910 /* printk("atyfb: CLOCK_CNTL: %02x\n", clock_cntl); */
2911 for (i = 0; i < 16; i++)
2912 pll_regs[i] = aty_ld_pll(i, info);
2913
2914 /*
2915 * PLL Reference Devider M:
2916 */
2917 M = pll_regs[2];
2918
2919 /*
2920 * PLL Feedback Devider N (Dependant on CLOCK_CNTL):
2921 */
2922 N = pll_regs[7 + (clock_cntl & 3)];
2923
2924 /*
2925 * PLL Post Devider P (Dependant on CLOCK_CNTL):
2926 */
2927 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
2928
2929 /*
2930 * PLL Devider Q:
2931 */
2932 Q = N / P;
2933
2934 /*
2935 * Target Frequency:
2936 *
2937 * T * M
2938 * Q = -------
2939 * 2 * R
2940 *
2941 * where R is XTALIN (= 14318 kHz).
2942 */
2943 T = 2 * Q * 14318 / M;
2944
2945 default_var.pixclock = 1000000000 / T;
2946 }
2947
2948 #else /* __sparc__ */
2949
2950 info->ati_regbase_phys = 0x7ff000 + addr;
2951 info->ati_regbase = (unsigned long)
2952 ioremap(info->ati_regbase_phys, 0x1000);
2953
2954 if(!info->ati_regbase) {
2955 kfree(info);
2956 return;
2957 }
2958
2959 info->ati_regbase_phys += 0xc00;
2960 info->ati_regbase += 0xc00;
2961
2962 /*
2963 * Enable memory-space accesses using config-space
2964 * command register.
2965 */
2966 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
2967 if (!(tmp & PCI_COMMAND_MEMORY)) {
2968 tmp |= PCI_COMMAND_MEMORY;
2969 pci_write_config_word(pdev, PCI_COMMAND, tmp);
2970 }
2971
2972 #ifdef __BIG_ENDIAN
2973 /* Use the big-endian aperture */
2974 addr += 0x800000;
2975 #endif
2976
2977 /* Map in frame buffer */
2978 info->frame_buffer_phys = addr;
2979 info->frame_buffer = (unsigned long)ioremap(addr, 0x800000);
2980
2981 if(!info->frame_buffer) {
2982 kfree(info);
2983 return;
2984 }
2985
2986 #endif /* __sparc__ */
2987
2988 if (!aty_init(info, "PCI")) {
2989 if (info->mmap_map)
2990 kfree(info->mmap_map);
2991 kfree(info);
2992 return;
2993 }
2994
2995 #ifdef __sparc__
2996 if (!prom_palette)
2997 prom_palette = atyfb_palette;
2998
2999 /*
3000 * Add /dev/fb mmap values.
3001 */
3002 info->mmap_map[0].voff = 0x8000000000000000UL;
3003 info->mmap_map[0].poff = __pa(info->frame_buffer & PAGE_MASK);
3004 info->mmap_map[0].size = info->total_vram;
3005 info->mmap_map[0].prot_mask = _PAGE_CACHE;
3006 info->mmap_map[0].prot_flag = _PAGE_E;
3007 info->mmap_map[1].voff = info->mmap_map[0].voff + info->total_vram;
3008 info->mmap_map[1].poff = __pa(info->ati_regbase & PAGE_MASK);
3009 info->mmap_map[1].size = PAGE_SIZE;
3010 info->mmap_map[1].prot_mask = _PAGE_CACHE;
3011 info->mmap_map[1].prot_flag = _PAGE_E;
3012 #endif /* __sparc__ */
3013 }
3014 }
3015 #elif defined(CONFIG_ATARI)
3016 int m64_num;
3017 struct fb_info_aty *info;
3018
3019 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3020 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3021 !phys_guiregbase[m64_num]) {
3022 printk(" phys_*[%d] parameters not set => returning early. \n",
3023 m64_num);
3024 continue;
3025 }
3026
3027 info = kmalloc(sizeof(struct fb_info_aty), GFP_ATOMIC);
3028 if (!info) {
3029 printk("atyfb_init: can't alloc fb_info_aty\n");
3030 return;
3031 }
3032 memset(info, 0, sizeof(struct fb_info_aty));
3033
3034 /*
3035 * Map the video memory (physical address given) to somewhere in the
3036 * kernel address space.
3037 */
3038 info->frame_buffer = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3039 info->frame_buffer_phys = info->frame_buffer;
3040 info->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000)+0xFC00ul;
3041 info->ati_regbase_phys = info->ati_regbase;
3042
3043 if (!aty_init(info, "ISA bus")) {
3044 kfree(info);
3045 /* This is insufficient! kernel_map has added two large chunks!! */
3046 return;
3047 }
3048 }
3049 #endif
3050 }
3051
3052 #ifdef CONFIG_FB_OF
3053 __initfunc(void atyfb_of_init(struct device_node *dp))
3054 {
3055 unsigned long addr;
3056 u8 bus, devfn;
3057 u16 cmd;
3058 struct fb_info_aty *info;
3059 int i;
3060
3061 switch (dp->n_addrs) {
3062 case 1:
3063 case 2:
3064 case 3:
3065 addr = dp->addrs[0].address;
3066 break;
3067 case 4:
3068 addr = dp->addrs[1].address;
3069 break;
3070 default:
3071 printk("Warning: got %d adresses for ATY:\n", dp->n_addrs);
3072 for (i = 0; i < dp->n_addrs; i++)
3073 printk(" %08x-%08x", dp->addrs[i].address,
3074 dp->addrs[i].address+dp->addrs[i].size-1);
3075 if (dp->n_addrs)
3076 printk("\n");
3077 return;
3078 }
3079
3080 info = kmalloc(sizeof(struct fb_info_aty), GFP_ATOMIC);
3081 if (!info) {
3082 printk("atyfb_of_init: can't alloc fb_info_aty\n");
3083 return;
3084 }
3085 memset(info, 0, sizeof(struct fb_info_aty));
3086
3087 info->ati_regbase_phys = 0x7ff000+addr;
3088 info->ati_regbase = (unsigned long)ioremap(info->ati_regbase_phys,
3089 0x1000);
3090
3091 if(! info->ati_regbase) {
3092 printk("atyfb_init: ioremap() returned NULL\n");
3093 kfree(info);
3094 return;
3095 }
3096
3097 info->ati_regbase_phys += 0xc00;
3098 info->ati_regbase += 0xc00;
3099
3100 /* enable memory-space accesses using config-space command register */
3101 if (pci_device_loc(dp, &bus, &devfn) == 0) {
3102 pcibios_read_config_word(bus, devfn, PCI_COMMAND, &cmd);
3103 if (cmd != 0xffff) {
3104 cmd |= PCI_COMMAND_MEMORY;
3105 pcibios_write_config_word(bus, devfn, PCI_COMMAND, cmd);
3106 }
3107 }
3108
3109 #ifdef __BIG_ENDIAN
3110 /* Use the big-endian aperture */
3111 addr += 0x800000;
3112 #endif
3113
3114 /* Map in frame buffer */
3115 info->frame_buffer_phys = addr;
3116 info->frame_buffer = (unsigned long)ioremap(addr, 0x800000);
3117
3118 if(! info->frame_buffer) {
3119 printk("atyfb_init: ioremap() returned NULL\n");
3120 kfree(info);
3121 return;
3122 }
3123
3124 if (!aty_init(info, dp->full_name)) {
3125 kfree(info);
3126 return;
3127 }
3128
3129 #ifdef CONFIG_FB_COMPAT_XPMAC
3130 if (!console_fb_info)
3131 console_fb_info = &info->fb_info;
3132 #endif /* CONFIG_FB_COMPAT_XPMAC */
3133 }
3134 #endif /* CONFIG_FB_OF */
3135
3136
3137 __initfunc(void atyfb_setup(char *options, int *ints))
3138 {
3139 char *this_opt;
3140
3141 if (!options || !*options)
3142 return;
3143
3144 for (this_opt = strtok(options, ","); this_opt;
3145 this_opt = strtok(NULL, ",")) {
3146 if (!strncmp(this_opt, "font:", 5)) {
3147 char *p;
3148 int i;
3149
3150 p = this_opt + 5;
3151 for (i = 0; i < sizeof(fontname) - 1; i++)
3152 if (!*p || *p == ' ' || *p == ',')
3153 break;
3154 memcpy(fontname, this_opt + 5, i);
3155 fontname[i] = 0;
3156 } else if (!strncmp(this_opt, "noblink", 7)) {
3157 curblink = 0;
3158 } else if (!strncmp(this_opt, "noaccel", 7)) {
3159 noaccel = 1;
3160 } else if (!strncmp(this_opt, "vram:", 5))
3161 default_vram = simple_strtoul(this_opt+5, NULL, 0);
3162 else if (!strncmp(this_opt, "pll:", 4))
3163 default_pll = simple_strtoul(this_opt+4, NULL, 0);
3164 else if (!strncmp(this_opt, "mclk:", 5))
3165 default_mclk = simple_strtoul(this_opt+5, NULL, 0);
3166 #if defined(CONFIG_PPC)
3167 else if (!strncmp(this_opt, "vmode:", 6)) {
3168 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
3169 if (vmode > 0 && vmode <= VMODE_MAX)
3170 default_vmode = vmode;
3171 } else if (!strncmp(this_opt, "cmode:", 6)) {
3172 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
3173 switch (cmode) {
3174 case 0:
3175 case 8:
3176 default_cmode = CMODE_8;
3177 break;
3178 case 15:
3179 case 16:
3180 default_cmode = CMODE_16;
3181 break;
3182 case 24:
3183 case 32:
3184 default_cmode = CMODE_32;
3185 break;
3186 }
3187 }
3188 #endif
3189 #ifdef CONFIG_ATARI
3190 /*
3191 * Why do we need this silly Mach64 argument?
3192 * We are already here because of mach64= so its redundant.
3193 */
3194 else if (MACH_IS_ATARI && (!strncmp(this_opt, "Mach64:", 7))) {
3195 static unsigned char m64_num;
3196 static char mach64_str[80];
3197 strncpy(mach64_str, this_opt+7, 80);
3198 if (!store_video_par(mach64_str, m64_num)) {
3199 m64_num++;
3200 mach64_count = m64_num;
3201 }
3202 }
3203 #endif
3204 }
3205 }
3206
3207 #ifdef CONFIG_ATARI
3208 __initfunc(static int store_video_par(char *video_str, unsigned char m64_num))
3209 {
3210 char *p;
3211 unsigned long vmembase, size, guiregbase;
3212
3213 printk("store_video_par() '%s' \n", video_str);
3214
3215 if (!(p = strtoke(video_str, ";")) || !*p)
3216 goto mach64_invalid;
3217 vmembase = simple_strtoul(p, NULL, 0);
3218 if (!(p = strtoke(NULL, ";")) || !*p)
3219 goto mach64_invalid;
3220 size = simple_strtoul(p, NULL, 0);
3221 if (!(p = strtoke(NULL, ";")) || !*p)
3222 goto mach64_invalid;
3223 guiregbase = simple_strtoul(p, NULL, 0);
3224
3225 phys_vmembase[m64_num] = vmembase;
3226 phys_size[m64_num] = size;
3227 phys_guiregbase[m64_num] = guiregbase;
3228 printk(" stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
3229 guiregbase);
3230 return 0;
3231
3232 mach64_invalid:
3233 phys_vmembase[m64_num] = 0;
3234 return -1;
3235 }
3236
3237 __initfunc(static char *strtoke(char *s, const char *ct))
3238 {
3239 static char *ssave = NULL;
3240 char *sbegin, *send;
3241
3242 sbegin = s ? s : ssave;
3243 if (!sbegin)
3244 return NULL;
3245 if (*sbegin == '\0') {
3246 ssave = NULL;
3247 return NULL;
3248 }
3249 send = strpbrk(sbegin, ct);
3250 if (send && *send != '\0')
3251 *send++ = '\0';
3252 ssave = send;
3253 return sbegin;
3254 }
3255 #endif /* CONFIG_ATARI */
3256
3257 static int atyfbcon_switch(int con, struct fb_info *fb)
3258 {
3259 struct fb_info_aty *info = (struct fb_info_aty *)fb;
3260 struct atyfb_par par;
3261
3262 /* Do we have to save the colormap? */
3263 if (fb_display[currcon].cmap.len)
3264 fb_get_cmap(&fb_display[currcon].cmap, 1, atyfb_getcolreg, fb);
3265
3266 /* Erase HW Cursor */
3267 if (info->cursor)
3268 atyfb_cursor(&fb_display[currcon], CM_ERASE,
3269 info->cursor->pos.x, info->cursor->pos.y);
3270
3271 currcon = con;
3272
3273 atyfb_decode_var(&fb_display[con].var, &par, info);
3274 atyfb_set_par(&par, info);
3275 atyfb_set_disp(&fb_display[con], info, par.crtc.bpp,
3276 par.accel_flags & FB_ACCELF_TEXT);
3277
3278 /* Install new colormap */
3279 do_install_cmap(con, fb);
3280
3281 /* Install hw cursor */
3282 if (info->cursor) {
3283 aty_set_cursor_color(info, cursor_pixel_map, cursor_color_map,
3284 cursor_color_map, cursor_color_map);
3285 aty_set_cursor_shape(info);
3286 }
3287 return 1;
3288 }
3289
3290 /*
3291 * Blank the display.
3292 */
3293
3294 static void atyfbcon_blank(int blank, struct fb_info *fb)
3295 {
3296 struct fb_info_aty *info = (struct fb_info_aty *)fb;
3297 u8 gen_cntl;
3298
3299 gen_cntl = aty_ld_8(CRTC_GEN_CNTL, info);
3300 if (blank > 0)
3301 switch (blank-1) {
3302 case VESA_NO_BLANKING:
3303 gen_cntl |= 0x40;
3304 break;
3305 case VESA_VSYNC_SUSPEND:
3306 gen_cntl |= 0x8;
3307 break;
3308 case VESA_HSYNC_SUSPEND:
3309 gen_cntl |= 0x4;
3310 break;
3311 case VESA_POWERDOWN:
3312 gen_cntl |= 0x4c;
3313 break;
3314 }
3315 else
3316 gen_cntl &= ~(0x4c);
3317 aty_st_8(CRTC_GEN_CNTL, gen_cntl, info);
3318 }
3319
3320
3321 /*
3322 * Read a single color register and split it into
3323 * colors/transparent. Return != 0 for invalid regno.
3324 */
3325
3326 static int atyfb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
3327 u_int *transp, struct fb_info *fb)
3328 {
3329 struct fb_info_aty *info = (struct fb_info_aty *)fb;
3330
3331 if (regno > 255)
3332 return 1;
3333 *red = (info->palette[regno].red<<8) | info->palette[regno].red;
3334 *green = (info->palette[regno].green<<8) | info->palette[regno].green;
3335 *blue = (info->palette[regno].blue<<8) | info->palette[regno].blue;
3336 *transp = 0;
3337 return 0;
3338 }
3339
3340
3341 /*
3342 * Set a single color register. The values supplied are already
3343 * rounded down to the hardware's capabilities (according to the
3344 * entries in the var structure). Return != 0 for invalid regno.
3345 */
3346
3347 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
3348 u_int transp, struct fb_info *fb)
3349 {
3350 struct fb_info_aty *info = (struct fb_info_aty *)fb;
3351 int i, scale;
3352
3353 if (regno > 255)
3354 return 1;
3355 red >>= 8;
3356 green >>= 8;
3357 blue >>= 8;
3358 info->palette[regno].red = red;
3359 info->palette[regno].green = green;
3360 info->palette[regno].blue = blue;
3361 i = aty_ld_8(DAC_CNTL, info) & 0xfc;
3362 if ((Gx == GT_CHIP_ID) || (Gx == GU_CHIP_ID) || (Gx == LG_CHIP_ID) ||
3363 (Gx == GB_CHIP_ID) || (Gx == GD_CHIP_ID) || (Gx == GI_CHIP_ID) ||
3364 (Gx == GP_CHIP_ID) || (Gx == GQ_CHIP_ID))
3365 i |= 0x2; /*DAC_CNTL|0x2 turns off the extra brightness for gt*/
3366 aty_st_8(DAC_CNTL, i, info);
3367 aty_st_8(DAC_MASK, 0xff, info);
3368 eieio();
3369 scale = ((Gx != GX_CHIP_ID) && (Gx != CX_CHIP_ID) &&
3370 (info->current_par.crtc.bpp == 16)) ? 3 : 0;
3371 info->aty_cmap_regs->windex = regno << scale;
3372 eieio();
3373 info->aty_cmap_regs->lut = red;
3374 eieio();
3375 info->aty_cmap_regs->lut = green;
3376 eieio();
3377 info->aty_cmap_regs->lut = blue;
3378 eieio();
3379 if (regno < 16)
3380 switch (info->current_par.crtc.bpp) {
3381 #ifdef FBCON_HAS_CFB16
3382 case 16:
3383 info->fbcon_cmap.cfb16[regno] = (regno << 10) | (regno << 5) |
3384 regno;
3385 break;
3386 #endif
3387 #ifdef FBCON_HAS_CFB24
3388 case 24:
3389 info->fbcon_cmap.cfb24[regno] = (regno << 16) | (regno << 8) |
3390 regno;
3391 break;
3392 #endif
3393 #ifdef FBCON_HAS_CFB32
3394 case 32:
3395 i = (regno << 8) | regno;
3396 info->fbcon_cmap.cfb32[regno] = (i << 16) | i;
3397 break;
3398 #endif
3399 }
3400 return 0;
3401 }
3402
3403
3404 static void do_install_cmap(int con, struct fb_info *info)
3405 {
3406 if (con != currcon)
3407 return;
3408 if (fb_display[con].cmap.len)
3409 fb_set_cmap(&fb_display[con].cmap, 1, atyfb_setcolreg, info);
3410 else {
3411 int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256;
3412 fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, info);
3413 }
3414 }
3415
3416
3417 /*
3418 * Accelerated functions
3419 */
3420
3421 static inline void draw_rect(s16 x, s16 y, u16 width, u16 height,
3422 struct fb_info_aty *info)
3423 {
3424 /* perform rectangle fill */
3425 wait_for_fifo(2, info);
3426 aty_st_le32(DST_Y_X, (x << 16) | y, info);
3427 aty_st_le32(DST_HEIGHT_WIDTH, (width << 16) | height, info);
3428 info->blitter_may_be_busy = 1;
3429 }
3430
3431 static inline void aty_rectcopy(int srcx, int srcy, int dstx, int dsty,
3432 u_int width, u_int height,
3433 struct fb_info_aty *info)
3434 {
3435 u32 direction = DST_LAST_PEL;
3436 u32 pitch_value;
3437
3438 if (!width || !height)
3439 return;
3440
3441 pitch_value = info->current_par.crtc.vxres;
3442 if (info->current_par.crtc.bpp == 24) {
3443 /* In 24 bpp, the engine is in 8 bpp - this requires that all */
3444 /* horizontal coordinates and widths must be adjusted */
3445 pitch_value *= 3;
3446 srcx *= 3;
3447 dstx *= 3;
3448 width *= 3;
3449 }
3450
3451 if (srcy < dsty) {
3452 dsty += height - 1;
3453 srcy += height - 1;
3454 } else
3455 direction |= DST_Y_TOP_TO_BOTTOM;
3456
3457 if (srcx < dstx) {
3458 dstx += width - 1;
3459 srcx += width - 1;
3460 } else
3461 direction |= DST_X_LEFT_TO_RIGHT;
3462
3463 wait_for_fifo(4, info);
3464 aty_st_le32(DP_SRC, FRGD_SRC_BLIT, info);
3465 aty_st_le32(SRC_Y_X, (srcx << 16) | srcy, info);
3466 aty_st_le32(SRC_HEIGHT1_WIDTH1, (width << 16) | height, info);
3467 aty_st_le32(DST_CNTL, direction, info);
3468 draw_rect(dstx, dsty, width, height, info);
3469 }
3470
3471 static inline void aty_rectfill(int dstx, int dsty, u_int width, u_int height,
3472 u_int color, struct fb_info_aty *info)
3473 {
3474 if (!width || !height)
3475 return;
3476
3477 if (info->current_par.crtc.bpp == 24) {
3478 /* In 24 bpp, the engine is in 8 bpp - this requires that all */
3479 /* horizontal coordinates and widths must be adjusted */
3480 dstx *= 3;
3481 width *= 3;
3482 }
3483
3484 wait_for_fifo(3, info);
3485 aty_st_le32(DP_FRGD_CLR, color, info);
3486 aty_st_le32(DP_SRC, BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR | MONO_SRC_ONE,
3487 info);
3488 aty_st_le32(DST_CNTL, DST_LAST_PEL | DST_Y_TOP_TO_BOTTOM |
3489 DST_X_LEFT_TO_RIGHT, info);
3490 draw_rect(dstx, dsty, width, height, info);
3491 }
3492
3493 /*
3494 * Update the `var' structure (called by fbcon.c)
3495 */
3496
3497 static int atyfbcon_updatevar(int con, struct fb_info *fb)
3498 {
3499 struct fb_info_aty *info = (struct fb_info_aty *)fb;
3500 struct atyfb_par *par = &info->current_par;
3501 struct display *p = &fb_display[con];
3502 struct vc_data *conp = p->conp;
3503 u32 yres, yoffset, sy, height;
3504
3505 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
3506 yoffset = fb_display[con].var.yoffset;
3507
3508 sy = (conp->vc_rows + p->yscroll) * fontheight(p);
3509 height = yres - conp->vc_rows * fontheight(p);
3510
3511 if (height && (yoffset + yres > sy)) {
3512 u32 xres, xoffset;
3513 u32 bgx;
3514
3515 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
3516 xoffset = fb_display[con].var.xoffset;
3517
3518
3519 bgx = attr_bgcol_ec(p, conp);
3520 bgx |= (bgx << 8);
3521 bgx |= (bgx << 16);
3522
3523 if (sy + height > par->crtc.vyres) {
3524 wait_for_fifo(1, info);
3525 aty_st_le32(SC_BOTTOM, sy + height - 1, info);
3526 }
3527 aty_rectfill(xoffset, sy, xres, height, bgx, info);
3528 }
3529
3530 if (info->cursor && (yoffset + yres <= sy))
3531 atyfb_cursor(p, CM_ERASE, info->cursor->pos.x, info->cursor->pos.y);
3532
3533 info->current_par.crtc.yoffset = yoffset;
3534 set_off_pitch(&info->current_par, info);
3535 return 0;
3536 }
3537
3538 /*
3539 * Text console acceleration
3540 */
3541
3542 static void fbcon_aty_bmove(struct display *p, int sy, int sx, int dy, int dx,
3543 int height, int width)
3544 {
3545 #ifdef __sparc__
3546 struct fb_info_aty *fb = (struct fb_info_aty *)(p->fb_info);
3547
3548 if (fb->mmaped && currcon == fb->vtconsole)
3549 return;
3550 #endif
3551
3552 sx *= fontwidth(p);
3553 sy *= fontheight(p);
3554 dx *= fontwidth(p);
3555 dy *= fontheight(p);
3556 width *= fontwidth(p);
3557 height *= fontheight(p);
3558
3559 aty_rectcopy(sx, sy, dx, dy, width, height,
3560 (struct fb_info_aty *)p->fb_info);
3561 }
3562
3563 static void fbcon_aty_clear(struct vc_data *conp, struct display *p, int sy,
3564 int sx, int height, int width)
3565 {
3566 u32 bgx;
3567 #ifdef __sparc__
3568 struct fb_info_aty *fb = (struct fb_info_aty *)(p->fb_info);
3569
3570 if (fb->mmaped && currcon == fb->vtconsole)
3571 return;
3572 #endif
3573
3574 bgx = attr_bgcol_ec(p, conp);
3575 bgx |= (bgx << 8);
3576 bgx |= (bgx << 16);
3577
3578 sx *= fontwidth(p);
3579 sy *= fontheight(p);
3580 width *= fontwidth(p);
3581 height *= fontheight(p);
3582
3583 aty_rectfill(sx, sy, width, height, bgx,
3584 (struct fb_info_aty *)p->fb_info);
3585 }
3586
3587 #ifdef FBCON_HAS_CFB8
3588 static void fbcon_aty8_putc(struct vc_data *conp, struct display *p, int c,
3589 int yy, int xx)
3590 {
3591 struct fb_info_aty *fb = (struct fb_info_aty *)(p->fb_info);
3592
3593 #ifdef __sparc__
3594 if (fb->mmaped && currcon == fb->vtconsole)
3595 return;
3596 #endif
3597
3598 if (fb->blitter_may_be_busy)
3599 wait_for_idle((struct fb_info_aty *)p->fb_info);
3600 fbcon_cfb8_putc(conp, p, c, yy, xx);
3601 }
3602
3603 static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p,
3604 const unsigned short *s, int count, int yy,
3605 int xx)
3606 {
3607 struct fb_info_aty *fb = (struct fb_info_aty *)(p->fb_info);
3608
3609 #ifdef __sparc__
3610 if (fb->mmaped && currcon == fb->vtconsole)
3611 return;
3612 #endif
3613
3614 if (fb->blitter_may_be_busy)
3615 wait_for_idle((struct fb_info_aty *)p->fb_info);
3616 fbcon_cfb8_putcs(conp, p, s, count, yy, xx);
3617 }
3618
3619 static void fbcon_aty8_clear_margins(struct vc_data *conp, struct display *p,
3620 int bottom_only)
3621 {
3622 struct fb_info_aty *fb = (struct fb_info_aty *)(p->fb_info);
3623
3624 #ifdef __sparc__
3625 if (fb->mmaped && currcon == fb->vtconsole)
3626 return;
3627 #endif
3628
3629 if (fb->blitter_may_be_busy)
3630 wait_for_idle((struct fb_info_aty *)p->fb_info);
3631 fbcon_cfb8_clear_margins(conp, p, bottom_only);
3632 }
3633
3634 static struct display_switch fbcon_aty8 = {
3635 fbcon_cfb8_setup, fbcon_aty_bmove, fbcon_aty_clear, fbcon_aty8_putc,
3636 fbcon_aty8_putcs, fbcon_cfb8_revc, NULL, NULL, fbcon_aty8_clear_margins,
3637 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
3638 };
3639 #endif
3640
3641 #ifdef FBCON_HAS_CFB16
3642 static void fbcon_aty16_putc(struct vc_data *conp, struct display *p, int c,
3643 int yy, int xx)
3644 {
3645 struct fb_info_aty *fb = (struct fb_info_aty *)(p->fb_info);
3646
3647 #ifdef __sparc__
3648 if (fb->mmaped && currcon == fb->vtconsole)
3649 return;
3650 #endif
3651
3652 if (fb->blitter_may_be_busy)
3653 wait_for_idle((struct fb_info_aty *)p->fb_info);
3654 fbcon_cfb16_putc(conp, p, c, yy, xx);
3655 }
3656
3657 static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p,
3658 const unsigned short *s, int count, int yy,
3659 int xx)
3660 {
3661 struct fb_info_aty *fb = (struct fb_info_aty *)(p->fb_info);
3662
3663 #ifdef __sparc__
3664 if (fb->mmaped && currcon == fb->vtconsole)
3665 return;
3666 #endif
3667
3668 if (fb->blitter_may_be_busy)
3669 wait_for_idle((struct fb_info_aty *)p->fb_info);
3670 fbcon_cfb16_putcs(conp, p, s, count, yy, xx);
3671 }
3672
3673 static void fbcon_aty16_clear_margins(struct vc_data *conp, struct display *p,
3674 int bottom_only)
3675 {
3676 struct fb_info_aty *fb = (struct fb_info_aty *)(p->fb_info);
3677
3678 #ifdef __sparc__
3679 if (fb->mmaped && currcon == fb->vtconsole)
3680 return;
3681 #endif
3682
3683 if (fb->blitter_may_be_busy)
3684 wait_for_idle((struct fb_info_aty *)p->fb_info);
3685 fbcon_cfb16_clear_margins(conp, p, bottom_only);
3686 }
3687
3688 static struct display_switch fbcon_aty16 = {
3689 fbcon_cfb16_setup, fbcon_aty_bmove, fbcon_aty_clear, fbcon_aty16_putc,
3690 fbcon_aty16_putcs, fbcon_cfb16_revc, NULL, NULL, fbcon_aty16_clear_margins,
3691 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
3692 };
3693 #endif
3694
3695 #ifdef FBCON_HAS_CFB24
3696 static void fbcon_aty24_putc(struct vc_data *conp, struct display *p, int c,
3697 int yy, int xx)
3698 {
3699 struct fb_info_aty *fb = (struct fb_info_aty *)(p->fb_info);
3700
3701 #ifdef __sparc__
3702 if (fb->mmaped && currcon == fb->vtconsole)
3703 return;
3704 #endif
3705
3706 if (fb->blitter_may_be_busy)
3707 wait_for_idle((struct fb_info_aty *)p->fb_info);
3708 fbcon_cfb24_putc(conp, p, c, yy, xx);
3709 }
3710
3711 static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p,
3712 const unsigned short *s, int count, int yy,
3713 int xx)
3714 {
3715 struct fb_info_aty *fb = (struct fb_info_aty *)(p->fb_info);
3716
3717 #ifdef __sparc__
3718 if (fb->mmaped && currcon == fb->vtconsole)
3719 return;
3720 #endif
3721
3722 if (fb->blitter_may_be_busy)
3723 wait_for_idle((struct fb_info_aty *)p->fb_info);
3724 fbcon_cfb24_putcs(conp, p, s, count, yy, xx);
3725 }
3726
3727 static void fbcon_aty24_clear_margins(struct vc_data *conp, struct display *p,
3728 int bottom_only)
3729 {
3730 struct fb_info_aty *fb = (struct fb_info_aty *)(p->fb_info);
3731
3732 #ifdef __sparc__
3733 if (fb->mmaped && currcon == fb->vtconsole)
3734 return;
3735 #endif
3736
3737 if (fb->blitter_may_be_busy)
3738 wait_for_idle((struct fb_info_aty *)p->fb_info);
3739 fbcon_cfb24_clear_margins(conp, p, bottom_only);
3740 }
3741
3742 static struct display_switch fbcon_aty24 = {
3743 fbcon_cfb24_setup, fbcon_aty_bmove, fbcon_aty_clear, fbcon_aty24_putc,
3744 fbcon_aty24_putcs, fbcon_cfb24_revc, NULL, NULL, fbcon_aty24_clear_margins,
3745 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
3746 };
3747 #endif
3748
3749 #ifdef FBCON_HAS_CFB32
3750 static void fbcon_aty32_putc(struct vc_data *conp, struct display *p, int c,
3751 int yy, int xx)
3752 {
3753 struct fb_info_aty *fb = (struct fb_info_aty *)(p->fb_info);
3754
3755 #ifdef __sparc__
3756 if (fb->mmaped && currcon == fb->vtconsole)
3757 return;
3758 #endif
3759
3760 if (fb->blitter_may_be_busy)
3761 wait_for_idle((struct fb_info_aty *)p->fb_info);
3762 fbcon_cfb32_putc(conp, p, c, yy, xx);
3763 }
3764
3765 static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p,
3766 const unsigned short *s, int count, int yy,
3767 int xx)
3768 {
3769 struct fb_info_aty *fb = (struct fb_info_aty *)(p->fb_info);
3770
3771 #ifdef __sparc__
3772 if (fb->mmaped && currcon == fb->vtconsole)
3773 return;
3774 #endif
3775
3776 if (fb->blitter_may_be_busy)
3777 wait_for_idle((struct fb_info_aty *)p->fb_info);
3778 fbcon_cfb32_putcs(conp, p, s, count, yy, xx);
3779 }
3780
3781 static void fbcon_aty32_clear_margins(struct vc_data *conp, struct display *p,
3782 int bottom_only)
3783 {
3784 struct fb_info_aty *fb = (struct fb_info_aty *)(p->fb_info);
3785
3786 #ifdef __sparc__
3787 if (fb->mmaped && currcon == fb->vtconsole)
3788 return;
3789 #endif
3790
3791 if (fb->blitter_may_be_busy)
3792 wait_for_idle((struct fb_info_aty *)p->fb_info);
3793 fbcon_cfb32_clear_margins(conp, p, bottom_only);
3794 }
3795
3796 static struct display_switch fbcon_aty32 = {
3797 fbcon_cfb32_setup, fbcon_aty_bmove, fbcon_aty_clear, fbcon_aty32_putc,
3798 fbcon_aty32_putcs, fbcon_cfb32_revc, NULL, NULL, fbcon_aty32_clear_margins,
3799 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
3800 };
3801 #endif
Copy of Dave Jones history.git as used by http://archive.org/details/git-history-of-linux