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sata_promise: fix error decode regression
[ccrypt.git] / drivers / ata / sata_promise.c
bloba7916d72c4caccc9282eecc6e19d19faeaa47563
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include "sata_promise.h"
46
47 #define DRV_NAME "sata_promise"
48 #define DRV_VERSION "2.05"
49
50
51 enum {
52 PDC_MMIO_BAR = 3,
53
54 /* register offsets */
55 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
56 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
57 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
58 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
59 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
60 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
61 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
62 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
63 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
64 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
65 PDC_FLASH_CTL = 0x44, /* Flash control register */
66 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
67 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
68 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
69 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
70 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
71 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
72
73 /* PDC_GLOBAL_CTL bit definitions */
74 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
75 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
76 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
77 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
78 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
79 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
80 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
81 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
82 PDC_DRIVE_ERR = (1 << 21), /* drive error */
83 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
84 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
85 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
86 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR,
87 PDC_ERR_MASK = (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC_OVERRUN_ERR
88 | PDC_UNDERRUN_ERR | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR
89 | PDC1_ERR_MASK | PDC2_ERR_MASK),
90
91 board_2037x = 0, /* FastTrak S150 TX2plus */
92 board_20319 = 1, /* FastTrak S150 TX4 */
93 board_20619 = 2, /* FastTrak TX4000 */
94 board_2057x = 3, /* SATAII150 Tx2plus */
95 board_40518 = 4, /* SATAII150 Tx4 */
96
97 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
98
99 /* Sequence counter control registers bit definitions */
100 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
101
102 /* Feature register values */
103 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
104 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
105
106 /* Device/Head register values */
107 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
108
109 /* PDC_CTLSTAT bit definitions */
110 PDC_DMA_ENABLE = (1 << 7),
111 PDC_IRQ_DISABLE = (1 << 10),
112 PDC_RESET = (1 << 11), /* HDMA reset */
113
114 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
115 ATA_FLAG_MMIO |
116 ATA_FLAG_PIO_POLLING,
117
118 /* hp->flags bits */
119 PDC_FLAG_GEN_II = (1 << 0),
120 };
121
122
123 struct pdc_port_priv {
124 u8 *pkt;
125 dma_addr_t pkt_dma;
126 };
127
128 struct pdc_host_priv {
129 unsigned long flags;
130 unsigned long port_flags[ATA_MAX_PORTS];
131 };
132
133 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
134 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
135 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
136 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
137 static int pdc_port_start(struct ata_port *ap);
138 static void pdc_qc_prep(struct ata_queued_cmd *qc);
139 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
140 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
141 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
142 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
143 static void pdc_irq_clear(struct ata_port *ap);
144 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
145 static void pdc_freeze(struct ata_port *ap);
146 static void pdc_thaw(struct ata_port *ap);
147 static void pdc_pata_error_handler(struct ata_port *ap);
148 static void pdc_sata_error_handler(struct ata_port *ap);
149 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
150 static int pdc_pata_cable_detect(struct ata_port *ap);
151 static int pdc_sata_cable_detect(struct ata_port *ap);
152
153 static struct scsi_host_template pdc_ata_sht = {
154 .module = THIS_MODULE,
155 .name = DRV_NAME,
156 .ioctl = ata_scsi_ioctl,
157 .queuecommand = ata_scsi_queuecmd,
158 .can_queue = ATA_DEF_QUEUE,
159 .this_id = ATA_SHT_THIS_ID,
160 .sg_tablesize = LIBATA_MAX_PRD,
161 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
162 .emulated = ATA_SHT_EMULATED,
163 .use_clustering = ATA_SHT_USE_CLUSTERING,
164 .proc_name = DRV_NAME,
165 .dma_boundary = ATA_DMA_BOUNDARY,
166 .slave_configure = ata_scsi_slave_config,
167 .slave_destroy = ata_scsi_slave_destroy,
168 .bios_param = ata_std_bios_param,
169 };
170
171 static const struct ata_port_operations pdc_sata_ops = {
172 .port_disable = ata_port_disable,
173 .tf_load = pdc_tf_load_mmio,
174 .tf_read = ata_tf_read,
175 .check_status = ata_check_status,
176 .exec_command = pdc_exec_command_mmio,
177 .dev_select = ata_std_dev_select,
178 .check_atapi_dma = pdc_check_atapi_dma,
179
180 .qc_prep = pdc_qc_prep,
181 .qc_issue = pdc_qc_issue_prot,
182 .freeze = pdc_freeze,
183 .thaw = pdc_thaw,
184 .error_handler = pdc_sata_error_handler,
185 .post_internal_cmd = pdc_post_internal_cmd,
186 .cable_detect = pdc_sata_cable_detect,
187 .data_xfer = ata_data_xfer,
188 .irq_handler = pdc_interrupt,
189 .irq_clear = pdc_irq_clear,
190 .irq_on = ata_irq_on,
191 .irq_ack = ata_irq_ack,
192
193 .scr_read = pdc_sata_scr_read,
194 .scr_write = pdc_sata_scr_write,
195 .port_start = pdc_port_start,
196 };
197
198 /* First-generation chips need a more restrictive ->check_atapi_dma op */
199 static const struct ata_port_operations pdc_old_sata_ops = {
200 .port_disable = ata_port_disable,
201 .tf_load = pdc_tf_load_mmio,
202 .tf_read = ata_tf_read,
203 .check_status = ata_check_status,
204 .exec_command = pdc_exec_command_mmio,
205 .dev_select = ata_std_dev_select,
206 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
207
208 .qc_prep = pdc_qc_prep,
209 .qc_issue = pdc_qc_issue_prot,
210 .freeze = pdc_freeze,
211 .thaw = pdc_thaw,
212 .error_handler = pdc_sata_error_handler,
213 .post_internal_cmd = pdc_post_internal_cmd,
214 .cable_detect = pdc_sata_cable_detect,
215 .data_xfer = ata_data_xfer,
216 .irq_handler = pdc_interrupt,
217 .irq_clear = pdc_irq_clear,
218 .irq_on = ata_irq_on,
219 .irq_ack = ata_irq_ack,
220
221 .scr_read = pdc_sata_scr_read,
222 .scr_write = pdc_sata_scr_write,
223 .port_start = pdc_port_start,
224 };
225
226 static const struct ata_port_operations pdc_pata_ops = {
227 .port_disable = ata_port_disable,
228 .tf_load = pdc_tf_load_mmio,
229 .tf_read = ata_tf_read,
230 .check_status = ata_check_status,
231 .exec_command = pdc_exec_command_mmio,
232 .dev_select = ata_std_dev_select,
233 .check_atapi_dma = pdc_check_atapi_dma,
234
235 .qc_prep = pdc_qc_prep,
236 .qc_issue = pdc_qc_issue_prot,
237 .freeze = pdc_freeze,
238 .thaw = pdc_thaw,
239 .error_handler = pdc_pata_error_handler,
240 .post_internal_cmd = pdc_post_internal_cmd,
241 .cable_detect = pdc_pata_cable_detect,
242 .data_xfer = ata_data_xfer,
243 .irq_handler = pdc_interrupt,
244 .irq_clear = pdc_irq_clear,
245 .irq_on = ata_irq_on,
246 .irq_ack = ata_irq_ack,
247
248 .port_start = pdc_port_start,
249 };
250
251 static const struct ata_port_info pdc_port_info[] = {
252 /* board_2037x */
253 {
254 .sht = &pdc_ata_sht,
255 .flags = PDC_COMMON_FLAGS,
256 .pio_mask = 0x1f, /* pio0-4 */
257 .mwdma_mask = 0x07, /* mwdma0-2 */
258 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
259 .port_ops = &pdc_old_sata_ops,
260 },
261
262 /* board_20319 */
263 {
264 .sht = &pdc_ata_sht,
265 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
266 .pio_mask = 0x1f, /* pio0-4 */
267 .mwdma_mask = 0x07, /* mwdma0-2 */
268 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
269 .port_ops = &pdc_old_sata_ops,
270 },
271
272 /* board_20619 */
273 {
274 .sht = &pdc_ata_sht,
275 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
276 .pio_mask = 0x1f, /* pio0-4 */
277 .mwdma_mask = 0x07, /* mwdma0-2 */
278 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
279 .port_ops = &pdc_pata_ops,
280 },
281
282 /* board_2057x */
283 {
284 .sht = &pdc_ata_sht,
285 .flags = PDC_COMMON_FLAGS,
286 .pio_mask = 0x1f, /* pio0-4 */
287 .mwdma_mask = 0x07, /* mwdma0-2 */
288 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
289 .port_ops = &pdc_sata_ops,
290 },
291
292 /* board_40518 */
293 {
294 .sht = &pdc_ata_sht,
295 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
296 .pio_mask = 0x1f, /* pio0-4 */
297 .mwdma_mask = 0x07, /* mwdma0-2 */
298 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
299 .port_ops = &pdc_sata_ops,
300 },
301 };
302
303 static const struct pci_device_id pdc_ata_pci_tbl[] = {
304 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
305 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
306 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
307 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
308 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
309 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
310 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
311 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
312 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
313 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
314
315 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
316 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
317 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
318 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
319 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
320 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
321
322 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
323
324 { } /* terminate list */
325 };
326
327
328 static struct pci_driver pdc_ata_pci_driver = {
329 .name = DRV_NAME,
330 .id_table = pdc_ata_pci_tbl,
331 .probe = pdc_ata_init_one,
332 .remove = ata_pci_remove_one,
333 };
334
335
336 static int pdc_common_port_start(struct ata_port *ap)
337 {
338 struct device *dev = ap->host->dev;
339 struct pdc_port_priv *pp;
340 int rc;
341
342 rc = ata_port_start(ap);
343 if (rc)
344 return rc;
345
346 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
347 if (!pp)
348 return -ENOMEM;
349
350 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
351 if (!pp->pkt)
352 return -ENOMEM;
353
354 ap->private_data = pp;
355
356 return 0;
357 }
358
359 static int pdc_sata_port_start(struct ata_port *ap)
360 {
361 struct pdc_host_priv *hp = ap->host->private_data;
362 int rc;
363
364 rc = pdc_common_port_start(ap);
365 if (rc)
366 return rc;
367
368 /* fix up PHYMODE4 align timing */
369 if (hp->flags & PDC_FLAG_GEN_II) {
370 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
371 unsigned int tmp;
372
373 tmp = readl(mmio + 0x014);
374 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
375 writel(tmp, mmio + 0x014);
376 }
377
378 return 0;
379 }
380
381 static int pdc_port_start(struct ata_port *ap)
382 {
383 struct pdc_host_priv *hp = ap->host->private_data;
384
385 /* fix up port flags and cable type for SATA+PATA chips */
386 ap->flags |= hp->port_flags[ap->port_no];
387 if (ap->flags & ATA_FLAG_SATA) {
388 ap->cbl = ATA_CBL_SATA;
389 return pdc_sata_port_start(ap);
390 } else {
391 ap->ops = &pdc_pata_ops;
392 return pdc_common_port_start(ap);
393 }
394 }
395
396 static void pdc_reset_port(struct ata_port *ap)
397 {
398 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
399 unsigned int i;
400 u32 tmp;
401
402 for (i = 11; i > 0; i--) {
403 tmp = readl(mmio);
404 if (tmp & PDC_RESET)
405 break;
406
407 udelay(100);
408
409 tmp |= PDC_RESET;
410 writel(tmp, mmio);
411 }
412
413 tmp &= ~PDC_RESET;
414 writel(tmp, mmio);
415 readl(mmio); /* flush */
416 }
417
418 static int pdc_pata_cable_detect(struct ata_port *ap)
419 {
420 u8 tmp;
421 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
422
423 tmp = readb(mmio);
424 if (tmp & 0x01)
425 return ATA_CBL_PATA40;
426 return ATA_CBL_PATA80;
427 }
428
429 static int pdc_sata_cable_detect(struct ata_port *ap)
430 {
431 return ATA_CBL_SATA;
432 }
433
434 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
435 {
436 if (sc_reg > SCR_CONTROL)
437 return 0xffffffffU;
438 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
439 }
440
441
442 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
443 u32 val)
444 {
445 if (sc_reg > SCR_CONTROL)
446 return;
447 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
448 }
449
450 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
451 {
452 struct ata_port *ap = qc->ap;
453 dma_addr_t sg_table = ap->prd_dma;
454 unsigned int cdb_len = qc->dev->cdb_len;
455 u8 *cdb = qc->cdb;
456 struct pdc_port_priv *pp = ap->private_data;
457 u8 *buf = pp->pkt;
458 u32 *buf32 = (u32 *) buf;
459 unsigned int dev_sel, feature, nbytes;
460
461 /* set control bits (byte 0), zero delay seq id (byte 3),
462 * and seq id (byte 2)
463 */
464 switch (qc->tf.protocol) {
465 case ATA_PROT_ATAPI_DMA:
466 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
467 buf32[0] = cpu_to_le32(PDC_PKT_READ);
468 else
469 buf32[0] = 0;
470 break;
471 case ATA_PROT_ATAPI_NODATA:
472 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
473 break;
474 default:
475 BUG();
476 break;
477 }
478 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
479 buf32[2] = 0; /* no next-packet */
480
481 /* select drive */
482 if (sata_scr_valid(ap)) {
483 dev_sel = PDC_DEVICE_SATA;
484 } else {
485 dev_sel = ATA_DEVICE_OBS;
486 if (qc->dev->devno != 0)
487 dev_sel |= ATA_DEV1;
488 }
489 buf[12] = (1 << 5) | ATA_REG_DEVICE;
490 buf[13] = dev_sel;
491 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
492 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
493
494 buf[16] = (1 << 5) | ATA_REG_NSECT;
495 buf[17] = 0x00;
496 buf[18] = (1 << 5) | ATA_REG_LBAL;
497 buf[19] = 0x00;
498
499 /* set feature and byte counter registers */
500 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
501 feature = PDC_FEATURE_ATAPI_PIO;
502 /* set byte counter register to real transfer byte count */
503 nbytes = qc->nbytes;
504 if (nbytes > 0xffff)
505 nbytes = 0xffff;
506 } else {
507 feature = PDC_FEATURE_ATAPI_DMA;
508 /* set byte counter register to 0 */
509 nbytes = 0;
510 }
511 buf[20] = (1 << 5) | ATA_REG_FEATURE;
512 buf[21] = feature;
513 buf[22] = (1 << 5) | ATA_REG_BYTEL;
514 buf[23] = nbytes & 0xFF;
515 buf[24] = (1 << 5) | ATA_REG_BYTEH;
516 buf[25] = (nbytes >> 8) & 0xFF;
517
518 /* send ATAPI packet command 0xA0 */
519 buf[26] = (1 << 5) | ATA_REG_CMD;
520 buf[27] = ATA_CMD_PACKET;
521
522 /* select drive and check DRQ */
523 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
524 buf[29] = dev_sel;
525
526 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
527 BUG_ON(cdb_len & ~0x1E);
528
529 /* append the CDB as the final part */
530 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
531 memcpy(buf+31, cdb, cdb_len);
532 }
533
534 static void pdc_qc_prep(struct ata_queued_cmd *qc)
535 {
536 struct pdc_port_priv *pp = qc->ap->private_data;
537 unsigned int i;
538
539 VPRINTK("ENTER\n");
540
541 switch (qc->tf.protocol) {
542 case ATA_PROT_DMA:
543 ata_qc_prep(qc);
544 /* fall through */
545
546 case ATA_PROT_NODATA:
547 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
548 qc->dev->devno, pp->pkt);
549
550 if (qc->tf.flags & ATA_TFLAG_LBA48)
551 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
552 else
553 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
554
555 pdc_pkt_footer(&qc->tf, pp->pkt, i);
556 break;
557
558 case ATA_PROT_ATAPI:
559 ata_qc_prep(qc);
560 break;
561
562 case ATA_PROT_ATAPI_DMA:
563 ata_qc_prep(qc);
564 /*FALLTHROUGH*/
565 case ATA_PROT_ATAPI_NODATA:
566 pdc_atapi_pkt(qc);
567 break;
568
569 default:
570 break;
571 }
572 }
573
574 static void pdc_freeze(struct ata_port *ap)
575 {
576 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
577 u32 tmp;
578
579 tmp = readl(mmio + PDC_CTLSTAT);
580 tmp |= PDC_IRQ_DISABLE;
581 tmp &= ~PDC_DMA_ENABLE;
582 writel(tmp, mmio + PDC_CTLSTAT);
583 readl(mmio + PDC_CTLSTAT); /* flush */
584 }
585
586 static void pdc_thaw(struct ata_port *ap)
587 {
588 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
589 u32 tmp;
590
591 /* clear IRQ */
592 readl(mmio + PDC_INT_SEQMASK);
593
594 /* turn IRQ back on */
595 tmp = readl(mmio + PDC_CTLSTAT);
596 tmp &= ~PDC_IRQ_DISABLE;
597 writel(tmp, mmio + PDC_CTLSTAT);
598 readl(mmio + PDC_CTLSTAT); /* flush */
599 }
600
601 static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
602 {
603 if (!(ap->pflags & ATA_PFLAG_FROZEN))
604 pdc_reset_port(ap);
605
606 /* perform recovery */
607 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
608 ata_std_postreset);
609 }
610
611 static void pdc_pata_error_handler(struct ata_port *ap)
612 {
613 pdc_common_error_handler(ap, NULL);
614 }
615
616 static void pdc_sata_error_handler(struct ata_port *ap)
617 {
618 pdc_common_error_handler(ap, sata_std_hardreset);
619 }
620
621 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
622 {
623 struct ata_port *ap = qc->ap;
624
625 if (qc->flags & ATA_QCFLAG_FAILED)
626 qc->err_mask |= AC_ERR_OTHER;
627
628 /* make DMA engine forget about the failed command */
629 if (qc->err_mask)
630 pdc_reset_port(ap);
631 }
632
633 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
634 u32 port_status, u32 err_mask)
635 {
636 struct ata_eh_info *ehi = &ap->eh_info;
637 unsigned int ac_err_mask = 0;
638
639 ata_ehi_clear_desc(ehi);
640 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
641 port_status &= err_mask;
642
643 if (port_status & PDC_DRIVE_ERR)
644 ac_err_mask |= AC_ERR_DEV;
645 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
646 ac_err_mask |= AC_ERR_HSM;
647 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
648 ac_err_mask |= AC_ERR_ATA_BUS;
649 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
650 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
651 ac_err_mask |= AC_ERR_HOST_BUS;
652
653 if (sata_scr_valid(ap))
654 ehi->serror |= pdc_sata_scr_read(ap, SCR_ERROR);
655
656 qc->err_mask |= ac_err_mask;
657
658 pdc_reset_port(ap);
659 }
660
661 static inline unsigned int pdc_host_intr( struct ata_port *ap,
662 struct ata_queued_cmd *qc)
663 {
664 unsigned int handled = 0;
665 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
666 struct pdc_host_priv *hp = ap->host->private_data;
667 u32 port_status, err_mask;
668
669 err_mask = PDC_ERR_MASK;
670 if (hp->flags & PDC_FLAG_GEN_II)
671 err_mask &= ~PDC1_ERR_MASK;
672 else
673 err_mask &= ~PDC2_ERR_MASK;
674 port_status = readl(port_mmio + PDC_GLOBAL_CTL);
675 if (unlikely(port_status & err_mask)) {
676 pdc_error_intr(ap, qc, port_status, err_mask);
677 return 1;
678 }
679
680 switch (qc->tf.protocol) {
681 case ATA_PROT_DMA:
682 case ATA_PROT_NODATA:
683 case ATA_PROT_ATAPI_DMA:
684 case ATA_PROT_ATAPI_NODATA:
685 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
686 ata_qc_complete(qc);
687 handled = 1;
688 break;
689
690 default:
691 ap->stats.idle_irq++;
692 break;
693 }
694
695 return handled;
696 }
697
698 static void pdc_irq_clear(struct ata_port *ap)
699 {
700 struct ata_host *host = ap->host;
701 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
702
703 readl(mmio + PDC_INT_SEQMASK);
704 }
705
706 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
707 {
708 struct ata_host *host = dev_instance;
709 struct ata_port *ap;
710 u32 mask = 0;
711 unsigned int i, tmp;
712 unsigned int handled = 0;
713 void __iomem *mmio_base;
714
715 VPRINTK("ENTER\n");
716
717 if (!host || !host->iomap[PDC_MMIO_BAR]) {
718 VPRINTK("QUICK EXIT\n");
719 return IRQ_NONE;
720 }
721
722 mmio_base = host->iomap[PDC_MMIO_BAR];
723
724 /* reading should also clear interrupts */
725 mask = readl(mmio_base + PDC_INT_SEQMASK);
726
727 if (mask == 0xffffffff) {
728 VPRINTK("QUICK EXIT 2\n");
729 return IRQ_NONE;
730 }
731
732 spin_lock(&host->lock);
733
734 mask &= 0xffff; /* only 16 tags possible */
735 if (!mask) {
736 VPRINTK("QUICK EXIT 3\n");
737 goto done_irq;
738 }
739
740 writel(mask, mmio_base + PDC_INT_SEQMASK);
741
742 for (i = 0; i < host->n_ports; i++) {
743 VPRINTK("port %u\n", i);
744 ap = host->ports[i];
745 tmp = mask & (1 << (i + 1));
746 if (tmp && ap &&
747 !(ap->flags & ATA_FLAG_DISABLED)) {
748 struct ata_queued_cmd *qc;
749
750 qc = ata_qc_from_tag(ap, ap->active_tag);
751 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
752 handled += pdc_host_intr(ap, qc);
753 }
754 }
755
756 VPRINTK("EXIT\n");
757
758 done_irq:
759 spin_unlock(&host->lock);
760 return IRQ_RETVAL(handled);
761 }
762
763 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
764 {
765 struct ata_port *ap = qc->ap;
766 struct pdc_port_priv *pp = ap->private_data;
767 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
768 unsigned int port_no = ap->port_no;
769 u8 seq = (u8) (port_no + 1);
770
771 VPRINTK("ENTER, ap %p\n", ap);
772
773 writel(0x00000001, mmio + (seq * 4));
774 readl(mmio + (seq * 4)); /* flush */
775
776 pp->pkt[2] = seq;
777 wmb(); /* flush PRD, pkt writes */
778 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
779 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
780 }
781
782 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
783 {
784 switch (qc->tf.protocol) {
785 case ATA_PROT_ATAPI_NODATA:
786 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
787 break;
788 /*FALLTHROUGH*/
789 case ATA_PROT_ATAPI_DMA:
790 case ATA_PROT_DMA:
791 case ATA_PROT_NODATA:
792 pdc_packet_start(qc);
793 return 0;
794
795 default:
796 break;
797 }
798
799 return ata_qc_issue_prot(qc);
800 }
801
802 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
803 {
804 WARN_ON (tf->protocol == ATA_PROT_DMA ||
805 tf->protocol == ATA_PROT_NODATA);
806 ata_tf_load(ap, tf);
807 }
808
809
810 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
811 {
812 WARN_ON (tf->protocol == ATA_PROT_DMA ||
813 tf->protocol == ATA_PROT_NODATA);
814 ata_exec_command(ap, tf);
815 }
816
817 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
818 {
819 u8 *scsicmd = qc->scsicmd->cmnd;
820 int pio = 1; /* atapi dma off by default */
821
822 /* Whitelist commands that may use DMA. */
823 switch (scsicmd[0]) {
824 case WRITE_12:
825 case WRITE_10:
826 case WRITE_6:
827 case READ_12:
828 case READ_10:
829 case READ_6:
830 case 0xad: /* READ_DVD_STRUCTURE */
831 case 0xbe: /* READ_CD */
832 pio = 0;
833 }
834 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
835 if (scsicmd[0] == WRITE_10) {
836 unsigned int lba;
837 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
838 if (lba >= 0xFFFF4FA2)
839 pio = 1;
840 }
841 return pio;
842 }
843
844 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
845 {
846 /* First generation chips cannot use ATAPI DMA on SATA ports */
847 return 1;
848 }
849
850 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base,
851 void __iomem *scr_addr)
852 {
853 port->cmd_addr = base;
854 port->data_addr = base;
855 port->feature_addr =
856 port->error_addr = base + 0x4;
857 port->nsect_addr = base + 0x8;
858 port->lbal_addr = base + 0xc;
859 port->lbam_addr = base + 0x10;
860 port->lbah_addr = base + 0x14;
861 port->device_addr = base + 0x18;
862 port->command_addr =
863 port->status_addr = base + 0x1c;
864 port->altstatus_addr =
865 port->ctl_addr = base + 0x38;
866 port->scr_addr = scr_addr;
867 }
868
869
870 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
871 {
872 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
873 struct pdc_host_priv *hp = pe->private_data;
874 int hotplug_offset;
875 u32 tmp;
876
877 if (hp->flags & PDC_FLAG_GEN_II)
878 hotplug_offset = PDC2_SATA_PLUG_CSR;
879 else
880 hotplug_offset = PDC_SATA_PLUG_CSR;
881
882 /*
883 * Except for the hotplug stuff, this is voodoo from the
884 * Promise driver. Label this entire section
885 * "TODO: figure out why we do this"
886 */
887
888 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
889 tmp = readl(mmio + PDC_FLASH_CTL);
890 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
891 if (!(hp->flags & PDC_FLAG_GEN_II))
892 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
893 writel(tmp, mmio + PDC_FLASH_CTL);
894
895 /* clear plug/unplug flags for all ports */
896 tmp = readl(mmio + hotplug_offset);
897 writel(tmp | 0xff, mmio + hotplug_offset);
898
899 /* mask plug/unplug ints */
900 tmp = readl(mmio + hotplug_offset);
901 writel(tmp | 0xff0000, mmio + hotplug_offset);
902
903 /* don't initialise TBG or SLEW on 2nd generation chips */
904 if (hp->flags & PDC_FLAG_GEN_II)
905 return;
906
907 /* reduce TBG clock to 133 Mhz. */
908 tmp = readl(mmio + PDC_TBG_MODE);
909 tmp &= ~0x30000; /* clear bit 17, 16*/
910 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
911 writel(tmp, mmio + PDC_TBG_MODE);
912
913 readl(mmio + PDC_TBG_MODE); /* flush */
914 msleep(10);
915
916 /* adjust slew rate control register. */
917 tmp = readl(mmio + PDC_SLEW_CTL);
918 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
919 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
920 writel(tmp, mmio + PDC_SLEW_CTL);
921 }
922
923 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
924 {
925 static int printed_version;
926 struct ata_probe_ent *probe_ent;
927 struct pdc_host_priv *hp;
928 void __iomem *base;
929 unsigned int board_idx = (unsigned int) ent->driver_data;
930 int rc;
931 u8 tmp;
932
933 if (!printed_version++)
934 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
935
936 rc = pcim_enable_device(pdev);
937 if (rc)
938 return rc;
939
940 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
941 if (rc == -EBUSY)
942 pcim_pin_device(pdev);
943 if (rc)
944 return rc;
945
946 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
947 if (rc)
948 return rc;
949 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
950 if (rc)
951 return rc;
952
953 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
954 if (probe_ent == NULL)
955 return -ENOMEM;
956
957 probe_ent->dev = pci_dev_to_dev(pdev);
958 INIT_LIST_HEAD(&probe_ent->node);
959
960 hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL);
961 if (hp == NULL)
962 return -ENOMEM;
963
964 probe_ent->private_data = hp;
965
966 probe_ent->sht = pdc_port_info[board_idx].sht;
967 probe_ent->port_flags = pdc_port_info[board_idx].flags;
968 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
969 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
970 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
971 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
972
973 probe_ent->irq = pdev->irq;
974 probe_ent->irq_flags = IRQF_SHARED;
975 probe_ent->iomap = pcim_iomap_table(pdev);
976
977 base = probe_ent->iomap[PDC_MMIO_BAR];
978
979 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200, base + 0x400);
980 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280, base + 0x500);
981
982 /* notice 4-port boards */
983 switch (board_idx) {
984 case board_40518:
985 hp->flags |= PDC_FLAG_GEN_II;
986 /* Fall through */
987 case board_20319:
988 probe_ent->n_ports = 4;
989 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, base + 0x600);
990 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, base + 0x700);
991 break;
992 case board_2057x:
993 hp->flags |= PDC_FLAG_GEN_II;
994 /* Fall through */
995 case board_2037x:
996 /* TX2plus boards also have a PATA port */
997 tmp = readb(base + PDC_FLASH_CTL+1);
998 if (!(tmp & 0x80)) {
999 probe_ent->n_ports = 3;
1000 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL);
1001 hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
1002 printk(KERN_INFO DRV_NAME " PATA port found\n");
1003 } else
1004 probe_ent->n_ports = 2;
1005 hp->port_flags[0] = ATA_FLAG_SATA;
1006 hp->port_flags[1] = ATA_FLAG_SATA;
1007 break;
1008 case board_20619:
1009 probe_ent->n_ports = 4;
1010 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL);
1011 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, NULL);
1012 break;
1013 default:
1014 BUG();
1015 break;
1016 }
1017
1018 pci_set_master(pdev);
1019
1020 /* initialize adapter */
1021 pdc_host_init(board_idx, probe_ent);
1022
1023 if (!ata_device_add(probe_ent))
1024 return -ENODEV;
1025
1026 devm_kfree(&pdev->dev, probe_ent);
1027 return 0;
1028 }
1029
1030
1031 static int __init pdc_ata_init(void)
1032 {
1033 return pci_register_driver(&pdc_ata_pci_driver);
1034 }
1035
1036
1037 static void __exit pdc_ata_exit(void)
1038 {
1039 pci_unregister_driver(&pdc_ata_pci_driver);
1040 }
1041
1042
1043 MODULE_AUTHOR("Jeff Garzik");
1044 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1045 MODULE_LICENSE("GPL");
1046 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1047 MODULE_VERSION(DRV_VERSION);
1048
1049 module_init(pdc_ata_init);
1050 module_exit(pdc_ata_exit);
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