arch/arm-cortex-m3/mach-stm32/include/stm32_regs.h

   1 #ifndef _STM32_REGS_H_
   2 #define _STM32_REGS_H_
   3
   4 #include <types.h>
   5
   6 #define STM32_FLASH_BASE   0x40022000
   7 #define STM32_RCC_BASE     0x40021000
   8 #define STM32_USART1_BASE  0x40013800
   9 #define STM32_GPIO_BASE(x) (0x40010800+0x400*(x))
  10 #define STM32_EXTI_BASE    0x40010400
  11 #define STM32_AFIO_BASE    0x40010000
  12 #define STM32_PWR_BASE     0x40007000
  13 #define STM32_I2C1_BASE    0x40005400
  14 #define STM32_I2C2_BASE    0x40005800
  15
  16
  17 struct stm32_i2c_regs {
  18         volatile u32 CR1;
  19         volatile u32 CR2;
  20         volatile u32 OAR1;
  21         volatile u32 OAR2;
  22         volatile u32 DR;
  23         volatile u32 SR1;
  24         volatile u32 SR2;
  25         volatile u32 CCR;
  26         volatile u32 TRISE;
  27 };
  28 #define STM32_I2C1 ((struct stm32_i2c_regs*)STM_I2C1_BASE)
  29 #define STM32_I2C2 ((struct stm32_i2c_regs*)STM_I2C2_BASE)
  30
  31 struct stm32_rcc_regs {
  32         volatile u32 CR;
  33         volatile u32 CFGR;
  34         volatile u32 CIR;
  35         volatile u32 APB2RSTR;
  36         volatile u32 APB1RSTR;
  37         volatile u32 APBHENR;
  38         volatile u32 APB2ENR;
  39         volatile u32 APB1ENR;
  40         volatile u32 DBCR;
  41         volatile u32 CSR;
  42 };
  43 #define STM32_RCC ((struct stm32_rcc_regs*)STM32_RCC_BASE)
  44
  45 struct stm32_gpio_regs {
  46         volatile u32 CRL;
  47         volatile u32 CRH;
  48         volatile u32 IDR;
  49         volatile u32 ODR;
  50         volatile u32 BSRR;
  51         volatile u32 BRR;
  52         volatile u32 LCKR;
  53 };
  54 #define STM32_GPIO(x) ((struct stm32_gpio_regs*)STM32_GPIO_BASE(x))
  55
  56 struct stm32_exti_regs {
  57         volatile u32 IMR;
  58         volatile u32 EMR;
  59         volatile u32 RTSR;
  60         volatile u32 FTSR;
  61         volatile u32 SWIER;
  62         volatile u32 PR;
  63 };
  64 #define STM32_EXTI ((struct stm32_exti_regs*)STM32_EXTI_BASE)
  65
  66 struct stm32_afio_regs {
  67         volatile u32 EVCR;
  68         volatile u32 MAPR;
  69         volatile u32 EXTICR1;
  70         volatile u32 EXTICR2;
  71         volatile u32 EXTICR3;
  72         volatile u32 EXTICR4;
  73 };
  74 #define STM32_AFIO ((struct stm32_afio_regs*)STM32_AFIO_BASE)
  75
  76 struct stm32_usart_regs {
  77         volatile u32 SR;
  78         volatile u32 DR;
  79         volatile u32 BRR;
  80         volatile u32 CR1;
  81         volatile u32 CR2;
  82         volatile u32 CR3;
  83         volatile u32 GTPR;
  84 };
  85 #define STM32_USART1 ((struct stm32_usart_regs*)STM32_USART1_BASE)
  86
  87 #define FLASH_ACR *(volatile u32 *)0x40022000
  88
  89 #define APB1_DAC        (1<<29)
  90 #define APB1_PWR        (1<<28)
  91 #define APB1_BKP        (1<<27)
  92 #define APB1_CAN        (1<<25)
  93 #define APB1_USB        (1<<23)
  94 #define APB1_I2C2       (1<<22)
  95 #define APB1_I2C1       (1<<21)
  96 #define APB1_UART5      (1<<20)
  97 #define APB1_UART4      (1<<19)
  98 #define APB1_USART3     (1<<18)
  99 #define APB1_USART2     (1<<17)
 100 #define APB1_SPI3       (1<<15)
 101 #define APB1_SPI2       (1<<14)
 102 #define APB1_WWDG       (1<<11)
 103 #define APB1_TIM7       (1<<5)
 104 #define APB1_TIM6       (1<<4)
 105 #define APB1_TIM5       (1<<3)
 106 #define APB1_TIM4       (1<<2)
 107 #define APB1_TIM3       (1<<1)
 108 #define APB1_TIM2       (1<<0)
 109
 110 #define APB2_ADC3       (1<<15)
 111 #define APB2_USART1     (1<<14)
 112 #define APB2_TIM8       (1<<13)
 113 #define APB2_SPI1       (1<<12)
 114 #define APB2_TIM1       (1<<11)
 115 #define APB2_ADC2       (1<<10)
 116 #define APB2_ADC1       (1<<9)
 117 #define APB2_IOPG       (1<<8)
 118 #define APB2_IOPF       (1<<7)
 119 #define APB2_IOPE       (1<<6)
 120 #define APB2_IOPD       (1<<5)
 121 #define APB2_IOPC       (1<<4)
 122 #define APB2_IOPB       (1<<3)
 123 #define APB2_IOPA       (1<<2)
 124 #define APB2_AFIO       (1<<0)
 125
 126
 127 #define REMAP_USART2    (1<<3)
 128 #define REMAP_USART1    (1<<2)
 129 #define REMAP_I2C1      (1<<1)
 130 #define REMAP_SPI1      (1<<0)
 131
 132 enum STM32_IRQ {
 133         IRQ_WWDG = 0,
 134         IRQ_PVD = 1,
 135         IRQ_TAMPER = 2,
 136         IRQ_RTC = 3,
 137         IRQ_FLASH = 4,
 138         IRQ_RCC = 5,
 139         IRQ_EXTI0 = 6,
 140         IRQ_EXTI1 = 7,
 141         IRQ_EXTI2 = 8,
 142         IRQ_EXTI3 = 9,
 143         IRQ_EXTI4 = 10,
 144         IRQ_DMA1_CH1 = 11,
 145         IRQ_DMA1_CH2 = 12,
 146         IRQ_DMA1_CH3 = 13,
 147         IRQ_DMA1_CH4 = 14,
 148         IRQ_DMA1_CH5 = 15,
 149         IRQ_DMA1_CH6 = 16,
 150         IRQ_DMA1_CH7 = 17,
 151         IRQ_ADC1_2 = 18,
 152         IRQ_CAN1_TX = 19,
 153         IRQ_CAN1_RX0 = 20,
 154         IRQ_CAN1_RX1 = 21,
 155         IRQ_CAN1_SCE = 22,
 156         IRQ_EXTI9_5 = 23,
 157         IRQ_TIM1_BRK = 24,
 158         IRQ_TIM1_UP = 25,
 159         IRQ_TIM1_TRG_COM = 26,
 160         IRQ_TIM1_CC = 27,
 161         IRQ_TIM2 = 28,
 162         IRQ_TIM3 = 29,
 163         IRQ_TIM4 = 30,
 164         IRQ_I2C1_EV = 31,
 165         IRQ_I2C1_ER = 32,
 166         IRQ_I2C2_EV = 33,
 167         IRQ_I2C2_ER = 34,
 168         IRQ_SPI1 = 35,
 169         IRQ_SPI2 = 36,
 170         IRQ_USART1 = 37,
 171         IRQ_USART2 = 38,
 172         IRQ_USART3 = 39,
 173         IRQ_EXTI15_10 = 40,
 174         IRQ_RTC_ALARM = 41,
 175         IRQ_OTG_FS_WKUP = 42,
 176
 177         IRQ_TIM5 = 50,
 178         IRQ_SPI3 = 51,
 179         IRQ_UART4 = 52,
 180         IRQ_UART5 = 53,
 181         IRQ_TIM6 = 54,
 182         IRQ_TIM7 = 55,
 183         IRQ_DMA2_CH1 = 56,
 184         IRQ_DMA2_CH2 = 57,
 185         IRQ_DMA2_CH3 = 58,
 186         IRQ_DMA2_CH4 = 59,
 187         IRQ_DMA2_CH5 = 60,
 188         IRQ_ETH = 61,
 189         IRQ_ETH_WKUP = 62,
 190         IRQ_CAN2_TX = 63,
 191         IRQ_CAN2_RX0 = 64,
 192         IRQ_CAN2_RX1 = 65,
 193         IRQ_CAN2_SCE = 66,
 194         IRQ_OTG_FS = 67,
 195 };
 196
 197 #endif