arch/arm-cortex-m3/mach-lpc13xx/include/lpc13xx_tmr.h

   1 #ifndef _ARCH_TMR_H_
   2 #define _ARCH_TMR_H_
   3
   4 #include <types.h>
   5
   6 struct lpc13xx_tmr {
   7         volatile u32 IR;        /* 0x0 */
   8         volatile u32 TCR;       /* 0x4 */
   9         volatile u32 TC;        /* 0x8 */
  10         volatile u32 PR;        /* 0xc */
  11
  12         volatile u32 PC;        /* 0x10 */
  13         volatile u32 MCR;       /* 0x14 */
  14         union {
  15                 struct {
  16                         volatile u32 MR0;       /* 0x18 */
  17                         volatile u32 MR1;       /* 0x1c */
  18
  19                         volatile u32 MR2;       /* 0x20 */
  20                         volatile u32 MR3;       /* 0x24 */
  21                 };
  22                 volatile u32 MR[4];
  23         };
  24         volatile u32 CCR;       /* 0x28 */
  25         volatile const u32 CR0; /* 0x2c */
  26         u32 _reserved0[3];
  27         volatile u32 EMR;       /* 0x3c */
  28         u32 _reserved1[12];
  29         volatile u32 CTCR;      /* 0x70 */
  30         volatile u32 PWMC;      /* 0x74 */
  31 };
  32
  33 #define TMR16B0_ADDR 0x4000c000
  34 #define TMR16B1_ADDR 0x40010000
  35 #define TMR32B0_ADDR 0x40014000
  36 #define TMR33B1_ADDR 0x40018000
  37
  38 #endif