arch/arm-cortex-m0/mach-lpc11xx/include/lpc11xx_gpio.h

   1 #ifndef _ARCH_GPIO_H_
   2 #define _ARCH_GPIO_H_
   3
   4 #define GPIO_MARK 0x800
   5 #define GPIO_HYST (1<<5)
   6 #define IOCON_REG(x) ((x)/4<<12)
   7 #define IOCON_SET(x) ((x)<<20)
   8
   9 #define GPIO_0_0_RESET          (0x000 | GPIO_MARK | IOCON_REG(0x0c) | IOCON_SET(0xc0))
  10 #define GPIO_0_0                (0x000 | GPIO_MARK | IOCON_REG(0x0c) | IOCON_SET(0xc1|GPIO_HYST))
  11 #define GPIO_0_1                (0x001 | GPIO_MARK | IOCON_REG(0x10) | IOCON_SET(0xc0|GPIO_HYST))
  12 #define GPIO_0_1_CLKOUT         (0x001 | GPIO_MARK | IOCON_REG(0x10) | IOCON_SET(0xc1))
  13 #define GPIO_0_1_CT32B0_MAT2    (0x001 | GPIO_MARK | IOCON_REG(0x10) | IOCON_SET(0xc2))
  14 #define GPIO_0_2                (0x002 | GPIO_MARK | IOCON_REG(0x1c) | IOCON_SET(0xc0|GPIO_HYST))
  15 #define GPIO_0_2_SSEL0          (0x002 | GPIO_MARK | IOCON_REG(0x1c) | IOCON_SET(0xc1))
  16 #define GPIO_0_2_CT16B0_CAP0    (0x002 | GPIO_MARK | IOCON_REG(0x1c) | IOCON_SET(0xc2))
  17 #define GPIO_0_3                (0x003 | GPIO_MARK | IOCON_REG(0x2c) | IOCON_SET(0xc0|GPIO_HYST))
  18 #define GPIO_0_4                (0x004 | GPIO_MARK | IOCON_REG(0x30) | IOCON_SET(0x100)) /* open drain pin */
  19 #define GPIO_0_4_SCL            (0x004 | GPIO_MARK | IOCON_REG(0x30) | IOCON_SET(0x1))
  20 #define GPIO_0_5                (0x005 | GPIO_MARK | IOCON_REG(0x34) | IOCON_SET(0x100)) /* open drain pin */
  21 #define GPIO_0_5_SDA            (0x005 | GPIO_MARK | IOCON_REG(0x34) | IOCON_SET(0x1))
  22 #define GPIO_0_6                (0x006 | GPIO_MARK | IOCON_REG(0x4c) | IOCON_SET(0xc0|GPIO_HYST))
  23 #define GPIO_0_6_SCK0           (0x006 | GPIO_MARK | IOCON_REG(0x4c) | IOCON_SET(0xc2)) /* + SCKLOC setting! */
  24 #define GPIO_0_7                (0x007 | GPIO_MARK | IOCON_REG(0x50) | IOCON_SET(0xc0|GPIO_HYST))
  25 #define GPIO_0_7_CTS            (0x007 | GPIO_MARK | IOCON_REG(0x50) | IOCON_SET(0xc1))
  26 #define GPIO_0_8                (0x008 | GPIO_MARK | IOCON_REG(0x60) | IOCON_SET(0xc0|GPIO_HYST))
  27 #define GPIO_0_8_MISO0          (0x008 | GPIO_MARK | IOCON_REG(0x60) | IOCON_SET(0xc1))
  28 #define GPIO_0_8_CT16B0_MAT0    (0x008 | GPIO_MARK | IOCON_REG(0x60) | IOCON_SET(0xc2))
  29 #define GPIO_0_9                (0x009 | GPIO_MARK | IOCON_REG(0x64) | IOCON_SET(0xc0|GPIO_HYST))
  30 #define GPIO_0_9_MOSI0          (0x009 | GPIO_MARK | IOCON_REG(0x64) | IOCON_SET(0xc1))
  31 #define GPIO_0_9_CT16B0_MAT1    (0x009 | GPIO_MARK | IOCON_REG(0x64) | IOCON_SET(0xc2))
  32 #define GPIO_0_9_SWO            (0x009 | GPIO_MARK | IOCON_REG(0x64) | IOCON_SET(0xc3))
  33 #define GPIO_0_10_SWCLK         (0x00a | GPIO_MARK | IOCON_REG(0x68) | IOCON_SET(0xc0))
  34 #define GPIO_0_10               (0x00a | GPIO_MARK | IOCON_REG(0x68) | IOCON_SET(0xc1|GPIO_HYST))
  35 #define GPIO_0_10_SCK0          (0x00a | GPIO_MARK | IOCON_REG(0x68) | IOCON_SET(0xc2)) /* + SCKLOC setting! */
  36 #define GPIO_0_10_CT16B0_MAT2   (0x00a | GPIO_MARK | IOCON_REG(0x68) | IOCON_SET(0xc3))
  37 #define GPIO_0_11               (0x00b | GPIO_MARK | IOCON_REG(0x74) | IOCON_SET(0xc1|GPIO_HYST))
  38 #define GPIO_0_11_AD0           (0x00b | GPIO_MARK | IOCON_REG(0x74) | IOCON_SET(0x42))
  39 #define GPIO_0_11_CT32B0_MAT3   (0x00b | GPIO_MARK | IOCON_REG(0x74) | IOCON_SET(0xc3))
  40
  41 #define GPIO_1_0                (0x100 | GPIO_MARK | IOCON_REG(0x78) | IOCON_SET(0xc1|GPIO_HYST))
  42 #define GPIO_1_0_AD1            (0x100 | GPIO_MARK | IOCON_REG(0x78) | IOCON_SET(0x42))
  43 #define GPIO_1_0_CT32B1_CAP0    (0x100 | GPIO_MARK | IOCON_REG(0x78) | IOCON_SET(0xc3))
  44 #define GPIO_1_1                (0x101 | GPIO_MARK | IOCON_REG(0x7c) | IOCON_SET(0xc1|GPIO_HYST))
  45 #define GPIO_1_1_AD2            (0x101 | GPIO_MARK | IOCON_REG(0x7c) | IOCON_SET(0x42))
  46 #define GPIO_1_1_CT32B1_MAT0    (0x101 | GPIO_MARK | IOCON_REG(0x7c) | IOCON_SET(0xc3))
  47 #define GPIO_1_2                (0x102 | GPIO_MARK | IOCON_REG(0x80) | IOCON_SET(0xc1|GPIO_HYST))
  48 #define GPIO_1_2_AD3            (0x102 | GPIO_MARK | IOCON_REG(0x80) | IOCON_SET(0x42))
  49 #define GPIO_1_2_CT32B1_MAT1    (0x102 | GPIO_MARK | IOCON_REG(0x80) | IOCON_SET(0xc3))
  50 #define GPIO_1_3_SWDIO          (0x103 | GPIO_MARK | IOCON_REG(0x90) | IOCON_SET(0xc0))
  51 #define GPIO_1_3                (0x103 | GPIO_MARK | IOCON_REG(0x90) | IOCON_SET(0xc1|GPIO_HYST))
  52 #define GPIO_1_3_AD4            (0x103 | GPIO_MARK | IOCON_REG(0x90) | IOCON_SET(0x42))
  53 #define GPIO_1_3_CT32B1_MAT2    (0x103 | GPIO_MARK | IOCON_REG(0x90) | IOCON_SET(0xc3))
  54 #define GPIO_1_4                (0x104 | GPIO_MARK | IOCON_REG(0x94) | IOCON_SET(0xc0|GPIO_HYST))
  55 #define GPIO_1_4_AD5            (0x104 | GPIO_MARK | IOCON_REG(0x94) | IOCON_SET(0x41))
  56 #define GPIO_1_4_CT32B1_MAT3    (0x104 | GPIO_MARK | IOCON_REG(0x94) | IOCON_SET(0xc2))
  57 #define GPIO_1_5                (0x105 | GPIO_MARK | IOCON_REG(0xa0) | IOCON_SET(0xc0|GPIO_HYST))
  58 #define GPIO_1_5_RTS            (0x105 | GPIO_MARK | IOCON_REG(0xa0) | IOCON_SET(0xc1))
  59 #define GPIO_1_5_CT32B0_CAP0    (0x105 | GPIO_MARK | IOCON_REG(0xa0) | IOCON_SET(0xc2))
  60 #define GPIO_1_6                (0x106 | GPIO_MARK | IOCON_REG(0xa4) | IOCON_SET(0xc0|GPIO_HYST))
  61 #define GPIO_1_6_UART_RXD       (0x106 | GPIO_MARK | IOCON_REG(0xa4) | IOCON_SET(0xc1))
  62 #define GPIO_1_6_CT32B0_MAT0    (0x106 | GPIO_MARK | IOCON_REG(0xa4) | IOCON_SET(0xc2))
  63 #define GPIO_1_7                (0x107 | GPIO_MARK | IOCON_REG(0xa8) | IOCON_SET(0xc0|GPIO_HYST))
  64 #define GPIO_1_7_UART_TXD       (0x107 | GPIO_MARK | IOCON_REG(0xa8) | IOCON_SET(0xc1))
  65 #define GPIO_1_7_CT32B0_MAT1    (0x107 | GPIO_MARK | IOCON_REG(0xa8) | IOCON_SET(0xc2))
  66 #define GPIO_1_8                (0x108 | GPIO_MARK | IOCON_REG(0x14) | IOCON_SET(0xc0|GPIO_HYST))
  67 #define GPIO_1_8_CT16B1_CAP0    (0x108 | GPIO_MARK | IOCON_REG(0x14) | IOCON_SET(0xc1))
  68 #define GPIO_1_9                (0x109 | GPIO_MARK | IOCON_REG(0x38) | IOCON_SET(0xc0|GPIO_HYST))
  69 #define GPIO_1_9_CT16B1_MAT0    (0x109 | GPIO_MARK | IOCON_REG(0x38) | IOCON_SET(0xc1))
  70 #define GPIO_1_10               (0x10a | GPIO_MARK | IOCON_REG(0x6c) | IOCON_SET(0xc0|GPIO_HYST))
  71 #define GPIO_1_10_AD6           (0x10a | GPIO_MARK | IOCON_REG(0x6c) | IOCON_SET(0x41))
  72 #define GPIO_1_10_CT16B1_MAT1   (0x10a | GPIO_MARK | IOCON_REG(0x6c) | IOCON_SET(0xc2))
  73 #define GPIO_1_11               (0x10b | GPIO_MARK | IOCON_REG(0x98) | IOCON_SET(0xc0|GPIO_HYST))
  74 #define GPIO_1_11_AD7           (0x10b | GPIO_MARK | IOCON_REG(0x98) | IOCON_SET(0x41))
  75
  76 #define GPIO_2_0                (0x200 | GPIO_MARK | IOCON_REG(0x08) | IOCON_SET(0xc0|GPIO_HYST))
  77 #define GPIO_2_0_DTR            (0x200 | GPIO_MARK | IOCON_REG(0x08) | IOCON_SET(0xc1)) /* no DTRSEL, both are driven */
  78 #define GPIO_2_0_SSEL1          (0x200 | GPIO_MARK | IOCON_REG(0x08) | IOCON_SET(0xc2))
  79 #define GPIO_2_1                (0x201 | GPIO_MARK | IOCON_REG(0x28) | IOCON_SET(0xc0|GPIO_HYST))
  80 #define GPIO_2_1_DSR            (0x201 | GPIO_MARK | IOCON_REG(0x28) | IOCON_SET(0xc1)) /* + DSRLOC */
  81 #define GPIO_2_1_SCK1           (0x201 | GPIO_MARK | IOCON_REG(0x28) | IOCON_SET(0xc2))
  82 #define GPIO_2_2                (0x202 | GPIO_MARK | IOCON_REG(0x5c) | IOCON_SET(0xc0|GPIO_HYST))
  83 #define GPIO_2_2_DCD            (0x202 | GPIO_MARK | IOCON_REG(0x5c) | IOCON_SET(0xc1)) /* + DCD_LOC */
  84 #define GPIO_2_2_MISO1          (0x202 | GPIO_MARK | IOCON_REG(0x5c) | IOCON_SET(0xc2))
  85 #define GPIO_2_3                (0x203 | GPIO_MARK | IOCON_REG(0x8c) | IOCON_SET(0xc0|GPIO_HYST))
  86 #define GPIO_2_3_RI             (0x203 | GPIO_MARK | IOCON_REG(0x8c) | IOCON_SET(0xc1)) /* + RILOC */
  87 #define GPIO_2_3_MOSI1          (0x203 | GPIO_MARK | IOCON_REG(0x8c) | IOCON_SET(0xc2))
  88 #define GPIO_2_4                (0x204 | GPIO_MARK | IOCON_REG(0x40) | IOCON_SET(0xc0|GPIO_HYST))
  89 #define GPIO_2_5                (0x205 | GPIO_MARK | IOCON_REG(0x44) | IOCON_SET(0xc0|GPIO_HYST))
  90 #define GPIO_2_6                (0x206 | GPIO_MARK | IOCON_REG(0x00) | IOCON_SET(0xc0|GPIO_HYST))
  91 #define GPIO_2_7                (0x207 | GPIO_MARK | IOCON_REG(0x20) | IOCON_SET(0xc0|GPIO_HYST))
  92 #define GPIO_2_8                (0x208 | GPIO_MARK | IOCON_REG(0x24) | IOCON_SET(0xc0|GPIO_HYST))
  93 #define GPIO_2_9                (0x209 | GPIO_MARK | IOCON_REG(0x54) | IOCON_SET(0xc0|GPIO_HYST))
  94 #define GPIO_2_10               (0x20a | GPIO_MARK | IOCON_REG(0x58) | IOCON_SET(0xc0|GPIO_HYST))
  95 #define GPIO_2_11               (0x20b | GPIO_MARK | IOCON_REG(0x70) | IOCON_SET(0xc0|GPIO_HYST))
  96 #define GPIO_2_11_SCK           (0x20b | GPIO_MARK | IOCON_REG(0x70) | IOCON_SET(0xc1)) /* + SCKLOC setting! */
  97
  98 #define GPIO_3_0                (0x300 | GPIO_MARK | IOCON_REG(0x84) | IOCON_SET(0xc0|GPIO_HYST))
  99 #define GPIO_3_0_DTR            (0x300 | GPIO_MARK | IOCON_REG(0x84) | IOCON_SET(0xc1)) /* no DTRSEL, both are driven */
 100 #define GPIO_3_1                (0x301 | GPIO_MARK | IOCON_REG(0x88) | IOCON_SET(0xc0|GPIO_HYST))
 101 #define GPIO_3_1_DSR            (0x301 | GPIO_MARK | IOCON_REG(0x88) | IOCON_SET(0xc1)) /* + DSRLOC */
 102 #define GPIO_3_2                (0x302 | GPIO_MARK | IOCON_REG(0x9c) | IOCON_SET(0xc0|GPIO_HYST))
 103 #define GPIO_3_2_DCD            (0x302 | GPIO_MARK | IOCON_REG(0x9c) | IOCON_SET(0xc1)) /* + DCDLOC */
 104 #define GPIO_3_3                (0x303 | GPIO_MARK | IOCON_REG(0xac) | IOCON_SET(0xc0|GPIO_HYST))
 105 #define GPIO_3_3_RI             (0x303 | GPIO_MARK | IOCON_REG(0xac) | IOCON_SET(0xc1)) /* + RILOC */
 106 /* only on lpc131x */
 107 #define GPIO_3_4                (0x304 | GPIO_MARK | IOCON_REG(0x3c) | IOCON_SET(0xc0|GPIO_HYST))
 108 #define GPIO_3_5                (0x305 | GPIO_MARK | IOCON_REG(0x48) | IOCON_SET(0xc0|GPIO_HYST))
 109
 110 #endif