opcodes: blackfin: fix decoding of dsp mult insns
commit19c72da9f10f30d8387dfbcf099e052a23130f0d
authorMike Frysinger <vapier@gentoo.org>
Sun, 13 Feb 2011 18:54:49 +0000 (13 18:54 +0000)
committerMike Frysinger <vapier@gentoo.org>
Sun, 13 Feb 2011 18:54:49 +0000 (13 18:54 +0000)
tree6bb6b0435ad438d574e28f95cf6f2367b7f55a60
parent468f625a82981170733a2d81278dd0b5545f495a
opcodes: blackfin: fix decoding of dsp mult insns

When assigning to a register half, the mac0 part of the mult insn
was not decoding properly.  It would always show a full dreg instead
of the dreg low half.

Once we fix the disassembler, we have to update a few of the gas
tests as their previous expected output was incorrect.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
gas/testsuite/ChangeLog
gas/testsuite/gas/bfin/arithmetic.d
gas/testsuite/gas/bfin/parallel.d
gas/testsuite/gas/bfin/parallel3.d
gas/testsuite/gas/bfin/vector.d
gas/testsuite/gas/bfin/vector2.d
opcodes/ChangeLog
opcodes/bfin-dis.c