From 19c72da9f10f30d8387dfbcf099e052a23130f0d Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sun, 13 Feb 2011 18:54:49 +0000 Subject: [PATCH] opcodes: blackfin: fix decoding of dsp mult insns When assigning to a register half, the mac0 part of the mult insn was not decoding properly. It would always show a full dreg instead of the dreg low half. Once we fix the disassembler, we have to update a few of the gas tests as their previous expected output was incorrect. Signed-off-by: Mike Frysinger --- gas/testsuite/ChangeLog | 7 ++++++- gas/testsuite/gas/bfin/arithmetic.d | 6 +++--- gas/testsuite/gas/bfin/parallel.d | 6 +++--- gas/testsuite/gas/bfin/parallel3.d | 12 ++++++------ gas/testsuite/gas/bfin/vector.d | 12 ++++++------ gas/testsuite/gas/bfin/vector2.d | 8 ++++---- opcodes/ChangeLog | 5 +++++ opcodes/bfin-dis.c | 4 ++-- 8 files changed, 35 insertions(+), 25 deletions(-) diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 946dc1b55..fb8816d1e 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,4 +1,9 @@ -2011-02-12 Mike Frysinger +2011-02-13 Mike Frysinger + + * gas/bfin/arithmetic.d, gas/bfin/parallel.d, gas/bfin/parallel3.d, + gas/bfin/vector.d, gas/bfin/vector2.d: Add ".L" to dsp mult insns. + +2011-02-13 Mike Frysinger * gas/bfin/video.d, gas/bfin/video.s, gas/bfin/video2.d, gas/bfin/video2.s: Remove BYTEOP2M insns. diff --git a/gas/testsuite/gas/bfin/arithmetic.d b/gas/testsuite/gas/bfin/arithmetic.d index 88d6dbe2e..0f145e010 100644 --- a/gas/testsuite/gas/bfin/arithmetic.d +++ b/gas/testsuite/gas/bfin/arithmetic.d @@ -82,9 +82,9 @@ Disassembly of section .text: a8: 2b c4 [0-3][[:xdigit:]] 40 R0.H = \(A0 \+= A1\); 000000ac : - ac: 00 c2 0a 24 R0 = R1.H \* R2.L; - b0: 20 c2 68 26 R1 = R5.H \* R0.H \(S2RND\); - b4: 80 c2 db 23 R7 = R3.L \* R3.H \(FU\); + ac: 00 c2 0a 24 R0.L = R1.H \* R2.L; + b0: 20 c2 68 26 R1.L = R5.H \* R0.H \(S2RND\); + b4: 80 c2 db 23 R7.L = R3.L \* R3.H \(FU\); b8: 28 c3 15 27 R4 = R2.H \* R5.H \(ISS2\); bc: 08 c3 0b 20 R0 = R1.L \* R3.L \(IS\); c0: 08 c2 a8 25 R6 = R5.H \* R0.L; diff --git a/gas/testsuite/gas/bfin/parallel.d b/gas/testsuite/gas/bfin/parallel.d index 06b8a6e07..db4c8fe99 100644 --- a/gas/testsuite/gas/bfin/parallel.d +++ b/gas/testsuite/gas/bfin/parallel.d @@ -89,11 +89,11 @@ Disassembly of section .text: 144: 3b 9b 0f 9c 148: 2b cc 00 40 R0.H = \(A0 \+= A1\) \|\| B\[P0\] = R3 \|\| R7 = \[I0\+\+\]; 14c: 03 9b 07 9c - 150: 00 ca 0a 24 R0 = R1.H \* R2.L \|\| B\[P1\] = R3 \|\| R1 = \[I0\+\+\]; + 150: 00 ca 0a 24 R0.L = R1.H \* R2.L \|\| B\[P1\] = R3 \|\| R1 = \[I0\+\+\]; 154: 0b 9b 01 9c - 158: 20 ca 68 26 R1 = R5.H \* R0.H \(S2RND\) \|\| B\[P2\] = R3 \|\| R2 = \[I0\+\+\]; + 158: 20 ca 68 26 R1.L = R5.H \* R0.H \(S2RND\) \|\| B\[P2\] = R3 \|\| R2 = \[I0\+\+\]; 15c: 13 9b 02 9c - 160: 80 ca db 23 R7 = R3.L \* R3.H \(FU\) \|\| B\[P3\] = R3 \|\| R3 = \[I0\+\+\]; + 160: 80 ca db 23 R7.L = R3.L \* R3.H \(FU\) \|\| B\[P3\] = R3 \|\| R3 = \[I0\+\+\]; 164: 1b 9b 03 9c 168: 28 cb 15 27 R4 = R2.H \* R5.H \(ISS2\) \|\| B\[P4\] = R3 \|\| R0 = \[I0\+\+\]; 16c: 23 9b 00 9c diff --git a/gas/testsuite/gas/bfin/parallel3.d b/gas/testsuite/gas/bfin/parallel3.d index 0568f9b16..9f23c594a 100644 --- a/gas/testsuite/gas/bfin/parallel3.d +++ b/gas/testsuite/gas/bfin/parallel3.d @@ -73,21 +73,21 @@ Disassembly of section .text: 104: 68 92 00 00 108: 06 cc 17 40 R0 = MIN \(R2, R7\) \(V\) \|\| \[P5--\] = P0 \|\| NOP; 10c: e8 92 00 00 - 110: 04 ca be 66 R2.H = R7.L \* R6.H, R2 = R7.H \* R6.H \|\| \[P5 \+ 0x8\] = P0 \|\| NOP; + 110: 04 ca be 66 R2.H = R7.L \* R6.H, R2.L = R7.H \* R6.H \|\| \[P5 \+ 0x8\] = P0 \|\| NOP; 114: a8 bc 00 00 - 118: 04 ca 08 e1 R4.H = R1.H \* R0.H, R4 = R1.L \* R0.L \|\| \[P5 \+ 0x4\] = P0 \|\| NOP; + 118: 04 ca 08 e1 R4.H = R1.H \* R0.H, R4.L = R1.L \* R0.L \|\| \[P5 \+ 0x4\] = P0 \|\| NOP; 11c: 68 bc 00 00 - 120: 04 ca 1a a0 R0.H = R3.H \* R2.L, R0 = R3.L \* R2.L \|\| \[P5\] = P0 \|\| NOP; + 120: 04 ca 1a a0 R0.H = R3.H \* R2.L, R0.L = R3.L \* R2.L \|\| \[P5\] = P0 \|\| NOP; 124: 68 93 00 00 - 128: 94 ca 5a e1 R5.H = R3.H \* R2.H \(M\), R5 = R3.L \* R2.L \(FU\) \|\| \[SP\] = P0 \|\| NOP; + 128: 94 ca 5a e1 R5.H = R3.H \* R2.H \(M\), R5.L = R3.L \* R2.L \(FU\) \|\| \[SP\] = P0 \|\| NOP; 12c: 70 93 00 00 130: 2c ca 27 e0 R1 = R4.H \* R7.H, R0 = R4.L \* R7.L \(S2RND\) \|\| \[SP\+\+\] = P0 \|\| NOP; 134: 70 92 00 00 138: 0c ca 95 27 R7 = R2.L \* R5.L, R6 = R2.H \* R5.H \|\| \[SP--\] = P0 \|\| NOP; 13c: f0 92 00 00 - 140: 24 cb 3e e0 R0.H = R7.H \* R6.H, R0 = R7.L \* R6.L \(ISS2\) \|\| \[SP \+ 0x3c\] = P0 \|\| NOP; + 140: 24 cb 3e e0 R0.H = R7.H \* R6.H, R0.L = R7.L \* R6.L \(ISS2\) \|\| \[SP \+ 0x3c\] = P0 \|\| NOP; 144: f0 bf 00 00 - 148: 04 cb c1 e0 R3.H = R0.H \* R1.H, R3 = R0.L \* R1.L \(IS\) \|\| \[FP\] = P0 \|\| NOP; + 148: 04 cb c1 e0 R3.H = R0.H \* R1.H, R3.L = R0.L \* R1.L \(IS\) \|\| \[FP\] = P0 \|\| NOP; 14c: 78 93 00 00 150: 00 c8 13 46 A1 = R2.L \* R3.H, A0 = R2.H \* R3.H \|\| \[FP\+\+\] = P0 \|\| NOP; 154: 78 92 00 00 diff --git a/gas/testsuite/gas/bfin/vector.d b/gas/testsuite/gas/bfin/vector.d index 26cdc1754..8caa68f1b 100644 --- a/gas/testsuite/gas/bfin/vector.d +++ b/gas/testsuite/gas/bfin/vector.d @@ -55,14 +55,14 @@ Disassembly of section .text: 84: 06 c4 17 40 R0 = MIN \(R2, R7\) \(V\); 00000088 : - 88: 04 c2 be 66 R2.H = R7.L \* R6.H, R2 = R7.H \* R6.H; - 8c: 04 c2 08 e1 R4.H = R1.H \* R0.H, R4 = R1.L \* R0.L; - 90: 04 c2 1a a0 R0.H = R3.H \* R2.L, R0 = R3.L \* R2.L; - 94: 94 c2 5a e1 R5.H = R3.H \* R2.H \(M\), R5 = R3.L \* R2.L \(FU\); + 88: 04 c2 be 66 R2.H = R7.L \* R6.H, R2.L = R7.H \* R6.H; + 8c: 04 c2 08 e1 R4.H = R1.H \* R0.H, R4.L = R1.L \* R0.L; + 90: 04 c2 1a a0 R0.H = R3.H \* R2.L, R0.L = R3.L \* R2.L; + 94: 94 c2 5a e1 R5.H = R3.H \* R2.H \(M\), R5.L = R3.L \* R2.L \(FU\); 98: 2c c2 27 e0 R1 = R4.H \* R7.H, R0 = R4.L \* R7.L \(S2RND\); 9c: 0c c2 95 27 R7 = R2.L \* R5.L, R6 = R2.H \* R5.H; - a0: 24 c3 3e e0 R0.H = R7.H \* R6.H, R0 = R7.L \* R6.L \(ISS2\); - a4: 04 c3 c1 e0 R3.H = R0.H \* R1.H, R3 = R0.L \* R1.L \(IS\); + a0: 24 c3 3e e0 R0.H = R7.H \* R6.H, R0.L = R7.L \* R6.L \(ISS2\); + a4: 04 c3 c1 e0 R3.H = R0.H \* R1.H, R3.L = R0.L \* R1.L \(IS\); a8: 00 c0 13 46 A1 = R2.L \* R3.H, A0 = R2.H \* R3.H; ac: 01 c0 08 c0 A1 \+= R1.H \* R0.H, A0 = R1.L \* R0.L; b0: 60 c0 2f c8 A1 = R5.H \* R7.H, A0 \+= R5.L \* R7.L \(W32\); diff --git a/gas/testsuite/gas/bfin/vector2.d b/gas/testsuite/gas/bfin/vector2.d index a6b19351d..33c57b463 100644 --- a/gas/testsuite/gas/bfin/vector2.d +++ b/gas/testsuite/gas/bfin/vector2.d @@ -411,9 +411,9 @@ Disassembly of section .text: 64c: 06 c4 01 4e R7 = MIN \(R0, R1\) \(V\); 650: 06 c4 1c 44 R2 = MIN \(R3, R4\) \(V\); 654: 06 c4 37 4a R5 = MIN \(R6, R7\) \(V\); - 658: 04 c2 be 66 R2.H = R7.L \* R6.H, R2 = R7.H \* R6.H; - 65c: 04 c2 08 e1 R4.H = R1.H \* R0.H, R4 = R1.L \* R0.L; - 660: 14 c2 1a a0 R0.H = R3.H \* R2.L \(M\), R0 = R3.L \* R2.L; + 658: 04 c2 be 66 R2.H = R7.L \* R6.H, R2.L = R7.H \* R6.H; + 65c: 04 c2 08 e1 R4.H = R1.H \* R0.H, R4.L = R1.L \* R0.L; + 660: 14 c2 1a a0 R0.H = R3.H \* R2.L \(M\), R0.L = R3.L \* R2.L; 664: 00 c0 13 46 A1 = R2.L \* R3.H, A0 = R2.H \* R3.H; 668: 01 c0 08 c0 A1 \+= R1.H \* R0.H, A0 = R1.L \* R0.L; 66c: 01 c0 1b 96 A1 \+= R3.H \* R3.L, A0 -= R3.H \* R3.H; @@ -469,7 +469,7 @@ Disassembly of section .text: 734: 00 9e 32 9c 738: 8b c8 9a 2f R6 = \(A0 \+= R3.H \* R2.H\) \(FU\) \|\| I2 -= M0 \|\| NOP; 73c: 72 9e 00 00 - 740: 14 c2 1a a0 R0.H = R3.H \* R2.L \(M\), R0 = R3.L \* R2.L; + 740: 14 c2 1a a0 R0.H = R3.H \* R2.L \(M\), R0.L = R3.L \* R2.L; 744: 1c c2 b8 60 R3 = R7.L \* R0.H \(M\), R2 = R7.L \* R0.L; 748: 1c c0 b8 60 R3 = \(A1 = R7.L \* R0.H\) \(M\), R2 = \(A0 = R7.L \* R0.L\); 74c: 44 c0 23 04 R0.H = \(A1 = R4.L \* R3.L\), A0 = R4.H \* R3.L \(T\); diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index aaafac47f..f0671504e 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2011-02-13 Mike Frysinger + * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output + dregs only when P is set, and dregs_lo otherwise. + +2011-02-13 Mike Frysinger + * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code. 2011-02-12 Mike Frysinger diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c index e6901dcaf..e7646c9ea 100644 --- a/opcodes/bfin-dis.c +++ b/opcodes/bfin-dis.c @@ -3084,7 +3084,7 @@ decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf) if (w1) { - OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst)); + OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst)); OUTS (outf, " = "); decode_multfunc (h01, h11, src0, src1, outf); @@ -3099,7 +3099,7 @@ decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf) if (w0) { - OUTS (outf, dregs (dst)); + OUTS (outf, P ? dregs (dst) : dregs_lo (dst)); OUTS (outf, " = "); decode_multfunc (h00, h10, src0, src1, outf); } -- 2.11.4.GIT