opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
   3    2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
   4    Written by Ian Lance Taylor, Cygnus Support
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING.  If not, write to the
  20    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include <stdio.h>
  24 #include "sysdep.h"
  25 #include "opcode/ppc.h"
  26 #include "opintl.h"
  27
  28 /* This file holds the PowerPC opcode table.  The opcode table
  29    includes almost all of the extended instruction mnemonics.  This
  30    permits the disassembler to use them, and simplifies the assembler
  31    logic, at the cost of increasing the table size.  The table is
  32    strictly constant data, so the compiler should be able to put it in
  33    the .text section.
  34
  35    This file also holds the operand table.  All knowledge about
  36    inserting operands into instructions and vice-versa is kept in this
  37    file.  */
  38 \f
  39 /* Local insertion and extraction functions.  */
  40
  41 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
  42 static long extract_bat (unsigned long, ppc_cpu_t, int *);
  43 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
  44 static long extract_bba (unsigned long, ppc_cpu_t, int *);
  45 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
  46 static long extract_bdm (unsigned long, ppc_cpu_t, int *);
  47 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
  48 static long extract_bdp (unsigned long, ppc_cpu_t, int *);
  49 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
  50 static long extract_bo (unsigned long, ppc_cpu_t, int *);
  51 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
  52 static long extract_boe (unsigned long, ppc_cpu_t, int *);
  53 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
  54 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
  55 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
  56 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
  57 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
  58 static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
  59 static long extract_nb (unsigned long, ppc_cpu_t, int *);
  60 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
  61 static long extract_nsi (unsigned long, ppc_cpu_t, int *);
  62 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
  63 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
  64 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
  65 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
  66 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
  67 static long extract_rbs (unsigned long, ppc_cpu_t, int *);
  68 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
  69 static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
  70 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
  71 static long extract_spr (unsigned long, ppc_cpu_t, int *);
  72 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
  73 static long extract_sprg (unsigned long, ppc_cpu_t, int *);
  74 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
  75 static long extract_tbr (unsigned long, ppc_cpu_t, int *);
  76 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
  77 static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
  78 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
  79 static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
  80 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
  81 static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
  82 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
  83 static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
  84 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
  85 static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
  86 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
  87 static long extract_dm (unsigned long, ppc_cpu_t, int *);
  88 \f
  89 /* The operands table.
  90
  91    The fields are bitm, shift, insert, extract, flags.
  92
  93    We used to put parens around the various additions, like the one
  94    for BA just below.  However, that caused trouble with feeble
  95    compilers with a limit on depth of a parenthesized expression, like
  96    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
  97    omit the parens, since the macros are never used in a context where
  98    the addition will be ambiguous.  */
  99
 100 const struct powerpc_operand powerpc_operands[] =
 101 {
 102   /* The zero index is used to indicate the end of the list of
 103      operands.  */
 104 #define UNUSED 0
 105   { 0, 0, NULL, NULL, 0 },
 106
 107   /* The BA field in an XL form instruction.  */
 108 #define BA UNUSED + 1
 109   /* The BI field in a B form or XL form instruction.  */
 110 #define BI BA
 111 #define BI_MASK (0x1f << 16)
 112   { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
 113
 114   /* The BA field in an XL form instruction when it must be the same
 115      as the BT field in the same instruction.  */
 116 #define BAT BA + 1
 117   { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 118
 119   /* The BB field in an XL form instruction.  */
 120 #define BB BAT + 1
 121 #define BB_MASK (0x1f << 11)
 122   { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
 123
 124   /* The BB field in an XL form instruction when it must be the same
 125      as the BA field in the same instruction.  */
 126 #define BBA BB + 1
 127   { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 128
 129   /* The BD field in a B form instruction.  The lower two bits are
 130      forced to zero.  */
 131 #define BD BBA + 1
 132   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 133
 134   /* The BD field in a B form instruction when absolute addressing is
 135      used.  */
 136 #define BDA BD + 1
 137   { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 138
 139   /* The BD field in a B form instruction when the - modifier is used.
 140      This sets the y bit of the BO field appropriately.  */
 141 #define BDM BDA + 1
 142   { 0xfffc, 0, insert_bdm, extract_bdm,
 143       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 144
 145   /* The BD field in a B form instruction when the - modifier is used
 146      and absolute address is used.  */
 147 #define BDMA BDM + 1
 148   { 0xfffc, 0, insert_bdm, extract_bdm,
 149       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 150
 151   /* The BD field in a B form instruction when the + modifier is used.
 152      This sets the y bit of the BO field appropriately.  */
 153 #define BDP BDMA + 1
 154   { 0xfffc, 0, insert_bdp, extract_bdp,
 155       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 156
 157   /* The BD field in a B form instruction when the + modifier is used
 158      and absolute addressing is used.  */
 159 #define BDPA BDP + 1
 160   { 0xfffc, 0, insert_bdp, extract_bdp,
 161       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 162
 163   /* The BF field in an X or XL form instruction.  */
 164 #define BF BDPA + 1
 165   /* The CRFD field in an X form instruction.  */
 166 #define CRFD BF
 167   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
 168
 169   /* The BF field in an X or XL form instruction.  */
 170 #define BFF BF + 1
 171   { 0x7, 23, NULL, NULL, 0 },
 172
 173   /* An optional BF field.  This is used for comparison instructions,
 174      in which an omitted BF field is taken as zero.  */
 175 #define OBF BFF + 1
 176   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 177
 178   /* The BFA field in an X or XL form instruction.  */
 179 #define BFA OBF + 1
 180   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
 181
 182   /* The BO field in a B form instruction.  Certain values are
 183      illegal.  */
 184 #define BO BFA + 1
 185 #define BO_MASK (0x1f << 21)
 186   { 0x1f, 21, insert_bo, extract_bo, 0 },
 187
 188   /* The BO field in a B form instruction when the + or - modifier is
 189      used.  This is like the BO field, but it must be even.  */
 190 #define BOE BO + 1
 191   { 0x1e, 21, insert_boe, extract_boe, 0 },
 192
 193 #define BH BOE + 1
 194   { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 195
 196   /* The BT field in an X or XL form instruction.  */
 197 #define BT BH + 1
 198   { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
 199
 200   /* The condition register number portion of the BI field in a B form
 201      or XL form instruction.  This is used for the extended
 202      conditional branch mnemonics, which set the lower two bits of the
 203      BI field.  This field is optional.  */
 204 #define CR BT + 1
 205   { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 206
 207   /* The CRB field in an X form instruction.  */
 208 #define CRB CR + 1
 209   /* The MB field in an M form instruction.  */
 210 #define MB CRB
 211 #define MB_MASK (0x1f << 6)
 212   { 0x1f, 6, NULL, NULL, 0 },
 213
 214   /* The CRFS field in an X form instruction.  */
 215 #define CRFS CRB + 1
 216   { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
 217
 218   /* The CT field in an X form instruction.  */
 219 #define CT CRFS + 1
 220   /* The MO field in an mbar instruction.  */
 221 #define MO CT
 222   { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 223
 224   /* The D field in a D form instruction.  This is a displacement off
 225      a register, and implies that the next operand is a register in
 226      parentheses.  */
 227 #define D CT + 1
 228   { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 229
 230   /* The DQ field in a DQ form instruction.  This is like D, but the
 231      lower four bits are forced to zero. */
 232 #define DQ D + 1
 233   { 0xfff0, 0, NULL, NULL,
 234     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 235
 236   /* The DS field in a DS form instruction.  This is like D, but the
 237      lower two bits are forced to zero.  */
 238 #define DS DQ + 1
 239   { 0xfffc, 0, NULL, NULL,
 240     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 241
 242   /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
 243 #define DUIS DS + 1
 244   { 0x3ff, 11, NULL, NULL, 0 },
 245
 246   /* The E field in a wrteei instruction.  */
 247   /* And the W bit in the pair singles instructions.  */
 248 #define E DUIS + 1
 249 #define PSW E
 250   { 0x1, 15, NULL, NULL, 0 },
 251
 252   /* The FL1 field in a POWER SC form instruction.  */
 253 #define FL1 E + 1
 254   /* The U field in an X form instruction.  */
 255 #define U FL1
 256   { 0xf, 12, NULL, NULL, 0 },
 257
 258   /* The FL2 field in a POWER SC form instruction.  */
 259 #define FL2 FL1 + 1
 260   { 0x7, 2, NULL, NULL, 0 },
 261
 262   /* The FLM field in an XFL form instruction.  */
 263 #define FLM FL2 + 1
 264   { 0xff, 17, NULL, NULL, 0 },
 265
 266   /* The FRA field in an X or A form instruction.  */
 267 #define FRA FLM + 1
 268 #define FRA_MASK (0x1f << 16)
 269   { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
 270
 271   /* The FRB field in an X or A form instruction.  */
 272 #define FRB FRA + 1
 273 #define FRB_MASK (0x1f << 11)
 274   { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
 275
 276   /* The FRC field in an A form instruction.  */
 277 #define FRC FRB + 1
 278 #define FRC_MASK (0x1f << 6)
 279   { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
 280
 281   /* The FRS field in an X form instruction or the FRT field in a D, X
 282      or A form instruction.  */
 283 #define FRS FRC + 1
 284 #define FRT FRS
 285   { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
 286
 287   /* The FXM field in an XFX instruction.  */
 288 #define FXM FRS + 1
 289   { 0xff, 12, insert_fxm, extract_fxm, 0 },
 290
 291   /* Power4 version for mfcr.  */
 292 #define FXM4 FXM + 1
 293   { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
 294
 295   /* The L field in a D or X form instruction.  */
 296 #define L FXM4 + 1
 297   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 298
 299   /* The LEV field in a POWER SVC form instruction.  */
 300 #define SVC_LEV L + 1
 301   { 0x7f, 5, NULL, NULL, 0 },
 302
 303   /* The LEV field in an SC form instruction.  */
 304 #define LEV SVC_LEV + 1
 305   { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
 306
 307   /* The LI field in an I form instruction.  The lower two bits are
 308      forced to zero.  */
 309 #define LI LEV + 1
 310   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 311
 312   /* The LI field in an I form instruction when used as an absolute
 313      address.  */
 314 #define LIA LI + 1
 315   { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 316
 317   /* The LS or WC field in an X (sync or wait) form instruction.  */
 318 #define LS LIA + 1
 319 #define WC LS
 320   { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 321
 322   /* The ME field in an M form instruction.  */
 323 #define ME LS + 1
 324 #define ME_MASK (0x1f << 1)
 325   { 0x1f, 1, NULL, NULL, 0 },
 326
 327   /* The MB and ME fields in an M form instruction expressed a single
 328      operand which is a bitmask indicating which bits to select.  This
 329      is a two operand form using PPC_OPERAND_NEXT.  See the
 330      description in opcode/ppc.h for what this means.  */
 331 #define MBE ME + 1
 332   { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 333   { -1, 0, insert_mbe, extract_mbe, 0 },
 334
 335   /* The MB or ME field in an MD or MDS form instruction.  The high
 336      bit is wrapped to the low end.  */
 337 #define MB6 MBE + 2
 338 #define ME6 MB6
 339 #define MB6_MASK (0x3f << 5)
 340   { 0x3f, 5, insert_mb6, extract_mb6, 0 },
 341
 342   /* The NB field in an X form instruction.  The value 32 is stored as
 343      0.  */
 344 #define NB MB6 + 1
 345   { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
 346
 347   /* The NSI field in a D form instruction.  This is the same as the
 348      SI field, only negated.  */
 349 #define NSI NB + 1
 350   { 0xffff, 0, insert_nsi, extract_nsi,
 351       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 352
 353   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 354 #define RA NSI + 1
 355 #define RA_MASK (0x1f << 16)
 356   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
 357
 358   /* As above, but 0 in the RA field means zero, not r0.  */
 359 #define RA0 RA + 1
 360   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
 361
 362   /* The RA field in the DQ form lq instruction, which has special
 363      value restrictions.  */
 364 #define RAQ RA0 + 1
 365   { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
 366
 367   /* The RA field in a D or X form instruction which is an updating
 368      load, which means that the RA field may not be zero and may not
 369      equal the RT field.  */
 370 #define RAL RAQ + 1
 371   { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
 372
 373   /* The RA field in an lmw instruction, which has special value
 374      restrictions.  */
 375 #define RAM RAL + 1
 376   { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
 377
 378   /* The RA field in a D or X form instruction which is an updating
 379      store or an updating floating point load, which means that the RA
 380      field may not be zero.  */
 381 #define RAS RAM + 1
 382   { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
 383
 384   /* The RA field of the tlbwe instruction, which is optional.  */
 385 #define RAOPT RAS + 1
 386   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 387
 388   /* The RB field in an X, XO, M, or MDS form instruction.  */
 389 #define RB RAOPT + 1
 390 #define RB_MASK (0x1f << 11)
 391   { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
 392
 393   /* The RB field in an X form instruction when it must be the same as
 394      the RS field in the instruction.  This is used for extended
 395      mnemonics like mr.  */
 396 #define RBS RB + 1
 397   { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 398
 399   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 400      instruction or the RT field in a D, DS, X, XFX or XO form
 401      instruction.  */
 402 #define RS RBS + 1
 403 #define RT RS
 404 #define RT_MASK (0x1f << 21)
 405   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
 406
 407   /* The RS and RT fields of the DS form stq instruction, which have
 408      special value restrictions.  */
 409 #define RSQ RS + 1
 410 #define RTQ RSQ
 411   { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
 412
 413   /* The RS field of the tlbwe instruction, which is optional.  */
 414 #define RSO RSQ + 1
 415 #define RTO RSO
 416   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 417
 418   /* The SH field in an X or M form instruction.  */
 419 #define SH RSO + 1
 420 #define SH_MASK (0x1f << 11)
 421   /* The other UIMM field in a EVX form instruction.  */
 422 #define EVUIMM SH
 423   { 0x1f, 11, NULL, NULL, 0 },
 424
 425   /* The SH field in an MD form instruction.  This is split.  */
 426 #define SH6 SH + 1
 427 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 428   { 0x3f, -1, insert_sh6, extract_sh6, 0 },
 429
 430   /* The SH field of the tlbwe instruction, which is optional.  */
 431 #define SHO SH6 + 1
 432   { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 433
 434   /* The SI field in a D form instruction.  */
 435 #define SI SHO + 1
 436   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 437
 438   /* The SI field in a D form instruction when we accept a wide range
 439      of positive values.  */
 440 #define SISIGNOPT SI + 1
 441   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 442
 443   /* The SPR field in an XFX form instruction.  This is flipped--the
 444      lower 5 bits are stored in the upper 5 and vice- versa.  */
 445 #define SPR SISIGNOPT + 1
 446 #define PMR SPR
 447 #define SPR_MASK (0x3ff << 11)
 448   { 0x3ff, 11, insert_spr, extract_spr, 0 },
 449
 450   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 451 #define SPRBAT SPR + 1
 452 #define SPRBAT_MASK (0x3 << 17)
 453   { 0x3, 17, NULL, NULL, 0 },
 454
 455   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 456 #define SPRG SPRBAT + 1
 457   { 0x1f, 16, insert_sprg, extract_sprg, 0 },
 458
 459   /* The SR field in an X form instruction.  */
 460 #define SR SPRG + 1
 461   { 0xf, 16, NULL, NULL, 0 },
 462
 463   /* The STRM field in an X AltiVec form instruction.  */
 464 #define STRM SR + 1
 465   /* The T field in a tlbilx form instruction.  */
 466 #define T STRM
 467   { 0x3, 21, NULL, NULL, 0 },
 468
 469   /* The SV field in a POWER SC form instruction.  */
 470 #define SV STRM + 1
 471   { 0x3fff, 2, NULL, NULL, 0 },
 472
 473   /* The TBR field in an XFX form instruction.  This is like the SPR
 474      field, but it is optional.  */
 475 #define TBR SV + 1
 476   { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 477
 478   /* The TO field in a D or X form instruction.  */
 479 #define TO TBR + 1
 480 #define DUI TO
 481 #define TO_MASK (0x1f << 21)
 482   { 0x1f, 21, NULL, NULL, 0 },
 483
 484   /* The UI field in a D form instruction.  */
 485 #define UI TO + 1
 486   { 0xffff, 0, NULL, NULL, 0 },
 487
 488   /* The VA field in a VA, VX or VXR form instruction.  */
 489 #define VA UI + 1
 490   { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
 491
 492   /* The VB field in a VA, VX or VXR form instruction.  */
 493 #define VB VA + 1
 494   { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
 495
 496   /* The VC field in a VA form instruction.  */
 497 #define VC VB + 1
 498   { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
 499
 500   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 501 #define VD VC + 1
 502 #define VS VD
 503   { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
 504
 505   /* The SIMM field in a VX form instruction, and TE in Z form.  */
 506 #define SIMM VD + 1
 507 #define TE SIMM
 508   { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
 509
 510   /* The UIMM field in a VX form instruction.  */
 511 #define UIMM SIMM + 1
 512   { 0x1f, 16, NULL, NULL, 0 },
 513
 514   /* The SHB field in a VA form instruction.  */
 515 #define SHB UIMM + 1
 516   { 0xf, 6, NULL, NULL, 0 },
 517
 518   /* The other UIMM field in a half word EVX form instruction.  */
 519 #define EVUIMM_2 SHB + 1
 520   { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
 521
 522   /* The other UIMM field in a word EVX form instruction.  */
 523 #define EVUIMM_4 EVUIMM_2 + 1
 524   { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
 525
 526   /* The other UIMM field in a double EVX form instruction.  */
 527 #define EVUIMM_8 EVUIMM_4 + 1
 528   { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
 529
 530   /* The WS field.  */
 531 #define WS EVUIMM_8 + 1
 532   { 0x7, 11, NULL, NULL, 0 },
 533
 534   /* PowerPC paired singles extensions.  */
 535   /* W bit in the pair singles instructions for x type instructions.  */
 536 #define PSWM WS + 1
 537   {  0x1, 10, 0, 0, 0 },
 538
 539   /* IDX bits for quantization in the pair singles instructions.  */
 540 #define PSQ PSWM + 1
 541   {  0x7, 12, 0, 0, 0 },
 542
 543   /* IDX bits for quantization in the pair singles x-type instructions.  */
 544 #define PSQM PSQ + 1
 545   {  0x7, 7, 0, 0, 0 },
 546
 547   /* Smaller D field for quantization in the pair singles instructions.  */
 548 #define PSD PSQM + 1
 549   {  0xfff, 0, 0, 0,  PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 550
 551 #define A_L PSD + 1
 552 #define W A_L
 553 #define MTMSRD_L W
 554   { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
 555
 556 #define RMC MTMSRD_L + 1
 557   { 0x3, 9, NULL, NULL, 0 },
 558
 559 #define R RMC + 1
 560   { 0x1, 16, NULL, NULL, 0 },
 561
 562 #define SP R + 1
 563   { 0x3, 19, NULL, NULL, 0 },
 564
 565 #define S SP + 1
 566   { 0x1, 20, NULL, NULL, 0 },
 567
 568   /* SH field starting at bit position 16.  */
 569 #define SH16 S + 1
 570   /* The DCM and DGM fields in a Z form instruction.  */
 571 #define DCM SH16
 572 #define DGM DCM
 573   { 0x3f, 10, NULL, NULL, 0 },
 574
 575   /* The EH field in larx instruction.  */
 576 #define EH SH16 + 1
 577   { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
 578
 579   /* The L field in an mtfsf or XFL form instruction.  */
 580 #define XFL_L EH + 1
 581   { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
 582
 583   /* Xilinx APU related masks and macros */
 584 #define FCRT XFL_L + 1
 585 #define FCRT_MASK (0x1f << 21)
 586   { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
 587
 588   /* Xilinx FSL related masks and macros */
 589 #define FSL FCRT + 1
 590 #define FSL_MASK (0x1f << 11)
 591   { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
 592
 593   /* Xilinx UDI related masks and macros */
 594 #define URT FSL + 1
 595   { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
 596
 597 #define URA URT + 1
 598   { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
 599
 600 #define URB URA + 1
 601   { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
 602
 603 #define URC URB + 1
 604   { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
 605
 606   /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
 607 #define XS6 URC + 1
 608 #define XT6 XS6
 609   { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
 610
 611   /* The XA field in an XX3 form instruction.  This is split.  */
 612 #define XA6 XT6 + 1
 613   { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
 614
 615   /* The XB field in an XX2 or XX3 form instruction.  This is split.  */
 616 #define XB6 XA6 + 1
 617   { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
 618
 619   /* The XB field in an XX3 form instruction when it must be the same as
 620      the XA field in the instruction.  This is used in extended mnemonics
 621      like xvmovdp.  This is split.  */
 622 #define XB6S XB6 + 1
 623   { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
 624
 625   /* The XC field in an XX4 form instruction.  This is split.  */
 626 #define XC6 XB6S + 1
 627   { 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
 628
 629   /* The DM or SHW field in an XX3 form instruction.  */
 630 #define DM XC6 + 1
 631 #define SHW DM
 632   { 0x3, 8, NULL, NULL, 0 },
 633
 634   /* The DM field in an extended mnemonic XX3 form instruction.  */
 635 #define DMEX DM + 1
 636   { 0x3, 8, insert_dm, extract_dm, 0 },
 637
 638   /* The UIM field in an XX2 form instruction.  */
 639 #define UIM DMEX + 1
 640   { 0x3, 16, NULL, NULL, 0 },
 641
 642 #define ERAT_T UIM + 1
 643   { 0x7, 21, NULL, NULL, 0 },
 644 };
 645
 646 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 647                                            / sizeof (powerpc_operands[0]));
 648
 649 /* The functions used to insert and extract complicated operands.  */
 650
 651 /* The BA field in an XL form instruction when it must be the same as
 652    the BT field in the same instruction.  This operand is marked FAKE.
 653    The insertion function just copies the BT field into the BA field,
 654    and the extraction function just checks that the fields are the
 655    same.  */
 656
 657 static unsigned long
 658 insert_bat (unsigned long insn,
 659             long value ATTRIBUTE_UNUSED,
 660             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 661             const char **errmsg ATTRIBUTE_UNUSED)
 662 {
 663   return insn | (((insn >> 21) & 0x1f) << 16);
 664 }
 665
 666 static long
 667 extract_bat (unsigned long insn,
 668              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 669              int *invalid)
 670 {
 671   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 672     *invalid = 1;
 673   return 0;
 674 }
 675
 676 /* The BB field in an XL form instruction when it must be the same as
 677    the BA field in the same instruction.  This operand is marked FAKE.
 678    The insertion function just copies the BA field into the BB field,
 679    and the extraction function just checks that the fields are the
 680    same.  */
 681
 682 static unsigned long
 683 insert_bba (unsigned long insn,
 684             long value ATTRIBUTE_UNUSED,
 685             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 686             const char **errmsg ATTRIBUTE_UNUSED)
 687 {
 688   return insn | (((insn >> 16) & 0x1f) << 11);
 689 }
 690
 691 static long
 692 extract_bba (unsigned long insn,
 693              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 694              int *invalid)
 695 {
 696   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 697     *invalid = 1;
 698   return 0;
 699 }
 700
 701 /* The BD field in a B form instruction when the - modifier is used.
 702    This modifier means that the branch is not expected to be taken.
 703    For chips built to versions of the architecture prior to version 2
 704    (ie. not Power4 compatible), we set the y bit of the BO field to 1
 705    if the offset is negative.  When extracting, we require that the y
 706    bit be 1 and that the offset be positive, since if the y bit is 0
 707    we just want to print the normal form of the instruction.
 708    Power4 compatible targets use two bits, "a", and "t", instead of
 709    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
 710    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
 711    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
 712    for branch on CTR.  We only handle the taken/not-taken hint here.
 713    Note that we don't relax the conditions tested here when
 714    disassembling with -Many because insns using extract_bdm and
 715    extract_bdp always occur in pairs.  One or the other will always
 716    be valid.  */
 717
 718 static unsigned long
 719 insert_bdm (unsigned long insn,
 720             long value,
 721             ppc_cpu_t dialect,
 722             const char **errmsg ATTRIBUTE_UNUSED)
 723 {
 724   if ((dialect & PPC_OPCODE_POWER4) == 0)
 725     {
 726       if ((value & 0x8000) != 0)
 727         insn |= 1 << 21;
 728     }
 729   else
 730     {
 731       if ((insn & (0x14 << 21)) == (0x04 << 21))
 732         insn |= 0x02 << 21;
 733       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 734         insn |= 0x08 << 21;
 735     }
 736   return insn | (value & 0xfffc);
 737 }
 738
 739 static long
 740 extract_bdm (unsigned long insn,
 741              ppc_cpu_t dialect,
 742              int *invalid)
 743 {
 744   if ((dialect & PPC_OPCODE_POWER4) == 0)
 745     {
 746       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
 747         *invalid = 1;
 748     }
 749   else
 750     {
 751       if ((insn & (0x17 << 21)) != (0x06 << 21)
 752           && (insn & (0x1d << 21)) != (0x18 << 21))
 753         *invalid = 1;
 754     }
 755
 756   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 757 }
 758
 759 /* The BD field in a B form instruction when the + modifier is used.
 760    This is like BDM, above, except that the branch is expected to be
 761    taken.  */
 762
 763 static unsigned long
 764 insert_bdp (unsigned long insn,
 765             long value,
 766             ppc_cpu_t dialect,
 767             const char **errmsg ATTRIBUTE_UNUSED)
 768 {
 769   if ((dialect & PPC_OPCODE_POWER4) == 0)
 770     {
 771       if ((value & 0x8000) == 0)
 772         insn |= 1 << 21;
 773     }
 774   else
 775     {
 776       if ((insn & (0x14 << 21)) == (0x04 << 21))
 777         insn |= 0x03 << 21;
 778       else if ((insn & (0x14 << 21)) == (0x10 << 21))
 779         insn |= 0x09 << 21;
 780     }
 781   return insn | (value & 0xfffc);
 782 }
 783
 784 static long
 785 extract_bdp (unsigned long insn,
 786              ppc_cpu_t dialect,
 787              int *invalid)
 788 {
 789   if ((dialect & PPC_OPCODE_POWER4) == 0)
 790     {
 791       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
 792         *invalid = 1;
 793     }
 794   else
 795     {
 796       if ((insn & (0x17 << 21)) != (0x07 << 21)
 797           && (insn & (0x1d << 21)) != (0x19 << 21))
 798         *invalid = 1;
 799     }
 800
 801   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 802 }
 803
 804 /* Check for legal values of a BO field.  */
 805
 806 static int
 807 valid_bo (long value, ppc_cpu_t dialect, int extract)
 808 {
 809   if ((dialect & PPC_OPCODE_POWER4) == 0)
 810     {
 811       int valid;
 812       /* Certain encodings have bits that are required to be zero.
 813          These are (z must be zero, y may be anything):
 814              001zy
 815              011zy
 816              1z00y
 817              1z01y
 818              1z1zz
 819       */
 820       switch (value & 0x14)
 821         {
 822         default:
 823         case 0:
 824           valid = 1;
 825           break;
 826         case 0x4:
 827           valid = (value & 0x2) == 0;
 828           break;
 829         case 0x10:
 830           valid = (value & 0x8) == 0;
 831           break;
 832         case 0x14:
 833           valid = value == 0x14;
 834           break;
 835         }
 836       /* When disassembling with -Many, accept power4 encodings too.  */
 837       if (valid
 838           || (dialect & PPC_OPCODE_ANY) == 0
 839           || !extract)
 840         return valid;
 841     }
 842
 843   /* Certain encodings have bits that are required to be zero.
 844      These are (z must be zero, a & t may be anything):
 845          0000z
 846          0001z
 847          0100z
 848          0101z
 849          001at
 850          011at
 851          1a00t
 852          1a01t
 853          1z1zz
 854   */
 855   if ((value & 0x14) == 0)
 856     return (value & 0x1) == 0;
 857   else if ((value & 0x14) == 0x14)
 858     return value == 0x14;
 859   else
 860     return 1;
 861 }
 862
 863 /* The BO field in a B form instruction.  Warn about attempts to set
 864    the field to an illegal value.  */
 865
 866 static unsigned long
 867 insert_bo (unsigned long insn,
 868            long value,
 869            ppc_cpu_t dialect,
 870            const char **errmsg)
 871 {
 872   if (!valid_bo (value, dialect, 0))
 873     *errmsg = _("invalid conditional option");
 874   return insn | ((value & 0x1f) << 21);
 875 }
 876
 877 static long
 878 extract_bo (unsigned long insn,
 879             ppc_cpu_t dialect,
 880             int *invalid)
 881 {
 882   long value;
 883
 884   value = (insn >> 21) & 0x1f;
 885   if (!valid_bo (value, dialect, 1))
 886     *invalid = 1;
 887   return value;
 888 }
 889
 890 /* The BO field in a B form instruction when the + or - modifier is
 891    used.  This is like the BO field, but it must be even.  When
 892    extracting it, we force it to be even.  */
 893
 894 static unsigned long
 895 insert_boe (unsigned long insn,
 896             long value,
 897             ppc_cpu_t dialect,
 898             const char **errmsg)
 899 {
 900   if (!valid_bo (value, dialect, 0))
 901     *errmsg = _("invalid conditional option");
 902   else if ((value & 1) != 0)
 903     *errmsg = _("attempt to set y bit when using + or - modifier");
 904
 905   return insn | ((value & 0x1f) << 21);
 906 }
 907
 908 static long
 909 extract_boe (unsigned long insn,
 910              ppc_cpu_t dialect,
 911              int *invalid)
 912 {
 913   long value;
 914
 915   value = (insn >> 21) & 0x1f;
 916   if (!valid_bo (value, dialect, 1))
 917     *invalid = 1;
 918   return value & 0x1e;
 919 }
 920
 921 /* FXM mask in mfcr and mtcrf instructions.  */
 922
 923 static unsigned long
 924 insert_fxm (unsigned long insn,
 925             long value,
 926             ppc_cpu_t dialect,
 927             const char **errmsg)
 928 {
 929   /* If we're handling the mfocrf and mtocrf insns ensure that exactly
 930      one bit of the mask field is set.  */
 931   if ((insn & (1 << 20)) != 0)
 932     {
 933       if (value == 0 || (value & -value) != value)
 934         {
 935           *errmsg = _("invalid mask field");
 936           value = 0;
 937         }
 938     }
 939
 940   /* If the optional field on mfcr is missing that means we want to use
 941      the old form of the instruction that moves the whole cr.  In that
 942      case we'll have VALUE zero.  There doesn't seem to be a way to
 943      distinguish this from the case where someone writes mfcr %r3,0.  */
 944   else if (value == 0)
 945     ;
 946
 947   /* If only one bit of the FXM field is set, we can use the new form
 948      of the instruction, which is faster.  Unlike the Power4 branch hint
 949      encoding, this is not backward compatible.  Do not generate the
 950      new form unless -mpower4 has been given, or -many and the two
 951      operand form of mfcr was used.  */
 952   else if ((value & -value) == value
 953            && ((dialect & PPC_OPCODE_POWER4) != 0
 954                || ((dialect & PPC_OPCODE_ANY) != 0
 955                    && (insn & (0x3ff << 1)) == 19 << 1)))
 956     insn |= 1 << 20;
 957
 958   /* Any other value on mfcr is an error.  */
 959   else if ((insn & (0x3ff << 1)) == 19 << 1)
 960     {
 961       *errmsg = _("ignoring invalid mfcr mask");
 962       value = 0;
 963     }
 964
 965   return insn | ((value & 0xff) << 12);
 966 }
 967
 968 static long
 969 extract_fxm (unsigned long insn,
 970              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
 971              int *invalid)
 972 {
 973   long mask = (insn >> 12) & 0xff;
 974
 975   /* Is this a Power4 insn?  */
 976   if ((insn & (1 << 20)) != 0)
 977     {
 978       /* Exactly one bit of MASK should be set.  */
 979       if (mask == 0 || (mask & -mask) != mask)
 980         *invalid = 1;
 981     }
 982
 983   /* Check that non-power4 form of mfcr has a zero MASK.  */
 984   else if ((insn & (0x3ff << 1)) == 19 << 1)
 985     {
 986       if (mask != 0)
 987         *invalid = 1;
 988     }
 989
 990   return mask;
 991 }
 992
 993 /* The MB and ME fields in an M form instruction expressed as a single
 994    operand which is itself a bitmask.  The extraction function always
 995    marks it as invalid, since we never want to recognize an
 996    instruction which uses a field of this type.  */
 997
 998 static unsigned long
 999 insert_mbe (unsigned long insn,
1000             long value,
1001             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1002             const char **errmsg)
1003 {
1004   unsigned long uval, mask;
1005   int mb, me, mx, count, last;
1006
1007   uval = value;
1008
1009   if (uval == 0)
1010     {
1011       *errmsg = _("illegal bitmask");
1012       return insn;
1013     }
1014
1015   mb = 0;
1016   me = 32;
1017   if ((uval & 1) != 0)
1018     last = 1;
1019   else
1020     last = 0;
1021   count = 0;
1022
1023   /* mb: location of last 0->1 transition */
1024   /* me: location of last 1->0 transition */
1025   /* count: # transitions */
1026
1027   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1028     {
1029       if ((uval & mask) && !last)
1030         {
1031           ++count;
1032           mb = mx;
1033           last = 1;
1034         }
1035       else if (!(uval & mask) && last)
1036         {
1037           ++count;
1038           me = mx;
1039           last = 0;
1040         }
1041     }
1042   if (me == 0)
1043     me = 32;
1044
1045   if (count != 2 && (count != 0 || ! last))
1046     *errmsg = _("illegal bitmask");
1047
1048   return insn | (mb << 6) | ((me - 1) << 1);
1049 }
1050
1051 static long
1052 extract_mbe (unsigned long insn,
1053              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1054              int *invalid)
1055 {
1056   long ret;
1057   int mb, me;
1058   int i;
1059
1060   *invalid = 1;
1061
1062   mb = (insn >> 6) & 0x1f;
1063   me = (insn >> 1) & 0x1f;
1064   if (mb < me + 1)
1065     {
1066       ret = 0;
1067       for (i = mb; i <= me; i++)
1068         ret |= 1L << (31 - i);
1069     }
1070   else if (mb == me + 1)
1071     ret = ~0;
1072   else /* (mb > me + 1) */
1073     {
1074       ret = ~0;
1075       for (i = me + 1; i < mb; i++)
1076         ret &= ~(1L << (31 - i));
1077     }
1078   return ret;
1079 }
1080
1081 /* The MB or ME field in an MD or MDS form instruction.  The high bit
1082    is wrapped to the low end.  */
1083
1084 static unsigned long
1085 insert_mb6 (unsigned long insn,
1086             long value,
1087             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1088             const char **errmsg ATTRIBUTE_UNUSED)
1089 {
1090   return insn | ((value & 0x1f) << 6) | (value & 0x20);
1091 }
1092
1093 static long
1094 extract_mb6 (unsigned long insn,
1095              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1096              int *invalid ATTRIBUTE_UNUSED)
1097 {
1098   return ((insn >> 6) & 0x1f) | (insn & 0x20);
1099 }
1100
1101 /* The NB field in an X form instruction.  The value 32 is stored as
1102    0.  */
1103
1104 static long
1105 extract_nb (unsigned long insn,
1106             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1107             int *invalid ATTRIBUTE_UNUSED)
1108 {
1109   long ret;
1110
1111   ret = (insn >> 11) & 0x1f;
1112   if (ret == 0)
1113     ret = 32;
1114   return ret;
1115 }
1116
1117 /* The NSI field in a D form instruction.  This is the same as the SI
1118    field, only negated.  The extraction function always marks it as
1119    invalid, since we never want to recognize an instruction which uses
1120    a field of this type.  */
1121
1122 static unsigned long
1123 insert_nsi (unsigned long insn,
1124             long value,
1125             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1126             const char **errmsg ATTRIBUTE_UNUSED)
1127 {
1128   return insn | (-value & 0xffff);
1129 }
1130
1131 static long
1132 extract_nsi (unsigned long insn,
1133              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1134              int *invalid)
1135 {
1136   *invalid = 1;
1137   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1138 }
1139
1140 /* The RA field in a D or X form instruction which is an updating
1141    load, which means that the RA field may not be zero and may not
1142    equal the RT field.  */
1143
1144 static unsigned long
1145 insert_ral (unsigned long insn,
1146             long value,
1147             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1148             const char **errmsg)
1149 {
1150   if (value == 0
1151       || (unsigned long) value == ((insn >> 21) & 0x1f))
1152     *errmsg = "invalid register operand when updating";
1153   return insn | ((value & 0x1f) << 16);
1154 }
1155
1156 /* The RA field in an lmw instruction, which has special value
1157    restrictions.  */
1158
1159 static unsigned long
1160 insert_ram (unsigned long insn,
1161             long value,
1162             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1163             const char **errmsg)
1164 {
1165   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1166     *errmsg = _("index register in load range");
1167   return insn | ((value & 0x1f) << 16);
1168 }
1169
1170 /* The RA field in the DQ form lq instruction, which has special
1171    value restrictions.  */
1172
1173 static unsigned long
1174 insert_raq (unsigned long insn,
1175             long value,
1176             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1177             const char **errmsg)
1178 {
1179   long rtvalue = (insn & RT_MASK) >> 21;
1180
1181   if (value == rtvalue)
1182     *errmsg = _("source and target register operands must be different");
1183   return insn | ((value & 0x1f) << 16);
1184 }
1185
1186 /* The RA field in a D or X form instruction which is an updating
1187    store or an updating floating point load, which means that the RA
1188    field may not be zero.  */
1189
1190 static unsigned long
1191 insert_ras (unsigned long insn,
1192             long value,
1193             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1194             const char **errmsg)
1195 {
1196   if (value == 0)
1197     *errmsg = _("invalid register operand when updating");
1198   return insn | ((value & 0x1f) << 16);
1199 }
1200
1201 /* The RB field in an X form instruction when it must be the same as
1202    the RS field in the instruction.  This is used for extended
1203    mnemonics like mr.  This operand is marked FAKE.  The insertion
1204    function just copies the BT field into the BA field, and the
1205    extraction function just checks that the fields are the same.  */
1206
1207 static unsigned long
1208 insert_rbs (unsigned long insn,
1209             long value ATTRIBUTE_UNUSED,
1210             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1211             const char **errmsg ATTRIBUTE_UNUSED)
1212 {
1213   return insn | (((insn >> 21) & 0x1f) << 11);
1214 }
1215
1216 static long
1217 extract_rbs (unsigned long insn,
1218              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1219              int *invalid)
1220 {
1221   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1222     *invalid = 1;
1223   return 0;
1224 }
1225
1226 /* The SH field in an MD form instruction.  This is split.  */
1227
1228 static unsigned long
1229 insert_sh6 (unsigned long insn,
1230             long value,
1231             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1232             const char **errmsg ATTRIBUTE_UNUSED)
1233 {
1234   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1235 }
1236
1237 static long
1238 extract_sh6 (unsigned long insn,
1239              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1240              int *invalid ATTRIBUTE_UNUSED)
1241 {
1242   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1243 }
1244
1245 /* The SPR field in an XFX form instruction.  This is flipped--the
1246    lower 5 bits are stored in the upper 5 and vice- versa.  */
1247
1248 static unsigned long
1249 insert_spr (unsigned long insn,
1250             long value,
1251             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1252             const char **errmsg ATTRIBUTE_UNUSED)
1253 {
1254   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1255 }
1256
1257 static long
1258 extract_spr (unsigned long insn,
1259              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1260              int *invalid ATTRIBUTE_UNUSED)
1261 {
1262   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1263 }
1264
1265 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
1266
1267 static unsigned long
1268 insert_sprg (unsigned long insn,
1269              long value,
1270              ppc_cpu_t dialect,
1271              const char **errmsg)
1272 {
1273   if (value > 7
1274       || (value > 3
1275           && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0))
1276     *errmsg = _("invalid sprg number");
1277
1278   /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1279      user mode.  Anything else must use spr 272..279.  */
1280   if (value <= 3 || (insn & 0x100) != 0)
1281     value |= 0x10;
1282
1283   return insn | ((value & 0x17) << 16);
1284 }
1285
1286 static long
1287 extract_sprg (unsigned long insn,
1288               ppc_cpu_t dialect,
1289               int *invalid)
1290 {
1291   unsigned long val = (insn >> 16) & 0x1f;
1292
1293   /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
1294      If not BOOKE or 405, then both use only 272..275.  */
1295   if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)
1296       || (val - 0x10 > 7 && (insn & 0x100) != 0)
1297       || val <= 3
1298       || (val & 8) != 0)
1299     *invalid = 1;
1300   return val & 7;
1301 }
1302
1303 /* The TBR field in an XFX instruction.  This is just like SPR, but it
1304    is optional.  When TBR is omitted, it must be inserted as 268 (the
1305    magic number of the TB register).  These functions treat 0
1306    (indicating an omitted optional operand) as 268.  This means that
1307    ``mftb 4,0'' is not handled correctly.  This does not matter very
1308    much, since the architecture manual does not define mftb as
1309    accepting any values other than 268 or 269.  */
1310
1311 #define TB (268)
1312
1313 static unsigned long
1314 insert_tbr (unsigned long insn,
1315             long value,
1316             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1317             const char **errmsg ATTRIBUTE_UNUSED)
1318 {
1319   if (value == 0)
1320     value = TB;
1321   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1322 }
1323
1324 static long
1325 extract_tbr (unsigned long insn,
1326              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1327              int *invalid ATTRIBUTE_UNUSED)
1328 {
1329   long ret;
1330
1331   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1332   if (ret == TB)
1333     ret = 0;
1334   return ret;
1335 }
1336
1337 /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
1338
1339 static unsigned long
1340 insert_xt6 (unsigned long insn,
1341             long value,
1342             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1343             const char **errmsg ATTRIBUTE_UNUSED)
1344 {
1345   return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
1346 }
1347
1348 static long
1349 extract_xt6 (unsigned long insn,
1350              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1351              int *invalid ATTRIBUTE_UNUSED)
1352 {
1353   return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
1354 }
1355
1356 /* The XA field in an XX3 form instruction.  This is split.  */
1357
1358 static unsigned long
1359 insert_xa6 (unsigned long insn,
1360             long value,
1361             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1362             const char **errmsg ATTRIBUTE_UNUSED)
1363 {
1364   return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
1365 }
1366
1367 static long
1368 extract_xa6 (unsigned long insn,
1369              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1370              int *invalid ATTRIBUTE_UNUSED)
1371 {
1372   return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1373 }
1374
1375 /* The XB field in an XX3 form instruction.  This is split.  */
1376
1377 static unsigned long
1378 insert_xb6 (unsigned long insn,
1379             long value,
1380             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1381             const char **errmsg ATTRIBUTE_UNUSED)
1382 {
1383   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1384 }
1385
1386 static long
1387 extract_xb6 (unsigned long insn,
1388              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1389              int *invalid ATTRIBUTE_UNUSED)
1390 {
1391   return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
1392 }
1393
1394 /* The XB field in an XX3 form instruction when it must be the same as
1395    the XA field in the instruction.  This is used for extended
1396    mnemonics like xvmovdp.  This operand is marked FAKE.  The insertion
1397    function just copies the XA field into the XB field, and the
1398    extraction function just checks that the fields are the same.  */
1399
1400 static unsigned long
1401 insert_xb6s (unsigned long insn,
1402             long value ATTRIBUTE_UNUSED,
1403             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1404             const char **errmsg ATTRIBUTE_UNUSED)
1405 {
1406   return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
1407 }
1408
1409 static long
1410 extract_xb6s (unsigned long insn,
1411              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1412              int *invalid)
1413 {
1414   if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1415       || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
1416     *invalid = 1;
1417   return 0;
1418 }
1419
1420 /* The XC field in an XX4 form instruction.  This is split.  */
1421
1422 static unsigned long
1423 insert_xc6 (unsigned long insn,
1424             long value,
1425             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1426             const char **errmsg ATTRIBUTE_UNUSED)
1427 {
1428   return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
1429 }
1430
1431 static long
1432 extract_xc6 (unsigned long insn,
1433              ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1434              int *invalid ATTRIBUTE_UNUSED)
1435 {
1436   return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
1437 }
1438
1439 static unsigned long
1440 insert_dm (unsigned long insn,
1441            long value,
1442            ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1443            const char **errmsg)
1444 {
1445   if (value != 0 && value != 1)
1446     *errmsg = _("invalid constant");
1447   return insn | (((value) ? 3 : 0) << 8);
1448 }
1449
1450 static long
1451 extract_dm (unsigned long insn,
1452             ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1453             int *invalid)
1454 {
1455   long value;
1456
1457   value = (insn >> 8) & 3;
1458   if (value != 0 && value != 3)
1459     *invalid = 1;
1460   return (value) ? 1 : 0;
1461 }
1462 \f
1463 /* Macros used to form opcodes.  */
1464
1465 /* The main opcode.  */
1466 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1467 #define OP_MASK OP (0x3f)
1468
1469 /* The main opcode combined with a trap code in the TO field of a D
1470    form instruction.  Used for extended mnemonics for the trap
1471    instructions.  */
1472 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1473 #define OPTO_MASK (OP_MASK | TO_MASK)
1474
1475 /* The main opcode combined with a comparison size bit in the L field
1476    of a D form or X form instruction.  Used for extended mnemonics for
1477    the comparison instructions.  */
1478 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1479 #define OPL_MASK OPL (0x3f,1)
1480
1481 /* An A form instruction.  */
1482 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1483 #define A_MASK A (0x3f, 0x1f, 1)
1484
1485 /* An A_MASK with the FRB field fixed.  */
1486 #define AFRB_MASK (A_MASK | FRB_MASK)
1487
1488 /* An A_MASK with the FRC field fixed.  */
1489 #define AFRC_MASK (A_MASK | FRC_MASK)
1490
1491 /* An A_MASK with the FRA and FRC fields fixed.  */
1492 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1493
1494 /* An AFRAFRC_MASK, but with L bit clear.  */
1495 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1496
1497 /* A B form instruction.  */
1498 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1499 #define B_MASK B (0x3f, 1, 1)
1500
1501 /* A B form instruction setting the BO field.  */
1502 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1503 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1504
1505 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1506    matching a conditional branch regardless of the setting of the y
1507    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1508 #define Y_MASK   (((unsigned long) 1) << 21)
1509 #define AT1_MASK (((unsigned long) 3) << 21)
1510 #define AT2_MASK (((unsigned long) 9) << 21)
1511 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1512 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1513
1514 /* A B form instruction setting the BO field and the condition bits of
1515    the BI field.  */
1516 #define BBOCB(op, bo, cb, aa, lk) \
1517   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1518 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1519
1520 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1521 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1522 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1523 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1524
1525 /* A BBOYCB_MASK in which the BI field is fixed.  */
1526 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1527 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1528
1529 /* An Context form instruction.  */
1530 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1531 #define CTX_MASK CTX(0x3f, 0x7)
1532
1533 /* An User Context form instruction.  */
1534 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1535 #define UCTX_MASK UCTX(0x3f, 0x1f)
1536
1537 /* The main opcode mask with the RA field clear.  */
1538 #define DRA_MASK (OP_MASK | RA_MASK)
1539
1540 /* A DS form instruction.  */
1541 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1542 #define DS_MASK DSO (0x3f, 3)
1543
1544 /* An EVSEL form instruction.  */
1545 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1546 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1547
1548 /* An M form instruction.  */
1549 #define M(op, rc) (OP (op) | ((rc) & 1))
1550 #define M_MASK M (0x3f, 1)
1551
1552 /* An M form instruction with the ME field specified.  */
1553 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1554
1555 /* An M_MASK with the MB and ME fields fixed.  */
1556 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1557
1558 /* An M_MASK with the SH and ME fields fixed.  */
1559 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1560
1561 /* An MD form instruction.  */
1562 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1563 #define MD_MASK MD (0x3f, 0x7, 1)
1564
1565 /* An MD_MASK with the MB field fixed.  */
1566 #define MDMB_MASK (MD_MASK | MB6_MASK)
1567
1568 /* An MD_MASK with the SH field fixed.  */
1569 #define MDSH_MASK (MD_MASK | SH6_MASK)
1570
1571 /* An MDS form instruction.  */
1572 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1573 #define MDS_MASK MDS (0x3f, 0xf, 1)
1574
1575 /* An MDS_MASK with the MB field fixed.  */
1576 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1577
1578 /* An SC form instruction.  */
1579 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1580 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1581
1582 /* An VX form instruction.  */
1583 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1584
1585 /* The mask for an VX form instruction.  */
1586 #define VX_MASK VX(0x3f, 0x7ff)
1587
1588 /* An VA form instruction.  */
1589 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1590
1591 /* The mask for an VA form instruction.  */
1592 #define VXA_MASK VXA(0x3f, 0x3f)
1593
1594 /* An VXR form instruction.  */
1595 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1596
1597 /* The mask for a VXR form instruction.  */
1598 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1599
1600 /* An X form instruction.  */
1601 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1602
1603 /* An XX2 form instruction.  */
1604 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
1605
1606 /* An XX3 form instruction.  */
1607 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
1608
1609 /* An XX3 form instruction with the RC bit specified.  */
1610 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
1611
1612 /* An XX4 form instruction.  */
1613 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
1614
1615 /* A Z form instruction.  */
1616 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1617
1618 /* An X form instruction with the RC bit specified.  */
1619 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1620
1621 /* A Z form instruction with the RC bit specified.  */
1622 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1623
1624 /* The mask for an X form instruction.  */
1625 #define X_MASK XRC (0x3f, 0x3ff, 1)
1626
1627 /* An X form wait instruction with everything filled in except the WC field.  */
1628 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
1629
1630 /* The mask for an XX1 form instruction.  */
1631 #define XX1_MASK X (0x3f, 0x3ff)
1632
1633 /* The mask for an XX2 form instruction.  */
1634 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
1635
1636 /* The mask for an XX2 form instruction with the UIM bits specified.  */
1637 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
1638
1639 /* The mask for an XX2 form instruction with the BF bits specified.  */
1640 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
1641
1642 /* The mask for an XX3 form instruction.  */
1643 #define XX3_MASK XX3 (0x3f, 0xff)
1644
1645 /* The mask for an XX3 form instruction with the BF bits specified.  */
1646 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
1647
1648 /* The mask for an XX3 form instruction with the DM or SHW bits specified.  */
1649 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
1650 #define XX3SHW_MASK XX3DM_MASK
1651
1652 /* The mask for an XX4 form instruction.  */
1653 #define XX4_MASK XX4 (0x3f, 0x3)
1654
1655 /* An X form wait instruction with everything filled in except the WC field.  */
1656 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
1657
1658 /* The mask for a Z form instruction.  */
1659 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1660 #define Z2_MASK ZRC (0x3f, 0xff, 1)
1661
1662 /* An X_MASK with the RA field fixed.  */
1663 #define XRA_MASK (X_MASK | RA_MASK)
1664
1665 /* An XRA_MASK with the W field clear.  */
1666 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1667
1668 /* An X_MASK with the RB field fixed.  */
1669 #define XRB_MASK (X_MASK | RB_MASK)
1670
1671 /* An X_MASK with the RT field fixed.  */
1672 #define XRT_MASK (X_MASK | RT_MASK)
1673
1674 /* An XRT_MASK mask with the L bits clear.  */
1675 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1676
1677 /* An X_MASK with the RA and RB fields fixed.  */
1678 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1679
1680 /* An XRARB_MASK, but with the L bit clear.  */
1681 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1682
1683 /* An X_MASK with the RT and RA fields fixed.  */
1684 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1685
1686 /* An XRTRA_MASK, but with L bit clear.  */
1687 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1688
1689 /* An X form instruction with the L bit specified.  */
1690 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1691
1692 /* An X form instruction with the L bits specified.  */
1693 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1694
1695 /* An X form instruction with RT fields specified */
1696 #define XRT(op, xop, rt) (X ((op), (xop)) \
1697         | ((((unsigned long)(rt)) & 0x1f) << 21))
1698
1699 /* An X form instruction with RT and RA fields specified */
1700 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
1701         | ((((unsigned long)(rt)) & 0x1f) << 21) \
1702         | ((((unsigned long)(ra)) & 0x1f) << 16))
1703
1704 /* The mask for an X form comparison instruction.  */
1705 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1706
1707 /* The mask for an X form comparison instruction with the L field
1708    fixed.  */
1709 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1710
1711 /* An X form trap instruction with the TO field specified.  */
1712 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1713 #define XTO_MASK (X_MASK | TO_MASK)
1714
1715 /* An X form tlb instruction with the SH field specified.  */
1716 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1717 #define XTLB_MASK (X_MASK | SH_MASK)
1718
1719 /* An X form sync instruction.  */
1720 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1721
1722 /* An X form sync instruction with everything filled in except the LS field.  */
1723 #define XSYNC_MASK (0xff9fffff)
1724
1725 /* An X_MASK, but with the EH bit clear.  */
1726 #define XEH_MASK (X_MASK & ~((unsigned long )1))
1727
1728 /* An X form AltiVec dss instruction.  */
1729 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1730 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1731
1732 /* An XFL form instruction.  */
1733 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1734 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
1735
1736 /* An X form isel instruction.  */
1737 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1738 #define XISEL_MASK      XISEL(0x3f, 0x1f)
1739
1740 /* An XL form instruction with the LK field set to 0.  */
1741 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1742
1743 /* An XL form instruction which uses the LK field.  */
1744 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1745
1746 /* The mask for an XL form instruction.  */
1747 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1748
1749 /* An XL form instruction which explicitly sets the BO field.  */
1750 #define XLO(op, bo, xop, lk) \
1751   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1752 #define XLO_MASK (XL_MASK | BO_MASK)
1753
1754 /* An XL form instruction which explicitly sets the y bit of the BO
1755    field.  */
1756 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1757 #define XLYLK_MASK (XL_MASK | Y_MASK)
1758
1759 /* An XL form instruction which sets the BO field and the condition
1760    bits of the BI field.  */
1761 #define XLOCB(op, bo, cb, xop, lk) \
1762   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1763 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1764
1765 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1766 #define XLBB_MASK (XL_MASK | BB_MASK)
1767 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1768 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1769
1770 /* A mask for branch instructions using the BH field.  */
1771 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1772
1773 /* An XL_MASK with the BO and BB fields fixed.  */
1774 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1775
1776 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1777 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1778
1779 /* An XO form instruction.  */
1780 #define XO(op, xop, oe, rc) \
1781   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1782 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1783
1784 /* An XO_MASK with the RB field fixed.  */
1785 #define XORB_MASK (XO_MASK | RB_MASK)
1786
1787 /* An XOPS form instruction for paired singles.  */
1788 #define XOPS(op, xop, rc) \
1789   (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1790 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
1791
1792
1793 /* An XS form instruction.  */
1794 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1795 #define XS_MASK XS (0x3f, 0x1ff, 1)
1796
1797 /* A mask for the FXM version of an XFX form instruction.  */
1798 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1799
1800 /* An XFX form instruction with the FXM field filled in.  */
1801 #define XFXM(op, xop, fxm, p4) \
1802   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1803    | ((unsigned long)(p4) << 20))
1804
1805 /* An XFX form instruction with the SPR field filled in.  */
1806 #define XSPR(op, xop, spr) \
1807   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1808 #define XSPR_MASK (X_MASK | SPR_MASK)
1809
1810 /* An XFX form instruction with the SPR field filled in except for the
1811    SPRBAT field.  */
1812 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1813
1814 /* An XFX form instruction with the SPR field filled in except for the
1815    SPRG field.  */
1816 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1817
1818 /* An X form instruction with everything filled in except the E field.  */
1819 #define XE_MASK (0xffff7fff)
1820
1821 /* An X form user context instruction.  */
1822 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1823 #define XUC_MASK      XUC(0x3f, 0x1f)
1824
1825 /* An XW form instruction.  */
1826 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
1827 /* The mask for a G form instruction. rc not supported at present.  */
1828 #define XW_MASK XW (0x3f, 0x3f, 0)
1829
1830 /* An APU form instruction.  */
1831 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
1832
1833 /* The mask for an APU form instruction.  */
1834 #define APU_MASK APU (0x3f, 0x3ff, 1)
1835 #define APU_RT_MASK (APU_MASK | RT_MASK)
1836 #define APU_RA_MASK (APU_MASK | RA_MASK)
1837
1838 /* The BO encodings used in extended conditional branch mnemonics.  */
1839 #define BODNZF  (0x0)
1840 #define BODNZFP (0x1)
1841 #define BODZF   (0x2)
1842 #define BODZFP  (0x3)
1843 #define BODNZT  (0x8)
1844 #define BODNZTP (0x9)
1845 #define BODZT   (0xa)
1846 #define BODZTP  (0xb)
1847
1848 #define BOF     (0x4)
1849 #define BOFP    (0x5)
1850 #define BOFM4   (0x6)
1851 #define BOFP4   (0x7)
1852 #define BOT     (0xc)
1853 #define BOTP    (0xd)
1854 #define BOTM4   (0xe)
1855 #define BOTP4   (0xf)
1856
1857 #define BODNZ   (0x10)
1858 #define BODNZP  (0x11)
1859 #define BODZ    (0x12)
1860 #define BODZP   (0x13)
1861 #define BODNZM4 (0x18)
1862 #define BODNZP4 (0x19)
1863 #define BODZM4  (0x1a)
1864 #define BODZP4  (0x1b)
1865
1866 #define BOU     (0x14)
1867
1868 /* The BI condition bit encodings used in extended conditional branch
1869    mnemonics.  */
1870 #define CBLT    (0)
1871 #define CBGT    (1)
1872 #define CBEQ    (2)
1873 #define CBSO    (3)
1874
1875 /* The TO encodings used in extended trap mnemonics.  */
1876 #define TOLGT   (0x1)
1877 #define TOLLT   (0x2)
1878 #define TOEQ    (0x4)
1879 #define TOLGE   (0x5)
1880 #define TOLNL   (0x5)
1881 #define TOLLE   (0x6)
1882 #define TOLNG   (0x6)
1883 #define TOGT    (0x8)
1884 #define TOGE    (0xc)
1885 #define TONL    (0xc)
1886 #define TOLT    (0x10)
1887 #define TOLE    (0x14)
1888 #define TONG    (0x14)
1889 #define TONE    (0x18)
1890 #define TOU     (0x1f)
1891 \f
1892 /* Smaller names for the flags so each entry in the opcodes table will
1893    fit on a single line.  */
1894 #define PPCNONE 0
1895 #undef  PPC
1896 #define PPC     PPC_OPCODE_PPC
1897 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1898 #define POWER4  PPC_OPCODE_POWER4
1899 #define POWER5  PPC_OPCODE_POWER5
1900 #define POWER6  PPC_OPCODE_POWER6
1901 #define POWER7  PPC_OPCODE_POWER7
1902 #define CELL    PPC_OPCODE_CELL
1903 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
1904 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
1905 #define PPC403  PPC_OPCODE_403
1906 #define PPC405  PPC_OPCODE_405
1907 #define PPC440  PPC_OPCODE_440
1908 #define PPC464  PPC440
1909 #define PPC476  PPC_OPCODE_476
1910 #define PPC750  PPC
1911 #define PPC7450 PPC
1912 #define PPC860  PPC
1913 #define PPCPS   PPC_OPCODE_PPCPS
1914 #define PPCVEC  PPC_OPCODE_ALTIVEC
1915 #define PPCVSX  PPC_OPCODE_VSX
1916 #define POWER   PPC_OPCODE_POWER
1917 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1918 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1919 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1920 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1921 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1922 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1923 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1924 #define MFDEC1  PPC_OPCODE_POWER
1925 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1926 #define BOOKE   PPC_OPCODE_BOOKE
1927 #define CLASSIC PPC_OPCODE_CLASSIC
1928 #define PPCE300 PPC_OPCODE_E300
1929 #define PPCSPE  PPC_OPCODE_SPE
1930 #define PPCISEL PPC_OPCODE_ISEL
1931 #define PPCEFS  PPC_OPCODE_EFS
1932 #define PPCBRLK PPC_OPCODE_BRLOCK
1933 #define PPCPMR  PPC_OPCODE_PMR
1934 #define PPCCHLK PPC_OPCODE_CACHELCK
1935 #define PPCRFMCI        PPC_OPCODE_RFMCI
1936 #define E500MC  PPC_OPCODE_E500MC
1937 #define PPCA2   PPC_OPCODE_A2
1938 #define TITAN   PPC_OPCODE_TITAN
1939 #define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
1940 \f
1941 /* The opcode table.
1942
1943    The format of the opcode table is:
1944
1945    NAME         OPCODE          MASK         FLAGS      {OPERANDS}
1946
1947    NAME is the name of the instruction.
1948    OPCODE is the instruction opcode.
1949    MASK is the opcode mask; this is used to tell the disassembler
1950      which bits in the actual opcode must match OPCODE.
1951    FLAGS are flags indicated what processors support the instruction.
1952    OPERANDS is the list of operands.
1953
1954    The disassembler reads the table in order and prints the first
1955    instruction which matches, so this table is sorted to put more
1956    specific instructions before more general instructions.
1957
1958    This table must be sorted by major opcode.  Please try to keep it
1959    vaguely sorted within major opcode too, except of course where
1960    constrained otherwise by disassembler operation.  */
1961
1962 const struct powerpc_opcode powerpc_opcodes[] = {
1963 {"attn",        X(0,256),       X_MASK,   POWER4|PPCA2, PPC476,         {0}},
1964 {"tdlgti",      OPTO(2,TOLGT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1965 {"tdllti",      OPTO(2,TOLLT),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1966 {"tdeqi",       OPTO(2,TOEQ),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1967 {"tdlgei",      OPTO(2,TOLGE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1968 {"tdlnli",      OPTO(2,TOLNL),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1969 {"tdllei",      OPTO(2,TOLLE),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1970 {"tdlngi",      OPTO(2,TOLNG),  OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1971 {"tdgti",       OPTO(2,TOGT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1972 {"tdgei",       OPTO(2,TOGE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1973 {"tdnli",       OPTO(2,TONL),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1974 {"tdlti",       OPTO(2,TOLT),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1975 {"tdlei",       OPTO(2,TOLE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1976 {"tdngi",       OPTO(2,TONG),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1977 {"tdnei",       OPTO(2,TONE),   OPTO_MASK,   PPC64,     PPCNONE,        {RA, SI}},
1978 {"tdi",         OP(2),          OP_MASK,     PPC64,     PPCNONE,        {TO, RA, SI}},
1979
1980 {"twlgti",      OPTO(3,TOLGT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1981 {"tlgti",       OPTO(3,TOLGT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1982 {"twllti",      OPTO(3,TOLLT),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1983 {"tllti",       OPTO(3,TOLLT),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1984 {"tweqi",       OPTO(3,TOEQ),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1985 {"teqi",        OPTO(3,TOEQ),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1986 {"twlgei",      OPTO(3,TOLGE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1987 {"tlgei",       OPTO(3,TOLGE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1988 {"twlnli",      OPTO(3,TOLNL),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1989 {"tlnli",       OPTO(3,TOLNL),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1990 {"twllei",      OPTO(3,TOLLE),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1991 {"tllei",       OPTO(3,TOLLE),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1992 {"twlngi",      OPTO(3,TOLNG),  OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1993 {"tlngi",       OPTO(3,TOLNG),  OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1994 {"twgti",       OPTO(3,TOGT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1995 {"tgti",        OPTO(3,TOGT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1996 {"twgei",       OPTO(3,TOGE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1997 {"tgei",        OPTO(3,TOGE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
1998 {"twnli",       OPTO(3,TONL),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
1999 {"tnli",        OPTO(3,TONL),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2000 {"twlti",       OPTO(3,TOLT),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2001 {"tlti",        OPTO(3,TOLT),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2002 {"twlei",       OPTO(3,TOLE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2003 {"tlei",        OPTO(3,TOLE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2004 {"twngi",       OPTO(3,TONG),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2005 {"tngi",        OPTO(3,TONG),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2006 {"twnei",       OPTO(3,TONE),   OPTO_MASK,   PPCCOM,    PPCNONE,        {RA, SI}},
2007 {"tnei",        OPTO(3,TONE),   OPTO_MASK,   PWRCOM,    PPCNONE,        {RA, SI}},
2008 {"twi",         OP(3),          OP_MASK,     PPCCOM,    PPCNONE,        {TO, RA, SI}},
2009 {"ti",          OP(3),          OP_MASK,     PWRCOM,    PPCNONE,        {TO, RA, SI}},
2010
2011 {"ps_cmpu0",    X  (4,   0), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2012 {"vaddubm",     VX (4,   0),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2013 {"vmaxub",      VX (4,   2),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2014 {"vrlb",        VX (4,   4),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2015 {"vcmpequb",    VXR(4,   6,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2016 {"vmuloub",     VX (4,   8),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2017 {"vaddfp",      VX (4,  10),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2018 {"psq_lx",      XW (4,   6,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
2019 {"vmrghb",      VX (4,  12),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2020 {"psq_stx",     XW (4,   7,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
2021 {"vpkuhum",     VX (4,  14),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2022 {"mulhhwu",     XRC(4,   8,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2023 {"mulhhwu.",    XRC(4,   8,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2024 {"ps_sum0",     A  (4,  10,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2025 {"ps_sum0.",    A  (4,  10,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2026 {"ps_sum1",     A  (4,  11,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2027 {"ps_sum1.",    A  (4,  11,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2028 {"ps_muls0",    A  (4,  12,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2029 {"machhwu",     XO (4,  12,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2030 {"ps_muls0.",   A  (4,  12,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2031 {"machhwu.",    XO (4,  12,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2032 {"ps_muls1",    A  (4,  13,0),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2033 {"ps_muls1.",   A  (4,  13,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2034 {"ps_madds0",   A  (4,  14,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2035 {"ps_madds0.",  A  (4,  14,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2036 {"ps_madds1",   A  (4,  15,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2037 {"ps_madds1.",  A  (4,  15,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2038 {"vmhaddshs",   VXA(4,  32),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2039 {"vmhraddshs",  VXA(4,  33),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2040 {"vmladduhm",   VXA(4,  34),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2041 {"ps_div",      A  (4,  18,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2042 {"vmsumubm",    VXA(4,  36),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2043 {"ps_div.",     A  (4,  18,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2044 {"vmsummbm",    VXA(4,  37),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2045 {"vmsumuhm",    VXA(4,  38),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2046 {"vmsumuhs",    VXA(4,  39),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2047 {"ps_sub",      A  (4,  20,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2048 {"vmsumshm",    VXA(4,  40),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2049 {"ps_sub.",     A  (4,  20,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2050 {"vmsumshs",    VXA(4,  41),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2051 {"ps_add",      A  (4,  21,0),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2052 {"vsel",        VXA(4,  42),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2053 {"ps_add.",     A  (4,  21,1),  AFRC_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2054 {"vperm",       VXA(4,  43),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, VC}},
2055 {"vsldoi",      VXA(4,  44),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB, SHB}},
2056 {"ps_sel",      A  (4,  23,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2057 {"vmaddfp",     VXA(4,  46),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VC, VB}},
2058 {"ps_sel.",     A  (4,  23,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2059 {"vnmsubfp",    VXA(4,  47),    VXA_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VC, VB}},
2060 {"ps_res",      A  (4,  24,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2061 {"ps_res.",     A  (4,  24,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2062 {"ps_mul",      A  (4,  25,0), AFRB_MASK,    PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2063 {"ps_mul.",     A  (4,  25,1),  AFRB_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRC}},
2064 {"ps_rsqrte",   A  (4,  26,0), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2065 {"ps_rsqrte.",  A  (4,  26,1), AFRAFRC_MASK, PPCPS,     PPCNONE,        {FRT, FRB}},
2066 {"ps_msub",     A  (4,  28,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2067 {"ps_msub.",    A  (4,  28,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2068 {"ps_madd",     A  (4,  29,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2069 {"ps_madd.",    A  (4,  29,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2070 {"ps_nmsub",    A  (4,  30,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2071 {"ps_nmsub.",   A  (4,  30,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2072 {"ps_nmadd",    A  (4,  31,0),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2073 {"ps_nmadd.",   A  (4,  31,1),  A_MASK,      PPCPS,     PPCNONE,        {FRT, FRA, FRC, FRB}},
2074 {"ps_cmpo0",    X  (4,  32), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2075 {"vadduhm",     VX (4,  64),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2076 {"vmaxuh",      VX (4,  66),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2077 {"vrlh",        VX (4,  68),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2078 {"vcmpequh",    VXR(4,  70,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2079 {"vmulouh",     VX (4,  72),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2080 {"vsubfp",      VX (4,  74),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2081 {"psq_lux",     XW (4,  38,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRT,RA,RB,PSWM,PSQM}},
2082 {"vmrghh",      VX (4,  76),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2083 {"psq_stux",    XW (4,  39,0),  XW_MASK,     PPCPS,     PPCNONE,        {FRS,RA,RB,PSWM,PSQM}},
2084 {"vpkuwum",     VX (4,  78),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2085 {"ps_neg",      XRC(4,  40,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2086 {"mulhhw",      XRC(4,  40,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2087 {"ps_neg.",     XRC(4,  40,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2088 {"mulhhw.",     XRC(4,  40,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2089 {"machhw",      XO (4,  44,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2090 {"machhw.",     XO (4,  44,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2091 {"nmachhw",     XO (4,  46,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2092 {"nmachhw.",    XO (4,  46,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2093 {"ps_cmpu1",    X  (4,  64), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2094 {"vadduwm",     VX (4,  128),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2095 {"vmaxuw",      VX (4,  130),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2096 {"vrlw",        VX (4,  132),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2097 {"vcmpequw",    VXR(4,  134,0), VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2098 {"vmrghw",      VX (4,  140),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2099 {"vpkuhus",     VX (4,  142),   VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2100 {"ps_mr",       XRC(4,  72,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2101 {"ps_mr.",      XRC(4,  72,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2102 {"machhwsu",    XO (4,  76,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2103 {"machhwsu.",   XO (4,  76,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2104 {"ps_cmpo1",    X  (4,  96), X_MASK|(3<<21), PPCPS,     PPCNONE,        {BF, FRA, FRB}},
2105 {"vcmpeqfp",    VXR(4, 198,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2106 {"vpkuwus",     VX (4, 206),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2107 {"machhws",     XO (4, 108,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2108 {"machhws.",    XO (4, 108,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2109 {"nmachhws",    XO (4, 110,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2110 {"nmachhws.",   XO (4, 110,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2111 {"vmaxsb",      VX (4, 258),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2112 {"vslb",        VX (4, 260),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2113 {"vmulosb",     VX (4, 264),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2114 {"vrefp",       VX (4, 266),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2115 {"vmrglb",      VX (4, 268),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2116 {"vpkshus",     VX (4, 270),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2117 {"ps_nabs",     XRC(4, 136,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2118 {"mulchwu",     XRC(4, 136,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2119 {"ps_nabs.",    XRC(4, 136,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2120 {"mulchwu.",    XRC(4, 136,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2121 {"macchwu",     XO (4, 140,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2122 {"macchwu.",    XO (4, 140,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2123 {"vmaxsh",      VX (4, 322),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2124 {"vslh",        VX (4, 324),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2125 {"vmulosh",     VX (4, 328),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2126 {"vrsqrtefp",   VX (4, 330),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2127 {"vmrglh",      VX (4, 332),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2128 {"vpkswus",     VX (4, 334),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2129 {"mulchw",      XRC(4, 168,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2130 {"mulchw.",     XRC(4, 168,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2131 {"macchw",      XO (4, 172,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2132 {"macchw.",     XO (4, 172,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2133 {"nmacchw",     XO (4, 174,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2134 {"nmacchw.",    XO (4, 174,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2135 {"vaddcuw",     VX (4, 384),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2136 {"vmaxsw",      VX (4, 386),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2137 {"vslw",        VX (4, 388),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2138 {"vexptefp",    VX (4, 394),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2139 {"vmrglw",      VX (4, 396),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2140 {"vpkshss",     VX (4, 398),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2141 {"macchwsu",    XO (4, 204,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2142 {"macchwsu.",   XO (4, 204,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2143 {"vsl",         VX (4, 452),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2144 {"vcmpgefp",    VXR(4, 454,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2145 {"vlogefp",     VX (4, 458),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2146 {"vpkswss",     VX (4, 462),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2147 {"macchws",     XO (4, 236,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2148 {"macchws.",    XO (4, 236,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2149 {"nmacchws",    XO (4, 238,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2150 {"nmacchws.",   XO (4, 238,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2151 {"evaddw",      VX (4, 512),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2152 {"vaddubs",     VX (4, 512),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2153 {"evaddiw",     VX (4, 514),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, UIMM}},
2154 {"vminub",      VX (4, 514),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2155 {"evsubfw",     VX (4, 516),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2156 {"evsubw",      VX (4, 516),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, RA}},
2157 {"vsrb",        VX (4, 516),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2158 {"evsubifw",    VX (4, 518),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, UIMM, RB}},
2159 {"evsubiw",     VX (4, 518),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB, UIMM}},
2160 {"vcmpgtub",    VXR(4, 518,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2161 {"evabs",       VX (4, 520),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2162 {"vmuleub",     VX (4, 520),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2163 {"evneg",       VX (4, 521),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2164 {"evextsb",     VX (4, 522),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2165 {"vrfin",       VX (4, 522),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2166 {"evextsh",     VX (4, 523),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2167 {"evrndw",      VX (4, 524),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2168 {"vspltb",      VX (4, 524),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2169 {"evcntlzw",    VX (4, 525),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2170 {"evcntlsw",    VX (4, 526),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2171 {"vupkhsb",     VX (4, 526),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2172 {"brinc",       VX (4, 527),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2173 {"ps_abs",      XRC(4, 264,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2174 {"ps_abs.",     XRC(4, 264,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
2175 {"evand",       VX (4, 529),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2176 {"evandc",      VX (4, 530),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2177 {"evxor",       VX (4, 534),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2178 {"evmr",        VX (4, 535),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, BBA}},
2179 {"evor",        VX (4, 535),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2180 {"evnor",       VX (4, 536),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2181 {"evnot",       VX (4, 536),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, BBA}},
2182 {"get",         APU(4, 268,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2183 {"eveqv",       VX (4, 537),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2184 {"evorc",       VX (4, 539),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2185 {"evnand",      VX (4, 542),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2186 {"evsrwu",      VX (4, 544),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2187 {"evsrws",      VX (4, 545),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2188 {"evsrwiu",     VX (4, 546),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2189 {"evsrwis",     VX (4, 547),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2190 {"evslw",       VX (4, 548),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2191 {"evslwi",      VX (4, 550),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2192 {"evrlw",       VX (4, 552),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2193 {"evsplati",    VX (4, 553),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, SIMM}},
2194 {"evrlwi",      VX (4, 554),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, EVUIMM}},
2195 {"evsplatfi",   VX (4, 555),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, SIMM}},
2196 {"evmergehi",   VX (4, 556),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2197 {"evmergelo",   VX (4, 557),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2198 {"evmergehilo", VX (4, 558),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2199 {"evmergelohi", VX (4, 559),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2200 {"evcmpgtu",    VX (4, 560),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2201 {"evcmpgts",    VX (4, 561),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2202 {"evcmpltu",    VX (4, 562),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2203 {"evcmplts",    VX (4, 563),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2204 {"evcmpeq",     VX (4, 564),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2205 {"cget",        APU(4, 284,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2206 {"vadduhs",     VX (4, 576),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2207 {"vminuh",      VX (4, 578),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2208 {"vsrh",        VX (4, 580),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2209 {"vcmpgtuh",    VXR(4, 582,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2210 {"vmuleuh",     VX (4, 584),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2211 {"vrfiz",       VX (4, 586),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2212 {"vsplth",      VX (4, 588),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2213 {"vupkhsh",     VX (4, 590),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2214 {"nget",        APU(4, 300,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2215 {"evsel",       EVSEL(4,79),    EVSEL_MASK,  PPCSPE,    PPCNONE,        {RS, RA, RB, CRFS}},
2216 {"ncget",       APU(4, 316,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
2217 {"evfsadd",     VX (4, 640),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2218 {"vadduws",     VX (4, 640),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2219 {"evfssub",     VX (4, 641),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2220 {"vminuw",      VX (4, 642),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2221 {"evfsabs",     VX (4, 644),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2222 {"vsrw",        VX (4, 644),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2223 {"evfsnabs",    VX (4, 645),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2224 {"evfsneg",     VX (4, 646),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2225 {"vcmpgtuw",    VXR(4, 646,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2226 {"evfsmul",     VX (4, 648),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2227 {"evfsdiv",     VX (4, 649),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2228 {"vrfip",       VX (4, 650),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2229 {"evfscmpgt",   VX (4, 652),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2230 {"vspltw",      VX (4, 652),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2231 {"evfscmplt",   VX (4, 653),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2232 {"evfscmpeq",   VX (4, 654),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2233 {"vupklsb",     VX (4, 654),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2234 {"evfscfui",    VX (4, 656),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2235 {"evfscfsi",    VX (4, 657),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2236 {"evfscfuf",    VX (4, 658),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2237 {"evfscfsf",    VX (4, 659),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2238 {"evfsctui",    VX (4, 660),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2239 {"evfsctsi",    VX (4, 661),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2240 {"evfsctuf",    VX (4, 662),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2241 {"evfsctsf",    VX (4, 663),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2242 {"evfsctuiz",   VX (4, 664),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2243 {"put",         APU(4, 332,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2244 {"evfsctsiz",   VX (4, 666),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RB}},
2245 {"evfststgt",   VX (4, 668),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2246 {"evfststlt",   VX (4, 669),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2247 {"evfststeq",   VX (4, 670),    VX_MASK,     PPCSPE,    PPCNONE,        {CRFD, RA, RB}},
2248 {"cput",        APU(4, 348,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2249 {"efsadd",      VX (4, 704),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2250 {"efssub",      VX (4, 705),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2251 {"efsabs",      VX (4, 708),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2252 {"vsr",         VX (4, 708),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2253 {"efsnabs",     VX (4, 709),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2254 {"efsneg",      VX (4, 710),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2255 {"vcmpgtfp",    VXR(4, 710,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2256 {"efsmul",      VX (4, 712),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2257 {"efsdiv",      VX (4, 713),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2258 {"vrfim",       VX (4, 714),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2259 {"efscmpgt",    VX (4, 716),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2260 {"efscmplt",    VX (4, 717),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2261 {"efscmpeq",    VX (4, 718),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2262 {"vupklsh",     VX (4, 718),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2263 {"efscfd",      VX (4, 719),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2264 {"efscfui",     VX (4, 720),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2265 {"efscfsi",     VX (4, 721),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2266 {"efscfuf",     VX (4, 722),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2267 {"efscfsf",     VX (4, 723),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2268 {"efsctui",     VX (4, 724),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2269 {"efsctsi",     VX (4, 725),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2270 {"efsctuf",     VX (4, 726),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2271 {"efsctsf",     VX (4, 727),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2272 {"efsctuiz",    VX (4, 728),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2273 {"nput",        APU(4, 364,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2274 {"efsctsiz",    VX (4, 730),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2275 {"efststgt",    VX (4, 732),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2276 {"efststlt",    VX (4, 733),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2277 {"efststeq",    VX (4, 734),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2278 {"efdadd",      VX (4, 736),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2279 {"efdsub",      VX (4, 737),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2280 {"efdcfuid",    VX (4, 738),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2281 {"efdcfsid",    VX (4, 739),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2282 {"efdabs",      VX (4, 740),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2283 {"efdnabs",     VX (4, 741),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2284 {"efdneg",      VX (4, 742),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA}},
2285 {"efdmul",      VX (4, 744),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2286 {"efddiv",      VX (4, 745),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RA, RB}},
2287 {"efdctuidz",   VX (4, 746),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2288 {"efdctsidz",   VX (4, 747),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2289 {"efdcmpgt",    VX (4, 748),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2290 {"efdcmplt",    VX (4, 749),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2291 {"efdcmpeq",    VX (4, 750),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2292 {"efdcfs",      VX (4, 751),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2293 {"efdcfui",     VX (4, 752),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2294 {"efdcfsi",     VX (4, 753),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2295 {"efdcfuf",     VX (4, 754),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2296 {"efdcfsf",     VX (4, 755),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2297 {"efdctui",     VX (4, 756),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2298 {"efdctsi",     VX (4, 757),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2299 {"efdctuf",     VX (4, 758),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2300 {"efdctsf",     VX (4, 759),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2301 {"efdctuiz",    VX (4, 760),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2302 {"ncput",       APU(4, 380,0),  APU_RT_MASK, PPC405,    PPCNONE,        {RA, FSL}},
2303 {"efdctsiz",    VX (4, 762),    VX_MASK,     PPCEFS,    PPCNONE,        {RS, RB}},
2304 {"efdtstgt",    VX (4, 764),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2305 {"efdtstlt",    VX (4, 765),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2306 {"efdtsteq",    VX (4, 766),    VX_MASK,     PPCEFS,    PPCNONE,        {CRFD, RA, RB}},
2307 {"evlddx",      VX (4, 768),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2308 {"vaddsbs",     VX (4, 768),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2309 {"evldd",       VX (4, 769),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2310 {"evldwx",      VX (4, 770),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2311 {"vminsb",      VX (4, 770),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2312 {"evldw",       VX (4, 771),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2313 {"evldhx",      VX (4, 772),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2314 {"vsrab",       VX (4, 772),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2315 {"evldh",       VX (4, 773),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2316 {"vcmpgtsb",    VXR(4, 774,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2317 {"evlhhesplatx",VX (4, 776),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2318 {"vmulesb",     VX (4, 776),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2319 {"evlhhesplat", VX (4, 777),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_2, RA}},
2320 {"vcfux",       VX (4, 778),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2321 {"evlhhousplatx",VX(4, 780),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2322 {"vspltisb",    VX (4, 780),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, SIMM}},
2323 {"evlhhousplat",VX (4, 781),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_2, RA}},
2324 {"evlhhossplatx",VX(4, 782),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2325 {"vpkpx",       VX (4, 782),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2326 {"evlhhossplat",VX (4, 783),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_2, RA}},
2327 {"mullhwu",     XRC(4, 392,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2328 {"evlwhex",     VX (4, 784),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2329 {"mullhwu.",    XRC(4, 392,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2330 {"evlwhe",      VX (4, 785),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2331 {"evlwhoux",    VX (4, 788),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2332 {"evlwhou",     VX (4, 789),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2333 {"evlwhosx",    VX (4, 790),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2334 {"evlwhos",     VX (4, 791),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2335 {"maclhwu",     XO (4, 396,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2336 {"evlwwsplatx", VX (4, 792),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2337 {"maclhwu.",    XO (4, 396,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2338 {"evlwwsplat",  VX (4, 793),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2339 {"evlwhsplatx", VX (4, 796),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2340 {"evlwhsplat",  VX (4, 797),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2341 {"evstddx",     VX (4, 800),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2342 {"evstdd",      VX (4, 801),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2343 {"evstdwx",     VX (4, 802),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2344 {"evstdw",      VX (4, 803),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2345 {"evstdhx",     VX (4, 804),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2346 {"evstdh",      VX (4, 805),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_8, RA}},
2347 {"evstwhex",    VX (4, 816),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2348 {"evstwhe",     VX (4, 817),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2349 {"evstwhox",    VX (4, 820),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2350 {"evstwho",     VX (4, 821),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2351 {"evstwwex",    VX (4, 824),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2352 {"evstwwe",     VX (4, 825),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2353 {"evstwwox",    VX (4, 828),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2354 {"evstwwo",     VX (4, 829),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, EVUIMM_4, RA}},
2355 {"vaddshs",     VX (4, 832),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2356 {"vminsh",      VX (4, 834),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2357 {"vsrah",       VX (4, 836),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2358 {"vcmpgtsh",    VXR(4, 838,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2359 {"vmulesh",     VX (4, 840),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2360 {"vcfsx",       VX (4, 842),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2361 {"vspltish",    VX (4, 844),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, SIMM}},
2362 {"vupkhpx",     VX (4, 846),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2363 {"mullhw",      XRC(4, 424,0),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2364 {"mullhw.",     XRC(4, 424,1),  X_MASK,      MULHW,     PPCNONE,        {RT, RA, RB}},
2365 {"maclhw",      XO (4, 428,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2366 {"maclhw.",     XO (4, 428,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2367 {"nmaclhw",     XO (4, 430,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2368 {"nmaclhw.",    XO (4, 430,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2369 {"vaddsws",     VX (4, 896),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2370 {"vminsw",      VX (4, 898),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2371 {"vsraw",       VX (4, 900),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2372 {"vcmpgtsw",    VXR(4, 902,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2373 {"vctuxs",      VX (4, 906),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2374 {"vspltisw",    VX (4, 908),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, SIMM}},
2375 {"maclhwsu",    XO (4, 460,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2376 {"maclhwsu.",   XO (4, 460,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2377 {"vcmpbfp",     VXR(4, 966,0),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2378 {"vctsxs",      VX (4, 970),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB, UIMM}},
2379 {"vupklpx",     VX (4, 974),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VB}},
2380 {"maclhws",     XO (4, 492,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2381 {"maclhws.",    XO (4, 492,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2382 {"nmaclhws",    XO (4, 494,0,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2383 {"nmaclhws.",   XO (4, 494,0,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2384 {"vsububm",     VX (4,1024),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2385 {"vavgub",      VX (4,1026),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2386 {"evmhessf",    VX (4,1027),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2387 {"vand",        VX (4,1028),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2388 {"vcmpequb.",   VXR(4,   6,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2389 {"udi0fcm.",    APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2390 {"udi0fcm",     APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2391 {"evmhossf",    VX (4,1031),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2392 {"evmheumi",    VX (4,1032),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2393 {"evmhesmi",    VX (4,1033),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2394 {"vmaxfp",      VX (4,1034),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2395 {"evmhesmf",    VX (4,1035),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2396 {"evmhoumi",    VX (4,1036),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2397 {"vslo",        VX (4,1036),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2398 {"evmhosmi",    VX (4,1037),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2399 {"evmhosmf",    VX (4,1039),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2400 {"machhwuo",    XO (4,  12,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2401 {"machhwuo.",   XO (4,  12,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2402 {"ps_merge00",  XOPS(4,528,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2403 {"ps_merge00.", XOPS(4,528,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2404 {"evmhessfa",   VX (4,1059),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2405 {"evmhossfa",   VX (4,1063),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2406 {"evmheumia",   VX (4,1064),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2407 {"evmhesmia",   VX (4,1065),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2408 {"evmhesmfa",   VX (4,1067),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2409 {"evmhoumia",   VX (4,1068),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2410 {"evmhosmia",   VX (4,1069),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2411 {"evmhosmfa",   VX (4,1071),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2412 {"vsubuhm",     VX (4,1088),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2413 {"vavguh",      VX (4,1090),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2414 {"vandc",       VX (4,1092),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2415 {"vcmpequh.",   VXR(4,  70,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2416 {"udi1fcm.",    APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2417 {"udi1fcm",     APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2418 {"evmwhssf",    VX (4,1095),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2419 {"evmwlumi",    VX (4,1096),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2420 {"vminfp",      VX (4,1098),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2421 {"evmwhumi",    VX (4,1100),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2422 {"vsro",        VX (4,1100),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2423 {"evmwhsmi",    VX (4,1101),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2424 {"evmwhsmf",    VX (4,1103),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2425 {"evmwssf",     VX (4,1107),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2426 {"machhwo",     XO (4,  44,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2427 {"evmwumi",     VX (4,1112),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2428 {"machhwo.",    XO (4,  44,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2429 {"evmwsmi",     VX (4,1113),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2430 {"evmwsmf",     VX (4,1115),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2431 {"nmachhwo",    XO (4,  46,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2432 {"nmachhwo.",   XO (4,  46,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2433 {"ps_merge01",  XOPS(4,560,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2434 {"ps_merge01.", XOPS(4,560,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2435 {"evmwhssfa",   VX (4,1127),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2436 {"evmwlumia",   VX (4,1128),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2437 {"evmwhumia",   VX (4,1132),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2438 {"evmwhsmia",   VX (4,1133),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2439 {"evmwhsmfa",   VX (4,1135),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2440 {"evmwssfa",    VX (4,1139),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2441 {"evmwumia",    VX (4,1144),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2442 {"evmwsmia",    VX (4,1145),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2443 {"evmwsmfa",    VX (4,1147),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2444 {"vsubuwm",     VX (4,1152),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2445 {"vavguw",      VX (4,1154),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2446 {"vor",         VX (4,1156),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2447 {"vcmpequw.",   VXR(4, 134,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2448 {"udi2fcm.",    APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2449 {"udi2fcm",     APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2450 {"machhwsuo",   XO (4,  76,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2451 {"machhwsuo.",  XO (4,  76,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2452 {"ps_merge10",  XOPS(4,592,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2453 {"ps_merge10.", XOPS(4,592,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2454 {"evaddusiaaw", VX (4,1216),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2455 {"evaddssiaaw", VX (4,1217),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2456 {"evsubfusiaaw",VX (4,1218),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2457 {"evsubfssiaaw",VX (4,1219),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2458 {"evmra",       VX (4,1220),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2459 {"vxor",        VX (4,1220),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2460 {"evdivws",     VX (4,1222),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2461 {"vcmpeqfp.",   VXR(4, 198,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2462 {"udi3fcm.",    APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2463 {"udi3fcm",     APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2464 {"evdivwu",     VX (4,1223),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2465 {"evaddumiaaw", VX (4,1224),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2466 {"evaddsmiaaw", VX (4,1225),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2467 {"evsubfumiaaw",VX (4,1226),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2468 {"evsubfsmiaaw",VX (4,1227),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA}},
2469 {"machhwso",    XO (4, 108,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2470 {"machhwso.",   XO (4, 108,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2471 {"nmachhwso",   XO (4, 110,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2472 {"nmachhwso.",  XO (4, 110,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2473 {"ps_merge11",  XOPS(4,624,0),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2474 {"ps_merge11.", XOPS(4,624,1),  XOPS_MASK,   PPCPS,     PPCNONE,        {FRT, FRA, FRB}},
2475 {"evmheusiaaw", VX (4,1280),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2476 {"evmhessiaaw", VX (4,1281),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2477 {"vavgsb",      VX (4,1282),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2478 {"evmhessfaaw", VX (4,1283),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2479 {"evmhousiaaw", VX (4,1284),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2480 {"vnor",        VX (4,1284),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2481 {"evmhossiaaw", VX (4,1285),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2482 {"udi4fcm.",    APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2483 {"udi4fcm",     APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2484 {"evmhossfaaw", VX (4,1287),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2485 {"evmheumiaaw", VX (4,1288),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2486 {"evmhesmiaaw", VX (4,1289),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2487 {"evmhesmfaaw", VX (4,1291),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2488 {"evmhoumiaaw", VX (4,1292),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2489 {"evmhosmiaaw", VX (4,1293),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2490 {"evmhosmfaaw", VX (4,1295),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2491 {"macchwuo",    XO (4, 140,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2492 {"macchwuo.",   XO (4, 140,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2493 {"evmhegumiaa", VX (4,1320),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2494 {"evmhegsmiaa", VX (4,1321),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2495 {"evmhegsmfaa", VX (4,1323),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2496 {"evmhogumiaa", VX (4,1324),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2497 {"evmhogsmiaa", VX (4,1325),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2498 {"evmhogsmfaa", VX (4,1327),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2499 {"evmwlusiaaw", VX (4,1344),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2500 {"evmwlssiaaw", VX (4,1345),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2501 {"vavgsh",      VX (4,1346),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2502 {"udi5fcm.",    APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2503 {"udi5fcm",     APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2504 {"evmwlumiaaw", VX (4,1352),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2505 {"evmwlsmiaaw", VX (4,1353),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2506 {"evmwssfaa",   VX (4,1363),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2507 {"macchwo",     XO (4, 172,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2508 {"evmwumiaa",   VX (4,1368),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2509 {"macchwo.",    XO (4, 172,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2510 {"evmwsmiaa",   VX (4,1369),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2511 {"evmwsmfaa",   VX (4,1371),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2512 {"nmacchwo",    XO (4, 174,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2513 {"nmacchwo.",   XO (4, 174,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2514 {"evmheusianw", VX (4,1408),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2515 {"vsubcuw",     VX (4,1408),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2516 {"evmhessianw", VX (4,1409),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2517 {"vavgsw",      VX (4,1410),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2518 {"evmhessfanw", VX (4,1411),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2519 {"evmhousianw", VX (4,1412),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2520 {"evmhossianw", VX (4,1413),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2521 {"udi6fcm.",    APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2522 {"udi6fcm",     APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2523 {"evmhossfanw", VX (4,1415),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2524 {"evmheumianw", VX (4,1416),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2525 {"evmhesmianw", VX (4,1417),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2526 {"evmhesmfanw", VX (4,1419),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2527 {"evmhoumianw", VX (4,1420),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2528 {"evmhosmianw", VX (4,1421),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2529 {"evmhosmfanw", VX (4,1423),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2530 {"macchwsuo",   XO (4, 204,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2531 {"macchwsuo.",  XO (4, 204,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2532 {"evmhegumian", VX (4,1448),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2533 {"evmhegsmian", VX (4,1449),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2534 {"evmhegsmfan", VX (4,1451),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2535 {"evmhogumian", VX (4,1452),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2536 {"evmhogsmian", VX (4,1453),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2537 {"evmhogsmfan", VX (4,1455),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2538 {"evmwlusianw", VX (4,1472),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2539 {"evmwlssianw", VX (4,1473),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2540 {"vcmpgefp.",   VXR(4, 454,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2541 {"udi7fcm.",    APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2542 {"udi7fcm",     APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476,         {URT, URA, URB}},
2543 {"evmwlumianw", VX (4,1480),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2544 {"evmwlsmianw", VX (4,1481),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2545 {"evmwssfan",   VX (4,1491),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2546 {"macchwso",    XO (4, 236,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2547 {"evmwumian",   VX (4,1496),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2548 {"macchwso.",   XO (4, 236,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2549 {"evmwsmian",   VX (4,1497),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2550 {"evmwsmfan",   VX (4,1499),    VX_MASK,     PPCSPE,    PPCNONE,        {RS, RA, RB}},
2551 {"nmacchwso",   XO (4, 238,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2552 {"nmacchwso.",  XO (4, 238,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2553 {"vsububs",     VX (4,1536),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2554 {"mfvscr",      VX (4,1540),    VX_MASK,     PPCVEC,    PPCNONE,        {VD}},
2555 {"vcmpgtub.",   VXR(4, 518,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2556 {"udi8fcm.",    APU(4, 771,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2557 {"udi8fcm",     APU(4, 771,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2558 {"vsum4ubs",    VX (4,1544),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2559 {"vsubuhs",     VX (4,1600),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2560 {"mtvscr",      VX (4,1604),    VX_MASK,     PPCVEC,    PPCNONE,        {VB}},
2561 {"vcmpgtuh.",   VXR(4, 582,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2562 {"vsum4shs",    VX (4,1608),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2563 {"udi9fcm.",    APU(4, 804,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2564 {"udi9fcm",     APU(4, 804,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2565 {"vsubuws",     VX (4,1664),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2566 {"vcmpgtuw.",   VXR(4, 646,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2567 {"udi10fcm.",   APU(4, 835,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2568 {"udi10fcm",    APU(4, 835,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2569 {"vsum2sws",    VX (4,1672),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2570 {"vcmpgtfp.",   VXR(4, 710,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2571 {"udi11fcm.",   APU(4, 867,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2572 {"udi11fcm",    APU(4, 867,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2573 {"vsubsbs",     VX (4,1792),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2574 {"vcmpgtsb.",   VXR(4, 774,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2575 {"udi12fcm.",   APU(4, 899,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2576 {"udi12fcm",    APU(4, 899,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2577 {"vsum4sbs",    VX (4,1800),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2578 {"maclhwuo",    XO (4, 396,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2579 {"maclhwuo.",   XO (4, 396,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2580 {"vsubshs",     VX (4,1856),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2581 {"vcmpgtsh.",   VXR(4, 838,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2582 {"udi13fcm.",   APU(4, 931,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2583 {"udi13fcm",    APU(4, 931,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2584 {"maclhwo",     XO (4, 428,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2585 {"maclhwo.",    XO (4, 428,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2586 {"nmaclhwo",    XO (4, 430,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2587 {"nmaclhwo.",   XO (4, 430,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2588 {"vsubsws",     VX (4,1920),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2589 {"vcmpgtsw.",   VXR(4, 902,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2590 {"udi14fcm.",   APU(4, 963,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2591 {"udi14fcm",    APU(4, 963,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2592 {"vsumsws",     VX (4,1928),    VX_MASK,     PPCVEC,    PPCNONE,        {VD, VA, VB}},
2593 {"maclhwsuo",   XO (4, 460,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2594 {"maclhwsuo.",  XO (4, 460,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2595 {"vcmpbfp.",    VXR(4, 966,1),  VXR_MASK,    PPCVEC,    PPCNONE,        {VD, VA, VB}},
2596 {"udi15fcm.",   APU(4, 995,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2597 {"udi15fcm",    APU(4, 995,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
2598 {"maclhwso",    XO (4, 492,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2599 {"maclhwso.",   XO (4, 492,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2600 {"nmaclhwso",   XO (4, 494,1,0),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2601 {"nmaclhwso.",  XO (4, 494,1,1),XO_MASK,     MULHW,     PPCNONE,        {RT, RA, RB}},
2602 {"dcbz_l",      X  (4,1014),    XRT_MASK,    PPCPS,     PPCNONE,        {RA, RB}},
2603
2604 {"mulli",       OP(7),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2605 {"muli",        OP(7),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2606
2607 {"subfic",      OP(8),          OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2608 {"sfi",         OP(8),          OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2609
2610 {"dozi",        OP(9),          OP_MASK,     M601,      PPCNONE,        {RT, RA, SI}},
2611
2612 {"cmplwi",      OPL(10,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, UI}},
2613 {"cmpldi",      OPL(10,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, UI}},
2614 {"cmpli",       OP(10),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, UI}},
2615 {"cmpli",       OP(10),         OP_MASK,     PWRCOM,    PPCNONE,        {BF, RA, UI}},
2616
2617 {"cmpwi",       OPL(11,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, SI}},
2618 {"cmpdi",       OPL(11,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, SI}},
2619 {"cmpi",        OP(11),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, SI}},
2620 {"cmpi",        OP(11),         OP_MASK,     PWRCOM,    PPCNONE,        {BF, RA, SI}},
2621
2622 {"addic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2623 {"ai",          OP(12),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2624 {"subic",       OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
2625
2626 {"addic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
2627 {"ai.",         OP(13),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
2628 {"subic.",      OP(13),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, NSI}},
2629
2630 {"li",          OP(14),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SI}},
2631 {"lil",         OP(14),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SI}},
2632 {"addi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SI}},
2633 {"cal",         OP(14),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
2634 {"subi",        OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
2635 {"la",          OP(14),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
2636
2637 {"lis",         OP(15),         DRA_MASK,    PPCCOM,    PPCNONE,        {RT, SISIGNOPT}},
2638 {"liu",         OP(15),         DRA_MASK,    PWRCOM,    PPCNONE,        {RT, SISIGNOPT}},
2639 {"addis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
2640 {"cau",         OP(15),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA0, SISIGNOPT}},
2641 {"subis",       OP(15),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA0, NSI}},
2642
2643 {"bdnz-",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2644 {"bdnz+",    BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2645 {"bdnz",     BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
2646 {"bdn",      BBO(16,BODNZ,0,0),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
2647 {"bdnzl-",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2648 {"bdnzl+",   BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2649 {"bdnzl",    BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BD}},
2650 {"bdnl",     BBO(16,BODNZ,0,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BD}},
2651 {"bdnza-",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2652 {"bdnza+",   BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2653 {"bdnza",    BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
2654 {"bdna",     BBO(16,BODNZ,1,0),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
2655 {"bdnzla-",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2656 {"bdnzla+",  BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2657 {"bdnzla",   BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDA}},
2658 {"bdnla",    BBO(16,BODNZ,1,1),         BBOATBI_MASK,  PWRCOM,   PPCNONE,       {BDA}},
2659 {"bdz-",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2660 {"bdz+",     BBO(16,BODZ,0,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2661 {"bdz",      BBO(16,BODZ,0,0),          BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
2662 {"bdzl-",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDM}},
2663 {"bdzl+",    BBO(16,BODZ,0,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDP}},
2664 {"bdzl",     BBO(16,BODZ,0,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BD}},
2665 {"bdza-",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2666 {"bdza+",    BBO(16,BODZ,1,0),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2667 {"bdza",     BBO(16,BODZ,1,0),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
2668 {"bdzla-",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDMA}},
2669 {"bdzla+",   BBO(16,BODZ,1,1),          BBOATBI_MASK,  PPCCOM,   PPCNONE,       {BDPA}},
2670 {"bdzla",    BBO(16,BODZ,1,1),          BBOATBI_MASK,  COM,      PPCNONE,       {BDA}},
2671
2672 {"bge-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2673 {"bge+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2674 {"bge",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2675 {"bnl-",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2676 {"bnl+",     BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2677 {"bnl",      BBOCB(16,BOF,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2678 {"bgel-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2679 {"bgel+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2680 {"bgel",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2681 {"bnll-",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2682 {"bnll+",    BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2683 {"bnll",     BBOCB(16,BOF,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2684 {"bgea-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2685 {"bgea+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2686 {"bgea",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2687 {"bnla-",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2688 {"bnla+",    BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2689 {"bnla",     BBOCB(16,BOF,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2690 {"bgela-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2691 {"bgela+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2692 {"bgela",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2693 {"bnlla-",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2694 {"bnlla+",   BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2695 {"bnlla",    BBOCB(16,BOF,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2696 {"ble-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2697 {"ble+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2698 {"ble",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2699 {"bng-",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2700 {"bng+",     BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2701 {"bng",      BBOCB(16,BOF,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2702 {"blel-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2703 {"blel+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2704 {"blel",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2705 {"bngl-",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2706 {"bngl+",    BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2707 {"bngl",     BBOCB(16,BOF,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2708 {"blea-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2709 {"blea+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2710 {"blea",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2711 {"bnga-",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2712 {"bnga+",    BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2713 {"bnga",     BBOCB(16,BOF,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2714 {"blela-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2715 {"blela+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2716 {"blela",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2717 {"bngla-",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2718 {"bngla+",   BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2719 {"bngla",    BBOCB(16,BOF,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2720 {"bne-",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2721 {"bne+",     BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2722 {"bne",      BBOCB(16,BOF,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2723 {"bnel-",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2724 {"bnel+",    BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2725 {"bnel",     BBOCB(16,BOF,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2726 {"bnea-",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2727 {"bnea+",    BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2728 {"bnea",     BBOCB(16,BOF,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2729 {"bnela-",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2730 {"bnela+",   BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2731 {"bnela",    BBOCB(16,BOF,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2732 {"bns-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2733 {"bns+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2734 {"bns",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2735 {"bnu-",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2736 {"bnu+",     BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2737 {"bnu",      BBOCB(16,BOF,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2738 {"bnsl-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2739 {"bnsl+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2740 {"bnsl",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2741 {"bnul-",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2742 {"bnul+",    BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2743 {"bnul",     BBOCB(16,BOF,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2744 {"bnsa-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2745 {"bnsa+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2746 {"bnsa",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2747 {"bnua-",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2748 {"bnua+",    BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2749 {"bnua",     BBOCB(16,BOF,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2750 {"bnsla-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2751 {"bnsla+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2752 {"bnsla",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2753 {"bnula-",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2754 {"bnula+",   BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2755 {"bnula",    BBOCB(16,BOF,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2756
2757 {"blt-",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2758 {"blt+",     BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2759 {"blt",      BBOCB(16,BOT,CBLT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2760 {"bltl-",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2761 {"bltl+",    BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2762 {"bltl",     BBOCB(16,BOT,CBLT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2763 {"blta-",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2764 {"blta+",    BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2765 {"blta",     BBOCB(16,BOT,CBLT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2766 {"bltla-",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2767 {"bltla+",   BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2768 {"bltla",    BBOCB(16,BOT,CBLT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2769 {"bgt-",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2770 {"bgt+",     BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2771 {"bgt",      BBOCB(16,BOT,CBGT,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2772 {"bgtl-",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2773 {"bgtl+",    BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2774 {"bgtl",     BBOCB(16,BOT,CBGT,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2775 {"bgta-",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2776 {"bgta+",    BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2777 {"bgta",     BBOCB(16,BOT,CBGT,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2778 {"bgtla-",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2779 {"bgtla+",   BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2780 {"bgtla",    BBOCB(16,BOT,CBGT,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2781 {"beq-",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2782 {"beq+",     BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2783 {"beq",      BBOCB(16,BOT,CBEQ,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2784 {"beql-",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2785 {"beql+",    BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2786 {"beql",     BBOCB(16,BOT,CBEQ,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2787 {"beqa-",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2788 {"beqa+",    BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2789 {"beqa",     BBOCB(16,BOT,CBEQ,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2790 {"beqla-",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2791 {"beqla+",   BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2792 {"beqla",    BBOCB(16,BOT,CBEQ,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2793 {"bso-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2794 {"bso+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2795 {"bso",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2796 {"bun-",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2797 {"bun+",     BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2798 {"bun",      BBOCB(16,BOT,CBSO,0,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2799 {"bsol-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2800 {"bsol+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2801 {"bsol",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BD}},
2802 {"bunl-",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDM}},
2803 {"bunl+",    BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDP}},
2804 {"bunl",     BBOCB(16,BOT,CBSO,0,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BD}},
2805 {"bsoa-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2806 {"bsoa+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2807 {"bsoa",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2808 {"buna-",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2809 {"buna+",    BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2810 {"buna",     BBOCB(16,BOT,CBSO,1,0),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2811 {"bsola-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2812 {"bsola+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2813 {"bsola",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  COM,      PPCNONE,       {CR, BDA}},
2814 {"bunla-",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDMA}},
2815 {"bunla+",   BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDPA}},
2816 {"bunla",    BBOCB(16,BOT,CBSO,1,1),    BBOATCB_MASK,  PPCCOM,   PPCNONE,       {CR, BDA}},
2817
2818 {"bdnzf-",   BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2819 {"bdnzf+",   BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2820 {"bdnzf",    BBO(16,BODNZF,0,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2821 {"bdnzfl-",  BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2822 {"bdnzfl+",  BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2823 {"bdnzfl",   BBO(16,BODNZF,0,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2824 {"bdnzfa-",  BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2825 {"bdnzfa+",  BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2826 {"bdnzfa",   BBO(16,BODNZF,1,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2827 {"bdnzfla-", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2828 {"bdnzfla+", BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2829 {"bdnzfla",  BBO(16,BODNZF,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2830 {"bdzf-",    BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2831 {"bdzf+",    BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2832 {"bdzf",     BBO(16,BODZF,0,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2833 {"bdzfl-",   BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2834 {"bdzfl+",   BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2835 {"bdzfl",    BBO(16,BODZF,0,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2836 {"bdzfa-",   BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2837 {"bdzfa+",   BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2838 {"bdzfa",    BBO(16,BODZF,1,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2839 {"bdzfla-",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2840 {"bdzfla+",  BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2841 {"bdzfla",   BBO(16,BODZF,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2842
2843 {"bf-",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2844 {"bf+",      BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2845 {"bf",       BBO(16,BOF,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2846 {"bbf",      BBO(16,BOF,0,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2847 {"bfl-",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2848 {"bfl+",     BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2849 {"bfl",      BBO(16,BOF,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2850 {"bbfl",     BBO(16,BOF,0,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2851 {"bfa-",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2852 {"bfa+",     BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2853 {"bfa",      BBO(16,BOF,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2854 {"bbfa",     BBO(16,BOF,1,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2855 {"bfla-",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2856 {"bfla+",    BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2857 {"bfla",     BBO(16,BOF,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2858 {"bbfla",    BBO(16,BOF,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2859
2860 {"bdnzt-",   BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2861 {"bdnzt+",   BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2862 {"bdnzt",    BBO(16,BODNZT,0,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2863 {"bdnztl-",  BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2864 {"bdnztl+",  BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2865 {"bdnztl",   BBO(16,BODNZT,0,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2866 {"bdnzta-",  BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2867 {"bdnzta+",  BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2868 {"bdnzta",   BBO(16,BODNZT,1,0),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2869 {"bdnztla-", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2870 {"bdnztla+", BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2871 {"bdnztla",  BBO(16,BODNZT,1,1),        BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2872 {"bdzt-",    BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2873 {"bdzt+",    BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2874 {"bdzt",     BBO(16,BODZT,0,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2875 {"bdztl-",   BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDM}},
2876 {"bdztl+",   BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDP}},
2877 {"bdztl",    BBO(16,BODZT,0,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BD}},
2878 {"bdzta-",   BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2879 {"bdzta+",   BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2880 {"bdzta",    BBO(16,BODZT,1,0),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2881 {"bdztla-",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDMA}},
2882 {"bdztla+",  BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   POWER4,        {BI, BDPA}},
2883 {"bdztla",   BBO(16,BODZT,1,1),         BBOY_MASK,     PPCCOM,   PPCNONE,       {BI, BDA}},
2884
2885 {"bt-",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2886 {"bt+",      BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2887 {"bt",       BBO(16,BOT,0,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2888 {"bbt",      BBO(16,BOT,0,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2889 {"btl-",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDM}},
2890 {"btl+",     BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDP}},
2891 {"btl",      BBO(16,BOT,0,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BD}},
2892 {"bbtl",     BBO(16,BOT,0,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BD}},
2893 {"bta-",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2894 {"bta+",     BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2895 {"bta",      BBO(16,BOT,1,0),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2896 {"bbta",     BBO(16,BOT,1,0),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2897 {"btla-",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDMA}},
2898 {"btla+",    BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDPA}},
2899 {"btla",     BBO(16,BOT,1,1),           BBOAT_MASK,    PPCCOM,   PPCNONE,       {BI, BDA}},
2900 {"bbtla",    BBO(16,BOT,1,1),           BBOAT_MASK,    PWRCOM,   PPCNONE,       {BI, BDA}},
2901
2902 {"bc-",         B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
2903 {"bc+",         B(16,0,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
2904 {"bc",          B(16,0,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
2905 {"bcl-",        B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDM}},
2906 {"bcl+",        B(16,0,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDP}},
2907 {"bcl",         B(16,0,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BD}},
2908 {"bca-",        B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
2909 {"bca+",        B(16,1,0),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
2910 {"bca",         B(16,1,0),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
2911 {"bcla-",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDMA}},
2912 {"bcla+",       B(16,1,1),      B_MASK,      PPCCOM,    PPCNONE,        {BOE, BI, BDPA}},
2913 {"bcla",        B(16,1,1),      B_MASK,      COM,       PPCNONE,        {BO, BI, BDA}},
2914
2915 {"svc",         SC(17,0,0),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
2916 {"svcl",        SC(17,0,1),     SC_MASK,     POWER,     PPCNONE,        {SVC_LEV, FL1, FL2}},
2917 {"sc",          SC(17,1,0),     SC_MASK,     PPC,       PPCNONE,        {LEV}},
2918 {"svca",        SC(17,1,0),     SC_MASK,     PWRCOM,    PPCNONE,        {SV}},
2919 {"svcla",       SC(17,1,1),     SC_MASK,     POWER,     PPCNONE,        {SV}},
2920
2921 {"b",           B(18,0,0),      B_MASK,      COM,       PPCNONE,        {LI}},
2922 {"bl",          B(18,0,1),      B_MASK,      COM,       PPCNONE,        {LI}},
2923 {"ba",          B(18,1,0),      B_MASK,      COM,       PPCNONE,        {LIA}},
2924 {"bla",         B(18,1,1),      B_MASK,      COM,       PPCNONE,        {LIA}},
2925
2926 {"mcrf",      XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
2927
2928 {"bdnzlr",   XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2929 {"bdnzlr-",  XLO(19,BODNZ,16,0),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2930 {"bdnzlrl",  XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2931 {"bdnzlrl-", XLO(19,BODNZ,16,1),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2932 {"bdnzlr+",  XLO(19,BODNZP,16,0),       XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2933 {"bdnzlrl+", XLO(19,BODNZP,16,1),       XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2934 {"bdzlr",    XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2935 {"bdzlr-",   XLO(19,BODZ,16,0),         XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2936 {"bdzlrl",   XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2937 {"bdzlrl-",  XLO(19,BODZ,16,1),         XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2938 {"bdzlr+",   XLO(19,BODZP,16,0),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2939 {"bdzlrl+",  XLO(19,BODZP,16,1),        XLBOBIBB_MASK, PPCCOM,   POWER4,        {0}},
2940 {"blr",      XLO(19,BOU,16,0),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2941 {"br",       XLO(19,BOU,16,0),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
2942 {"blrl",     XLO(19,BOU,16,1),          XLBOBIBB_MASK, PPCCOM,   PPCNONE,       {0}},
2943 {"brl",      XLO(19,BOU,16,1),          XLBOBIBB_MASK, PWRCOM,   PPCNONE,       {0}},
2944 {"bdnzlr-",  XLO(19,BODNZM4,16,0),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2945 {"bdnzlrl-", XLO(19,BODNZM4,16,1),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2946 {"bdnzlr+",  XLO(19,BODNZP4,16,0),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2947 {"bdnzlrl+", XLO(19,BODNZP4,16,1),      XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2948 {"bdzlr-",   XLO(19,BODZM4,16,0),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2949 {"bdzlrl-",  XLO(19,BODZM4,16,1),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2950 {"bdzlr+",   XLO(19,BODZP4,16,0),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2951 {"bdzlrl+",  XLO(19,BODZP4,16,1),       XLBOBIBB_MASK, POWER4,   PPCNONE,       {0}},
2952
2953 {"bgelr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2954 {"bgelr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2955 {"bger",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2956 {"bnllr",    XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2957 {"bnllr-",   XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2958 {"bnlr",     XLOCB(19,BOF,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2959 {"bgelrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2960 {"bgelrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2961 {"bgerl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2962 {"bnllrl",   XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2963 {"bnllrl-",  XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2964 {"bnlrl",    XLOCB(19,BOF,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2965 {"blelr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2966 {"blelr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2967 {"bler",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2968 {"bnglr",    XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2969 {"bnglr-",   XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2970 {"bngr",     XLOCB(19,BOF,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2971 {"blelrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2972 {"blelrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2973 {"blerl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2974 {"bnglrl",   XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2975 {"bnglrl-",  XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2976 {"bngrl",    XLOCB(19,BOF,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2977 {"bnelr",    XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2978 {"bnelr-",   XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2979 {"bner",     XLOCB(19,BOF,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2980 {"bnelrl",   XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2981 {"bnelrl-",  XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2982 {"bnerl",    XLOCB(19,BOF,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2983 {"bnslr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2984 {"bnslr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2985 {"bnsr",     XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2986 {"bnulr",    XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2987 {"bnulr-",   XLOCB(19,BOF,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2988 {"bnslrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2989 {"bnslrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2990 {"bnsrl",    XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
2991 {"bnulrl",   XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
2992 {"bnulrl-",  XLOCB(19,BOF,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2993 {"bgelr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2994 {"bnllr+",   XLOCB(19,BOFP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2995 {"bgelrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2996 {"bnllrl+",  XLOCB(19,BOFP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2997 {"blelr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2998 {"bnglr+",   XLOCB(19,BOFP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
2999 {"blelrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3000 {"bnglrl+",  XLOCB(19,BOFP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3001 {"bnelr+",   XLOCB(19,BOFP,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3002 {"bnelrl+",  XLOCB(19,BOFP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3003 {"bnslr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3004 {"bnulr+",   XLOCB(19,BOFP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3005 {"bnslrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3006 {"bnulrl+",  XLOCB(19,BOFP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3007 {"bgelr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3008 {"bnllr-",   XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3009 {"bgelrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3010 {"bnllrl-",  XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3011 {"blelr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3012 {"bnglr-",   XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3013 {"blelrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3014 {"bnglrl-",  XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3015 {"bnelr-",   XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3016 {"bnelrl-",  XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3017 {"bnslr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3018 {"bnulr-",   XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3019 {"bnslrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3020 {"bnulrl-",  XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3021 {"bgelr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3022 {"bnllr+",   XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3023 {"bgelrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3024 {"bnllrl+",  XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3025 {"blelr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3026 {"bnglr+",   XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3027 {"blelrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3028 {"bnglrl+",  XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3029 {"bnelr+",   XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3030 {"bnelrl+",  XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3031 {"bnslr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3032 {"bnulr+",   XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3033 {"bnslrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3034 {"bnulrl+",  XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3035 {"bltlr",    XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3036 {"bltlr-",   XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3037 {"bltr",     XLOCB(19,BOT,CBLT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3038 {"bltlrl",   XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3039 {"bltlrl-",  XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3040 {"bltrl",    XLOCB(19,BOT,CBLT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3041 {"bgtlr",    XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3042 {"bgtlr-",   XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3043 {"bgtr",     XLOCB(19,BOT,CBGT,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3044 {"bgtlrl",   XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3045 {"bgtlrl-",  XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3046 {"bgtrl",    XLOCB(19,BOT,CBGT,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3047 {"beqlr",    XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3048 {"beqlr-",   XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3049 {"beqr",     XLOCB(19,BOT,CBEQ,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3050 {"beqlrl",   XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3051 {"beqlrl-",  XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3052 {"beqrl",    XLOCB(19,BOT,CBEQ,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3053 {"bsolr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3054 {"bsolr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3055 {"bsor",     XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3056 {"bunlr",    XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3057 {"bunlr-",   XLOCB(19,BOT,CBSO,16,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3058 {"bsolrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3059 {"bsolrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3060 {"bsorl",    XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PWRCOM,   PPCNONE,       {CR}},
3061 {"bunlrl",   XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3062 {"bunlrl-",  XLOCB(19,BOT,CBSO,16,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3063 {"bltlr+",   XLOCB(19,BOTP,CBLT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3064 {"bltlrl+",  XLOCB(19,BOTP,CBLT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3065 {"bgtlr+",   XLOCB(19,BOTP,CBGT,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3066 {"bgtlrl+",  XLOCB(19,BOTP,CBGT,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3067 {"beqlr+",   XLOCB(19,BOTP,CBEQ,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3068 {"beqlrl+",  XLOCB(19,BOTP,CBEQ,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3069 {"bsolr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3070 {"bunlr+",   XLOCB(19,BOTP,CBSO,16,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3071 {"bsolrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3072 {"bunlrl+",  XLOCB(19,BOTP,CBSO,16,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3073 {"bltlr-",   XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3074 {"bltlrl-",  XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3075 {"bgtlr-",   XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3076 {"bgtlrl-",  XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3077 {"beqlr-",   XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3078 {"beqlrl-",  XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3079 {"bsolr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3080 {"bunlr-",   XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3081 {"bsolrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3082 {"bunlrl-",  XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3083 {"bltlr+",   XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3084 {"bltlrl+",  XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3085 {"bgtlr+",   XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3086 {"bgtlrl+",  XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3087 {"beqlr+",   XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3088 {"beqlrl+",  XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3089 {"bsolr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3090 {"bunlr+",   XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3091 {"bsolrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3092 {"bunlrl+",  XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3093
3094 {"bdnzflr",  XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3095 {"bdnzflr-", XLO(19,BODNZF,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3096 {"bdnzflrl", XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3097 {"bdnzflrl-",XLO(19,BODNZF,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3098 {"bdnzflr+", XLO(19,BODNZFP,16,0),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3099 {"bdnzflrl+",XLO(19,BODNZFP,16,1),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3100 {"bdzflr",   XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3101 {"bdzflr-",  XLO(19,BODZF,16,0),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3102 {"bdzflrl",  XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3103 {"bdzflrl-", XLO(19,BODZF,16,1),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3104 {"bdzflr+",  XLO(19,BODZFP,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3105 {"bdzflrl+", XLO(19,BODZFP,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3106 {"bflr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3107 {"bflr-",    XLO(19,BOF,16,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3108 {"bbfr",     XLO(19,BOF,16,0),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3109 {"bflrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3110 {"bflrl-",   XLO(19,BOF,16,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3111 {"bbfrl",    XLO(19,BOF,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3112 {"bflr+",    XLO(19,BOFP,16,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3113 {"bflrl+",   XLO(19,BOFP,16,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3114 {"bflr-",    XLO(19,BOFM4,16,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3115 {"bflrl-",   XLO(19,BOFM4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3116 {"bflr+",    XLO(19,BOFP4,16,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3117 {"bflrl+",   XLO(19,BOFP4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3118 {"bdnztlr",  XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3119 {"bdnztlr-", XLO(19,BODNZT,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3120 {"bdnztlrl", XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3121 {"bdnztlrl-",XLO(19,BODNZT,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3122 {"bdnztlr+", XLO(19,BODNZTP,16,0),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3123 {"bdnztlrl+",XLO(19,BODNZTP,16,1),      XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3124 {"bdztlr",   XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3125 {"bdztlr-",  XLO(19,BODZT,16,0),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3126 {"bdztlrl",  XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3127 {"bdztlrl-", XLO(19,BODZT,16,1),        XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3128 {"bdztlr+",  XLO(19,BODZTP,16,0),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3129 {"bdztlrl+", XLO(19,BODZTP,16,1),       XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3130 {"btlr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3131 {"btlr-",    XLO(19,BOT,16,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3132 {"bbtr",     XLO(19,BOT,16,0),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3133 {"btlrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3134 {"btlrl-",   XLO(19,BOT,16,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3135 {"bbtrl",    XLO(19,BOT,16,1),          XLBOBB_MASK,   PWRCOM,   PPCNONE,       {BI}},
3136 {"btlr+",    XLO(19,BOTP,16,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3137 {"btlrl+",   XLO(19,BOTP,16,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3138 {"btlr-",    XLO(19,BOTM4,16,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3139 {"btlrl-",   XLO(19,BOTM4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3140 {"btlr+",    XLO(19,BOTP4,16,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3141 {"btlrl+",   XLO(19,BOTP4,16,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3142
3143 {"bclr-",    XLYLK(19,16,0,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3144 {"bclrl-",   XLYLK(19,16,0,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3145 {"bclr+",    XLYLK(19,16,1,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3146 {"bclrl+",   XLYLK(19,16,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3147 {"bclr",     XLLK(19,16,0),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3148 {"bcr",      XLLK(19,16,0),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3149 {"bclrl",    XLLK(19,16,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3150 {"bcrl",     XLLK(19,16,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3151
3152 {"rfid",        XL(19,18),      0xffffffff,  PPC64,     PPCNONE,        {0}},
3153
3154 {"crnot",       XL(19,33),      XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
3155 {"crnor",       XL(19,33),      XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3156 {"rfmci",       X(19,38),   0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCNONE, {0}},
3157
3158 {"rfdi",        XL(19,39),      0xffffffff,  E500MC,    PPCNONE,        {0}},
3159 {"rfi",         XL(19,50),      0xffffffff,  COM,       PPCNONE,        {0}},
3160 {"rfci",        XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {0}},
3161
3162 {"rfsvc",       XL(19,82),      0xffffffff,  POWER,     PPCNONE,        {0}},
3163
3164 {"rfgi",        XL(19,102),   0xffffffff, E500MC|PPCA2, PPCNONE,        {0}},
3165
3166 {"crandc",      XL(19,129),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3167
3168 {"isync",       XL(19,150),     0xffffffff,  PPCCOM,    PPCNONE,        {0}},
3169 {"ics",         XL(19,150),     0xffffffff,  PWRCOM,    PPCNONE,        {0}},
3170
3171 {"crclr",       XL(19,193),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
3172 {"crxor",       XL(19,193),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3173
3174 {"dnh",         X(19,198),      X_MASK,      E500MC,    PPCNONE,        {DUI, DUIS}},
3175
3176 {"crnand",      XL(19,225),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3177
3178 {"crand",       XL(19,257),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3179
3180 {"hrfid",       XL(19,274),     0xffffffff, POWER5|CELL, PPC476,        {0}},
3181
3182 {"crset",       XL(19,289),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BAT, BBA}},
3183 {"creqv",       XL(19,289),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3184
3185 {"doze",        XL(19,402),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3186
3187 {"crorc",       XL(19,417),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3188
3189 {"nap",         XL(19,434),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3190
3191 {"crmove",      XL(19,449),     XL_MASK,     PPCCOM,    PPCNONE,        {BT, BA, BBA}},
3192 {"cror",        XL(19,449),     XL_MASK,     COM,       PPCNONE,        {BT, BA, BB}},
3193
3194 {"sleep",       XL(19,466),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3195 {"rvwinkle",    XL(19,498),     0xffffffff,  POWER6,    PPCNONE,        {0}},
3196
3197 {"bctr",    XLO(19,BOU,528,0),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
3198 {"bctrl",   XLO(19,BOU,528,1),          XLBOBIBB_MASK, COM,      PPCNONE,       {0}},
3199
3200 {"bgectr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3201 {"bgectr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3202 {"bnlctr",  XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3203 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3204 {"bgectrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3205 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3206 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3207 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3208 {"blectr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3209 {"blectr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3210 {"bngctr",  XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3211 {"bngctr-", XLOCB(19,BOF,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3212 {"blectrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3213 {"blectrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3214 {"bngctrl", XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3215 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3216 {"bnectr",  XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3217 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3218 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3219 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3220 {"bnsctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3221 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3222 {"bnuctr",  XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3223 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3224 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3225 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3226 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3227 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3228 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3229 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3230 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3231 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3232 {"blectr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3233 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3234 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3235 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3236 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3237 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3238 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3239 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3240 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3241 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3242 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3243 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3244 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3245 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3246 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3247 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3248 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3249 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3250 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3251 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3252 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3253 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3254 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3255 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3256 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3257 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3258 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3259 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3260 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3261 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3262 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3263 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3264 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3265 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3266 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3267 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3268 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3269 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3270 {"bltctr",  XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3271 {"bltctr-", XLOCB(19,BOT,CBLT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3272 {"bltctrl", XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3273 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3274 {"bgtctr",  XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3275 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3276 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3277 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3278 {"beqctr",  XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3279 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3280 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3281 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3282 {"bsoctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3283 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3284 {"bunctr",  XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3285 {"bunctr-", XLOCB(19,BOT,CBSO,528,0),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3286 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3287 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3288 {"bunctrl", XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   PPCNONE,       {CR}},
3289 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1),   XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3290 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3291 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3292 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3293 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3294 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3295 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3296 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3297 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3298 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3299 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,   POWER4,        {CR}},
3300 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3301 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3302 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3303 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3304 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3305 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3306 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3307 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3308 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3309 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3310 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3311 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3312 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3313 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3314 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3315 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3316 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3317 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3318 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3319 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4,   PPCNONE,       {CR}},
3320
3321 {"bfctr",   XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3322 {"bfctr-",  XLO(19,BOF,528,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3323 {"bfctrl",  XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3324 {"bfctrl-", XLO(19,BOF,528,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3325 {"bfctr+",  XLO(19,BOFP,528,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3326 {"bfctrl+", XLO(19,BOFP,528,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3327 {"bfctr-",  XLO(19,BOFM4,528,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3328 {"bfctrl-", XLO(19,BOFM4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3329 {"bfctr+",  XLO(19,BOFP4,528,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3330 {"bfctrl+", XLO(19,BOFP4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3331 {"btctr",   XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3332 {"btctr-",  XLO(19,BOT,528,0),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3333 {"btctrl",  XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   PPCNONE,       {BI}},
3334 {"btctrl-", XLO(19,BOT,528,1),          XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3335 {"btctr+",  XLO(19,BOTP,528,0),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3336 {"btctrl+", XLO(19,BOTP,528,1),         XLBOBB_MASK,   PPCCOM,   POWER4,        {BI}},
3337 {"btctr-",  XLO(19,BOTM4,528,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3338 {"btctrl-", XLO(19,BOTM4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3339 {"btctr+",  XLO(19,BOTP4,528,0),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3340 {"btctrl+", XLO(19,BOTP4,528,1),        XLBOBB_MASK,   POWER4,   PPCNONE,       {BI}},
3341
3342 {"bcctr-",  XLYLK(19,528,0,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3343 {"bcctrl-", XLYLK(19,528,0,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3344 {"bcctr+",  XLYLK(19,528,1,0),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3345 {"bcctrl+", XLYLK(19,528,1,1),          XLYBB_MASK,    PPCCOM,   PPCNONE,       {BOE, BI}},
3346 {"bcctr",   XLLK(19,528,0),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3347 {"bcc",     XLLK(19,528,0),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3348 {"bcctrl",  XLLK(19,528,1),             XLBH_MASK,     PPCCOM,   PPCNONE,       {BO, BI, BH}},
3349 {"bccl",    XLLK(19,528,1),             XLBB_MASK,     PWRCOM,   PPCNONE,       {BO, BI}},
3350
3351 {"rlwimi",      M(20,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3352 {"rlimi",       M(20,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3353
3354 {"rlwimi.",     M(20,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3355 {"rlimi.",      M(20,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3356
3357 {"rotlwi",      MME(21,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
3358 {"clrlwi",      MME(21,31,0),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
3359 {"rlwinm",      M(21,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3360 {"rlinm",       M(21,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3361 {"rotlwi.",     MME(21,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, SH}},
3362 {"clrlwi.",     MME(21,31,1),   MSHME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, MB}},
3363 {"rlwinm.",     M(21,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3364 {"rlinm.",      M(21,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH, MBE, ME}},
3365
3366 {"rlmi",        M(22,0),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
3367 {"rlmi.",       M(22,1),        M_MASK,      M601,      PPCNONE,        {RA, RS, RB, MBE, ME}},
3368
3369 {"rotlw",       MME(23,31,0),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
3370 {"rlwnm",       M(23,0),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3371 {"rlnm",        M(23,0),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3372 {"rotlw.",      MME(23,31,1),   MMBME_MASK,  PPCCOM,    PPCNONE,        {RA, RS, RB}},
3373 {"rlwnm.",      M(23,1),        M_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3374 {"rlnm.",       M(23,1),        M_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB, MBE, ME}},
3375
3376 {"nop",         OP(24),         0xffffffff,  PPCCOM,    PPCNONE,        {0}},
3377 {"ori",         OP(24),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3378 {"oril",        OP(24),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3379
3380 {"oris",        OP(25),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3381 {"oriu",        OP(25),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3382
3383 {"xori",        OP(26),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3384 {"xoril",       OP(26),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3385
3386 {"xoris",       OP(27),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3387 {"xoriu",       OP(27),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3388
3389 {"andi.",       OP(28),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3390 {"andil.",      OP(28),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3391
3392 {"andis.",      OP(29),         OP_MASK,     PPCCOM,    PPCNONE,        {RA, RS, UI}},
3393 {"andiu.",      OP(29),         OP_MASK,     PWRCOM,    PPCNONE,        {RA, RS, UI}},
3394
3395 {"rotldi",      MD(30,0,0),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
3396 {"clrldi",      MD(30,0,0),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
3397 {"rldicl",      MD(30,0,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3398 {"rotldi.",     MD(30,0,1),     MDMB_MASK,   PPC64,     PPCNONE,        {RA, RS, SH6}},
3399 {"clrldi.",     MD(30,0,1),     MDSH_MASK,   PPC64,     PPCNONE,        {RA, RS, MB6}},
3400 {"rldicl.",     MD(30,0,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3401
3402 {"rldicr",      MD(30,1,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
3403 {"rldicr.",     MD(30,1,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, ME6}},
3404
3405 {"rldic",       MD(30,2,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3406 {"rldic.",      MD(30,2,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3407
3408 {"rldimi",      MD(30,3,0),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3409 {"rldimi.",     MD(30,3,1),     MD_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6, MB6}},
3410
3411 {"rotld",       MDS(30,8,0),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
3412 {"rldcl",       MDS(30,8,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
3413 {"rotld.",      MDS(30,8,1),    MDSMB_MASK,  PPC64,     PPCNONE,        {RA, RS, RB}},
3414 {"rldcl.",      MDS(30,8,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, MB6}},
3415
3416 {"rldcr",       MDS(30,9,0),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
3417 {"rldcr.",      MDS(30,9,1),    MDS_MASK,    PPC64,     PPCNONE,        {RA, RS, RB, ME6}},
3418
3419 {"cmpw",        XOPL(31,0,0),   XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
3420 {"cmpd",        XOPL(31,0,1),   XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
3421 {"cmp",         X(31,0),        XCMP_MASK,   PPC,       PPCNONE,        {BF, L, RA, RB}},
3422 {"cmp",         X(31,0),        XCMPL_MASK,  PWRCOM,    PPCNONE,        {BF, RA, RB}},
3423
3424 {"twlgt",       XTO(31,4,TOLGT), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3425 {"tlgt",        XTO(31,4,TOLGT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3426 {"twllt",       XTO(31,4,TOLLT), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3427 {"tllt",        XTO(31,4,TOLLT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3428 {"tweq",        XTO(31,4,TOEQ),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3429 {"teq",         XTO(31,4,TOEQ),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3430 {"twlge",       XTO(31,4,TOLGE), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3431 {"tlge",        XTO(31,4,TOLGE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3432 {"twlnl",       XTO(31,4,TOLNL), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3433 {"tlnl",        XTO(31,4,TOLNL), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3434 {"twlle",       XTO(31,4,TOLLE), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3435 {"tlle",        XTO(31,4,TOLLE), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3436 {"twlng",       XTO(31,4,TOLNG), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3437 {"tlng",        XTO(31,4,TOLNG), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3438 {"twgt",        XTO(31,4,TOGT),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3439 {"tgt",         XTO(31,4,TOGT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3440 {"twge",        XTO(31,4,TOGE),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3441 {"tge",         XTO(31,4,TOGE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3442 {"twnl",        XTO(31,4,TONL),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3443 {"tnl",         XTO(31,4,TONL),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3444 {"twlt",        XTO(31,4,TOLT),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3445 {"tlt",         XTO(31,4,TOLT),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3446 {"twle",        XTO(31,4,TOLE),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3447 {"tle",         XTO(31,4,TOLE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3448 {"twng",        XTO(31,4,TONG),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3449 {"tng",         XTO(31,4,TONG),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3450 {"twne",        XTO(31,4,TONE),  XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
3451 {"tne",         XTO(31,4,TONE),  XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
3452 {"trap",        XTO(31,4,TOU),   0xffffffff, PPCCOM,    PPCNONE,        {0}},
3453 {"tw",          X(31,4),         X_MASK,     PPCCOM,    PPCNONE,        {TO, RA, RB}},
3454 {"t",           X(31,4),         X_MASK,     PWRCOM,    PPCNONE,        {TO, RA, RB}},
3455
3456 {"lvsl",        X(31,6),        X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3457 {"lvebx",       X(31,7),        X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3458 {"lbfcmx",      APU(31,7,0),    APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3459
3460 {"subfc",       XO(31,8,0,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3461 {"sf",          XO(31,8,0,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3462 {"subc",        XO(31,8,0,0),   XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
3463 {"subfc.",      XO(31,8,0,1),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3464 {"sf.",         XO(31,8,0,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3465 {"subc.",       XO(31,8,0,1),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RB, RA}},
3466
3467 {"mulhdu",      XO(31,9,0,0),   XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3468 {"mulhdu.",     XO(31,9,0,1),   XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3469
3470 {"addc",        XO(31,10,0,0),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3471 {"a",           XO(31,10,0,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3472 {"addc.",       XO(31,10,0,1),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3473 {"a.",          XO(31,10,0,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3474
3475 {"mulhwu",      XO(31,11,0,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3476 {"mulhwu.",     XO(31,11,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3477
3478 {"isellt",      X(31,15),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA, RB}},
3479
3480 {"tlbilxlpid",  XTO(31,18,0),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
3481 {"tlbilxpid",   XTO(31,18,1),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {0}},
3482 {"tlbilxva",    XTO(31,18,3),   XTO_MASK, E500MC|PPCA2, PPCNONE,        {RA0, RB}},
3483 {"tlbilx",      X(31,18),       X_MASK,   E500MC|PPCA2, PPCNONE,        {T, RA0, RB}},
3484
3485 {"mfcr",        XFXM(31,19,0,0), XFXFXM_MASK, POWER4,   PPCNONE,        {RT, FXM4}},
3486 {"mfcr",        XFXM(31,19,0,0), XRARB_MASK, COM,       POWER4,         {RT}},
3487 {"mfocrf",      XFXM(31,19,0,1), XFXFXM_MASK, COM,      PPCNONE,        {RT, FXM}},
3488
3489 {"lwarx",       X(31,20),       XEH_MASK,    PPC,       PPCNONE,        {RT, RA0, RB, EH}},
3490
3491 {"ldx",         X(31,21),       X_MASK,      PPC64,     PPCNONE,        {RT, RA0, RB}},
3492
3493 {"icbt",        X(31,22),       X_MASK, BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {CT, RA, RB}},
3494
3495 {"lwzx",        X(31,23),       X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
3496 {"lx",          X(31,23),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
3497
3498 {"slw",         XRC(31,24,0),   X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
3499 {"sl",          XRC(31,24,0),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
3500 {"slw.",        XRC(31,24,1),   X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
3501 {"sl.",         XRC(31,24,1),   X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
3502
3503 {"cntlzw",      XRC(31,26,0),   XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
3504 {"cntlz",       XRC(31,26,0),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
3505 {"cntlzw.",     XRC(31,26,1),   XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
3506 {"cntlz.",      XRC(31,26,1),   XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
3507
3508 {"sld",         XRC(31,27,0),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
3509 {"sld.",        XRC(31,27,1),   X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
3510
3511 {"and",         XRC(31,28,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3512 {"and.",        XRC(31,28,1),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3513
3514 {"maskg",       XRC(31,29,0),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
3515 {"maskg.",      XRC(31,29,1),   X_MASK,      M601,      PPCA2,          {RA, RS, RB}},
3516
3517 {"ldepx",       X(31,29),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3518 {"lwepx",       X(31,31),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3519
3520 {"cmplw",       XOPL(31,32,0),  XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
3521 {"cmpld",       XOPL(31,32,1),  XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
3522 {"cmpl",        X(31,32),       XCMP_MASK,   PPC,       PPCNONE,        {BF, L, RA, RB}},
3523 {"cmpl",        X(31,32),       XCMPL_MASK,  PWRCOM,    PPCNONE,        {BF, RA, RB}},
3524
3525 {"lvsr",        X(31,38),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3526 {"lvehx",       X(31,39),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3527 {"lhfcmx",      APU(31,39,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3528
3529 {"iselgt",      X(31,47),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA, RB}},
3530
3531 {"lvewx",       X(31,71),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3532
3533 {"addg6s",      XO(31,74,0,0),  XO_MASK,     POWER6,    PPCNONE,        {RT, RA, RB}},
3534
3535 {"iseleq",      X(31,79),       X_MASK,      PPCISEL,   PPCNONE,        {RT, RA, RB}},
3536
3537 {"isel",        XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, PPCNONE,       {RT, RA, RB, CRB}},
3538
3539 {"subf",        XO(31,40,0,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3540 {"sub",         XO(31,40,0,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
3541 {"subf.",       XO(31,40,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3542 {"sub.",        XO(31,40,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
3543
3544 {"eratilx",     X(31,51),       X_MASK,      PPCA2,     PPCNONE,        {ERAT_T, RA, RB}},
3545
3546 {"lbarx",       X(31,52),       XEH_MASK,    POWER7,    PPCNONE,        {RT, RA0, RB, EH}},
3547
3548 {"ldux",        X(31,53),       X_MASK,      PPC64,     PPCNONE,        {RT, RAL, RB}},
3549
3550 {"dcbst",       X(31,54),       XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
3551
3552 {"lwzux",       X(31,55),       X_MASK,      PPCCOM,    PPCNONE,        {RT, RAL, RB}},
3553 {"lux",         X(31,55),       X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
3554
3555 {"cntlzd",      XRC(31,58,0),   XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
3556 {"cntlzd.",     XRC(31,58,1),   XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
3557
3558 {"andc",        XRC(31,60,0),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3559 {"andc.",       XRC(31,60,1),   X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3560
3561 {"waitrsv",     X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
3562 {"waitimpl",    X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
3563 {"wait",        X(31,62),         XWC_MASK,   POWER7|E500MC|PPCA2, PPCNONE, {WC}},
3564
3565 {"dcbstep",     XRT(31,63,0),   XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
3566
3567 {"tdlgt",       XTO(31,68,TOLGT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3568 {"tdllt",       XTO(31,68,TOLLT), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3569 {"tdeq",        XTO(31,68,TOEQ),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3570 {"tdlge",       XTO(31,68,TOLGE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3571 {"tdlnl",       XTO(31,68,TOLNL), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3572 {"tdlle",       XTO(31,68,TOLLE), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3573 {"tdlng",       XTO(31,68,TOLNG), XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3574 {"tdgt",        XTO(31,68,TOGT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3575 {"tdge",        XTO(31,68,TOGE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3576 {"tdnl",        XTO(31,68,TONL),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3577 {"tdlt",        XTO(31,68,TOLT),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3578 {"tdle",        XTO(31,68,TOLE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3579 {"tdng",        XTO(31,68,TONG),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3580 {"tdne",        XTO(31,68,TONE),  XTO_MASK,  PPC64,     PPCNONE,        {RA, RB}},
3581 {"td",          X(31,68),       X_MASK,      PPC64,     PPCNONE,        {TO, RA, RB}},
3582
3583 {"lwfcmx",      APU(31,71,0),   APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3584 {"mulhd",       XO(31,73,0,0),  XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3585 {"mulhd.",      XO(31,73,0,1),  XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3586
3587 {"mulhw",       XO(31,75,0,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3588 {"mulhw.",      XO(31,75,0,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
3589
3590 {"dlmzb",       XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, PPCNONE,     {RA, RS, RB}},
3591 {"dlmzb.",      XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, PPCNONE,     {RA, RS, RB}},
3592
3593 {"mtsrd",       X(31,82),  XRB_MASK|(1<<20), PPC64,     PPCNONE,        {SR, RS}},
3594
3595 {"mfmsr",       X(31,83),       XRARB_MASK,  COM,       PPCNONE,        {RT}},
3596
3597 {"ldarx",       X(31,84),       XEH_MASK,    PPC64,     PPCNONE,        {RT, RA0, RB, EH}},
3598
3599 {"dcbfl",       XOPL(31,86,1),  XRT_MASK,    POWER5,    PPC476,         {RA, RB}},
3600 {"dcbf",        X(31,86),       XLRT_MASK,   PPC,       PPCNONE,        {RA, RB, L}},
3601
3602 {"lbzx",        X(31,87),       X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
3603
3604 {"lbepx",       X(31,95),       X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3605
3606 {"lvx",         X(31,103),      X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
3607 {"lqfcmx",      APU(31,103,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3608
3609 {"neg",         XO(31,104,0,0), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
3610 {"neg.",        XO(31,104,0,1), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
3611
3612 {"mul",         XO(31,107,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3613 {"mul.",        XO(31,107,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3614
3615 {"mtsrdin",     X(31,114),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
3616
3617 {"lharx",       X(31,116),      XEH_MASK,    POWER7,    PPCNONE,        {RT, RA0, RB, EH}},
3618
3619 {"clf",         X(31,118),      XTO_MASK,    POWER,     PPCNONE,        {RA, RB}},
3620
3621 {"lbzux",       X(31,119),      X_MASK,      COM,       PPCNONE,        {RT, RAL, RB}},
3622
3623 {"popcntb",     X(31,122),      XRB_MASK,    POWER5,    PPCNONE,        {RA, RS}},
3624
3625 {"not",         XRC(31,124,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
3626 {"nor",         XRC(31,124,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3627 {"not.",        XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
3628 {"nor.",        XRC(31,124,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3629
3630 {"dcbfep",      XRT(31,127,0),  XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
3631
3632 {"wrtee",       X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RS}},
3633
3634 {"dcbtstls",    X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,       {CT, RA, RB}},
3635
3636 {"stvebx",      X(31,135),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3637 {"stbfcmx",     APU(31,135,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3638
3639 {"subfe",       XO(31,136,0,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3640 {"sfe",         XO(31,136,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3641 {"subfe.",      XO(31,136,0,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3642 {"sfe.",        XO(31,136,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3643
3644 {"adde",        XO(31,138,0,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3645 {"ae",          XO(31,138,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3646 {"adde.",       XO(31,138,0,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3647 {"ae.",         XO(31,138,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3648
3649 {"dcbtstlse",   X(31,142),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
3650
3651 {"mtcr",        XFXM(31,144,0xff,0), XRARB_MASK, COM,   PPCNONE,        {RS}},
3652 {"mtcrf",       XFXM(31,144,0,0), XFXFXM_MASK, COM,     PPCNONE,        {FXM, RS}},
3653 {"mtocrf",      XFXM(31,144,0,1), XFXFXM_MASK, COM,     PPCNONE,        {FXM, RS}},
3654
3655 {"mtmsr",       X(31,146),      XRLARB_MASK, COM,       PPCNONE,        {RS, A_L}},
3656
3657 {"eratsx",      XRC(31,147,0),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
3658 {"eratsx.",     XRC(31,147,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
3659
3660 {"stdx",        X(31,149),      X_MASK,      PPC64,     PPCNONE,        {RS, RA0, RB}},
3661
3662 {"stwcx.",      XRC(31,150,1),  X_MASK,      PPC,       PPCNONE,        {RS, RA0, RB}},
3663
3664 {"stwx",        X(31,151),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, RB}},
3665 {"stx",         X(31,151),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA, RB}},
3666
3667 {"slq",         XRC(31,152,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3668 {"slq.",        XRC(31,152,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3669
3670 {"sle",         XRC(31,153,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3671 {"sle.",        XRC(31,153,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3672
3673 {"prtyw",       X(31,154),      XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}},
3674
3675 {"stdepx",      X(31,157),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
3676
3677 {"stwepx",      X(31,159),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
3678
3679 {"wrteei",      X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {E}},
3680
3681 {"dcbtls",      X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,       {CT, RA, RB}},
3682
3683 {"stvehx",      X(31,167),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3684 {"sthfcmx",     APU(31,167,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3685
3686 {"dcbtlse",     X(31,174),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
3687
3688 {"mtmsrd",      X(31,178),      XRLARB_MASK, PPC64,     PPCNONE,        {RS, A_L}},
3689
3690 {"eratre",      X(31,179),      X_MASK,      PPCA2,     PPCNONE,        {RT, RA, WS}},
3691
3692 {"stdux",       X(31,181),      X_MASK,      PPC64,     PPCNONE,        {RS, RAS, RB}},
3693
3694 {"wchkall",     X(31,182),      X_MASK,      PPCA2,     PPCNONE,        {OBF}},
3695
3696 {"stwux",       X(31,183),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RAS, RB}},
3697 {"stux",        X(31,183),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
3698
3699 {"sliq",        XRC(31,184,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3700 {"sliq.",       XRC(31,184,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3701
3702 {"prtyd",       X(31,186),      XRB_MASK, POWER6|PPCA2, PPCNONE,        {RA, RS}},
3703
3704 {"stvewx",      X(31,199),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3705 {"stwfcmx",     APU(31,199,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3706
3707 {"subfze",      XO(31,200,0,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3708 {"sfze",        XO(31,200,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3709 {"subfze.",     XO(31,200,0,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3710 {"sfze.",       XO(31,200,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3711
3712 {"addze",       XO(31,202,0,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3713 {"aze",         XO(31,202,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3714 {"addze.",      XO(31,202,0,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3715 {"aze.",        XO(31,202,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3716
3717 {"msgsnd",      XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE,   {RB}},
3718
3719 {"mtsr",        X(31,210), XRB_MASK|(1<<20), COM32,     TITAN,          {SR, RS}},
3720
3721 {"eratwe",      X(31,211),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA, WS}},
3722
3723 {"ldawx.",      XRC(31,212,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, RA0, RB}},
3724
3725 {"stdcx.",      XRC(31,214,1),  X_MASK,      PPC64,     PPCNONE,        {RS, RA0, RB}},
3726
3727 {"stbx",        X(31,215),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
3728
3729 {"sllq",        XRC(31,216,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3730 {"sllq.",       XRC(31,216,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3731
3732 {"sleq",        XRC(31,217,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3733 {"sleq.",       XRC(31,217,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
3734
3735 {"stbepx",      X(31,223),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
3736
3737 {"icblc",       X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,       {CT, RA, RB}},
3738
3739 {"stvx",        X(31,231),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
3740 {"stqfcmx",     APU(31,231,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3741
3742 {"subfme",      XO(31,232,0,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3743 {"sfme",        XO(31,232,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3744 {"subfme.",     XO(31,232,0,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3745 {"sfme.",       XO(31,232,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3746
3747 {"mulld",       XO(31,233,0,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3748 {"mulld.",      XO(31,233,0,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
3749
3750 {"addme",       XO(31,234,0,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3751 {"ame",         XO(31,234,0,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3752 {"addme.",      XO(31,234,0,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
3753 {"ame.",        XO(31,234,0,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
3754
3755 {"mullw",       XO(31,235,0,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3756 {"muls",        XO(31,235,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3757 {"mullw.",      XO(31,235,0,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3758 {"muls.",       XO(31,235,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3759
3760 {"icblce",      X(31,238),      X_MASK,      PPCCHLK,   E500MC|PPCA2,   {CT, RA, RB}},
3761 {"msgclr",      XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE,     {RB}},
3762 {"mtsrin",      X(31,242),      XRA_MASK,    PPC32,     TITAN,          {RS, RB}},
3763 {"mtsri",       X(31,242),      XRA_MASK,    POWER32,   PPCNONE,        {RS, RB}},
3764
3765 {"dcbtstt",     XRT(31,246,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA, RB}},
3766 {"dcbtst",      X(31,246),      X_MASK,      POWER4,    PPCNONE,        {RA, RB, CT}},
3767 {"dcbtst",      X(31,246),      X_MASK,      PPC,       POWER4,         {CT, RA, RB}},
3768
3769 {"stbux",       X(31,247),      X_MASK,      COM,       PPCNONE,        {RS, RAS, RB}},
3770
3771 {"slliq",       XRC(31,248,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3772 {"slliq.",      XRC(31,248,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
3773
3774 {"bpermd",      X(31,252),      X_MASK,   POWER7|PPCA2, PPCNONE,        {RA, RS, RB}},
3775
3776 {"dcbtstep",    XRT(31,255,0),  X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3777
3778 {"mfdcrx",      X(31,259),      X_MASK, BOOKE|PPCA2|PPC476, TITAN,      {RS, RA}},
3779 {"mfdcrx.",     XRC(31,259,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA}},
3780
3781 {"icbt",        X(31,262),      XRT_MASK,    PPC403,    PPCNONE,        {RA, RB}},
3782
3783 {"ldfcmx",      APU(31,263,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
3784 {"doz",         XO(31,264,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3785 {"doz.",        XO(31,264,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3786
3787 {"add",         XO(31,266,0,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3788 {"cax",         XO(31,266,0,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3789 {"add.",        XO(31,266,0,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
3790 {"cax.",        XO(31,266,0,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
3791
3792 {"ehpriv",      X(31,270),      0xffffffff, E500MC|PPCA2, PPCNONE,      {0}},
3793
3794 {"tlbiel",      X(31,274),      XRTLRA_MASK, POWER4,    PPC476,         {RB, L}},
3795
3796 {"mfapidi",     X(31,275),      X_MASK,      BOOKE,     TITAN,          {RT, RA}},
3797
3798 {"lscbx",       XRC(31,277,0),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
3799 {"lscbx.",      XRC(31,277,1),  X_MASK,      M601,      PPCNONE,        {RT, RA, RB}},
3800
3801 {"dcbtt",       XRT(31,278,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA, RB}},
3802 {"dcbt",        X(31,278),      X_MASK,      POWER4,    PPCNONE,        {RA, RB, CT}},
3803 {"dcbt",        X(31,278),      X_MASK,      PPC,       POWER4,         {CT, RA, RB}},
3804
3805 {"lhzx",        X(31,279),      X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
3806
3807 {"cdtbcd",      X(31,282),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
3808
3809 {"eqv",         XRC(31,284,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3810 {"eqv.",        XRC(31,284,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3811
3812 {"lhepx",       X(31,287),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3813
3814 {"mfdcrux",     X(31,291),      X_MASK,      PPC464,    PPCNONE,        {RS, RA}},
3815
3816 {"tlbie",       X(31,306),      XRTLRA_MASK, PPC,       TITAN,          {RB, L}},
3817 {"tlbi",        X(31,306),      XRT_MASK,    POWER,     PPCNONE,        {RA0, RB}},
3818
3819 {"eciwx",       X(31,310),      X_MASK,      PPC,       TITAN,          {RT, RA, RB}},
3820
3821 {"lhzux",       X(31,311),      X_MASK,      COM,       PPCNONE,        {RT, RAL, RB}},
3822
3823 {"cbcdtd",      X(31,314),      XRB_MASK,    POWER6,    PPCNONE,        {RA, RS}},
3824
3825 {"xor",         XRC(31,316,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3826 {"xor.",        XRC(31,316,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
3827
3828 {"dcbtep",      XRT(31,319,0),  X_MASK,   E500MC|PPCA2, PPCNONE,        {RT, RA, RB}},
3829
3830 {"mfexisr",     XSPR(31,323, 64), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3831 {"mfexier",     XSPR(31,323, 66), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3832 {"mfbr0",       XSPR(31,323,128), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3833 {"mfbr1",       XSPR(31,323,129), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3834 {"mfbr2",       XSPR(31,323,130), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3835 {"mfbr3",       XSPR(31,323,131), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3836 {"mfbr4",       XSPR(31,323,132), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3837 {"mfbr5",       XSPR(31,323,133), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3838 {"mfbr6",       XSPR(31,323,134), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3839 {"mfbr7",       XSPR(31,323,135), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3840 {"mfbear",      XSPR(31,323,144), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3841 {"mfbesr",      XSPR(31,323,145), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3842 {"mfiocr",      XSPR(31,323,160), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3843 {"mfdmacr0",    XSPR(31,323,192), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3844 {"mfdmact0",    XSPR(31,323,193), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3845 {"mfdmada0",    XSPR(31,323,194), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3846 {"mfdmasa0",    XSPR(31,323,195), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3847 {"mfdmacc0",    XSPR(31,323,196), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3848 {"mfdmacr1",    XSPR(31,323,200), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3849 {"mfdmact1",    XSPR(31,323,201), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3850 {"mfdmada1",    XSPR(31,323,202), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3851 {"mfdmasa1",    XSPR(31,323,203), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3852 {"mfdmacc1",    XSPR(31,323,204), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3853 {"mfdmacr2",    XSPR(31,323,208), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3854 {"mfdmact2",    XSPR(31,323,209), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3855 {"mfdmada2",    XSPR(31,323,210), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3856 {"mfdmasa2",    XSPR(31,323,211), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3857 {"mfdmacc2",    XSPR(31,323,212), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3858 {"mfdmacr3",    XSPR(31,323,216), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3859 {"mfdmact3",    XSPR(31,323,217), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3860 {"mfdmada3",    XSPR(31,323,218), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3861 {"mfdmasa3",    XSPR(31,323,219), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3862 {"mfdmacc3",    XSPR(31,323,220), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3863 {"mfdmasr",     XSPR(31,323,224), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
3864 {"mfdcr",       X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN,    {RT, SPR}},
3865 {"mfdcr.",      XRC(31,323,1),  X_MASK,      PPCA2,     PPCNONE,        {RT, SPR}},
3866
3867 {"dcread",      X(31,326),      X_MASK,  PPC476|TITAN,  PPCNONE,        {RT, RA, RB}},
3868
3869 {"div",         XO(31,331,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3870 {"div.",        XO(31,331,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
3871
3872 {"lxvdsx",      X(31,332),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
3873
3874 {"mfpmr",       X(31,334),      X_MASK, PPCPMR|PPCE300, PPCNONE,        {RT, PMR}},
3875
3876 {"mfmq",        XSPR(31,339,  0), XSPR_MASK, M601,      PPCNONE,        {RT}},
3877 {"mfxer",       XSPR(31,339,  1), XSPR_MASK, COM,       PPCNONE,        {RT}},
3878 {"mfrtcu",      XSPR(31,339,  4), XSPR_MASK, COM,       TITAN,          {RT}},
3879 {"mfrtcl",      XSPR(31,339,  5), XSPR_MASK, COM,       TITAN,          {RT}},
3880 {"mfdec",       XSPR(31,339,  6), XSPR_MASK, MFDEC1,    PPCNONE,        {RT}},
3881 {"mflr",        XSPR(31,339,  8), XSPR_MASK, COM,       PPCNONE,        {RT}},
3882 {"mfctr",       XSPR(31,339,  9), XSPR_MASK, COM,       PPCNONE,        {RT}},
3883 {"mftid",       XSPR(31,339, 17), XSPR_MASK, POWER,     PPCNONE,        {RT}},
3884 {"mfdsisr",     XSPR(31,339, 18), XSPR_MASK, COM,       TITAN,          {RT}},
3885 {"mfdar",       XSPR(31,339, 19), XSPR_MASK, COM,       TITAN,          {RT}},
3886 {"mfdec",       XSPR(31,339, 22), XSPR_MASK, MFDEC2|TITAN, PPCNONE,     {RT}},
3887 {"mfsdr0",      XSPR(31,339, 24), XSPR_MASK, POWER,     PPCNONE,        {RT}},
3888 {"mfsdr1",      XSPR(31,339, 25), XSPR_MASK, COM,       TITAN,          {RT}},
3889 {"mfsrr0",      XSPR(31,339, 26), XSPR_MASK, COM,       PPCNONE,        {RT}},
3890 {"mfsrr1",      XSPR(31,339, 27), XSPR_MASK, COM,       PPCNONE,        {RT}},
3891 {"mfcfar",      XSPR(31,339, 28), XSPR_MASK, POWER6,    PPCNONE,        {RT}},
3892 {"mfpid",       XSPR(31,339, 48), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3893 {"mfcsrr0",     XSPR(31,339, 58), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3894 {"mfcsrr1",     XSPR(31,339, 59), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3895 {"mfdear",      XSPR(31,339, 61), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3896 {"mfesr",       XSPR(31,339, 62), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3897 {"mfivpr",      XSPR(31,339, 63), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3898 {"mfcmpa",      XSPR(31,339,144), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3899 {"mfcmpb",      XSPR(31,339,145), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3900 {"mfcmpc",      XSPR(31,339,146), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3901 {"mfcmpd",      XSPR(31,339,147), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3902 {"mficr",       XSPR(31,339,148), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3903 {"mfder",       XSPR(31,339,149), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3904 {"mfcounta",    XSPR(31,339,150), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3905 {"mfcountb",    XSPR(31,339,151), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3906 {"mfcmpe",      XSPR(31,339,152), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3907 {"mfcmpf",      XSPR(31,339,153), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3908 {"mfcmpg",      XSPR(31,339,154), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3909 {"mfcmph",      XSPR(31,339,155), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3910 {"mflctrl1",    XSPR(31,339,156), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3911 {"mflctrl2",    XSPR(31,339,157), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3912 {"mfictrl",     XSPR(31,339,158), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3913 {"mfbar",       XSPR(31,339,159), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3914 {"mfvrsave",    XSPR(31,339,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RT}},
3915 {"mfusprg0",    XSPR(31,339,256), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3916 {"mfsprg",      XSPR(31,339,256), XSPRG_MASK, PPC,      PPCNONE,        {RT, SPRG}},
3917 {"mfsprg4",     XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3918 {"mfsprg5",     XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3919 {"mfsprg6",     XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3920 {"mfsprg7",     XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RT}},
3921 {"mftb",        XSPR(31,339,268), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3922 {"mftbl",       XSPR(31,339,268), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3923 {"mftbu",       XSPR(31,339,269), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3924 {"mfsprg0",     XSPR(31,339,272), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3925 {"mfsprg1",     XSPR(31,339,273), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3926 {"mfsprg2",     XSPR(31,339,274), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3927 {"mfsprg3",     XSPR(31,339,275), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3928 {"mfasr",       XSPR(31,339,280), XSPR_MASK, PPC64,     PPCNONE,        {RT}},
3929 {"mfear",       XSPR(31,339,282), XSPR_MASK, PPC,       TITAN,          {RT}},
3930 {"mfpir",       XSPR(31,339,286), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3931 {"mfpvr",       XSPR(31,339,287), XSPR_MASK, PPC,       PPCNONE,        {RT}},
3932 {"mfdbsr",      XSPR(31,339,304), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3933 {"mfdbcr0",     XSPR(31,339,308), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3934 {"mfdbcr1",     XSPR(31,339,309), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3935 {"mfdbcr2",     XSPR(31,339,310), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3936 {"mfiac1",      XSPR(31,339,312), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3937 {"mfiac2",      XSPR(31,339,313), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3938 {"mfiac3",      XSPR(31,339,314), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3939 {"mfiac4",      XSPR(31,339,315), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3940 {"mfdac1",      XSPR(31,339,316), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3941 {"mfdac2",      XSPR(31,339,317), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3942 {"mfdvc1",      XSPR(31,339,318), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3943 {"mfdvc2",      XSPR(31,339,319), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3944 {"mftsr",       XSPR(31,339,336), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3945 {"mftcr",       XSPR(31,339,340), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3946 {"mfivor0",     XSPR(31,339,400), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3947 {"mfivor1",     XSPR(31,339,401), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3948 {"mfivor2",     XSPR(31,339,402), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3949 {"mfivor3",     XSPR(31,339,403), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3950 {"mfivor4",     XSPR(31,339,404), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3951 {"mfivor5",     XSPR(31,339,405), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3952 {"mfivor6",     XSPR(31,339,406), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3953 {"mfivor7",     XSPR(31,339,407), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3954 {"mfivor8",     XSPR(31,339,408), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3955 {"mfivor9",     XSPR(31,339,409), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3956 {"mfivor10",    XSPR(31,339,410), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3957 {"mfivor11",    XSPR(31,339,411), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3958 {"mfivor12",    XSPR(31,339,412), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3959 {"mfivor13",    XSPR(31,339,413), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3960 {"mfivor14",    XSPR(31,339,414), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3961 {"mfivor15",    XSPR(31,339,415), XSPR_MASK, BOOKE,     PPCNONE,        {RT}},
3962 {"mfspefscr",   XSPR(31,339,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
3963 {"mfbbear",     XSPR(31,339,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
3964 {"mfbbtar",     XSPR(31,339,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RT}},
3965 {"mfivor32",    XSPR(31,339,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
3966 {"mfibatu",     XSPR(31,339,528), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
3967 {"mfivor33",    XSPR(31,339,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
3968 {"mfibatl",     XSPR(31,339,529), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
3969 {"mfivor34",    XSPR(31,339,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RT}},
3970 {"mfivor35",    XSPR(31,339,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RT}},
3971 {"mfdbatu",     XSPR(31,339,536), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
3972 {"mfdbatl",     XSPR(31,339,537), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
3973 {"mfic_cst",    XSPR(31,339,560), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3974 {"mfic_adr",    XSPR(31,339,561), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3975 {"mfic_dat",    XSPR(31,339,562), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3976 {"mfdc_cst",    XSPR(31,339,568), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3977 {"mfdc_adr",    XSPR(31,339,569), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3978 {"mfdc_dat",    XSPR(31,339,570), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3979 {"mfmcsrr0",    XSPR(31,339,570), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
3980 {"mfmcsrr1",    XSPR(31,339,571), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
3981 {"mfmcsr",      XSPR(31,339,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RT}},
3982 {"mfmcar",      XSPR(31,339,573), XSPR_MASK, PPCRFMCI,  TITAN,          {RT}},
3983 {"mfdpdr",      XSPR(31,339,630), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3984 {"mfdpir",      XSPR(31,339,631), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3985 {"mfimmr",      XSPR(31,339,638), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3986 {"mfmi_ctr",    XSPR(31,339,784), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3987 {"mfmi_ap",     XSPR(31,339,786), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3988 {"mfmi_epn",    XSPR(31,339,787), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3989 {"mfmi_twc",    XSPR(31,339,789), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3990 {"mfmi_rpn",    XSPR(31,339,790), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3991 {"mfmd_ctr",    XSPR(31,339,792), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3992 {"mfm_casid",   XSPR(31,339,793), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3993 {"mfmd_ap",     XSPR(31,339,794), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3994 {"mfmd_epn",    XSPR(31,339,795), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3995 {"mfmd_twb",    XSPR(31,339,796), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3996 {"mfmd_twc",    XSPR(31,339,797), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3997 {"mfmd_rpn",    XSPR(31,339,798), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3998 {"mfm_tw",      XSPR(31,339,799), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
3999 {"mfmi_dbcam",  XSPR(31,339,816), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4000 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4001 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4002 {"mfmd_dbcam",  XSPR(31,339,824), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4003 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4004 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860,    PPCNONE,        {RT}},
4005 {"mfivndx",     XSPR(31,339,880), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4006 {"mfdvndx",     XSPR(31,339,881), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4007 {"mfivlim",     XSPR(31,339,882), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4008 {"mfdvlim",     XSPR(31,339,883), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4009 {"mfclcsr",     XSPR(31,339,884), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4010 {"mfccr1",      XSPR(31,339,888), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4011 {"mfrstcfg",    XSPR(31,339,923), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4012 {"mfdcdbtrl",   XSPR(31,339,924), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4013 {"mfdcdbtrh",   XSPR(31,339,925), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4014 {"mficdbtr",    XSPR(31,339,927), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4015 {"mfummcr0",    XSPR(31,339,936), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4016 {"mfupmc1",     XSPR(31,339,937), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4017 {"mfupmc2",     XSPR(31,339,938), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4018 {"mfusia",      XSPR(31,339,939), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4019 {"mfummcr1",    XSPR(31,339,940), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4020 {"mfupmc3",     XSPR(31,339,941), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4021 {"mfupmc4",     XSPR(31,339,942), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4022 {"mfzpr",       XSPR(31,339,944), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4023 {"mfpid",       XSPR(31,339,945), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4024 {"mfmmucr",     XSPR(31,339,946), XSPR_MASK, TITAN,     PPCNONE,        {RT}},
4025 {"mfccr0",      XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RT}},
4026 {"mfiac3",      XSPR(31,339,948), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4027 {"mfiac4",      XSPR(31,339,949), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4028 {"mfdvc1",      XSPR(31,339,950), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4029 {"mfdvc2",      XSPR(31,339,951), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4030 {"mfmmcr0",     XSPR(31,339,952), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4031 {"mfpmc1",      XSPR(31,339,953), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4032 {"mfsgr",       XSPR(31,339,953), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4033 {"mfdcwr",      XSPR(31,339,954), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4034 {"mfpmc2",      XSPR(31,339,954), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4035 {"mfsia",       XSPR(31,339,955), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4036 {"mfsler",      XSPR(31,339,955), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4037 {"mfmmcr1",     XSPR(31,339,956), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4038 {"mfsu0r",      XSPR(31,339,956), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4039 {"mfdbcr1",     XSPR(31,339,957), XSPR_MASK, PPC405,    PPCNONE,        {RT}},
4040 {"mfpmc3",      XSPR(31,339,957), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4041 {"mfpmc4",      XSPR(31,339,958), XSPR_MASK, PPC750,    PPCNONE,        {RT}},
4042 {"mficdbdr",    XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, PPCNONE,     {RT}},
4043 {"mfesr",       XSPR(31,339,980), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4044 {"mfdear",      XSPR(31,339,981), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4045 {"mfevpr",      XSPR(31,339,982), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4046 {"mfcdbcr",     XSPR(31,339,983), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4047 {"mftsr",       XSPR(31,339,984), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4048 {"mftcr",       XSPR(31,339,986), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4049 {"mfpit",       XSPR(31,339,987), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4050 {"mftbhi",      XSPR(31,339,988), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4051 {"mftblo",      XSPR(31,339,989), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4052 {"mfsrr2",      XSPR(31,339,990), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4053 {"mfsrr3",      XSPR(31,339,991), XSPR_MASK, PPC403,    PPCNONE,        {RT}},
4054 {"mfdbsr",      XSPR(31,339,1008), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4055 {"mfdbcr0",     XSPR(31,339,1010), XSPR_MASK, PPC405,   PPCNONE,        {RT}},
4056 {"mfdbdr",      XSPR(31,339,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
4057 {"mfiac1",      XSPR(31,339,1012), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4058 {"mfiac2",      XSPR(31,339,1013), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4059 {"mfdac1",      XSPR(31,339,1014), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4060 {"mfdac2",      XSPR(31,339,1015), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4061 {"mfl2cr",      XSPR(31,339,1017), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4062 {"mfdccr",      XSPR(31,339,1018), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4063 {"mficcr",      XSPR(31,339,1019), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4064 {"mfictc",      XSPR(31,339,1019), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4065 {"mfpbl1",      XSPR(31,339,1020), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4066 {"mfthrm1",     XSPR(31,339,1020), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4067 {"mfpbu1",      XSPR(31,339,1021), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4068 {"mfthrm2",     XSPR(31,339,1021), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4069 {"mfpbl2",      XSPR(31,339,1022), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4070 {"mfthrm3",     XSPR(31,339,1022), XSPR_MASK, PPC750,   PPCNONE,        {RT}},
4071 {"mfpbu2",      XSPR(31,339,1023), XSPR_MASK, PPC403,   PPCNONE,        {RT}},
4072 {"mfspr",       X(31,339),      X_MASK,      COM,       PPCNONE,        {RT, SPR}},
4073
4074 {"lwax",        X(31,341),      X_MASK,      PPC64,     PPCNONE,        {RT, RA0, RB}},
4075
4076 {"dst",         XDSS(31,342,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4077
4078 {"lhax",        X(31,343),      X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
4079
4080 {"lvxl",        X(31,359),      X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
4081
4082 {"abs",         XO(31,360,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4083 {"abs.",        XO(31,360,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4084
4085 {"divs",        XO(31,363,0,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4086 {"divs.",       XO(31,363,0,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4087
4088 {"tlbia",       X(31,370),      0xffffffff,  PPC,       TITAN,          {0}},
4089
4090 {"mftbl",       XSPR(31,371,268), XSPR_MASK, CLASSIC,   PPCNONE,        {RT}},
4091 {"mftbu",       XSPR(31,371,269), XSPR_MASK, CLASSIC,   PPCNONE,        {RT}},
4092 {"mftb",        X(31,371),      X_MASK,  CLASSIC|PPCA2, POWER7,         {RT, TBR}},
4093
4094 {"lwaux",       X(31,373),      X_MASK,      PPC64,     PPCNONE,        {RT, RAL, RB}},
4095
4096 {"dstst",       XDSS(31,374,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4097
4098 {"lhaux",       X(31,375),      X_MASK,      COM,       PPCNONE,        {RT, RAL, RB}},
4099
4100 {"popcntw",     X(31,378),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
4101
4102 {"mtdcrx",      X(31,387),      X_MASK, BOOKE|PPCA2|PPC476, TITAN,      {RA, RS}},
4103 {"mtdcrx.",     XRC(31,387,1),  X_MASK,      PPCA2,     PPCNONE,        {RA, RS}},
4104
4105 {"dcblc",       X(31,390),      X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,  {CT, RA, RB}},
4106 {"stdfcmx",     APU(31,391,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4107
4108 {"divdeu",      XO(31,393,0,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4109 {"divdeu.",     XO(31,393,0,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4110 {"divweu",      XO(31,395,0,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4111 {"divweu.",     XO(31,395,0,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4112
4113 {"dcblce",      X(31,398),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
4114
4115 {"slbmte",      X(31,402),      XRA_MASK,    PPC64,     PPCNONE,        {RS, RB}},
4116
4117 {"icswx",       XRC(31,406,0),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
4118 {"icswx.",      XRC(31,406,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
4119
4120 {"sthx",        X(31,407),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
4121
4122 {"orc",         XRC(31,412,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4123 {"orc.",        XRC(31,412,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4124
4125 {"sthepx",      X(31,415),      X_MASK,   E500MC|PPCA2, PPCNONE,        {RS, RA, RB}},
4126
4127 {"mtdcrux",     X(31,419),      X_MASK,      PPC464,    PPCNONE,        {RA, RS}},
4128
4129 {"divde",       XO(31,425,0,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4130 {"divde.",      XO(31,425,0,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4131 {"divwe",       XO(31,427,0,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4132 {"divwe.",      XO(31,427,0,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4133
4134 {"slbie",       X(31,434),      XRTRA_MASK,  PPC64,     PPCNONE,        {RB}},
4135
4136 {"ecowx",       X(31,438),      X_MASK,      PPC,       TITAN,          {RT, RA, RB}},
4137
4138 {"sthux",       X(31,439),      X_MASK,      COM,       PPCNONE,        {RS, RAS, RB}},
4139
4140 {"mdors",       0x7f9ce378,     0xffffffff,  E500MC,    PPCNONE,        {0}},
4141
4142 {"mr",          XRC(31,444,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4143 {"or",          XRC(31,444,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4144 {"mr.",         XRC(31,444,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RBS}},
4145 {"or.",         XRC(31,444,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4146
4147 {"mtexisr",     XSPR(31,451, 64), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4148 {"mtexier",     XSPR(31,451, 66), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4149 {"mtbr0",       XSPR(31,451,128), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4150 {"mtbr1",       XSPR(31,451,129), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4151 {"mtbr2",       XSPR(31,451,130), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4152 {"mtbr3",       XSPR(31,451,131), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4153 {"mtbr4",       XSPR(31,451,132), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4154 {"mtbr5",       XSPR(31,451,133), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4155 {"mtbr6",       XSPR(31,451,134), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4156 {"mtbr7",       XSPR(31,451,135), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4157 {"mtbear",      XSPR(31,451,144), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4158 {"mtbesr",      XSPR(31,451,145), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4159 {"mtiocr",      XSPR(31,451,160), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4160 {"mtdmacr0",    XSPR(31,451,192), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4161 {"mtdmact0",    XSPR(31,451,193), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4162 {"mtdmada0",    XSPR(31,451,194), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4163 {"mtdmasa0",    XSPR(31,451,195), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4164 {"mtdmacc0",    XSPR(31,451,196), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4165 {"mtdmacr1",    XSPR(31,451,200), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4166 {"mtdmact1",    XSPR(31,451,201), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4167 {"mtdmada1",    XSPR(31,451,202), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4168 {"mtdmasa1",    XSPR(31,451,203), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4169 {"mtdmacc1",    XSPR(31,451,204), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4170 {"mtdmacr2",    XSPR(31,451,208), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4171 {"mtdmact2",    XSPR(31,451,209), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4172 {"mtdmada2",    XSPR(31,451,210), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4173 {"mtdmasa2",    XSPR(31,451,211), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4174 {"mtdmacc2",    XSPR(31,451,212), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4175 {"mtdmacr3",    XSPR(31,451,216), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4176 {"mtdmact3",    XSPR(31,451,217), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4177 {"mtdmada3",    XSPR(31,451,218), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4178 {"mtdmasa3",    XSPR(31,451,219), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4179 {"mtdmacc3",    XSPR(31,451,220), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4180 {"mtdmasr",     XSPR(31,451,224), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4181 {"mtdcr",       X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN,    {SPR, RS}},
4182 {"mtdcr.",      XRC(31,451,1), X_MASK,       PPCA2,     PPCNONE,        {SPR, RS}},
4183
4184 {"dccci",       X(31,454), XRT_MASK, PPC403|PPC440|TITAN, PPCA2|PPC476, {RA, RB}},
4185 {"dci",         X(31,454),      XRARB_MASK, PPCA2|PPC476, PPCNONE,      {CT}},
4186
4187 {"divdu",       XO(31,457,0,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4188 {"divdu.",      XO(31,457,0,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4189
4190 {"divwu",       XO(31,459,0,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4191 {"divwu.",      XO(31,459,0,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4192
4193 {"mtpmr",       X(31,462),      X_MASK, PPCPMR|PPCE300, PPCNONE,        {PMR, RS}},
4194
4195 {"mtmq",        XSPR(31,467,  0), XSPR_MASK, M601,      PPCNONE,        {RS}},
4196 {"mtxer",       XSPR(31,467,  1), XSPR_MASK, COM,       PPCNONE,        {RS}},
4197 {"mtlr",        XSPR(31,467,  8), XSPR_MASK, COM,       PPCNONE,        {RS}},
4198 {"mtctr",       XSPR(31,467,  9), XSPR_MASK, COM,       PPCNONE,        {RS}},
4199 {"mttid",       XSPR(31,467, 17), XSPR_MASK, POWER,     PPCNONE,        {RS}},
4200 {"mtdsisr",     XSPR(31,467, 18), XSPR_MASK, COM,       TITAN,          {RS}},
4201 {"mtdar",       XSPR(31,467, 19), XSPR_MASK, COM,       TITAN,          {RS}},
4202 {"mtrtcu",      XSPR(31,467, 20), XSPR_MASK, COM,       TITAN,          {RS}},
4203 {"mtrtcl",      XSPR(31,467, 21), XSPR_MASK, COM,       TITAN,          {RS}},
4204 {"mtdec",       XSPR(31,467, 22), XSPR_MASK, COM,       PPCNONE,        {RS}},
4205 {"mtsdr0",      XSPR(31,467, 24), XSPR_MASK, POWER,     PPCNONE,        {RS}},
4206 {"mtsdr1",      XSPR(31,467, 25), XSPR_MASK, COM,       TITAN,          {RS}},
4207 {"mtsrr0",      XSPR(31,467, 26), XSPR_MASK, COM,       PPCNONE,        {RS}},
4208 {"mtsrr1",      XSPR(31,467, 27), XSPR_MASK, COM,       PPCNONE,        {RS}},
4209 {"mtcfar",      XSPR(31,467, 28), XSPR_MASK, POWER6,    PPCNONE,        {RS}},
4210 {"mtpid",       XSPR(31,467, 48), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4211 {"mtdecar",     XSPR(31,467, 54), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4212 {"mtcsrr0",     XSPR(31,467, 58), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4213 {"mtcsrr1",     XSPR(31,467, 59), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4214 {"mtdear",      XSPR(31,467, 61), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4215 {"mtesr",       XSPR(31,467, 62), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4216 {"mtivpr",      XSPR(31,467, 63), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4217 {"mtcmpa",      XSPR(31,467,144), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4218 {"mtcmpb",      XSPR(31,467,145), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4219 {"mtcmpc",      XSPR(31,467,146), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4220 {"mtcmpd",      XSPR(31,467,147), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4221 {"mticr",       XSPR(31,467,148), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4222 {"mtder",       XSPR(31,467,149), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4223 {"mtcounta",    XSPR(31,467,150), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4224 {"mtcountb",    XSPR(31,467,151), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4225 {"mtcmpe",      XSPR(31,467,152), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4226 {"mtcmpf",      XSPR(31,467,153), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4227 {"mtcmpg",      XSPR(31,467,154), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4228 {"mtcmph",      XSPR(31,467,155), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4229 {"mtlctrl1",    XSPR(31,467,156), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4230 {"mtlctrl2",    XSPR(31,467,157), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4231 {"mtictrl",     XSPR(31,467,158), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4232 {"mtbar",       XSPR(31,467,159), XSPR_MASK, PPC860,    PPCNONE,        {RS}},
4233 {"mtvrsave",    XSPR(31,467,256), XSPR_MASK, PPCVEC,    PPCNONE,        {RS}},
4234 {"mtusprg0",    XSPR(31,467,256), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4235 {"mtsprg",      XSPR(31,467,256), XSPRG_MASK,PPC,       PPCNONE,        {SPRG, RS}},
4236 {"mtsprg0",     XSPR(31,467,272), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4237 {"mtsprg1",     XSPR(31,467,273), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4238 {"mtsprg2",     XSPR(31,467,274), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4239 {"mtsprg3",     XSPR(31,467,275), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4240 {"mtsprg4",     XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4241 {"mtsprg5",     XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4242 {"mtsprg6",     XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4243 {"mtsprg7",     XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE,     {RS}},
4244 {"mtasr",       XSPR(31,467,280), XSPR_MASK, PPC64,     PPCNONE,        {RS}},
4245 {"mtear",       XSPR(31,467,282), XSPR_MASK, PPC,       TITAN,          {RS}},
4246 {"mttbl",       XSPR(31,467,284), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4247 {"mttbu",       XSPR(31,467,285), XSPR_MASK, PPC,       PPCNONE,        {RS}},
4248 {"mtdbsr",      XSPR(31,467,304), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4249 {"mtdbcr0",     XSPR(31,467,308), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4250 {"mtdbcr1",     XSPR(31,467,309), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4251 {"mtdbcr2",     XSPR(31,467,310), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4252 {"mtiac1",      XSPR(31,467,312), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4253 {"mtiac2",      XSPR(31,467,313), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4254 {"mtiac3",      XSPR(31,467,314), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4255 {"mtiac4",      XSPR(31,467,315), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4256 {"mtdac1",      XSPR(31,467,316), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4257 {"mtdac2",      XSPR(31,467,317), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4258 {"mtdvc1",      XSPR(31,467,318), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4259 {"mtdvc2",      XSPR(31,467,319), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4260 {"mttsr",       XSPR(31,467,336), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4261 {"mttcr",       XSPR(31,467,340), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4262 {"mtivor0",     XSPR(31,467,400), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4263 {"mtivor1",     XSPR(31,467,401), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4264 {"mtivor2",     XSPR(31,467,402), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4265 {"mtivor3",     XSPR(31,467,403), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4266 {"mtivor4",     XSPR(31,467,404), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4267 {"mtivor5",     XSPR(31,467,405), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4268 {"mtivor6",     XSPR(31,467,406), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4269 {"mtivor7",     XSPR(31,467,407), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4270 {"mtivor8",     XSPR(31,467,408), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4271 {"mtivor9",     XSPR(31,467,409), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4272 {"mtivor10",    XSPR(31,467,410), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4273 {"mtivor11",    XSPR(31,467,411), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4274 {"mtivor12",    XSPR(31,467,412), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4275 {"mtivor13",    XSPR(31,467,413), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4276 {"mtivor14",    XSPR(31,467,414), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4277 {"mtivor15",    XSPR(31,467,415), XSPR_MASK, BOOKE,     PPCNONE,        {RS}},
4278 {"mtspefscr",   XSPR(31,467,512), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4279 {"mtbbear",     XSPR(31,467,513), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
4280 {"mtbbtar",     XSPR(31,467,514), XSPR_MASK, PPCBRLK,   PPCNONE,        {RS}},
4281 {"mtivor32",    XSPR(31,467,528), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4282 {"mtibatu",     XSPR(31,467,528), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
4283 {"mtivor33",    XSPR(31,467,529), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4284 {"mtibatl",     XSPR(31,467,529), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
4285 {"mtivor34",    XSPR(31,467,530), XSPR_MASK, PPCSPE,    PPCNONE,        {RS}},
4286 {"mtivor35",    XSPR(31,467,531), XSPR_MASK, PPCPMR,    PPCNONE,        {RS}},
4287 {"mtdbatu",     XSPR(31,467,536), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
4288 {"mtdbatl",     XSPR(31,467,537), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
4289 {"mtmcsrr0",    XSPR(31,467,570), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
4290 {"mtmcsrr1",    XSPR(31,467,571), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
4291 {"mtmcsr",      XSPR(31,467,572), XSPR_MASK, PPCRFMCI,  PPCNONE,        {RS}},
4292 {"mtivndx",     XSPR(31,467,880), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4293 {"mtdvndx",     XSPR(31,467,881), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4294 {"mtivlim",     XSPR(31,467,882), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4295 {"mtdvlim",     XSPR(31,467,883), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4296 {"mtclcsr",     XSPR(31,467,884), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4297 {"mtccr1",      XSPR(31,467,888), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4298 {"mtummcr0",    XSPR(31,467,936), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4299 {"mtupmc1",     XSPR(31,467,937), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4300 {"mtupmc2",     XSPR(31,467,938), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4301 {"mtusia",      XSPR(31,467,939), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4302 {"mtummcr1",    XSPR(31,467,940), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4303 {"mtupmc3",     XSPR(31,467,941), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4304 {"mtupmc4",     XSPR(31,467,942), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4305 {"mtzpr",       XSPR(31,467,944), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4306 {"mtpid",       XSPR(31,467,945), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4307 {"mtrmmucr",    XSPR(31,467,946), XSPR_MASK, TITAN,     PPCNONE,        {RS}},
4308 {"mtccr0",      XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, PPCNONE,     {RS}},
4309 {"mtiac3",      XSPR(31,467,948), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4310 {"mtiac4",      XSPR(31,467,949), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4311 {"mtdvc1",      XSPR(31,467,950), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4312 {"mtdvc2",      XSPR(31,467,951), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4313 {"mtmmcr0",     XSPR(31,467,952), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4314 {"mtpmc1",      XSPR(31,467,953), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4315 {"mtsgr",       XSPR(31,467,953), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4316 {"mtdcwr",      XSPR(31,467,954), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4317 {"mtpmc2",      XSPR(31,467,954), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4318 {"mtsia",       XSPR(31,467,955), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4319 {"mtsler",      XSPR(31,467,955), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4320 {"mtmmcr1",     XSPR(31,467,956), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4321 {"mtsu0r",      XSPR(31,467,956), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4322 {"mtdbcr1",     XSPR(31,467,957), XSPR_MASK, PPC405,    PPCNONE,        {RS}},
4323 {"mtpmc3",      XSPR(31,467,957), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4324 {"mtpmc4",      XSPR(31,467,958), XSPR_MASK, PPC750,    PPCNONE,        {RS}},
4325 {"mticdbdr",    XSPR(31,467,979), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4326 {"mtesr",       XSPR(31,467,980), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4327 {"mtdear",      XSPR(31,467,981), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4328 {"mtevpr",      XSPR(31,467,982), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4329 {"mtcdbcr",     XSPR(31,467,983), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4330 {"mttsr",       XSPR(31,467,984), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4331 {"mttcr",       XSPR(31,467,986), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4332 {"mtpit",       XSPR(31,467,987), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4333 {"mttbhi",      XSPR(31,467,988), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4334 {"mttblo",      XSPR(31,467,989), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4335 {"mtsrr2",      XSPR(31,467,990), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4336 {"mtsrr3",      XSPR(31,467,991), XSPR_MASK, PPC403,    PPCNONE,        {RS}},
4337 {"mtdbsr",      XSPR(31,467,1008), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4338 {"mtdbdr",      XSPR(31,467,1011), XSPR_MASK, TITAN,    PPCNONE,        {RS}},
4339 {"mtdbcr0",     XSPR(31,467,1010), XSPR_MASK, PPC405,   PPCNONE,        {RS}},
4340 {"mtiac1",      XSPR(31,467,1012), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4341 {"mtiac2",      XSPR(31,467,1013), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4342 {"mtdac1",      XSPR(31,467,1014), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4343 {"mtdac2",      XSPR(31,467,1015), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4344 {"mtl2cr",      XSPR(31,467,1017), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4345 {"mtdccr",      XSPR(31,467,1018), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4346 {"mticcr",      XSPR(31,467,1019), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4347 {"mtictc",      XSPR(31,467,1019), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4348 {"mtpbl1",      XSPR(31,467,1020), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4349 {"mtthrm1",     XSPR(31,467,1020), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4350 {"mtpbu1",      XSPR(31,467,1021), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4351 {"mtthrm2",     XSPR(31,467,1021), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4352 {"mtpbl2",      XSPR(31,467,1022), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4353 {"mtthrm3",     XSPR(31,467,1022), XSPR_MASK, PPC750,   PPCNONE,        {RS}},
4354 {"mtpbu2",      XSPR(31,467,1023), XSPR_MASK, PPC403,   PPCNONE,        {RS}},
4355 {"mtspr",       X(31,467),        X_MASK,    COM,       PPCNONE,        {SPR, RS}},
4356
4357 {"dcbi",        X(31,470),      XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4358
4359 {"nand",        XRC(31,476,0),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4360 {"nand.",       XRC(31,476,1),  X_MASK,      COM,       PPCNONE,        {RA, RS, RB}},
4361
4362 {"dsn",         X(31,483),      XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
4363
4364 {"dcread",      X(31,486),      X_MASK,  PPC403|PPC440, PPCA2|PPC476,   {RT, RA, RB}},
4365
4366 {"icbtls",      X(31,486),      X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,  {CT, RA, RB}},
4367
4368 {"stvxl",       X(31,487),      X_MASK,      PPCVEC,    PPCNONE,        {VS, RA, RB}},
4369
4370 {"nabs",        XO(31,488,0,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4371 {"nabs.",       XO(31,488,0,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4372
4373 {"divd",        XO(31,489,0,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4374 {"divd.",       XO(31,489,0,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4375
4376 {"divw",        XO(31,491,0,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4377 {"divw.",       XO(31,491,0,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4378
4379 {"icbtlse",     X(31,494),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
4380
4381 {"slbia",       X(31,498),      0xffffffff,  PPC64,     PPCNONE,        {0}},
4382
4383 {"cli",         X(31,502),      XRB_MASK,    POWER,     PPCNONE,        {RT, RA}},
4384
4385 {"popcntd",     X(31,506),      XRB_MASK, POWER7|PPCA2, PPCNONE,        {RA, RS}},
4386
4387 {"cmpb",        X(31,508),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {RA, RS, RB}},
4388
4389 {"mcrxr",       X(31,512), XRARB_MASK|(3<<21), COM,     POWER7,         {BF}},
4390
4391 {"lbdx",        X(31,515),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4392
4393 {"bblels",      X(31,518),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
4394
4395 {"lvlx",        X(31,519),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4396 {"lbfcmux",     APU(31,519,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4397
4398 {"subfco",      XO(31,8,1,0),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4399 {"sfo",         XO(31,8,1,0),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4400 {"subco",       XO(31,8,1,0),   XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
4401 {"subfco.",     XO(31,8,1,1),   XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4402 {"sfo.",        XO(31,8,1,1),   XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4403 {"subco.",      XO(31,8,1,1),   XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
4404
4405 {"addco",       XO(31,10,1,0),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4406 {"ao",          XO(31,10,1,0),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4407 {"addco.",      XO(31,10,1,1),  XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4408 {"ao.",         XO(31,10,1,1),  XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4409
4410 {"clcs",        X(31,531),      XRB_MASK,    M601,      PPCNONE,        {RT, RA}},
4411
4412 {"ldbrx",       X(31,532),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RT, RA0, RB}},
4413
4414 {"lswx",        X(31,533),      X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
4415 {"lsx",         X(31,533),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4416
4417 {"lwbrx",       X(31,534),      X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
4418 {"lbrx",        X(31,534),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4419
4420 {"lfsx",        X(31,535),      X_MASK,      COM,       PPCNONE,        {FRT, RA0, RB}},
4421
4422 {"srw",         XRC(31,536,0),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4423 {"sr",          XRC(31,536,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4424 {"srw.",        XRC(31,536,1),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4425 {"sr.",         XRC(31,536,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4426
4427 {"rrib",        XRC(31,537,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4428 {"rrib.",       XRC(31,537,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4429
4430 {"srd",         XRC(31,539,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4431 {"srd.",        XRC(31,539,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4432
4433 {"maskir",      XRC(31,541,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4434 {"maskir.",     XRC(31,541,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4435
4436 {"lhdx",        X(31,547),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4437
4438 {"bbelr",       X(31,550),      X_MASK,      PPCBRLK,   PPCNONE,        {0}},
4439
4440 {"lvrx",        X(31,551),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4441 {"lhfcmux",     APU(31,551,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4442
4443 {"subfo",       XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4444 {"subo",        XO(31,40,1,0),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
4445 {"subfo.",      XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4446 {"subo.",       XO(31,40,1,1),  XO_MASK,     PPC,       PPCNONE,        {RT, RB, RA}},
4447
4448 {"tlbsync",     X(31,566),      0xffffffff,  PPC,       PPCNONE,        {0}},
4449
4450 {"lfsux",       X(31,567),      X_MASK,      COM,       PPCNONE,        {FRT, RAS, RB}},
4451
4452 {"lwdx",        X(31,579),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4453
4454 {"lwfcmux",     APU(31,583,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4455
4456 {"lxsdx",       X(31,588),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
4457
4458 {"mfsr",        X(31,595), XRB_MASK|(1<<20), COM32,     TITAN,          {RT, SR}},
4459
4460 {"lswi",        X(31,597),      X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, NB}},
4461 {"lsi",         X(31,597),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA0, NB}},
4462
4463 {"lwsync",      XSYNC(31,598,1), 0xffffffff, PPC,       PPCNONE,        {0}},
4464 {"ptesync",     XSYNC(31,598,2), 0xffffffff, PPC64,     PPCNONE,        {0}},
4465 {"sync",        X(31,598),      XSYNC_MASK,  PPCCOM,    BOOKE|PPC476,   {LS}},
4466 {"msync",       X(31,598),      0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
4467 {"dcs",         X(31,598),      0xffffffff,  PWRCOM,    PPCNONE,        {0}},
4468
4469 {"lfdx",        X(31,599),      X_MASK,      COM,       PPCNONE,        {FRT, RA0, RB}},
4470
4471 {"mffgpr",      XRC(31,607,0),  XRA_MASK,    POWER6,    POWER7,         {FRT, RB}},
4472 {"lfdepx",      X(31,607),      X_MASK,   E500MC|PPCA2, PPCNONE,        {FRT, RA, RB}},
4473
4474 {"lddx",        X(31,611),      X_MASK,      E500MC,    PPCNONE,        {RT, RA, RB}},
4475
4476 {"lqfcmux",     APU(31,615,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4477
4478 {"nego",        XO(31,104,1,0), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
4479 {"nego.",       XO(31,104,1,1), XORB_MASK,   COM,       PPCNONE,        {RT, RA}},
4480
4481 {"mulo",        XO(31,107,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4482 {"mulo.",       XO(31,107,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4483
4484 {"mfsri",       X(31,627),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4485
4486 {"dclst",       X(31,630),      XRB_MASK,    PWRCOM,    PPCNONE,        {RS, RA}},
4487
4488 {"lfdux",       X(31,631),      X_MASK,      COM,       PPCNONE,        {FRT, RAS, RB}},
4489
4490 {"stbdx",       X(31,643),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4491
4492 {"stvlx",       X(31,647),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4493 {"stbfcmux",    APU(31,647,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4494
4495 {"subfeo",      XO(31,136,1,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4496 {"sfeo",        XO(31,136,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4497 {"subfeo.",     XO(31,136,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4498 {"sfeo.",       XO(31,136,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4499
4500 {"addeo",       XO(31,138,1,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4501 {"aeo",         XO(31,138,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4502 {"addeo.",      XO(31,138,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4503 {"aeo.",        XO(31,138,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4504
4505 {"mfsrin",      X(31,659),      XRA_MASK,    PPC32,     TITAN,          {RT, RB}},
4506
4507 {"stdbrx",      X(31,660),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RS, RA0, RB}},
4508
4509 {"stswx",       X(31,661),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, RB}},
4510 {"stsx",        X(31,661),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
4511
4512 {"stwbrx",      X(31,662),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, RB}},
4513 {"stbrx",       X(31,662),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
4514
4515 {"stfsx",       X(31,663),      X_MASK,      COM,       PPCNONE,        {FRS, RA0, RB}},
4516
4517 {"srq",         XRC(31,664,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4518 {"srq.",        XRC(31,664,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4519
4520 {"sre",         XRC(31,665,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4521 {"sre.",        XRC(31,665,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4522
4523 {"sthdx",       X(31,675),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4524
4525 {"stvrx",       X(31,679),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4526 {"sthfcmux",    APU(31,679,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4527
4528 {"wclrone",     XOPL2(31,694,2),XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
4529 {"wclrall",     X(31,694),      XRARB_MASK,  PPCA2,     PPCNONE,        {L}},
4530 {"wclr",        X(31,694),      X_MASK,      PPCA2,     PPCNONE,        {L, RA0, RB}},
4531
4532 {"stbcx.",      XRC(31,694,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},
4533
4534 {"stfsux",      X(31,695),      X_MASK,      COM,       PPCNONE,        {FRS, RAS, RB}},
4535
4536 {"sriq",        XRC(31,696,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4537 {"sriq.",       XRC(31,696,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4538
4539 {"stwdx",       X(31,707),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4540
4541 {"stwfcmux",    APU(31,711,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4542
4543 {"stxsdx",      X(31,716),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
4544
4545 {"subfzeo",     XO(31,200,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4546 {"sfzeo",       XO(31,200,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4547 {"subfzeo.",    XO(31,200,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4548 {"sfzeo.",      XO(31,200,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4549
4550 {"addzeo",      XO(31,202,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4551 {"azeo",        XO(31,202,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4552 {"addzeo.",     XO(31,202,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4553 {"azeo.",       XO(31,202,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4554
4555 {"stswi",       X(31,725),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, NB}},
4556 {"stsi",        X(31,725),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, NB}},
4557
4558 {"sthcx.",      XRC(31,726,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},
4559
4560 {"stfdx",       X(31,727),      X_MASK,      COM,       PPCNONE,        {FRS, RA0, RB}},
4561
4562 {"srlq",        XRC(31,728,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4563 {"srlq.",       XRC(31,728,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4564
4565 {"sreq",        XRC(31,729,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4566 {"sreq.",       XRC(31,729,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4567
4568 {"mftgpr",      XRC(31,735,0),  XRA_MASK,    POWER6,    POWER7,         {RT, FRB}},
4569 {"stfdepx",     X(31,735),      X_MASK,   E500MC|PPCA2, PPCNONE,        {FRS, RA, RB}},
4570
4571 {"stddx",       X(31,739),      X_MASK,      E500MC,    PPCNONE,        {RS, RA, RB}},
4572
4573 {"stqfcmux",    APU(31,743,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4574
4575 {"subfmeo",     XO(31,232,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4576 {"sfmeo",       XO(31,232,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4577 {"subfmeo.",    XO(31,232,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4578 {"sfmeo.",      XO(31,232,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4579
4580 {"mulldo",      XO(31,233,1,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4581 {"mulldo.",     XO(31,233,1,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4582
4583 {"addmeo",      XO(31,234,1,0), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4584 {"ameo",        XO(31,234,1,0), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4585 {"addmeo.",     XO(31,234,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
4586 {"ameo.",       XO(31,234,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
4587
4588 {"mullwo",      XO(31,235,1,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4589 {"mulso",       XO(31,235,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4590 {"mullwo.",     XO(31,235,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4591 {"mulso.",      XO(31,235,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4592
4593 {"dcba",        X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
4594 {"dcbal",       XOPL(31,758,1), XRT_MASK,    E500MC,    PPCNONE,        {RA, RB}},
4595
4596 {"stfdux",      X(31,759),      X_MASK,      COM,       PPCNONE,        {FRS, RAS, RB}},
4597
4598 {"srliq",       XRC(31,760,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4599 {"srliq.",      XRC(31,760,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4600
4601 {"lvlxl",       X(31,775),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4602 {"ldfcmux",     APU(31,775,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4603
4604 {"dozo",        XO(31,264,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4605 {"dozo.",       XO(31,264,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4606
4607 {"addo",        XO(31,266,1,0), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4608 {"caxo",        XO(31,266,1,0), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4609 {"addo.",       XO(31,266,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
4610 {"caxo.",       XO(31,266,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
4611
4612 {"lxvw4x",      X(31,780),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
4613
4614 {"tlbivax",     X(31,786),      XRT_MASK,  BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
4615
4616 {"lwzcix",      X(31,789),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4617
4618 {"lhbrx",       X(31,790),      X_MASK,      COM,       PPCNONE,        {RT, RA0, RB}},
4619
4620 {"lfdpx",       X(31,791),      X_MASK,      POWER6,    POWER7,         {FRT, RA, RB}},
4621 {"lfqx",        X(31,791),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
4622
4623 {"sraw",        XRC(31,792,0),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4624 {"sra",         XRC(31,792,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4625 {"sraw.",       XRC(31,792,1),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, RB}},
4626 {"sra.",        XRC(31,792,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, RB}},
4627
4628 {"srad",        XRC(31,794,0),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4629 {"srad.",       XRC(31,794,1),  X_MASK,      PPC64,     PPCNONE,        {RA, RS, RB}},
4630
4631 {"lfddx",       X(31,803),      X_MASK,      E500MC,    PPCNONE,        {FRT, RA, RB}},
4632
4633 {"lvrxl",       X(31,807),      X_MASK,      CELL,      PPCNONE,        {VD, RA0, RB}},
4634
4635 {"rac",         X(31,818),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
4636
4637 {"erativax",    X(31,819),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA0, RB}},
4638
4639 {"lhzcix",      X(31,821),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4640
4641 {"dss",         XDSS(31,822,0), XDSS_MASK,   PPCVEC,    PPCNONE,        {STRM}},
4642
4643 {"lfqux",       X(31,823),      X_MASK,      POWER2,    PPCNONE,        {FRT, RA, RB}},
4644
4645 {"srawi",       XRC(31,824,0),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH}},
4646 {"srai",        XRC(31,824,0),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
4647 {"srawi.",      XRC(31,824,1),  X_MASK,      PPCCOM,    PPCNONE,        {RA, RS, SH}},
4648 {"srai.",       XRC(31,824,1),  X_MASK,      PWRCOM,    PPCNONE,        {RA, RS, SH}},
4649
4650 {"sradi",       XS(31,413,0),   XS_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6}},
4651 {"sradi.",      XS(31,413,1),   XS_MASK,     PPC64,     PPCNONE,        {RA, RS, SH6}},
4652
4653 {"divo",        XO(31,331,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4654 {"divo.",       XO(31,331,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4655
4656 {"lxvd2x",      X(31,844),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
4657
4658 {"tlbsrx.",     XRC(31,850,1),  XRT_MASK,    PPCA2,     PPCNONE,        {RA, RB}},
4659
4660 {"slbmfev",     X(31,851),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
4661
4662 {"lbzcix",      X(31,853),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4663
4664 {"eieio",       X(31,854),      0xffffffff,  PPC,   BOOKE|PPCA2|PPC476, {0}},
4665 {"mbar",        X(31,854),      X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,    {MO}},
4666 {"eieio",       X(31,854),      0xffffffff, PPCA2|PPC476, PPCNONE,      {0}},
4667
4668 {"lfiwax",      X(31,855),      X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, RA0, RB}},
4669
4670 {"abso",        XO(31,360,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4671 {"abso.",       XO(31,360,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4672
4673 {"divso",       XO(31,363,1,0), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4674 {"divso.",      XO(31,363,1,1), XO_MASK,     M601,      PPCNONE,        {RT, RA, RB}},
4675
4676 {"ldcix",       X(31,885),      X_MASK,      POWER6,    PPCNONE,        {RT, RA0, RB}},
4677
4678 {"lfiwzx",      X(31,887),      X_MASK,   POWER7|PPCA2, PPCNONE,        {FRT, RA0, RB}},
4679
4680 {"stvlxl",      X(31,903),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4681 {"stdfcmux",    APU(31,903,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
4682
4683 {"divdeuo",     XO(31,393,1,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4684 {"divdeuo.",    XO(31,393,1,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4685 {"divweuo",     XO(31,395,1,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4686 {"divweuo.",    XO(31,395,1,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4687
4688 {"stxvw4x",     X(31,908),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
4689
4690 {"tlbsx",       XRC(31,914,0),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
4691 {"tlbsx.",      XRC(31,914,1),  X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
4692
4693 {"slbmfee",     X(31,915),      XRA_MASK,    PPC64,     PPCNONE,        {RT, RB}},
4694
4695 {"stwcix",      X(31,917),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4696
4697 {"sthbrx",      X(31,918),      X_MASK,      COM,       PPCNONE,        {RS, RA0, RB}},
4698
4699 {"stfdpx",      X(31,919),      X_MASK,      POWER6,    PPCNONE,        {FRS, RA, RB}},
4700 {"stfqx",       X(31,919),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA, RB}},
4701
4702 {"sraq",        XRC(31,920,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4703 {"sraq.",       XRC(31,920,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4704
4705 {"srea",        XRC(31,921,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4706 {"srea.",       XRC(31,921,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, RB}},
4707
4708 {"extsh",       XRC(31,922,0),  XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
4709 {"exts",        XRC(31,922,0),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4710 {"extsh.",      XRC(31,922,1),  XRB_MASK,    PPCCOM,    PPCNONE,        {RA, RS}},
4711 {"exts.",       XRC(31,922,1),  XRB_MASK,    PWRCOM,    PPCNONE,        {RA, RS}},
4712
4713 {"stfddx",      X(31,931),      X_MASK,      E500MC,    PPCNONE,        {FRS, RA, RB}},
4714
4715 {"stvrxl",      X(31,935),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
4716
4717 {"divdeo",      XO(31,425,1,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4718 {"divdeo.",     XO(31,425,1,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4719 {"divweo",      XO(31,427,1,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4720 {"divweo.",     XO(31,427,1,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
4721
4722 {"tlbrehi",     XTLB(31,946,0), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
4723 {"tlbrelo",     XTLB(31,946,1), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
4724 {"tlbre",       X(31,946),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
4725
4726 {"sthcix",      X(31,949),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4727
4728 {"stfqux",      X(31,951),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA, RB}},
4729
4730 {"sraiq",       XRC(31,952,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4731 {"sraiq.",      XRC(31,952,1),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},
4732
4733 {"extsb",       XRC(31,954,0),  XRB_MASK,    PPC,       PPCNONE,        {RA, RS}},
4734 {"extsb.",      XRC(31,954,1),  XRB_MASK,    PPC,       PPCNONE,        {RA, RS}},
4735
4736 {"iccci",       X(31,966),     XRT_MASK, PPC403|PPC440|TITAN, PPC476,   {RA, RB}},
4737 {"ici",         X(31,966),      XRARB_MASK,  PPCA2|PPC476, PPCNONE,     {CT}},
4738
4739 {"divduo",      XO(31,457,1,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4740 {"divduo.",     XO(31,457,1,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4741
4742 {"divwuo",      XO(31,459,1,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4743 {"divwuo.",     XO(31,459,1,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4744
4745 {"stxvd2x",     X(31,972),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
4746
4747 {"tlbld",       X(31,978),      XRTRA_MASK,  PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
4748 {"tlbwehi",     XTLB(31,978,0), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
4749 {"tlbwelo",     XTLB(31,978,1), XTLB_MASK,   PPC403,    PPCNONE,        {RT, RA}},
4750 {"tlbwe",       X(31,978),      X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
4751
4752 {"stbcix",      X(31,981),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4753
4754 {"icbi",        X(31,982),      XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4755
4756 {"stfiwx",      X(31,983),      X_MASK,      PPC,       PPCNONE,        {FRS, RA0, RB}},
4757
4758 {"extsw",       XRC(31,986,0),  XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
4759 {"extsw.",      XRC(31,986,1),  XRB_MASK,    PPC64,     PPCNONE,        {RA, RS}},
4760
4761 {"icbiep",      XRT(31,991,0),  XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
4762
4763 {"icread",      X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE, {RA, RB}},
4764
4765 {"nabso",       XO(31,488,1,0), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4766 {"nabso.",      XO(31,488,1,1), XORB_MASK,   M601,      PPCNONE,        {RT, RA}},
4767
4768 {"divdo",       XO(31,489,1,0), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4769 {"divdo.",      XO(31,489,1,1), XO_MASK,     PPC64,     PPCNONE,        {RT, RA, RB}},
4770
4771 {"divwo",       XO(31,491,1,0), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4772 {"divwo.",      XO(31,491,1,1), XO_MASK,     PPC,       PPCNONE,        {RT, RA, RB}},
4773
4774 {"tlbli",       X(31,1010),     XRTRA_MASK,  PPC,       TITAN,          {RB}},
4775
4776 {"stdcix",      X(31,1013),     X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
4777
4778 {"dcbz",        X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4779 {"dclz",        X(31,1014),     XRT_MASK,    PPC,       PPCNONE,        {RA, RB}},
4780
4781 {"dcbzep",      XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, PPCNONE,        {RA, RB}},
4782
4783 {"dcbzl",       XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476,       {RA, RB}},
4784
4785 {"cctpl",       0x7c210b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4786 {"cctpm",       0x7c421378,     0xffffffff,  CELL,      PPCNONE,        {0}},
4787 {"cctph",       0x7c631b78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4788
4789 {"dstt",        XDSS(31,342,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4790 {"dststt",      XDSS(31,374,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {RA, RB, STRM}},
4791 {"dssall",      XDSS(31,822,1), XDSS_MASK,   PPCVEC,    PPCNONE,        {0}},
4792
4793 {"db8cyc",      0x7f9ce378,     0xffffffff,  CELL,      PPCNONE,        {0}},
4794 {"db10cyc",     0x7fbdeb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4795 {"db12cyc",     0x7fdef378,     0xffffffff,  CELL,      PPCNONE,        {0}},
4796 {"db16cyc",     0x7ffffb78,     0xffffffff,  CELL,      PPCNONE,        {0}},
4797
4798 {"lwz",         OP(32),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RA0}},
4799 {"l",           OP(32),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
4800
4801 {"lwzu",        OP(33),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAL}},
4802 {"lu",          OP(33),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
4803
4804 {"lbz",         OP(34),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
4805
4806 {"lbzu",        OP(35),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
4807
4808 {"stw",         OP(36),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
4809 {"st",          OP(36),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
4810
4811 {"stwu",        OP(37),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RAS}},
4812 {"stu",         OP(37),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
4813
4814 {"stb",         OP(38),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
4815
4816 {"stbu",        OP(39),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
4817
4818 {"lhz",         OP(40),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
4819
4820 {"lhzu",        OP(41),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
4821
4822 {"lha",         OP(42),         OP_MASK,     COM,       PPCNONE,        {RT, D, RA0}},
4823
4824 {"lhau",        OP(43),         OP_MASK,     COM,       PPCNONE,        {RT, D, RAL}},
4825
4826 {"sth",         OP(44),         OP_MASK,     COM,       PPCNONE,        {RS, D, RA0}},
4827
4828 {"sthu",        OP(45),         OP_MASK,     COM,       PPCNONE,        {RS, D, RAS}},
4829
4830 {"lmw",         OP(46),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, D, RAM}},
4831 {"lm",          OP(46),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, D, RA0}},
4832
4833 {"stmw",        OP(47),         OP_MASK,     PPCCOM,    PPCNONE,        {RS, D, RA0}},
4834 {"stm",         OP(47),         OP_MASK,     PWRCOM,    PPCNONE,        {RS, D, RA0}},
4835
4836 {"lfs",         OP(48),         OP_MASK,     COM,       PPCNONE,        {FRT, D, RA0}},
4837
4838 {"lfsu",        OP(49),         OP_MASK,     COM,       PPCNONE,        {FRT, D, RAS}},
4839
4840 {"lfd",         OP(50),         OP_MASK,     COM,       PPCNONE,        {FRT, D, RA0}},
4841
4842 {"lfdu",        OP(51),         OP_MASK,     COM,       PPCNONE,        {FRT, D, RAS}},
4843
4844 {"stfs",        OP(52),         OP_MASK,     COM,       PPCNONE,        {FRS, D, RA0}},
4845
4846 {"stfsu",       OP(53),         OP_MASK,     COM,       PPCNONE,        {FRS, D, RAS}},
4847
4848 {"stfd",        OP(54),         OP_MASK,     COM,       PPCNONE,        {FRS, D, RA0}},
4849
4850 {"stfdu",       OP(55),         OP_MASK,     COM,       PPCNONE,        {FRS, D, RAS}},
4851
4852 {"lq",          OP(56),         OP_MASK,     POWER4,    PPC476,         {RTQ, DQ, RAQ}},
4853 {"psq_l",       OP(56),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
4854 {"lfq",         OP(56),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
4855
4856 {"lfdp",        OP(57),         OP_MASK,     POWER6,    POWER7,         {FRT, D, RA0}},
4857 {"psq_lu",      OP(57),         OP_MASK,     PPCPS,     PPCNONE,        {FRT,PSD,RA,PSW,PSQ}},
4858 {"lfqu",        OP(57),         OP_MASK,     POWER2,    PPCNONE,        {FRT, D, RA0}},
4859
4860 {"ld",          DSO(58,0),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
4861 {"ldu",         DSO(58,1),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RAL}},
4862 {"lwa",         DSO(58,2),      DS_MASK,     PPC64,     PPCNONE,        {RT, DS, RA0}},
4863
4864 {"dadd",        XRC(59,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4865 {"dadd.",       XRC(59,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4866
4867 {"dqua",        ZRC(59,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
4868 {"dqua.",       ZRC(59,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRT,FRA,FRB,RMC}},
4869
4870 {"fdivs",       A(59,18,0),     AFRC_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRB}},
4871 {"fdivs.",      A(59,18,1),     AFRC_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRB}},
4872
4873 {"fsubs",       A(59,20,0),     AFRC_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRB}},
4874 {"fsubs.",      A(59,20,1),     AFRC_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRB}},
4875
4876 {"fadds",       A(59,21,0),     AFRC_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRB}},
4877 {"fadds.",      A(59,21,1),     AFRC_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRB}},
4878
4879 {"fsqrts",      A(59,22,0),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
4880 {"fsqrts.",     A(59,22,1),    AFRAFRC_MASK, PPC,       TITAN,          {FRT, FRB}},
4881
4882 {"fres",        A(59,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
4883 {"fres",        A(59,24,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
4884 {"fres.",       A(59,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
4885 {"fres.",       A(59,24,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
4886
4887 {"fmuls",       A(59,25,0),     AFRB_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRC}},
4888 {"fmuls.",      A(59,25,1),     AFRB_MASK,   PPC,       PPCNONE,        {FRT, FRA, FRC}},
4889
4890 {"frsqrtes",    A(59,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
4891 {"frsqrtes",    A(59,26,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
4892 {"frsqrtes.",   A(59,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
4893 {"frsqrtes.",   A(59,26,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
4894
4895 {"fmsubs",      A(59,28,0),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4896 {"fmsubs.",     A(59,28,1),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4897
4898 {"fmadds",      A(59,29,0),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4899 {"fmadds.",     A(59,29,1),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4900
4901 {"fnmsubs",     A(59,30,0),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4902 {"fnmsubs.",    A(59,30,1),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4903
4904 {"fnmadds",     A(59,31,0),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4905 {"fnmadds.",    A(59,31,1),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
4906
4907 {"dmul",        XRC(59,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4908 {"dmul.",       XRC(59,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4909
4910 {"drrnd",       ZRC(59,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
4911 {"drrnd.",      ZRC(59,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
4912
4913 {"dscli",       ZRC(59,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
4914 {"dscli.",      ZRC(59,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
4915
4916 {"dquai",       ZRC(59,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
4917 {"dquai.",      ZRC(59,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT,FRB,RMC}},
4918
4919 {"dscri",       ZRC(59,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
4920 {"dscri.",      ZRC(59,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
4921
4922 {"drintx",      ZRC(59,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
4923 {"drintx.",     ZRC(59,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
4924
4925 {"dcmpo",       X(59,130),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
4926
4927 {"dtstex",      X(59,162),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
4928 {"dtstdc",      Z(59,194),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DCM}},
4929 {"dtstdg",      Z(59,226),      Z_MASK,      POWER6,    PPCNONE,        {BF,  FRA, DGM}},
4930
4931 {"drintn",      ZRC(59,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
4932 {"drintn.",     ZRC(59,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
4933
4934 {"dctdp",       XRC(59,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4935 {"dctdp.",      XRC(59,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4936
4937 {"dctfix",      XRC(59,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4938 {"dctfix.",     XRC(59,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4939
4940 {"ddedpd",      XRC(59,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
4941 {"ddedpd.",     XRC(59,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
4942
4943 {"dxex",        XRC(59,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4944 {"dxex.",       XRC(59,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4945
4946 {"dsub",        XRC(59,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4947 {"dsub.",       XRC(59,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4948
4949 {"ddiv",        XRC(59,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4950 {"ddiv.",       XRC(59,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4951
4952 {"dcmpu",       X(59,642),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
4953
4954 {"dtstsf",      X(59,674),      X_MASK,      POWER6,    PPCNONE,        {BF,  FRA, FRB}},
4955
4956 {"drsp",        XRC(59,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4957 {"drsp.",       XRC(59,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
4958
4959 {"dcffix",      XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
4960 {"dcffix.",     XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCNONE,        {FRT, FRB}},
4961
4962 {"denbcd",      XRC(59,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
4963 {"denbcd.",     XRC(59,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
4964
4965 {"fcfids",      XRC(59,846,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
4966 {"fcfids.",     XRC(59,846,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
4967
4968 {"diex",        XRC(59,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4969 {"diex.",       XRC(59,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
4970
4971 {"fcfidus",     XRC(59,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
4972 {"fcfidus.",    XRC(59,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
4973
4974 {"xxsldwi",     XX3(60,2),      XX3SHW_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6, SHW}},
4975 {"xxsel",       XX4(60,3),      XX4_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6, XC6}},
4976 {"xxspltd",     XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6S, DMEX}},
4977 {"xxmrghd",     XX3(60,10),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4978 {"xxswapd",     XX3(60,10)|(2<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
4979 {"xxmrgld",     XX3(60,10)|(3<<8), XX3_MASK, PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4980 {"xxpermdi",    XX3(60,10),     XX3DM_MASK,  PPCVSX,    PPCNONE,        {XT6, XA6, XB6, DM}},
4981 {"xxmrghw",     XX3(60,18),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4982 {"xsadddp",     XX3(60,32),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4983 {"xsmaddadp",   XX3(60,33),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4984 {"xscmpudp",    XX3(60,35),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
4985 {"xssubdp",     XX3(60,40),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4986 {"xsmaddmdp",   XX3(60,41),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4987 {"xscmpodp",    XX3(60,43),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
4988 {"xsmuldp",     XX3(60,48),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4989 {"xsmsubadp",   XX3(60,49),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4990 {"xxmrglw",     XX3(60,50),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4991 {"xsdivdp",     XX3(60,56),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4992 {"xsmsubmdp",   XX3(60,57),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4993 {"xstdivdp",    XX3(60,61),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
4994 {"xvaddsp",     XX3(60,64),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4995 {"xvmaddasp",   XX3(60,65),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4996 {"xvcmpeqsp",   XX3RC(60,67,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4997 {"xvcmpeqsp.",  XX3RC(60,67,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4998 {"xvsubsp",     XX3(60,72),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
4999 {"xscvdpuxws",  XX2(60,72),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5000 {"xvmaddmsp",   XX3(60,73),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5001 {"xsrdpi",      XX2(60,73),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5002 {"xsrsqrtedp",  XX2(60,74),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5003 {"xssqrtdp",    XX2(60,75),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5004 {"xvcmpgtsp",   XX3RC(60,75,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5005 {"xvcmpgtsp.",  XX3RC(60,75,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5006 {"xvmulsp",     XX3(60,80),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5007 {"xvmsubasp",   XX3(60,81),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5008 {"xvcmpgesp",   XX3RC(60,83,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5009 {"xvcmpgesp.",  XX3RC(60,83,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5010 {"xvdivsp",     XX3(60,88),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5011 {"xscvdpsxws",  XX2(60,88),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5012 {"xvmsubmsp",   XX3(60,89),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5013 {"xsrdpiz",     XX2(60,89),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5014 {"xsredp",      XX2(60,90),     XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5015 {"xvtdivsp",    XX3(60,93),     XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5016 {"xvadddp",     XX3(60,96),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5017 {"xvmaddadp",   XX3(60,97),     XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5018 {"xvcmpeqdp",   XX3RC(60,99,0), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5019 {"xvcmpeqdp.",  XX3RC(60,99,1), XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5020 {"xvsubdp",     XX3(60,104),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5021 {"xvmaddmdp",   XX3(60,105),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5022 {"xsrdpip",     XX2(60,105),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5023 {"xstsqrtdp",   XX2(60,106),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5024 {"xsrdpic",     XX2(60,107),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5025 {"xvcmpgtdp",   XX3RC(60,107,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5026 {"xvcmpgtdp.",  XX3RC(60,107,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5027 {"xvmuldp",     XX3(60,112),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5028 {"xvmsubadp",   XX3(60,113),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5029 {"xvcmpgedp",   XX3RC(60,115,0), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5030 {"xvcmpgedp.",  XX3RC(60,115,1), XX3_MASK,   PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5031 {"xvdivdp",     XX3(60,120),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5032 {"xvmsubmdp",   XX3(60,121),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5033 {"xsrdpim",     XX2(60,121),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5034 {"xvtdivdp",    XX3(60,125),    XX3BF_MASK,  PPCVSX,    PPCNONE,        {BF, XA6, XB6}},
5035 {"xxland",      XX3(60,130),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5036 {"xvcvspuxws",  XX2(60,136),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5037 {"xvrspi",      XX2(60,137),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5038 {"xxlandc",     XX3(60,138),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5039 {"xvrsqrtesp",  XX2(60,138),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5040 {"xvsqrtsp",    XX2(60,139),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5041 {"xxlor",       XX3(60,146),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5042 {"xvcvspsxws",  XX2(60,152),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5043 {"xvrspiz",     XX2(60,153),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5044 {"xxlxor",      XX3(60,154),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5045 {"xvresp",      XX2(60,154),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5046 {"xsmaxdp",     XX3(60,160),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5047 {"xsnmaddadp",  XX3(60,161),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5048 {"xxlnor",      XX3(60,162),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5049 {"xxspltw",     XX2(60,164),    XX2UIM_MASK, PPCVSX,    PPCNONE,        {XT6, XB6, UIM}},
5050 {"xsmindp",     XX3(60,168),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5051 {"xvcvuxwsp",   XX2(60,168),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5052 {"xsnmaddmdp",  XX3(60,169),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5053 {"xvrspip",     XX2(60,169),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5054 {"xvtsqrtsp",   XX2(60,170),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5055 {"xvrspic",     XX2(60,171),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5056 {"xscpsgndp",   XX3(60,176),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5057 {"xsnmsubadp",  XX3(60,177),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5058 {"xvcvsxwsp",   XX2(60,184),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5059 {"xsnmsubmdp",  XX3(60,185),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5060 {"xvrspim",     XX2(60,185),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5061 {"xvmaxsp",     XX3(60,192),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5062 {"xvnmaddasp",  XX3(60,193),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5063 {"xvminsp",     XX3(60,200),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5064 {"xvcvdpuxws",  XX2(60,200),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5065 {"xvnmaddmsp",  XX3(60,201),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5066 {"xvrdpi",      XX2(60,201),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5067 {"xvrsqrtedp",  XX2(60,202),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5068 {"xvsqrtdp",    XX2(60,203),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5069 {"xvmovsp",     XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5070 {"xvcpsgnsp",   XX3(60,208),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5071 {"xvnmsubasp",  XX3(60,209),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5072 {"xvcvdpsxws",  XX2(60,216),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5073 {"xvnmsubmsp",  XX3(60,217),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5074 {"xvrdpiz",     XX2(60,217),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5075 {"xvredp",      XX2(60,218),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5076 {"xvmaxdp",     XX3(60,224),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5077 {"xvnmaddadp",  XX3(60,225),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5078 {"xvmindp",     XX3(60,232),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5079 {"xvnmaddmdp",  XX3(60,233),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5080 {"xvcvuxwdp",   XX2(60,232),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5081 {"xvrdpip",     XX2(60,233),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5082 {"xvtsqrtdp",   XX2(60,234),    XX2BF_MASK,  PPCVSX,    PPCNONE,        {BF, XB6}},
5083 {"xvrdpic",     XX2(60,235),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5084 {"xvmovdp",     XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6S}},
5085 {"xvcpsgndp",   XX3(60,240),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5086 {"xvnmsubadp",  XX3(60,241),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5087 {"xvcvsxwdp",   XX2(60,248),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5088 {"xvnmsubmdp",  XX3(60,249),    XX3_MASK,    PPCVSX,    PPCNONE,        {XT6, XA6, XB6}},
5089 {"xvrdpim",     XX2(60,249),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5090 {"xscvdpsp",    XX2(60,265),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5091 {"xscvdpuxds",  XX2(60,328),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5092 {"xscvspdp",    XX2(60,329),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5093 {"xscvdpsxds",  XX2(60,344),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5094 {"xsabsdp",     XX2(60,345),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5095 {"xscvuxddp",   XX2(60,360),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5096 {"xsnabsdp",    XX2(60,361),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5097 {"xscvsxddp",   XX2(60,376),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5098 {"xsnegdp",     XX2(60,377),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5099 {"xvcvspuxds",  XX2(60,392),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5100 {"xvcvdpsp",    XX2(60,393),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5101 {"xvcvspsxds",  XX2(60,408),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5102 {"xvabssp",     XX2(60,409),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5103 {"xvcvuxdsp",   XX2(60,424),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5104 {"xvnabssp",    XX2(60,425),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5105 {"xvcvsxdsp",   XX2(60,440),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5106 {"xvnegsp",     XX2(60,441),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5107 {"xvcvdpuxds",  XX2(60,456),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5108 {"xvcvspdp",    XX2(60,457),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5109 {"xvcvdpsxds",  XX2(60,472),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5110 {"xvabsdp",     XX2(60,473),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5111 {"xvcvuxddp",   XX2(60,488),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5112 {"xvnabsdp",    XX2(60,489),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5113 {"xvcvsxddp",   XX2(60,504),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5114 {"xvnegdp",     XX2(60,505),    XX2_MASK,    PPCVSX,    PPCNONE,        {XT6, XB6}},
5115
5116 {"psq_st",      OP(60),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
5117 {"stfq",        OP(60),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
5118
5119 {"stfdp",       OP(61),         OP_MASK,     POWER6,    PPCNONE,        {FRT, D, RA0}},
5120 {"psq_stu",     OP(61),         OP_MASK,     PPCPS,     PPCNONE,        {FRS,PSD,RA,PSW,PSQ}},
5121 {"stfqu",       OP(61),         OP_MASK,     POWER2,    PPCNONE,        {FRS, D, RA}},
5122
5123 {"std",         DSO(62,0),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RA0}},
5124 {"stdu",        DSO(62,1),      DS_MASK,     PPC64,     PPCNONE,        {RS, DS, RAS}},
5125 {"stq",         DSO(62,2),      DS_MASK,     POWER4,    PPC476,         {RSQ, DS, RA0}},
5126
5127 {"fcmpu",       X(63,0),     X_MASK|(3<<21), COM,       PPCNONE,        {BF, FRA, FRB}},
5128
5129 {"daddq",       XRC(63,2,0),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5130 {"daddq.",      XRC(63,2,1),    X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5131
5132 {"dquaq",       ZRC(63,3,0),    Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5133 {"dquaq.",      ZRC(63,3,1),    Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5134
5135 {"fcpsgn",      XRC(63,8,0),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
5136 {"fcpsgn.",     XRC(63,8,1),    X_MASK, POWER6|PPCA2|PPC476, PPCNONE,   {FRT, FRA, FRB}},
5137
5138 {"frsp",        XRC(63,12,0),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5139 {"frsp.",       XRC(63,12,1),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5140
5141 {"fctiw",       XRC(63,14,0),   XRA_MASK,    PPCCOM,    PPCNONE,        {FRT, FRB}},
5142 {"fcir",        XRC(63,14,0),   XRA_MASK,    POWER2,    PPCNONE,        {FRT, FRB}},
5143 {"fctiw.",      XRC(63,14,1),   XRA_MASK,    PPCCOM,    PPCNONE,        {FRT, FRB}},
5144 {"fcir.",       XRC(63,14,1),   XRA_MASK,    POWER2,    PPCNONE,        {FRT, FRB}},
5145
5146 {"fctiwz",      XRC(63,15,0),   XRA_MASK,    PPCCOM,    PPCNONE,        {FRT, FRB}},
5147 {"fcirz",       XRC(63,15,0),   XRA_MASK,    POWER2,    PPCNONE,        {FRT, FRB}},
5148 {"fctiwz.",     XRC(63,15,1),   XRA_MASK,    PPCCOM,    PPCNONE,        {FRT, FRB}},
5149 {"fcirz.",      XRC(63,15,1),   XRA_MASK,    POWER2,    PPCNONE,        {FRT, FRB}},
5150
5151 {"fdiv",        A(63,18,0),     AFRC_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRB}},
5152 {"fd",          A(63,18,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5153 {"fdiv.",       A(63,18,1),     AFRC_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRB}},
5154 {"fd.",         A(63,18,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5155
5156 {"fsub",        A(63,20,0),     AFRC_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRB}},
5157 {"fs",          A(63,20,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5158 {"fsub.",       A(63,20,1),     AFRC_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRB}},
5159 {"fs.",         A(63,20,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5160
5161 {"fadd",        A(63,21,0),     AFRC_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRB}},
5162 {"fa",          A(63,21,0),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5163 {"fadd.",       A(63,21,1),     AFRC_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRB}},
5164 {"fa.",         A(63,21,1),     AFRC_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRB}},
5165
5166 {"fsqrt",       A(63,22,0),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
5167 {"fsqrt.",      A(63,22,1),    AFRAFRC_MASK, PPCPWR2,   TITAN,          {FRT, FRB}},
5168
5169 {"fsel",        A(63,23,0),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
5170 {"fsel.",       A(63,23,1),     A_MASK,      PPC,       PPCNONE,        {FRT, FRA, FRC, FRB}},
5171
5172 {"fre",         A(63,24,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5173 {"fre",         A(63,24,0),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5174 {"fre.",        A(63,24,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5175 {"fre.",        A(63,24,1),   AFRALFRC_MASK, POWER5,    POWER7,         {FRT, FRB, A_L}},
5176
5177 {"fmul",        A(63,25,0),     AFRB_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRC}},
5178 {"fm",          A(63,25,0),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
5179 {"fmul.",       A(63,25,1),     AFRB_MASK,   PPCCOM,    PPCNONE,        {FRT, FRA, FRC}},
5180 {"fm.",         A(63,25,1),     AFRB_MASK,   PWRCOM,    PPCNONE,        {FRT, FRA, FRC}},
5181
5182 {"frsqrte",     A(63,26,0),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5183 {"frsqrte",     A(63,26,0),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
5184 {"frsqrte.",    A(63,26,1),   AFRAFRC_MASK,  POWER7,    PPCNONE,        {FRT, FRB}},
5185 {"frsqrte.",    A(63,26,1),   AFRALFRC_MASK, PPC,       POWER7,         {FRT, FRB, A_L}},
5186
5187 {"fmsub",       A(63,28,0),     A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5188 {"fms",         A(63,28,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5189 {"fmsub.",      A(63,28,1),     A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5190 {"fms.",        A(63,28,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5191
5192 {"fmadd",       A(63,29,0),     A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5193 {"fma",         A(63,29,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5194 {"fmadd.",      A(63,29,1),     A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5195 {"fma.",        A(63,29,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5196
5197 {"fnmsub",      A(63,30,0),     A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5198 {"fnms",        A(63,30,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5199 {"fnmsub.",     A(63,30,1),     A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5200 {"fnms.",       A(63,30,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5201
5202 {"fnmadd",      A(63,31,0),     A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5203 {"fnma",        A(63,31,0),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5204 {"fnmadd.",     A(63,31,1),     A_MASK,      PPCCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5205 {"fnma.",       A(63,31,1),     A_MASK,      PWRCOM,    PPCNONE,        {FRT, FRA, FRC, FRB}},
5206
5207 {"fcmpo",       X(63,32),    X_MASK|(3<<21), COM,       PPCNONE,        {BF, FRA, FRB}},
5208
5209 {"dmulq",       XRC(63,34,0),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5210 {"dmulq.",      XRC(63,34,1),   X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5211
5212 {"drrndq",      ZRC(63,35,0),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5213 {"drrndq.",     ZRC(63,35,1),   Z2_MASK,     POWER6,    PPCNONE,        {FRT, FRA, FRB, RMC}},
5214
5215 {"mtfsb1",      XRC(63,38,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
5216 {"mtfsb1.",     XRC(63,38,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
5217
5218 {"fneg",        XRC(63,40,0),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5219 {"fneg.",       XRC(63,40,1),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5220
5221 {"mcrfs",      X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCNONE,        {BF, BFA}},
5222
5223 {"dscliq",      ZRC(63,66,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5224 {"dscliq.",     ZRC(63,66,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5225
5226 {"dquaiq",      ZRC(63,67,0),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT, FRB, RMC}},
5227 {"dquaiq.",     ZRC(63,67,1),   Z2_MASK,     POWER6,    PPCNONE,        {TE, FRT, FRB, RMC}},
5228
5229 {"mtfsb0",      XRC(63,70,0),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
5230 {"mtfsb0.",     XRC(63,70,1),   XRARB_MASK,  COM,       PPCNONE,        {BT}},
5231
5232 {"fmr",         XRC(63,72,0),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5233 {"fmr.",        XRC(63,72,1),   XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5234
5235 {"dscriq",      ZRC(63,98,0),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5236 {"dscriq.",     ZRC(63,98,1),   Z_MASK,      POWER6,    PPCNONE,        {FRT, FRA, SH16}},
5237
5238 {"drintxq",     ZRC(63,99,0),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5239 {"drintxq.",    ZRC(63,99,1),   Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5240
5241 {"ftdiv",       X(63,128),   X_MASK|(3<<21), POWER7,    PPCNONE,        {BF, FRA, FRB}},
5242
5243 {"dcmpoq",      X(63,130),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
5244
5245 {"mtfsfi",  XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
5246 {"mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
5247 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}},
5248 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}},
5249
5250 {"fnabs",       XRC(63,136,0),  XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5251 {"fnabs.",      XRC(63,136,1),  XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5252
5253 {"fctiwu",      XRC(63,142,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5254 {"fctiwu.",     XRC(63,142,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5255 {"fctiwuz",     XRC(63,143,0),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5256 {"fctiwuz.",    XRC(63,143,1),  XRA_MASK,    POWER7,    PPCNONE,        {FRT, FRB}},
5257
5258 {"ftsqrt",      X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE,    {BF, FRB}},
5259
5260 {"dtstexq",     X(63,162),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
5261 {"dtstdcq",     Z(63,194),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRA, DCM}},
5262 {"dtstdgq",     Z(63,226),      Z_MASK,      POWER6,    PPCNONE,        {BF, FRA, DGM}},
5263
5264 {"drintnq",     ZRC(63,227,0),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5265 {"drintnq.",    ZRC(63,227,1),  Z2_MASK,     POWER6,    PPCNONE,        {R, FRT, FRB, RMC}},
5266
5267 {"dctqpq",      XRC(63,258,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5268 {"dctqpq.",     XRC(63,258,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5269
5270 {"fabs",        XRC(63,264,0),  XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5271 {"fabs.",       XRC(63,264,1),  XRA_MASK,    COM,       PPCNONE,        {FRT, FRB}},
5272
5273 {"dctfixq",     XRC(63,290,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5274 {"dctfixq.",    XRC(63,290,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5275
5276 {"ddedpdq",     XRC(63,322,0),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
5277 {"ddedpdq.",    XRC(63,322,1),  X_MASK,      POWER6,    PPCNONE,        {SP, FRT, FRB}},
5278
5279 {"dxexq",       XRC(63,354,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5280 {"dxexq.",      XRC(63,354,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5281
5282 {"frin",        XRC(63,392,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5283 {"frin.",       XRC(63,392,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5284 {"friz",        XRC(63,424,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5285 {"friz.",       XRC(63,424,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5286 {"frip",        XRC(63,456,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5287 {"frip.",       XRC(63,456,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5288 {"frim",        XRC(63,488,0),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5289 {"frim.",       XRC(63,488,1),  XRA_MASK,    POWER5,    PPCNONE,        {FRT, FRB}},
5290
5291 {"dsubq",       XRC(63,514,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5292 {"dsubq.",      XRC(63,514,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5293
5294 {"ddivq",       XRC(63,546,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5295 {"ddivq.",      XRC(63,546,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5296
5297 {"mffs",        XRC(63,583,0),  XRARB_MASK,  COM,       PPCNONE,        {FRT}},
5298 {"mffs.",       XRC(63,583,1),  XRARB_MASK,  COM,       PPCNONE,        {FRT}},
5299
5300 {"dcmpuq",      X(63,642),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
5301
5302 {"dtstsfq",     X(63,674),      X_MASK,      POWER6,    PPCNONE,        {BF, FRA, FRB}},
5303
5304 {"mtfsf",       XFL(63,711,0),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
5305 {"mtfsf",       XFL(63,711,0),  XFL_MASK,    COM, POWER6|PPCA2|PPC476,  {FLM, FRB}},
5306 {"mtfsf.",      XFL(63,711,1),  XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}},
5307 {"mtfsf.",      XFL(63,711,1),  XFL_MASK,    COM, POWER6|PPCA2|PPC476,  {FLM, FRB}},
5308
5309 {"drdpq",       XRC(63,770,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5310 {"drdpq.",      XRC(63,770,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5311
5312 {"dcffixq",     XRC(63,802,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5313 {"dcffixq.",    XRC(63,802,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRB}},
5314
5315 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5316 {"fctid",       XRC(63,814,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5317 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5318 {"fctid.",      XRC(63,814,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5319
5320 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5321 {"fctidz",      XRC(63,815,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5322 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5323 {"fctidz.",     XRC(63,815,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5324
5325 {"denbcdq",     XRC(63,834,0),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
5326 {"denbcdq.",    XRC(63,834,1),  X_MASK,      POWER6,    PPCNONE,        {S, FRT, FRB}},
5327
5328 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5329 {"fcfid",       XRC(63,846,0),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5330 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC64,     PPCNONE,        {FRT, FRB}},
5331 {"fcfid.",      XRC(63,846,1),  XRA_MASK,    PPC476,    PPCNONE,        {FRT, FRB}},
5332
5333 {"diexq",       XRC(63,866,0),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5334 {"diexq.",      XRC(63,866,1),  X_MASK,      POWER6,    PPCNONE,        {FRT, FRA, FRB}},
5335
5336 {"fctidu",      XRC(63,942,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5337 {"fctidu.",     XRC(63,942,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5338
5339 {"fctiduz",     XRC(63,943,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5340 {"fctiduz.",    XRC(63,943,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5341
5342 {"fcfidu",      XRC(63,974,0),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5343 {"fcfidu.",     XRC(63,974,1),  XRA_MASK, POWER7|PPCA2, PPCNONE,        {FRT, FRB}},
5344 };
5345
5346 const int powerpc_num_opcodes =
5347   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
5348 \f
5349 /* The macro table.  This is only used by the assembler.  */
5350
5351 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
5352    when x=0; 32-x when x is between 1 and 31; are negative if x is
5353    negative; and are 32 or more otherwise.  This is what you want
5354    when, for instance, you are emulating a right shift by a
5355    rotate-left-and-mask, because the underlying instructions support
5356    shifts of size 0 but not shifts of size 32.  By comparison, when
5357    extracting x bits from some word you want to use just 32-x, because
5358    the underlying instructions don't support extracting 0 bits but do
5359    support extracting the whole word (32 bits in this case).  */
5360
5361 const struct powerpc_macro powerpc_macros[] = {
5362 {"extldi",   4, PPC64,  "rldicr %0,%1,%3,(%2)-1"},
5363 {"extldi.",  4, PPC64,  "rldicr. %0,%1,%3,(%2)-1"},
5364 {"extrdi",   4, PPC64,  "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
5365 {"extrdi.",  4, PPC64,  "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
5366 {"insrdi",   4, PPC64,  "rldimi %0,%1,64-((%2)+(%3)),%3"},
5367 {"insrdi.",  4, PPC64,  "rldimi. %0,%1,64-((%2)+(%3)),%3"},
5368 {"rotrdi",   3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
5369 {"rotrdi.",  3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
5370 {"sldi",     3, PPC64,  "rldicr %0,%1,%2,63-(%2)"},
5371 {"sldi.",    3, PPC64,  "rldicr. %0,%1,%2,63-(%2)"},
5372 {"srdi",     3, PPC64,  "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
5373 {"srdi.",    3, PPC64,  "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
5374 {"clrrdi",   3, PPC64,  "rldicr %0,%1,0,63-(%2)"},
5375 {"clrrdi.",  3, PPC64,  "rldicr. %0,%1,0,63-(%2)"},
5376 {"clrlsldi", 4, PPC64,  "rldic %0,%1,%3,(%2)-(%3)"},
5377 {"clrlsldi.",4, PPC64,  "rldic. %0,%1,%3,(%2)-(%3)"},
5378
5379 {"extlwi",   4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
5380 {"extlwi.",  4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
5381 {"extrwi",   4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5382 {"extrwi.",  4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
5383 {"inslwi",   4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5384 {"inslwi.",  4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5385 {"insrwi",   4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5386 {"insrwi.",  4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5387 {"rotrwi",   3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5388 {"rotrwi.",  3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
5389 {"slwi",     3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
5390 {"sli",      3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
5391 {"slwi.",    3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
5392 {"sli.",     3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
5393 {"srwi",     3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5394 {"sri",      3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5395 {"srwi.",    3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5396 {"sri.",     3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
5397 {"clrrwi",   3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
5398 {"clrrwi.",  3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
5399 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
5400 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
5401 };
5402
5403 const int powerpc_num_macros =
5404   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);