1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma
, disassemble_info
*);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma
);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma
);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma
get64 (void);
60 static bfd_signed_vma
get32 (void);
61 static bfd_signed_vma
get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma
, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_EX_VexImmW (int, int);
95 static void OP_XMM_Vex (int, int);
96 static void OP_XMM_VexW (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VEXI4_Fixup (int, int);
100 static void VZERO_Fixup (int, int);
101 static void VCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void CMPXCHG8B_Fixup (int, int);
112 static void XMM_Fixup (int, int);
113 static void CRC32_Fixup (int, int);
114 static void FXSAVE_Fixup (int, int);
115 static void OP_LWPCB_E (int, int);
116 static void OP_LWP_E (int, int);
117 static void OP_Vex_2src_1 (int, int);
118 static void OP_Vex_2src_2 (int, int);
120 static void MOVBE_Fixup (int, int);
123 /* Points to first byte not fetched. */
124 bfd_byte
*max_fetched
;
125 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
138 enum address_mode address_mode
;
140 /* Flags for the prefixes for the current instruction. See below. */
143 /* REX prefix the current instruction. See below. */
145 /* Bits of REX we've already used. */
147 /* REX bits in original REX prefix ignored. */
148 static int rex_ignored
;
149 /* Mark parts used in the REX prefix. When we are testing for
150 empty prefix (for 8bit register REX extension), just mask it
151 out. Otherwise test for REX bit is excuse for existence of REX
152 only in case value is nonzero. */
153 #define USED_REX(value) \
158 rex_used |= (value) | REX_OPCODE; \
161 rex_used |= REX_OPCODE; \
164 /* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166 static int used_prefixes
;
168 /* Flags stored in PREFIXES. */
169 #define PREFIX_REPZ 1
170 #define PREFIX_REPNZ 2
171 #define PREFIX_LOCK 4
173 #define PREFIX_SS 0x10
174 #define PREFIX_DS 0x20
175 #define PREFIX_ES 0x40
176 #define PREFIX_FS 0x80
177 #define PREFIX_GS 0x100
178 #define PREFIX_DATA 0x200
179 #define PREFIX_ADDR 0x400
180 #define PREFIX_FWAIT 0x800
182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
185 #define FETCH_DATA(info, addr) \
186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
187 ? 1 : fetch_data ((info), (addr)))
190 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
193 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
194 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
196 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
197 status
= (*info
->read_memory_func
) (start
,
199 addr
- priv
->max_fetched
,
205 /* If we did manage to read at least one byte, then
206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
209 if (priv
->max_fetched
== priv
->the_buffer
)
210 (*info
->memory_error_func
) (status
, start
, info
);
211 longjmp (priv
->bailout
, 1);
214 priv
->max_fetched
= addr
;
218 #define XX { NULL, 0 }
219 #define Bad_Opcode NULL, { { NULL, 0 } }
221 #define Eb { OP_E, b_mode }
222 #define EbS { OP_E, b_swap_mode }
223 #define Ev { OP_E, v_mode }
224 #define EvS { OP_E, v_swap_mode }
225 #define Ed { OP_E, d_mode }
226 #define Edq { OP_E, dq_mode }
227 #define Edqw { OP_E, dqw_mode }
228 #define Edqb { OP_E, dqb_mode }
229 #define Edqd { OP_E, dqd_mode }
230 #define Eq { OP_E, q_mode }
231 #define indirEv { OP_indirE, stack_v_mode }
232 #define indirEp { OP_indirE, f_mode }
233 #define stackEv { OP_E, stack_v_mode }
234 #define Em { OP_E, m_mode }
235 #define Ew { OP_E, w_mode }
236 #define M { OP_M, 0 } /* lea, lgdt, etc. */
237 #define Ma { OP_M, a_mode }
238 #define Mb { OP_M, b_mode }
239 #define Md { OP_M, d_mode }
240 #define Mo { OP_M, o_mode }
241 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
242 #define Mq { OP_M, q_mode }
243 #define Mx { OP_M, x_mode }
244 #define Mxmm { OP_M, xmm_mode }
245 #define Gb { OP_G, b_mode }
246 #define Gv { OP_G, v_mode }
247 #define Gd { OP_G, d_mode }
248 #define Gdq { OP_G, dq_mode }
249 #define Gm { OP_G, m_mode }
250 #define Gw { OP_G, w_mode }
251 #define Rd { OP_R, d_mode }
252 #define Rm { OP_R, m_mode }
253 #define Ib { OP_I, b_mode }
254 #define sIb { OP_sI, b_mode } /* sign extened byte */
255 #define Iv { OP_I, v_mode }
256 #define sIv { OP_sI, v_mode }
257 #define Iq { OP_I, q_mode }
258 #define Iv64 { OP_I64, v_mode }
259 #define Iw { OP_I, w_mode }
260 #define I1 { OP_I, const_1_mode }
261 #define Jb { OP_J, b_mode }
262 #define Jv { OP_J, v_mode }
263 #define Cm { OP_C, m_mode }
264 #define Dm { OP_D, m_mode }
265 #define Td { OP_T, d_mode }
266 #define Skip_MODRM { OP_Skip_MODRM, 0 }
268 #define RMeAX { OP_REG, eAX_reg }
269 #define RMeBX { OP_REG, eBX_reg }
270 #define RMeCX { OP_REG, eCX_reg }
271 #define RMeDX { OP_REG, eDX_reg }
272 #define RMeSP { OP_REG, eSP_reg }
273 #define RMeBP { OP_REG, eBP_reg }
274 #define RMeSI { OP_REG, eSI_reg }
275 #define RMeDI { OP_REG, eDI_reg }
276 #define RMrAX { OP_REG, rAX_reg }
277 #define RMrBX { OP_REG, rBX_reg }
278 #define RMrCX { OP_REG, rCX_reg }
279 #define RMrDX { OP_REG, rDX_reg }
280 #define RMrSP { OP_REG, rSP_reg }
281 #define RMrBP { OP_REG, rBP_reg }
282 #define RMrSI { OP_REG, rSI_reg }
283 #define RMrDI { OP_REG, rDI_reg }
284 #define RMAL { OP_REG, al_reg }
285 #define RMCL { OP_REG, cl_reg }
286 #define RMDL { OP_REG, dl_reg }
287 #define RMBL { OP_REG, bl_reg }
288 #define RMAH { OP_REG, ah_reg }
289 #define RMCH { OP_REG, ch_reg }
290 #define RMDH { OP_REG, dh_reg }
291 #define RMBH { OP_REG, bh_reg }
292 #define RMAX { OP_REG, ax_reg }
293 #define RMDX { OP_REG, dx_reg }
295 #define eAX { OP_IMREG, eAX_reg }
296 #define eBX { OP_IMREG, eBX_reg }
297 #define eCX { OP_IMREG, eCX_reg }
298 #define eDX { OP_IMREG, eDX_reg }
299 #define eSP { OP_IMREG, eSP_reg }
300 #define eBP { OP_IMREG, eBP_reg }
301 #define eSI { OP_IMREG, eSI_reg }
302 #define eDI { OP_IMREG, eDI_reg }
303 #define AL { OP_IMREG, al_reg }
304 #define CL { OP_IMREG, cl_reg }
305 #define DL { OP_IMREG, dl_reg }
306 #define BL { OP_IMREG, bl_reg }
307 #define AH { OP_IMREG, ah_reg }
308 #define CH { OP_IMREG, ch_reg }
309 #define DH { OP_IMREG, dh_reg }
310 #define BH { OP_IMREG, bh_reg }
311 #define AX { OP_IMREG, ax_reg }
312 #define DX { OP_IMREG, dx_reg }
313 #define zAX { OP_IMREG, z_mode_ax_reg }
314 #define indirDX { OP_IMREG, indir_dx_reg }
316 #define Sw { OP_SEG, w_mode }
317 #define Sv { OP_SEG, v_mode }
318 #define Ap { OP_DIR, 0 }
319 #define Ob { OP_OFF64, b_mode }
320 #define Ov { OP_OFF64, v_mode }
321 #define Xb { OP_DSreg, eSI_reg }
322 #define Xv { OP_DSreg, eSI_reg }
323 #define Xz { OP_DSreg, eSI_reg }
324 #define Yb { OP_ESreg, eDI_reg }
325 #define Yv { OP_ESreg, eDI_reg }
326 #define DSBX { OP_DSreg, eBX_reg }
328 #define es { OP_REG, es_reg }
329 #define ss { OP_REG, ss_reg }
330 #define cs { OP_REG, cs_reg }
331 #define ds { OP_REG, ds_reg }
332 #define fs { OP_REG, fs_reg }
333 #define gs { OP_REG, gs_reg }
335 #define MX { OP_MMX, 0 }
336 #define XM { OP_XMM, 0 }
337 #define XMScalar { OP_XMM, scalar_mode }
338 #define XMM { OP_XMM, xmm_mode }
339 #define EM { OP_EM, v_mode }
340 #define EMS { OP_EM, v_swap_mode }
341 #define EMd { OP_EM, d_mode }
342 #define EMx { OP_EM, x_mode }
343 #define EXw { OP_EX, w_mode }
344 #define EXd { OP_EX, d_mode }
345 #define EXdScalar { OP_EX, d_scalar_mode }
346 #define EXdS { OP_EX, d_swap_mode }
347 #define EXq { OP_EX, q_mode }
348 #define EXqScalar { OP_EX, q_scalar_mode }
349 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
350 #define EXqS { OP_EX, q_swap_mode }
351 #define EXx { OP_EX, x_mode }
352 #define EXxS { OP_EX, x_swap_mode }
353 #define EXxmm { OP_EX, xmm_mode }
354 #define EXxmmq { OP_EX, xmmq_mode }
355 #define EXymmq { OP_EX, ymmq_mode }
356 #define EXVexWdq { OP_EX, vex_w_dq_mode }
357 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
358 #define MS { OP_MS, v_mode }
359 #define XS { OP_XS, v_mode }
360 #define EMCq { OP_EMC, q_mode }
361 #define MXC { OP_MXC, 0 }
362 #define OPSUF { OP_3DNowSuffix, 0 }
363 #define CMP { CMP_Fixup, 0 }
364 #define XMM0 { XMM_Fixup, 0 }
365 #define FXSAVE { FXSAVE_Fixup, 0 }
366 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
367 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
369 #define Vex { OP_VEX, vex_mode }
370 #define VexScalar { OP_VEX, vex_scalar_mode }
371 #define Vex128 { OP_VEX, vex128_mode }
372 #define Vex256 { OP_VEX, vex256_mode }
373 #define VexI4 { VEXI4_Fixup, 0}
374 #define EXdVex { OP_EX_Vex, d_mode }
375 #define EXdVexS { OP_EX_Vex, d_swap_mode }
376 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
377 #define EXqVex { OP_EX_Vex, q_mode }
378 #define EXqVexS { OP_EX_Vex, q_swap_mode }
379 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
380 #define EXVexW { OP_EX_VexW, x_mode }
381 #define EXdVexW { OP_EX_VexW, d_mode }
382 #define EXqVexW { OP_EX_VexW, q_mode }
383 #define EXVexImmW { OP_EX_VexImmW, x_mode }
384 #define XMVex { OP_XMM_Vex, 0 }
385 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
386 #define XMVexW { OP_XMM_VexW, 0 }
387 #define XMVexI4 { OP_REG_VexI4, x_mode }
388 #define PCLMUL { PCLMUL_Fixup, 0 }
389 #define VZERO { VZERO_Fixup, 0 }
390 #define VCMP { VCMP_Fixup, 0 }
392 /* Used handle "rep" prefix for string instructions. */
393 #define Xbr { REP_Fixup, eSI_reg }
394 #define Xvr { REP_Fixup, eSI_reg }
395 #define Ybr { REP_Fixup, eDI_reg }
396 #define Yvr { REP_Fixup, eDI_reg }
397 #define Yzr { REP_Fixup, eDI_reg }
398 #define indirDXr { REP_Fixup, indir_dx_reg }
399 #define ALr { REP_Fixup, al_reg }
400 #define eAXr { REP_Fixup, eAX_reg }
402 #define cond_jump_flag { NULL, cond_jump_mode }
403 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
405 /* bits in sizeflag */
406 #define SUFFIX_ALWAYS 4
414 /* byte operand with operand swapped */
416 /* operand size depends on prefixes */
418 /* operand size depends on prefixes with operand swapped */
422 /* double word operand */
424 /* double word operand with operand swapped */
426 /* quad word operand */
428 /* quad word operand with operand swapped */
430 /* ten-byte operand */
432 /* 16-byte XMM or 32-byte YMM operand */
434 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
436 /* 16-byte XMM operand */
438 /* 16-byte XMM or quad word operand */
440 /* 32-byte YMM or quad word operand */
442 /* d_mode in 32bit, q_mode in 64bit mode. */
444 /* pair of v_mode operands */
448 /* operand size depends on REX prefixes. */
450 /* registers like dq_mode, memory like w_mode. */
452 /* 4- or 6-byte pointer operand */
455 /* v_mode for stack-related opcodes. */
457 /* non-quad operand size depends on prefixes */
459 /* 16-byte operand */
461 /* registers like dq_mode, memory like b_mode. */
463 /* registers like dq_mode, memory like d_mode. */
465 /* normal vex mode */
467 /* 128bit vex mode */
469 /* 256bit vex mode */
471 /* operand size depends on the VEX.W bit. */
474 /* scalar, ignore vector length. */
476 /* like d_mode, ignore vector length. */
478 /* like d_swap_mode, ignore vector length. */
480 /* like q_mode, ignore vector length. */
482 /* like q_swap_mode, ignore vector length. */
484 /* like vex_mode, ignore vector length. */
486 /* like vex_w_dq_mode, ignore vector length. */
487 vex_scalar_w_dq_mode
,
552 #define FLOAT NULL, { { NULL, FLOATCODE } }
554 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
555 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
556 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
557 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
558 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
559 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
560 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
561 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
562 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
563 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
564 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
565 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
662 MOD_VEX_0F12_PREFIX_0
,
664 MOD_VEX_0F16_PREFIX_0
,
680 MOD_VEX_0FD7_PREFIX_2
,
681 MOD_VEX_0FE7_PREFIX_2
,
682 MOD_VEX_0FF0_PREFIX_3
,
683 MOD_VEX_0F3818_PREFIX_2
,
684 MOD_VEX_0F3819_PREFIX_2
,
685 MOD_VEX_0F381A_PREFIX_2
,
686 MOD_VEX_0F382A_PREFIX_2
,
687 MOD_VEX_0F382C_PREFIX_2
,
688 MOD_VEX_0F382D_PREFIX_2
,
689 MOD_VEX_0F382E_PREFIX_2
,
690 MOD_VEX_0F382F_PREFIX_2
859 PREFIX_VEX_0F71_REG_2
,
860 PREFIX_VEX_0F71_REG_4
,
861 PREFIX_VEX_0F71_REG_6
,
862 PREFIX_VEX_0F72_REG_2
,
863 PREFIX_VEX_0F72_REG_4
,
864 PREFIX_VEX_0F72_REG_6
,
865 PREFIX_VEX_0F73_REG_2
,
866 PREFIX_VEX_0F73_REG_3
,
867 PREFIX_VEX_0F73_REG_6
,
868 PREFIX_VEX_0F73_REG_7
,
1108 THREE_BYTE_0F38
= 0,
1129 VEX_LEN_0F10_P_1
= 0,
1133 VEX_LEN_0F12_P_0_M_0
,
1134 VEX_LEN_0F12_P_0_M_1
,
1137 VEX_LEN_0F16_P_0_M_0
,
1138 VEX_LEN_0F16_P_0_M_1
,
1187 VEX_LEN_0F71_R_2_P_2
,
1188 VEX_LEN_0F71_R_4_P_2
,
1189 VEX_LEN_0F71_R_6_P_2
,
1190 VEX_LEN_0F72_R_2_P_2
,
1191 VEX_LEN_0F72_R_4_P_2
,
1192 VEX_LEN_0F72_R_6_P_2
,
1193 VEX_LEN_0F73_R_2_P_2
,
1194 VEX_LEN_0F73_R_3_P_2
,
1195 VEX_LEN_0F73_R_6_P_2
,
1196 VEX_LEN_0F73_R_7_P_2
,
1202 VEX_LEN_0FAE_R_2_M_0
,
1203 VEX_LEN_0FAE_R_3_M_0
,
1214 VEX_LEN_0FD7_P_2_M_1
,
1263 VEX_LEN_0F3819_P_2_M_0
,
1264 VEX_LEN_0F381A_P_2_M_0
,
1276 VEX_LEN_0F382A_P_2_M_0
,
1331 VEX_LEN_0FXOP_09_80
,
1519 VEX_W_0F3818_P_2_M_0
,
1520 VEX_W_0F3819_P_2_M_0
,
1521 VEX_W_0F381A_P_2_M_0
,
1533 VEX_W_0F382A_P_2_M_0
,
1535 VEX_W_0F382C_P_2_M_0
,
1536 VEX_W_0F382D_P_2_M_0
,
1537 VEX_W_0F382E_P_2_M_0
,
1538 VEX_W_0F382F_P_2_M_0
,
1594 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1605 /* Upper case letters in the instruction names here are macros.
1606 'A' => print 'b' if no register operands or suffix_always is true
1607 'B' => print 'b' if suffix_always is true
1608 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1610 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1611 suffix_always is true
1612 'E' => print 'e' if 32-bit form of jcxz
1613 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1614 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1615 'H' => print ",pt" or ",pn" branch hint
1616 'I' => honor following macro letter even in Intel mode (implemented only
1617 for some of the macro letters)
1619 'K' => print 'd' or 'q' if rex prefix is present.
1620 'L' => print 'l' if suffix_always is true
1621 'M' => print 'r' if intel_mnemonic is false.
1622 'N' => print 'n' if instruction has no wait "prefix"
1623 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1624 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1625 or suffix_always is true. print 'q' if rex prefix is present.
1626 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1628 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1629 'S' => print 'w', 'l' or 'q' if suffix_always is true
1630 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1631 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1632 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1633 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1634 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1635 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1636 suffix_always is true.
1637 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1638 '!' => change condition from true to false or from false to true.
1639 '%' => add 1 upper case letter to the macro.
1641 2 upper case letter macros:
1642 "XY" => print 'x' or 'y' if no register operands or suffix_always
1644 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1645 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1646 or suffix_always is true
1647 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1648 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1649 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1651 Many of the above letters print nothing in Intel mode. See "putop"
1654 Braces '{' and '}', and vertical bars '|', indicate alternative
1655 mnemonic strings for AT&T and Intel. */
1657 static const struct dis386 dis386
[] = {
1659 { "addB", { Eb
, Gb
} },
1660 { "addS", { Ev
, Gv
} },
1661 { "addB", { Gb
, EbS
} },
1662 { "addS", { Gv
, EvS
} },
1663 { "addB", { AL
, Ib
} },
1664 { "addS", { eAX
, Iv
} },
1665 { X86_64_TABLE (X86_64_06
) },
1666 { X86_64_TABLE (X86_64_07
) },
1668 { "orB", { Eb
, Gb
} },
1669 { "orS", { Ev
, Gv
} },
1670 { "orB", { Gb
, EbS
} },
1671 { "orS", { Gv
, EvS
} },
1672 { "orB", { AL
, Ib
} },
1673 { "orS", { eAX
, Iv
} },
1674 { X86_64_TABLE (X86_64_0D
) },
1675 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1677 { "adcB", { Eb
, Gb
} },
1678 { "adcS", { Ev
, Gv
} },
1679 { "adcB", { Gb
, EbS
} },
1680 { "adcS", { Gv
, EvS
} },
1681 { "adcB", { AL
, Ib
} },
1682 { "adcS", { eAX
, Iv
} },
1683 { X86_64_TABLE (X86_64_16
) },
1684 { X86_64_TABLE (X86_64_17
) },
1686 { "sbbB", { Eb
, Gb
} },
1687 { "sbbS", { Ev
, Gv
} },
1688 { "sbbB", { Gb
, EbS
} },
1689 { "sbbS", { Gv
, EvS
} },
1690 { "sbbB", { AL
, Ib
} },
1691 { "sbbS", { eAX
, Iv
} },
1692 { X86_64_TABLE (X86_64_1E
) },
1693 { X86_64_TABLE (X86_64_1F
) },
1695 { "andB", { Eb
, Gb
} },
1696 { "andS", { Ev
, Gv
} },
1697 { "andB", { Gb
, EbS
} },
1698 { "andS", { Gv
, EvS
} },
1699 { "andB", { AL
, Ib
} },
1700 { "andS", { eAX
, Iv
} },
1701 { Bad_Opcode
}, /* SEG ES prefix */
1702 { X86_64_TABLE (X86_64_27
) },
1704 { "subB", { Eb
, Gb
} },
1705 { "subS", { Ev
, Gv
} },
1706 { "subB", { Gb
, EbS
} },
1707 { "subS", { Gv
, EvS
} },
1708 { "subB", { AL
, Ib
} },
1709 { "subS", { eAX
, Iv
} },
1710 { Bad_Opcode
}, /* SEG CS prefix */
1711 { X86_64_TABLE (X86_64_2F
) },
1713 { "xorB", { Eb
, Gb
} },
1714 { "xorS", { Ev
, Gv
} },
1715 { "xorB", { Gb
, EbS
} },
1716 { "xorS", { Gv
, EvS
} },
1717 { "xorB", { AL
, Ib
} },
1718 { "xorS", { eAX
, Iv
} },
1719 { Bad_Opcode
}, /* SEG SS prefix */
1720 { X86_64_TABLE (X86_64_37
) },
1722 { "cmpB", { Eb
, Gb
} },
1723 { "cmpS", { Ev
, Gv
} },
1724 { "cmpB", { Gb
, EbS
} },
1725 { "cmpS", { Gv
, EvS
} },
1726 { "cmpB", { AL
, Ib
} },
1727 { "cmpS", { eAX
, Iv
} },
1728 { Bad_Opcode
}, /* SEG DS prefix */
1729 { X86_64_TABLE (X86_64_3F
) },
1731 { "inc{S|}", { RMeAX
} },
1732 { "inc{S|}", { RMeCX
} },
1733 { "inc{S|}", { RMeDX
} },
1734 { "inc{S|}", { RMeBX
} },
1735 { "inc{S|}", { RMeSP
} },
1736 { "inc{S|}", { RMeBP
} },
1737 { "inc{S|}", { RMeSI
} },
1738 { "inc{S|}", { RMeDI
} },
1740 { "dec{S|}", { RMeAX
} },
1741 { "dec{S|}", { RMeCX
} },
1742 { "dec{S|}", { RMeDX
} },
1743 { "dec{S|}", { RMeBX
} },
1744 { "dec{S|}", { RMeSP
} },
1745 { "dec{S|}", { RMeBP
} },
1746 { "dec{S|}", { RMeSI
} },
1747 { "dec{S|}", { RMeDI
} },
1749 { "pushV", { RMrAX
} },
1750 { "pushV", { RMrCX
} },
1751 { "pushV", { RMrDX
} },
1752 { "pushV", { RMrBX
} },
1753 { "pushV", { RMrSP
} },
1754 { "pushV", { RMrBP
} },
1755 { "pushV", { RMrSI
} },
1756 { "pushV", { RMrDI
} },
1758 { "popV", { RMrAX
} },
1759 { "popV", { RMrCX
} },
1760 { "popV", { RMrDX
} },
1761 { "popV", { RMrBX
} },
1762 { "popV", { RMrSP
} },
1763 { "popV", { RMrBP
} },
1764 { "popV", { RMrSI
} },
1765 { "popV", { RMrDI
} },
1767 { X86_64_TABLE (X86_64_60
) },
1768 { X86_64_TABLE (X86_64_61
) },
1769 { X86_64_TABLE (X86_64_62
) },
1770 { X86_64_TABLE (X86_64_63
) },
1771 { Bad_Opcode
}, /* seg fs */
1772 { Bad_Opcode
}, /* seg gs */
1773 { Bad_Opcode
}, /* op size prefix */
1774 { Bad_Opcode
}, /* adr size prefix */
1776 { "pushT", { sIv
} },
1777 { "imulS", { Gv
, Ev
, Iv
} },
1778 { "pushT", { sIb
} },
1779 { "imulS", { Gv
, Ev
, sIb
} },
1780 { "ins{b|}", { Ybr
, indirDX
} },
1781 { X86_64_TABLE (X86_64_6D
) },
1782 { "outs{b|}", { indirDXr
, Xb
} },
1783 { X86_64_TABLE (X86_64_6F
) },
1785 { "joH", { Jb
, XX
, cond_jump_flag
} },
1786 { "jnoH", { Jb
, XX
, cond_jump_flag
} },
1787 { "jbH", { Jb
, XX
, cond_jump_flag
} },
1788 { "jaeH", { Jb
, XX
, cond_jump_flag
} },
1789 { "jeH", { Jb
, XX
, cond_jump_flag
} },
1790 { "jneH", { Jb
, XX
, cond_jump_flag
} },
1791 { "jbeH", { Jb
, XX
, cond_jump_flag
} },
1792 { "jaH", { Jb
, XX
, cond_jump_flag
} },
1794 { "jsH", { Jb
, XX
, cond_jump_flag
} },
1795 { "jnsH", { Jb
, XX
, cond_jump_flag
} },
1796 { "jpH", { Jb
, XX
, cond_jump_flag
} },
1797 { "jnpH", { Jb
, XX
, cond_jump_flag
} },
1798 { "jlH", { Jb
, XX
, cond_jump_flag
} },
1799 { "jgeH", { Jb
, XX
, cond_jump_flag
} },
1800 { "jleH", { Jb
, XX
, cond_jump_flag
} },
1801 { "jgH", { Jb
, XX
, cond_jump_flag
} },
1803 { REG_TABLE (REG_80
) },
1804 { REG_TABLE (REG_81
) },
1806 { REG_TABLE (REG_82
) },
1807 { "testB", { Eb
, Gb
} },
1808 { "testS", { Ev
, Gv
} },
1809 { "xchgB", { Eb
, Gb
} },
1810 { "xchgS", { Ev
, Gv
} },
1812 { "movB", { Eb
, Gb
} },
1813 { "movS", { Ev
, Gv
} },
1814 { "movB", { Gb
, EbS
} },
1815 { "movS", { Gv
, EvS
} },
1816 { "movD", { Sv
, Sw
} },
1817 { MOD_TABLE (MOD_8D
) },
1818 { "movD", { Sw
, Sv
} },
1819 { REG_TABLE (REG_8F
) },
1821 { PREFIX_TABLE (PREFIX_90
) },
1822 { "xchgS", { RMeCX
, eAX
} },
1823 { "xchgS", { RMeDX
, eAX
} },
1824 { "xchgS", { RMeBX
, eAX
} },
1825 { "xchgS", { RMeSP
, eAX
} },
1826 { "xchgS", { RMeBP
, eAX
} },
1827 { "xchgS", { RMeSI
, eAX
} },
1828 { "xchgS", { RMeDI
, eAX
} },
1830 { "cW{t|}R", { XX
} },
1831 { "cR{t|}O", { XX
} },
1832 { X86_64_TABLE (X86_64_9A
) },
1833 { Bad_Opcode
}, /* fwait */
1834 { "pushfT", { XX
} },
1835 { "popfT", { XX
} },
1839 { "mov%LB", { AL
, Ob
} },
1840 { "mov%LS", { eAX
, Ov
} },
1841 { "mov%LB", { Ob
, AL
} },
1842 { "mov%LS", { Ov
, eAX
} },
1843 { "movs{b|}", { Ybr
, Xb
} },
1844 { "movs{R|}", { Yvr
, Xv
} },
1845 { "cmps{b|}", { Xb
, Yb
} },
1846 { "cmps{R|}", { Xv
, Yv
} },
1848 { "testB", { AL
, Ib
} },
1849 { "testS", { eAX
, Iv
} },
1850 { "stosB", { Ybr
, AL
} },
1851 { "stosS", { Yvr
, eAX
} },
1852 { "lodsB", { ALr
, Xb
} },
1853 { "lodsS", { eAXr
, Xv
} },
1854 { "scasB", { AL
, Yb
} },
1855 { "scasS", { eAX
, Yv
} },
1857 { "movB", { RMAL
, Ib
} },
1858 { "movB", { RMCL
, Ib
} },
1859 { "movB", { RMDL
, Ib
} },
1860 { "movB", { RMBL
, Ib
} },
1861 { "movB", { RMAH
, Ib
} },
1862 { "movB", { RMCH
, Ib
} },
1863 { "movB", { RMDH
, Ib
} },
1864 { "movB", { RMBH
, Ib
} },
1866 { "mov%LV", { RMeAX
, Iv64
} },
1867 { "mov%LV", { RMeCX
, Iv64
} },
1868 { "mov%LV", { RMeDX
, Iv64
} },
1869 { "mov%LV", { RMeBX
, Iv64
} },
1870 { "mov%LV", { RMeSP
, Iv64
} },
1871 { "mov%LV", { RMeBP
, Iv64
} },
1872 { "mov%LV", { RMeSI
, Iv64
} },
1873 { "mov%LV", { RMeDI
, Iv64
} },
1875 { REG_TABLE (REG_C0
) },
1876 { REG_TABLE (REG_C1
) },
1879 { X86_64_TABLE (X86_64_C4
) },
1880 { X86_64_TABLE (X86_64_C5
) },
1881 { REG_TABLE (REG_C6
) },
1882 { REG_TABLE (REG_C7
) },
1884 { "enterT", { Iw
, Ib
} },
1885 { "leaveT", { XX
} },
1886 { "Jret{|f}P", { Iw
} },
1887 { "Jret{|f}P", { XX
} },
1890 { X86_64_TABLE (X86_64_CE
) },
1891 { "iretP", { XX
} },
1893 { REG_TABLE (REG_D0
) },
1894 { REG_TABLE (REG_D1
) },
1895 { REG_TABLE (REG_D2
) },
1896 { REG_TABLE (REG_D3
) },
1897 { X86_64_TABLE (X86_64_D4
) },
1898 { X86_64_TABLE (X86_64_D5
) },
1900 { "xlat", { DSBX
} },
1911 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
} },
1912 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
} },
1913 { "loopFH", { Jb
, XX
, loop_jcxz_flag
} },
1914 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
} },
1915 { "inB", { AL
, Ib
} },
1916 { "inG", { zAX
, Ib
} },
1917 { "outB", { Ib
, AL
} },
1918 { "outG", { Ib
, zAX
} },
1920 { "callT", { Jv
} },
1922 { X86_64_TABLE (X86_64_EA
) },
1924 { "inB", { AL
, indirDX
} },
1925 { "inG", { zAX
, indirDX
} },
1926 { "outB", { indirDX
, AL
} },
1927 { "outG", { indirDX
, zAX
} },
1929 { Bad_Opcode
}, /* lock prefix */
1930 { "icebp", { XX
} },
1931 { Bad_Opcode
}, /* repne */
1932 { Bad_Opcode
}, /* repz */
1935 { REG_TABLE (REG_F6
) },
1936 { REG_TABLE (REG_F7
) },
1944 { REG_TABLE (REG_FE
) },
1945 { REG_TABLE (REG_FF
) },
1948 static const struct dis386 dis386_twobyte
[] = {
1950 { REG_TABLE (REG_0F00
) },
1951 { REG_TABLE (REG_0F01
) },
1952 { "larS", { Gv
, Ew
} },
1953 { "lslS", { Gv
, Ew
} },
1955 { "syscall", { XX
} },
1957 { "sysretP", { XX
} },
1960 { "wbinvd", { XX
} },
1964 { REG_TABLE (REG_0F0D
) },
1965 { "femms", { XX
} },
1966 { "", { MX
, EM
, OPSUF
} }, /* See OP_3DNowSuffix. */
1968 { PREFIX_TABLE (PREFIX_0F10
) },
1969 { PREFIX_TABLE (PREFIX_0F11
) },
1970 { PREFIX_TABLE (PREFIX_0F12
) },
1971 { MOD_TABLE (MOD_0F13
) },
1972 { "unpcklpX", { XM
, EXx
} },
1973 { "unpckhpX", { XM
, EXx
} },
1974 { PREFIX_TABLE (PREFIX_0F16
) },
1975 { MOD_TABLE (MOD_0F17
) },
1977 { REG_TABLE (REG_0F18
) },
1986 { MOD_TABLE (MOD_0F20
) },
1987 { MOD_TABLE (MOD_0F21
) },
1988 { MOD_TABLE (MOD_0F22
) },
1989 { MOD_TABLE (MOD_0F23
) },
1990 { MOD_TABLE (MOD_0F24
) },
1992 { MOD_TABLE (MOD_0F26
) },
1995 { "movapX", { XM
, EXx
} },
1996 { "movapX", { EXxS
, XM
} },
1997 { PREFIX_TABLE (PREFIX_0F2A
) },
1998 { PREFIX_TABLE (PREFIX_0F2B
) },
1999 { PREFIX_TABLE (PREFIX_0F2C
) },
2000 { PREFIX_TABLE (PREFIX_0F2D
) },
2001 { PREFIX_TABLE (PREFIX_0F2E
) },
2002 { PREFIX_TABLE (PREFIX_0F2F
) },
2004 { "wrmsr", { XX
} },
2005 { "rdtsc", { XX
} },
2006 { "rdmsr", { XX
} },
2007 { "rdpmc", { XX
} },
2008 { "sysenter", { XX
} },
2009 { "sysexit", { XX
} },
2011 { "getsec", { XX
} },
2013 { THREE_BYTE_TABLE (THREE_BYTE_0F38
) },
2015 { THREE_BYTE_TABLE (THREE_BYTE_0F3A
) },
2022 { "cmovoS", { Gv
, Ev
} },
2023 { "cmovnoS", { Gv
, Ev
} },
2024 { "cmovbS", { Gv
, Ev
} },
2025 { "cmovaeS", { Gv
, Ev
} },
2026 { "cmoveS", { Gv
, Ev
} },
2027 { "cmovneS", { Gv
, Ev
} },
2028 { "cmovbeS", { Gv
, Ev
} },
2029 { "cmovaS", { Gv
, Ev
} },
2031 { "cmovsS", { Gv
, Ev
} },
2032 { "cmovnsS", { Gv
, Ev
} },
2033 { "cmovpS", { Gv
, Ev
} },
2034 { "cmovnpS", { Gv
, Ev
} },
2035 { "cmovlS", { Gv
, Ev
} },
2036 { "cmovgeS", { Gv
, Ev
} },
2037 { "cmovleS", { Gv
, Ev
} },
2038 { "cmovgS", { Gv
, Ev
} },
2040 { MOD_TABLE (MOD_0F51
) },
2041 { PREFIX_TABLE (PREFIX_0F51
) },
2042 { PREFIX_TABLE (PREFIX_0F52
) },
2043 { PREFIX_TABLE (PREFIX_0F53
) },
2044 { "andpX", { XM
, EXx
} },
2045 { "andnpX", { XM
, EXx
} },
2046 { "orpX", { XM
, EXx
} },
2047 { "xorpX", { XM
, EXx
} },
2049 { PREFIX_TABLE (PREFIX_0F58
) },
2050 { PREFIX_TABLE (PREFIX_0F59
) },
2051 { PREFIX_TABLE (PREFIX_0F5A
) },
2052 { PREFIX_TABLE (PREFIX_0F5B
) },
2053 { PREFIX_TABLE (PREFIX_0F5C
) },
2054 { PREFIX_TABLE (PREFIX_0F5D
) },
2055 { PREFIX_TABLE (PREFIX_0F5E
) },
2056 { PREFIX_TABLE (PREFIX_0F5F
) },
2058 { PREFIX_TABLE (PREFIX_0F60
) },
2059 { PREFIX_TABLE (PREFIX_0F61
) },
2060 { PREFIX_TABLE (PREFIX_0F62
) },
2061 { "packsswb", { MX
, EM
} },
2062 { "pcmpgtb", { MX
, EM
} },
2063 { "pcmpgtw", { MX
, EM
} },
2064 { "pcmpgtd", { MX
, EM
} },
2065 { "packuswb", { MX
, EM
} },
2067 { "punpckhbw", { MX
, EM
} },
2068 { "punpckhwd", { MX
, EM
} },
2069 { "punpckhdq", { MX
, EM
} },
2070 { "packssdw", { MX
, EM
} },
2071 { PREFIX_TABLE (PREFIX_0F6C
) },
2072 { PREFIX_TABLE (PREFIX_0F6D
) },
2073 { "movK", { MX
, Edq
} },
2074 { PREFIX_TABLE (PREFIX_0F6F
) },
2076 { PREFIX_TABLE (PREFIX_0F70
) },
2077 { REG_TABLE (REG_0F71
) },
2078 { REG_TABLE (REG_0F72
) },
2079 { REG_TABLE (REG_0F73
) },
2080 { "pcmpeqb", { MX
, EM
} },
2081 { "pcmpeqw", { MX
, EM
} },
2082 { "pcmpeqd", { MX
, EM
} },
2085 { PREFIX_TABLE (PREFIX_0F78
) },
2086 { PREFIX_TABLE (PREFIX_0F79
) },
2087 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2089 { PREFIX_TABLE (PREFIX_0F7C
) },
2090 { PREFIX_TABLE (PREFIX_0F7D
) },
2091 { PREFIX_TABLE (PREFIX_0F7E
) },
2092 { PREFIX_TABLE (PREFIX_0F7F
) },
2094 { "joH", { Jv
, XX
, cond_jump_flag
} },
2095 { "jnoH", { Jv
, XX
, cond_jump_flag
} },
2096 { "jbH", { Jv
, XX
, cond_jump_flag
} },
2097 { "jaeH", { Jv
, XX
, cond_jump_flag
} },
2098 { "jeH", { Jv
, XX
, cond_jump_flag
} },
2099 { "jneH", { Jv
, XX
, cond_jump_flag
} },
2100 { "jbeH", { Jv
, XX
, cond_jump_flag
} },
2101 { "jaH", { Jv
, XX
, cond_jump_flag
} },
2103 { "jsH", { Jv
, XX
, cond_jump_flag
} },
2104 { "jnsH", { Jv
, XX
, cond_jump_flag
} },
2105 { "jpH", { Jv
, XX
, cond_jump_flag
} },
2106 { "jnpH", { Jv
, XX
, cond_jump_flag
} },
2107 { "jlH", { Jv
, XX
, cond_jump_flag
} },
2108 { "jgeH", { Jv
, XX
, cond_jump_flag
} },
2109 { "jleH", { Jv
, XX
, cond_jump_flag
} },
2110 { "jgH", { Jv
, XX
, cond_jump_flag
} },
2113 { "setno", { Eb
} },
2115 { "setae", { Eb
} },
2117 { "setne", { Eb
} },
2118 { "setbe", { Eb
} },
2122 { "setns", { Eb
} },
2124 { "setnp", { Eb
} },
2126 { "setge", { Eb
} },
2127 { "setle", { Eb
} },
2130 { "pushT", { fs
} },
2132 { "cpuid", { XX
} },
2133 { "btS", { Ev
, Gv
} },
2134 { "shldS", { Ev
, Gv
, Ib
} },
2135 { "shldS", { Ev
, Gv
, CL
} },
2136 { REG_TABLE (REG_0FA6
) },
2137 { REG_TABLE (REG_0FA7
) },
2139 { "pushT", { gs
} },
2142 { "btsS", { Ev
, Gv
} },
2143 { "shrdS", { Ev
, Gv
, Ib
} },
2144 { "shrdS", { Ev
, Gv
, CL
} },
2145 { REG_TABLE (REG_0FAE
) },
2146 { "imulS", { Gv
, Ev
} },
2148 { "cmpxchgB", { Eb
, Gb
} },
2149 { "cmpxchgS", { Ev
, Gv
} },
2150 { MOD_TABLE (MOD_0FB2
) },
2151 { "btrS", { Ev
, Gv
} },
2152 { MOD_TABLE (MOD_0FB4
) },
2153 { MOD_TABLE (MOD_0FB5
) },
2154 { "movz{bR|x}", { Gv
, Eb
} },
2155 { "movz{wR|x}", { Gv
, Ew
} }, /* yes, there really is movzww ! */
2157 { PREFIX_TABLE (PREFIX_0FB8
) },
2159 { REG_TABLE (REG_0FBA
) },
2160 { "btcS", { Ev
, Gv
} },
2161 { "bsfS", { Gv
, Ev
} },
2162 { PREFIX_TABLE (PREFIX_0FBD
) },
2163 { "movs{bR|x}", { Gv
, Eb
} },
2164 { "movs{wR|x}", { Gv
, Ew
} }, /* yes, there really is movsww ! */
2166 { "xaddB", { Eb
, Gb
} },
2167 { "xaddS", { Ev
, Gv
} },
2168 { PREFIX_TABLE (PREFIX_0FC2
) },
2169 { PREFIX_TABLE (PREFIX_0FC3
) },
2170 { "pinsrw", { MX
, Edqw
, Ib
} },
2171 { "pextrw", { Gdq
, MS
, Ib
} },
2172 { "shufpX", { XM
, EXx
, Ib
} },
2173 { REG_TABLE (REG_0FC7
) },
2175 { "bswap", { RMeAX
} },
2176 { "bswap", { RMeCX
} },
2177 { "bswap", { RMeDX
} },
2178 { "bswap", { RMeBX
} },
2179 { "bswap", { RMeSP
} },
2180 { "bswap", { RMeBP
} },
2181 { "bswap", { RMeSI
} },
2182 { "bswap", { RMeDI
} },
2184 { PREFIX_TABLE (PREFIX_0FD0
) },
2185 { "psrlw", { MX
, EM
} },
2186 { "psrld", { MX
, EM
} },
2187 { "psrlq", { MX
, EM
} },
2188 { "paddq", { MX
, EM
} },
2189 { "pmullw", { MX
, EM
} },
2190 { PREFIX_TABLE (PREFIX_0FD6
) },
2191 { MOD_TABLE (MOD_0FD7
) },
2193 { "psubusb", { MX
, EM
} },
2194 { "psubusw", { MX
, EM
} },
2195 { "pminub", { MX
, EM
} },
2196 { "pand", { MX
, EM
} },
2197 { "paddusb", { MX
, EM
} },
2198 { "paddusw", { MX
, EM
} },
2199 { "pmaxub", { MX
, EM
} },
2200 { "pandn", { MX
, EM
} },
2202 { "pavgb", { MX
, EM
} },
2203 { "psraw", { MX
, EM
} },
2204 { "psrad", { MX
, EM
} },
2205 { "pavgw", { MX
, EM
} },
2206 { "pmulhuw", { MX
, EM
} },
2207 { "pmulhw", { MX
, EM
} },
2208 { PREFIX_TABLE (PREFIX_0FE6
) },
2209 { PREFIX_TABLE (PREFIX_0FE7
) },
2211 { "psubsb", { MX
, EM
} },
2212 { "psubsw", { MX
, EM
} },
2213 { "pminsw", { MX
, EM
} },
2214 { "por", { MX
, EM
} },
2215 { "paddsb", { MX
, EM
} },
2216 { "paddsw", { MX
, EM
} },
2217 { "pmaxsw", { MX
, EM
} },
2218 { "pxor", { MX
, EM
} },
2220 { PREFIX_TABLE (PREFIX_0FF0
) },
2221 { "psllw", { MX
, EM
} },
2222 { "pslld", { MX
, EM
} },
2223 { "psllq", { MX
, EM
} },
2224 { "pmuludq", { MX
, EM
} },
2225 { "pmaddwd", { MX
, EM
} },
2226 { "psadbw", { MX
, EM
} },
2227 { PREFIX_TABLE (PREFIX_0FF7
) },
2229 { "psubb", { MX
, EM
} },
2230 { "psubw", { MX
, EM
} },
2231 { "psubd", { MX
, EM
} },
2232 { "psubq", { MX
, EM
} },
2233 { "paddb", { MX
, EM
} },
2234 { "paddw", { MX
, EM
} },
2235 { "paddd", { MX
, EM
} },
2239 static const unsigned char onebyte_has_modrm
[256] = {
2240 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2241 /* ------------------------------- */
2242 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2243 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2244 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2245 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2246 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2247 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2248 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2249 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2250 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2251 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2252 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2253 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2254 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2255 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2256 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2257 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2258 /* ------------------------------- */
2259 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2262 static const unsigned char twobyte_has_modrm
[256] = {
2263 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2264 /* ------------------------------- */
2265 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2266 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2267 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2268 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2269 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2270 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2271 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2272 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2273 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2274 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2275 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2276 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2277 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2278 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2279 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2280 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2281 /* ------------------------------- */
2282 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2285 static char obuf
[100];
2287 static char *mnemonicendp
;
2288 static char scratchbuf
[100];
2289 static unsigned char *start_codep
;
2290 static unsigned char *insn_codep
;
2291 static unsigned char *codep
;
2292 static int last_lock_prefix
;
2293 static int last_repz_prefix
;
2294 static int last_repnz_prefix
;
2295 static int last_data_prefix
;
2296 static int last_addr_prefix
;
2297 static int last_rex_prefix
;
2298 static int last_seg_prefix
;
2299 #define MAX_CODE_LENGTH 15
2300 /* We can up to 14 prefixes since the maximum instruction length is
2302 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2303 static disassemble_info
*the_info
;
2311 static unsigned char need_modrm
;
2321 int register_specifier
;
2327 static unsigned char need_vex
;
2328 static unsigned char need_vex_reg
;
2329 static unsigned char vex_w_done
;
2337 /* If we are accessing mod/rm/reg without need_modrm set, then the
2338 values are stale. Hitting this abort likely indicates that you
2339 need to update onebyte_has_modrm or twobyte_has_modrm. */
2340 #define MODRM_CHECK if (!need_modrm) abort ()
2342 static const char **names64
;
2343 static const char **names32
;
2344 static const char **names16
;
2345 static const char **names8
;
2346 static const char **names8rex
;
2347 static const char **names_seg
;
2348 static const char *index64
;
2349 static const char *index32
;
2350 static const char **index16
;
2352 static const char *intel_names64
[] = {
2353 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2354 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2356 static const char *intel_names32
[] = {
2357 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2358 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2360 static const char *intel_names16
[] = {
2361 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2362 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2364 static const char *intel_names8
[] = {
2365 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2367 static const char *intel_names8rex
[] = {
2368 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2369 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2371 static const char *intel_names_seg
[] = {
2372 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2374 static const char *intel_index64
= "riz";
2375 static const char *intel_index32
= "eiz";
2376 static const char *intel_index16
[] = {
2377 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2380 static const char *att_names64
[] = {
2381 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2382 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2384 static const char *att_names32
[] = {
2385 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2386 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2388 static const char *att_names16
[] = {
2389 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2390 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2392 static const char *att_names8
[] = {
2393 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2395 static const char *att_names8rex
[] = {
2396 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2397 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2399 static const char *att_names_seg
[] = {
2400 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2402 static const char *att_index64
= "%riz";
2403 static const char *att_index32
= "%eiz";
2404 static const char *att_index16
[] = {
2405 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2408 static const char **names_mm
;
2409 static const char *intel_names_mm
[] = {
2410 "mm0", "mm1", "mm2", "mm3",
2411 "mm4", "mm5", "mm6", "mm7"
2413 static const char *att_names_mm
[] = {
2414 "%mm0", "%mm1", "%mm2", "%mm3",
2415 "%mm4", "%mm5", "%mm6", "%mm7"
2418 static const char **names_xmm
;
2419 static const char *intel_names_xmm
[] = {
2420 "xmm0", "xmm1", "xmm2", "xmm3",
2421 "xmm4", "xmm5", "xmm6", "xmm7",
2422 "xmm8", "xmm9", "xmm10", "xmm11",
2423 "xmm12", "xmm13", "xmm14", "xmm15"
2425 static const char *att_names_xmm
[] = {
2426 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2427 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2428 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2429 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2432 static const char **names_ymm
;
2433 static const char *intel_names_ymm
[] = {
2434 "ymm0", "ymm1", "ymm2", "ymm3",
2435 "ymm4", "ymm5", "ymm6", "ymm7",
2436 "ymm8", "ymm9", "ymm10", "ymm11",
2437 "ymm12", "ymm13", "ymm14", "ymm15"
2439 static const char *att_names_ymm
[] = {
2440 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2441 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2442 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2443 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2446 static const struct dis386 reg_table
[][8] = {
2449 { "addA", { Eb
, Ib
} },
2450 { "orA", { Eb
, Ib
} },
2451 { "adcA", { Eb
, Ib
} },
2452 { "sbbA", { Eb
, Ib
} },
2453 { "andA", { Eb
, Ib
} },
2454 { "subA", { Eb
, Ib
} },
2455 { "xorA", { Eb
, Ib
} },
2456 { "cmpA", { Eb
, Ib
} },
2460 { "addQ", { Ev
, Iv
} },
2461 { "orQ", { Ev
, Iv
} },
2462 { "adcQ", { Ev
, Iv
} },
2463 { "sbbQ", { Ev
, Iv
} },
2464 { "andQ", { Ev
, Iv
} },
2465 { "subQ", { Ev
, Iv
} },
2466 { "xorQ", { Ev
, Iv
} },
2467 { "cmpQ", { Ev
, Iv
} },
2471 { "addQ", { Ev
, sIb
} },
2472 { "orQ", { Ev
, sIb
} },
2473 { "adcQ", { Ev
, sIb
} },
2474 { "sbbQ", { Ev
, sIb
} },
2475 { "andQ", { Ev
, sIb
} },
2476 { "subQ", { Ev
, sIb
} },
2477 { "xorQ", { Ev
, sIb
} },
2478 { "cmpQ", { Ev
, sIb
} },
2482 { "popU", { stackEv
} },
2483 { XOP_8F_TABLE (XOP_09
) },
2487 { XOP_8F_TABLE (XOP_09
) },
2491 { "rolA", { Eb
, Ib
} },
2492 { "rorA", { Eb
, Ib
} },
2493 { "rclA", { Eb
, Ib
} },
2494 { "rcrA", { Eb
, Ib
} },
2495 { "shlA", { Eb
, Ib
} },
2496 { "shrA", { Eb
, Ib
} },
2498 { "sarA", { Eb
, Ib
} },
2502 { "rolQ", { Ev
, Ib
} },
2503 { "rorQ", { Ev
, Ib
} },
2504 { "rclQ", { Ev
, Ib
} },
2505 { "rcrQ", { Ev
, Ib
} },
2506 { "shlQ", { Ev
, Ib
} },
2507 { "shrQ", { Ev
, Ib
} },
2509 { "sarQ", { Ev
, Ib
} },
2513 { "movA", { Eb
, Ib
} },
2517 { "movQ", { Ev
, Iv
} },
2521 { "rolA", { Eb
, I1
} },
2522 { "rorA", { Eb
, I1
} },
2523 { "rclA", { Eb
, I1
} },
2524 { "rcrA", { Eb
, I1
} },
2525 { "shlA", { Eb
, I1
} },
2526 { "shrA", { Eb
, I1
} },
2528 { "sarA", { Eb
, I1
} },
2532 { "rolQ", { Ev
, I1
} },
2533 { "rorQ", { Ev
, I1
} },
2534 { "rclQ", { Ev
, I1
} },
2535 { "rcrQ", { Ev
, I1
} },
2536 { "shlQ", { Ev
, I1
} },
2537 { "shrQ", { Ev
, I1
} },
2539 { "sarQ", { Ev
, I1
} },
2543 { "rolA", { Eb
, CL
} },
2544 { "rorA", { Eb
, CL
} },
2545 { "rclA", { Eb
, CL
} },
2546 { "rcrA", { Eb
, CL
} },
2547 { "shlA", { Eb
, CL
} },
2548 { "shrA", { Eb
, CL
} },
2550 { "sarA", { Eb
, CL
} },
2554 { "rolQ", { Ev
, CL
} },
2555 { "rorQ", { Ev
, CL
} },
2556 { "rclQ", { Ev
, CL
} },
2557 { "rcrQ", { Ev
, CL
} },
2558 { "shlQ", { Ev
, CL
} },
2559 { "shrQ", { Ev
, CL
} },
2561 { "sarQ", { Ev
, CL
} },
2565 { "testA", { Eb
, Ib
} },
2569 { "mulA", { Eb
} }, /* Don't print the implicit %al register, */
2570 { "imulA", { Eb
} }, /* to distinguish these opcodes from other */
2571 { "divA", { Eb
} }, /* mul/imul opcodes. Do the same for div */
2572 { "idivA", { Eb
} }, /* and idiv for consistency. */
2576 { "testQ", { Ev
, Iv
} },
2580 { "mulQ", { Ev
} }, /* Don't print the implicit register. */
2581 { "imulQ", { Ev
} },
2583 { "idivQ", { Ev
} },
2594 { "call{T|}", { indirEv
} },
2595 { "Jcall{T|}", { indirEp
} },
2596 { "jmp{T|}", { indirEv
} },
2597 { "Jjmp{T|}", { indirEp
} },
2598 { "pushU", { stackEv
} },
2603 { "sldtD", { Sv
} },
2614 { MOD_TABLE (MOD_0F01_REG_0
) },
2615 { MOD_TABLE (MOD_0F01_REG_1
) },
2616 { MOD_TABLE (MOD_0F01_REG_2
) },
2617 { MOD_TABLE (MOD_0F01_REG_3
) },
2618 { "smswD", { Sv
} },
2621 { MOD_TABLE (MOD_0F01_REG_7
) },
2625 { "prefetch", { Mb
} },
2626 { "prefetchw", { Mb
} },
2630 { MOD_TABLE (MOD_0F18_REG_0
) },
2631 { MOD_TABLE (MOD_0F18_REG_1
) },
2632 { MOD_TABLE (MOD_0F18_REG_2
) },
2633 { MOD_TABLE (MOD_0F18_REG_3
) },
2639 { MOD_TABLE (MOD_0F71_REG_2
) },
2641 { MOD_TABLE (MOD_0F71_REG_4
) },
2643 { MOD_TABLE (MOD_0F71_REG_6
) },
2649 { MOD_TABLE (MOD_0F72_REG_2
) },
2651 { MOD_TABLE (MOD_0F72_REG_4
) },
2653 { MOD_TABLE (MOD_0F72_REG_6
) },
2659 { MOD_TABLE (MOD_0F73_REG_2
) },
2660 { MOD_TABLE (MOD_0F73_REG_3
) },
2663 { MOD_TABLE (MOD_0F73_REG_6
) },
2664 { MOD_TABLE (MOD_0F73_REG_7
) },
2668 { "montmul", { { OP_0f07
, 0 } } },
2669 { "xsha1", { { OP_0f07
, 0 } } },
2670 { "xsha256", { { OP_0f07
, 0 } } },
2674 { "xstore-rng", { { OP_0f07
, 0 } } },
2675 { "xcrypt-ecb", { { OP_0f07
, 0 } } },
2676 { "xcrypt-cbc", { { OP_0f07
, 0 } } },
2677 { "xcrypt-ctr", { { OP_0f07
, 0 } } },
2678 { "xcrypt-cfb", { { OP_0f07
, 0 } } },
2679 { "xcrypt-ofb", { { OP_0f07
, 0 } } },
2683 { MOD_TABLE (MOD_0FAE_REG_0
) },
2684 { MOD_TABLE (MOD_0FAE_REG_1
) },
2685 { MOD_TABLE (MOD_0FAE_REG_2
) },
2686 { MOD_TABLE (MOD_0FAE_REG_3
) },
2687 { MOD_TABLE (MOD_0FAE_REG_4
) },
2688 { MOD_TABLE (MOD_0FAE_REG_5
) },
2689 { MOD_TABLE (MOD_0FAE_REG_6
) },
2690 { MOD_TABLE (MOD_0FAE_REG_7
) },
2698 { "btQ", { Ev
, Ib
} },
2699 { "btsQ", { Ev
, Ib
} },
2700 { "btrQ", { Ev
, Ib
} },
2701 { "btcQ", { Ev
, Ib
} },
2706 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} } },
2711 { MOD_TABLE (MOD_0FC7_REG_6
) },
2712 { MOD_TABLE (MOD_0FC7_REG_7
) },
2718 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
2720 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
2722 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
2728 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
2730 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
2732 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
2738 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
2739 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
2742 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
2743 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
2749 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
2750 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
2754 { "llwpcb", { { OP_LWPCB_E
, 0 } } },
2755 { "slwpcb", { { OP_LWPCB_E
, 0 } } },
2759 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
2760 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
2764 static const struct dis386 prefix_table
[][4] = {
2767 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
2768 { "pause", { XX
} },
2769 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
2774 { "movups", { XM
, EXx
} },
2775 { "movss", { XM
, EXd
} },
2776 { "movupd", { XM
, EXx
} },
2777 { "movsd", { XM
, EXq
} },
2782 { "movups", { EXxS
, XM
} },
2783 { "movss", { EXdS
, XM
} },
2784 { "movupd", { EXxS
, XM
} },
2785 { "movsd", { EXqS
, XM
} },
2790 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
2791 { "movsldup", { XM
, EXx
} },
2792 { "movlpd", { XM
, EXq
} },
2793 { "movddup", { XM
, EXq
} },
2798 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
2799 { "movshdup", { XM
, EXx
} },
2800 { "movhpd", { XM
, EXq
} },
2805 { "cvtpi2ps", { XM
, EMCq
} },
2806 { "cvtsi2ss%LQ", { XM
, Ev
} },
2807 { "cvtpi2pd", { XM
, EMCq
} },
2808 { "cvtsi2sd%LQ", { XM
, Ev
} },
2813 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
2814 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
2815 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
2816 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
2821 { "cvttps2pi", { MXC
, EXq
} },
2822 { "cvttss2siY", { Gv
, EXd
} },
2823 { "cvttpd2pi", { MXC
, EXx
} },
2824 { "cvttsd2siY", { Gv
, EXq
} },
2829 { "cvtps2pi", { MXC
, EXq
} },
2830 { "cvtss2siY", { Gv
, EXd
} },
2831 { "cvtpd2pi", { MXC
, EXx
} },
2832 { "cvtsd2siY", { Gv
, EXq
} },
2837 { "ucomiss",{ XM
, EXd
} },
2839 { "ucomisd",{ XM
, EXq
} },
2844 { "comiss", { XM
, EXd
} },
2846 { "comisd", { XM
, EXq
} },
2851 { "sqrtps", { XM
, EXx
} },
2852 { "sqrtss", { XM
, EXd
} },
2853 { "sqrtpd", { XM
, EXx
} },
2854 { "sqrtsd", { XM
, EXq
} },
2859 { "rsqrtps",{ XM
, EXx
} },
2860 { "rsqrtss",{ XM
, EXd
} },
2865 { "rcpps", { XM
, EXx
} },
2866 { "rcpss", { XM
, EXd
} },
2871 { "addps", { XM
, EXx
} },
2872 { "addss", { XM
, EXd
} },
2873 { "addpd", { XM
, EXx
} },
2874 { "addsd", { XM
, EXq
} },
2879 { "mulps", { XM
, EXx
} },
2880 { "mulss", { XM
, EXd
} },
2881 { "mulpd", { XM
, EXx
} },
2882 { "mulsd", { XM
, EXq
} },
2887 { "cvtps2pd", { XM
, EXq
} },
2888 { "cvtss2sd", { XM
, EXd
} },
2889 { "cvtpd2ps", { XM
, EXx
} },
2890 { "cvtsd2ss", { XM
, EXq
} },
2895 { "cvtdq2ps", { XM
, EXx
} },
2896 { "cvttps2dq", { XM
, EXx
} },
2897 { "cvtps2dq", { XM
, EXx
} },
2902 { "subps", { XM
, EXx
} },
2903 { "subss", { XM
, EXd
} },
2904 { "subpd", { XM
, EXx
} },
2905 { "subsd", { XM
, EXq
} },
2910 { "minps", { XM
, EXx
} },
2911 { "minss", { XM
, EXd
} },
2912 { "minpd", { XM
, EXx
} },
2913 { "minsd", { XM
, EXq
} },
2918 { "divps", { XM
, EXx
} },
2919 { "divss", { XM
, EXd
} },
2920 { "divpd", { XM
, EXx
} },
2921 { "divsd", { XM
, EXq
} },
2926 { "maxps", { XM
, EXx
} },
2927 { "maxss", { XM
, EXd
} },
2928 { "maxpd", { XM
, EXx
} },
2929 { "maxsd", { XM
, EXq
} },
2934 { "punpcklbw",{ MX
, EMd
} },
2936 { "punpcklbw",{ MX
, EMx
} },
2941 { "punpcklwd",{ MX
, EMd
} },
2943 { "punpcklwd",{ MX
, EMx
} },
2948 { "punpckldq",{ MX
, EMd
} },
2950 { "punpckldq",{ MX
, EMx
} },
2957 { "punpcklqdq", { XM
, EXx
} },
2964 { "punpckhqdq", { XM
, EXx
} },
2969 { "movq", { MX
, EM
} },
2970 { "movdqu", { XM
, EXx
} },
2971 { "movdqa", { XM
, EXx
} },
2976 { "pshufw", { MX
, EM
, Ib
} },
2977 { "pshufhw",{ XM
, EXx
, Ib
} },
2978 { "pshufd", { XM
, EXx
, Ib
} },
2979 { "pshuflw",{ XM
, EXx
, Ib
} },
2982 /* PREFIX_0F73_REG_3 */
2986 { "psrldq", { XS
, Ib
} },
2989 /* PREFIX_0F73_REG_7 */
2993 { "pslldq", { XS
, Ib
} },
2998 {"vmread", { Em
, Gm
} },
3000 {"extrq", { XS
, Ib
, Ib
} },
3001 {"insertq", { XM
, XS
, Ib
, Ib
} },
3006 {"vmwrite", { Gm
, Em
} },
3008 {"extrq", { XM
, XS
} },
3009 {"insertq", { XM
, XS
} },
3016 { "haddpd", { XM
, EXx
} },
3017 { "haddps", { XM
, EXx
} },
3024 { "hsubpd", { XM
, EXx
} },
3025 { "hsubps", { XM
, EXx
} },
3030 { "movK", { Edq
, MX
} },
3031 { "movq", { XM
, EXq
} },
3032 { "movK", { Edq
, XM
} },
3037 { "movq", { EMS
, MX
} },
3038 { "movdqu", { EXxS
, XM
} },
3039 { "movdqa", { EXxS
, XM
} },
3042 /* PREFIX_0FAE_REG_0 */
3045 { "rdfsbase", { Ev
} },
3048 /* PREFIX_0FAE_REG_1 */
3051 { "rdgsbase", { Ev
} },
3054 /* PREFIX_0FAE_REG_2 */
3057 { "wrfsbase", { Ev
} },
3060 /* PREFIX_0FAE_REG_3 */
3063 { "wrgsbase", { Ev
} },
3069 { "popcntS", { Gv
, Ev
} },
3074 { "bsrS", { Gv
, Ev
} },
3075 { "lzcntS", { Gv
, Ev
} },
3076 { "bsrS", { Gv
, Ev
} },
3081 { "cmpps", { XM
, EXx
, CMP
} },
3082 { "cmpss", { XM
, EXd
, CMP
} },
3083 { "cmppd", { XM
, EXx
, CMP
} },
3084 { "cmpsd", { XM
, EXq
, CMP
} },
3089 { "movntiS", { Ma
, Gv
} },
3092 /* PREFIX_0FC7_REG_6 */
3094 { "vmptrld",{ Mq
} },
3095 { "vmxon", { Mq
} },
3096 { "vmclear",{ Mq
} },
3103 { "addsubpd", { XM
, EXx
} },
3104 { "addsubps", { XM
, EXx
} },
3110 { "movq2dq",{ XM
, MS
} },
3111 { "movq", { EXqS
, XM
} },
3112 { "movdq2q",{ MX
, XS
} },
3118 { "cvtdq2pd", { XM
, EXq
} },
3119 { "cvttpd2dq", { XM
, EXx
} },
3120 { "cvtpd2dq", { XM
, EXx
} },
3125 { "movntq", { Mq
, MX
} },
3127 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3135 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3140 { "maskmovq", { MX
, MS
} },
3142 { "maskmovdqu", { XM
, XS
} },
3149 { "pblendvb", { XM
, EXx
, XMM0
} },
3156 { "blendvps", { XM
, EXx
, XMM0
} },
3163 { "blendvpd", { XM
, EXx
, XMM0
} },
3170 { "ptest", { XM
, EXx
} },
3177 { "pmovsxbw", { XM
, EXq
} },
3184 { "pmovsxbd", { XM
, EXd
} },
3191 { "pmovsxbq", { XM
, EXw
} },
3198 { "pmovsxwd", { XM
, EXq
} },
3205 { "pmovsxwq", { XM
, EXd
} },
3212 { "pmovsxdq", { XM
, EXq
} },
3219 { "pmuldq", { XM
, EXx
} },
3226 { "pcmpeqq", { XM
, EXx
} },
3233 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
3240 { "packusdw", { XM
, EXx
} },
3247 { "pmovzxbw", { XM
, EXq
} },
3254 { "pmovzxbd", { XM
, EXd
} },
3261 { "pmovzxbq", { XM
, EXw
} },
3268 { "pmovzxwd", { XM
, EXq
} },
3275 { "pmovzxwq", { XM
, EXd
} },
3282 { "pmovzxdq", { XM
, EXq
} },
3289 { "pcmpgtq", { XM
, EXx
} },
3296 { "pminsb", { XM
, EXx
} },
3303 { "pminsd", { XM
, EXx
} },
3310 { "pminuw", { XM
, EXx
} },
3317 { "pminud", { XM
, EXx
} },
3324 { "pmaxsb", { XM
, EXx
} },
3331 { "pmaxsd", { XM
, EXx
} },
3338 { "pmaxuw", { XM
, EXx
} },
3345 { "pmaxud", { XM
, EXx
} },
3352 { "pmulld", { XM
, EXx
} },
3359 { "phminposuw", { XM
, EXx
} },
3366 { "invept", { Gm
, Mo
} },
3373 { "invvpid", { Gm
, Mo
} },
3380 { "aesimc", { XM
, EXx
} },
3387 { "aesenc", { XM
, EXx
} },
3394 { "aesenclast", { XM
, EXx
} },
3401 { "aesdec", { XM
, EXx
} },
3408 { "aesdeclast", { XM
, EXx
} },
3413 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
3415 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
3416 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} } },
3421 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
3423 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
3424 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} } },
3431 { "roundps", { XM
, EXx
, Ib
} },
3438 { "roundpd", { XM
, EXx
, Ib
} },
3445 { "roundss", { XM
, EXd
, Ib
} },
3452 { "roundsd", { XM
, EXq
, Ib
} },
3459 { "blendps", { XM
, EXx
, Ib
} },
3466 { "blendpd", { XM
, EXx
, Ib
} },
3473 { "pblendw", { XM
, EXx
, Ib
} },
3480 { "pextrb", { Edqb
, XM
, Ib
} },
3487 { "pextrw", { Edqw
, XM
, Ib
} },
3494 { "pextrK", { Edq
, XM
, Ib
} },
3501 { "extractps", { Edqd
, XM
, Ib
} },
3508 { "pinsrb", { XM
, Edqb
, Ib
} },
3515 { "insertps", { XM
, EXd
, Ib
} },
3522 { "pinsrK", { XM
, Edq
, Ib
} },
3529 { "dpps", { XM
, EXx
, Ib
} },
3536 { "dppd", { XM
, EXx
, Ib
} },
3543 { "mpsadbw", { XM
, EXx
, Ib
} },
3550 { "pclmulqdq", { XM
, EXx
, PCLMUL
} },
3557 { "pcmpestrm", { XM
, EXx
, Ib
} },
3564 { "pcmpestri", { XM
, EXx
, Ib
} },
3571 { "pcmpistrm", { XM
, EXx
, Ib
} },
3578 { "pcmpistri", { XM
, EXx
, Ib
} },
3585 { "aeskeygenassist", { XM
, EXx
, Ib
} },
3588 /* PREFIX_VEX_0F10 */
3590 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
3591 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
3592 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
3593 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
3596 /* PREFIX_VEX_0F11 */
3598 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
3599 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
3600 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
3601 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
3604 /* PREFIX_VEX_0F12 */
3606 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
3607 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
3608 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
3609 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
3612 /* PREFIX_VEX_0F16 */
3614 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
3615 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
3616 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
3619 /* PREFIX_VEX_0F2A */
3622 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
3624 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
3627 /* PREFIX_VEX_0F2C */
3630 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
3632 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
3635 /* PREFIX_VEX_0F2D */
3638 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
3640 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
3643 /* PREFIX_VEX_0F2E */
3645 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
3647 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
3650 /* PREFIX_VEX_0F2F */
3652 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
3654 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
3657 /* PREFIX_VEX_0F51 */
3659 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
3660 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
3661 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
3662 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
3665 /* PREFIX_VEX_0F52 */
3667 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
3668 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
3671 /* PREFIX_VEX_0F53 */
3673 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
3674 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
3677 /* PREFIX_VEX_0F58 */
3679 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
3680 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
3681 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
3682 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
3685 /* PREFIX_VEX_0F59 */
3687 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
3688 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
3689 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
3690 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
3693 /* PREFIX_VEX_0F5A */
3695 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
3696 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
3697 { "vcvtpd2ps%XY", { XMM
, EXx
} },
3698 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
3701 /* PREFIX_VEX_0F5B */
3703 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
3704 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
3705 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
3708 /* PREFIX_VEX_0F5C */
3710 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
3711 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
3712 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
3713 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
3716 /* PREFIX_VEX_0F5D */
3718 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
3719 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
3720 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
3721 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
3724 /* PREFIX_VEX_0F5E */
3726 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
3727 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
3728 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
3729 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
3732 /* PREFIX_VEX_0F5F */
3734 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
3735 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
3736 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
3737 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
3740 /* PREFIX_VEX_0F60 */
3744 { VEX_LEN_TABLE (VEX_LEN_0F60_P_2
) },
3747 /* PREFIX_VEX_0F61 */
3751 { VEX_LEN_TABLE (VEX_LEN_0F61_P_2
) },
3754 /* PREFIX_VEX_0F62 */
3758 { VEX_LEN_TABLE (VEX_LEN_0F62_P_2
) },
3761 /* PREFIX_VEX_0F63 */
3765 { VEX_LEN_TABLE (VEX_LEN_0F63_P_2
) },
3768 /* PREFIX_VEX_0F64 */
3772 { VEX_LEN_TABLE (VEX_LEN_0F64_P_2
) },
3775 /* PREFIX_VEX_0F65 */
3779 { VEX_LEN_TABLE (VEX_LEN_0F65_P_2
) },
3782 /* PREFIX_VEX_0F66 */
3786 { VEX_LEN_TABLE (VEX_LEN_0F66_P_2
) },
3789 /* PREFIX_VEX_0F67 */
3793 { VEX_LEN_TABLE (VEX_LEN_0F67_P_2
) },
3796 /* PREFIX_VEX_0F68 */
3800 { VEX_LEN_TABLE (VEX_LEN_0F68_P_2
) },
3803 /* PREFIX_VEX_0F69 */
3807 { VEX_LEN_TABLE (VEX_LEN_0F69_P_2
) },
3810 /* PREFIX_VEX_0F6A */
3814 { VEX_LEN_TABLE (VEX_LEN_0F6A_P_2
) },
3817 /* PREFIX_VEX_0F6B */
3821 { VEX_LEN_TABLE (VEX_LEN_0F6B_P_2
) },
3824 /* PREFIX_VEX_0F6C */
3828 { VEX_LEN_TABLE (VEX_LEN_0F6C_P_2
) },
3831 /* PREFIX_VEX_0F6D */
3835 { VEX_LEN_TABLE (VEX_LEN_0F6D_P_2
) },
3838 /* PREFIX_VEX_0F6E */
3842 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
3845 /* PREFIX_VEX_0F6F */
3848 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
3849 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
3852 /* PREFIX_VEX_0F70 */
3855 { VEX_LEN_TABLE (VEX_LEN_0F70_P_1
) },
3856 { VEX_LEN_TABLE (VEX_LEN_0F70_P_2
) },
3857 { VEX_LEN_TABLE (VEX_LEN_0F70_P_3
) },
3860 /* PREFIX_VEX_0F71_REG_2 */
3864 { VEX_LEN_TABLE (VEX_LEN_0F71_R_2_P_2
) },
3867 /* PREFIX_VEX_0F71_REG_4 */
3871 { VEX_LEN_TABLE (VEX_LEN_0F71_R_4_P_2
) },
3874 /* PREFIX_VEX_0F71_REG_6 */
3878 { VEX_LEN_TABLE (VEX_LEN_0F71_R_6_P_2
) },
3881 /* PREFIX_VEX_0F72_REG_2 */
3885 { VEX_LEN_TABLE (VEX_LEN_0F72_R_2_P_2
) },
3888 /* PREFIX_VEX_0F72_REG_4 */
3892 { VEX_LEN_TABLE (VEX_LEN_0F72_R_4_P_2
) },
3895 /* PREFIX_VEX_0F72_REG_6 */
3899 { VEX_LEN_TABLE (VEX_LEN_0F72_R_6_P_2
) },
3902 /* PREFIX_VEX_0F73_REG_2 */
3906 { VEX_LEN_TABLE (VEX_LEN_0F73_R_2_P_2
) },
3909 /* PREFIX_VEX_0F73_REG_3 */
3913 { VEX_LEN_TABLE (VEX_LEN_0F73_R_3_P_2
) },
3916 /* PREFIX_VEX_0F73_REG_6 */
3920 { VEX_LEN_TABLE (VEX_LEN_0F73_R_6_P_2
) },
3923 /* PREFIX_VEX_0F73_REG_7 */
3927 { VEX_LEN_TABLE (VEX_LEN_0F73_R_7_P_2
) },
3930 /* PREFIX_VEX_0F74 */
3934 { VEX_LEN_TABLE (VEX_LEN_0F74_P_2
) },
3937 /* PREFIX_VEX_0F75 */
3941 { VEX_LEN_TABLE (VEX_LEN_0F75_P_2
) },
3944 /* PREFIX_VEX_0F76 */
3948 { VEX_LEN_TABLE (VEX_LEN_0F76_P_2
) },
3951 /* PREFIX_VEX_0F77 */
3953 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
3956 /* PREFIX_VEX_0F7C */
3960 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
3961 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
3964 /* PREFIX_VEX_0F7D */
3968 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
3969 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
3972 /* PREFIX_VEX_0F7E */
3975 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
3976 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
3979 /* PREFIX_VEX_0F7F */
3982 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
3983 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
3986 /* PREFIX_VEX_0FC2 */
3988 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
3989 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
3990 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
3991 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
3994 /* PREFIX_VEX_0FC4 */
3998 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
4001 /* PREFIX_VEX_0FC5 */
4005 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
4008 /* PREFIX_VEX_0FD0 */
4012 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
4013 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
4016 /* PREFIX_VEX_0FD1 */
4020 { VEX_LEN_TABLE (VEX_LEN_0FD1_P_2
) },
4023 /* PREFIX_VEX_0FD2 */
4027 { VEX_LEN_TABLE (VEX_LEN_0FD2_P_2
) },
4030 /* PREFIX_VEX_0FD3 */
4034 { VEX_LEN_TABLE (VEX_LEN_0FD3_P_2
) },
4037 /* PREFIX_VEX_0FD4 */
4041 { VEX_LEN_TABLE (VEX_LEN_0FD4_P_2
) },
4044 /* PREFIX_VEX_0FD5 */
4048 { VEX_LEN_TABLE (VEX_LEN_0FD5_P_2
) },
4051 /* PREFIX_VEX_0FD6 */
4055 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
4058 /* PREFIX_VEX_0FD7 */
4062 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
4065 /* PREFIX_VEX_0FD8 */
4069 { VEX_LEN_TABLE (VEX_LEN_0FD8_P_2
) },
4072 /* PREFIX_VEX_0FD9 */
4076 { VEX_LEN_TABLE (VEX_LEN_0FD9_P_2
) },
4079 /* PREFIX_VEX_0FDA */
4083 { VEX_LEN_TABLE (VEX_LEN_0FDA_P_2
) },
4086 /* PREFIX_VEX_0FDB */
4090 { VEX_LEN_TABLE (VEX_LEN_0FDB_P_2
) },
4093 /* PREFIX_VEX_0FDC */
4097 { VEX_LEN_TABLE (VEX_LEN_0FDC_P_2
) },
4100 /* PREFIX_VEX_0FDD */
4104 { VEX_LEN_TABLE (VEX_LEN_0FDD_P_2
) },
4107 /* PREFIX_VEX_0FDE */
4111 { VEX_LEN_TABLE (VEX_LEN_0FDE_P_2
) },
4114 /* PREFIX_VEX_0FDF */
4118 { VEX_LEN_TABLE (VEX_LEN_0FDF_P_2
) },
4121 /* PREFIX_VEX_0FE0 */
4125 { VEX_LEN_TABLE (VEX_LEN_0FE0_P_2
) },
4128 /* PREFIX_VEX_0FE1 */
4132 { VEX_LEN_TABLE (VEX_LEN_0FE1_P_2
) },
4135 /* PREFIX_VEX_0FE2 */
4139 { VEX_LEN_TABLE (VEX_LEN_0FE2_P_2
) },
4142 /* PREFIX_VEX_0FE3 */
4146 { VEX_LEN_TABLE (VEX_LEN_0FE3_P_2
) },
4149 /* PREFIX_VEX_0FE4 */
4153 { VEX_LEN_TABLE (VEX_LEN_0FE4_P_2
) },
4156 /* PREFIX_VEX_0FE5 */
4160 { VEX_LEN_TABLE (VEX_LEN_0FE5_P_2
) },
4163 /* PREFIX_VEX_0FE6 */
4166 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
4167 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
4168 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
4171 /* PREFIX_VEX_0FE7 */
4175 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
4178 /* PREFIX_VEX_0FE8 */
4182 { VEX_LEN_TABLE (VEX_LEN_0FE8_P_2
) },
4185 /* PREFIX_VEX_0FE9 */
4189 { VEX_LEN_TABLE (VEX_LEN_0FE9_P_2
) },
4192 /* PREFIX_VEX_0FEA */
4196 { VEX_LEN_TABLE (VEX_LEN_0FEA_P_2
) },
4199 /* PREFIX_VEX_0FEB */
4203 { VEX_LEN_TABLE (VEX_LEN_0FEB_P_2
) },
4206 /* PREFIX_VEX_0FEC */
4210 { VEX_LEN_TABLE (VEX_LEN_0FEC_P_2
) },
4213 /* PREFIX_VEX_0FED */
4217 { VEX_LEN_TABLE (VEX_LEN_0FED_P_2
) },
4220 /* PREFIX_VEX_0FEE */
4224 { VEX_LEN_TABLE (VEX_LEN_0FEE_P_2
) },
4227 /* PREFIX_VEX_0FEF */
4231 { VEX_LEN_TABLE (VEX_LEN_0FEF_P_2
) },
4234 /* PREFIX_VEX_0FF0 */
4239 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
4242 /* PREFIX_VEX_0FF1 */
4246 { VEX_LEN_TABLE (VEX_LEN_0FF1_P_2
) },
4249 /* PREFIX_VEX_0FF2 */
4253 { VEX_LEN_TABLE (VEX_LEN_0FF2_P_2
) },
4256 /* PREFIX_VEX_0FF3 */
4260 { VEX_LEN_TABLE (VEX_LEN_0FF3_P_2
) },
4263 /* PREFIX_VEX_0FF4 */
4267 { VEX_LEN_TABLE (VEX_LEN_0FF4_P_2
) },
4270 /* PREFIX_VEX_0FF5 */
4274 { VEX_LEN_TABLE (VEX_LEN_0FF5_P_2
) },
4277 /* PREFIX_VEX_0FF6 */
4281 { VEX_LEN_TABLE (VEX_LEN_0FF6_P_2
) },
4284 /* PREFIX_VEX_0FF7 */
4288 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
4291 /* PREFIX_VEX_0FF8 */
4295 { VEX_LEN_TABLE (VEX_LEN_0FF8_P_2
) },
4298 /* PREFIX_VEX_0FF9 */
4302 { VEX_LEN_TABLE (VEX_LEN_0FF9_P_2
) },
4305 /* PREFIX_VEX_0FFA */
4309 { VEX_LEN_TABLE (VEX_LEN_0FFA_P_2
) },
4312 /* PREFIX_VEX_0FFB */
4316 { VEX_LEN_TABLE (VEX_LEN_0FFB_P_2
) },
4319 /* PREFIX_VEX_0FFC */
4323 { VEX_LEN_TABLE (VEX_LEN_0FFC_P_2
) },
4326 /* PREFIX_VEX_0FFD */
4330 { VEX_LEN_TABLE (VEX_LEN_0FFD_P_2
) },
4333 /* PREFIX_VEX_0FFE */
4337 { VEX_LEN_TABLE (VEX_LEN_0FFE_P_2
) },
4340 /* PREFIX_VEX_0F3800 */
4344 { VEX_LEN_TABLE (VEX_LEN_0F3800_P_2
) },
4347 /* PREFIX_VEX_0F3801 */
4351 { VEX_LEN_TABLE (VEX_LEN_0F3801_P_2
) },
4354 /* PREFIX_VEX_0F3802 */
4358 { VEX_LEN_TABLE (VEX_LEN_0F3802_P_2
) },
4361 /* PREFIX_VEX_0F3803 */
4365 { VEX_LEN_TABLE (VEX_LEN_0F3803_P_2
) },
4368 /* PREFIX_VEX_0F3804 */
4372 { VEX_LEN_TABLE (VEX_LEN_0F3804_P_2
) },
4375 /* PREFIX_VEX_0F3805 */
4379 { VEX_LEN_TABLE (VEX_LEN_0F3805_P_2
) },
4382 /* PREFIX_VEX_0F3806 */
4386 { VEX_LEN_TABLE (VEX_LEN_0F3806_P_2
) },
4389 /* PREFIX_VEX_0F3807 */
4393 { VEX_LEN_TABLE (VEX_LEN_0F3807_P_2
) },
4396 /* PREFIX_VEX_0F3808 */
4400 { VEX_LEN_TABLE (VEX_LEN_0F3808_P_2
) },
4403 /* PREFIX_VEX_0F3809 */
4407 { VEX_LEN_TABLE (VEX_LEN_0F3809_P_2
) },
4410 /* PREFIX_VEX_0F380A */
4414 { VEX_LEN_TABLE (VEX_LEN_0F380A_P_2
) },
4417 /* PREFIX_VEX_0F380B */
4421 { VEX_LEN_TABLE (VEX_LEN_0F380B_P_2
) },
4424 /* PREFIX_VEX_0F380C */
4428 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
4431 /* PREFIX_VEX_0F380D */
4435 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
4438 /* PREFIX_VEX_0F380E */
4442 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
4445 /* PREFIX_VEX_0F380F */
4449 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
4452 /* PREFIX_VEX_0F3813 */
4456 { "vcvtph2ps", { XM
, EXxmmq
} },
4459 /* PREFIX_VEX_0F3817 */
4463 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
4466 /* PREFIX_VEX_0F3818 */
4470 { MOD_TABLE (MOD_VEX_0F3818_PREFIX_2
) },
4473 /* PREFIX_VEX_0F3819 */
4477 { MOD_TABLE (MOD_VEX_0F3819_PREFIX_2
) },
4480 /* PREFIX_VEX_0F381A */
4484 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
4487 /* PREFIX_VEX_0F381C */
4491 { VEX_LEN_TABLE (VEX_LEN_0F381C_P_2
) },
4494 /* PREFIX_VEX_0F381D */
4498 { VEX_LEN_TABLE (VEX_LEN_0F381D_P_2
) },
4501 /* PREFIX_VEX_0F381E */
4505 { VEX_LEN_TABLE (VEX_LEN_0F381E_P_2
) },
4508 /* PREFIX_VEX_0F3820 */
4512 { VEX_LEN_TABLE (VEX_LEN_0F3820_P_2
) },
4515 /* PREFIX_VEX_0F3821 */
4519 { VEX_LEN_TABLE (VEX_LEN_0F3821_P_2
) },
4522 /* PREFIX_VEX_0F3822 */
4526 { VEX_LEN_TABLE (VEX_LEN_0F3822_P_2
) },
4529 /* PREFIX_VEX_0F3823 */
4533 { VEX_LEN_TABLE (VEX_LEN_0F3823_P_2
) },
4536 /* PREFIX_VEX_0F3824 */
4540 { VEX_LEN_TABLE (VEX_LEN_0F3824_P_2
) },
4543 /* PREFIX_VEX_0F3825 */
4547 { VEX_LEN_TABLE (VEX_LEN_0F3825_P_2
) },
4550 /* PREFIX_VEX_0F3828 */
4554 { VEX_LEN_TABLE (VEX_LEN_0F3828_P_2
) },
4557 /* PREFIX_VEX_0F3829 */
4561 { VEX_LEN_TABLE (VEX_LEN_0F3829_P_2
) },
4564 /* PREFIX_VEX_0F382A */
4568 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
4571 /* PREFIX_VEX_0F382B */
4575 { VEX_LEN_TABLE (VEX_LEN_0F382B_P_2
) },
4578 /* PREFIX_VEX_0F382C */
4582 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
4585 /* PREFIX_VEX_0F382D */
4589 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
4592 /* PREFIX_VEX_0F382E */
4596 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
4599 /* PREFIX_VEX_0F382F */
4603 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
4606 /* PREFIX_VEX_0F3830 */
4610 { VEX_LEN_TABLE (VEX_LEN_0F3830_P_2
) },
4613 /* PREFIX_VEX_0F3831 */
4617 { VEX_LEN_TABLE (VEX_LEN_0F3831_P_2
) },
4620 /* PREFIX_VEX_0F3832 */
4624 { VEX_LEN_TABLE (VEX_LEN_0F3832_P_2
) },
4627 /* PREFIX_VEX_0F3833 */
4631 { VEX_LEN_TABLE (VEX_LEN_0F3833_P_2
) },
4634 /* PREFIX_VEX_0F3834 */
4638 { VEX_LEN_TABLE (VEX_LEN_0F3834_P_2
) },
4641 /* PREFIX_VEX_0F3835 */
4645 { VEX_LEN_TABLE (VEX_LEN_0F3835_P_2
) },
4648 /* PREFIX_VEX_0F3837 */
4652 { VEX_LEN_TABLE (VEX_LEN_0F3837_P_2
) },
4655 /* PREFIX_VEX_0F3838 */
4659 { VEX_LEN_TABLE (VEX_LEN_0F3838_P_2
) },
4662 /* PREFIX_VEX_0F3839 */
4666 { VEX_LEN_TABLE (VEX_LEN_0F3839_P_2
) },
4669 /* PREFIX_VEX_0F383A */
4673 { VEX_LEN_TABLE (VEX_LEN_0F383A_P_2
) },
4676 /* PREFIX_VEX_0F383B */
4680 { VEX_LEN_TABLE (VEX_LEN_0F383B_P_2
) },
4683 /* PREFIX_VEX_0F383C */
4687 { VEX_LEN_TABLE (VEX_LEN_0F383C_P_2
) },
4690 /* PREFIX_VEX_0F383D */
4694 { VEX_LEN_TABLE (VEX_LEN_0F383D_P_2
) },
4697 /* PREFIX_VEX_0F383E */
4701 { VEX_LEN_TABLE (VEX_LEN_0F383E_P_2
) },
4704 /* PREFIX_VEX_0F383F */
4708 { VEX_LEN_TABLE (VEX_LEN_0F383F_P_2
) },
4711 /* PREFIX_VEX_0F3840 */
4715 { VEX_LEN_TABLE (VEX_LEN_0F3840_P_2
) },
4718 /* PREFIX_VEX_0F3841 */
4722 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
4725 /* PREFIX_VEX_0F3896 */
4729 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
} },
4732 /* PREFIX_VEX_0F3897 */
4736 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
} },
4739 /* PREFIX_VEX_0F3898 */
4743 { "vfmadd132p%XW", { XM
, Vex
, EXx
} },
4746 /* PREFIX_VEX_0F3899 */
4750 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4753 /* PREFIX_VEX_0F389A */
4757 { "vfmsub132p%XW", { XM
, Vex
, EXx
} },
4760 /* PREFIX_VEX_0F389B */
4764 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4767 /* PREFIX_VEX_0F389C */
4771 { "vfnmadd132p%XW", { XM
, Vex
, EXx
} },
4774 /* PREFIX_VEX_0F389D */
4778 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4781 /* PREFIX_VEX_0F389E */
4785 { "vfnmsub132p%XW", { XM
, Vex
, EXx
} },
4788 /* PREFIX_VEX_0F389F */
4792 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4795 /* PREFIX_VEX_0F38A6 */
4799 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
} },
4803 /* PREFIX_VEX_0F38A7 */
4807 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
} },
4810 /* PREFIX_VEX_0F38A8 */
4814 { "vfmadd213p%XW", { XM
, Vex
, EXx
} },
4817 /* PREFIX_VEX_0F38A9 */
4821 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4824 /* PREFIX_VEX_0F38AA */
4828 { "vfmsub213p%XW", { XM
, Vex
, EXx
} },
4831 /* PREFIX_VEX_0F38AB */
4835 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4838 /* PREFIX_VEX_0F38AC */
4842 { "vfnmadd213p%XW", { XM
, Vex
, EXx
} },
4845 /* PREFIX_VEX_0F38AD */
4849 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4852 /* PREFIX_VEX_0F38AE */
4856 { "vfnmsub213p%XW", { XM
, Vex
, EXx
} },
4859 /* PREFIX_VEX_0F38AF */
4863 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4866 /* PREFIX_VEX_0F38B6 */
4870 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
} },
4873 /* PREFIX_VEX_0F38B7 */
4877 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
} },
4880 /* PREFIX_VEX_0F38B8 */
4884 { "vfmadd231p%XW", { XM
, Vex
, EXx
} },
4887 /* PREFIX_VEX_0F38B9 */
4891 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4894 /* PREFIX_VEX_0F38BA */
4898 { "vfmsub231p%XW", { XM
, Vex
, EXx
} },
4901 /* PREFIX_VEX_0F38BB */
4905 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4908 /* PREFIX_VEX_0F38BC */
4912 { "vfnmadd231p%XW", { XM
, Vex
, EXx
} },
4915 /* PREFIX_VEX_0F38BD */
4919 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4922 /* PREFIX_VEX_0F38BE */
4926 { "vfnmsub231p%XW", { XM
, Vex
, EXx
} },
4929 /* PREFIX_VEX_0F38BF */
4933 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4936 /* PREFIX_VEX_0F38DB */
4940 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
4943 /* PREFIX_VEX_0F38DC */
4947 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
4950 /* PREFIX_VEX_0F38DD */
4954 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
4957 /* PREFIX_VEX_0F38DE */
4961 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
4964 /* PREFIX_VEX_0F38DF */
4968 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
4971 /* PREFIX_VEX_0F3A04 */
4975 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
4978 /* PREFIX_VEX_0F3A05 */
4982 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
4985 /* PREFIX_VEX_0F3A06 */
4989 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
4992 /* PREFIX_VEX_0F3A08 */
4996 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
4999 /* PREFIX_VEX_0F3A09 */
5003 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
5006 /* PREFIX_VEX_0F3A0A */
5010 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
5013 /* PREFIX_VEX_0F3A0B */
5017 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
5020 /* PREFIX_VEX_0F3A0C */
5024 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
5027 /* PREFIX_VEX_0F3A0D */
5031 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
5034 /* PREFIX_VEX_0F3A0E */
5038 { VEX_LEN_TABLE (VEX_LEN_0F3A0E_P_2
) },
5041 /* PREFIX_VEX_0F3A0F */
5045 { VEX_LEN_TABLE (VEX_LEN_0F3A0F_P_2
) },
5048 /* PREFIX_VEX_0F3A14 */
5052 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
5055 /* PREFIX_VEX_0F3A15 */
5059 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
5062 /* PREFIX_VEX_0F3A16 */
5066 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
5069 /* PREFIX_VEX_0F3A17 */
5073 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
5076 /* PREFIX_VEX_0F3A18 */
5080 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
5083 /* PREFIX_VEX_0F3A19 */
5087 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
5090 /* PREFIX_VEX_0F3A1D */
5094 { "vcvtps2ph", { EXxmmq
, XM
, Ib
} },
5097 /* PREFIX_VEX_0F3A20 */
5101 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
5104 /* PREFIX_VEX_0F3A21 */
5108 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
5111 /* PREFIX_VEX_0F3A22 */
5115 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
5118 /* PREFIX_VEX_0F3A40 */
5122 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
5125 /* PREFIX_VEX_0F3A41 */
5129 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
5132 /* PREFIX_VEX_0F3A42 */
5136 { VEX_LEN_TABLE (VEX_LEN_0F3A42_P_2
) },
5139 /* PREFIX_VEX_0F3A44 */
5143 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
5146 /* PREFIX_VEX_0F3A48 */
5150 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
5153 /* PREFIX_VEX_0F3A49 */
5157 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
5160 /* PREFIX_VEX_0F3A4A */
5164 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
5167 /* PREFIX_VEX_0F3A4B */
5171 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
5174 /* PREFIX_VEX_0F3A4C */
5178 { VEX_LEN_TABLE (VEX_LEN_0F3A4C_P_2
) },
5181 /* PREFIX_VEX_0F3A5C */
5185 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5188 /* PREFIX_VEX_0F3A5D */
5192 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5195 /* PREFIX_VEX_0F3A5E */
5199 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5202 /* PREFIX_VEX_0F3A5F */
5206 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5209 /* PREFIX_VEX_0F3A60 */
5213 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
5217 /* PREFIX_VEX_0F3A61 */
5221 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
5224 /* PREFIX_VEX_0F3A62 */
5228 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
5231 /* PREFIX_VEX_0F3A63 */
5235 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
5238 /* PREFIX_VEX_0F3A68 */
5242 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5245 /* PREFIX_VEX_0F3A69 */
5249 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5252 /* PREFIX_VEX_0F3A6A */
5256 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
5259 /* PREFIX_VEX_0F3A6B */
5263 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
5266 /* PREFIX_VEX_0F3A6C */
5270 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5273 /* PREFIX_VEX_0F3A6D */
5277 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5280 /* PREFIX_VEX_0F3A6E */
5284 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
5287 /* PREFIX_VEX_0F3A6F */
5291 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
5294 /* PREFIX_VEX_0F3A78 */
5298 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5301 /* PREFIX_VEX_0F3A79 */
5305 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5308 /* PREFIX_VEX_0F3A7A */
5312 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
5315 /* PREFIX_VEX_0F3A7B */
5319 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
5322 /* PREFIX_VEX_0F3A7C */
5326 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5330 /* PREFIX_VEX_0F3A7D */
5334 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5337 /* PREFIX_VEX_0F3A7E */
5341 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
5344 /* PREFIX_VEX_0F3A7F */
5348 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
5351 /* PREFIX_VEX_0F3ADF */
5355 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
5359 static const struct dis386 x86_64_table
[][2] = {
5362 { "pushP", { es
} },
5372 { "pushP", { cs
} },
5377 { "pushP", { ss
} },
5387 { "pushP", { ds
} },
5417 { "pushaP", { XX
} },
5422 { "popaP", { XX
} },
5427 { MOD_TABLE (MOD_62_32BIT
) },
5432 { "arpl", { Ew
, Gw
} },
5433 { "movs{lq|xd}", { Gv
, Ed
} },
5438 { "ins{R|}", { Yzr
, indirDX
} },
5439 { "ins{G|}", { Yzr
, indirDX
} },
5444 { "outs{R|}", { indirDXr
, Xz
} },
5445 { "outs{G|}", { indirDXr
, Xz
} },
5450 { "Jcall{T|}", { Ap
} },
5455 { MOD_TABLE (MOD_C4_32BIT
) },
5456 { VEX_C4_TABLE (VEX_0F
) },
5461 { MOD_TABLE (MOD_C5_32BIT
) },
5462 { VEX_C5_TABLE (VEX_0F
) },
5482 { "Jjmp{T|}", { Ap
} },
5485 /* X86_64_0F01_REG_0 */
5487 { "sgdt{Q|IQ}", { M
} },
5491 /* X86_64_0F01_REG_1 */
5493 { "sidt{Q|IQ}", { M
} },
5497 /* X86_64_0F01_REG_2 */
5499 { "lgdt{Q|Q}", { M
} },
5503 /* X86_64_0F01_REG_3 */
5505 { "lidt{Q|Q}", { M
} },
5510 static const struct dis386 three_byte_table
[][256] = {
5512 /* THREE_BYTE_0F38 */
5515 { "pshufb", { MX
, EM
} },
5516 { "phaddw", { MX
, EM
} },
5517 { "phaddd", { MX
, EM
} },
5518 { "phaddsw", { MX
, EM
} },
5519 { "pmaddubsw", { MX
, EM
} },
5520 { "phsubw", { MX
, EM
} },
5521 { "phsubd", { MX
, EM
} },
5522 { "phsubsw", { MX
, EM
} },
5524 { "psignb", { MX
, EM
} },
5525 { "psignw", { MX
, EM
} },
5526 { "psignd", { MX
, EM
} },
5527 { "pmulhrsw", { MX
, EM
} },
5533 { PREFIX_TABLE (PREFIX_0F3810
) },
5537 { PREFIX_TABLE (PREFIX_0F3814
) },
5538 { PREFIX_TABLE (PREFIX_0F3815
) },
5540 { PREFIX_TABLE (PREFIX_0F3817
) },
5546 { "pabsb", { MX
, EM
} },
5547 { "pabsw", { MX
, EM
} },
5548 { "pabsd", { MX
, EM
} },
5551 { PREFIX_TABLE (PREFIX_0F3820
) },
5552 { PREFIX_TABLE (PREFIX_0F3821
) },
5553 { PREFIX_TABLE (PREFIX_0F3822
) },
5554 { PREFIX_TABLE (PREFIX_0F3823
) },
5555 { PREFIX_TABLE (PREFIX_0F3824
) },
5556 { PREFIX_TABLE (PREFIX_0F3825
) },
5560 { PREFIX_TABLE (PREFIX_0F3828
) },
5561 { PREFIX_TABLE (PREFIX_0F3829
) },
5562 { PREFIX_TABLE (PREFIX_0F382A
) },
5563 { PREFIX_TABLE (PREFIX_0F382B
) },
5569 { PREFIX_TABLE (PREFIX_0F3830
) },
5570 { PREFIX_TABLE (PREFIX_0F3831
) },
5571 { PREFIX_TABLE (PREFIX_0F3832
) },
5572 { PREFIX_TABLE (PREFIX_0F3833
) },
5573 { PREFIX_TABLE (PREFIX_0F3834
) },
5574 { PREFIX_TABLE (PREFIX_0F3835
) },
5576 { PREFIX_TABLE (PREFIX_0F3837
) },
5578 { PREFIX_TABLE (PREFIX_0F3838
) },
5579 { PREFIX_TABLE (PREFIX_0F3839
) },
5580 { PREFIX_TABLE (PREFIX_0F383A
) },
5581 { PREFIX_TABLE (PREFIX_0F383B
) },
5582 { PREFIX_TABLE (PREFIX_0F383C
) },
5583 { PREFIX_TABLE (PREFIX_0F383D
) },
5584 { PREFIX_TABLE (PREFIX_0F383E
) },
5585 { PREFIX_TABLE (PREFIX_0F383F
) },
5587 { PREFIX_TABLE (PREFIX_0F3840
) },
5588 { PREFIX_TABLE (PREFIX_0F3841
) },
5659 { PREFIX_TABLE (PREFIX_0F3880
) },
5660 { PREFIX_TABLE (PREFIX_0F3881
) },
5761 { PREFIX_TABLE (PREFIX_0F38DB
) },
5762 { PREFIX_TABLE (PREFIX_0F38DC
) },
5763 { PREFIX_TABLE (PREFIX_0F38DD
) },
5764 { PREFIX_TABLE (PREFIX_0F38DE
) },
5765 { PREFIX_TABLE (PREFIX_0F38DF
) },
5785 { PREFIX_TABLE (PREFIX_0F38F0
) },
5786 { PREFIX_TABLE (PREFIX_0F38F1
) },
5803 /* THREE_BYTE_0F3A */
5815 { PREFIX_TABLE (PREFIX_0F3A08
) },
5816 { PREFIX_TABLE (PREFIX_0F3A09
) },
5817 { PREFIX_TABLE (PREFIX_0F3A0A
) },
5818 { PREFIX_TABLE (PREFIX_0F3A0B
) },
5819 { PREFIX_TABLE (PREFIX_0F3A0C
) },
5820 { PREFIX_TABLE (PREFIX_0F3A0D
) },
5821 { PREFIX_TABLE (PREFIX_0F3A0E
) },
5822 { "palignr", { MX
, EM
, Ib
} },
5828 { PREFIX_TABLE (PREFIX_0F3A14
) },
5829 { PREFIX_TABLE (PREFIX_0F3A15
) },
5830 { PREFIX_TABLE (PREFIX_0F3A16
) },
5831 { PREFIX_TABLE (PREFIX_0F3A17
) },
5842 { PREFIX_TABLE (PREFIX_0F3A20
) },
5843 { PREFIX_TABLE (PREFIX_0F3A21
) },
5844 { PREFIX_TABLE (PREFIX_0F3A22
) },
5878 { PREFIX_TABLE (PREFIX_0F3A40
) },
5879 { PREFIX_TABLE (PREFIX_0F3A41
) },
5880 { PREFIX_TABLE (PREFIX_0F3A42
) },
5882 { PREFIX_TABLE (PREFIX_0F3A44
) },
5914 { PREFIX_TABLE (PREFIX_0F3A60
) },
5915 { PREFIX_TABLE (PREFIX_0F3A61
) },
5916 { PREFIX_TABLE (PREFIX_0F3A62
) },
5917 { PREFIX_TABLE (PREFIX_0F3A63
) },
6056 { PREFIX_TABLE (PREFIX_0F3ADF
) },
6095 /* THREE_BYTE_0F7A */
6134 { "ptest", { XX
} },
6171 { "phaddbw", { XM
, EXq
} },
6172 { "phaddbd", { XM
, EXq
} },
6173 { "phaddbq", { XM
, EXq
} },
6176 { "phaddwd", { XM
, EXq
} },
6177 { "phaddwq", { XM
, EXq
} },
6182 { "phadddq", { XM
, EXq
} },
6189 { "phaddubw", { XM
, EXq
} },
6190 { "phaddubd", { XM
, EXq
} },
6191 { "phaddubq", { XM
, EXq
} },
6194 { "phadduwd", { XM
, EXq
} },
6195 { "phadduwq", { XM
, EXq
} },
6200 { "phaddudq", { XM
, EXq
} },
6207 { "phsubbw", { XM
, EXq
} },
6208 { "phsubbd", { XM
, EXq
} },
6209 { "phsubbq", { XM
, EXq
} },
6388 static const struct dis386 xop_table
[][256] = {
6541 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6542 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6543 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6551 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6552 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6559 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6560 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6561 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6569 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6570 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6574 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6575 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6578 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6596 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6608 { "vprotb", { XM
, Vex_2src_1
, Ib
} },
6609 { "vprotw", { XM
, Vex_2src_1
, Ib
} },
6610 { "vprotd", { XM
, Vex_2src_1
, Ib
} },
6611 { "vprotq", { XM
, Vex_2src_1
, Ib
} },
6621 { "vpcomb", { XM
, Vex128
, EXx
, Ib
} },
6622 { "vpcomw", { XM
, Vex128
, EXx
, Ib
} },
6623 { "vpcomd", { XM
, Vex128
, EXx
, Ib
} },
6624 { "vpcomq", { XM
, Vex128
, EXx
, Ib
} },
6657 { "vpcomub", { XM
, Vex128
, EXx
, Ib
} },
6658 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
} },
6659 { "vpcomud", { XM
, Vex128
, EXx
, Ib
} },
6660 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
} },
6703 { REG_TABLE (REG_XOP_LWPCB
) },
6827 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
6828 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
6829 { "vfrczss", { XM
, EXd
} },
6830 { "vfrczsd", { XM
, EXq
} },
6845 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
} },
6846 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6847 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
} },
6848 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6849 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
} },
6850 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6851 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
} },
6852 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6854 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
} },
6855 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6856 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
} },
6857 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6900 { "vphaddbw", { XM
, EXxmm
} },
6901 { "vphaddbd", { XM
, EXxmm
} },
6902 { "vphaddbq", { XM
, EXxmm
} },
6905 { "vphaddwd", { XM
, EXxmm
} },
6906 { "vphaddwq", { XM
, EXxmm
} },
6911 { "vphadddq", { XM
, EXxmm
} },
6918 { "vphaddubw", { XM
, EXxmm
} },
6919 { "vphaddubd", { XM
, EXxmm
} },
6920 { "vphaddubq", { XM
, EXxmm
} },
6923 { "vphadduwd", { XM
, EXxmm
} },
6924 { "vphadduwq", { XM
, EXxmm
} },
6929 { "vphaddudq", { XM
, EXxmm
} },
6936 { "vphsubbw", { XM
, EXxmm
} },
6937 { "vphsubwd", { XM
, EXxmm
} },
6938 { "vphsubdq", { XM
, EXxmm
} },
6994 { REG_TABLE (REG_XOP_LWP
) },
7264 static const struct dis386 vex_table
[][256] = {
7286 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
7287 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
7288 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
7289 { MOD_TABLE (MOD_VEX_0F13
) },
7290 { VEX_W_TABLE (VEX_W_0F14
) },
7291 { VEX_W_TABLE (VEX_W_0F15
) },
7292 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
7293 { MOD_TABLE (MOD_VEX_0F17
) },
7313 { VEX_W_TABLE (VEX_W_0F28
) },
7314 { VEX_W_TABLE (VEX_W_0F29
) },
7315 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
7316 { MOD_TABLE (MOD_VEX_0F2B
) },
7317 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
7318 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
7319 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
7320 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
7358 { MOD_TABLE (MOD_VEX_0F50
) },
7359 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
7360 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
7361 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
7362 { "vandpX", { XM
, Vex
, EXx
} },
7363 { "vandnpX", { XM
, Vex
, EXx
} },
7364 { "vorpX", { XM
, Vex
, EXx
} },
7365 { "vxorpX", { XM
, Vex
, EXx
} },
7367 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
7368 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
7369 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
7370 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
7371 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
7372 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
7373 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
7374 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
7376 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
7377 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
7378 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
7379 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
7380 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
7381 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
7382 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
7383 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
7385 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
7386 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
7387 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
7388 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
7389 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
7390 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
7391 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
7392 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
7394 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
7395 { REG_TABLE (REG_VEX_0F71
) },
7396 { REG_TABLE (REG_VEX_0F72
) },
7397 { REG_TABLE (REG_VEX_0F73
) },
7398 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
7399 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
7400 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
7401 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
7407 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
7408 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
7409 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
7410 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
7463 { REG_TABLE (REG_VEX_0FAE
) },
7486 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
7488 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
7489 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
7490 { "vshufpX", { XM
, Vex
, EXx
, Ib
} },
7502 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
7503 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
7504 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
7505 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
7506 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
7507 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
7508 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
7509 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
7511 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
7512 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
7513 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
7514 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
7515 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
7516 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
7517 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
7518 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
7520 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
7521 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
7522 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
7523 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
7524 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
7525 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
7526 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
7527 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
7529 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
7530 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
7531 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
7532 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
7533 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
7534 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
7535 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
7536 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
7538 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
7539 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
7540 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
7541 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
7542 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
7543 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
7544 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
7545 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
7547 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
7548 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
7549 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
7550 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
7551 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
7552 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
7553 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
7559 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
7560 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
7561 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
7562 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
7563 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
7564 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
7565 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
7566 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
7568 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
7569 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
7570 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
7571 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
7572 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
7573 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
7574 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
7575 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
7580 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
7584 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
7586 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
7587 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
7588 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
7590 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
7591 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
7592 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
7595 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
7596 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
7597 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
7598 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
7599 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
7600 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
7604 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
7605 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
7606 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
7607 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
7608 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
7609 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
7610 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
7611 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
7613 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
7614 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
7615 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
7616 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
7617 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
7618 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
7620 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
7622 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
7623 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
7624 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
7625 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
7626 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
7627 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
7628 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
7629 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
7631 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
7632 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
7727 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
7728 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
7730 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
7731 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
7732 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
7733 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
7734 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
7735 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
7736 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
7737 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
7745 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
7746 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
7748 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
7749 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
7750 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
7751 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
7752 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
7753 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
7754 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
7755 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
7763 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
7764 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
7766 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
7767 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
7768 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
7769 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
7770 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
7771 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
7772 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
7773 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
7805 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
7806 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
7807 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
7808 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
7809 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
7854 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
7855 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
7856 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
7859 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
7860 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
7861 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
7862 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
7863 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
7864 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
7865 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
7866 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
7872 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
7873 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
7874 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
7875 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
7877 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
7878 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
7882 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
7886 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
7887 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
7888 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
7922 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
7923 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
7924 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
7926 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
7931 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
7932 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
7933 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
7934 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
7935 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
7953 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
7954 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
7955 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
7956 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
7958 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
7959 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
7960 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
7961 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
7967 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
7968 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
7969 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
7970 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
7971 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
7972 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
7973 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
7974 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
7985 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
7986 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
7987 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
7988 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
7989 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
7990 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
7991 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
7992 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
8100 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
8140 static const struct dis386 vex_len_table
[][2] = {
8141 /* VEX_LEN_0F10_P_1 */
8143 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
8144 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
8147 /* VEX_LEN_0F10_P_3 */
8149 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
8150 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
8153 /* VEX_LEN_0F11_P_1 */
8155 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
8156 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
8159 /* VEX_LEN_0F11_P_3 */
8161 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
8162 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
8165 /* VEX_LEN_0F12_P_0_M_0 */
8167 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
8170 /* VEX_LEN_0F12_P_0_M_1 */
8172 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
8175 /* VEX_LEN_0F12_P_2 */
8177 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
8180 /* VEX_LEN_0F13_M_0 */
8182 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
8185 /* VEX_LEN_0F16_P_0_M_0 */
8187 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
8190 /* VEX_LEN_0F16_P_0_M_1 */
8192 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
8195 /* VEX_LEN_0F16_P_2 */
8197 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
8200 /* VEX_LEN_0F17_M_0 */
8202 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
8205 /* VEX_LEN_0F2A_P_1 */
8207 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
8208 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
8211 /* VEX_LEN_0F2A_P_3 */
8213 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
8214 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
8217 /* VEX_LEN_0F2C_P_1 */
8219 { "vcvttss2siY", { Gv
, EXdScalar
} },
8220 { "vcvttss2siY", { Gv
, EXdScalar
} },
8223 /* VEX_LEN_0F2C_P_3 */
8225 { "vcvttsd2siY", { Gv
, EXqScalar
} },
8226 { "vcvttsd2siY", { Gv
, EXqScalar
} },
8229 /* VEX_LEN_0F2D_P_1 */
8231 { "vcvtss2siY", { Gv
, EXdScalar
} },
8232 { "vcvtss2siY", { Gv
, EXdScalar
} },
8235 /* VEX_LEN_0F2D_P_3 */
8237 { "vcvtsd2siY", { Gv
, EXqScalar
} },
8238 { "vcvtsd2siY", { Gv
, EXqScalar
} },
8241 /* VEX_LEN_0F2E_P_0 */
8243 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
8244 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
8247 /* VEX_LEN_0F2E_P_2 */
8249 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
8250 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
8253 /* VEX_LEN_0F2F_P_0 */
8255 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
8256 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
8259 /* VEX_LEN_0F2F_P_2 */
8261 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
8262 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
8265 /* VEX_LEN_0F51_P_1 */
8267 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
8268 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
8271 /* VEX_LEN_0F51_P_3 */
8273 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
8274 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
8277 /* VEX_LEN_0F52_P_1 */
8279 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
8280 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
8283 /* VEX_LEN_0F53_P_1 */
8285 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
8286 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
8289 /* VEX_LEN_0F58_P_1 */
8291 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
8292 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
8295 /* VEX_LEN_0F58_P_3 */
8297 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
8298 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
8301 /* VEX_LEN_0F59_P_1 */
8303 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
8304 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
8307 /* VEX_LEN_0F59_P_3 */
8309 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
8310 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
8313 /* VEX_LEN_0F5A_P_1 */
8315 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
8316 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
8319 /* VEX_LEN_0F5A_P_3 */
8321 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
8322 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
8325 /* VEX_LEN_0F5C_P_1 */
8327 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
8328 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
8331 /* VEX_LEN_0F5C_P_3 */
8333 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
8334 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
8337 /* VEX_LEN_0F5D_P_1 */
8339 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
8340 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
8343 /* VEX_LEN_0F5D_P_3 */
8345 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
8346 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
8349 /* VEX_LEN_0F5E_P_1 */
8351 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
8352 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
8355 /* VEX_LEN_0F5E_P_3 */
8357 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
8358 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
8361 /* VEX_LEN_0F5F_P_1 */
8363 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
8364 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
8367 /* VEX_LEN_0F5F_P_3 */
8369 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
8370 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
8373 /* VEX_LEN_0F60_P_2 */
8375 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
8378 /* VEX_LEN_0F61_P_2 */
8380 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
8383 /* VEX_LEN_0F62_P_2 */
8385 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
8388 /* VEX_LEN_0F63_P_2 */
8390 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
8393 /* VEX_LEN_0F64_P_2 */
8395 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
8398 /* VEX_LEN_0F65_P_2 */
8400 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
8403 /* VEX_LEN_0F66_P_2 */
8405 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
8408 /* VEX_LEN_0F67_P_2 */
8410 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
8413 /* VEX_LEN_0F68_P_2 */
8415 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
8418 /* VEX_LEN_0F69_P_2 */
8420 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
8423 /* VEX_LEN_0F6A_P_2 */
8425 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
8428 /* VEX_LEN_0F6B_P_2 */
8430 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
8433 /* VEX_LEN_0F6C_P_2 */
8435 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
8438 /* VEX_LEN_0F6D_P_2 */
8440 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
8443 /* VEX_LEN_0F6E_P_2 */
8445 { "vmovK", { XMScalar
, Edq
} },
8446 { "vmovK", { XMScalar
, Edq
} },
8449 /* VEX_LEN_0F70_P_1 */
8451 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
8454 /* VEX_LEN_0F70_P_2 */
8456 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
8459 /* VEX_LEN_0F70_P_3 */
8461 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
8464 /* VEX_LEN_0F71_R_2_P_2 */
8466 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
8469 /* VEX_LEN_0F71_R_4_P_2 */
8471 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
8474 /* VEX_LEN_0F71_R_6_P_2 */
8476 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
8479 /* VEX_LEN_0F72_R_2_P_2 */
8481 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
8484 /* VEX_LEN_0F72_R_4_P_2 */
8486 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
8489 /* VEX_LEN_0F72_R_6_P_2 */
8491 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
8494 /* VEX_LEN_0F73_R_2_P_2 */
8496 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
8499 /* VEX_LEN_0F73_R_3_P_2 */
8501 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
8504 /* VEX_LEN_0F73_R_6_P_2 */
8506 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
8509 /* VEX_LEN_0F73_R_7_P_2 */
8511 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
8514 /* VEX_LEN_0F74_P_2 */
8516 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
8519 /* VEX_LEN_0F75_P_2 */
8521 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
8524 /* VEX_LEN_0F76_P_2 */
8526 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
8529 /* VEX_LEN_0F7E_P_1 */
8531 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
8532 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
8535 /* VEX_LEN_0F7E_P_2 */
8537 { "vmovK", { Edq
, XMScalar
} },
8538 { "vmovK", { Edq
, XMScalar
} },
8541 /* VEX_LEN_0FAE_R_2_M_0 */
8543 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
8546 /* VEX_LEN_0FAE_R_3_M_0 */
8548 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
8551 /* VEX_LEN_0FC2_P_1 */
8553 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
8554 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
8557 /* VEX_LEN_0FC2_P_3 */
8559 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
8560 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
8563 /* VEX_LEN_0FC4_P_2 */
8565 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
8568 /* VEX_LEN_0FC5_P_2 */
8570 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
8573 /* VEX_LEN_0FD1_P_2 */
8575 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
8578 /* VEX_LEN_0FD2_P_2 */
8580 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
8583 /* VEX_LEN_0FD3_P_2 */
8585 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
8588 /* VEX_LEN_0FD4_P_2 */
8590 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
8593 /* VEX_LEN_0FD5_P_2 */
8595 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
8598 /* VEX_LEN_0FD6_P_2 */
8600 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
8601 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
8604 /* VEX_LEN_0FD7_P_2_M_1 */
8606 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
8609 /* VEX_LEN_0FD8_P_2 */
8611 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
8614 /* VEX_LEN_0FD9_P_2 */
8616 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
8619 /* VEX_LEN_0FDA_P_2 */
8621 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
8624 /* VEX_LEN_0FDB_P_2 */
8626 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
8629 /* VEX_LEN_0FDC_P_2 */
8631 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
8634 /* VEX_LEN_0FDD_P_2 */
8636 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
8639 /* VEX_LEN_0FDE_P_2 */
8641 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
8644 /* VEX_LEN_0FDF_P_2 */
8646 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
8649 /* VEX_LEN_0FE0_P_2 */
8651 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
8654 /* VEX_LEN_0FE1_P_2 */
8656 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
8659 /* VEX_LEN_0FE2_P_2 */
8661 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
8664 /* VEX_LEN_0FE3_P_2 */
8666 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
8669 /* VEX_LEN_0FE4_P_2 */
8671 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
8674 /* VEX_LEN_0FE5_P_2 */
8676 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
8679 /* VEX_LEN_0FE8_P_2 */
8681 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
8684 /* VEX_LEN_0FE9_P_2 */
8686 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
8689 /* VEX_LEN_0FEA_P_2 */
8691 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
8694 /* VEX_LEN_0FEB_P_2 */
8696 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
8699 /* VEX_LEN_0FEC_P_2 */
8701 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
8704 /* VEX_LEN_0FED_P_2 */
8706 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
8709 /* VEX_LEN_0FEE_P_2 */
8711 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
8714 /* VEX_LEN_0FEF_P_2 */
8716 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
8719 /* VEX_LEN_0FF1_P_2 */
8721 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
8724 /* VEX_LEN_0FF2_P_2 */
8726 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
8729 /* VEX_LEN_0FF3_P_2 */
8731 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
8734 /* VEX_LEN_0FF4_P_2 */
8736 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
8739 /* VEX_LEN_0FF5_P_2 */
8741 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
8744 /* VEX_LEN_0FF6_P_2 */
8746 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
8749 /* VEX_LEN_0FF7_P_2 */
8751 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
8754 /* VEX_LEN_0FF8_P_2 */
8756 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
8759 /* VEX_LEN_0FF9_P_2 */
8761 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
8764 /* VEX_LEN_0FFA_P_2 */
8766 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
8769 /* VEX_LEN_0FFB_P_2 */
8771 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
8774 /* VEX_LEN_0FFC_P_2 */
8776 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
8779 /* VEX_LEN_0FFD_P_2 */
8781 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
8784 /* VEX_LEN_0FFE_P_2 */
8786 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
8789 /* VEX_LEN_0F3800_P_2 */
8791 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
8794 /* VEX_LEN_0F3801_P_2 */
8796 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
8799 /* VEX_LEN_0F3802_P_2 */
8801 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
8804 /* VEX_LEN_0F3803_P_2 */
8806 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
8809 /* VEX_LEN_0F3804_P_2 */
8811 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
8814 /* VEX_LEN_0F3805_P_2 */
8816 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
8819 /* VEX_LEN_0F3806_P_2 */
8821 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
8824 /* VEX_LEN_0F3807_P_2 */
8826 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
8829 /* VEX_LEN_0F3808_P_2 */
8831 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
8834 /* VEX_LEN_0F3809_P_2 */
8836 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
8839 /* VEX_LEN_0F380A_P_2 */
8841 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
8844 /* VEX_LEN_0F380B_P_2 */
8846 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
8849 /* VEX_LEN_0F3819_P_2_M_0 */
8852 { VEX_W_TABLE (VEX_W_0F3819_P_2_M_0
) },
8855 /* VEX_LEN_0F381A_P_2_M_0 */
8858 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
8861 /* VEX_LEN_0F381C_P_2 */
8863 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
8866 /* VEX_LEN_0F381D_P_2 */
8868 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
8871 /* VEX_LEN_0F381E_P_2 */
8873 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
8876 /* VEX_LEN_0F3820_P_2 */
8878 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
8881 /* VEX_LEN_0F3821_P_2 */
8883 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
8886 /* VEX_LEN_0F3822_P_2 */
8888 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
8891 /* VEX_LEN_0F3823_P_2 */
8893 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
8896 /* VEX_LEN_0F3824_P_2 */
8898 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
8901 /* VEX_LEN_0F3825_P_2 */
8903 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
8906 /* VEX_LEN_0F3828_P_2 */
8908 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
8911 /* VEX_LEN_0F3829_P_2 */
8913 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
8916 /* VEX_LEN_0F382A_P_2_M_0 */
8918 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
8921 /* VEX_LEN_0F382B_P_2 */
8923 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
8926 /* VEX_LEN_0F3830_P_2 */
8928 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
8931 /* VEX_LEN_0F3831_P_2 */
8933 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
8936 /* VEX_LEN_0F3832_P_2 */
8938 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
8941 /* VEX_LEN_0F3833_P_2 */
8943 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
8946 /* VEX_LEN_0F3834_P_2 */
8948 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
8951 /* VEX_LEN_0F3835_P_2 */
8953 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
8956 /* VEX_LEN_0F3837_P_2 */
8958 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
8961 /* VEX_LEN_0F3838_P_2 */
8963 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
8966 /* VEX_LEN_0F3839_P_2 */
8968 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
8971 /* VEX_LEN_0F383A_P_2 */
8973 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
8976 /* VEX_LEN_0F383B_P_2 */
8978 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
8981 /* VEX_LEN_0F383C_P_2 */
8983 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
8986 /* VEX_LEN_0F383D_P_2 */
8988 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
8991 /* VEX_LEN_0F383E_P_2 */
8993 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
8996 /* VEX_LEN_0F383F_P_2 */
8998 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
9001 /* VEX_LEN_0F3840_P_2 */
9003 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
9006 /* VEX_LEN_0F3841_P_2 */
9008 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9011 /* VEX_LEN_0F38DB_P_2 */
9013 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9016 /* VEX_LEN_0F38DC_P_2 */
9018 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
9021 /* VEX_LEN_0F38DD_P_2 */
9023 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
9026 /* VEX_LEN_0F38DE_P_2 */
9028 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
9031 /* VEX_LEN_0F38DF_P_2 */
9033 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
9036 /* VEX_LEN_0F3A06_P_2 */
9039 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9042 /* VEX_LEN_0F3A0A_P_2 */
9044 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9045 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9048 /* VEX_LEN_0F3A0B_P_2 */
9050 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9051 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9054 /* VEX_LEN_0F3A0E_P_2 */
9056 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
9059 /* VEX_LEN_0F3A0F_P_2 */
9061 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
9064 /* VEX_LEN_0F3A14_P_2 */
9066 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
9069 /* VEX_LEN_0F3A15_P_2 */
9071 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
9074 /* VEX_LEN_0F3A16_P_2 */
9076 { "vpextrK", { Edq
, XM
, Ib
} },
9079 /* VEX_LEN_0F3A17_P_2 */
9081 { "vextractps", { Edqd
, XM
, Ib
} },
9084 /* VEX_LEN_0F3A18_P_2 */
9087 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9090 /* VEX_LEN_0F3A19_P_2 */
9093 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9096 /* VEX_LEN_0F3A20_P_2 */
9098 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
9101 /* VEX_LEN_0F3A21_P_2 */
9103 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
9106 /* VEX_LEN_0F3A22_P_2 */
9108 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
} },
9111 /* VEX_LEN_0F3A41_P_2 */
9113 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
9116 /* VEX_LEN_0F3A42_P_2 */
9118 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
9121 /* VEX_LEN_0F3A44_P_2 */
9123 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
9126 /* VEX_LEN_0F3A4C_P_2 */
9128 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
9131 /* VEX_LEN_0F3A60_P_2 */
9133 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
9136 /* VEX_LEN_0F3A61_P_2 */
9138 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
9141 /* VEX_LEN_0F3A62_P_2 */
9143 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
9146 /* VEX_LEN_0F3A63_P_2 */
9148 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
9151 /* VEX_LEN_0F3A6A_P_2 */
9153 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9156 /* VEX_LEN_0F3A6B_P_2 */
9158 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9161 /* VEX_LEN_0F3A6E_P_2 */
9163 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9166 /* VEX_LEN_0F3A6F_P_2 */
9168 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9171 /* VEX_LEN_0F3A7A_P_2 */
9173 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9176 /* VEX_LEN_0F3A7B_P_2 */
9178 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9181 /* VEX_LEN_0F3A7E_P_2 */
9183 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9186 /* VEX_LEN_0F3A7F_P_2 */
9188 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9191 /* VEX_LEN_0F3ADF_P_2 */
9193 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
9196 /* VEX_LEN_0FXOP_09_80 */
9198 { "vfrczps", { XM
, EXxmm
} },
9199 { "vfrczps", { XM
, EXymmq
} },
9202 /* VEX_LEN_0FXOP_09_81 */
9204 { "vfrczpd", { XM
, EXxmm
} },
9205 { "vfrczpd", { XM
, EXymmq
} },
9209 static const struct dis386 vex_w_table
[][2] = {
9211 /* VEX_W_0F10_P_0 */
9212 { "vmovups", { XM
, EXx
} },
9215 /* VEX_W_0F10_P_1 */
9216 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
} },
9219 /* VEX_W_0F10_P_2 */
9220 { "vmovupd", { XM
, EXx
} },
9223 /* VEX_W_0F10_P_3 */
9224 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
} },
9227 /* VEX_W_0F11_P_0 */
9228 { "vmovups", { EXxS
, XM
} },
9231 /* VEX_W_0F11_P_1 */
9232 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
} },
9235 /* VEX_W_0F11_P_2 */
9236 { "vmovupd", { EXxS
, XM
} },
9239 /* VEX_W_0F11_P_3 */
9240 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
} },
9243 /* VEX_W_0F12_P_0_M_0 */
9244 { "vmovlps", { XM
, Vex128
, EXq
} },
9247 /* VEX_W_0F12_P_0_M_1 */
9248 { "vmovhlps", { XM
, Vex128
, EXq
} },
9251 /* VEX_W_0F12_P_1 */
9252 { "vmovsldup", { XM
, EXx
} },
9255 /* VEX_W_0F12_P_2 */
9256 { "vmovlpd", { XM
, Vex128
, EXq
} },
9259 /* VEX_W_0F12_P_3 */
9260 { "vmovddup", { XM
, EXymmq
} },
9263 /* VEX_W_0F13_M_0 */
9264 { "vmovlpX", { EXq
, XM
} },
9268 { "vunpcklpX", { XM
, Vex
, EXx
} },
9272 { "vunpckhpX", { XM
, Vex
, EXx
} },
9275 /* VEX_W_0F16_P_0_M_0 */
9276 { "vmovhps", { XM
, Vex128
, EXq
} },
9279 /* VEX_W_0F16_P_0_M_1 */
9280 { "vmovlhps", { XM
, Vex128
, EXq
} },
9283 /* VEX_W_0F16_P_1 */
9284 { "vmovshdup", { XM
, EXx
} },
9287 /* VEX_W_0F16_P_2 */
9288 { "vmovhpd", { XM
, Vex128
, EXq
} },
9291 /* VEX_W_0F17_M_0 */
9292 { "vmovhpX", { EXq
, XM
} },
9296 { "vmovapX", { XM
, EXx
} },
9300 { "vmovapX", { EXxS
, XM
} },
9303 /* VEX_W_0F2B_M_0 */
9304 { "vmovntpX", { Mx
, XM
} },
9307 /* VEX_W_0F2E_P_0 */
9308 { "vucomiss", { XMScalar
, EXdScalar
} },
9311 /* VEX_W_0F2E_P_2 */
9312 { "vucomisd", { XMScalar
, EXqScalar
} },
9315 /* VEX_W_0F2F_P_0 */
9316 { "vcomiss", { XMScalar
, EXdScalar
} },
9319 /* VEX_W_0F2F_P_2 */
9320 { "vcomisd", { XMScalar
, EXqScalar
} },
9323 /* VEX_W_0F50_M_0 */
9324 { "vmovmskpX", { Gdq
, XS
} },
9327 /* VEX_W_0F51_P_0 */
9328 { "vsqrtps", { XM
, EXx
} },
9331 /* VEX_W_0F51_P_1 */
9332 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
9335 /* VEX_W_0F51_P_2 */
9336 { "vsqrtpd", { XM
, EXx
} },
9339 /* VEX_W_0F51_P_3 */
9340 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
} },
9343 /* VEX_W_0F52_P_0 */
9344 { "vrsqrtps", { XM
, EXx
} },
9347 /* VEX_W_0F52_P_1 */
9348 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
9351 /* VEX_W_0F53_P_0 */
9352 { "vrcpps", { XM
, EXx
} },
9355 /* VEX_W_0F53_P_1 */
9356 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
} },
9359 /* VEX_W_0F58_P_0 */
9360 { "vaddps", { XM
, Vex
, EXx
} },
9363 /* VEX_W_0F58_P_1 */
9364 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
} },
9367 /* VEX_W_0F58_P_2 */
9368 { "vaddpd", { XM
, Vex
, EXx
} },
9371 /* VEX_W_0F58_P_3 */
9372 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
} },
9375 /* VEX_W_0F59_P_0 */
9376 { "vmulps", { XM
, Vex
, EXx
} },
9379 /* VEX_W_0F59_P_1 */
9380 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
} },
9383 /* VEX_W_0F59_P_2 */
9384 { "vmulpd", { XM
, Vex
, EXx
} },
9387 /* VEX_W_0F59_P_3 */
9388 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
} },
9391 /* VEX_W_0F5A_P_0 */
9392 { "vcvtps2pd", { XM
, EXxmmq
} },
9395 /* VEX_W_0F5A_P_1 */
9396 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
} },
9399 /* VEX_W_0F5A_P_3 */
9400 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
} },
9403 /* VEX_W_0F5B_P_0 */
9404 { "vcvtdq2ps", { XM
, EXx
} },
9407 /* VEX_W_0F5B_P_1 */
9408 { "vcvttps2dq", { XM
, EXx
} },
9411 /* VEX_W_0F5B_P_2 */
9412 { "vcvtps2dq", { XM
, EXx
} },
9415 /* VEX_W_0F5C_P_0 */
9416 { "vsubps", { XM
, Vex
, EXx
} },
9419 /* VEX_W_0F5C_P_1 */
9420 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
} },
9423 /* VEX_W_0F5C_P_2 */
9424 { "vsubpd", { XM
, Vex
, EXx
} },
9427 /* VEX_W_0F5C_P_3 */
9428 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
} },
9431 /* VEX_W_0F5D_P_0 */
9432 { "vminps", { XM
, Vex
, EXx
} },
9435 /* VEX_W_0F5D_P_1 */
9436 { "vminss", { XMScalar
, VexScalar
, EXdScalar
} },
9439 /* VEX_W_0F5D_P_2 */
9440 { "vminpd", { XM
, Vex
, EXx
} },
9443 /* VEX_W_0F5D_P_3 */
9444 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
} },
9447 /* VEX_W_0F5E_P_0 */
9448 { "vdivps", { XM
, Vex
, EXx
} },
9451 /* VEX_W_0F5E_P_1 */
9452 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
} },
9455 /* VEX_W_0F5E_P_2 */
9456 { "vdivpd", { XM
, Vex
, EXx
} },
9459 /* VEX_W_0F5E_P_3 */
9460 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
} },
9463 /* VEX_W_0F5F_P_0 */
9464 { "vmaxps", { XM
, Vex
, EXx
} },
9467 /* VEX_W_0F5F_P_1 */
9468 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
} },
9471 /* VEX_W_0F5F_P_2 */
9472 { "vmaxpd", { XM
, Vex
, EXx
} },
9475 /* VEX_W_0F5F_P_3 */
9476 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
} },
9479 /* VEX_W_0F60_P_2 */
9480 { "vpunpcklbw", { XM
, Vex128
, EXx
} },
9483 /* VEX_W_0F61_P_2 */
9484 { "vpunpcklwd", { XM
, Vex128
, EXx
} },
9487 /* VEX_W_0F62_P_2 */
9488 { "vpunpckldq", { XM
, Vex128
, EXx
} },
9491 /* VEX_W_0F63_P_2 */
9492 { "vpacksswb", { XM
, Vex128
, EXx
} },
9495 /* VEX_W_0F64_P_2 */
9496 { "vpcmpgtb", { XM
, Vex128
, EXx
} },
9499 /* VEX_W_0F65_P_2 */
9500 { "vpcmpgtw", { XM
, Vex128
, EXx
} },
9503 /* VEX_W_0F66_P_2 */
9504 { "vpcmpgtd", { XM
, Vex128
, EXx
} },
9507 /* VEX_W_0F67_P_2 */
9508 { "vpackuswb", { XM
, Vex128
, EXx
} },
9511 /* VEX_W_0F68_P_2 */
9512 { "vpunpckhbw", { XM
, Vex128
, EXx
} },
9515 /* VEX_W_0F69_P_2 */
9516 { "vpunpckhwd", { XM
, Vex128
, EXx
} },
9519 /* VEX_W_0F6A_P_2 */
9520 { "vpunpckhdq", { XM
, Vex128
, EXx
} },
9523 /* VEX_W_0F6B_P_2 */
9524 { "vpackssdw", { XM
, Vex128
, EXx
} },
9527 /* VEX_W_0F6C_P_2 */
9528 { "vpunpcklqdq", { XM
, Vex128
, EXx
} },
9531 /* VEX_W_0F6D_P_2 */
9532 { "vpunpckhqdq", { XM
, Vex128
, EXx
} },
9535 /* VEX_W_0F6F_P_1 */
9536 { "vmovdqu", { XM
, EXx
} },
9539 /* VEX_W_0F6F_P_2 */
9540 { "vmovdqa", { XM
, EXx
} },
9543 /* VEX_W_0F70_P_1 */
9544 { "vpshufhw", { XM
, EXx
, Ib
} },
9547 /* VEX_W_0F70_P_2 */
9548 { "vpshufd", { XM
, EXx
, Ib
} },
9551 /* VEX_W_0F70_P_3 */
9552 { "vpshuflw", { XM
, EXx
, Ib
} },
9555 /* VEX_W_0F71_R_2_P_2 */
9556 { "vpsrlw", { Vex128
, XS
, Ib
} },
9559 /* VEX_W_0F71_R_4_P_2 */
9560 { "vpsraw", { Vex128
, XS
, Ib
} },
9563 /* VEX_W_0F71_R_6_P_2 */
9564 { "vpsllw", { Vex128
, XS
, Ib
} },
9567 /* VEX_W_0F72_R_2_P_2 */
9568 { "vpsrld", { Vex128
, XS
, Ib
} },
9571 /* VEX_W_0F72_R_4_P_2 */
9572 { "vpsrad", { Vex128
, XS
, Ib
} },
9575 /* VEX_W_0F72_R_6_P_2 */
9576 { "vpslld", { Vex128
, XS
, Ib
} },
9579 /* VEX_W_0F73_R_2_P_2 */
9580 { "vpsrlq", { Vex128
, XS
, Ib
} },
9583 /* VEX_W_0F73_R_3_P_2 */
9584 { "vpsrldq", { Vex128
, XS
, Ib
} },
9587 /* VEX_W_0F73_R_6_P_2 */
9588 { "vpsllq", { Vex128
, XS
, Ib
} },
9591 /* VEX_W_0F73_R_7_P_2 */
9592 { "vpslldq", { Vex128
, XS
, Ib
} },
9595 /* VEX_W_0F74_P_2 */
9596 { "vpcmpeqb", { XM
, Vex128
, EXx
} },
9599 /* VEX_W_0F75_P_2 */
9600 { "vpcmpeqw", { XM
, Vex128
, EXx
} },
9603 /* VEX_W_0F76_P_2 */
9604 { "vpcmpeqd", { XM
, Vex128
, EXx
} },
9607 /* VEX_W_0F77_P_0 */
9611 /* VEX_W_0F7C_P_2 */
9612 { "vhaddpd", { XM
, Vex
, EXx
} },
9615 /* VEX_W_0F7C_P_3 */
9616 { "vhaddps", { XM
, Vex
, EXx
} },
9619 /* VEX_W_0F7D_P_2 */
9620 { "vhsubpd", { XM
, Vex
, EXx
} },
9623 /* VEX_W_0F7D_P_3 */
9624 { "vhsubps", { XM
, Vex
, EXx
} },
9627 /* VEX_W_0F7E_P_1 */
9628 { "vmovq", { XMScalar
, EXqScalar
} },
9631 /* VEX_W_0F7F_P_1 */
9632 { "vmovdqu", { EXxS
, XM
} },
9635 /* VEX_W_0F7F_P_2 */
9636 { "vmovdqa", { EXxS
, XM
} },
9639 /* VEX_W_0FAE_R_2_M_0 */
9640 { "vldmxcsr", { Md
} },
9643 /* VEX_W_0FAE_R_3_M_0 */
9644 { "vstmxcsr", { Md
} },
9647 /* VEX_W_0FC2_P_0 */
9648 { "vcmpps", { XM
, Vex
, EXx
, VCMP
} },
9651 /* VEX_W_0FC2_P_1 */
9652 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
} },
9655 /* VEX_W_0FC2_P_2 */
9656 { "vcmppd", { XM
, Vex
, EXx
, VCMP
} },
9659 /* VEX_W_0FC2_P_3 */
9660 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
} },
9663 /* VEX_W_0FC4_P_2 */
9664 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
} },
9667 /* VEX_W_0FC5_P_2 */
9668 { "vpextrw", { Gdq
, XS
, Ib
} },
9671 /* VEX_W_0FD0_P_2 */
9672 { "vaddsubpd", { XM
, Vex
, EXx
} },
9675 /* VEX_W_0FD0_P_3 */
9676 { "vaddsubps", { XM
, Vex
, EXx
} },
9679 /* VEX_W_0FD1_P_2 */
9680 { "vpsrlw", { XM
, Vex128
, EXx
} },
9683 /* VEX_W_0FD2_P_2 */
9684 { "vpsrld", { XM
, Vex128
, EXx
} },
9687 /* VEX_W_0FD3_P_2 */
9688 { "vpsrlq", { XM
, Vex128
, EXx
} },
9691 /* VEX_W_0FD4_P_2 */
9692 { "vpaddq", { XM
, Vex128
, EXx
} },
9695 /* VEX_W_0FD5_P_2 */
9696 { "vpmullw", { XM
, Vex128
, EXx
} },
9699 /* VEX_W_0FD6_P_2 */
9700 { "vmovq", { EXqScalarS
, XMScalar
} },
9703 /* VEX_W_0FD7_P_2_M_1 */
9704 { "vpmovmskb", { Gdq
, XS
} },
9707 /* VEX_W_0FD8_P_2 */
9708 { "vpsubusb", { XM
, Vex128
, EXx
} },
9711 /* VEX_W_0FD9_P_2 */
9712 { "vpsubusw", { XM
, Vex128
, EXx
} },
9715 /* VEX_W_0FDA_P_2 */
9716 { "vpminub", { XM
, Vex128
, EXx
} },
9719 /* VEX_W_0FDB_P_2 */
9720 { "vpand", { XM
, Vex128
, EXx
} },
9723 /* VEX_W_0FDC_P_2 */
9724 { "vpaddusb", { XM
, Vex128
, EXx
} },
9727 /* VEX_W_0FDD_P_2 */
9728 { "vpaddusw", { XM
, Vex128
, EXx
} },
9731 /* VEX_W_0FDE_P_2 */
9732 { "vpmaxub", { XM
, Vex128
, EXx
} },
9735 /* VEX_W_0FDF_P_2 */
9736 { "vpandn", { XM
, Vex128
, EXx
} },
9739 /* VEX_W_0FE0_P_2 */
9740 { "vpavgb", { XM
, Vex128
, EXx
} },
9743 /* VEX_W_0FE1_P_2 */
9744 { "vpsraw", { XM
, Vex128
, EXx
} },
9747 /* VEX_W_0FE2_P_2 */
9748 { "vpsrad", { XM
, Vex128
, EXx
} },
9751 /* VEX_W_0FE3_P_2 */
9752 { "vpavgw", { XM
, Vex128
, EXx
} },
9755 /* VEX_W_0FE4_P_2 */
9756 { "vpmulhuw", { XM
, Vex128
, EXx
} },
9759 /* VEX_W_0FE5_P_2 */
9760 { "vpmulhw", { XM
, Vex128
, EXx
} },
9763 /* VEX_W_0FE6_P_1 */
9764 { "vcvtdq2pd", { XM
, EXxmmq
} },
9767 /* VEX_W_0FE6_P_2 */
9768 { "vcvttpd2dq%XY", { XMM
, EXx
} },
9771 /* VEX_W_0FE6_P_3 */
9772 { "vcvtpd2dq%XY", { XMM
, EXx
} },
9775 /* VEX_W_0FE7_P_2_M_0 */
9776 { "vmovntdq", { Mx
, XM
} },
9779 /* VEX_W_0FE8_P_2 */
9780 { "vpsubsb", { XM
, Vex128
, EXx
} },
9783 /* VEX_W_0FE9_P_2 */
9784 { "vpsubsw", { XM
, Vex128
, EXx
} },
9787 /* VEX_W_0FEA_P_2 */
9788 { "vpminsw", { XM
, Vex128
, EXx
} },
9791 /* VEX_W_0FEB_P_2 */
9792 { "vpor", { XM
, Vex128
, EXx
} },
9795 /* VEX_W_0FEC_P_2 */
9796 { "vpaddsb", { XM
, Vex128
, EXx
} },
9799 /* VEX_W_0FED_P_2 */
9800 { "vpaddsw", { XM
, Vex128
, EXx
} },
9803 /* VEX_W_0FEE_P_2 */
9804 { "vpmaxsw", { XM
, Vex128
, EXx
} },
9807 /* VEX_W_0FEF_P_2 */
9808 { "vpxor", { XM
, Vex128
, EXx
} },
9811 /* VEX_W_0FF0_P_3_M_0 */
9812 { "vlddqu", { XM
, M
} },
9815 /* VEX_W_0FF1_P_2 */
9816 { "vpsllw", { XM
, Vex128
, EXx
} },
9819 /* VEX_W_0FF2_P_2 */
9820 { "vpslld", { XM
, Vex128
, EXx
} },
9823 /* VEX_W_0FF3_P_2 */
9824 { "vpsllq", { XM
, Vex128
, EXx
} },
9827 /* VEX_W_0FF4_P_2 */
9828 { "vpmuludq", { XM
, Vex128
, EXx
} },
9831 /* VEX_W_0FF5_P_2 */
9832 { "vpmaddwd", { XM
, Vex128
, EXx
} },
9835 /* VEX_W_0FF6_P_2 */
9836 { "vpsadbw", { XM
, Vex128
, EXx
} },
9839 /* VEX_W_0FF7_P_2 */
9840 { "vmaskmovdqu", { XM
, XS
} },
9843 /* VEX_W_0FF8_P_2 */
9844 { "vpsubb", { XM
, Vex128
, EXx
} },
9847 /* VEX_W_0FF9_P_2 */
9848 { "vpsubw", { XM
, Vex128
, EXx
} },
9851 /* VEX_W_0FFA_P_2 */
9852 { "vpsubd", { XM
, Vex128
, EXx
} },
9855 /* VEX_W_0FFB_P_2 */
9856 { "vpsubq", { XM
, Vex128
, EXx
} },
9859 /* VEX_W_0FFC_P_2 */
9860 { "vpaddb", { XM
, Vex128
, EXx
} },
9863 /* VEX_W_0FFD_P_2 */
9864 { "vpaddw", { XM
, Vex128
, EXx
} },
9867 /* VEX_W_0FFE_P_2 */
9868 { "vpaddd", { XM
, Vex128
, EXx
} },
9871 /* VEX_W_0F3800_P_2 */
9872 { "vpshufb", { XM
, Vex128
, EXx
} },
9875 /* VEX_W_0F3801_P_2 */
9876 { "vphaddw", { XM
, Vex128
, EXx
} },
9879 /* VEX_W_0F3802_P_2 */
9880 { "vphaddd", { XM
, Vex128
, EXx
} },
9883 /* VEX_W_0F3803_P_2 */
9884 { "vphaddsw", { XM
, Vex128
, EXx
} },
9887 /* VEX_W_0F3804_P_2 */
9888 { "vpmaddubsw", { XM
, Vex128
, EXx
} },
9891 /* VEX_W_0F3805_P_2 */
9892 { "vphsubw", { XM
, Vex128
, EXx
} },
9895 /* VEX_W_0F3806_P_2 */
9896 { "vphsubd", { XM
, Vex128
, EXx
} },
9899 /* VEX_W_0F3807_P_2 */
9900 { "vphsubsw", { XM
, Vex128
, EXx
} },
9903 /* VEX_W_0F3808_P_2 */
9904 { "vpsignb", { XM
, Vex128
, EXx
} },
9907 /* VEX_W_0F3809_P_2 */
9908 { "vpsignw", { XM
, Vex128
, EXx
} },
9911 /* VEX_W_0F380A_P_2 */
9912 { "vpsignd", { XM
, Vex128
, EXx
} },
9915 /* VEX_W_0F380B_P_2 */
9916 { "vpmulhrsw", { XM
, Vex128
, EXx
} },
9919 /* VEX_W_0F380C_P_2 */
9920 { "vpermilps", { XM
, Vex
, EXx
} },
9923 /* VEX_W_0F380D_P_2 */
9924 { "vpermilpd", { XM
, Vex
, EXx
} },
9927 /* VEX_W_0F380E_P_2 */
9928 { "vtestps", { XM
, EXx
} },
9931 /* VEX_W_0F380F_P_2 */
9932 { "vtestpd", { XM
, EXx
} },
9935 /* VEX_W_0F3817_P_2 */
9936 { "vptest", { XM
, EXx
} },
9939 /* VEX_W_0F3818_P_2_M_0 */
9940 { "vbroadcastss", { XM
, Md
} },
9943 /* VEX_W_0F3819_P_2_M_0 */
9944 { "vbroadcastsd", { XM
, Mq
} },
9947 /* VEX_W_0F381A_P_2_M_0 */
9948 { "vbroadcastf128", { XM
, Mxmm
} },
9951 /* VEX_W_0F381C_P_2 */
9952 { "vpabsb", { XM
, EXx
} },
9955 /* VEX_W_0F381D_P_2 */
9956 { "vpabsw", { XM
, EXx
} },
9959 /* VEX_W_0F381E_P_2 */
9960 { "vpabsd", { XM
, EXx
} },
9963 /* VEX_W_0F3820_P_2 */
9964 { "vpmovsxbw", { XM
, EXq
} },
9967 /* VEX_W_0F3821_P_2 */
9968 { "vpmovsxbd", { XM
, EXd
} },
9971 /* VEX_W_0F3822_P_2 */
9972 { "vpmovsxbq", { XM
, EXw
} },
9975 /* VEX_W_0F3823_P_2 */
9976 { "vpmovsxwd", { XM
, EXq
} },
9979 /* VEX_W_0F3824_P_2 */
9980 { "vpmovsxwq", { XM
, EXd
} },
9983 /* VEX_W_0F3825_P_2 */
9984 { "vpmovsxdq", { XM
, EXq
} },
9987 /* VEX_W_0F3828_P_2 */
9988 { "vpmuldq", { XM
, Vex128
, EXx
} },
9991 /* VEX_W_0F3829_P_2 */
9992 { "vpcmpeqq", { XM
, Vex128
, EXx
} },
9995 /* VEX_W_0F382A_P_2_M_0 */
9996 { "vmovntdqa", { XM
, Mx
} },
9999 /* VEX_W_0F382B_P_2 */
10000 { "vpackusdw", { XM
, Vex128
, EXx
} },
10003 /* VEX_W_0F382C_P_2_M_0 */
10004 { "vmaskmovps", { XM
, Vex
, Mx
} },
10007 /* VEX_W_0F382D_P_2_M_0 */
10008 { "vmaskmovpd", { XM
, Vex
, Mx
} },
10011 /* VEX_W_0F382E_P_2_M_0 */
10012 { "vmaskmovps", { Mx
, Vex
, XM
} },
10015 /* VEX_W_0F382F_P_2_M_0 */
10016 { "vmaskmovpd", { Mx
, Vex
, XM
} },
10019 /* VEX_W_0F3830_P_2 */
10020 { "vpmovzxbw", { XM
, EXq
} },
10023 /* VEX_W_0F3831_P_2 */
10024 { "vpmovzxbd", { XM
, EXd
} },
10027 /* VEX_W_0F3832_P_2 */
10028 { "vpmovzxbq", { XM
, EXw
} },
10031 /* VEX_W_0F3833_P_2 */
10032 { "vpmovzxwd", { XM
, EXq
} },
10035 /* VEX_W_0F3834_P_2 */
10036 { "vpmovzxwq", { XM
, EXd
} },
10039 /* VEX_W_0F3835_P_2 */
10040 { "vpmovzxdq", { XM
, EXq
} },
10043 /* VEX_W_0F3837_P_2 */
10044 { "vpcmpgtq", { XM
, Vex128
, EXx
} },
10047 /* VEX_W_0F3838_P_2 */
10048 { "vpminsb", { XM
, Vex128
, EXx
} },
10051 /* VEX_W_0F3839_P_2 */
10052 { "vpminsd", { XM
, Vex128
, EXx
} },
10055 /* VEX_W_0F383A_P_2 */
10056 { "vpminuw", { XM
, Vex128
, EXx
} },
10059 /* VEX_W_0F383B_P_2 */
10060 { "vpminud", { XM
, Vex128
, EXx
} },
10063 /* VEX_W_0F383C_P_2 */
10064 { "vpmaxsb", { XM
, Vex128
, EXx
} },
10067 /* VEX_W_0F383D_P_2 */
10068 { "vpmaxsd", { XM
, Vex128
, EXx
} },
10071 /* VEX_W_0F383E_P_2 */
10072 { "vpmaxuw", { XM
, Vex128
, EXx
} },
10075 /* VEX_W_0F383F_P_2 */
10076 { "vpmaxud", { XM
, Vex128
, EXx
} },
10079 /* VEX_W_0F3840_P_2 */
10080 { "vpmulld", { XM
, Vex128
, EXx
} },
10083 /* VEX_W_0F3841_P_2 */
10084 { "vphminposuw", { XM
, EXx
} },
10087 /* VEX_W_0F38DB_P_2 */
10088 { "vaesimc", { XM
, EXx
} },
10091 /* VEX_W_0F38DC_P_2 */
10092 { "vaesenc", { XM
, Vex128
, EXx
} },
10095 /* VEX_W_0F38DD_P_2 */
10096 { "vaesenclast", { XM
, Vex128
, EXx
} },
10099 /* VEX_W_0F38DE_P_2 */
10100 { "vaesdec", { XM
, Vex128
, EXx
} },
10103 /* VEX_W_0F38DF_P_2 */
10104 { "vaesdeclast", { XM
, Vex128
, EXx
} },
10107 /* VEX_W_0F3A04_P_2 */
10108 { "vpermilps", { XM
, EXx
, Ib
} },
10111 /* VEX_W_0F3A05_P_2 */
10112 { "vpermilpd", { XM
, EXx
, Ib
} },
10115 /* VEX_W_0F3A06_P_2 */
10116 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
} },
10119 /* VEX_W_0F3A08_P_2 */
10120 { "vroundps", { XM
, EXx
, Ib
} },
10123 /* VEX_W_0F3A09_P_2 */
10124 { "vroundpd", { XM
, EXx
, Ib
} },
10127 /* VEX_W_0F3A0A_P_2 */
10128 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
} },
10131 /* VEX_W_0F3A0B_P_2 */
10132 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
} },
10135 /* VEX_W_0F3A0C_P_2 */
10136 { "vblendps", { XM
, Vex
, EXx
, Ib
} },
10139 /* VEX_W_0F3A0D_P_2 */
10140 { "vblendpd", { XM
, Vex
, EXx
, Ib
} },
10143 /* VEX_W_0F3A0E_P_2 */
10144 { "vpblendw", { XM
, Vex128
, EXx
, Ib
} },
10147 /* VEX_W_0F3A0F_P_2 */
10148 { "vpalignr", { XM
, Vex128
, EXx
, Ib
} },
10151 /* VEX_W_0F3A14_P_2 */
10152 { "vpextrb", { Edqb
, XM
, Ib
} },
10155 /* VEX_W_0F3A15_P_2 */
10156 { "vpextrw", { Edqw
, XM
, Ib
} },
10159 /* VEX_W_0F3A18_P_2 */
10160 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
} },
10163 /* VEX_W_0F3A19_P_2 */
10164 { "vextractf128", { EXxmm
, XM
, Ib
} },
10167 /* VEX_W_0F3A20_P_2 */
10168 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
} },
10171 /* VEX_W_0F3A21_P_2 */
10172 { "vinsertps", { XM
, Vex128
, EXd
, Ib
} },
10175 /* VEX_W_0F3A40_P_2 */
10176 { "vdpps", { XM
, Vex
, EXx
, Ib
} },
10179 /* VEX_W_0F3A41_P_2 */
10180 { "vdppd", { XM
, Vex128
, EXx
, Ib
} },
10183 /* VEX_W_0F3A42_P_2 */
10184 { "vmpsadbw", { XM
, Vex128
, EXx
, Ib
} },
10187 /* VEX_W_0F3A44_P_2 */
10188 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
} },
10191 /* VEX_W_0F3A48_P_2 */
10192 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10193 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10196 /* VEX_W_0F3A49_P_2 */
10197 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10198 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10201 /* VEX_W_0F3A4A_P_2 */
10202 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
} },
10205 /* VEX_W_0F3A4B_P_2 */
10206 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
} },
10209 /* VEX_W_0F3A4C_P_2 */
10210 { "vpblendvb", { XM
, Vex128
, EXx
, XMVexI4
} },
10213 /* VEX_W_0F3A60_P_2 */
10214 { "vpcmpestrm", { XM
, EXx
, Ib
} },
10217 /* VEX_W_0F3A61_P_2 */
10218 { "vpcmpestri", { XM
, EXx
, Ib
} },
10221 /* VEX_W_0F3A62_P_2 */
10222 { "vpcmpistrm", { XM
, EXx
, Ib
} },
10225 /* VEX_W_0F3A63_P_2 */
10226 { "vpcmpistri", { XM
, EXx
, Ib
} },
10229 /* VEX_W_0F3ADF_P_2 */
10230 { "vaeskeygenassist", { XM
, EXx
, Ib
} },
10234 static const struct dis386 mod_table
[][2] = {
10237 { "leaS", { Gv
, M
} },
10240 /* MOD_0F01_REG_0 */
10241 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10242 { RM_TABLE (RM_0F01_REG_0
) },
10245 /* MOD_0F01_REG_1 */
10246 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10247 { RM_TABLE (RM_0F01_REG_1
) },
10250 /* MOD_0F01_REG_2 */
10251 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10252 { RM_TABLE (RM_0F01_REG_2
) },
10255 /* MOD_0F01_REG_3 */
10256 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10257 { RM_TABLE (RM_0F01_REG_3
) },
10260 /* MOD_0F01_REG_7 */
10261 { "invlpg", { Mb
} },
10262 { RM_TABLE (RM_0F01_REG_7
) },
10265 /* MOD_0F12_PREFIX_0 */
10266 { "movlps", { XM
, EXq
} },
10267 { "movhlps", { XM
, EXq
} },
10271 { "movlpX", { EXq
, XM
} },
10274 /* MOD_0F16_PREFIX_0 */
10275 { "movhps", { XM
, EXq
} },
10276 { "movlhps", { XM
, EXq
} },
10280 { "movhpX", { EXq
, XM
} },
10283 /* MOD_0F18_REG_0 */
10284 { "prefetchnta", { Mb
} },
10287 /* MOD_0F18_REG_1 */
10288 { "prefetcht0", { Mb
} },
10291 /* MOD_0F18_REG_2 */
10292 { "prefetcht1", { Mb
} },
10295 /* MOD_0F18_REG_3 */
10296 { "prefetcht2", { Mb
} },
10301 { "movZ", { Rm
, Cm
} },
10306 { "movZ", { Rm
, Dm
} },
10311 { "movZ", { Cm
, Rm
} },
10316 { "movZ", { Dm
, Rm
} },
10321 { "movL", { Rd
, Td
} },
10326 { "movL", { Td
, Rd
} },
10329 /* MOD_0F2B_PREFIX_0 */
10330 {"movntps", { Mx
, XM
} },
10333 /* MOD_0F2B_PREFIX_1 */
10334 {"movntss", { Md
, XM
} },
10337 /* MOD_0F2B_PREFIX_2 */
10338 {"movntpd", { Mx
, XM
} },
10341 /* MOD_0F2B_PREFIX_3 */
10342 {"movntsd", { Mq
, XM
} },
10347 { "movmskpX", { Gdq
, XS
} },
10350 /* MOD_0F71_REG_2 */
10352 { "psrlw", { MS
, Ib
} },
10355 /* MOD_0F71_REG_4 */
10357 { "psraw", { MS
, Ib
} },
10360 /* MOD_0F71_REG_6 */
10362 { "psllw", { MS
, Ib
} },
10365 /* MOD_0F72_REG_2 */
10367 { "psrld", { MS
, Ib
} },
10370 /* MOD_0F72_REG_4 */
10372 { "psrad", { MS
, Ib
} },
10375 /* MOD_0F72_REG_6 */
10377 { "pslld", { MS
, Ib
} },
10380 /* MOD_0F73_REG_2 */
10382 { "psrlq", { MS
, Ib
} },
10385 /* MOD_0F73_REG_3 */
10387 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10390 /* MOD_0F73_REG_6 */
10392 { "psllq", { MS
, Ib
} },
10395 /* MOD_0F73_REG_7 */
10397 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10400 /* MOD_0FAE_REG_0 */
10401 { "fxsave", { FXSAVE
} },
10402 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
10405 /* MOD_0FAE_REG_1 */
10406 { "fxrstor", { FXSAVE
} },
10407 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
10410 /* MOD_0FAE_REG_2 */
10411 { "ldmxcsr", { Md
} },
10412 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
10415 /* MOD_0FAE_REG_3 */
10416 { "stmxcsr", { Md
} },
10417 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
10420 /* MOD_0FAE_REG_4 */
10421 { "xsave", { FXSAVE
} },
10424 /* MOD_0FAE_REG_5 */
10425 { "xrstor", { FXSAVE
} },
10426 { RM_TABLE (RM_0FAE_REG_5
) },
10429 /* MOD_0FAE_REG_6 */
10430 { "xsaveopt", { FXSAVE
} },
10431 { RM_TABLE (RM_0FAE_REG_6
) },
10434 /* MOD_0FAE_REG_7 */
10435 { "clflush", { Mb
} },
10436 { RM_TABLE (RM_0FAE_REG_7
) },
10440 { "lssS", { Gv
, Mp
} },
10444 { "lfsS", { Gv
, Mp
} },
10448 { "lgsS", { Gv
, Mp
} },
10451 /* MOD_0FC7_REG_6 */
10452 { PREFIX_TABLE (PREFIX_0FC7_REG_6
) },
10453 { "rdrand", { Ev
} },
10456 /* MOD_0FC7_REG_7 */
10457 { "vmptrst", { Mq
} },
10462 { "pmovmskb", { Gdq
, MS
} },
10465 /* MOD_0FE7_PREFIX_2 */
10466 { "movntdq", { Mx
, XM
} },
10469 /* MOD_0FF0_PREFIX_3 */
10470 { "lddqu", { XM
, M
} },
10473 /* MOD_0F382A_PREFIX_2 */
10474 { "movntdqa", { XM
, Mx
} },
10478 { "bound{S|}", { Gv
, Ma
} },
10482 { "lesS", { Gv
, Mp
} },
10483 { VEX_C4_TABLE (VEX_0F
) },
10487 { "ldsS", { Gv
, Mp
} },
10488 { VEX_C5_TABLE (VEX_0F
) },
10491 /* MOD_VEX_0F12_PREFIX_0 */
10492 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10493 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10497 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10500 /* MOD_VEX_0F16_PREFIX_0 */
10501 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10502 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10506 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10510 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
10515 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
10518 /* MOD_VEX_0F71_REG_2 */
10520 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10523 /* MOD_VEX_0F71_REG_4 */
10525 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10528 /* MOD_VEX_0F71_REG_6 */
10530 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10533 /* MOD_VEX_0F72_REG_2 */
10535 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10538 /* MOD_VEX_0F72_REG_4 */
10540 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10543 /* MOD_VEX_0F72_REG_6 */
10545 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10548 /* MOD_VEX_0F73_REG_2 */
10550 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10553 /* MOD_VEX_0F73_REG_3 */
10555 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10558 /* MOD_VEX_0F73_REG_6 */
10560 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10563 /* MOD_VEX_0F73_REG_7 */
10565 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10568 /* MOD_VEX_0FAE_REG_2 */
10569 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10572 /* MOD_VEX_0FAE_REG_3 */
10573 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10576 /* MOD_VEX_0FD7_PREFIX_2 */
10578 { VEX_LEN_TABLE (VEX_LEN_0FD7_P_2_M_1
) },
10581 /* MOD_VEX_0FE7_PREFIX_2 */
10582 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
10585 /* MOD_VEX_0FF0_PREFIX_3 */
10586 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
10589 /* MOD_VEX_0F3818_PREFIX_2 */
10590 { VEX_W_TABLE (VEX_W_0F3818_P_2_M_0
) },
10593 /* MOD_VEX_0F3819_PREFIX_2 */
10594 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2_M_0
) },
10597 /* MOD_VEX_0F381A_PREFIX_2 */
10598 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10601 /* MOD_VEX_0F382A_PREFIX_2 */
10602 { VEX_LEN_TABLE (VEX_LEN_0F382A_P_2_M_0
) },
10605 /* MOD_VEX_0F382C_PREFIX_2 */
10606 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10609 /* MOD_VEX_0F382D_PREFIX_2 */
10610 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10613 /* MOD_VEX_0F382E_PREFIX_2 */
10614 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10617 /* MOD_VEX_0F382F_PREFIX_2 */
10618 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10622 static const struct dis386 rm_table
[][8] = {
10624 /* RM_0F01_REG_0 */
10626 { "vmcall", { Skip_MODRM
} },
10627 { "vmlaunch", { Skip_MODRM
} },
10628 { "vmresume", { Skip_MODRM
} },
10629 { "vmxoff", { Skip_MODRM
} },
10632 /* RM_0F01_REG_1 */
10633 { "monitor", { { OP_Monitor
, 0 } } },
10634 { "mwait", { { OP_Mwait
, 0 } } },
10637 /* RM_0F01_REG_2 */
10638 { "xgetbv", { Skip_MODRM
} },
10639 { "xsetbv", { Skip_MODRM
} },
10642 /* RM_0F01_REG_3 */
10643 { "vmrun", { Skip_MODRM
} },
10644 { "vmmcall", { Skip_MODRM
} },
10645 { "vmload", { Skip_MODRM
} },
10646 { "vmsave", { Skip_MODRM
} },
10647 { "stgi", { Skip_MODRM
} },
10648 { "clgi", { Skip_MODRM
} },
10649 { "skinit", { Skip_MODRM
} },
10650 { "invlpga", { Skip_MODRM
} },
10653 /* RM_0F01_REG_7 */
10654 { "swapgs", { Skip_MODRM
} },
10655 { "rdtscp", { Skip_MODRM
} },
10658 /* RM_0FAE_REG_5 */
10659 { "lfence", { Skip_MODRM
} },
10662 /* RM_0FAE_REG_6 */
10663 { "mfence", { Skip_MODRM
} },
10666 /* RM_0FAE_REG_7 */
10667 { "sfence", { Skip_MODRM
} },
10671 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10673 /* We use the high bit to indicate different name for the same
10675 #define ADDR16_PREFIX (0x67 | 0x100)
10676 #define ADDR32_PREFIX (0x67 | 0x200)
10677 #define DATA16_PREFIX (0x66 | 0x100)
10678 #define DATA32_PREFIX (0x66 | 0x200)
10679 #define REP_PREFIX (0xf3 | 0x100)
10684 int newrex
, i
, length
;
10690 last_lock_prefix
= -1;
10691 last_repz_prefix
= -1;
10692 last_repnz_prefix
= -1;
10693 last_data_prefix
= -1;
10694 last_addr_prefix
= -1;
10695 last_rex_prefix
= -1;
10696 last_seg_prefix
= -1;
10697 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
10698 all_prefixes
[i
] = 0;
10701 /* The maximum instruction length is 15bytes. */
10702 while (length
< MAX_CODE_LENGTH
- 1)
10704 FETCH_DATA (the_info
, codep
+ 1);
10708 /* REX prefixes family. */
10725 if (address_mode
== mode_64bit
)
10729 last_rex_prefix
= i
;
10732 prefixes
|= PREFIX_REPZ
;
10733 last_repz_prefix
= i
;
10736 prefixes
|= PREFIX_REPNZ
;
10737 last_repnz_prefix
= i
;
10740 prefixes
|= PREFIX_LOCK
;
10741 last_lock_prefix
= i
;
10744 prefixes
|= PREFIX_CS
;
10745 last_seg_prefix
= i
;
10748 prefixes
|= PREFIX_SS
;
10749 last_seg_prefix
= i
;
10752 prefixes
|= PREFIX_DS
;
10753 last_seg_prefix
= i
;
10756 prefixes
|= PREFIX_ES
;
10757 last_seg_prefix
= i
;
10760 prefixes
|= PREFIX_FS
;
10761 last_seg_prefix
= i
;
10764 prefixes
|= PREFIX_GS
;
10765 last_seg_prefix
= i
;
10768 prefixes
|= PREFIX_DATA
;
10769 last_data_prefix
= i
;
10772 prefixes
|= PREFIX_ADDR
;
10773 last_addr_prefix
= i
;
10776 /* fwait is really an instruction. If there are prefixes
10777 before the fwait, they belong to the fwait, *not* to the
10778 following instruction. */
10779 if (prefixes
|| rex
)
10781 prefixes
|= PREFIX_FWAIT
;
10785 prefixes
= PREFIX_FWAIT
;
10790 /* Rex is ignored when followed by another prefix. */
10796 if (*codep
!= FWAIT_OPCODE
)
10797 all_prefixes
[i
++] = *codep
;
10806 seg_prefix (int pref
)
10827 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10830 static const char *
10831 prefix_name (int pref
, int sizeflag
)
10833 static const char *rexes
[16] =
10836 "rex.B", /* 0x41 */
10837 "rex.X", /* 0x42 */
10838 "rex.XB", /* 0x43 */
10839 "rex.R", /* 0x44 */
10840 "rex.RB", /* 0x45 */
10841 "rex.RX", /* 0x46 */
10842 "rex.RXB", /* 0x47 */
10843 "rex.W", /* 0x48 */
10844 "rex.WB", /* 0x49 */
10845 "rex.WX", /* 0x4a */
10846 "rex.WXB", /* 0x4b */
10847 "rex.WR", /* 0x4c */
10848 "rex.WRB", /* 0x4d */
10849 "rex.WRX", /* 0x4e */
10850 "rex.WRXB", /* 0x4f */
10855 /* REX prefixes family. */
10872 return rexes
[pref
- 0x40];
10892 return (sizeflag
& DFLAG
) ? "data16" : "data32";
10894 if (address_mode
== mode_64bit
)
10895 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
10897 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
10900 case ADDR16_PREFIX
:
10902 case ADDR32_PREFIX
:
10904 case DATA16_PREFIX
:
10906 case DATA32_PREFIX
:
10915 static char op_out
[MAX_OPERANDS
][100];
10916 static int op_ad
, op_index
[MAX_OPERANDS
];
10917 static int two_source_ops
;
10918 static bfd_vma op_address
[MAX_OPERANDS
];
10919 static bfd_vma op_riprel
[MAX_OPERANDS
];
10920 static bfd_vma start_pc
;
10923 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10924 * (see topic "Redundant prefixes" in the "Differences from 8086"
10925 * section of the "Virtual 8086 Mode" chapter.)
10926 * 'pc' should be the address of this instruction, it will
10927 * be used to print the target address if this is a relative jump or call
10928 * The function returns the length of this instruction in bytes.
10931 static char intel_syntax
;
10932 static char intel_mnemonic
= !SYSV386_COMPAT
;
10933 static char open_char
;
10934 static char close_char
;
10935 static char separator_char
;
10936 static char scale_char
;
10938 /* Here for backwards compatibility. When gdb stops using
10939 print_insn_i386_att and print_insn_i386_intel these functions can
10940 disappear, and print_insn_i386 be merged into print_insn. */
10942 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
10946 return print_insn (pc
, info
);
10950 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
10954 return print_insn (pc
, info
);
10958 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
10962 return print_insn (pc
, info
);
10966 print_i386_disassembler_options (FILE *stream
)
10968 fprintf (stream
, _("\n\
10969 The following i386/x86-64 specific disassembler options are supported for use\n\
10970 with the -M switch (multiple options should be separated by commas):\n"));
10972 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
10973 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
10974 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
10975 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
10976 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
10977 fprintf (stream
, _(" att-mnemonic\n"
10978 " Display instruction in AT&T mnemonic\n"));
10979 fprintf (stream
, _(" intel-mnemonic\n"
10980 " Display instruction in Intel mnemonic\n"));
10981 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
10982 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
10983 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
10984 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
10985 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
10986 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
10990 static const struct dis386 bad_opcode
= { "(bad)", { XX
} };
10992 /* Get a pointer to struct dis386 with a valid name. */
10994 static const struct dis386
*
10995 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
10997 int vindex
, vex_table_index
;
10999 if (dp
->name
!= NULL
)
11002 switch (dp
->op
[0].bytemode
)
11004 case USE_REG_TABLE
:
11005 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11008 case USE_MOD_TABLE
:
11009 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11010 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11014 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11017 case USE_PREFIX_TABLE
:
11020 /* The prefix in VEX is implicit. */
11021 switch (vex
.prefix
)
11026 case REPE_PREFIX_OPCODE
:
11029 case DATA_PREFIX_OPCODE
:
11032 case REPNE_PREFIX_OPCODE
:
11043 used_prefixes
|= (prefixes
& PREFIX_REPZ
);
11044 if (prefixes
& PREFIX_REPZ
)
11047 all_prefixes
[last_repz_prefix
] = 0;
11051 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11053 used_prefixes
|= (prefixes
& PREFIX_REPNZ
);
11054 if (prefixes
& PREFIX_REPNZ
)
11057 all_prefixes
[last_repnz_prefix
] = 0;
11061 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11062 if (prefixes
& PREFIX_DATA
)
11065 all_prefixes
[last_data_prefix
] = 0;
11070 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11073 case USE_X86_64_TABLE
:
11074 vindex
= address_mode
== mode_64bit
? 1 : 0;
11075 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11078 case USE_3BYTE_TABLE
:
11079 FETCH_DATA (info
, codep
+ 2);
11081 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11082 modrm
.mod
= (*codep
>> 6) & 3;
11083 modrm
.reg
= (*codep
>> 3) & 7;
11084 modrm
.rm
= *codep
& 7;
11087 case USE_VEX_LEN_TABLE
:
11091 switch (vex
.length
)
11104 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11107 case USE_XOP_8F_TABLE
:
11108 FETCH_DATA (info
, codep
+ 3);
11109 /* All bits in the REX prefix are ignored. */
11111 rex
= ~(*codep
>> 5) & 0x7;
11113 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11114 switch ((*codep
& 0x1f))
11120 vex_table_index
= XOP_08
;
11123 vex_table_index
= XOP_09
;
11126 vex_table_index
= XOP_0A
;
11130 vex
.w
= *codep
& 0x80;
11131 if (vex
.w
&& address_mode
== mode_64bit
)
11134 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11135 if (address_mode
!= mode_64bit
11136 && vex
.register_specifier
> 0x7)
11142 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11143 switch ((*codep
& 0x3))
11149 vex
.prefix
= DATA_PREFIX_OPCODE
;
11152 vex
.prefix
= REPE_PREFIX_OPCODE
;
11155 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11162 dp
= &xop_table
[vex_table_index
][vindex
];
11164 FETCH_DATA (info
, codep
+ 1);
11165 modrm
.mod
= (*codep
>> 6) & 3;
11166 modrm
.reg
= (*codep
>> 3) & 7;
11167 modrm
.rm
= *codep
& 7;
11170 case USE_VEX_C4_TABLE
:
11171 FETCH_DATA (info
, codep
+ 3);
11172 /* All bits in the REX prefix are ignored. */
11174 rex
= ~(*codep
>> 5) & 0x7;
11175 switch ((*codep
& 0x1f))
11181 vex_table_index
= VEX_0F
;
11184 vex_table_index
= VEX_0F38
;
11187 vex_table_index
= VEX_0F3A
;
11191 vex
.w
= *codep
& 0x80;
11192 if (vex
.w
&& address_mode
== mode_64bit
)
11195 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11196 if (address_mode
!= mode_64bit
11197 && vex
.register_specifier
> 0x7)
11203 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11204 switch ((*codep
& 0x3))
11210 vex
.prefix
= DATA_PREFIX_OPCODE
;
11213 vex
.prefix
= REPE_PREFIX_OPCODE
;
11216 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11223 dp
= &vex_table
[vex_table_index
][vindex
];
11224 /* There is no MODRM byte for VEX [82|77]. */
11225 if (vindex
!= 0x77 && vindex
!= 0x82)
11227 FETCH_DATA (info
, codep
+ 1);
11228 modrm
.mod
= (*codep
>> 6) & 3;
11229 modrm
.reg
= (*codep
>> 3) & 7;
11230 modrm
.rm
= *codep
& 7;
11234 case USE_VEX_C5_TABLE
:
11235 FETCH_DATA (info
, codep
+ 2);
11236 /* All bits in the REX prefix are ignored. */
11238 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11240 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11241 if (address_mode
!= mode_64bit
11242 && vex
.register_specifier
> 0x7)
11250 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11251 switch ((*codep
& 0x3))
11257 vex
.prefix
= DATA_PREFIX_OPCODE
;
11260 vex
.prefix
= REPE_PREFIX_OPCODE
;
11263 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11270 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11271 /* There is no MODRM byte for VEX [82|77]. */
11272 if (vindex
!= 0x77 && vindex
!= 0x82)
11274 FETCH_DATA (info
, codep
+ 1);
11275 modrm
.mod
= (*codep
>> 6) & 3;
11276 modrm
.reg
= (*codep
>> 3) & 7;
11277 modrm
.rm
= *codep
& 7;
11281 case USE_VEX_W_TABLE
:
11285 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11296 if (dp
->name
!= NULL
)
11299 return get_valid_dis386 (dp
, info
);
11303 get_sib (disassemble_info
*info
)
11305 /* If modrm.mod == 3, operand must be register. */
11307 && address_mode
!= mode_16bit
11311 FETCH_DATA (info
, codep
+ 2);
11312 sib
.index
= (codep
[1] >> 3) & 7;
11313 sib
.scale
= (codep
[1] >> 6) & 3;
11314 sib
.base
= codep
[1] & 7;
11319 print_insn (bfd_vma pc
, disassemble_info
*info
)
11321 const struct dis386
*dp
;
11323 char *op_txt
[MAX_OPERANDS
];
11327 struct dis_private priv
;
11329 int default_prefixes
;
11331 if (info
->mach
== bfd_mach_x86_64_intel_syntax
11332 || info
->mach
== bfd_mach_x86_64
11333 || info
->mach
== bfd_mach_x64_32_intel_syntax
11334 || info
->mach
== bfd_mach_x64_32
11335 || info
->mach
== bfd_mach_l1om
11336 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11337 address_mode
= mode_64bit
;
11339 address_mode
= mode_32bit
;
11341 if (intel_syntax
== (char) -1)
11342 intel_syntax
= (info
->mach
== bfd_mach_i386_i386_intel_syntax
11343 || info
->mach
== bfd_mach_x86_64_intel_syntax
11344 || info
->mach
== bfd_mach_x64_32_intel_syntax
11345 || info
->mach
== bfd_mach_l1om_intel_syntax
);
11347 if (info
->mach
== bfd_mach_i386_i386
11348 || info
->mach
== bfd_mach_x86_64
11349 || info
->mach
== bfd_mach_x64_32
11350 || info
->mach
== bfd_mach_l1om
11351 || info
->mach
== bfd_mach_i386_i386_intel_syntax
11352 || info
->mach
== bfd_mach_x86_64_intel_syntax
11353 || info
->mach
== bfd_mach_x64_32_intel_syntax
11354 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11355 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11356 else if (info
->mach
== bfd_mach_i386_i8086
)
11357 priv
.orig_sizeflag
= 0;
11361 for (p
= info
->disassembler_options
; p
!= NULL
; )
11363 if (CONST_STRNEQ (p
, "x86-64"))
11365 address_mode
= mode_64bit
;
11366 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11368 else if (CONST_STRNEQ (p
, "i386"))
11370 address_mode
= mode_32bit
;
11371 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11373 else if (CONST_STRNEQ (p
, "i8086"))
11375 address_mode
= mode_16bit
;
11376 priv
.orig_sizeflag
= 0;
11378 else if (CONST_STRNEQ (p
, "intel"))
11381 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11382 intel_mnemonic
= 1;
11384 else if (CONST_STRNEQ (p
, "att"))
11387 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11388 intel_mnemonic
= 0;
11390 else if (CONST_STRNEQ (p
, "addr"))
11392 if (address_mode
== mode_64bit
)
11394 if (p
[4] == '3' && p
[5] == '2')
11395 priv
.orig_sizeflag
&= ~AFLAG
;
11396 else if (p
[4] == '6' && p
[5] == '4')
11397 priv
.orig_sizeflag
|= AFLAG
;
11401 if (p
[4] == '1' && p
[5] == '6')
11402 priv
.orig_sizeflag
&= ~AFLAG
;
11403 else if (p
[4] == '3' && p
[5] == '2')
11404 priv
.orig_sizeflag
|= AFLAG
;
11407 else if (CONST_STRNEQ (p
, "data"))
11409 if (p
[4] == '1' && p
[5] == '6')
11410 priv
.orig_sizeflag
&= ~DFLAG
;
11411 else if (p
[4] == '3' && p
[5] == '2')
11412 priv
.orig_sizeflag
|= DFLAG
;
11414 else if (CONST_STRNEQ (p
, "suffix"))
11415 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11417 p
= strchr (p
, ',');
11424 names64
= intel_names64
;
11425 names32
= intel_names32
;
11426 names16
= intel_names16
;
11427 names8
= intel_names8
;
11428 names8rex
= intel_names8rex
;
11429 names_seg
= intel_names_seg
;
11430 names_mm
= intel_names_mm
;
11431 names_xmm
= intel_names_xmm
;
11432 names_ymm
= intel_names_ymm
;
11433 index64
= intel_index64
;
11434 index32
= intel_index32
;
11435 index16
= intel_index16
;
11438 separator_char
= '+';
11443 names64
= att_names64
;
11444 names32
= att_names32
;
11445 names16
= att_names16
;
11446 names8
= att_names8
;
11447 names8rex
= att_names8rex
;
11448 names_seg
= att_names_seg
;
11449 names_mm
= att_names_mm
;
11450 names_xmm
= att_names_xmm
;
11451 names_ymm
= att_names_ymm
;
11452 index64
= att_index64
;
11453 index32
= att_index32
;
11454 index16
= att_index16
;
11457 separator_char
= ',';
11461 /* The output looks better if we put 7 bytes on a line, since that
11462 puts most long word instructions on a single line. Use 8 bytes
11464 if (info
->mach
== bfd_mach_l1om
11465 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11466 info
->bytes_per_line
= 8;
11468 info
->bytes_per_line
= 7;
11470 info
->private_data
= &priv
;
11471 priv
.max_fetched
= priv
.the_buffer
;
11472 priv
.insn_start
= pc
;
11475 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11483 start_codep
= priv
.the_buffer
;
11484 codep
= priv
.the_buffer
;
11486 if (setjmp (priv
.bailout
) != 0)
11490 /* Getting here means we tried for data but didn't get it. That
11491 means we have an incomplete instruction of some sort. Just
11492 print the first byte as a prefix or a .byte pseudo-op. */
11493 if (codep
> priv
.the_buffer
)
11495 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
11497 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11500 /* Just print the first byte as a .byte instruction. */
11501 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
11502 (unsigned int) priv
.the_buffer
[0]);
11512 sizeflag
= priv
.orig_sizeflag
;
11514 if (!ckprefix () || rex_used
)
11516 /* Too many prefixes or unused REX prefixes. */
11518 all_prefixes
[i
] && i
< (int) ARRAY_SIZE (all_prefixes
);
11520 (*info
->fprintf_func
) (info
->stream
, "%s",
11521 prefix_name (all_prefixes
[i
], sizeflag
));
11525 insn_codep
= codep
;
11527 FETCH_DATA (info
, codep
+ 1);
11528 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
11530 if (((prefixes
& PREFIX_FWAIT
)
11531 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
11533 (*info
->fprintf_func
) (info
->stream
, "fwait");
11537 if (*codep
== 0x0f)
11539 unsigned char threebyte
;
11540 FETCH_DATA (info
, codep
+ 2);
11541 threebyte
= *++codep
;
11542 dp
= &dis386_twobyte
[threebyte
];
11543 need_modrm
= twobyte_has_modrm
[*codep
];
11548 dp
= &dis386
[*codep
];
11549 need_modrm
= onebyte_has_modrm
[*codep
];
11553 if ((prefixes
& PREFIX_REPZ
))
11554 used_prefixes
|= PREFIX_REPZ
;
11555 if ((prefixes
& PREFIX_REPNZ
))
11556 used_prefixes
|= PREFIX_REPNZ
;
11557 if ((prefixes
& PREFIX_LOCK
))
11558 used_prefixes
|= PREFIX_LOCK
;
11560 default_prefixes
= 0;
11561 if (prefixes
& PREFIX_ADDR
)
11564 if (dp
->op
[2].bytemode
!= loop_jcxz_mode
|| intel_syntax
)
11566 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11567 all_prefixes
[last_addr_prefix
] = ADDR32_PREFIX
;
11569 all_prefixes
[last_addr_prefix
] = ADDR16_PREFIX
;
11570 default_prefixes
|= PREFIX_ADDR
;
11574 if ((prefixes
& PREFIX_DATA
))
11577 if (dp
->op
[2].bytemode
== cond_jump_mode
11578 && dp
->op
[0].bytemode
== v_mode
11581 if (sizeflag
& DFLAG
)
11582 all_prefixes
[last_data_prefix
] = DATA32_PREFIX
;
11584 all_prefixes
[last_data_prefix
] = DATA16_PREFIX
;
11585 default_prefixes
|= PREFIX_DATA
;
11587 else if (rex
& REX_W
)
11589 /* REX_W will override PREFIX_DATA. */
11590 default_prefixes
|= PREFIX_DATA
;
11596 FETCH_DATA (info
, codep
+ 1);
11597 modrm
.mod
= (*codep
>> 6) & 3;
11598 modrm
.reg
= (*codep
>> 3) & 7;
11599 modrm
.rm
= *codep
& 7;
11606 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
11609 dofloat (sizeflag
);
11613 dp
= get_valid_dis386 (dp
, info
);
11614 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
11617 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11620 op_ad
= MAX_OPERANDS
- 1 - i
;
11622 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
11627 /* See if any prefixes were not used. If so, print the first one
11628 separately. If we don't do this, we'll wind up printing an
11629 instruction stream which does not precisely correspond to the
11630 bytes we are disassembling. */
11631 if ((prefixes
& ~(used_prefixes
| default_prefixes
)) != 0)
11633 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11634 if (all_prefixes
[i
])
11637 name
= prefix_name (all_prefixes
[i
], priv
.orig_sizeflag
);
11639 name
= INTERNAL_DISASSEMBLER_ERROR
;
11640 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11645 /* Check if the REX prefix is used. */
11646 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0)
11647 all_prefixes
[last_rex_prefix
] = 0;
11649 /* Check if the SEG prefix is used. */
11650 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
11651 | PREFIX_FS
| PREFIX_GS
)) != 0
11653 & seg_prefix (all_prefixes
[last_seg_prefix
])) != 0)
11654 all_prefixes
[last_seg_prefix
] = 0;
11656 /* Check if the ADDR prefix is used. */
11657 if ((prefixes
& PREFIX_ADDR
) != 0
11658 && (used_prefixes
& PREFIX_ADDR
) != 0)
11659 all_prefixes
[last_addr_prefix
] = 0;
11661 /* Check if the DATA prefix is used. */
11662 if ((prefixes
& PREFIX_DATA
) != 0
11663 && (used_prefixes
& PREFIX_DATA
) != 0)
11664 all_prefixes
[last_data_prefix
] = 0;
11667 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11668 if (all_prefixes
[i
])
11671 name
= prefix_name (all_prefixes
[i
], sizeflag
);
11674 prefix_length
+= strlen (name
) + 1;
11675 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
11678 /* Check maximum code length. */
11679 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
11681 (*info
->fprintf_func
) (info
->stream
, "(bad)");
11682 return MAX_CODE_LENGTH
;
11685 obufp
= mnemonicendp
;
11686 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
11689 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
11691 /* The enter and bound instructions are printed with operands in the same
11692 order as the intel book; everything else is printed in reverse order. */
11693 if (intel_syntax
|| two_source_ops
)
11697 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11698 op_txt
[i
] = op_out
[i
];
11700 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
11702 op_ad
= op_index
[i
];
11703 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
11704 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
11705 riprel
= op_riprel
[i
];
11706 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
11707 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
11712 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11713 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
11717 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11721 (*info
->fprintf_func
) (info
->stream
, ",");
11722 if (op_index
[i
] != -1 && !op_riprel
[i
])
11723 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
11725 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
11729 for (i
= 0; i
< MAX_OPERANDS
; i
++)
11730 if (op_index
[i
] != -1 && op_riprel
[i
])
11732 (*info
->fprintf_func
) (info
->stream
, " # ");
11733 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
11734 + op_address
[op_index
[i
]]), info
);
11737 return codep
- priv
.the_buffer
;
11740 static const char *float_mem
[] = {
11815 static const unsigned char float_mem_mode
[] = {
11890 #define ST { OP_ST, 0 }
11891 #define STi { OP_STi, 0 }
11893 #define FGRPd9_2 NULL, { { NULL, 0 } }
11894 #define FGRPd9_4 NULL, { { NULL, 1 } }
11895 #define FGRPd9_5 NULL, { { NULL, 2 } }
11896 #define FGRPd9_6 NULL, { { NULL, 3 } }
11897 #define FGRPd9_7 NULL, { { NULL, 4 } }
11898 #define FGRPda_5 NULL, { { NULL, 5 } }
11899 #define FGRPdb_4 NULL, { { NULL, 6 } }
11900 #define FGRPde_3 NULL, { { NULL, 7 } }
11901 #define FGRPdf_4 NULL, { { NULL, 8 } }
11903 static const struct dis386 float_reg
[][8] = {
11906 { "fadd", { ST
, STi
} },
11907 { "fmul", { ST
, STi
} },
11908 { "fcom", { STi
} },
11909 { "fcomp", { STi
} },
11910 { "fsub", { ST
, STi
} },
11911 { "fsubr", { ST
, STi
} },
11912 { "fdiv", { ST
, STi
} },
11913 { "fdivr", { ST
, STi
} },
11917 { "fld", { STi
} },
11918 { "fxch", { STi
} },
11928 { "fcmovb", { ST
, STi
} },
11929 { "fcmove", { ST
, STi
} },
11930 { "fcmovbe",{ ST
, STi
} },
11931 { "fcmovu", { ST
, STi
} },
11939 { "fcmovnb",{ ST
, STi
} },
11940 { "fcmovne",{ ST
, STi
} },
11941 { "fcmovnbe",{ ST
, STi
} },
11942 { "fcmovnu",{ ST
, STi
} },
11944 { "fucomi", { ST
, STi
} },
11945 { "fcomi", { ST
, STi
} },
11950 { "fadd", { STi
, ST
} },
11951 { "fmul", { STi
, ST
} },
11954 { "fsub!M", { STi
, ST
} },
11955 { "fsubM", { STi
, ST
} },
11956 { "fdiv!M", { STi
, ST
} },
11957 { "fdivM", { STi
, ST
} },
11961 { "ffree", { STi
} },
11963 { "fst", { STi
} },
11964 { "fstp", { STi
} },
11965 { "fucom", { STi
} },
11966 { "fucomp", { STi
} },
11972 { "faddp", { STi
, ST
} },
11973 { "fmulp", { STi
, ST
} },
11976 { "fsub!Mp", { STi
, ST
} },
11977 { "fsubMp", { STi
, ST
} },
11978 { "fdiv!Mp", { STi
, ST
} },
11979 { "fdivMp", { STi
, ST
} },
11983 { "ffreep", { STi
} },
11988 { "fucomip", { ST
, STi
} },
11989 { "fcomip", { ST
, STi
} },
11994 static char *fgrps
[][8] = {
11997 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12002 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12007 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12012 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12017 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12022 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12027 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12028 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12033 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12038 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12043 swap_operand (void)
12045 mnemonicendp
[0] = '.';
12046 mnemonicendp
[1] = 's';
12051 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12052 int sizeflag ATTRIBUTE_UNUSED
)
12054 /* Skip mod/rm byte. */
12060 dofloat (int sizeflag
)
12062 const struct dis386
*dp
;
12063 unsigned char floatop
;
12065 floatop
= codep
[-1];
12067 if (modrm
.mod
!= 3)
12069 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12071 putop (float_mem
[fp_indx
], sizeflag
);
12074 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12077 /* Skip mod/rm byte. */
12081 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12082 if (dp
->name
== NULL
)
12084 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12086 /* Instruction fnstsw is only one with strange arg. */
12087 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12088 strcpy (op_out
[0], names16
[0]);
12092 putop (dp
->name
, sizeflag
);
12097 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12102 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12107 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12109 oappend ("%st" + intel_syntax
);
12113 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12115 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12116 oappend (scratchbuf
+ intel_syntax
);
12119 /* Capital letters in template are macros. */
12121 putop (const char *in_template
, int sizeflag
)
12126 unsigned int l
= 0, len
= 1;
12129 #define SAVE_LAST(c) \
12130 if (l < len && l < sizeof (last)) \
12135 for (p
= in_template
; *p
; p
++)
12152 while (*++p
!= '|')
12153 if (*p
== '}' || *p
== '\0')
12156 /* Fall through. */
12161 while (*++p
!= '}')
12172 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12176 if (l
== 0 && len
== 1)
12181 if (sizeflag
& SUFFIX_ALWAYS
)
12194 if (address_mode
== mode_64bit
12195 && !(prefixes
& PREFIX_ADDR
))
12206 if (intel_syntax
&& !alt
)
12208 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12210 if (sizeflag
& DFLAG
)
12211 *obufp
++ = intel_syntax
? 'd' : 'l';
12213 *obufp
++ = intel_syntax
? 'w' : 's';
12214 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12218 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12221 if (modrm
.mod
== 3)
12227 if (sizeflag
& DFLAG
)
12228 *obufp
++ = intel_syntax
? 'd' : 'l';
12231 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12237 case 'E': /* For jcxz/jecxz */
12238 if (address_mode
== mode_64bit
)
12240 if (sizeflag
& AFLAG
)
12246 if (sizeflag
& AFLAG
)
12248 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12253 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12255 if (sizeflag
& AFLAG
)
12256 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12258 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12259 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12263 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12265 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12269 if (!(rex
& REX_W
))
12270 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12275 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12276 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12278 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12281 if (prefixes
& PREFIX_DS
)
12302 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12307 /* Fall through. */
12310 if (l
!= 0 || len
!= 1)
12318 if (sizeflag
& SUFFIX_ALWAYS
)
12322 if (intel_mnemonic
!= cond
)
12326 if ((prefixes
& PREFIX_FWAIT
) == 0)
12329 used_prefixes
|= PREFIX_FWAIT
;
12335 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12339 if (!(rex
& REX_W
))
12340 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12344 && address_mode
== mode_64bit
12345 && (sizeflag
& DFLAG
))
12350 /* Fall through. */
12354 if ((rex
& REX_W
) == 0
12355 && (prefixes
& PREFIX_DATA
))
12357 if ((sizeflag
& DFLAG
) == 0)
12359 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12363 if ((prefixes
& PREFIX_DATA
)
12365 || (sizeflag
& SUFFIX_ALWAYS
))
12372 if (sizeflag
& DFLAG
)
12376 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12383 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12385 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12389 /* Fall through. */
12392 if (l
== 0 && len
== 1)
12395 if (intel_syntax
&& !alt
)
12398 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12404 if (sizeflag
& DFLAG
)
12405 *obufp
++ = intel_syntax
? 'd' : 'l';
12408 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12414 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12420 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12435 else if (sizeflag
& DFLAG
)
12444 if (intel_syntax
&& !p
[1]
12445 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
12447 if (!(rex
& REX_W
))
12448 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12451 if (l
== 0 && len
== 1)
12455 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12457 if (sizeflag
& SUFFIX_ALWAYS
)
12479 /* Fall through. */
12482 if (l
== 0 && len
== 1)
12487 if (sizeflag
& SUFFIX_ALWAYS
)
12493 if (sizeflag
& DFLAG
)
12497 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12511 if (address_mode
== mode_64bit
12512 && !(prefixes
& PREFIX_ADDR
))
12523 if (l
!= 0 || len
!= 1)
12528 if (need_vex
&& vex
.prefix
)
12530 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
12537 if (prefixes
& PREFIX_DATA
)
12541 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12545 if (l
== 0 && len
== 1)
12547 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12558 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12566 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12568 switch (vex
.length
)
12582 if (l
== 0 && len
== 1)
12584 /* operand size flag for cwtl, cbtw */
12593 else if (sizeflag
& DFLAG
)
12597 if (!(rex
& REX_W
))
12598 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12602 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12609 *obufp
++ = vex
.w
? 'd': 's';
12616 mnemonicendp
= obufp
;
12621 oappend (const char *s
)
12623 obufp
= stpcpy (obufp
, s
);
12629 if (prefixes
& PREFIX_CS
)
12631 used_prefixes
|= PREFIX_CS
;
12632 oappend ("%cs:" + intel_syntax
);
12634 if (prefixes
& PREFIX_DS
)
12636 used_prefixes
|= PREFIX_DS
;
12637 oappend ("%ds:" + intel_syntax
);
12639 if (prefixes
& PREFIX_SS
)
12641 used_prefixes
|= PREFIX_SS
;
12642 oappend ("%ss:" + intel_syntax
);
12644 if (prefixes
& PREFIX_ES
)
12646 used_prefixes
|= PREFIX_ES
;
12647 oappend ("%es:" + intel_syntax
);
12649 if (prefixes
& PREFIX_FS
)
12651 used_prefixes
|= PREFIX_FS
;
12652 oappend ("%fs:" + intel_syntax
);
12654 if (prefixes
& PREFIX_GS
)
12656 used_prefixes
|= PREFIX_GS
;
12657 oappend ("%gs:" + intel_syntax
);
12662 OP_indirE (int bytemode
, int sizeflag
)
12666 OP_E (bytemode
, sizeflag
);
12670 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
12672 if (address_mode
== mode_64bit
)
12680 sprintf_vma (tmp
, disp
);
12681 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
12682 strcpy (buf
+ 2, tmp
+ i
);
12686 bfd_signed_vma v
= disp
;
12693 /* Check for possible overflow on 0x8000000000000000. */
12696 strcpy (buf
, "9223372036854775808");
12710 tmp
[28 - i
] = (v
% 10) + '0';
12714 strcpy (buf
, tmp
+ 29 - i
);
12720 sprintf (buf
, "0x%x", (unsigned int) disp
);
12722 sprintf (buf
, "%d", (int) disp
);
12726 /* Put DISP in BUF as signed hex number. */
12729 print_displacement (char *buf
, bfd_vma disp
)
12731 bfd_signed_vma val
= disp
;
12740 /* Check for possible overflow. */
12743 switch (address_mode
)
12746 strcpy (buf
+ j
, "0x8000000000000000");
12749 strcpy (buf
+ j
, "0x80000000");
12752 strcpy (buf
+ j
, "0x8000");
12762 sprintf_vma (tmp
, (bfd_vma
) val
);
12763 for (i
= 0; tmp
[i
] == '0'; i
++)
12765 if (tmp
[i
] == '\0')
12767 strcpy (buf
+ j
, tmp
+ i
);
12771 intel_operand_size (int bytemode
, int sizeflag
)
12778 oappend ("BYTE PTR ");
12782 oappend ("WORD PTR ");
12785 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12787 oappend ("QWORD PTR ");
12796 oappend ("QWORD PTR ");
12799 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
12800 oappend ("DWORD PTR ");
12802 oappend ("WORD PTR ");
12803 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12807 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12809 oappend ("WORD PTR ");
12810 if (!(rex
& REX_W
))
12811 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12814 if (sizeflag
& DFLAG
)
12815 oappend ("QWORD PTR ");
12817 oappend ("DWORD PTR ");
12818 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12821 case d_scalar_mode
:
12822 case d_scalar_swap_mode
:
12825 oappend ("DWORD PTR ");
12828 case q_scalar_mode
:
12829 case q_scalar_swap_mode
:
12831 oappend ("QWORD PTR ");
12834 if (address_mode
== mode_64bit
)
12835 oappend ("QWORD PTR ");
12837 oappend ("DWORD PTR ");
12840 if (sizeflag
& DFLAG
)
12841 oappend ("FWORD PTR ");
12843 oappend ("DWORD PTR ");
12844 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12847 oappend ("TBYTE PTR ");
12853 switch (vex
.length
)
12856 oappend ("XMMWORD PTR ");
12859 oappend ("YMMWORD PTR ");
12866 oappend ("XMMWORD PTR ");
12869 oappend ("XMMWORD PTR ");
12875 switch (vex
.length
)
12878 oappend ("QWORD PTR ");
12881 oappend ("XMMWORD PTR ");
12891 switch (vex
.length
)
12894 oappend ("QWORD PTR ");
12897 oappend ("YMMWORD PTR ");
12904 oappend ("OWORD PTR ");
12906 case vex_w_dq_mode
:
12907 case vex_scalar_w_dq_mode
:
12912 oappend ("QWORD PTR ");
12914 oappend ("DWORD PTR ");
12922 OP_E_register (int bytemode
, int sizeflag
)
12924 int reg
= modrm
.rm
;
12925 const char **names
;
12931 if ((sizeflag
& SUFFIX_ALWAYS
)
12932 && (bytemode
== b_swap_mode
|| bytemode
== v_swap_mode
))
12955 names
= address_mode
== mode_64bit
? names64
: names32
;
12958 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12976 if ((sizeflag
& DFLAG
)
12977 || (bytemode
!= v_mode
12978 && bytemode
!= v_swap_mode
))
12982 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12988 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12991 oappend (names
[reg
]);
12995 OP_E_memory (int bytemode
, int sizeflag
)
12998 int add
= (rex
& REX_B
) ? 8 : 0;
13003 intel_operand_size (bytemode
, sizeflag
);
13006 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13008 /* 32/64 bit address mode */
13026 vindex
= sib
.index
;
13032 haveindex
= vindex
!= 4;
13035 rbase
= base
+ add
;
13043 if (address_mode
== mode_64bit
&& !havesib
)
13049 FETCH_DATA (the_info
, codep
+ 1);
13051 if ((disp
& 0x80) != 0)
13059 /* In 32bit mode, we need index register to tell [offset] from
13060 [eiz*1 + offset]. */
13061 needindex
= (havesib
13064 && address_mode
== mode_32bit
);
13065 havedisp
= (havebase
13067 || (havesib
&& (haveindex
|| scale
!= 0)));
13070 if (modrm
.mod
!= 0 || base
== 5)
13072 if (havedisp
|| riprel
)
13073 print_displacement (scratchbuf
, disp
);
13075 print_operand_value (scratchbuf
, 1, disp
);
13076 oappend (scratchbuf
);
13080 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
13084 if (havebase
|| haveindex
|| riprel
)
13085 used_prefixes
|= PREFIX_ADDR
;
13087 if (havedisp
|| (intel_syntax
&& riprel
))
13089 *obufp
++ = open_char
;
13090 if (intel_syntax
&& riprel
)
13093 oappend (sizeflag
& AFLAG
? "rip" : "eip");
13097 oappend (address_mode
== mode_64bit
&& (sizeflag
& AFLAG
)
13098 ? names64
[rbase
] : names32
[rbase
]);
13101 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
13102 print index to tell base + index from base. */
13106 || (havebase
&& base
!= ESP_REG_NUM
))
13108 if (!intel_syntax
|| havebase
)
13110 *obufp
++ = separator_char
;
13114 oappend (address_mode
== mode_64bit
13115 && (sizeflag
& AFLAG
)
13116 ? names64
[vindex
] : names32
[vindex
]);
13118 oappend (address_mode
== mode_64bit
13119 && (sizeflag
& AFLAG
)
13120 ? index64
: index32
);
13122 *obufp
++ = scale_char
;
13124 sprintf (scratchbuf
, "%d", 1 << scale
);
13125 oappend (scratchbuf
);
13129 && (disp
|| modrm
.mod
!= 0 || base
== 5))
13131 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
13136 else if (modrm
.mod
!= 1 && disp
!= -disp
)
13140 disp
= - (bfd_signed_vma
) disp
;
13144 print_displacement (scratchbuf
, disp
);
13146 print_operand_value (scratchbuf
, 1, disp
);
13147 oappend (scratchbuf
);
13150 *obufp
++ = close_char
;
13153 else if (intel_syntax
)
13155 if (modrm
.mod
!= 0 || base
== 5)
13157 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13158 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
13162 oappend (names_seg
[ds_reg
- es_reg
]);
13165 print_operand_value (scratchbuf
, 1, disp
);
13166 oappend (scratchbuf
);
13172 /* 16 bit address mode */
13173 used_prefixes
|= prefixes
& PREFIX_ADDR
;
13180 if ((disp
& 0x8000) != 0)
13185 FETCH_DATA (the_info
, codep
+ 1);
13187 if ((disp
& 0x80) != 0)
13192 if ((disp
& 0x8000) != 0)
13198 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
13200 print_displacement (scratchbuf
, disp
);
13201 oappend (scratchbuf
);
13204 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
13206 *obufp
++ = open_char
;
13208 oappend (index16
[modrm
.rm
]);
13210 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
13212 if ((bfd_signed_vma
) disp
>= 0)
13217 else if (modrm
.mod
!= 1)
13221 disp
= - (bfd_signed_vma
) disp
;
13224 print_displacement (scratchbuf
, disp
);
13225 oappend (scratchbuf
);
13228 *obufp
++ = close_char
;
13231 else if (intel_syntax
)
13233 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13234 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
13238 oappend (names_seg
[ds_reg
- es_reg
]);
13241 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
13242 oappend (scratchbuf
);
13248 OP_E (int bytemode
, int sizeflag
)
13250 /* Skip mod/rm byte. */
13254 if (modrm
.mod
== 3)
13255 OP_E_register (bytemode
, sizeflag
);
13257 OP_E_memory (bytemode
, sizeflag
);
13261 OP_G (int bytemode
, int sizeflag
)
13272 oappend (names8rex
[modrm
.reg
+ add
]);
13274 oappend (names8
[modrm
.reg
+ add
]);
13277 oappend (names16
[modrm
.reg
+ add
]);
13280 oappend (names32
[modrm
.reg
+ add
]);
13283 oappend (names64
[modrm
.reg
+ add
]);
13292 oappend (names64
[modrm
.reg
+ add
]);
13295 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
13296 oappend (names32
[modrm
.reg
+ add
]);
13298 oappend (names16
[modrm
.reg
+ add
]);
13299 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13303 if (address_mode
== mode_64bit
)
13304 oappend (names64
[modrm
.reg
+ add
]);
13306 oappend (names32
[modrm
.reg
+ add
]);
13309 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13322 FETCH_DATA (the_info
, codep
+ 8);
13323 a
= *codep
++ & 0xff;
13324 a
|= (*codep
++ & 0xff) << 8;
13325 a
|= (*codep
++ & 0xff) << 16;
13326 a
|= (*codep
++ & 0xff) << 24;
13327 b
= *codep
++ & 0xff;
13328 b
|= (*codep
++ & 0xff) << 8;
13329 b
|= (*codep
++ & 0xff) << 16;
13330 b
|= (*codep
++ & 0xff) << 24;
13331 x
= a
+ ((bfd_vma
) b
<< 32);
13339 static bfd_signed_vma
13342 bfd_signed_vma x
= 0;
13344 FETCH_DATA (the_info
, codep
+ 4);
13345 x
= *codep
++ & (bfd_signed_vma
) 0xff;
13346 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
13347 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
13348 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
13352 static bfd_signed_vma
13355 bfd_signed_vma x
= 0;
13357 FETCH_DATA (the_info
, codep
+ 4);
13358 x
= *codep
++ & (bfd_signed_vma
) 0xff;
13359 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
13360 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
13361 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
13363 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
13373 FETCH_DATA (the_info
, codep
+ 2);
13374 x
= *codep
++ & 0xff;
13375 x
|= (*codep
++ & 0xff) << 8;
13380 set_op (bfd_vma op
, int riprel
)
13382 op_index
[op_ad
] = op_ad
;
13383 if (address_mode
== mode_64bit
)
13385 op_address
[op_ad
] = op
;
13386 op_riprel
[op_ad
] = riprel
;
13390 /* Mask to get a 32-bit address. */
13391 op_address
[op_ad
] = op
& 0xffffffff;
13392 op_riprel
[op_ad
] = riprel
& 0xffffffff;
13397 OP_REG (int code
, int sizeflag
)
13409 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
13410 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
13411 s
= names16
[code
- ax_reg
+ add
];
13413 case es_reg
: case ss_reg
: case cs_reg
:
13414 case ds_reg
: case fs_reg
: case gs_reg
:
13415 s
= names_seg
[code
- es_reg
+ add
];
13417 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
13418 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
13421 s
= names8rex
[code
- al_reg
+ add
];
13423 s
= names8
[code
- al_reg
];
13425 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
13426 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
13427 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
13429 s
= names64
[code
- rAX_reg
+ add
];
13432 code
+= eAX_reg
- rAX_reg
;
13433 /* Fall through. */
13434 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
13435 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
13438 s
= names64
[code
- eAX_reg
+ add
];
13441 if (sizeflag
& DFLAG
)
13442 s
= names32
[code
- eAX_reg
+ add
];
13444 s
= names16
[code
- eAX_reg
+ add
];
13445 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13449 s
= INTERNAL_DISASSEMBLER_ERROR
;
13456 OP_IMREG (int code
, int sizeflag
)
13468 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
13469 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
13470 s
= names16
[code
- ax_reg
];
13472 case es_reg
: case ss_reg
: case cs_reg
:
13473 case ds_reg
: case fs_reg
: case gs_reg
:
13474 s
= names_seg
[code
- es_reg
];
13476 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
13477 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
13480 s
= names8rex
[code
- al_reg
];
13482 s
= names8
[code
- al_reg
];
13484 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
13485 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
13488 s
= names64
[code
- eAX_reg
];
13491 if (sizeflag
& DFLAG
)
13492 s
= names32
[code
- eAX_reg
];
13494 s
= names16
[code
- eAX_reg
];
13495 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13498 case z_mode_ax_reg
:
13499 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13503 if (!(rex
& REX_W
))
13504 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13507 s
= INTERNAL_DISASSEMBLER_ERROR
;
13514 OP_I (int bytemode
, int sizeflag
)
13517 bfd_signed_vma mask
= -1;
13522 FETCH_DATA (the_info
, codep
+ 1);
13527 if (address_mode
== mode_64bit
)
13532 /* Fall through. */
13539 if (sizeflag
& DFLAG
)
13549 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13561 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13566 scratchbuf
[0] = '$';
13567 print_operand_value (scratchbuf
+ 1, 1, op
);
13568 oappend (scratchbuf
+ intel_syntax
);
13569 scratchbuf
[0] = '\0';
13573 OP_I64 (int bytemode
, int sizeflag
)
13576 bfd_signed_vma mask
= -1;
13578 if (address_mode
!= mode_64bit
)
13580 OP_I (bytemode
, sizeflag
);
13587 FETCH_DATA (the_info
, codep
+ 1);
13597 if (sizeflag
& DFLAG
)
13607 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13615 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13620 scratchbuf
[0] = '$';
13621 print_operand_value (scratchbuf
+ 1, 1, op
);
13622 oappend (scratchbuf
+ intel_syntax
);
13623 scratchbuf
[0] = '\0';
13627 OP_sI (int bytemode
, int sizeflag
)
13634 FETCH_DATA (the_info
, codep
+ 1);
13636 if ((op
& 0x80) != 0)
13640 if (sizeflag
& DFLAG
)
13646 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13650 scratchbuf
[0] = '$';
13651 print_operand_value (scratchbuf
+ 1, 1, op
);
13652 oappend (scratchbuf
+ intel_syntax
);
13656 OP_J (int bytemode
, int sizeflag
)
13660 bfd_vma segment
= 0;
13665 FETCH_DATA (the_info
, codep
+ 1);
13667 if ((disp
& 0x80) != 0)
13672 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
13677 if ((disp
& 0x8000) != 0)
13679 /* In 16bit mode, address is wrapped around at 64k within
13680 the same segment. Otherwise, a data16 prefix on a jump
13681 instruction means that the pc is masked to 16 bits after
13682 the displacement is added! */
13684 if ((prefixes
& PREFIX_DATA
) == 0)
13685 segment
= ((start_pc
+ codep
- start_codep
)
13686 & ~((bfd_vma
) 0xffff));
13688 if (!(rex
& REX_W
))
13689 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13692 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13695 disp
= ((start_pc
+ codep
- start_codep
+ disp
) & mask
) | segment
;
13697 print_operand_value (scratchbuf
, 1, disp
);
13698 oappend (scratchbuf
);
13702 OP_SEG (int bytemode
, int sizeflag
)
13704 if (bytemode
== w_mode
)
13705 oappend (names_seg
[modrm
.reg
]);
13707 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
13711 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
13715 if (sizeflag
& DFLAG
)
13725 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13727 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
13729 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
13730 oappend (scratchbuf
);
13734 OP_OFF (int bytemode
, int sizeflag
)
13738 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
13739 intel_operand_size (bytemode
, sizeflag
);
13742 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13749 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13750 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
13752 oappend (names_seg
[ds_reg
- es_reg
]);
13756 print_operand_value (scratchbuf
, 1, off
);
13757 oappend (scratchbuf
);
13761 OP_OFF64 (int bytemode
, int sizeflag
)
13765 if (address_mode
!= mode_64bit
13766 || (prefixes
& PREFIX_ADDR
))
13768 OP_OFF (bytemode
, sizeflag
);
13772 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
13773 intel_operand_size (bytemode
, sizeflag
);
13780 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13781 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
13783 oappend (names_seg
[ds_reg
- es_reg
]);
13787 print_operand_value (scratchbuf
, 1, off
);
13788 oappend (scratchbuf
);
13792 ptr_reg (int code
, int sizeflag
)
13796 *obufp
++ = open_char
;
13797 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13798 if (address_mode
== mode_64bit
)
13800 if (!(sizeflag
& AFLAG
))
13801 s
= names32
[code
- eAX_reg
];
13803 s
= names64
[code
- eAX_reg
];
13805 else if (sizeflag
& AFLAG
)
13806 s
= names32
[code
- eAX_reg
];
13808 s
= names16
[code
- eAX_reg
];
13810 *obufp
++ = close_char
;
13815 OP_ESreg (int code
, int sizeflag
)
13821 case 0x6d: /* insw/insl */
13822 intel_operand_size (z_mode
, sizeflag
);
13824 case 0xa5: /* movsw/movsl/movsq */
13825 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13826 case 0xab: /* stosw/stosl */
13827 case 0xaf: /* scasw/scasl */
13828 intel_operand_size (v_mode
, sizeflag
);
13831 intel_operand_size (b_mode
, sizeflag
);
13834 oappend ("%es:" + intel_syntax
);
13835 ptr_reg (code
, sizeflag
);
13839 OP_DSreg (int code
, int sizeflag
)
13845 case 0x6f: /* outsw/outsl */
13846 intel_operand_size (z_mode
, sizeflag
);
13848 case 0xa5: /* movsw/movsl/movsq */
13849 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13850 case 0xad: /* lodsw/lodsl/lodsq */
13851 intel_operand_size (v_mode
, sizeflag
);
13854 intel_operand_size (b_mode
, sizeflag
);
13863 | PREFIX_GS
)) == 0)
13864 prefixes
|= PREFIX_DS
;
13866 ptr_reg (code
, sizeflag
);
13870 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13878 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
13880 all_prefixes
[last_lock_prefix
] = 0;
13881 used_prefixes
|= PREFIX_LOCK
;
13886 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
13887 oappend (scratchbuf
+ intel_syntax
);
13891 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13900 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
13902 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
13903 oappend (scratchbuf
);
13907 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13909 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
13910 oappend (scratchbuf
+ intel_syntax
);
13914 OP_R (int bytemode
, int sizeflag
)
13916 if (modrm
.mod
== 3)
13917 OP_E (bytemode
, sizeflag
);
13923 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13925 int reg
= modrm
.reg
;
13926 const char **names
;
13928 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13929 if (prefixes
& PREFIX_DATA
)
13938 oappend (names
[reg
]);
13942 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13944 int reg
= modrm
.reg
;
13945 const char **names
;
13951 && bytemode
!= xmm_mode
13952 && bytemode
!= scalar_mode
)
13954 switch (vex
.length
)
13968 oappend (names
[reg
]);
13972 OP_EM (int bytemode
, int sizeflag
)
13975 const char **names
;
13977 if (modrm
.mod
!= 3)
13980 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
13982 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
13983 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13985 OP_E (bytemode
, sizeflag
);
13989 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
13992 /* Skip mod/rm byte. */
13995 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13997 if (prefixes
& PREFIX_DATA
)
14006 oappend (names
[reg
]);
14009 /* cvt* are the only instructions in sse2 which have
14010 both SSE and MMX operands and also have 0x66 prefix
14011 in their opcode. 0x66 was originally used to differentiate
14012 between SSE and MMX instruction(operands). So we have to handle the
14013 cvt* separately using OP_EMC and OP_MXC */
14015 OP_EMC (int bytemode
, int sizeflag
)
14017 if (modrm
.mod
!= 3)
14019 if (intel_syntax
&& bytemode
== v_mode
)
14021 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
14022 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14024 OP_E (bytemode
, sizeflag
);
14028 /* Skip mod/rm byte. */
14031 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14032 oappend (names_mm
[modrm
.rm
]);
14036 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14038 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14039 oappend (names_mm
[modrm
.reg
]);
14043 OP_EX (int bytemode
, int sizeflag
)
14046 const char **names
;
14048 /* Skip mod/rm byte. */
14052 if (modrm
.mod
!= 3)
14054 OP_E_memory (bytemode
, sizeflag
);
14063 if ((sizeflag
& SUFFIX_ALWAYS
)
14064 && (bytemode
== x_swap_mode
14065 || bytemode
== d_swap_mode
14066 || bytemode
== d_scalar_swap_mode
14067 || bytemode
== q_swap_mode
14068 || bytemode
== q_scalar_swap_mode
))
14072 && bytemode
!= xmm_mode
14073 && bytemode
!= xmmq_mode
14074 && bytemode
!= d_scalar_mode
14075 && bytemode
!= d_scalar_swap_mode
14076 && bytemode
!= q_scalar_mode
14077 && bytemode
!= q_scalar_swap_mode
14078 && bytemode
!= vex_scalar_w_dq_mode
)
14080 switch (vex
.length
)
14094 oappend (names
[reg
]);
14098 OP_MS (int bytemode
, int sizeflag
)
14100 if (modrm
.mod
== 3)
14101 OP_EM (bytemode
, sizeflag
);
14107 OP_XS (int bytemode
, int sizeflag
)
14109 if (modrm
.mod
== 3)
14110 OP_EX (bytemode
, sizeflag
);
14116 OP_M (int bytemode
, int sizeflag
)
14118 if (modrm
.mod
== 3)
14119 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14122 OP_E (bytemode
, sizeflag
);
14126 OP_0f07 (int bytemode
, int sizeflag
)
14128 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
14131 OP_E (bytemode
, sizeflag
);
14134 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14135 32bit mode and "xchg %rax,%rax" in 64bit mode. */
14138 NOP_Fixup1 (int bytemode
, int sizeflag
)
14140 if ((prefixes
& PREFIX_DATA
) != 0
14143 && address_mode
== mode_64bit
))
14144 OP_REG (bytemode
, sizeflag
);
14146 strcpy (obuf
, "nop");
14150 NOP_Fixup2 (int bytemode
, int sizeflag
)
14152 if ((prefixes
& PREFIX_DATA
) != 0
14155 && address_mode
== mode_64bit
))
14156 OP_IMREG (bytemode
, sizeflag
);
14159 static const char *const Suffix3DNow
[] = {
14160 /* 00 */ NULL
, NULL
, NULL
, NULL
,
14161 /* 04 */ NULL
, NULL
, NULL
, NULL
,
14162 /* 08 */ NULL
, NULL
, NULL
, NULL
,
14163 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
14164 /* 10 */ NULL
, NULL
, NULL
, NULL
,
14165 /* 14 */ NULL
, NULL
, NULL
, NULL
,
14166 /* 18 */ NULL
, NULL
, NULL
, NULL
,
14167 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
14168 /* 20 */ NULL
, NULL
, NULL
, NULL
,
14169 /* 24 */ NULL
, NULL
, NULL
, NULL
,
14170 /* 28 */ NULL
, NULL
, NULL
, NULL
,
14171 /* 2C */ NULL
, NULL
, NULL
, NULL
,
14172 /* 30 */ NULL
, NULL
, NULL
, NULL
,
14173 /* 34 */ NULL
, NULL
, NULL
, NULL
,
14174 /* 38 */ NULL
, NULL
, NULL
, NULL
,
14175 /* 3C */ NULL
, NULL
, NULL
, NULL
,
14176 /* 40 */ NULL
, NULL
, NULL
, NULL
,
14177 /* 44 */ NULL
, NULL
, NULL
, NULL
,
14178 /* 48 */ NULL
, NULL
, NULL
, NULL
,
14179 /* 4C */ NULL
, NULL
, NULL
, NULL
,
14180 /* 50 */ NULL
, NULL
, NULL
, NULL
,
14181 /* 54 */ NULL
, NULL
, NULL
, NULL
,
14182 /* 58 */ NULL
, NULL
, NULL
, NULL
,
14183 /* 5C */ NULL
, NULL
, NULL
, NULL
,
14184 /* 60 */ NULL
, NULL
, NULL
, NULL
,
14185 /* 64 */ NULL
, NULL
, NULL
, NULL
,
14186 /* 68 */ NULL
, NULL
, NULL
, NULL
,
14187 /* 6C */ NULL
, NULL
, NULL
, NULL
,
14188 /* 70 */ NULL
, NULL
, NULL
, NULL
,
14189 /* 74 */ NULL
, NULL
, NULL
, NULL
,
14190 /* 78 */ NULL
, NULL
, NULL
, NULL
,
14191 /* 7C */ NULL
, NULL
, NULL
, NULL
,
14192 /* 80 */ NULL
, NULL
, NULL
, NULL
,
14193 /* 84 */ NULL
, NULL
, NULL
, NULL
,
14194 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
14195 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
14196 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
14197 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
14198 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
14199 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
14200 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
14201 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
14202 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
14203 /* AC */ NULL
, NULL
, "pfacc", NULL
,
14204 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
14205 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
14206 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
14207 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
14208 /* C0 */ NULL
, NULL
, NULL
, NULL
,
14209 /* C4 */ NULL
, NULL
, NULL
, NULL
,
14210 /* C8 */ NULL
, NULL
, NULL
, NULL
,
14211 /* CC */ NULL
, NULL
, NULL
, NULL
,
14212 /* D0 */ NULL
, NULL
, NULL
, NULL
,
14213 /* D4 */ NULL
, NULL
, NULL
, NULL
,
14214 /* D8 */ NULL
, NULL
, NULL
, NULL
,
14215 /* DC */ NULL
, NULL
, NULL
, NULL
,
14216 /* E0 */ NULL
, NULL
, NULL
, NULL
,
14217 /* E4 */ NULL
, NULL
, NULL
, NULL
,
14218 /* E8 */ NULL
, NULL
, NULL
, NULL
,
14219 /* EC */ NULL
, NULL
, NULL
, NULL
,
14220 /* F0 */ NULL
, NULL
, NULL
, NULL
,
14221 /* F4 */ NULL
, NULL
, NULL
, NULL
,
14222 /* F8 */ NULL
, NULL
, NULL
, NULL
,
14223 /* FC */ NULL
, NULL
, NULL
, NULL
,
14227 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14229 const char *mnemonic
;
14231 FETCH_DATA (the_info
, codep
+ 1);
14232 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14233 place where an 8-bit immediate would normally go. ie. the last
14234 byte of the instruction. */
14235 obufp
= mnemonicendp
;
14236 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
14238 oappend (mnemonic
);
14241 /* Since a variable sized modrm/sib chunk is between the start
14242 of the opcode (0x0f0f) and the opcode suffix, we need to do
14243 all the modrm processing first, and don't know until now that
14244 we have a bad opcode. This necessitates some cleaning up. */
14245 op_out
[0][0] = '\0';
14246 op_out
[1][0] = '\0';
14249 mnemonicendp
= obufp
;
14252 static struct op simd_cmp_op
[] =
14254 { STRING_COMMA_LEN ("eq") },
14255 { STRING_COMMA_LEN ("lt") },
14256 { STRING_COMMA_LEN ("le") },
14257 { STRING_COMMA_LEN ("unord") },
14258 { STRING_COMMA_LEN ("neq") },
14259 { STRING_COMMA_LEN ("nlt") },
14260 { STRING_COMMA_LEN ("nle") },
14261 { STRING_COMMA_LEN ("ord") }
14265 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14267 unsigned int cmp_type
;
14269 FETCH_DATA (the_info
, codep
+ 1);
14270 cmp_type
= *codep
++ & 0xff;
14271 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
14274 char *p
= mnemonicendp
- 2;
14278 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
14279 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
14283 /* We have a reserved extension byte. Output it directly. */
14284 scratchbuf
[0] = '$';
14285 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
14286 oappend (scratchbuf
+ intel_syntax
);
14287 scratchbuf
[0] = '\0';
14292 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
14293 int sizeflag ATTRIBUTE_UNUSED
)
14295 /* mwait %eax,%ecx */
14298 const char **names
= (address_mode
== mode_64bit
14299 ? names64
: names32
);
14300 strcpy (op_out
[0], names
[0]);
14301 strcpy (op_out
[1], names
[1]);
14302 two_source_ops
= 1;
14304 /* Skip mod/rm byte. */
14310 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
14311 int sizeflag ATTRIBUTE_UNUSED
)
14313 /* monitor %eax,%ecx,%edx" */
14316 const char **op1_names
;
14317 const char **names
= (address_mode
== mode_64bit
14318 ? names64
: names32
);
14320 if (!(prefixes
& PREFIX_ADDR
))
14321 op1_names
= (address_mode
== mode_16bit
14322 ? names16
: names
);
14325 /* Remove "addr16/addr32". */
14326 all_prefixes
[last_addr_prefix
] = 0;
14327 op1_names
= (address_mode
!= mode_32bit
14328 ? names32
: names16
);
14329 used_prefixes
|= PREFIX_ADDR
;
14331 strcpy (op_out
[0], op1_names
[0]);
14332 strcpy (op_out
[1], names
[1]);
14333 strcpy (op_out
[2], names
[2]);
14334 two_source_ops
= 1;
14336 /* Skip mod/rm byte. */
14344 /* Throw away prefixes and 1st. opcode byte. */
14345 codep
= insn_codep
+ 1;
14350 REP_Fixup (int bytemode
, int sizeflag
)
14352 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14354 if (prefixes
& PREFIX_REPZ
)
14355 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
14362 OP_IMREG (bytemode
, sizeflag
);
14365 OP_ESreg (bytemode
, sizeflag
);
14368 OP_DSreg (bytemode
, sizeflag
);
14377 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
14382 /* Change cmpxchg8b to cmpxchg16b. */
14383 char *p
= mnemonicendp
- 2;
14384 mnemonicendp
= stpcpy (p
, "16b");
14387 OP_M (bytemode
, sizeflag
);
14391 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
14393 const char **names
;
14397 switch (vex
.length
)
14411 oappend (names
[reg
]);
14415 CRC32_Fixup (int bytemode
, int sizeflag
)
14417 /* Add proper suffix to "crc32". */
14418 char *p
= mnemonicendp
;
14437 if (sizeflag
& DFLAG
)
14441 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14445 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14452 if (modrm
.mod
== 3)
14456 /* Skip mod/rm byte. */
14461 add
= (rex
& REX_B
) ? 8 : 0;
14462 if (bytemode
== b_mode
)
14466 oappend (names8rex
[modrm
.rm
+ add
]);
14468 oappend (names8
[modrm
.rm
+ add
]);
14474 oappend (names64
[modrm
.rm
+ add
]);
14475 else if ((prefixes
& PREFIX_DATA
))
14476 oappend (names16
[modrm
.rm
+ add
]);
14478 oappend (names32
[modrm
.rm
+ add
]);
14482 OP_E (bytemode
, sizeflag
);
14486 FXSAVE_Fixup (int bytemode
, int sizeflag
)
14488 /* Add proper suffix to "fxsave" and "fxrstor". */
14492 char *p
= mnemonicendp
;
14498 OP_M (bytemode
, sizeflag
);
14501 /* Display the destination register operand for instructions with
14505 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14508 const char **names
;
14516 reg
= vex
.register_specifier
;
14517 if (bytemode
== vex_scalar_mode
)
14519 oappend (names_xmm
[reg
]);
14523 switch (vex
.length
)
14555 oappend (names
[reg
]);
14558 /* Get the VEX immediate byte without moving codep. */
14560 static unsigned char
14561 get_vex_imm8 (int sizeflag
, int opnum
)
14563 int bytes_before_imm
= 0;
14565 if (modrm
.mod
!= 3)
14567 /* There are SIB/displacement bytes. */
14568 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14570 /* 32/64 bit address mode */
14571 int base
= modrm
.rm
;
14573 /* Check SIB byte. */
14576 FETCH_DATA (the_info
, codep
+ 1);
14578 /* When decoding the third source, don't increase
14579 bytes_before_imm as this has already been incremented
14580 by one in OP_E_memory while decoding the second
14583 bytes_before_imm
++;
14586 /* Don't increase bytes_before_imm when decoding the third source,
14587 it has already been incremented by OP_E_memory while decoding
14588 the second source operand. */
14594 /* When modrm.rm == 5 or modrm.rm == 4 and base in
14595 SIB == 5, there is a 4 byte displacement. */
14597 /* No displacement. */
14600 /* 4 byte displacement. */
14601 bytes_before_imm
+= 4;
14604 /* 1 byte displacement. */
14605 bytes_before_imm
++;
14612 /* 16 bit address mode */
14613 /* Don't increase bytes_before_imm when decoding the third source,
14614 it has already been incremented by OP_E_memory while decoding
14615 the second source operand. */
14621 /* When modrm.rm == 6, there is a 2 byte displacement. */
14623 /* No displacement. */
14626 /* 2 byte displacement. */
14627 bytes_before_imm
+= 2;
14630 /* 1 byte displacement: when decoding the third source,
14631 don't increase bytes_before_imm as this has already
14632 been incremented by one in OP_E_memory while decoding
14633 the second source operand. */
14635 bytes_before_imm
++;
14643 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
14644 return codep
[bytes_before_imm
];
14648 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
14650 const char **names
;
14652 if (reg
== -1 && modrm
.mod
!= 3)
14654 OP_E_memory (bytemode
, sizeflag
);
14666 else if (reg
> 7 && address_mode
!= mode_64bit
)
14670 switch (vex
.length
)
14681 oappend (names
[reg
]);
14685 OP_EX_VexImmW (int bytemode
, int sizeflag
)
14688 static unsigned char vex_imm8
;
14690 if (vex_w_done
== 0)
14694 /* Skip mod/rm byte. */
14698 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
14701 reg
= vex_imm8
>> 4;
14703 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14705 else if (vex_w_done
== 1)
14710 reg
= vex_imm8
>> 4;
14712 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14716 /* Output the imm8 directly. */
14717 scratchbuf
[0] = '$';
14718 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
14719 oappend (scratchbuf
+ intel_syntax
);
14720 scratchbuf
[0] = '\0';
14726 OP_Vex_2src (int bytemode
, int sizeflag
)
14728 if (modrm
.mod
== 3)
14730 int reg
= modrm
.rm
;
14734 oappend (names_xmm
[reg
]);
14739 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
14741 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
14742 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14744 OP_E (bytemode
, sizeflag
);
14749 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
14751 if (modrm
.mod
== 3)
14753 /* Skip mod/rm byte. */
14759 oappend (names_xmm
[vex
.register_specifier
]);
14761 OP_Vex_2src (bytemode
, sizeflag
);
14765 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
14768 OP_Vex_2src (bytemode
, sizeflag
);
14770 oappend (names_xmm
[vex
.register_specifier
]);
14774 OP_EX_VexW (int bytemode
, int sizeflag
)
14782 /* Skip mod/rm byte. */
14787 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
14792 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
14795 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14799 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
14800 int sizeflag ATTRIBUTE_UNUSED
)
14802 /* Skip the immediate byte and check for invalid bits. */
14803 FETCH_DATA (the_info
, codep
+ 1);
14804 if (*codep
++ & 0xf)
14809 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14812 const char **names
;
14814 FETCH_DATA (the_info
, codep
+ 1);
14817 if (bytemode
!= x_mode
)
14824 if (reg
> 7 && address_mode
!= mode_64bit
)
14827 switch (vex
.length
)
14838 oappend (names
[reg
]);
14842 OP_XMM_VexW (int bytemode
, int sizeflag
)
14844 /* Turn off the REX.W bit since it is used for swapping operands
14847 OP_XMM (bytemode
, sizeflag
);
14851 OP_EX_Vex (int bytemode
, int sizeflag
)
14853 if (modrm
.mod
!= 3)
14855 if (vex
.register_specifier
!= 0)
14859 OP_EX (bytemode
, sizeflag
);
14863 OP_XMM_Vex (int bytemode
, int sizeflag
)
14865 if (modrm
.mod
!= 3)
14867 if (vex
.register_specifier
!= 0)
14871 OP_XMM (bytemode
, sizeflag
);
14875 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14877 switch (vex
.length
)
14880 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
14883 mnemonicendp
= stpcpy (obuf
, "vzeroall");
14890 static struct op vex_cmp_op
[] =
14892 { STRING_COMMA_LEN ("eq") },
14893 { STRING_COMMA_LEN ("lt") },
14894 { STRING_COMMA_LEN ("le") },
14895 { STRING_COMMA_LEN ("unord") },
14896 { STRING_COMMA_LEN ("neq") },
14897 { STRING_COMMA_LEN ("nlt") },
14898 { STRING_COMMA_LEN ("nle") },
14899 { STRING_COMMA_LEN ("ord") },
14900 { STRING_COMMA_LEN ("eq_uq") },
14901 { STRING_COMMA_LEN ("nge") },
14902 { STRING_COMMA_LEN ("ngt") },
14903 { STRING_COMMA_LEN ("false") },
14904 { STRING_COMMA_LEN ("neq_oq") },
14905 { STRING_COMMA_LEN ("ge") },
14906 { STRING_COMMA_LEN ("gt") },
14907 { STRING_COMMA_LEN ("true") },
14908 { STRING_COMMA_LEN ("eq_os") },
14909 { STRING_COMMA_LEN ("lt_oq") },
14910 { STRING_COMMA_LEN ("le_oq") },
14911 { STRING_COMMA_LEN ("unord_s") },
14912 { STRING_COMMA_LEN ("neq_us") },
14913 { STRING_COMMA_LEN ("nlt_uq") },
14914 { STRING_COMMA_LEN ("nle_uq") },
14915 { STRING_COMMA_LEN ("ord_s") },
14916 { STRING_COMMA_LEN ("eq_us") },
14917 { STRING_COMMA_LEN ("nge_uq") },
14918 { STRING_COMMA_LEN ("ngt_uq") },
14919 { STRING_COMMA_LEN ("false_os") },
14920 { STRING_COMMA_LEN ("neq_os") },
14921 { STRING_COMMA_LEN ("ge_oq") },
14922 { STRING_COMMA_LEN ("gt_oq") },
14923 { STRING_COMMA_LEN ("true_us") },
14927 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14929 unsigned int cmp_type
;
14931 FETCH_DATA (the_info
, codep
+ 1);
14932 cmp_type
= *codep
++ & 0xff;
14933 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
14936 char *p
= mnemonicendp
- 2;
14940 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
14941 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
14945 /* We have a reserved extension byte. Output it directly. */
14946 scratchbuf
[0] = '$';
14947 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
14948 oappend (scratchbuf
+ intel_syntax
);
14949 scratchbuf
[0] = '\0';
14953 static const struct op pclmul_op
[] =
14955 { STRING_COMMA_LEN ("lql") },
14956 { STRING_COMMA_LEN ("hql") },
14957 { STRING_COMMA_LEN ("lqh") },
14958 { STRING_COMMA_LEN ("hqh") }
14962 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
14963 int sizeflag ATTRIBUTE_UNUSED
)
14965 unsigned int pclmul_type
;
14967 FETCH_DATA (the_info
, codep
+ 1);
14968 pclmul_type
= *codep
++ & 0xff;
14969 switch (pclmul_type
)
14980 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
14983 char *p
= mnemonicendp
- 3;
14988 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
14989 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
14993 /* We have a reserved extension byte. Output it directly. */
14994 scratchbuf
[0] = '$';
14995 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
14996 oappend (scratchbuf
+ intel_syntax
);
14997 scratchbuf
[0] = '\0';
15002 MOVBE_Fixup (int bytemode
, int sizeflag
)
15004 /* Add proper suffix to "movbe". */
15005 char *p
= mnemonicendp
;
15014 if (sizeflag
& SUFFIX_ALWAYS
)
15020 if (sizeflag
& DFLAG
)
15024 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15029 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15036 OP_M (bytemode
, sizeflag
);
15040 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15043 const char **names
;
15045 /* Skip mod/rm byte. */
15059 oappend (names
[reg
]);
15063 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15065 const char **names
;
15072 oappend (names
[vex
.register_specifier
]);