1 /* opcode/i386.h -- Intel 80386 opcode table
2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
21 ix86 Unix assemblers, generate floating point instructions with
22 reversed source and destination registers in certain cases.
23 Unfortunately, gcc and possibly many other programs use this
24 reversed syntax, so we're stuck with it.
26 eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
27 `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
28 the expected st(3) = st(3) - st
30 This happens with all the non-commutative arithmetic floating point
31 operations with two register operands, where the source register is
32 %st, and destination register is %st(i). See FloatDR below.
34 The affected opcode map is dceX, dcfX, deeX, defX. */
36 #ifndef SYSV386_COMPAT
37 /* Set non-zero for broken, compatible instructions. Set to zero for
38 non-broken opcodes at your peril. gcc generates SystemV/386
39 compatible instructions. */
40 #define SYSV386_COMPAT 1
43 /* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
44 generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
46 #define OLDGCC_COMPAT SYSV386_COMPAT
49 static const template i386_optab
[] = {
52 #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
53 #define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
54 #define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
55 #define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_dSuf|No_xSuf)
56 #define d_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf)
57 #define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_dSuf)
58 #define bw_Suf (No_lSuf|No_sSuf|No_dSuf|No_xSuf)
59 #define bl_Suf (No_wSuf|No_sSuf|No_dSuf|No_xSuf)
60 #define wl_Suf (No_bSuf|No_sSuf|No_dSuf|No_xSuf)
61 #define sl_Suf (No_bSuf|No_wSuf|No_dSuf|No_xSuf)
62 #define sld_Suf (No_bSuf|No_wSuf|No_xSuf)
63 #define sldx_Suf (No_bSuf|No_wSuf)
64 #define bwl_Suf (No_sSuf|No_dSuf|No_xSuf)
65 #define bwld_Suf (No_sSuf|No_xSuf)
66 #define FP (NoSuf|IgnoreSize)
67 #define l_FP (l_Suf|IgnoreSize)
68 #define d_FP (d_Suf|IgnoreSize)
69 #define x_FP (x_Suf|IgnoreSize)
70 #define sl_FP (sl_Suf|IgnoreSize)
71 #define sld_FP (sld_Suf|IgnoreSize)
72 #define sldx_FP (sldx_Suf|IgnoreSize)
74 /* Someone forgot that the FloatR bit reverses the operation when not
75 equal to the FloatD bit. ie. Changing only FloatD results in the
76 destination being swapped *and* the direction being reversed. */
77 #define FloatDR FloatD
79 #define FloatDR (FloatD|FloatR)
82 /* Move instructions. */
83 #define MOV_AX_DISP32 0xa0
84 { "mov", 2, 0xa0, X
, bwl_Suf
|D
|W
, { Disp16
|Disp32
, Acc
, 0 } },
85 { "mov", 2, 0x88, X
, bwl_Suf
|D
|W
|Modrm
, { Reg
, Reg
|AnyMem
, 0 } },
86 { "mov", 2, 0xb0, X
, bwl_Suf
|W
|ShortForm
, { Imm
, Reg
, 0 } },
87 { "mov", 2, 0xc6, X
, bwl_Suf
|W
|Modrm
, { Imm
, Reg
|AnyMem
, 0 } },
88 /* The next two instructions accept WordReg so that a segment register
89 can be copied to a 32 bit register, and vice versa, without using a
90 size prefix. When moving to a 32 bit register, the upper 16 bits
91 are set to an implementation defined value (on the Pentium Pro,
92 the implementation defined value is zero). */
93 { "mov", 2, 0x8c, X
, wl_Suf
|Modrm
, { SReg3
|SReg2
, WordReg
|WordMem
, 0 } },
94 { "mov", 2, 0x8e, X
, wl_Suf
|Modrm
|IgnoreSize
, { WordReg
|WordMem
, SReg3
|SReg2
, 0 } },
95 /* Move to/from control debug registers. */
96 { "mov", 2, 0x0f20, X
, l_Suf
|D
|Modrm
|IgnoreSize
, { Control
, Reg32
|InvMem
, 0} },
97 { "mov", 2, 0x0f21, X
, l_Suf
|D
|Modrm
|IgnoreSize
, { Debug
, Reg32
|InvMem
, 0} },
98 { "mov", 2, 0x0f24, X
, l_Suf
|D
|Modrm
|IgnoreSize
, { Test
, Reg32
|InvMem
, 0} },
100 /* Move with sign extend. */
101 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
102 conflict with the "movs" string move instruction. */
103 {"movsbl", 2, 0x0fbe, X
, NoSuf
|Modrm
, { Reg8
|ByteMem
, Reg32
, 0} },
104 {"movsbw", 2, 0x0fbe, X
, NoSuf
|Modrm
, { Reg8
|ByteMem
, Reg16
, 0} },
105 {"movswl", 2, 0x0fbf, X
, NoSuf
|Modrm
, { Reg16
|ShortMem
, Reg32
, 0} },
107 {"movsx", 2, 0x0fbf, X
, w_Suf
|Modrm
|IgnoreSize
, { Reg16
|ShortMem
, Reg32
, 0} },
108 {"movsx", 2, 0x0fbe, X
, b_Suf
|Modrm
, { Reg8
|ByteMem
, WordReg
, 0} },
110 /* Move with zero extend. */
111 {"movzb", 2, 0x0fb6, X
, wl_Suf
|Modrm
, { Reg8
|ByteMem
, WordReg
, 0} },
112 {"movzwl", 2, 0x0fb7, X
, NoSuf
|Modrm
, { Reg16
|ShortMem
, Reg32
, 0} },
114 {"movzx", 2, 0x0fb7, X
, w_Suf
|Modrm
|IgnoreSize
, { Reg16
|ShortMem
, Reg32
, 0} },
115 {"movzx", 2, 0x0fb6, X
, b_Suf
|Modrm
, { Reg8
|ByteMem
, WordReg
, 0} },
117 /* Push instructions. */
118 {"push", 1, 0x50, X
, wl_Suf
|ShortForm
|DefaultSize
, { WordReg
, 0, 0 } },
119 {"push", 1, 0xff, 6, wl_Suf
|Modrm
|DefaultSize
, { WordReg
|WordMem
, 0, 0 } },
120 {"push", 1, 0x6a, X
, wl_Suf
|DefaultSize
, { Imm8S
, 0, 0} },
121 {"push", 1, 0x68, X
, wl_Suf
|DefaultSize
, { Imm16
|Imm32
, 0, 0} },
122 {"push", 1, 0x06, X
, wl_Suf
|Seg2ShortForm
|DefaultSize
, { SReg2
, 0, 0 } },
123 {"push", 1, 0x0fa0, X
, wl_Suf
|Seg3ShortForm
|DefaultSize
, { SReg3
, 0, 0 } },
124 {"pusha", 0, 0x60, X
, wl_Suf
|DefaultSize
, { 0, 0, 0 } },
126 /* Pop instructions. */
127 {"pop", 1, 0x58, X
, wl_Suf
|ShortForm
|DefaultSize
, { WordReg
, 0, 0 } },
128 {"pop", 1, 0x8f, 0, wl_Suf
|Modrm
|DefaultSize
, { WordReg
|WordMem
, 0, 0 } },
129 #define POP_SEG_SHORT 0x07
130 {"pop", 1, 0x07, X
, wl_Suf
|Seg2ShortForm
|DefaultSize
, { SReg2
, 0, 0 } },
131 {"pop", 1, 0x0fa1, X
, wl_Suf
|Seg3ShortForm
|DefaultSize
, { SReg3
, 0, 0 } },
132 {"popa", 0, 0x61, X
, wl_Suf
|DefaultSize
, { 0, 0, 0 } },
134 /* Exchange instructions.
135 xchg commutes: we allow both operand orders. */
136 {"xchg", 2, 0x90, X
, wl_Suf
|ShortForm
, { WordReg
, Acc
, 0 } },
137 {"xchg", 2, 0x90, X
, wl_Suf
|ShortForm
, { Acc
, WordReg
, 0 } },
138 {"xchg", 2, 0x86, X
, bwl_Suf
|W
|Modrm
, { Reg
, Reg
|AnyMem
, 0 } },
139 {"xchg", 2, 0x86, X
, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, Reg
, 0 } },
141 /* In/out from ports. */
142 {"in", 2, 0xe4, X
, bwl_Suf
|W
, { Imm8
, Acc
, 0 } },
143 {"in", 2, 0xec, X
, bwl_Suf
|W
, { InOutPortReg
, Acc
, 0 } },
144 {"in", 1, 0xe4, X
, bwl_Suf
|W
, { Imm8
, 0, 0 } },
145 {"in", 1, 0xec, X
, bwl_Suf
|W
, { InOutPortReg
, 0, 0 } },
146 {"out", 2, 0xe6, X
, bwl_Suf
|W
, { Acc
, Imm8
, 0 } },
147 {"out", 2, 0xee, X
, bwl_Suf
|W
, { Acc
, InOutPortReg
, 0 } },
148 {"out", 1, 0xe6, X
, bwl_Suf
|W
, { Imm8
, 0, 0 } },
149 {"out", 1, 0xee, X
, bwl_Suf
|W
, { InOutPortReg
, 0, 0 } },
151 /* Load effective address. */
152 {"lea", 2, 0x8d, X
, wl_Suf
|Modrm
, { WordMem
, WordReg
, 0 } },
154 /* Load segment registers from memory. */
155 {"lds", 2, 0xc5, X
, wl_Suf
|Modrm
, { WordMem
, WordReg
, 0} },
156 {"les", 2, 0xc4, X
, wl_Suf
|Modrm
, { WordMem
, WordReg
, 0} },
157 {"lfs", 2, 0x0fb4, X
, wl_Suf
|Modrm
, { WordMem
, WordReg
, 0} },
158 {"lgs", 2, 0x0fb5, X
, wl_Suf
|Modrm
, { WordMem
, WordReg
, 0} },
159 {"lss", 2, 0x0fb2, X
, wl_Suf
|Modrm
, { WordMem
, WordReg
, 0} },
161 /* Flags register instructions. */
162 {"clc", 0, 0xf8, X
, NoSuf
, { 0, 0, 0} },
163 {"cld", 0, 0xfc, X
, NoSuf
, { 0, 0, 0} },
164 {"cli", 0, 0xfa, X
, NoSuf
, { 0, 0, 0} },
165 {"clts", 0, 0x0f06, X
, NoSuf
, { 0, 0, 0} },
166 {"cmc", 0, 0xf5, X
, NoSuf
, { 0, 0, 0} },
167 {"lahf", 0, 0x9f, X
, NoSuf
, { 0, 0, 0} },
168 {"sahf", 0, 0x9e, X
, NoSuf
, { 0, 0, 0} },
169 {"pushf", 0, 0x9c, X
, wl_Suf
|DefaultSize
, { 0, 0, 0} },
170 {"popf", 0, 0x9d, X
, wl_Suf
|DefaultSize
, { 0, 0, 0} },
171 {"stc", 0, 0xf9, X
, NoSuf
, { 0, 0, 0} },
172 {"std", 0, 0xfd, X
, NoSuf
, { 0, 0, 0} },
173 {"sti", 0, 0xfb, X
, NoSuf
, { 0, 0, 0} },
176 {"add", 2, 0x00, X
, bwl_Suf
|D
|W
|Modrm
, { Reg
, Reg
|AnyMem
, 0} },
177 {"add", 2, 0x83, 0, wl_Suf
|Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
178 {"add", 2, 0x04, X
, bwl_Suf
|W
, { Imm
, Acc
, 0} },
179 {"add", 2, 0x80, 0, bwl_Suf
|W
|Modrm
, { Imm
, Reg
|AnyMem
, 0} },
181 {"inc", 1, 0x40, X
, wl_Suf
|ShortForm
, { WordReg
, 0, 0} },
182 {"inc", 1, 0xfe, 0, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
184 {"sub", 2, 0x28, X
, bwl_Suf
|D
|W
|Modrm
, { Reg
, Reg
|AnyMem
, 0} },
185 {"sub", 2, 0x83, 5, wl_Suf
|Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
186 {"sub", 2, 0x2c, X
, bwl_Suf
|W
, { Imm
, Acc
, 0} },
187 {"sub", 2, 0x80, 5, bwl_Suf
|W
|Modrm
, { Imm
, Reg
|AnyMem
, 0} },
189 {"dec", 1, 0x48, X
, wl_Suf
|ShortForm
, { WordReg
, 0, 0} },
190 {"dec", 1, 0xfe, 1, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
192 {"sbb", 2, 0x18, X
, bwl_Suf
|D
|W
|Modrm
, { Reg
, Reg
|AnyMem
, 0} },
193 {"sbb", 2, 0x83, 3, wl_Suf
|Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
194 {"sbb", 2, 0x1c, X
, bwl_Suf
|W
, { Imm
, Acc
, 0} },
195 {"sbb", 2, 0x80, 3, bwl_Suf
|W
|Modrm
, { Imm
, Reg
|AnyMem
, 0} },
197 {"cmp", 2, 0x38, X
, bwl_Suf
|D
|W
|Modrm
, { Reg
, Reg
|AnyMem
, 0} },
198 {"cmp", 2, 0x83, 7, wl_Suf
|Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
199 {"cmp", 2, 0x3c, X
, bwl_Suf
|W
, { Imm
, Acc
, 0} },
200 {"cmp", 2, 0x80, 7, bwl_Suf
|W
|Modrm
, { Imm
, Reg
|AnyMem
, 0} },
202 {"test", 2, 0x84, X
, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, Reg
, 0} },
203 {"test", 2, 0x84, X
, bwl_Suf
|W
|Modrm
, { Reg
, Reg
|AnyMem
, 0} },
204 {"test", 2, 0xa8, X
, bwl_Suf
|W
, { Imm
, Acc
, 0} },
205 {"test", 2, 0xf6, 0, bwl_Suf
|W
|Modrm
, { Imm
, Reg
|AnyMem
, 0} },
207 {"and", 2, 0x20, X
, bwl_Suf
|D
|W
|Modrm
, { Reg
, Reg
|AnyMem
, 0} },
208 {"and", 2, 0x83, 4, wl_Suf
|Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
209 {"and", 2, 0x24, X
, bwl_Suf
|W
, { Imm
, Acc
, 0} },
210 {"and", 2, 0x80, 4, bwl_Suf
|W
|Modrm
, { Imm
, Reg
|AnyMem
, 0} },
212 {"or", 2, 0x08, X
, bwl_Suf
|D
|W
|Modrm
, { Reg
, Reg
|AnyMem
, 0} },
213 {"or", 2, 0x83, 1, wl_Suf
|Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
214 {"or", 2, 0x0c, X
, bwl_Suf
|W
, { Imm
, Acc
, 0} },
215 {"or", 2, 0x80, 1, bwl_Suf
|W
|Modrm
, { Imm
, Reg
|AnyMem
, 0} },
217 {"xor", 2, 0x30, X
, bwl_Suf
|D
|W
|Modrm
, { Reg
, Reg
|AnyMem
, 0} },
218 {"xor", 2, 0x83, 6, wl_Suf
|Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
219 {"xor", 2, 0x34, X
, bwl_Suf
|W
, { Imm
, Acc
, 0} },
220 {"xor", 2, 0x80, 6, bwl_Suf
|W
|Modrm
, { Imm
, Reg
|AnyMem
, 0} },
222 /* iclr with 1 operand is really xor with 2 operands. */
223 {"clr", 1, 0x30, X
, bwl_Suf
|W
|Modrm
|regKludge
, { Reg
, 0, 0 } },
225 {"adc", 2, 0x10, X
, bwl_Suf
|D
|W
|Modrm
, { Reg
, Reg
|AnyMem
, 0} },
226 {"adc", 2, 0x83, 2, wl_Suf
|Modrm
, { Imm8S
, WordReg
|WordMem
, 0} },
227 {"adc", 2, 0x14, X
, bwl_Suf
|W
, { Imm
, Acc
, 0} },
228 {"adc", 2, 0x80, 2, bwl_Suf
|W
|Modrm
, { Imm
, Reg
|AnyMem
, 0} },
230 {"neg", 1, 0xf6, 3, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
231 {"not", 1, 0xf6, 2, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
233 {"aaa", 0, 0x37, X
, NoSuf
, { 0, 0, 0} },
234 {"aas", 0, 0x3f, X
, NoSuf
, { 0, 0, 0} },
235 {"daa", 0, 0x27, X
, NoSuf
, { 0, 0, 0} },
236 {"das", 0, 0x2f, X
, NoSuf
, { 0, 0, 0} },
237 {"aad", 0, 0xd50a, X
, NoSuf
, { 0, 0, 0} },
238 {"aad", 1, 0xd5, X
, NoSuf
, { Imm8S
, 0, 0} },
239 {"aam", 0, 0xd40a, X
, NoSuf
, { 0, 0, 0} },
240 {"aam", 1, 0xd4, X
, NoSuf
, { Imm8S
, 0, 0} },
242 /* Conversion insns. */
244 {"cbw", 0, 0x98, X
, NoSuf
|Size16
, { 0, 0, 0} },
245 {"cwde", 0, 0x98, X
, NoSuf
|Size32
, { 0, 0, 0} },
246 {"cwd", 0, 0x99, X
, NoSuf
|Size16
, { 0, 0, 0} },
247 {"cdq", 0, 0x99, X
, NoSuf
|Size32
, { 0, 0, 0} },
249 {"cbtw", 0, 0x98, X
, NoSuf
|Size16
, { 0, 0, 0} },
250 {"cwtl", 0, 0x98, X
, NoSuf
|Size32
, { 0, 0, 0} },
251 {"cwtd", 0, 0x99, X
, NoSuf
|Size16
, { 0, 0, 0} },
252 {"cltd", 0, 0x99, X
, NoSuf
|Size32
, { 0, 0, 0} },
254 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
255 expanding 64-bit multiplies, and *cannot* be selected to accomplish
256 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
257 These multiplies can only be selected with single operand forms. */
258 {"mul", 1, 0xf6, 4, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
259 {"imul", 1, 0xf6, 5, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
260 {"imul", 2, 0x0faf, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
261 {"imul", 3, 0x6b, X
, wl_Suf
|Modrm
, { Imm8S
, WordReg
|WordMem
, WordReg
} },
262 {"imul", 3, 0x69, X
, wl_Suf
|Modrm
, { Imm16
|Imm32
, WordReg
|WordMem
, WordReg
} },
263 /* imul with 2 operands mimics imul with 3 by putting the register in
264 both i.rm.reg & i.rm.regmem fields. regKludge enables this
266 {"imul", 2, 0x6b, X
, wl_Suf
|Modrm
|regKludge
,{ Imm8S
, WordReg
, 0} },
267 {"imul", 2, 0x69, X
, wl_Suf
|Modrm
|regKludge
,{ Imm16
|Imm32
, WordReg
, 0} },
269 {"div", 1, 0xf6, 6, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
270 {"div", 2, 0xf6, 6, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, Acc
, 0} },
271 {"idiv", 1, 0xf6, 7, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
272 {"idiv", 2, 0xf6, 7, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, Acc
, 0} },
274 {"rol", 2, 0xd0, 0, bwl_Suf
|W
|Modrm
, { Imm1
, Reg
|AnyMem
, 0} },
275 {"rol", 2, 0xc0, 0, bwl_Suf
|W
|Modrm
, { Imm8
, Reg
|AnyMem
, 0} },
276 {"rol", 2, 0xd2, 0, bwl_Suf
|W
|Modrm
, { ShiftCount
, Reg
|AnyMem
, 0} },
277 {"rol", 1, 0xd0, 0, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
279 {"ror", 2, 0xd0, 1, bwl_Suf
|W
|Modrm
, { Imm1
, Reg
|AnyMem
, 0} },
280 {"ror", 2, 0xc0, 1, bwl_Suf
|W
|Modrm
, { Imm8
, Reg
|AnyMem
, 0} },
281 {"ror", 2, 0xd2, 1, bwl_Suf
|W
|Modrm
, { ShiftCount
, Reg
|AnyMem
, 0} },
282 {"ror", 1, 0xd0, 1, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
284 {"rcl", 2, 0xd0, 2, bwl_Suf
|W
|Modrm
, { Imm1
, Reg
|AnyMem
, 0} },
285 {"rcl", 2, 0xc0, 2, bwl_Suf
|W
|Modrm
, { Imm8
, Reg
|AnyMem
, 0} },
286 {"rcl", 2, 0xd2, 2, bwl_Suf
|W
|Modrm
, { ShiftCount
, Reg
|AnyMem
, 0} },
287 {"rcl", 1, 0xd0, 2, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
289 {"rcr", 2, 0xd0, 3, bwl_Suf
|W
|Modrm
, { Imm1
, Reg
|AnyMem
, 0} },
290 {"rcr", 2, 0xc0, 3, bwl_Suf
|W
|Modrm
, { Imm8
, Reg
|AnyMem
, 0} },
291 {"rcr", 2, 0xd2, 3, bwl_Suf
|W
|Modrm
, { ShiftCount
, Reg
|AnyMem
, 0} },
292 {"rcr", 1, 0xd0, 3, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
294 {"sal", 2, 0xd0, 4, bwl_Suf
|W
|Modrm
, { Imm1
, Reg
|AnyMem
, 0} },
295 {"sal", 2, 0xc0, 4, bwl_Suf
|W
|Modrm
, { Imm8
, Reg
|AnyMem
, 0} },
296 {"sal", 2, 0xd2, 4, bwl_Suf
|W
|Modrm
, { ShiftCount
, Reg
|AnyMem
, 0} },
297 {"sal", 1, 0xd0, 4, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
298 {"shl", 2, 0xd0, 4, bwl_Suf
|W
|Modrm
, { Imm1
, Reg
|AnyMem
, 0} },
299 {"shl", 2, 0xc0, 4, bwl_Suf
|W
|Modrm
, { Imm8
, Reg
|AnyMem
, 0} },
300 {"shl", 2, 0xd2, 4, bwl_Suf
|W
|Modrm
, { ShiftCount
, Reg
|AnyMem
, 0} },
301 {"shl", 1, 0xd0, 4, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
303 {"shld", 3, 0x0fa4, X
, wl_Suf
|Modrm
, { Imm8
, WordReg
, WordReg
|WordMem
} },
304 {"shld", 3, 0x0fa5, X
, wl_Suf
|Modrm
, { ShiftCount
, WordReg
, WordReg
|WordMem
} },
305 {"shld", 2, 0x0fa5, X
, wl_Suf
|Modrm
, { WordReg
, WordReg
|WordMem
, 0} },
307 {"shr", 2, 0xd0, 5, bwl_Suf
|W
|Modrm
, { Imm1
, Reg
|AnyMem
, 0} },
308 {"shr", 2, 0xc0, 5, bwl_Suf
|W
|Modrm
, { Imm8
, Reg
|AnyMem
, 0} },
309 {"shr", 2, 0xd2, 5, bwl_Suf
|W
|Modrm
, { ShiftCount
, Reg
|AnyMem
, 0} },
310 {"shr", 1, 0xd0, 5, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
312 {"shrd", 3, 0x0fac, X
, wl_Suf
|Modrm
, { Imm8
, WordReg
, WordReg
|WordMem
} },
313 {"shrd", 3, 0x0fad, X
, wl_Suf
|Modrm
, { ShiftCount
, WordReg
, WordReg
|WordMem
} },
314 {"shrd", 2, 0x0fad, X
, wl_Suf
|Modrm
, { WordReg
, WordReg
|WordMem
, 0} },
316 {"sar", 2, 0xd0, 7, bwl_Suf
|W
|Modrm
, { Imm1
, Reg
|AnyMem
, 0} },
317 {"sar", 2, 0xc0, 7, bwl_Suf
|W
|Modrm
, { Imm8
, Reg
|AnyMem
, 0} },
318 {"sar", 2, 0xd2, 7, bwl_Suf
|W
|Modrm
, { ShiftCount
, Reg
|AnyMem
, 0} },
319 {"sar", 1, 0xd0, 7, bwl_Suf
|W
|Modrm
, { Reg
|AnyMem
, 0, 0} },
321 /* Control transfer instructions. */
322 {"call", 1, 0xe8, X
, wl_Suf
|JumpDword
|DefaultSize
, { Disp16
|Disp32
, 0, 0} },
323 {"call", 1, 0xff, 2, wl_Suf
|Modrm
|DefaultSize
, { WordReg
|WordMem
|JumpAbsolute
, 0, 0} },
325 {"call", 2, 0x9a, X
, wl_Suf
|JumpInterSegment
|DefaultSize
, { Imm16
, Imm16
|Imm32
, 0} },
327 {"call", 1, 0xff, 3, x_Suf
|Modrm
|DefaultSize
, { WordMem
, 0, 0} },
328 {"lcall", 2, 0x9a, X
, wl_Suf
|JumpInterSegment
|DefaultSize
, { Imm16
, Imm16
|Imm32
, 0} },
329 {"lcall", 1, 0xff, 3, wl_Suf
|Modrm
|DefaultSize
, { WordMem
|JumpAbsolute
, 0, 0} },
331 #define JUMP_PC_RELATIVE 0xeb
332 {"jmp", 1, 0xeb, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
333 {"jmp", 1, 0xff, 4, wl_Suf
|Modrm
, { WordReg
|WordMem
|JumpAbsolute
, 0, 0} },
335 {"jmp", 2, 0xea, X
, wl_Suf
|JumpInterSegment
, { Imm16
, Imm16
|Imm32
, 0} },
337 {"jmp", 1, 0xff, 5, x_Suf
|Modrm
, { WordMem
, 0, 0} },
338 {"ljmp", 2, 0xea, X
, wl_Suf
|JumpInterSegment
, { Imm16
, Imm16
|Imm32
, 0} },
339 {"ljmp", 1, 0xff, 5, wl_Suf
|Modrm
, { WordMem
|JumpAbsolute
, 0, 0} },
341 {"ret", 0, 0xc3, X
, wl_Suf
|DefaultSize
, { 0, 0, 0} },
342 {"ret", 1, 0xc2, X
, wl_Suf
|DefaultSize
, { Imm16
, 0, 0} },
343 {"lret", 0, 0xcb, X
, wl_Suf
|DefaultSize
, { 0, 0, 0} },
344 {"lret", 1, 0xca, X
, wl_Suf
|DefaultSize
, { Imm16
, 0, 0} },
345 {"enter", 2, 0xc8, X
, wl_Suf
|DefaultSize
, { Imm16
, Imm8
, 0} },
346 {"leave", 0, 0xc9, X
, wl_Suf
|DefaultSize
, { 0, 0, 0} },
348 /* Conditional jumps. */
349 {"jo", 1, 0x70, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
350 {"jno", 1, 0x71, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
351 {"jb", 1, 0x72, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
352 {"jc", 1, 0x72, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
353 {"jnae", 1, 0x72, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
354 {"jnb", 1, 0x73, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
355 {"jnc", 1, 0x73, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
356 {"jae", 1, 0x73, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
357 {"je", 1, 0x74, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
358 {"jz", 1, 0x74, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
359 {"jne", 1, 0x75, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
360 {"jnz", 1, 0x75, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
361 {"jbe", 1, 0x76, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
362 {"jna", 1, 0x76, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
363 {"jnbe", 1, 0x77, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
364 {"ja", 1, 0x77, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
365 {"js", 1, 0x78, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
366 {"jns", 1, 0x79, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
367 {"jp", 1, 0x7a, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
368 {"jpe", 1, 0x7a, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
369 {"jnp", 1, 0x7b, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
370 {"jpo", 1, 0x7b, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
371 {"jl", 1, 0x7c, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
372 {"jnge", 1, 0x7c, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
373 {"jnl", 1, 0x7d, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
374 {"jge", 1, 0x7d, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
375 {"jle", 1, 0x7e, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
376 {"jng", 1, 0x7e, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
377 {"jnle", 1, 0x7f, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
378 {"jg", 1, 0x7f, X
, NoSuf
|Jump
, { Disp
, 0, 0} },
380 /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
381 {"jcxz", 1, 0xe3, X
, NoSuf
|JumpByte
|Size16
, { Disp
, 0, 0} },
382 {"jecxz", 1, 0xe3, X
, NoSuf
|JumpByte
|Size32
, { Disp
, 0, 0} },
384 /* The loop instructions also use the address size prefix to select
385 %cx rather than %ecx for the loop count, so the `w' form of these
386 instructions emit an address size prefix rather than a data size
388 {"loop", 1, 0xe2, X
, wl_Suf
|JumpByte
, { Disp
, 0, 0} },
389 {"loopz", 1, 0xe1, X
, wl_Suf
|JumpByte
, { Disp
, 0, 0} },
390 {"loope", 1, 0xe1, X
, wl_Suf
|JumpByte
, { Disp
, 0, 0} },
391 {"loopnz", 1, 0xe0, X
, wl_Suf
|JumpByte
, { Disp
, 0, 0} },
392 {"loopne", 1, 0xe0, X
, wl_Suf
|JumpByte
, { Disp
, 0, 0} },
394 /* Set byte on flag instructions. */
395 {"seto", 1, 0x0f90, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
396 {"setno", 1, 0x0f91, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
397 {"setb", 1, 0x0f92, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
398 {"setc", 1, 0x0f92, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
399 {"setnae", 1, 0x0f92, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
400 {"setnb", 1, 0x0f93, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
401 {"setnc", 1, 0x0f93, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
402 {"setae", 1, 0x0f93, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
403 {"sete", 1, 0x0f94, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
404 {"setz", 1, 0x0f94, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
405 {"setne", 1, 0x0f95, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
406 {"setnz", 1, 0x0f95, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
407 {"setbe", 1, 0x0f96, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
408 {"setna", 1, 0x0f96, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
409 {"setnbe", 1, 0x0f97, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
410 {"seta", 1, 0x0f97, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
411 {"sets", 1, 0x0f98, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
412 {"setns", 1, 0x0f99, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
413 {"setp", 1, 0x0f9a, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
414 {"setpe", 1, 0x0f9a, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
415 {"setnp", 1, 0x0f9b, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
416 {"setpo", 1, 0x0f9b, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
417 {"setl", 1, 0x0f9c, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
418 {"setnge", 1, 0x0f9c, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
419 {"setnl", 1, 0x0f9d, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
420 {"setge", 1, 0x0f9d, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
421 {"setle", 1, 0x0f9e, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
422 {"setng", 1, 0x0f9e, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
423 {"setnle", 1, 0x0f9f, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
424 {"setg", 1, 0x0f9f, 0, b_Suf
|Modrm
, { Reg8
|ByteMem
, 0, 0} },
426 /* String manipulation. */
427 {"cmps", 0, 0xa6, X
, bwld_Suf
|W
|IsString
, { 0, 0, 0} },
428 {"cmps", 2, 0xa6, X
, bwld_Suf
|W
|IsString
, { AnyMem
|EsSeg
, AnyMem
, 0} },
429 {"scmp", 0, 0xa6, X
, bwld_Suf
|W
|IsString
, { 0, 0, 0} },
430 {"scmp", 2, 0xa6, X
, bwld_Suf
|W
|IsString
, { AnyMem
|EsSeg
, AnyMem
, 0} },
431 {"ins", 0, 0x6c, X
, bwld_Suf
|W
|IsString
, { 0, 0, 0} },
432 {"ins", 2, 0x6c, X
, bwld_Suf
|W
|IsString
, { InOutPortReg
, AnyMem
|EsSeg
, 0} },
433 {"outs", 0, 0x6e, X
, bwld_Suf
|W
|IsString
, { 0, 0, 0} },
434 {"outs", 2, 0x6e, X
, bwld_Suf
|W
|IsString
, { AnyMem
, InOutPortReg
, 0} },
435 {"lods", 0, 0xac, X
, bwld_Suf
|W
|IsString
, { 0, 0, 0} },
436 {"lods", 1, 0xac, X
, bwld_Suf
|W
|IsString
, { AnyMem
, 0, 0} },
437 {"lods", 2, 0xac, X
, bwld_Suf
|W
|IsString
, { AnyMem
, Acc
, 0} },
438 {"slod", 0, 0xac, X
, bwld_Suf
|W
|IsString
, { 0, 0, 0} },
439 {"slod", 1, 0xac, X
, bwld_Suf
|W
|IsString
, { AnyMem
, 0, 0} },
440 {"slod", 2, 0xac, X
, bwld_Suf
|W
|IsString
, { AnyMem
, Acc
, 0} },
441 {"movs", 0, 0xa4, X
, bwld_Suf
|W
|IsString
, { 0, 0, 0} },
442 {"movs", 2, 0xa4, X
, bwld_Suf
|W
|IsString
, { AnyMem
, AnyMem
|EsSeg
, 0} },
443 {"smov", 0, 0xa4, X
, bwld_Suf
|W
|IsString
, { 0, 0, 0} },
444 {"smov", 2, 0xa4, X
, bwld_Suf
|W
|IsString
, { AnyMem
, AnyMem
|EsSeg
, 0} },
445 {"scas", 0, 0xae, X
, bwld_Suf
|W
|IsString
, { 0, 0, 0} },
446 {"scas", 1, 0xae, X
, bwld_Suf
|W
|IsString
, { AnyMem
|EsSeg
, 0, 0} },
447 {"scas", 2, 0xae, X
, bwld_Suf
|W
|IsString
, { AnyMem
|EsSeg
, Acc
, 0} },
448 {"ssca", 0, 0xae, X
, bwld_Suf
|W
|IsString
, { 0, 0, 0} },
449 {"ssca", 1, 0xae, X
, bwld_Suf
|W
|IsString
, { AnyMem
|EsSeg
, 0, 0} },
450 {"ssca", 2, 0xae, X
, bwld_Suf
|W
|IsString
, { AnyMem
|EsSeg
, Acc
, 0} },
451 {"stos", 0, 0xaa, X
, bwld_Suf
|W
|IsString
, { 0, 0, 0} },
452 {"stos", 1, 0xaa, X
, bwld_Suf
|W
|IsString
, { AnyMem
|EsSeg
, 0, 0} },
453 {"stos", 2, 0xaa, X
, bwld_Suf
|W
|IsString
, { Acc
, AnyMem
|EsSeg
, 0} },
454 {"ssto", 0, 0xaa, X
, bwld_Suf
|W
|IsString
, { 0, 0, 0} },
455 {"ssto", 1, 0xaa, X
, bwld_Suf
|W
|IsString
, { AnyMem
|EsSeg
, 0, 0} },
456 {"ssto", 2, 0xaa, X
, bwld_Suf
|W
|IsString
, { Acc
, AnyMem
|EsSeg
, 0} },
457 {"xlat", 0, 0xd7, X
, b_Suf
|IsString
, { 0, 0, 0} },
458 {"xlat", 1, 0xd7, X
, b_Suf
|IsString
, { AnyMem
, 0, 0} },
460 /* Bit manipulation. */
461 {"bsf", 2, 0x0fbc, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
462 {"bsr", 2, 0x0fbd, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
463 {"bt", 2, 0x0fa3, X
, wl_Suf
|Modrm
, { WordReg
, WordReg
|WordMem
, 0} },
464 {"bt", 2, 0x0fba, 4, wl_Suf
|Modrm
, { Imm8
, WordReg
|WordMem
, 0} },
465 {"btc", 2, 0x0fbb, X
, wl_Suf
|Modrm
, { WordReg
, WordReg
|WordMem
, 0} },
466 {"btc", 2, 0x0fba, 7, wl_Suf
|Modrm
, { Imm8
, WordReg
|WordMem
, 0} },
467 {"btr", 2, 0x0fb3, X
, wl_Suf
|Modrm
, { WordReg
, WordReg
|WordMem
, 0} },
468 {"btr", 2, 0x0fba, 6, wl_Suf
|Modrm
, { Imm8
, WordReg
|WordMem
, 0} },
469 {"bts", 2, 0x0fab, X
, wl_Suf
|Modrm
, { WordReg
, WordReg
|WordMem
, 0} },
470 {"bts", 2, 0x0fba, 5, wl_Suf
|Modrm
, { Imm8
, WordReg
|WordMem
, 0} },
472 /* Interrupts & op. sys insns. */
473 /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
475 #define INT_OPCODE 0xcd
476 #define INT3_OPCODE 0xcc
477 {"int", 1, 0xcd, X
, NoSuf
, { Imm8
, 0, 0} },
478 {"int3", 0, 0xcc, X
, NoSuf
, { 0, 0, 0} },
479 {"into", 0, 0xce, X
, NoSuf
, { 0, 0, 0} },
480 {"iret", 0, 0xcf, X
, wl_Suf
, { 0, 0, 0} },
481 /* i386sl, i486sl, later 486, and Pentium. */
482 {"rsm", 0, 0x0faa, X
, NoSuf
, { 0, 0, 0} },
484 {"bound", 2, 0x62, X
, wl_Suf
|Modrm
, { WordReg
, WordMem
, 0} },
486 {"hlt", 0, 0xf4, X
, NoSuf
, { 0, 0, 0} },
487 /* nop is actually 'xchgl %eax, %eax'. */
488 {"nop", 0, 0x90, X
, NoSuf
, { 0, 0, 0} },
490 /* Protection control. */
491 {"arpl", 2, 0x63, X
, w_Suf
|Modrm
|IgnoreSize
,{ Reg16
, Reg16
|ShortMem
, 0} },
492 {"lar", 2, 0x0f02, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
493 {"lgdt", 1, 0x0f01, 2, wl_Suf
|Modrm
, { WordMem
, 0, 0} },
494 {"lidt", 1, 0x0f01, 3, wl_Suf
|Modrm
, { WordMem
, 0, 0} },
495 {"lldt", 1, 0x0f00, 2, w_Suf
|Modrm
|IgnoreSize
,{ Reg16
|ShortMem
, 0, 0} },
496 {"lmsw", 1, 0x0f01, 6, w_Suf
|Modrm
|IgnoreSize
,{ Reg16
|ShortMem
, 0, 0} },
497 {"lsl", 2, 0x0f03, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
498 {"ltr", 1, 0x0f00, 3, w_Suf
|Modrm
|IgnoreSize
,{ Reg16
|ShortMem
, 0, 0} },
500 {"sgdt", 1, 0x0f01, 0, wl_Suf
|Modrm
, { WordMem
, 0, 0} },
501 {"sidt", 1, 0x0f01, 1, wl_Suf
|Modrm
, { WordMem
, 0, 0} },
502 {"sldt", 1, 0x0f00, 0, wl_Suf
|Modrm
, { WordReg
|WordMem
, 0, 0} },
503 {"smsw", 1, 0x0f01, 4, wl_Suf
|Modrm
, { WordReg
|WordMem
, 0, 0} },
504 {"str", 1, 0x0f00, 1, w_Suf
|Modrm
|IgnoreSize
,{ Reg16
|ShortMem
, 0, 0} },
506 {"verr", 1, 0x0f00, 4, w_Suf
|Modrm
|IgnoreSize
,{ Reg16
|ShortMem
, 0, 0} },
507 {"verw", 1, 0x0f00, 5, w_Suf
|Modrm
|IgnoreSize
,{ Reg16
|ShortMem
, 0, 0} },
509 /* Floating point instructions. */
512 {"fld", 1, 0xd9c0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} }, /* register */
513 {"fld", 1, 0xd9, 0, sld_FP
|FloatMF
|Modrm
, { LongMem
|LLongMem
, 0, 0} }, /* %st0 <-- mem float/double */
514 {"fld", 1, 0xd9c0, X
, l_FP
|ShortForm
|Ugh
, { FloatReg
, 0, 0} },
516 {"fld", 1, 0xdb, 5, x_FP
|Modrm
, { LLongMem
, 0, 0} }, /* %st0 <-- mem efloat */
517 {"fild", 1, 0xdf, 0, sl_Suf
|FloatMF
|Modrm
, { ShortMem
|LongMem
, 0, 0} }, /* %st0 <-- mem word(16)/dword(32) */
519 {"fildd", 1, 0xdf, 5, FP
|Modrm
, { LLongMem
, 0, 0} }, /* %st0 <-- mem qword (64) */
520 {"fildq", 1, 0xdf, 5, FP
|Modrm
, { LLongMem
, 0, 0} }, /* %st0 <-- mem qword (64) */
521 {"fildll", 1, 0xdf, 5, FP
|Modrm
, { LLongMem
, 0, 0} }, /* %st0 <-- mem qword (64) */
522 {"fldt", 1, 0xdb, 5, FP
|Modrm
, { LLongMem
, 0, 0} }, /* %st0 <-- mem efloat */
523 {"fbld", 1, 0xdf, 4, FP
|Modrm
, { LLongMem
, 0, 0} }, /* %st0 <-- mem bcd */
526 {"fst", 1, 0xddd0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} }, /* register */
527 {"fst", 1, 0xd9, 2, sld_FP
|FloatMF
|Modrm
, { LongMem
|LLongMem
, 0, 0} }, /* %st0 --> mem float/double */
528 {"fst", 1, 0xddd0, X
, l_FP
|ShortForm
|Ugh
, { FloatReg
, 0, 0} },
529 {"fist", 1, 0xdf, 2, sld_FP
|FloatMF
|Modrm
, { ShortMem
|LongMem
, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */
531 /* store (with pop) */
532 {"fstp", 1, 0xddd8, X
, FP
|ShortForm
, { FloatReg
, 0, 0} }, /* register */
533 {"fstp", 1, 0xd9, 3, sld_FP
|FloatMF
|Modrm
, { LongMem
|LLongMem
, 0, 0} }, /* %st0 --> mem float/double */
534 {"fstp", 1, 0xddd8, X
, l_FP
|ShortForm
|Ugh
, { FloatReg
, 0, 0} },
536 {"fstp", 1, 0xdb, 7, x_FP
|Modrm
, { LLongMem
, 0, 0} }, /* %st0 --> mem efloat */
537 {"fistp", 1, 0xdf, 3, sl_FP
|FloatMF
|Modrm
, { ShortMem
|LongMem
, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */
539 {"fistpd", 1, 0xdf, 7, FP
|Modrm
, { LLongMem
, 0, 0} }, /* %st0 --> mem qword (64) */
540 {"fistpq", 1, 0xdf, 7, FP
|Modrm
, { LLongMem
, 0, 0} }, /* %st0 --> mem qword (64) */
541 {"fistpll",1, 0xdf, 7, FP
|Modrm
, { LLongMem
, 0, 0} }, /* %st0 --> mem qword (64) */
542 {"fstpt", 1, 0xdb, 7, FP
|Modrm
, { LLongMem
, 0, 0} }, /* %st0 --> mem efloat */
543 {"fbstp", 1, 0xdf, 6, FP
|Modrm
, { LLongMem
, 0, 0} }, /* %st0 --> mem bcd */
545 /* exchange %st<n> with %st0 */
546 {"fxch", 1, 0xd9c8, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
547 {"fxch", 0, 0xd9c9, X
, FP
, { 0, 0, 0} }, /* alias for fxch %st(1) */
549 /* comparison (without pop) */
550 {"fcom", 1, 0xd8d0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
551 {"fcom", 0, 0xd8d1, X
, FP
, { 0, 0, 0} }, /* alias for fcom %st(1) */
552 {"fcom", 1, 0xd8, 2, sld_FP
|FloatMF
|Modrm
, { LongMem
|LLongMem
, 0, 0} }, /* compare %st0, mem float/double */
553 {"fcom", 1, 0xd8d0, X
, l_FP
|ShortForm
|Ugh
, { FloatReg
, 0, 0} },
554 {"ficom", 1, 0xde, 2, sl_FP
|FloatMF
|Modrm
, { ShortMem
|LongMem
, 0, 0} }, /* compare %st0, mem word/dword */
556 /* comparison (with pop) */
557 {"fcomp", 1, 0xd8d8, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
558 {"fcomp", 0, 0xd8d9, X
, FP
, { 0, 0, 0} }, /* alias for fcomp %st(1) */
559 {"fcomp", 1, 0xd8, 3, sld_FP
|FloatMF
|Modrm
, { LongMem
|LLongMem
, 0, 0} }, /* compare %st0, mem float/double */
560 {"fcomp", 1, 0xd8d8, X
, l_FP
|ShortForm
|Ugh
, { FloatReg
, 0, 0} },
561 {"ficomp", 1, 0xde, 3, sl_FP
|FloatMF
|Modrm
, { ShortMem
|LongMem
, 0, 0} }, /* compare %st0, mem word/dword */
562 {"fcompp", 0, 0xded9, X
, FP
, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */
564 /* unordered comparison (with pop) */
565 {"fucom", 1, 0xdde0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
566 {"fucom", 0, 0xdde1, X
, FP
, { 0, 0, 0} }, /* alias for fucom %st(1) */
567 {"fucomp", 1, 0xdde8, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
568 {"fucomp", 0, 0xdde9, X
, FP
, { 0, 0, 0} }, /* alias for fucomp %st(1) */
569 {"fucompp",0, 0xdae9, X
, FP
, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
571 {"ftst", 0, 0xd9e4, X
, FP
, { 0, 0, 0} }, /* test %st0 */
572 {"fxam", 0, 0xd9e5, X
, FP
, { 0, 0, 0} }, /* examine %st0 */
574 /* load constants into %st0 */
575 {"fld1", 0, 0xd9e8, X
, FP
, { 0, 0, 0} }, /* %st0 <-- 1.0 */
576 {"fldl2t", 0, 0xd9e9, X
, FP
, { 0, 0, 0} }, /* %st0 <-- log2(10) */
577 {"fldl2e", 0, 0xd9ea, X
, FP
, { 0, 0, 0} }, /* %st0 <-- log2(e) */
578 {"fldpi", 0, 0xd9eb, X
, FP
, { 0, 0, 0} }, /* %st0 <-- pi */
579 {"fldlg2", 0, 0xd9ec, X
, FP
, { 0, 0, 0} }, /* %st0 <-- log10(2) */
580 {"fldln2", 0, 0xd9ed, X
, FP
, { 0, 0, 0} }, /* %st0 <-- ln(2) */
581 {"fldz", 0, 0xd9ee, X
, FP
, { 0, 0, 0} }, /* %st0 <-- 0.0 */
586 {"fadd", 2, 0xd8c0, X
, FP
|ShortForm
|FloatD
, { FloatReg
, FloatAcc
, 0} },
587 {"fadd", 1, 0xd8c0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} }, /* alias for fadd %st(i), %st */
589 {"fadd", 0, 0xdec1, X
, FP
|Ugh
, { 0, 0, 0} }, /* alias for faddp */
591 {"fadd", 1, 0xd8, 0, sld_FP
|FloatMF
|Modrm
, { LongMem
|LLongMem
, 0, 0} },
592 {"fiadd", 1, 0xde, 0, sld_FP
|FloatMF
|Modrm
, { ShortMem
|LongMem
, 0, 0} },
594 {"faddp", 2, 0xdec0, X
, FP
|ShortForm
, { FloatAcc
, FloatReg
, 0} },
595 {"faddp", 1, 0xdec0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
596 {"faddp", 0, 0xdec1, X
, FP
, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
597 {"faddp", 2, 0xdec0, X
, FP
|ShortForm
|Ugh
, { FloatReg
, FloatAcc
, 0} },
600 {"fsub", 2, 0xd8e0, X
, FP
|ShortForm
|FloatDR
, { FloatReg
, FloatAcc
, 0} },
601 {"fsub", 1, 0xd8e0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
603 {"fsub", 0, 0xdee1, X
, FP
|Ugh
, { 0, 0, 0} }, /* alias for fsubp */
605 {"fsub", 1, 0xd8, 4, sld_FP
|FloatMF
|Modrm
, { LongMem
|LLongMem
, 0, 0} },
606 {"fisub", 1, 0xde, 4, sl_FP
|FloatMF
|Modrm
, { ShortMem
|LongMem
, 0, 0} },
609 {"fsubp", 2, 0xdee0, X
, FP
|ShortForm
, { FloatAcc
, FloatReg
, 0} },
610 {"fsubp", 1, 0xdee0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
611 {"fsubp", 0, 0xdee1, X
, FP
, { 0, 0, 0} },
613 {"fsubp", 2, 0xdee0, X
, FP
|ShortForm
|Ugh
, { FloatReg
, FloatAcc
, 0} },
616 {"fsubp", 2, 0xdee8, X
, FP
|ShortForm
, { FloatAcc
, FloatReg
, 0} },
617 {"fsubp", 1, 0xdee8, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
618 {"fsubp", 0, 0xdee9, X
, FP
, { 0, 0, 0} },
621 /* subtract reverse */
622 {"fsubr", 2, 0xd8e8, X
, FP
|ShortForm
|FloatDR
, { FloatReg
, FloatAcc
, 0} },
623 {"fsubr", 1, 0xd8e8, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
625 {"fsubr", 0, 0xdee9, X
, FP
|Ugh
, { 0, 0, 0} }, /* alias for fsubrp */
627 {"fsubr", 1, 0xd8, 5, sld_FP
|FloatMF
|Modrm
, { LongMem
|LLongMem
, 0, 0} },
628 {"fisubr", 1, 0xde, 5, sl_FP
|FloatMF
|Modrm
, { ShortMem
|LongMem
, 0, 0} },
631 {"fsubrp", 2, 0xdee8, X
, FP
|ShortForm
, { FloatAcc
, FloatReg
, 0} },
632 {"fsubrp", 1, 0xdee8, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
633 {"fsubrp", 0, 0xdee9, X
, FP
, { 0, 0, 0} },
635 {"fsubrp", 2, 0xdee8, X
, FP
|ShortForm
|Ugh
, { FloatReg
, FloatAcc
, 0} },
638 {"fsubrp", 2, 0xdee0, X
, FP
|ShortForm
, { FloatAcc
, FloatReg
, 0} },
639 {"fsubrp", 1, 0xdee0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
640 {"fsubrp", 0, 0xdee1, X
, FP
, { 0, 0, 0} },
644 {"fmul", 2, 0xd8c8, X
, FP
|ShortForm
|FloatD
, { FloatReg
, FloatAcc
, 0} },
645 {"fmul", 1, 0xd8c8, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
647 {"fmul", 0, 0xdec9, X
, FP
|Ugh
, { 0, 0, 0} }, /* alias for fmulp */
649 {"fmul", 1, 0xd8, 1, sld_FP
|FloatMF
|Modrm
, { LongMem
|LLongMem
, 0, 0} },
650 {"fimul", 1, 0xde, 1, sld_FP
|FloatMF
|Modrm
, { ShortMem
|LongMem
, 0, 0} },
652 {"fmulp", 2, 0xdec8, X
, FP
|ShortForm
, { FloatAcc
, FloatReg
, 0} },
653 {"fmulp", 1, 0xdec8, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
654 {"fmulp", 0, 0xdec9, X
, FP
, { 0, 0, 0} },
655 {"fmulp", 2, 0xdec8, X
, FP
|ShortForm
|Ugh
, { FloatReg
, FloatAcc
, 0} },
658 {"fdiv", 2, 0xd8f0, X
, FP
|ShortForm
|FloatDR
, { FloatReg
, FloatAcc
, 0} },
659 {"fdiv", 1, 0xd8f0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
661 {"fdiv", 0, 0xdef1, X
, FP
|Ugh
, { 0, 0, 0} }, /* alias for fdivp */
663 {"fdiv", 1, 0xd8, 6, sld_FP
|FloatMF
|Modrm
, { LongMem
|LLongMem
, 0, 0} },
664 {"fidiv", 1, 0xde, 6, sld_FP
|FloatMF
|Modrm
, { ShortMem
|LongMem
, 0, 0} },
667 {"fdivp", 2, 0xdef0, X
, FP
|ShortForm
, { FloatAcc
, FloatReg
, 0} },
668 {"fdivp", 1, 0xdef0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
669 {"fdivp", 0, 0xdef1, X
, FP
, { 0, 0, 0} },
671 {"fdivp", 2, 0xdef0, X
, FP
|ShortForm
|Ugh
, { FloatReg
, FloatAcc
, 0} },
674 {"fdivp", 2, 0xdef8, X
, FP
|ShortForm
, { FloatAcc
, FloatReg
, 0} },
675 {"fdivp", 1, 0xdef8, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
676 {"fdivp", 0, 0xdef9, X
, FP
, { 0, 0, 0} },
680 {"fdivr", 2, 0xd8f8, X
, FP
|ShortForm
|FloatDR
, { FloatReg
, FloatAcc
, 0} },
681 {"fdivr", 1, 0xd8f8, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
683 {"fdivr", 0, 0xdef9, X
, FP
|Ugh
, { 0, 0, 0} }, /* alias for fdivrp */
685 {"fdivr", 1, 0xd8, 7, sld_FP
|FloatMF
|Modrm
, { LongMem
|LLongMem
, 0, 0} },
686 {"fidivr", 1, 0xde, 7, sl_FP
|FloatMF
|Modrm
, { ShortMem
|LongMem
, 0, 0} },
689 {"fdivrp", 2, 0xdef8, X
, FP
|ShortForm
, { FloatAcc
, FloatReg
, 0} },
690 {"fdivrp", 1, 0xdef8, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
691 {"fdivrp", 0, 0xdef9, X
, FP
, { 0, 0, 0} },
693 {"fdivrp", 2, 0xdef8, X
, FP
|ShortForm
|Ugh
, { FloatReg
, FloatAcc
, 0} },
696 {"fdivrp", 2, 0xdef0, X
, FP
|ShortForm
, { FloatAcc
, FloatReg
, 0} },
697 {"fdivrp", 1, 0xdef0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
698 {"fdivrp", 0, 0xdef1, X
, FP
, { 0, 0, 0} },
701 {"f2xm1", 0, 0xd9f0, X
, FP
, { 0, 0, 0} },
702 {"fyl2x", 0, 0xd9f1, X
, FP
, { 0, 0, 0} },
703 {"fptan", 0, 0xd9f2, X
, FP
, { 0, 0, 0} },
704 {"fpatan", 0, 0xd9f3, X
, FP
, { 0, 0, 0} },
705 {"fxtract",0, 0xd9f4, X
, FP
, { 0, 0, 0} },
706 {"fprem1", 0, 0xd9f5, X
, FP
, { 0, 0, 0} },
707 {"fdecstp",0, 0xd9f6, X
, FP
, { 0, 0, 0} },
708 {"fincstp",0, 0xd9f7, X
, FP
, { 0, 0, 0} },
709 {"fprem", 0, 0xd9f8, X
, FP
, { 0, 0, 0} },
710 {"fyl2xp1",0, 0xd9f9, X
, FP
, { 0, 0, 0} },
711 {"fsqrt", 0, 0xd9fa, X
, FP
, { 0, 0, 0} },
712 {"fsincos",0, 0xd9fb, X
, FP
, { 0, 0, 0} },
713 {"frndint",0, 0xd9fc, X
, FP
, { 0, 0, 0} },
714 {"fscale", 0, 0xd9fd, X
, FP
, { 0, 0, 0} },
715 {"fsin", 0, 0xd9fe, X
, FP
, { 0, 0, 0} },
716 {"fcos", 0, 0xd9ff, X
, FP
, { 0, 0, 0} },
717 {"fchs", 0, 0xd9e0, X
, FP
, { 0, 0, 0} },
718 {"fabs", 0, 0xd9e1, X
, FP
, { 0, 0, 0} },
720 /* processor control */
721 {"fninit", 0, 0xdbe3, X
, FP
, { 0, 0, 0} },
722 {"finit", 0, 0xdbe3, X
, FP
|FWait
, { 0, 0, 0} },
723 {"fldcw", 1, 0xd9, 5, FP
|Modrm
, { ShortMem
, 0, 0} },
724 {"fnstcw", 1, 0xd9, 7, FP
|Modrm
, { ShortMem
, 0, 0} },
725 {"fstcw", 1, 0xd9, 7, FP
|FWait
|Modrm
, { ShortMem
, 0, 0} },
726 {"fnstsw", 1, 0xdfe0, X
, FP
, { Acc
, 0, 0} },
727 {"fnstsw", 1, 0xdd, 7, FP
|Modrm
, { ShortMem
, 0, 0} },
728 {"fnstsw", 0, 0xdfe0, X
, FP
, { 0, 0, 0} },
729 {"fstsw", 1, 0xdfe0, X
, FP
|FWait
, { Acc
, 0, 0} },
730 {"fstsw", 1, 0xdd, 7, FP
|FWait
|Modrm
, { ShortMem
, 0, 0} },
731 {"fstsw", 0, 0xdfe0, X
, FP
|FWait
, { 0, 0, 0} },
732 {"fnclex", 0, 0xdbe2, X
, FP
, { 0, 0, 0} },
733 {"fclex", 0, 0xdbe2, X
, FP
|FWait
, { 0, 0, 0} },
734 /* Short forms of fldenv, fstenv use data size prefix. */
735 {"fnstenv",1, 0xd9, 6, sl_Suf
|Modrm
, { LLongMem
, 0, 0} },
736 {"fstenv", 1, 0xd9, 6, sl_Suf
|FWait
|Modrm
, { LLongMem
, 0, 0} },
737 {"fldenv", 1, 0xd9, 4, sl_Suf
|Modrm
, { LLongMem
, 0, 0} },
738 {"fnsave", 1, 0xdd, 6, sl_Suf
|Modrm
, { LLongMem
, 0, 0} },
739 {"fsave", 1, 0xdd, 6, sl_Suf
|FWait
|Modrm
, { LLongMem
, 0, 0} },
740 {"frstor", 1, 0xdd, 4, sl_Suf
|Modrm
, { LLongMem
, 0, 0} },
742 {"ffree", 1, 0xddc0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
743 /* P6:free st(i), pop st */
744 {"ffreep", 1, 0xdfc0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
745 {"fnop", 0, 0xd9d0, X
, FP
, { 0, 0, 0} },
746 #define FWAIT_OPCODE 0x9b
747 {"fwait", 0, 0x9b, X
, FP
, { 0, 0, 0} },
749 /* Opcode prefixes; we allow them as separate insns too. */
751 #define ADDR_PREFIX_OPCODE 0x67
752 {"addr16", 0, 0x67, X
, NoSuf
|IsPrefix
|Size16
|IgnoreSize
, { 0, 0, 0} },
753 {"addr32", 0, 0x67, X
, NoSuf
|IsPrefix
|Size32
|IgnoreSize
, { 0, 0, 0} },
754 {"aword", 0, 0x67, X
, NoSuf
|IsPrefix
|Size16
|IgnoreSize
, { 0, 0, 0} },
755 {"adword", 0, 0x67, X
, NoSuf
|IsPrefix
|Size32
|IgnoreSize
, { 0, 0, 0} },
756 #define DATA_PREFIX_OPCODE 0x66
757 {"data16", 0, 0x66, X
, NoSuf
|IsPrefix
|Size16
|IgnoreSize
, { 0, 0, 0} },
758 {"data32", 0, 0x66, X
, NoSuf
|IsPrefix
|Size32
|IgnoreSize
, { 0, 0, 0} },
759 {"word", 0, 0x66, X
, NoSuf
|IsPrefix
|Size16
|IgnoreSize
, { 0, 0, 0} },
760 {"dword", 0, 0x66, X
, NoSuf
|IsPrefix
|Size32
|IgnoreSize
, { 0, 0, 0} },
761 #define LOCK_PREFIX_OPCODE 0xf0
762 {"lock", 0, 0xf0, X
, NoSuf
|IsPrefix
, { 0, 0, 0} },
763 {"wait", 0, 0x9b, X
, NoSuf
|IsPrefix
, { 0, 0, 0} },
764 #define CS_PREFIX_OPCODE 0x2e
765 {"cs", 0, 0x2e, X
, NoSuf
|IsPrefix
, { 0, 0, 0} },
766 #define DS_PREFIX_OPCODE 0x3e
767 {"ds", 0, 0x3e, X
, NoSuf
|IsPrefix
, { 0, 0, 0} },
768 #define ES_PREFIX_OPCODE 0x26
769 {"es", 0, 0x26, X
, NoSuf
|IsPrefix
, { 0, 0, 0} },
770 #define FS_PREFIX_OPCODE 0x64
771 {"fs", 0, 0x64, X
, NoSuf
|IsPrefix
, { 0, 0, 0} },
772 #define GS_PREFIX_OPCODE 0x65
773 {"gs", 0, 0x65, X
, NoSuf
|IsPrefix
, { 0, 0, 0} },
774 #define SS_PREFIX_OPCODE 0x36
775 {"ss", 0, 0x36, X
, NoSuf
|IsPrefix
, { 0, 0, 0} },
776 #define REPNE_PREFIX_OPCODE 0xf2
777 #define REPE_PREFIX_OPCODE 0xf3
778 {"rep", 0, 0xf3, X
, NoSuf
|IsPrefix
, { 0, 0, 0} },
779 {"repe", 0, 0xf3, X
, NoSuf
|IsPrefix
, { 0, 0, 0} },
780 {"repz", 0, 0xf3, X
, NoSuf
|IsPrefix
, { 0, 0, 0} },
781 {"repne", 0, 0xf2, X
, NoSuf
|IsPrefix
, { 0, 0, 0} },
782 {"repnz", 0, 0xf2, X
, NoSuf
|IsPrefix
, { 0, 0, 0} },
784 /* 486 extensions. */
786 {"bswap", 1, 0x0fc8, X
, l_Suf
|ShortForm
, { Reg32
, 0, 0 } },
787 {"xadd", 2, 0x0fc0, X
, bwl_Suf
|W
|Modrm
, { Reg
, Reg
|AnyMem
, 0 } },
788 {"cmpxchg", 2, 0x0fb0, X
, bwl_Suf
|W
|Modrm
, { Reg
, Reg
|AnyMem
, 0 } },
789 {"invd", 0, 0x0f08, X
, NoSuf
, { 0, 0, 0} },
790 {"wbinvd", 0, 0x0f09, X
, NoSuf
, { 0, 0, 0} },
791 {"invlpg", 1, 0x0f01, 7, NoSuf
|Modrm
, { AnyMem
, 0, 0} },
793 /* 586 and late 486 extensions. */
794 {"cpuid", 0, 0x0fa2, X
, NoSuf
, { 0, 0, 0} },
796 /* Pentium extensions. */
797 {"wrmsr", 0, 0x0f30, X
, NoSuf
, { 0, 0, 0} },
798 {"rdtsc", 0, 0x0f31, X
, NoSuf
, { 0, 0, 0} },
799 {"rdmsr", 0, 0x0f32, X
, NoSuf
, { 0, 0, 0} },
800 {"cmpxchg8b",1,0x0fc7, 1, NoSuf
|Modrm
, { LLongMem
, 0, 0} },
801 {"sysenter",0, 0x0f34, X
, NoSuf
, { 0, 0, 0} },
802 {"sysexit", 0, 0x0f35, X
, NoSuf
, { 0, 0, 0} },
803 {"fxsave", 1, 0x0fae, 0, FP
|Modrm
, { LLongMem
, 0, 0} },
804 {"fxrstor", 1, 0x0fae, 1, FP
|Modrm
, { LLongMem
, 0, 0} },
806 /* Pentium Pro extensions. */
807 {"rdpmc", 0, 0x0f33, X
, NoSuf
, { 0, 0, 0} },
809 {"ud2", 0, 0x0f0b, X
, NoSuf
, { 0, 0, 0} }, /* official undefined instr. */
810 {"ud2a", 0, 0x0f0b, X
, NoSuf
, { 0, 0, 0} }, /* alias for ud2 */
811 {"ud2b", 0, 0x0fb9, X
, NoSuf
, { 0, 0, 0} }, /* 2nd. official undefined instr. */
813 {"cmovo", 2, 0x0f40, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
814 {"cmovno", 2, 0x0f41, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
815 {"cmovb", 2, 0x0f42, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
816 {"cmovc", 2, 0x0f42, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
817 {"cmovnae", 2, 0x0f42, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
818 {"cmovae", 2, 0x0f43, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
819 {"cmovnc", 2, 0x0f43, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
820 {"cmovnb", 2, 0x0f43, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
821 {"cmove", 2, 0x0f44, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
822 {"cmovz", 2, 0x0f44, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
823 {"cmovne", 2, 0x0f45, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
824 {"cmovnz", 2, 0x0f45, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
825 {"cmovbe", 2, 0x0f46, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
826 {"cmovna", 2, 0x0f46, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
827 {"cmova", 2, 0x0f47, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
828 {"cmovnbe", 2, 0x0f47, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
829 {"cmovs", 2, 0x0f48, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
830 {"cmovns", 2, 0x0f49, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
831 {"cmovp", 2, 0x0f4a, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
832 {"cmovnp", 2, 0x0f4b, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
833 {"cmovl", 2, 0x0f4c, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
834 {"cmovnge", 2, 0x0f4c, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
835 {"cmovge", 2, 0x0f4d, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
836 {"cmovnl", 2, 0x0f4d, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
837 {"cmovle", 2, 0x0f4e, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
838 {"cmovng", 2, 0x0f4e, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
839 {"cmovg", 2, 0x0f4f, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
840 {"cmovnle", 2, 0x0f4f, X
, wl_Suf
|Modrm
, { WordReg
|WordMem
, WordReg
, 0} },
842 {"fcmovb", 2, 0xdac0, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
843 {"fcmovnae",2, 0xdac0, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
844 {"fcmove", 2, 0xdac8, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
845 {"fcmovbe", 2, 0xdad0, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
846 {"fcmovna", 2, 0xdad0, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
847 {"fcmovu", 2, 0xdad8, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
848 {"fcmovae", 2, 0xdbc0, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
849 {"fcmovnb", 2, 0xdbc0, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
850 {"fcmovne", 2, 0xdbc8, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
851 {"fcmova", 2, 0xdbd0, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
852 {"fcmovnbe",2, 0xdbd0, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
853 {"fcmovnu", 2, 0xdbd8, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
855 {"fcomi", 2, 0xdbf0, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
856 {"fcomi", 0, 0xdbf1, X
, FP
|ShortForm
, { 0, 0, 0} },
857 {"fcomi", 1, 0xdbf0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
858 {"fucomi", 2, 0xdbe8, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
859 {"fucomi", 0, 0xdbe9, X
, FP
|ShortForm
, { 0, 0, 0} },
860 {"fucomi", 1, 0xdbe8, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
861 {"fcomip", 2, 0xdff0, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
862 {"fcompi", 2, 0xdff0, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
863 {"fcompi", 0, 0xdff1, X
, FP
|ShortForm
, { 0, 0, 0} },
864 {"fcompi", 1, 0xdff0, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
865 {"fucomip", 2, 0xdfe8, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
866 {"fucompi", 2, 0xdfe8, X
, FP
|ShortForm
, { FloatReg
, FloatAcc
, 0} },
867 {"fucompi", 0, 0xdfe9, X
, FP
|ShortForm
, { 0, 0, 0} },
868 {"fucompi", 1, 0xdfe8, X
, FP
|ShortForm
, { FloatReg
, 0, 0} },
870 /* MMX instructions. */
872 {"emms", 0, 0x0f77, X
, FP
, { 0, 0, 0 } },
873 {"movd", 2, 0x0f6e, X
, FP
|Modrm
, { Reg32
|LongMem
, RegMMX
, 0 } },
874 {"movd", 2, 0x0f7e, X
, FP
|Modrm
, { RegMMX
, Reg32
|LongMem
, 0 } },
875 {"movq", 2, 0x0f6f, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
876 {"movq", 2, 0x0f7f, X
, FP
|Modrm
, { RegMMX
, RegMMX
|LongMem
, 0 } },
877 {"packssdw", 2, 0x0f6b, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
878 {"packsswb", 2, 0x0f63, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
879 {"packuswb", 2, 0x0f67, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
880 {"paddb", 2, 0x0ffc, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
881 {"paddw", 2, 0x0ffd, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
882 {"paddd", 2, 0x0ffe, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
883 {"paddsb", 2, 0x0fec, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
884 {"paddsw", 2, 0x0fed, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
885 {"paddusb", 2, 0x0fdc, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
886 {"paddusw", 2, 0x0fdd, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
887 {"pand", 2, 0x0fdb, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
888 {"pandn", 2, 0x0fdf, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
889 {"pcmpeqb", 2, 0x0f74, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
890 {"pcmpeqw", 2, 0x0f75, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
891 {"pcmpeqd", 2, 0x0f76, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
892 {"pcmpgtb", 2, 0x0f64, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
893 {"pcmpgtw", 2, 0x0f65, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
894 {"pcmpgtd", 2, 0x0f66, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
895 {"pmaddwd", 2, 0x0ff5, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
896 {"pmulhw", 2, 0x0fe5, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
897 {"pmullw", 2, 0x0fd5, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
898 {"por", 2, 0x0feb, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
899 {"psllw", 2, 0x0ff1, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
900 {"psllw", 2, 0x0f71, 6, FP
|Modrm
, { Imm8
, RegMMX
, 0 } },
901 {"pslld", 2, 0x0ff2, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
902 {"pslld", 2, 0x0f72, 6, FP
|Modrm
, { Imm8
, RegMMX
, 0 } },
903 {"psllq", 2, 0x0ff3, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
904 {"psllq", 2, 0x0f73, 6, FP
|Modrm
, { Imm8
, RegMMX
, 0 } },
905 {"psraw", 2, 0x0fe1, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
906 {"psraw", 2, 0x0f71, 4, FP
|Modrm
, { Imm8
, RegMMX
, 0 } },
907 {"psrad", 2, 0x0fe2, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
908 {"psrad", 2, 0x0f72, 4, FP
|Modrm
, { Imm8
, RegMMX
, 0 } },
909 {"psrlw", 2, 0x0fd1, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
910 {"psrlw", 2, 0x0f71, 2, FP
|Modrm
, { Imm8
, RegMMX
, 0 } },
911 {"psrld", 2, 0x0fd2, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
912 {"psrld", 2, 0x0f72, 2, FP
|Modrm
, { Imm8
, RegMMX
, 0 } },
913 {"psrlq", 2, 0x0fd3, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
914 {"psrlq", 2, 0x0f73, 2, FP
|Modrm
, { Imm8
, RegMMX
, 0 } },
915 {"psubb", 2, 0x0ff8, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
916 {"psubw", 2, 0x0ff9, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
917 {"psubd", 2, 0x0ffa, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
918 {"psubsb", 2, 0x0fe8, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
919 {"psubsw", 2, 0x0fe9, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
920 {"psubusb", 2, 0x0fd8, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
921 {"psubusw", 2, 0x0fd9, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
922 {"punpckhbw",2, 0x0f68, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
923 {"punpckhwd",2, 0x0f69, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
924 {"punpckhdq",2, 0x0f6a, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
925 {"punpcklbw",2, 0x0f60, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
926 {"punpcklwd",2, 0x0f61, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
927 {"punpckldq",2, 0x0f62, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
928 {"pxor", 2, 0x0fef, X
, FP
|Modrm
, { RegMMX
|LongMem
, RegMMX
, 0 } },
931 /* PIII Katmai New Instructions / SIMD instructions. */
933 {"addps", 2, 0x0f58, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
934 {"addss", 2, 0xf30f58, X
, FP
|Modrm
, { RegXMM
|WordMem
, RegXMM
, 0 } },
935 {"andnps", 2, 0x0f55, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
936 {"andps", 2, 0x0f54, X
, FP
|Modrm
, { RegXMM
|WordMem
, RegXMM
, 0 } },
937 {"cmpeqps", 2, 0x0fc2, 0, FP
|Modrm
|ImmExt
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
938 {"cmpeqss", 2, 0xf30fc2, 0, FP
|Modrm
|ImmExt
, { RegXMM
|WordMem
, RegXMM
, 0 } },
939 {"cmpleps", 2, 0x0fc2, 2, FP
|Modrm
|ImmExt
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
940 {"cmpless", 2, 0xf30fc2, 2, FP
|Modrm
|ImmExt
, { RegXMM
|WordMem
, RegXMM
, 0 } },
941 {"cmpltps", 2, 0x0fc2, 1, FP
|Modrm
|ImmExt
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
942 {"cmpltss", 2, 0xf30fc2, 1, FP
|Modrm
|ImmExt
, { RegXMM
|WordMem
, RegXMM
, 0 } },
943 {"cmpneqps", 2, 0x0fc2, 4, FP
|Modrm
|ImmExt
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
944 {"cmpneqss", 2, 0xf30fc2, 4, FP
|Modrm
|ImmExt
, { RegXMM
|WordMem
, RegXMM
, 0 } },
945 {"cmpnleps", 2, 0x0fc2, 6, FP
|Modrm
|ImmExt
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
946 {"cmpnless", 2, 0xf30fc2, 6, FP
|Modrm
|ImmExt
, { RegXMM
|WordMem
, RegXMM
, 0 } },
947 {"cmpnltps", 2, 0x0fc2, 5, FP
|Modrm
|ImmExt
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
948 {"cmpnltss", 2, 0xf30fc2, 5, FP
|Modrm
|ImmExt
, { RegXMM
|WordMem
, RegXMM
, 0 } },
949 {"cmpordps", 2, 0x0fc2, 7, FP
|Modrm
|ImmExt
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
950 {"cmpordss", 2, 0xf30fc2, 7, FP
|Modrm
|ImmExt
, { RegXMM
|WordMem
, RegXMM
, 0 } },
951 {"cmpunordps",2, 0x0fc2, 3, FP
|Modrm
|ImmExt
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
952 {"cmpunordss",2, 0xf30fc2, 3, FP
|Modrm
|ImmExt
, { RegXMM
|WordMem
, RegXMM
, 0 } },
953 {"cmpps", 3, 0x0fc2, X
, FP
|Modrm
, { Imm8
, RegXMM
|LLongMem
, RegXMM
} },
954 {"cmpss", 3, 0xf30fc2, X
, FP
|Modrm
, { Imm8
, RegXMM
|WordMem
, RegXMM
} },
955 {"comiss", 2, 0x0f2f, X
, FP
|Modrm
, { RegXMM
|WordMem
, RegXMM
, 0 } },
956 {"cvtpi2ps", 2, 0x0f2a, X
, FP
|Modrm
, { RegMMX
|LLongMem
, RegXMM
, 0 } },
957 {"cvtps2pi", 2, 0x0f2d, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegMMX
, 0 } },
958 {"cvtsi2ss", 2, 0xf30f2a, X
, FP
|Modrm
, { Reg32
|WordMem
, RegXMM
, 0 } },
959 {"cvtss2si", 2, 0xf30f2d, X
, FP
|Modrm
, { RegXMM
|WordMem
, Reg32
, 0 } },
960 {"cvttps2pi", 2, 0x0f2c, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegMMX
, 0 } },
961 {"cvttss2si", 2, 0xf30f2c, X
, FP
|Modrm
, { RegXMM
|WordMem
, Reg32
, 0 } },
962 {"divps", 2, 0x0f5e, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
963 {"divss", 2, 0xf30f5e, X
, FP
|Modrm
, { RegXMM
|WordMem
, RegXMM
, 0 } },
964 {"ldmxcsr", 1, 0x0fae, 2, FP
|Modrm
, { WordMem
, 0, 0 } },
965 {"maskmovq", 2, 0x0ff7, X
, FP
|Modrm
, { RegMMX
|InvMem
, RegMMX
, 0 } },
966 {"maxps", 2, 0x0f5f, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
967 {"maxss", 2, 0xf30f5f, X
, FP
|Modrm
, { RegXMM
|WordMem
, RegXMM
, 0 } },
968 {"minps", 2, 0x0f5d, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
969 {"minss", 2, 0xf30f5d, X
, FP
|Modrm
, { RegXMM
|WordMem
, RegXMM
, 0 } },
970 {"movaps", 2, 0x0f28, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
971 {"movaps", 2, 0x0f29, X
, FP
|Modrm
, { RegXMM
, RegXMM
|LLongMem
, 0 } },
972 {"movhlps", 2, 0x0f12, X
, FP
|Modrm
, { RegXMM
|InvMem
, RegXMM
, 0 } },
973 {"movhps", 2, 0x0f16, X
, FP
|Modrm
, { LLongMem
, RegXMM
, 0 } },
974 {"movhps", 2, 0x0f17, X
, FP
|Modrm
, { RegXMM
, LLongMem
, 0 } },
975 {"movlhps", 2, 0x0f16, X
, FP
|Modrm
, { RegXMM
|InvMem
, RegXMM
, 0 } },
976 {"movlps", 2, 0x0f12, X
, FP
|Modrm
, { LLongMem
, RegXMM
, 0 } },
977 {"movlps", 2, 0x0f13, X
, FP
|Modrm
, { RegXMM
, LLongMem
, 0 } },
978 {"movmskps", 2, 0x0f50, X
, FP
|Modrm
, { RegXMM
|InvMem
, Reg32
, 0 } },
979 {"movntps", 2, 0x0f2b, X
, FP
|Modrm
, { RegXMM
, LLongMem
, 0 } },
980 {"movntq", 2, 0x0fe7, X
, FP
|Modrm
, { RegMMX
, LLongMem
, 0 } },
981 {"movss", 2, 0xf30f10, X
, FP
|Modrm
, { RegXMM
|WordMem
, RegXMM
, 0 } },
982 {"movss", 2, 0xf30f11, X
, FP
|Modrm
, { RegXMM
, RegXMM
|WordMem
, 0 } },
983 {"movups", 2, 0x0f10, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
984 {"movups", 2, 0x0f11, X
, FP
|Modrm
, { RegXMM
, RegXMM
|LLongMem
, 0 } },
985 {"mulps", 2, 0x0f59, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
986 {"mulss", 2, 0xf30f59, X
, FP
|Modrm
, { RegXMM
|WordMem
, RegXMM
, 0 } },
987 {"orps", 2, 0x0f56, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
988 {"pavgb", 2, 0x0fe0, X
, FP
|Modrm
, { RegMMX
|LLongMem
, RegMMX
, 0 } },
989 {"pavgw", 2, 0x0fe3, X
, FP
|Modrm
, { RegMMX
|LLongMem
, RegMMX
, 0 } },
990 {"pextrw", 3, 0x0fc5, X
, FP
|Modrm
, { Imm8
, RegMMX
, Reg32
|InvMem
} },
991 {"pinsrw", 3, 0x0fc4, X
, FP
|Modrm
, { Imm8
, Reg32
|ShortMem
, RegMMX
} },
992 {"pmaxsw", 2, 0x0fee, X
, FP
|Modrm
, { RegMMX
|LLongMem
, RegMMX
, 0 } },
993 {"pmaxub", 2, 0x0fde, X
, FP
|Modrm
, { RegMMX
|LLongMem
, RegMMX
, 0 } },
994 {"pminsw", 2, 0x0fea, X
, FP
|Modrm
, { RegMMX
|LLongMem
, RegMMX
, 0 } },
995 {"pminub", 2, 0x0fda, X
, FP
|Modrm
, { RegMMX
|LLongMem
, RegMMX
, 0 } },
996 {"pmovmskb", 2, 0x0fd7, X
, FP
|Modrm
, { RegMMX
, Reg32
|InvMem
, 0 } },
997 {"pmulhuw", 2, 0x0fe4, X
, FP
|Modrm
, { RegMMX
|LLongMem
, RegMMX
, 0 } },
998 {"prefetchnta", 1, 0x0f18, 0, FP
|Modrm
, { LLongMem
, 0, 0 } },
999 {"prefetcht0", 1, 0x0f18, 1, FP
|Modrm
, { LLongMem
, 0, 0 } },
1000 {"prefetcht1", 1, 0x0f18, 2, FP
|Modrm
, { LLongMem
, 0, 0 } },
1001 {"prefetcht2", 1, 0x0f18, 3, FP
|Modrm
, { LLongMem
, 0, 0 } },
1002 {"psadbw", 2, 0x0ff6, X
, FP
|Modrm
, { RegMMX
|LLongMem
, RegMMX
, 0 } },
1003 {"pshufw", 3, 0x0f70, X
, FP
|Modrm
, { Imm8
, RegMMX
|LLongMem
, RegMMX
} },
1004 {"rcpps", 2, 0x0f53, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
1005 {"rcpss", 2, 0xf30f53, X
, FP
|Modrm
, { RegXMM
|WordMem
, RegXMM
, 0 } },
1006 {"rsqrtps", 2, 0x0f52, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
1007 {"rsqrtss", 2, 0xf30f52, X
, FP
|Modrm
, { RegXMM
|WordMem
, RegXMM
, 0 } },
1008 {"sfence", 0, 0x0faef8, X
, FP
, { 0, 0, 0 } },
1009 {"shufps", 3, 0x0fc6, X
, FP
|Modrm
, { Imm8
, RegXMM
|LLongMem
, RegXMM
} },
1010 {"sqrtps", 2, 0x0f51, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
1011 {"sqrtss", 2, 0xf30f51, X
, FP
|Modrm
, { RegXMM
|WordMem
, RegXMM
, 0 } },
1012 {"stmxcsr", 1, 0x0fae, 3, FP
|Modrm
, { WordMem
, 0, 0 } },
1013 {"subps", 2, 0x0f5c, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
1014 {"subss", 2, 0xf30f5c, X
, FP
|Modrm
, { RegXMM
|WordMem
, RegXMM
, 0 } },
1015 {"ucomiss", 2, 0x0f2e, X
, FP
|Modrm
, { RegXMM
|WordMem
, RegXMM
, 0 } },
1016 {"unpckhps", 2, 0x0f15, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
1017 {"unpcklps", 2, 0x0f14, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
1018 {"xorps", 2, 0x0f57, X
, FP
|Modrm
, { RegXMM
|LLongMem
, RegXMM
, 0 } },
1020 /* AMD 3DNow! instructions. */
1022 {"prefetch", 1, 0x0f0d, 0, FP
|Modrm
, { ByteMem
, 0, 0 } },
1023 {"prefetchw",1, 0x0f0d, 1, FP
|Modrm
, { ByteMem
, 0, 0 } },
1024 {"femms", 0, 0x0f0e, X
, FP
, { 0, 0, 0 } },
1025 {"pavgusb", 2, 0x0f0f, 0xbf, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1026 {"pf2id", 2, 0x0f0f, 0x1d, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1027 {"pf2iw", 2, 0x0f0f, 0x1c, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } }, /* Athlon */
1028 {"pfacc", 2, 0x0f0f, 0xae, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1029 {"pfadd", 2, 0x0f0f, 0x9e, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1030 {"pfcmpeq", 2, 0x0f0f, 0xb0, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1031 {"pfcmpge", 2, 0x0f0f, 0x90, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1032 {"pfcmpgt", 2, 0x0f0f, 0xa0, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1033 {"pfmax", 2, 0x0f0f, 0xa4, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1034 {"pfmin", 2, 0x0f0f, 0x94, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1035 {"pfmul", 2, 0x0f0f, 0xb4, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1036 {"pfnacc", 2, 0x0f0f, 0x8a, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } }, /* Athlon */
1037 {"pfpnacc", 2, 0x0f0f, 0x8e, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } }, /* Athlon */
1038 {"pfrcp", 2, 0x0f0f, 0x96, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1039 {"pfrcpit1", 2, 0x0f0f, 0xa6, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1040 {"pfrcpit2", 2, 0x0f0f, 0xb6, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1041 {"pfrsqit1", 2, 0x0f0f, 0xa7, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1042 {"pfrsqrt", 2, 0x0f0f, 0x97, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1043 {"pfsub", 2, 0x0f0f, 0x9a, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1044 {"pfsubr", 2, 0x0f0f, 0xaa, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1045 {"pi2fd", 2, 0x0f0f, 0x0d, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1046 {"pi2fw", 2, 0x0f0f, 0x0c, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } }, /* Athlon */
1047 {"pmulhrw", 2, 0x0f0f, 0xb7, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } },
1048 {"pswapd", 2, 0x0f0f, 0xbb, FP
|Modrm
|ImmExt
, { RegMMX
|LongMem
, RegMMX
, 0 } }, /* Athlon */
1050 {NULL
, 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
1075 #define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */
1078 /* 386 register table. */
1080 static const reg_entry i386_regtab
[] = {
1081 /* make %st first as we test for it */
1082 {"st", FloatReg
|FloatAcc
, 0},
1084 {"al", Reg8
|Acc
, 0},
1085 {"cl", Reg8
|ShiftCount
, 1},
1093 {"ax", Reg16
|Acc
, 0},
1095 {"dx", Reg16
|InOutPortReg
, 2},
1096 {"bx", Reg16
|BaseIndex
, 3},
1098 {"bp", Reg16
|BaseIndex
, 5},
1099 {"si", Reg16
|BaseIndex
, 6},
1100 {"di", Reg16
|BaseIndex
, 7},
1102 {"eax", Reg32
|BaseIndex
|Acc
, 0},
1103 {"ecx", Reg32
|BaseIndex
, 1},
1104 {"edx", Reg32
|BaseIndex
, 2},
1105 {"ebx", Reg32
|BaseIndex
, 3},
1107 {"ebp", Reg32
|BaseIndex
, 5},
1108 {"esi", Reg32
|BaseIndex
, 6},
1109 {"edi", Reg32
|BaseIndex
, 7},
1110 /* segment registers */
1117 /* control registers */
1118 {"cr0", Control
, 0},
1119 {"cr1", Control
, 1},
1120 {"cr2", Control
, 2},
1121 {"cr3", Control
, 3},
1122 {"cr4", Control
, 4},
1123 {"cr5", Control
, 5},
1124 {"cr6", Control
, 6},
1125 {"cr7", Control
, 7},
1126 /* debug registers */
1143 /* test registers */
1152 /* mmx and simd registers */
1161 {"xmm0", RegXMM
, 0},
1162 {"xmm1", RegXMM
, 1},
1163 {"xmm2", RegXMM
, 2},
1164 {"xmm3", RegXMM
, 3},
1165 {"xmm4", RegXMM
, 4},
1166 {"xmm5", RegXMM
, 5},
1167 {"xmm6", RegXMM
, 6},
1171 static const reg_entry i386_float_regtab
[] = {
1172 {"st(0)", FloatReg
|FloatAcc
, 0},
1173 {"st(1)", FloatReg
, 1},
1174 {"st(2)", FloatReg
, 2},
1175 {"st(3)", FloatReg
, 3},
1176 {"st(4)", FloatReg
, 4},
1177 {"st(5)", FloatReg
, 5},
1178 {"st(6)", FloatReg
, 6},
1179 {"st(7)", FloatReg
, 7}
1182 #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
1185 static const seg_entry cs
= { "cs", 0x2e };
1186 static const seg_entry ds
= { "ds", 0x3e };
1187 static const seg_entry ss
= { "ss", 0x36 };
1188 static const seg_entry es
= { "es", 0x26 };
1189 static const seg_entry fs
= { "fs", 0x64 };
1190 static const seg_entry gs
= { "gs", 0x65 };
1192 /* end of opcode/i386.h */