1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
; /* arch string length */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags flags
; /* cpu feature flags */
134 unsigned int skip
; /* show_arch should skip this. */
135 unsigned int negated
; /* turn off indicated flags. */
139 static void update_code_flag (int, int);
140 static void set_code_flag (int);
141 static void set_16bit_gcc_code_flag (int);
142 static void set_intel_syntax (int);
143 static void set_intel_mnemonic (int);
144 static void set_allow_index_reg (int);
145 static void set_sse_check (int);
146 static void set_cpu_arch (int);
148 static void pe_directive_secrel (int);
150 static void signed_cons (int);
151 static char *output_invalid (int c
);
152 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
154 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
156 static int i386_att_operand (char *);
157 static int i386_intel_operand (char *, int);
158 static int i386_intel_simplify (expressionS
*);
159 static int i386_intel_parse_name (const char *, expressionS
*);
160 static const reg_entry
*parse_register (char *, char **);
161 static char *parse_insn (char *, char *);
162 static char *parse_operands (char *, const char *);
163 static void swap_operands (void);
164 static void swap_2_operands (int, int);
165 static void optimize_imm (void);
166 static void optimize_disp (void);
167 static const insn_template
*match_template (void);
168 static int check_string (void);
169 static int process_suffix (void);
170 static int check_byte_reg (void);
171 static int check_long_reg (void);
172 static int check_qword_reg (void);
173 static int check_word_reg (void);
174 static int finalize_imm (void);
175 static int process_operands (void);
176 static const seg_entry
*build_modrm_byte (void);
177 static void output_insn (void);
178 static void output_imm (fragS
*, offsetT
);
179 static void output_disp (fragS
*, offsetT
);
181 static void s_bss (int);
183 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
187 static const char *default_arch
= DEFAULT_ARCH
;
192 /* VEX prefix is either 2 byte or 3 byte. */
193 unsigned char bytes
[3];
195 /* Destination or source register specifier. */
196 const reg_entry
*register_specifier
;
199 /* 'md_assemble ()' gathers together information and puts it into a
206 const reg_entry
*regs
;
211 operand_size_mismatch
,
212 operand_type_mismatch
,
213 register_type_mismatch
,
214 number_of_operands_mismatch
,
215 invalid_instruction_suffix
,
218 unsupported_with_intel_mnemonic
,
225 /* TM holds the template for the insn were currently assembling. */
228 /* SUFFIX holds the instruction size suffix for byte, word, dword
229 or qword, if given. */
232 /* OPERANDS gives the number of given operands. */
233 unsigned int operands
;
235 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
236 of given register, displacement, memory operands and immediate
238 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
240 /* TYPES [i] is the type (see above #defines) which tells us how to
241 use OP[i] for the corresponding operand. */
242 i386_operand_type types
[MAX_OPERANDS
];
244 /* Displacement expression, immediate expression, or register for each
246 union i386_op op
[MAX_OPERANDS
];
248 /* Flags for operands. */
249 unsigned int flags
[MAX_OPERANDS
];
250 #define Operand_PCrel 1
252 /* Relocation type for operand */
253 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
255 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
256 the base index byte below. */
257 const reg_entry
*base_reg
;
258 const reg_entry
*index_reg
;
259 unsigned int log2_scale_factor
;
261 /* SEG gives the seg_entries of this insn. They are zero unless
262 explicit segment overrides are given. */
263 const seg_entry
*seg
[2];
265 /* PREFIX holds all the given prefix opcodes (usually null).
266 PREFIXES is the number of prefix opcodes. */
267 unsigned int prefixes
;
268 unsigned char prefix
[MAX_PREFIXES
];
270 /* RM and SIB are the modrm byte and the sib byte where the
271 addressing modes of this insn are encoded. */
277 /* Swap operand in encoding. */
278 unsigned int swap_operand
;
280 /* Force 32bit displacement in encoding. */
281 unsigned int disp32_encoding
;
284 enum i386_error error
;
287 typedef struct _i386_insn i386_insn
;
289 /* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
291 const char extra_symbol_chars
[] = "*%-(["
300 #if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
302 && !defined (TE_GNU) \
303 && !defined (TE_LINUX) \
304 && !defined (TE_NETWARE) \
305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
307 /* This array holds the chars that always start a comment. If the
308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310 const char *i386_comment_chars
= "#/";
311 #define SVR4_COMMENT_CHARS 1
312 #define PREFIX_SEPARATOR '\\'
315 const char *i386_comment_chars
= "#";
316 #define PREFIX_SEPARATOR '/'
319 /* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
323 first line of the input file. This is because the compiler outputs
324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
326 '/' isn't otherwise defined. */
327 const char line_comment_chars
[] = "#/";
329 const char line_separator_chars
[] = ";";
331 /* Chars that can be used to separate mant from exp in floating point
333 const char EXP_CHARS
[] = "eE";
335 /* Chars that mean this number is a floating point constant
338 const char FLT_CHARS
[] = "fFdDxX";
340 /* Tables for lexical analysis. */
341 static char mnemonic_chars
[256];
342 static char register_chars
[256];
343 static char operand_chars
[256];
344 static char identifier_chars
[256];
345 static char digit_chars
[256];
347 /* Lexical macros. */
348 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349 #define is_operand_char(x) (operand_chars[(unsigned char) x])
350 #define is_register_char(x) (register_chars[(unsigned char) x])
351 #define is_space_char(x) ((x) == ' ')
352 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353 #define is_digit_char(x) (digit_chars[(unsigned char) x])
355 /* All non-digit non-letter characters that may occur in an operand. */
356 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
358 /* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
361 assembler instruction). */
362 static char save_stack
[32];
363 static char *save_stack_p
;
364 #define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366 #define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
369 /* The instruction we're assembling. */
372 /* Possible templates for current insn. */
373 static const templates
*current_templates
;
375 /* Per instruction expressionS buffers: max displacements & immediates. */
376 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
377 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
379 /* Current operand we are working on. */
380 static int this_operand
= -1;
382 /* We support four different modes. FLAG_CODE variable is used to distinguish
390 static enum flag_code flag_code
;
391 static unsigned int object_64bit
;
392 static int use_rela_relocations
= 0;
394 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
395 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
396 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
398 /* The ELF ABI to use. */
406 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
409 /* The names used to print error messages. */
410 static const char *flag_code_names
[] =
417 /* 1 for intel syntax,
419 static int intel_syntax
= 0;
421 /* 1 for intel mnemonic,
422 0 if att mnemonic. */
423 static int intel_mnemonic
= !SYSV386_COMPAT
;
425 /* 1 if support old (<= 2.8.1) versions of gcc. */
426 static int old_gcc
= OLDGCC_COMPAT
;
428 /* 1 if pseudo registers are permitted. */
429 static int allow_pseudo_reg
= 0;
431 /* 1 if register prefix % not required. */
432 static int allow_naked_reg
= 0;
434 /* 1 if pseudo index register, eiz/riz, is allowed . */
435 static int allow_index_reg
= 0;
445 /* Register prefix used for error message. */
446 static const char *register_prefix
= "%";
448 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
449 leave, push, and pop instructions so that gcc has the same stack
450 frame as in 32 bit mode. */
451 static char stackop_size
= '\0';
453 /* Non-zero to optimize code alignment. */
454 int optimize_align_code
= 1;
456 /* Non-zero to quieten some warnings. */
457 static int quiet_warnings
= 0;
460 static const char *cpu_arch_name
= NULL
;
461 static char *cpu_sub_arch_name
= NULL
;
463 /* CPU feature flags. */
464 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
466 /* If we have selected a cpu we are generating instructions for. */
467 static int cpu_arch_tune_set
= 0;
469 /* Cpu we are generating instructions for. */
470 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
472 /* CPU feature flags of cpu we are generating instructions for. */
473 static i386_cpu_flags cpu_arch_tune_flags
;
475 /* CPU instruction set architecture used. */
476 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
478 /* CPU feature flags of instruction set architecture used. */
479 i386_cpu_flags cpu_arch_isa_flags
;
481 /* If set, conditional jumps are not automatically promoted to handle
482 larger than a byte offset. */
483 static unsigned int no_cond_jump_promotion
= 0;
485 /* Encode SSE instructions with VEX prefix. */
486 static unsigned int sse2avx
;
488 /* Encode scalar AVX instructions with specific vector length. */
495 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
496 static symbolS
*GOT_symbol
;
498 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
499 unsigned int x86_dwarf2_return_column
;
501 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
502 int x86_cie_data_alignment
;
504 /* Interface to relax_segment.
505 There are 3 major relax states for 386 jump insns because the
506 different types of jumps add different sizes to frags when we're
507 figuring out what sort of jump to choose to reach a given label. */
510 #define UNCOND_JUMP 0
512 #define COND_JUMP86 2
517 #define SMALL16 (SMALL | CODE16)
519 #define BIG16 (BIG | CODE16)
523 #define INLINE __inline__
529 #define ENCODE_RELAX_STATE(type, size) \
530 ((relax_substateT) (((type) << 2) | (size)))
531 #define TYPE_FROM_RELAX_STATE(s) \
533 #define DISP_SIZE_FROM_RELAX_STATE(s) \
534 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
536 /* This table is used by relax_frag to promote short jumps to long
537 ones where necessary. SMALL (short) jumps may be promoted to BIG
538 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
539 don't allow a short jump in a 32 bit code segment to be promoted to
540 a 16 bit offset jump because it's slower (requires data size
541 prefix), and doesn't work, unless the destination is in the bottom
542 64k of the code segment (The top 16 bits of eip are zeroed). */
544 const relax_typeS md_relax_table
[] =
547 1) most positive reach of this state,
548 2) most negative reach of this state,
549 3) how many bytes this mode will have in the variable part of the frag
550 4) which index into the table to try if we can't fit into this one. */
552 /* UNCOND_JUMP states. */
553 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
554 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
555 /* dword jmp adds 4 bytes to frag:
556 0 extra opcode bytes, 4 displacement bytes. */
558 /* word jmp adds 2 byte2 to frag:
559 0 extra opcode bytes, 2 displacement bytes. */
562 /* COND_JUMP states. */
563 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
564 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
565 /* dword conditionals adds 5 bytes to frag:
566 1 extra opcode byte, 4 displacement bytes. */
568 /* word conditionals add 3 bytes to frag:
569 1 extra opcode byte, 2 displacement bytes. */
572 /* COND_JUMP86 states. */
573 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
574 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
575 /* dword conditionals adds 5 bytes to frag:
576 1 extra opcode byte, 4 displacement bytes. */
578 /* word conditionals add 4 bytes to frag:
579 1 displacement byte and a 3 byte long branch insn. */
583 static const arch_entry cpu_arch
[] =
585 /* Do not replace the first two entries - i386_target_format()
586 relies on them being there in this order. */
587 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
588 CPU_GENERIC32_FLAGS
, 0, 0 },
589 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
590 CPU_GENERIC64_FLAGS
, 0, 0 },
591 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
592 CPU_NONE_FLAGS
, 0, 0 },
593 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
594 CPU_I186_FLAGS
, 0, 0 },
595 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
596 CPU_I286_FLAGS
, 0, 0 },
597 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
598 CPU_I386_FLAGS
, 0, 0 },
599 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
600 CPU_I486_FLAGS
, 0, 0 },
601 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
602 CPU_I586_FLAGS
, 0, 0 },
603 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
604 CPU_I686_FLAGS
, 0, 0 },
605 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
606 CPU_I586_FLAGS
, 0, 0 },
607 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
608 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
609 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
610 CPU_P2_FLAGS
, 0, 0 },
611 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
612 CPU_P3_FLAGS
, 0, 0 },
613 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
614 CPU_P4_FLAGS
, 0, 0 },
615 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
616 CPU_CORE_FLAGS
, 0, 0 },
617 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
618 CPU_NOCONA_FLAGS
, 0, 0 },
619 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
620 CPU_CORE_FLAGS
, 1, 0 },
621 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
622 CPU_CORE_FLAGS
, 0, 0 },
623 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
624 CPU_CORE2_FLAGS
, 1, 0 },
625 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
626 CPU_CORE2_FLAGS
, 0, 0 },
627 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
628 CPU_COREI7_FLAGS
, 0, 0 },
629 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
630 CPU_L1OM_FLAGS
, 0, 0 },
631 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
632 CPU_K6_FLAGS
, 0, 0 },
633 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
634 CPU_K6_2_FLAGS
, 0, 0 },
635 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
636 CPU_ATHLON_FLAGS
, 0, 0 },
637 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
638 CPU_K8_FLAGS
, 1, 0 },
639 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
640 CPU_K8_FLAGS
, 0, 0 },
641 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
642 CPU_K8_FLAGS
, 0, 0 },
643 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
644 CPU_AMDFAM10_FLAGS
, 0, 0 },
645 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1
,
646 CPU_BDVER1_FLAGS
, 0, 0 },
647 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
648 CPU_8087_FLAGS
, 0, 0 },
649 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
650 CPU_287_FLAGS
, 0, 0 },
651 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
652 CPU_387_FLAGS
, 0, 0 },
653 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
654 CPU_ANY87_FLAGS
, 0, 1 },
655 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
656 CPU_MMX_FLAGS
, 0, 0 },
657 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
658 CPU_3DNOWA_FLAGS
, 0, 1 },
659 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
660 CPU_SSE_FLAGS
, 0, 0 },
661 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
662 CPU_SSE2_FLAGS
, 0, 0 },
663 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
664 CPU_SSE3_FLAGS
, 0, 0 },
665 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
666 CPU_SSSE3_FLAGS
, 0, 0 },
667 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
668 CPU_SSE4_1_FLAGS
, 0, 0 },
669 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
670 CPU_SSE4_2_FLAGS
, 0, 0 },
671 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
672 CPU_SSE4_2_FLAGS
, 0, 0 },
673 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
674 CPU_ANY_SSE_FLAGS
, 0, 1 },
675 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
676 CPU_AVX_FLAGS
, 0, 0 },
677 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
678 CPU_ANY_AVX_FLAGS
, 0, 1 },
679 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
680 CPU_VMX_FLAGS
, 0, 0 },
681 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
682 CPU_SMX_FLAGS
, 0, 0 },
683 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
684 CPU_XSAVE_FLAGS
, 0, 0 },
685 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
686 CPU_XSAVEOPT_FLAGS
, 0, 0 },
687 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
688 CPU_AES_FLAGS
, 0, 0 },
689 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
690 CPU_PCLMUL_FLAGS
, 0, 0 },
691 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
692 CPU_PCLMUL_FLAGS
, 1, 0 },
693 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
694 CPU_FSGSBASE_FLAGS
, 0, 0 },
695 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
696 CPU_RDRND_FLAGS
, 0, 0 },
697 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
698 CPU_F16C_FLAGS
, 0, 0 },
699 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
700 CPU_FMA_FLAGS
, 0, 0 },
701 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
702 CPU_FMA4_FLAGS
, 0, 0 },
703 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
704 CPU_XOP_FLAGS
, 0, 0 },
705 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
706 CPU_LWP_FLAGS
, 0, 0 },
707 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
708 CPU_MOVBE_FLAGS
, 0, 0 },
709 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
710 CPU_EPT_FLAGS
, 0, 0 },
711 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
712 CPU_CLFLUSH_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
714 CPU_NOP_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
716 CPU_SYSCALL_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
718 CPU_RDTSCP_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
720 CPU_3DNOW_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
722 CPU_3DNOWA_FLAGS
, 0, 0 },
723 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
724 CPU_PADLOCK_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
726 CPU_SVME_FLAGS
, 1, 0 },
727 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
728 CPU_SVME_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
730 CPU_SSE4A_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
732 CPU_ABM_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
734 CPU_BMI_FLAGS
, 0, 0 },
738 /* Like s_lcomm_internal in gas/read.c but the alignment string
739 is allowed to be optional. */
742 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
749 && *input_line_pointer
== ',')
751 align
= parse_align (needs_align
- 1);
753 if (align
== (addressT
) -1)
768 bss_alloc (symbolP
, size
, align
);
773 pe_lcomm (int needs_align
)
775 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
779 const pseudo_typeS md_pseudo_table
[] =
781 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
782 {"align", s_align_bytes
, 0},
784 {"align", s_align_ptwo
, 0},
786 {"arch", set_cpu_arch
, 0},
790 {"lcomm", pe_lcomm
, 1},
792 {"ffloat", float_cons
, 'f'},
793 {"dfloat", float_cons
, 'd'},
794 {"tfloat", float_cons
, 'x'},
796 {"slong", signed_cons
, 4},
797 {"noopt", s_ignore
, 0},
798 {"optim", s_ignore
, 0},
799 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
800 {"code16", set_code_flag
, CODE_16BIT
},
801 {"code32", set_code_flag
, CODE_32BIT
},
802 {"code64", set_code_flag
, CODE_64BIT
},
803 {"intel_syntax", set_intel_syntax
, 1},
804 {"att_syntax", set_intel_syntax
, 0},
805 {"intel_mnemonic", set_intel_mnemonic
, 1},
806 {"att_mnemonic", set_intel_mnemonic
, 0},
807 {"allow_index_reg", set_allow_index_reg
, 1},
808 {"disallow_index_reg", set_allow_index_reg
, 0},
809 {"sse_check", set_sse_check
, 0},
810 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
811 {"largecomm", handle_large_common
, 0},
813 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
814 {"loc", dwarf2_directive_loc
, 0},
815 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
818 {"secrel32", pe_directive_secrel
, 0},
823 /* For interface with expression (). */
824 extern char *input_line_pointer
;
826 /* Hash table for instruction mnemonic lookup. */
827 static struct hash_control
*op_hash
;
829 /* Hash table for register lookup. */
830 static struct hash_control
*reg_hash
;
833 i386_align_code (fragS
*fragP
, int count
)
835 /* Various efficient no-op patterns for aligning code labels.
836 Note: Don't try to assemble the instructions in the comments.
837 0L and 0w are not legal. */
838 static const char f32_1
[] =
840 static const char f32_2
[] =
841 {0x66,0x90}; /* xchg %ax,%ax */
842 static const char f32_3
[] =
843 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
844 static const char f32_4
[] =
845 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
846 static const char f32_5
[] =
848 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
849 static const char f32_6
[] =
850 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
851 static const char f32_7
[] =
852 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
853 static const char f32_8
[] =
855 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
856 static const char f32_9
[] =
857 {0x89,0xf6, /* movl %esi,%esi */
858 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
859 static const char f32_10
[] =
860 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
861 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
862 static const char f32_11
[] =
863 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
864 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
865 static const char f32_12
[] =
866 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
867 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
868 static const char f32_13
[] =
869 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
870 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
871 static const char f32_14
[] =
872 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
873 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
874 static const char f16_3
[] =
875 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
876 static const char f16_4
[] =
877 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
878 static const char f16_5
[] =
880 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
881 static const char f16_6
[] =
882 {0x89,0xf6, /* mov %si,%si */
883 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
884 static const char f16_7
[] =
885 {0x8d,0x74,0x00, /* lea 0(%si),%si */
886 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
887 static const char f16_8
[] =
888 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
889 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
890 static const char jump_31
[] =
891 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
892 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
893 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
894 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
895 static const char *const f32_patt
[] = {
896 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
897 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
899 static const char *const f16_patt
[] = {
900 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
903 static const char alt_3
[] =
905 /* nopl 0(%[re]ax) */
906 static const char alt_4
[] =
907 {0x0f,0x1f,0x40,0x00};
908 /* nopl 0(%[re]ax,%[re]ax,1) */
909 static const char alt_5
[] =
910 {0x0f,0x1f,0x44,0x00,0x00};
911 /* nopw 0(%[re]ax,%[re]ax,1) */
912 static const char alt_6
[] =
913 {0x66,0x0f,0x1f,0x44,0x00,0x00};
914 /* nopl 0L(%[re]ax) */
915 static const char alt_7
[] =
916 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
917 /* nopl 0L(%[re]ax,%[re]ax,1) */
918 static const char alt_8
[] =
919 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
920 /* nopw 0L(%[re]ax,%[re]ax,1) */
921 static const char alt_9
[] =
922 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
923 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
924 static const char alt_10
[] =
925 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
927 nopw %cs:0L(%[re]ax,%[re]ax,1) */
928 static const char alt_long_11
[] =
930 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
933 nopw %cs:0L(%[re]ax,%[re]ax,1) */
934 static const char alt_long_12
[] =
937 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
941 nopw %cs:0L(%[re]ax,%[re]ax,1) */
942 static const char alt_long_13
[] =
946 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
951 nopw %cs:0L(%[re]ax,%[re]ax,1) */
952 static const char alt_long_14
[] =
957 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
963 nopw %cs:0L(%[re]ax,%[re]ax,1) */
964 static const char alt_long_15
[] =
970 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
971 /* nopl 0(%[re]ax,%[re]ax,1)
972 nopw 0(%[re]ax,%[re]ax,1) */
973 static const char alt_short_11
[] =
974 {0x0f,0x1f,0x44,0x00,0x00,
975 0x66,0x0f,0x1f,0x44,0x00,0x00};
976 /* nopw 0(%[re]ax,%[re]ax,1)
977 nopw 0(%[re]ax,%[re]ax,1) */
978 static const char alt_short_12
[] =
979 {0x66,0x0f,0x1f,0x44,0x00,0x00,
980 0x66,0x0f,0x1f,0x44,0x00,0x00};
981 /* nopw 0(%[re]ax,%[re]ax,1)
983 static const char alt_short_13
[] =
984 {0x66,0x0f,0x1f,0x44,0x00,0x00,
985 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
988 static const char alt_short_14
[] =
989 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
990 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
992 nopl 0L(%[re]ax,%[re]ax,1) */
993 static const char alt_short_15
[] =
994 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
995 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
996 static const char *const alt_short_patt
[] = {
997 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
998 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
999 alt_short_14
, alt_short_15
1001 static const char *const alt_long_patt
[] = {
1002 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1003 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1004 alt_long_14
, alt_long_15
1007 /* Only align for at least a positive non-zero boundary. */
1008 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1011 /* We need to decide which NOP sequence to use for 32bit and
1012 64bit. When -mtune= is used:
1014 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1015 PROCESSOR_GENERIC32, f32_patt will be used.
1016 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1017 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1018 PROCESSOR_GENERIC64, alt_long_patt will be used.
1019 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1020 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
1023 When -mtune= isn't used, alt_long_patt will be used if
1024 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1027 When -march= or .arch is used, we can't use anything beyond
1028 cpu_arch_isa_flags. */
1030 if (flag_code
== CODE_16BIT
)
1034 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1036 /* Adjust jump offset. */
1037 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1040 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1041 f16_patt
[count
- 1], count
);
1045 const char *const *patt
= NULL
;
1047 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1049 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1050 switch (cpu_arch_tune
)
1052 case PROCESSOR_UNKNOWN
:
1053 /* We use cpu_arch_isa_flags to check if we SHOULD
1054 optimize with nops. */
1055 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1056 patt
= alt_long_patt
;
1060 case PROCESSOR_PENTIUMPRO
:
1061 case PROCESSOR_PENTIUM4
:
1062 case PROCESSOR_NOCONA
:
1063 case PROCESSOR_CORE
:
1064 case PROCESSOR_CORE2
:
1065 case PROCESSOR_COREI7
:
1066 case PROCESSOR_L1OM
:
1067 case PROCESSOR_GENERIC64
:
1068 patt
= alt_long_patt
;
1071 case PROCESSOR_ATHLON
:
1073 case PROCESSOR_AMDFAM10
:
1074 case PROCESSOR_BDVER1
:
1075 patt
= alt_short_patt
;
1077 case PROCESSOR_I386
:
1078 case PROCESSOR_I486
:
1079 case PROCESSOR_PENTIUM
:
1080 case PROCESSOR_GENERIC32
:
1087 switch (fragP
->tc_frag_data
.tune
)
1089 case PROCESSOR_UNKNOWN
:
1090 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1091 PROCESSOR_UNKNOWN. */
1095 case PROCESSOR_I386
:
1096 case PROCESSOR_I486
:
1097 case PROCESSOR_PENTIUM
:
1099 case PROCESSOR_ATHLON
:
1101 case PROCESSOR_AMDFAM10
:
1102 case PROCESSOR_BDVER1
:
1103 case PROCESSOR_GENERIC32
:
1104 /* We use cpu_arch_isa_flags to check if we CAN optimize
1106 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1107 patt
= alt_short_patt
;
1111 case PROCESSOR_PENTIUMPRO
:
1112 case PROCESSOR_PENTIUM4
:
1113 case PROCESSOR_NOCONA
:
1114 case PROCESSOR_CORE
:
1115 case PROCESSOR_CORE2
:
1116 case PROCESSOR_COREI7
:
1117 case PROCESSOR_L1OM
:
1118 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1119 patt
= alt_long_patt
;
1123 case PROCESSOR_GENERIC64
:
1124 patt
= alt_long_patt
;
1129 if (patt
== f32_patt
)
1131 /* If the padding is less than 15 bytes, we use the normal
1132 ones. Otherwise, we use a jump instruction and adjust
1136 /* For 64bit, the limit is 3 bytes. */
1137 if (flag_code
== CODE_64BIT
1138 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1143 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1144 patt
[count
- 1], count
);
1147 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1149 /* Adjust jump offset. */
1150 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1155 /* Maximum length of an instruction is 15 byte. If the
1156 padding is greater than 15 bytes and we don't use jump,
1157 we have to break it into smaller pieces. */
1158 int padding
= count
;
1159 while (padding
> 15)
1162 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1167 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1168 patt
[padding
- 1], padding
);
1171 fragP
->fr_var
= count
;
1175 operand_type_all_zero (const union i386_operand_type
*x
)
1177 switch (ARRAY_SIZE(x
->array
))
1186 return !x
->array
[0];
1193 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1195 switch (ARRAY_SIZE(x
->array
))
1210 operand_type_equal (const union i386_operand_type
*x
,
1211 const union i386_operand_type
*y
)
1213 switch (ARRAY_SIZE(x
->array
))
1216 if (x
->array
[2] != y
->array
[2])
1219 if (x
->array
[1] != y
->array
[1])
1222 return x
->array
[0] == y
->array
[0];
1230 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1232 switch (ARRAY_SIZE(x
->array
))
1241 return !x
->array
[0];
1248 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1250 switch (ARRAY_SIZE(x
->array
))
1265 cpu_flags_equal (const union i386_cpu_flags
*x
,
1266 const union i386_cpu_flags
*y
)
1268 switch (ARRAY_SIZE(x
->array
))
1271 if (x
->array
[2] != y
->array
[2])
1274 if (x
->array
[1] != y
->array
[1])
1277 return x
->array
[0] == y
->array
[0];
1285 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1287 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1288 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1291 static INLINE i386_cpu_flags
1292 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1294 switch (ARRAY_SIZE (x
.array
))
1297 x
.array
[2] &= y
.array
[2];
1299 x
.array
[1] &= y
.array
[1];
1301 x
.array
[0] &= y
.array
[0];
1309 static INLINE i386_cpu_flags
1310 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1312 switch (ARRAY_SIZE (x
.array
))
1315 x
.array
[2] |= y
.array
[2];
1317 x
.array
[1] |= y
.array
[1];
1319 x
.array
[0] |= y
.array
[0];
1327 static INLINE i386_cpu_flags
1328 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1330 switch (ARRAY_SIZE (x
.array
))
1333 x
.array
[2] &= ~y
.array
[2];
1335 x
.array
[1] &= ~y
.array
[1];
1337 x
.array
[0] &= ~y
.array
[0];
1345 #define CPU_FLAGS_ARCH_MATCH 0x1
1346 #define CPU_FLAGS_64BIT_MATCH 0x2
1347 #define CPU_FLAGS_AES_MATCH 0x4
1348 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1349 #define CPU_FLAGS_AVX_MATCH 0x10
1351 #define CPU_FLAGS_32BIT_MATCH \
1352 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1353 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1354 #define CPU_FLAGS_PERFECT_MATCH \
1355 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1357 /* Return CPU flags match bits. */
1360 cpu_flags_match (const insn_template
*t
)
1362 i386_cpu_flags x
= t
->cpu_flags
;
1363 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1365 x
.bitfield
.cpu64
= 0;
1366 x
.bitfield
.cpuno64
= 0;
1368 if (cpu_flags_all_zero (&x
))
1370 /* This instruction is available on all archs. */
1371 match
|= CPU_FLAGS_32BIT_MATCH
;
1375 /* This instruction is available only on some archs. */
1376 i386_cpu_flags cpu
= cpu_arch_flags
;
1378 cpu
.bitfield
.cpu64
= 0;
1379 cpu
.bitfield
.cpuno64
= 0;
1380 cpu
= cpu_flags_and (x
, cpu
);
1381 if (!cpu_flags_all_zero (&cpu
))
1383 if (x
.bitfield
.cpuavx
)
1385 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1386 if (cpu
.bitfield
.cpuavx
)
1388 /* Check SSE2AVX. */
1389 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1391 match
|= (CPU_FLAGS_ARCH_MATCH
1392 | CPU_FLAGS_AVX_MATCH
);
1394 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1395 match
|= CPU_FLAGS_AES_MATCH
;
1397 if (!x
.bitfield
.cpupclmul
1398 || cpu
.bitfield
.cpupclmul
)
1399 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1403 match
|= CPU_FLAGS_ARCH_MATCH
;
1406 match
|= CPU_FLAGS_32BIT_MATCH
;
1412 static INLINE i386_operand_type
1413 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1415 switch (ARRAY_SIZE (x
.array
))
1418 x
.array
[2] &= y
.array
[2];
1420 x
.array
[1] &= y
.array
[1];
1422 x
.array
[0] &= y
.array
[0];
1430 static INLINE i386_operand_type
1431 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1433 switch (ARRAY_SIZE (x
.array
))
1436 x
.array
[2] |= y
.array
[2];
1438 x
.array
[1] |= y
.array
[1];
1440 x
.array
[0] |= y
.array
[0];
1448 static INLINE i386_operand_type
1449 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1451 switch (ARRAY_SIZE (x
.array
))
1454 x
.array
[2] ^= y
.array
[2];
1456 x
.array
[1] ^= y
.array
[1];
1458 x
.array
[0] ^= y
.array
[0];
1466 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1467 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1468 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1469 static const i386_operand_type inoutportreg
1470 = OPERAND_TYPE_INOUTPORTREG
;
1471 static const i386_operand_type reg16_inoutportreg
1472 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1473 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1474 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1475 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1476 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1477 static const i386_operand_type anydisp
1478 = OPERAND_TYPE_ANYDISP
;
1479 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1480 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1481 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1482 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1483 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1484 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1485 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1486 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1487 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1488 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1489 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1490 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1501 operand_type_check (i386_operand_type t
, enum operand_type c
)
1506 return (t
.bitfield
.reg8
1509 || t
.bitfield
.reg64
);
1512 return (t
.bitfield
.imm8
1516 || t
.bitfield
.imm32s
1517 || t
.bitfield
.imm64
);
1520 return (t
.bitfield
.disp8
1521 || t
.bitfield
.disp16
1522 || t
.bitfield
.disp32
1523 || t
.bitfield
.disp32s
1524 || t
.bitfield
.disp64
);
1527 return (t
.bitfield
.disp8
1528 || t
.bitfield
.disp16
1529 || t
.bitfield
.disp32
1530 || t
.bitfield
.disp32s
1531 || t
.bitfield
.disp64
1532 || t
.bitfield
.baseindex
);
1541 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1542 operand J for instruction template T. */
1545 match_reg_size (const insn_template
*t
, unsigned int j
)
1547 return !((i
.types
[j
].bitfield
.byte
1548 && !t
->operand_types
[j
].bitfield
.byte
)
1549 || (i
.types
[j
].bitfield
.word
1550 && !t
->operand_types
[j
].bitfield
.word
)
1551 || (i
.types
[j
].bitfield
.dword
1552 && !t
->operand_types
[j
].bitfield
.dword
)
1553 || (i
.types
[j
].bitfield
.qword
1554 && !t
->operand_types
[j
].bitfield
.qword
));
1557 /* Return 1 if there is no conflict in any size on operand J for
1558 instruction template T. */
1561 match_mem_size (const insn_template
*t
, unsigned int j
)
1563 return (match_reg_size (t
, j
)
1564 && !((i
.types
[j
].bitfield
.unspecified
1565 && !t
->operand_types
[j
].bitfield
.unspecified
)
1566 || (i
.types
[j
].bitfield
.fword
1567 && !t
->operand_types
[j
].bitfield
.fword
)
1568 || (i
.types
[j
].bitfield
.tbyte
1569 && !t
->operand_types
[j
].bitfield
.tbyte
)
1570 || (i
.types
[j
].bitfield
.xmmword
1571 && !t
->operand_types
[j
].bitfield
.xmmword
)
1572 || (i
.types
[j
].bitfield
.ymmword
1573 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1576 /* Return 1 if there is no size conflict on any operands for
1577 instruction template T. */
1580 operand_size_match (const insn_template
*t
)
1585 /* Don't check jump instructions. */
1586 if (t
->opcode_modifier
.jump
1587 || t
->opcode_modifier
.jumpbyte
1588 || t
->opcode_modifier
.jumpdword
1589 || t
->opcode_modifier
.jumpintersegment
)
1592 /* Check memory and accumulator operand size. */
1593 for (j
= 0; j
< i
.operands
; j
++)
1595 if (t
->operand_types
[j
].bitfield
.anysize
)
1598 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1604 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1613 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1616 i
.error
= operand_size_mismatch
;
1620 /* Check reverse. */
1621 gas_assert (i
.operands
== 2);
1624 for (j
= 0; j
< 2; j
++)
1626 if (t
->operand_types
[j
].bitfield
.acc
1627 && !match_reg_size (t
, j
? 0 : 1))
1630 if (i
.types
[j
].bitfield
.mem
1631 && !match_mem_size (t
, j
? 0 : 1))
1639 operand_type_match (i386_operand_type overlap
,
1640 i386_operand_type given
)
1642 i386_operand_type temp
= overlap
;
1644 temp
.bitfield
.jumpabsolute
= 0;
1645 temp
.bitfield
.unspecified
= 0;
1646 temp
.bitfield
.byte
= 0;
1647 temp
.bitfield
.word
= 0;
1648 temp
.bitfield
.dword
= 0;
1649 temp
.bitfield
.fword
= 0;
1650 temp
.bitfield
.qword
= 0;
1651 temp
.bitfield
.tbyte
= 0;
1652 temp
.bitfield
.xmmword
= 0;
1653 temp
.bitfield
.ymmword
= 0;
1654 if (operand_type_all_zero (&temp
))
1657 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1658 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1662 i
.error
= operand_type_mismatch
;
1666 /* If given types g0 and g1 are registers they must be of the same type
1667 unless the expected operand type register overlap is null.
1668 Note that Acc in a template matches every size of reg. */
1671 operand_type_register_match (i386_operand_type m0
,
1672 i386_operand_type g0
,
1673 i386_operand_type t0
,
1674 i386_operand_type m1
,
1675 i386_operand_type g1
,
1676 i386_operand_type t1
)
1678 if (!operand_type_check (g0
, reg
))
1681 if (!operand_type_check (g1
, reg
))
1684 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1685 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1686 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1687 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1690 if (m0
.bitfield
.acc
)
1692 t0
.bitfield
.reg8
= 1;
1693 t0
.bitfield
.reg16
= 1;
1694 t0
.bitfield
.reg32
= 1;
1695 t0
.bitfield
.reg64
= 1;
1698 if (m1
.bitfield
.acc
)
1700 t1
.bitfield
.reg8
= 1;
1701 t1
.bitfield
.reg16
= 1;
1702 t1
.bitfield
.reg32
= 1;
1703 t1
.bitfield
.reg64
= 1;
1706 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1707 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1708 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1709 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1712 i
.error
= register_type_mismatch
;
1717 static INLINE
unsigned int
1718 mode_from_disp_size (i386_operand_type t
)
1720 if (t
.bitfield
.disp8
)
1722 else if (t
.bitfield
.disp16
1723 || t
.bitfield
.disp32
1724 || t
.bitfield
.disp32s
)
1731 fits_in_signed_byte (offsetT num
)
1733 return (num
>= -128) && (num
<= 127);
1737 fits_in_unsigned_byte (offsetT num
)
1739 return (num
& 0xff) == num
;
1743 fits_in_unsigned_word (offsetT num
)
1745 return (num
& 0xffff) == num
;
1749 fits_in_signed_word (offsetT num
)
1751 return (-32768 <= num
) && (num
<= 32767);
1755 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1760 return (!(((offsetT
) -1 << 31) & num
)
1761 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1763 } /* fits_in_signed_long() */
1766 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1771 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1773 } /* fits_in_unsigned_long() */
1776 fits_in_imm4 (offsetT num
)
1778 return (num
& 0xf) == num
;
1781 static i386_operand_type
1782 smallest_imm_type (offsetT num
)
1784 i386_operand_type t
;
1786 operand_type_set (&t
, 0);
1787 t
.bitfield
.imm64
= 1;
1789 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1791 /* This code is disabled on the 486 because all the Imm1 forms
1792 in the opcode table are slower on the i486. They're the
1793 versions with the implicitly specified single-position
1794 displacement, which has another syntax if you really want to
1796 t
.bitfield
.imm1
= 1;
1797 t
.bitfield
.imm8
= 1;
1798 t
.bitfield
.imm8s
= 1;
1799 t
.bitfield
.imm16
= 1;
1800 t
.bitfield
.imm32
= 1;
1801 t
.bitfield
.imm32s
= 1;
1803 else if (fits_in_signed_byte (num
))
1805 t
.bitfield
.imm8
= 1;
1806 t
.bitfield
.imm8s
= 1;
1807 t
.bitfield
.imm16
= 1;
1808 t
.bitfield
.imm32
= 1;
1809 t
.bitfield
.imm32s
= 1;
1811 else if (fits_in_unsigned_byte (num
))
1813 t
.bitfield
.imm8
= 1;
1814 t
.bitfield
.imm16
= 1;
1815 t
.bitfield
.imm32
= 1;
1816 t
.bitfield
.imm32s
= 1;
1818 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1820 t
.bitfield
.imm16
= 1;
1821 t
.bitfield
.imm32
= 1;
1822 t
.bitfield
.imm32s
= 1;
1824 else if (fits_in_signed_long (num
))
1826 t
.bitfield
.imm32
= 1;
1827 t
.bitfield
.imm32s
= 1;
1829 else if (fits_in_unsigned_long (num
))
1830 t
.bitfield
.imm32
= 1;
1836 offset_in_range (offsetT val
, int size
)
1842 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1843 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1844 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1846 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1852 /* If BFD64, sign extend val for 32bit address mode. */
1853 if (flag_code
!= CODE_64BIT
1854 || i
.prefix
[ADDR_PREFIX
])
1855 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1856 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1859 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1861 char buf1
[40], buf2
[40];
1863 sprint_value (buf1
, val
);
1864 sprint_value (buf2
, val
& mask
);
1865 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1879 a. PREFIX_EXIST if attempting to add a prefix where one from the
1880 same class already exists.
1881 b. PREFIX_LOCK if lock prefix is added.
1882 c. PREFIX_REP if rep/repne prefix is added.
1883 d. PREFIX_OTHER if other prefix is added.
1886 static enum PREFIX_GROUP
1887 add_prefix (unsigned int prefix
)
1889 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1892 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1893 && flag_code
== CODE_64BIT
)
1895 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1896 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1897 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1908 case CS_PREFIX_OPCODE
:
1909 case DS_PREFIX_OPCODE
:
1910 case ES_PREFIX_OPCODE
:
1911 case FS_PREFIX_OPCODE
:
1912 case GS_PREFIX_OPCODE
:
1913 case SS_PREFIX_OPCODE
:
1917 case REPNE_PREFIX_OPCODE
:
1918 case REPE_PREFIX_OPCODE
:
1923 case LOCK_PREFIX_OPCODE
:
1932 case ADDR_PREFIX_OPCODE
:
1936 case DATA_PREFIX_OPCODE
:
1940 if (i
.prefix
[q
] != 0)
1948 i
.prefix
[q
] |= prefix
;
1951 as_bad (_("same type of prefix used twice"));
1957 update_code_flag (int value
, int check
)
1959 PRINTF_LIKE ((*as_error
));
1961 flag_code
= (enum flag_code
) value
;
1962 if (flag_code
== CODE_64BIT
)
1964 cpu_arch_flags
.bitfield
.cpu64
= 1;
1965 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1969 cpu_arch_flags
.bitfield
.cpu64
= 0;
1970 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1972 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1975 as_error
= as_fatal
;
1978 (*as_error
) (_("64bit mode not supported on `%s'."),
1979 cpu_arch_name
? cpu_arch_name
: default_arch
);
1981 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1984 as_error
= as_fatal
;
1987 (*as_error
) (_("32bit mode not supported on `%s'."),
1988 cpu_arch_name
? cpu_arch_name
: default_arch
);
1990 stackop_size
= '\0';
1994 set_code_flag (int value
)
1996 update_code_flag (value
, 0);
2000 set_16bit_gcc_code_flag (int new_code_flag
)
2002 flag_code
= (enum flag_code
) new_code_flag
;
2003 if (flag_code
!= CODE_16BIT
)
2005 cpu_arch_flags
.bitfield
.cpu64
= 0;
2006 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2007 stackop_size
= LONG_MNEM_SUFFIX
;
2011 set_intel_syntax (int syntax_flag
)
2013 /* Find out if register prefixing is specified. */
2014 int ask_naked_reg
= 0;
2017 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2019 char *string
= input_line_pointer
;
2020 int e
= get_symbol_end ();
2022 if (strcmp (string
, "prefix") == 0)
2024 else if (strcmp (string
, "noprefix") == 0)
2027 as_bad (_("bad argument to syntax directive."));
2028 *input_line_pointer
= e
;
2030 demand_empty_rest_of_line ();
2032 intel_syntax
= syntax_flag
;
2034 if (ask_naked_reg
== 0)
2035 allow_naked_reg
= (intel_syntax
2036 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2038 allow_naked_reg
= (ask_naked_reg
< 0);
2040 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2042 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2043 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2044 register_prefix
= allow_naked_reg
? "" : "%";
2048 set_intel_mnemonic (int mnemonic_flag
)
2050 intel_mnemonic
= mnemonic_flag
;
2054 set_allow_index_reg (int flag
)
2056 allow_index_reg
= flag
;
2060 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
2064 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2066 char *string
= input_line_pointer
;
2067 int e
= get_symbol_end ();
2069 if (strcmp (string
, "none") == 0)
2070 sse_check
= sse_check_none
;
2071 else if (strcmp (string
, "warning") == 0)
2072 sse_check
= sse_check_warning
;
2073 else if (strcmp (string
, "error") == 0)
2074 sse_check
= sse_check_error
;
2076 as_bad (_("bad argument to sse_check directive."));
2077 *input_line_pointer
= e
;
2080 as_bad (_("missing argument for sse_check directive"));
2082 demand_empty_rest_of_line ();
2086 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2087 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2089 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2090 static const char *arch
;
2092 /* Intel LIOM is only supported on ELF. */
2098 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2099 use default_arch. */
2100 arch
= cpu_arch_name
;
2102 arch
= default_arch
;
2105 /* If we are targeting Intel L1OM, we must enable it. */
2106 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2107 || new_flag
.bitfield
.cpul1om
)
2110 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2115 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2119 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2121 char *string
= input_line_pointer
;
2122 int e
= get_symbol_end ();
2124 i386_cpu_flags flags
;
2126 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2128 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2130 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2134 cpu_arch_name
= cpu_arch
[j
].name
;
2135 cpu_sub_arch_name
= NULL
;
2136 cpu_arch_flags
= cpu_arch
[j
].flags
;
2137 if (flag_code
== CODE_64BIT
)
2139 cpu_arch_flags
.bitfield
.cpu64
= 1;
2140 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2144 cpu_arch_flags
.bitfield
.cpu64
= 0;
2145 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2147 cpu_arch_isa
= cpu_arch
[j
].type
;
2148 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2149 if (!cpu_arch_tune_set
)
2151 cpu_arch_tune
= cpu_arch_isa
;
2152 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2157 if (!cpu_arch
[j
].negated
)
2158 flags
= cpu_flags_or (cpu_arch_flags
,
2161 flags
= cpu_flags_and_not (cpu_arch_flags
,
2163 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2165 if (cpu_sub_arch_name
)
2167 char *name
= cpu_sub_arch_name
;
2168 cpu_sub_arch_name
= concat (name
,
2170 (const char *) NULL
);
2174 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2175 cpu_arch_flags
= flags
;
2177 *input_line_pointer
= e
;
2178 demand_empty_rest_of_line ();
2182 if (j
>= ARRAY_SIZE (cpu_arch
))
2183 as_bad (_("no such architecture: `%s'"), string
);
2185 *input_line_pointer
= e
;
2188 as_bad (_("missing cpu architecture"));
2190 no_cond_jump_promotion
= 0;
2191 if (*input_line_pointer
== ','
2192 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2194 char *string
= ++input_line_pointer
;
2195 int e
= get_symbol_end ();
2197 if (strcmp (string
, "nojumps") == 0)
2198 no_cond_jump_promotion
= 1;
2199 else if (strcmp (string
, "jumps") == 0)
2202 as_bad (_("no such architecture modifier: `%s'"), string
);
2204 *input_line_pointer
= e
;
2207 demand_empty_rest_of_line ();
2210 enum bfd_architecture
2213 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2215 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2216 || flag_code
!= CODE_64BIT
)
2217 as_fatal (_("Intel L1OM is 64bit ELF only"));
2218 return bfd_arch_l1om
;
2221 return bfd_arch_i386
;
2227 if (!strncmp (default_arch
, "x86_64", 6))
2229 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2231 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2232 || default_arch
[6] != '\0')
2233 as_fatal (_("Intel L1OM is 64bit ELF only"));
2234 return bfd_mach_l1om
;
2236 else if (default_arch
[6] == '\0')
2237 return bfd_mach_x86_64
;
2239 return bfd_mach_x64_32
;
2241 else if (!strcmp (default_arch
, "i386"))
2242 return bfd_mach_i386_i386
;
2244 as_fatal (_("Unknown architecture"));
2250 const char *hash_err
;
2252 /* Initialize op_hash hash table. */
2253 op_hash
= hash_new ();
2256 const insn_template
*optab
;
2257 templates
*core_optab
;
2259 /* Setup for loop. */
2261 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2262 core_optab
->start
= optab
;
2267 if (optab
->name
== NULL
2268 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2270 /* different name --> ship out current template list;
2271 add to hash table; & begin anew. */
2272 core_optab
->end
= optab
;
2273 hash_err
= hash_insert (op_hash
,
2275 (void *) core_optab
);
2278 as_fatal (_("Internal Error: Can't hash %s: %s"),
2282 if (optab
->name
== NULL
)
2284 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2285 core_optab
->start
= optab
;
2290 /* Initialize reg_hash hash table. */
2291 reg_hash
= hash_new ();
2293 const reg_entry
*regtab
;
2294 unsigned int regtab_size
= i386_regtab_size
;
2296 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2298 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2300 as_fatal (_("Internal Error: Can't hash %s: %s"),
2306 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2311 for (c
= 0; c
< 256; c
++)
2316 mnemonic_chars
[c
] = c
;
2317 register_chars
[c
] = c
;
2318 operand_chars
[c
] = c
;
2320 else if (ISLOWER (c
))
2322 mnemonic_chars
[c
] = c
;
2323 register_chars
[c
] = c
;
2324 operand_chars
[c
] = c
;
2326 else if (ISUPPER (c
))
2328 mnemonic_chars
[c
] = TOLOWER (c
);
2329 register_chars
[c
] = mnemonic_chars
[c
];
2330 operand_chars
[c
] = c
;
2333 if (ISALPHA (c
) || ISDIGIT (c
))
2334 identifier_chars
[c
] = c
;
2337 identifier_chars
[c
] = c
;
2338 operand_chars
[c
] = c
;
2343 identifier_chars
['@'] = '@';
2346 identifier_chars
['?'] = '?';
2347 operand_chars
['?'] = '?';
2349 digit_chars
['-'] = '-';
2350 mnemonic_chars
['_'] = '_';
2351 mnemonic_chars
['-'] = '-';
2352 mnemonic_chars
['.'] = '.';
2353 identifier_chars
['_'] = '_';
2354 identifier_chars
['.'] = '.';
2356 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2357 operand_chars
[(unsigned char) *p
] = *p
;
2360 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2363 record_alignment (text_section
, 2);
2364 record_alignment (data_section
, 2);
2365 record_alignment (bss_section
, 2);
2369 if (flag_code
== CODE_64BIT
)
2371 x86_dwarf2_return_column
= 16;
2372 x86_cie_data_alignment
= -8;
2376 x86_dwarf2_return_column
= 8;
2377 x86_cie_data_alignment
= -4;
2382 i386_print_statistics (FILE *file
)
2384 hash_print_statistics (file
, "i386 opcode", op_hash
);
2385 hash_print_statistics (file
, "i386 register", reg_hash
);
2390 /* Debugging routines for md_assemble. */
2391 static void pte (insn_template
*);
2392 static void pt (i386_operand_type
);
2393 static void pe (expressionS
*);
2394 static void ps (symbolS
*);
2397 pi (char *line
, i386_insn
*x
)
2401 fprintf (stdout
, "%s: template ", line
);
2403 fprintf (stdout
, " address: base %s index %s scale %x\n",
2404 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2405 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2406 x
->log2_scale_factor
);
2407 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2408 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2409 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2410 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2411 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2412 (x
->rex
& REX_W
) != 0,
2413 (x
->rex
& REX_R
) != 0,
2414 (x
->rex
& REX_X
) != 0,
2415 (x
->rex
& REX_B
) != 0);
2416 for (j
= 0; j
< x
->operands
; j
++)
2418 fprintf (stdout
, " #%d: ", j
+ 1);
2420 fprintf (stdout
, "\n");
2421 if (x
->types
[j
].bitfield
.reg8
2422 || x
->types
[j
].bitfield
.reg16
2423 || x
->types
[j
].bitfield
.reg32
2424 || x
->types
[j
].bitfield
.reg64
2425 || x
->types
[j
].bitfield
.regmmx
2426 || x
->types
[j
].bitfield
.regxmm
2427 || x
->types
[j
].bitfield
.regymm
2428 || x
->types
[j
].bitfield
.sreg2
2429 || x
->types
[j
].bitfield
.sreg3
2430 || x
->types
[j
].bitfield
.control
2431 || x
->types
[j
].bitfield
.debug
2432 || x
->types
[j
].bitfield
.test
)
2433 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2434 if (operand_type_check (x
->types
[j
], imm
))
2436 if (operand_type_check (x
->types
[j
], disp
))
2437 pe (x
->op
[j
].disps
);
2442 pte (insn_template
*t
)
2445 fprintf (stdout
, " %d operands ", t
->operands
);
2446 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2447 if (t
->extension_opcode
!= None
)
2448 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2449 if (t
->opcode_modifier
.d
)
2450 fprintf (stdout
, "D");
2451 if (t
->opcode_modifier
.w
)
2452 fprintf (stdout
, "W");
2453 fprintf (stdout
, "\n");
2454 for (j
= 0; j
< t
->operands
; j
++)
2456 fprintf (stdout
, " #%d type ", j
+ 1);
2457 pt (t
->operand_types
[j
]);
2458 fprintf (stdout
, "\n");
2465 fprintf (stdout
, " operation %d\n", e
->X_op
);
2466 fprintf (stdout
, " add_number %ld (%lx)\n",
2467 (long) e
->X_add_number
, (long) e
->X_add_number
);
2468 if (e
->X_add_symbol
)
2470 fprintf (stdout
, " add_symbol ");
2471 ps (e
->X_add_symbol
);
2472 fprintf (stdout
, "\n");
2476 fprintf (stdout
, " op_symbol ");
2477 ps (e
->X_op_symbol
);
2478 fprintf (stdout
, "\n");
2485 fprintf (stdout
, "%s type %s%s",
2487 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2488 segment_name (S_GET_SEGMENT (s
)));
2491 static struct type_name
2493 i386_operand_type mask
;
2496 const type_names
[] =
2498 { OPERAND_TYPE_REG8
, "r8" },
2499 { OPERAND_TYPE_REG16
, "r16" },
2500 { OPERAND_TYPE_REG32
, "r32" },
2501 { OPERAND_TYPE_REG64
, "r64" },
2502 { OPERAND_TYPE_IMM8
, "i8" },
2503 { OPERAND_TYPE_IMM8
, "i8s" },
2504 { OPERAND_TYPE_IMM16
, "i16" },
2505 { OPERAND_TYPE_IMM32
, "i32" },
2506 { OPERAND_TYPE_IMM32S
, "i32s" },
2507 { OPERAND_TYPE_IMM64
, "i64" },
2508 { OPERAND_TYPE_IMM1
, "i1" },
2509 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2510 { OPERAND_TYPE_DISP8
, "d8" },
2511 { OPERAND_TYPE_DISP16
, "d16" },
2512 { OPERAND_TYPE_DISP32
, "d32" },
2513 { OPERAND_TYPE_DISP32S
, "d32s" },
2514 { OPERAND_TYPE_DISP64
, "d64" },
2515 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2516 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2517 { OPERAND_TYPE_CONTROL
, "control reg" },
2518 { OPERAND_TYPE_TEST
, "test reg" },
2519 { OPERAND_TYPE_DEBUG
, "debug reg" },
2520 { OPERAND_TYPE_FLOATREG
, "FReg" },
2521 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2522 { OPERAND_TYPE_SREG2
, "SReg2" },
2523 { OPERAND_TYPE_SREG3
, "SReg3" },
2524 { OPERAND_TYPE_ACC
, "Acc" },
2525 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2526 { OPERAND_TYPE_REGMMX
, "rMMX" },
2527 { OPERAND_TYPE_REGXMM
, "rXMM" },
2528 { OPERAND_TYPE_REGYMM
, "rYMM" },
2529 { OPERAND_TYPE_ESSEG
, "es" },
2533 pt (i386_operand_type t
)
2536 i386_operand_type a
;
2538 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2540 a
= operand_type_and (t
, type_names
[j
].mask
);
2541 if (!operand_type_all_zero (&a
))
2542 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2547 #endif /* DEBUG386 */
2549 static bfd_reloc_code_real_type
2550 reloc (unsigned int size
,
2553 bfd_reloc_code_real_type other
)
2555 if (other
!= NO_RELOC
)
2557 reloc_howto_type
*rel
;
2562 case BFD_RELOC_X86_64_GOT32
:
2563 return BFD_RELOC_X86_64_GOT64
;
2565 case BFD_RELOC_X86_64_PLTOFF64
:
2566 return BFD_RELOC_X86_64_PLTOFF64
;
2568 case BFD_RELOC_X86_64_GOTPC32
:
2569 other
= BFD_RELOC_X86_64_GOTPC64
;
2571 case BFD_RELOC_X86_64_GOTPCREL
:
2572 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2574 case BFD_RELOC_X86_64_TPOFF32
:
2575 other
= BFD_RELOC_X86_64_TPOFF64
;
2577 case BFD_RELOC_X86_64_DTPOFF32
:
2578 other
= BFD_RELOC_X86_64_DTPOFF64
;
2584 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2585 if (size
== 4 && flag_code
!= CODE_64BIT
)
2588 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2590 as_bad (_("unknown relocation (%u)"), other
);
2591 else if (size
!= bfd_get_reloc_size (rel
))
2592 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2593 bfd_get_reloc_size (rel
),
2595 else if (pcrel
&& !rel
->pc_relative
)
2596 as_bad (_("non-pc-relative relocation for pc-relative field"));
2597 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2599 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2601 as_bad (_("relocated field and relocation type differ in signedness"));
2610 as_bad (_("there are no unsigned pc-relative relocations"));
2613 case 1: return BFD_RELOC_8_PCREL
;
2614 case 2: return BFD_RELOC_16_PCREL
;
2615 case 4: return BFD_RELOC_32_PCREL
;
2616 case 8: return BFD_RELOC_64_PCREL
;
2618 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2625 case 4: return BFD_RELOC_X86_64_32S
;
2630 case 1: return BFD_RELOC_8
;
2631 case 2: return BFD_RELOC_16
;
2632 case 4: return BFD_RELOC_32
;
2633 case 8: return BFD_RELOC_64
;
2635 as_bad (_("cannot do %s %u byte relocation"),
2636 sign
> 0 ? "signed" : "unsigned", size
);
2642 /* Here we decide which fixups can be adjusted to make them relative to
2643 the beginning of the section instead of the symbol. Basically we need
2644 to make sure that the dynamic relocations are done correctly, so in
2645 some cases we force the original symbol to be used. */
2648 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2650 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2654 /* Don't adjust pc-relative references to merge sections in 64-bit
2656 if (use_rela_relocations
2657 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2661 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2662 and changed later by validate_fix. */
2663 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2664 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2667 /* adjust_reloc_syms doesn't know about the GOT. */
2668 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2669 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2670 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2671 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2672 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2673 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2674 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2675 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2676 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2677 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2678 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2679 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2680 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2681 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2682 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2683 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2684 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2685 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2686 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2687 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2688 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2689 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2690 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2691 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2692 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2693 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2694 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2695 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2702 intel_float_operand (const char *mnemonic
)
2704 /* Note that the value returned is meaningful only for opcodes with (memory)
2705 operands, hence the code here is free to improperly handle opcodes that
2706 have no operands (for better performance and smaller code). */
2708 if (mnemonic
[0] != 'f')
2709 return 0; /* non-math */
2711 switch (mnemonic
[1])
2713 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2714 the fs segment override prefix not currently handled because no
2715 call path can make opcodes without operands get here */
2717 return 2 /* integer op */;
2719 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2720 return 3; /* fldcw/fldenv */
2723 if (mnemonic
[2] != 'o' /* fnop */)
2724 return 3; /* non-waiting control op */
2727 if (mnemonic
[2] == 's')
2728 return 3; /* frstor/frstpm */
2731 if (mnemonic
[2] == 'a')
2732 return 3; /* fsave */
2733 if (mnemonic
[2] == 't')
2735 switch (mnemonic
[3])
2737 case 'c': /* fstcw */
2738 case 'd': /* fstdw */
2739 case 'e': /* fstenv */
2740 case 's': /* fsts[gw] */
2746 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2747 return 0; /* fxsave/fxrstor are not really math ops */
2754 /* Build the VEX prefix. */
2757 build_vex_prefix (const insn_template
*t
)
2759 unsigned int register_specifier
;
2760 unsigned int implied_prefix
;
2761 unsigned int vector_length
;
2763 /* Check register specifier. */
2764 if (i
.vex
.register_specifier
)
2766 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2767 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2768 register_specifier
+= 8;
2769 register_specifier
= ~register_specifier
& 0xf;
2772 register_specifier
= 0xf;
2774 /* Use 2-byte VEX prefix by swappping destination and source
2777 && i
.operands
== i
.reg_operands
2778 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2779 && i
.tm
.opcode_modifier
.s
2782 unsigned int xchg
= i
.operands
- 1;
2783 union i386_op temp_op
;
2784 i386_operand_type temp_type
;
2786 temp_type
= i
.types
[xchg
];
2787 i
.types
[xchg
] = i
.types
[0];
2788 i
.types
[0] = temp_type
;
2789 temp_op
= i
.op
[xchg
];
2790 i
.op
[xchg
] = i
.op
[0];
2793 gas_assert (i
.rm
.mode
== 3);
2797 i
.rm
.regmem
= i
.rm
.reg
;
2800 /* Use the next insn. */
2804 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2805 vector_length
= avxscalar
;
2807 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2809 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2814 case DATA_PREFIX_OPCODE
:
2817 case REPE_PREFIX_OPCODE
:
2820 case REPNE_PREFIX_OPCODE
:
2827 /* Use 2-byte VEX prefix if possible. */
2828 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2829 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
2830 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2832 /* 2-byte VEX prefix. */
2836 i
.vex
.bytes
[0] = 0xc5;
2838 /* Check the REX.R bit. */
2839 r
= (i
.rex
& REX_R
) ? 0 : 1;
2840 i
.vex
.bytes
[1] = (r
<< 7
2841 | register_specifier
<< 3
2842 | vector_length
<< 2
2847 /* 3-byte VEX prefix. */
2852 switch (i
.tm
.opcode_modifier
.vexopcode
)
2856 i
.vex
.bytes
[0] = 0xc4;
2860 i
.vex
.bytes
[0] = 0xc4;
2864 i
.vex
.bytes
[0] = 0xc4;
2868 i
.vex
.bytes
[0] = 0x8f;
2872 i
.vex
.bytes
[0] = 0x8f;
2876 i
.vex
.bytes
[0] = 0x8f;
2882 /* The high 3 bits of the second VEX byte are 1's compliment
2883 of RXB bits from REX. */
2884 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2886 /* Check the REX.W bit. */
2887 w
= (i
.rex
& REX_W
) ? 1 : 0;
2888 if (i
.tm
.opcode_modifier
.vexw
)
2893 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2897 i
.vex
.bytes
[2] = (w
<< 7
2898 | register_specifier
<< 3
2899 | vector_length
<< 2
2905 process_immext (void)
2909 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2911 /* SSE3 Instructions have the fixed operands with an opcode
2912 suffix which is coded in the same place as an 8-bit immediate
2913 field would be. Here we check those operands and remove them
2917 for (x
= 0; x
< i
.operands
; x
++)
2918 if (i
.op
[x
].regs
->reg_num
!= x
)
2919 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2920 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2926 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2927 which is coded in the same place as an 8-bit immediate field
2928 would be. Here we fake an 8-bit immediate operand from the
2929 opcode suffix stored in tm.extension_opcode.
2931 AVX instructions also use this encoding, for some of
2932 3 argument instructions. */
2934 gas_assert (i
.imm_operands
== 0
2936 || (i
.tm
.opcode_modifier
.vex
2937 && i
.operands
<= 4)));
2939 exp
= &im_expressions
[i
.imm_operands
++];
2940 i
.op
[i
.operands
].imms
= exp
;
2941 i
.types
[i
.operands
] = imm8
;
2943 exp
->X_op
= O_constant
;
2944 exp
->X_add_number
= i
.tm
.extension_opcode
;
2945 i
.tm
.extension_opcode
= None
;
2948 /* This is the guts of the machine-dependent assembler. LINE points to a
2949 machine dependent instruction. This function is supposed to emit
2950 the frags/bytes it assembles to. */
2953 md_assemble (char *line
)
2956 char mnemonic
[MAX_MNEM_SIZE
];
2957 const insn_template
*t
;
2959 /* Initialize globals. */
2960 memset (&i
, '\0', sizeof (i
));
2961 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2962 i
.reloc
[j
] = NO_RELOC
;
2963 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2964 memset (im_expressions
, '\0', sizeof (im_expressions
));
2965 save_stack_p
= save_stack
;
2967 /* First parse an instruction mnemonic & call i386_operand for the operands.
2968 We assume that the scrubber has arranged it so that line[0] is the valid
2969 start of a (possibly prefixed) mnemonic. */
2971 line
= parse_insn (line
, mnemonic
);
2975 line
= parse_operands (line
, mnemonic
);
2980 /* Now we've parsed the mnemonic into a set of templates, and have the
2981 operands at hand. */
2983 /* All intel opcodes have reversed operands except for "bound" and
2984 "enter". We also don't reverse intersegment "jmp" and "call"
2985 instructions with 2 immediate operands so that the immediate segment
2986 precedes the offset, as it does when in AT&T mode. */
2989 && (strcmp (mnemonic
, "bound") != 0)
2990 && (strcmp (mnemonic
, "invlpga") != 0)
2991 && !(operand_type_check (i
.types
[0], imm
)
2992 && operand_type_check (i
.types
[1], imm
)))
2995 /* The order of the immediates should be reversed
2996 for 2 immediates extrq and insertq instructions */
2997 if (i
.imm_operands
== 2
2998 && (strcmp (mnemonic
, "extrq") == 0
2999 || strcmp (mnemonic
, "insertq") == 0))
3000 swap_2_operands (0, 1);
3005 /* Don't optimize displacement for movabs since it only takes 64bit
3008 && !i
.disp32_encoding
3009 && (flag_code
!= CODE_64BIT
3010 || strcmp (mnemonic
, "movabs") != 0))
3013 /* Next, we find a template that matches the given insn,
3014 making sure the overlap of the given operands types is consistent
3015 with the template operand types. */
3017 if (!(t
= match_template ()))
3020 if (sse_check
!= sse_check_none
3021 && !i
.tm
.opcode_modifier
.noavx
3022 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3023 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3024 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3025 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3026 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3027 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3029 (sse_check
== sse_check_warning
3031 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3034 /* Zap movzx and movsx suffix. The suffix has been set from
3035 "word ptr" or "byte ptr" on the source operand in Intel syntax
3036 or extracted from mnemonic in AT&T syntax. But we'll use
3037 the destination register to choose the suffix for encoding. */
3038 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3040 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3041 there is no suffix, the default will be byte extension. */
3042 if (i
.reg_operands
!= 2
3045 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3050 if (i
.tm
.opcode_modifier
.fwait
)
3051 if (!add_prefix (FWAIT_OPCODE
))
3054 /* Check for lock without a lockable instruction. Destination operand
3055 must be memory unless it is xchg (0x86). */
3056 if (i
.prefix
[LOCK_PREFIX
]
3057 && (!i
.tm
.opcode_modifier
.islockable
3058 || i
.mem_operands
== 0
3059 || (i
.tm
.base_opcode
!= 0x86
3060 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3062 as_bad (_("expecting lockable instruction after `lock'"));
3066 /* Check string instruction segment overrides. */
3067 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3069 if (!check_string ())
3071 i
.disp_operands
= 0;
3074 if (!process_suffix ())
3077 /* Update operand types. */
3078 for (j
= 0; j
< i
.operands
; j
++)
3079 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3081 /* Make still unresolved immediate matches conform to size of immediate
3082 given in i.suffix. */
3083 if (!finalize_imm ())
3086 if (i
.types
[0].bitfield
.imm1
)
3087 i
.imm_operands
= 0; /* kludge for shift insns. */
3089 /* We only need to check those implicit registers for instructions
3090 with 3 operands or less. */
3091 if (i
.operands
<= 3)
3092 for (j
= 0; j
< i
.operands
; j
++)
3093 if (i
.types
[j
].bitfield
.inoutportreg
3094 || i
.types
[j
].bitfield
.shiftcount
3095 || i
.types
[j
].bitfield
.acc
3096 || i
.types
[j
].bitfield
.floatacc
)
3099 /* ImmExt should be processed after SSE2AVX. */
3100 if (!i
.tm
.opcode_modifier
.sse2avx
3101 && i
.tm
.opcode_modifier
.immext
)
3104 /* For insns with operands there are more diddles to do to the opcode. */
3107 if (!process_operands ())
3110 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3112 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3113 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3116 if (i
.tm
.opcode_modifier
.vex
)
3117 build_vex_prefix (t
);
3119 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3120 instructions may define INT_OPCODE as well, so avoid this corner
3121 case for those instructions that use MODRM. */
3122 if (i
.tm
.base_opcode
== INT_OPCODE
3123 && !i
.tm
.opcode_modifier
.modrm
3124 && i
.op
[0].imms
->X_add_number
== 3)
3126 i
.tm
.base_opcode
= INT3_OPCODE
;
3130 if ((i
.tm
.opcode_modifier
.jump
3131 || i
.tm
.opcode_modifier
.jumpbyte
3132 || i
.tm
.opcode_modifier
.jumpdword
)
3133 && i
.op
[0].disps
->X_op
== O_constant
)
3135 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3136 the absolute address given by the constant. Since ix86 jumps and
3137 calls are pc relative, we need to generate a reloc. */
3138 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3139 i
.op
[0].disps
->X_op
= O_symbol
;
3142 if (i
.tm
.opcode_modifier
.rex64
)
3145 /* For 8 bit registers we need an empty rex prefix. Also if the
3146 instruction already has a prefix, we need to convert old
3147 registers to new ones. */
3149 if ((i
.types
[0].bitfield
.reg8
3150 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3151 || (i
.types
[1].bitfield
.reg8
3152 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3153 || ((i
.types
[0].bitfield
.reg8
3154 || i
.types
[1].bitfield
.reg8
)
3159 i
.rex
|= REX_OPCODE
;
3160 for (x
= 0; x
< 2; x
++)
3162 /* Look for 8 bit operand that uses old registers. */
3163 if (i
.types
[x
].bitfield
.reg8
3164 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3166 /* In case it is "hi" register, give up. */
3167 if (i
.op
[x
].regs
->reg_num
> 3)
3168 as_bad (_("can't encode register '%s%s' in an "
3169 "instruction requiring REX prefix."),
3170 register_prefix
, i
.op
[x
].regs
->reg_name
);
3172 /* Otherwise it is equivalent to the extended register.
3173 Since the encoding doesn't change this is merely
3174 cosmetic cleanup for debug output. */
3176 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3182 add_prefix (REX_OPCODE
| i
.rex
);
3184 /* We are ready to output the insn. */
3189 parse_insn (char *line
, char *mnemonic
)
3192 char *token_start
= l
;
3195 const insn_template
*t
;
3198 /* Non-zero if we found a prefix only acceptable with string insns. */
3199 const char *expecting_string_instruction
= NULL
;
3204 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3209 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3211 as_bad (_("no such instruction: `%s'"), token_start
);
3216 if (!is_space_char (*l
)
3217 && *l
!= END_OF_INSN
3219 || (*l
!= PREFIX_SEPARATOR
3222 as_bad (_("invalid character %s in mnemonic"),
3223 output_invalid (*l
));
3226 if (token_start
== l
)
3228 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3229 as_bad (_("expecting prefix; got nothing"));
3231 as_bad (_("expecting mnemonic; got nothing"));
3235 /* Look up instruction (or prefix) via hash table. */
3236 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3238 if (*l
!= END_OF_INSN
3239 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3240 && current_templates
3241 && current_templates
->start
->opcode_modifier
.isprefix
)
3243 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3245 as_bad ((flag_code
!= CODE_64BIT
3246 ? _("`%s' is only supported in 64-bit mode")
3247 : _("`%s' is not supported in 64-bit mode")),
3248 current_templates
->start
->name
);
3251 /* If we are in 16-bit mode, do not allow addr16 or data16.
3252 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3253 if ((current_templates
->start
->opcode_modifier
.size16
3254 || current_templates
->start
->opcode_modifier
.size32
)
3255 && flag_code
!= CODE_64BIT
3256 && (current_templates
->start
->opcode_modifier
.size32
3257 ^ (flag_code
== CODE_16BIT
)))
3259 as_bad (_("redundant %s prefix"),
3260 current_templates
->start
->name
);
3263 /* Add prefix, checking for repeated prefixes. */
3264 switch (add_prefix (current_templates
->start
->base_opcode
))
3269 expecting_string_instruction
= current_templates
->start
->name
;
3274 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3281 if (!current_templates
)
3283 /* Check if we should swap operand or force 32bit displacement in
3285 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3287 else if (mnem_p
- 4 == dot_p
3291 i
.disp32_encoding
= 1;
3296 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3299 if (!current_templates
)
3302 /* See if we can get a match by trimming off a suffix. */
3305 case WORD_MNEM_SUFFIX
:
3306 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3307 i
.suffix
= SHORT_MNEM_SUFFIX
;
3309 case BYTE_MNEM_SUFFIX
:
3310 case QWORD_MNEM_SUFFIX
:
3311 i
.suffix
= mnem_p
[-1];
3313 current_templates
= (const templates
*) hash_find (op_hash
,
3316 case SHORT_MNEM_SUFFIX
:
3317 case LONG_MNEM_SUFFIX
:
3320 i
.suffix
= mnem_p
[-1];
3322 current_templates
= (const templates
*) hash_find (op_hash
,
3331 if (intel_float_operand (mnemonic
) == 1)
3332 i
.suffix
= SHORT_MNEM_SUFFIX
;
3334 i
.suffix
= LONG_MNEM_SUFFIX
;
3336 current_templates
= (const templates
*) hash_find (op_hash
,
3341 if (!current_templates
)
3343 as_bad (_("no such instruction: `%s'"), token_start
);
3348 if (current_templates
->start
->opcode_modifier
.jump
3349 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3351 /* Check for a branch hint. We allow ",pt" and ",pn" for
3352 predict taken and predict not taken respectively.
3353 I'm not sure that branch hints actually do anything on loop
3354 and jcxz insns (JumpByte) for current Pentium4 chips. They
3355 may work in the future and it doesn't hurt to accept them
3357 if (l
[0] == ',' && l
[1] == 'p')
3361 if (!add_prefix (DS_PREFIX_OPCODE
))
3365 else if (l
[2] == 'n')
3367 if (!add_prefix (CS_PREFIX_OPCODE
))
3373 /* Any other comma loses. */
3376 as_bad (_("invalid character %s in mnemonic"),
3377 output_invalid (*l
));
3381 /* Check if instruction is supported on specified architecture. */
3383 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3385 supported
|= cpu_flags_match (t
);
3386 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3390 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3392 as_bad (flag_code
== CODE_64BIT
3393 ? _("`%s' is not supported in 64-bit mode")
3394 : _("`%s' is only supported in 64-bit mode"),
3395 current_templates
->start
->name
);
3398 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3400 as_bad (_("`%s' is not supported on `%s%s'"),
3401 current_templates
->start
->name
,
3402 cpu_arch_name
? cpu_arch_name
: default_arch
,
3403 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3408 if (!cpu_arch_flags
.bitfield
.cpui386
3409 && (flag_code
!= CODE_16BIT
))
3411 as_warn (_("use .code16 to ensure correct addressing mode"));
3414 /* Check for rep/repne without a string instruction. */
3415 if (expecting_string_instruction
)
3417 static templates override
;
3419 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3420 if (t
->opcode_modifier
.isstring
)
3422 if (t
>= current_templates
->end
)
3424 as_bad (_("expecting string instruction after `%s'"),
3425 expecting_string_instruction
);
3428 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3429 if (!t
->opcode_modifier
.isstring
)
3432 current_templates
= &override
;
3439 parse_operands (char *l
, const char *mnemonic
)
3443 /* 1 if operand is pending after ','. */
3444 unsigned int expecting_operand
= 0;
3446 /* Non-zero if operand parens not balanced. */
3447 unsigned int paren_not_balanced
;
3449 while (*l
!= END_OF_INSN
)
3451 /* Skip optional white space before operand. */
3452 if (is_space_char (*l
))
3454 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3456 as_bad (_("invalid character %s before operand %d"),
3457 output_invalid (*l
),
3461 token_start
= l
; /* after white space */
3462 paren_not_balanced
= 0;
3463 while (paren_not_balanced
|| *l
!= ',')
3465 if (*l
== END_OF_INSN
)
3467 if (paren_not_balanced
)
3470 as_bad (_("unbalanced parenthesis in operand %d."),
3473 as_bad (_("unbalanced brackets in operand %d."),
3478 break; /* we are done */
3480 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3482 as_bad (_("invalid character %s in operand %d"),
3483 output_invalid (*l
),
3490 ++paren_not_balanced
;
3492 --paren_not_balanced
;
3497 ++paren_not_balanced
;
3499 --paren_not_balanced
;
3503 if (l
!= token_start
)
3504 { /* Yes, we've read in another operand. */
3505 unsigned int operand_ok
;
3506 this_operand
= i
.operands
++;
3507 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3508 if (i
.operands
> MAX_OPERANDS
)
3510 as_bad (_("spurious operands; (%d operands/instruction max)"),
3514 /* Now parse operand adding info to 'i' as we go along. */
3515 END_STRING_AND_SAVE (l
);
3519 i386_intel_operand (token_start
,
3520 intel_float_operand (mnemonic
));
3522 operand_ok
= i386_att_operand (token_start
);
3524 RESTORE_END_STRING (l
);
3530 if (expecting_operand
)
3532 expecting_operand_after_comma
:
3533 as_bad (_("expecting operand after ','; got nothing"));
3538 as_bad (_("expecting operand before ','; got nothing"));
3543 /* Now *l must be either ',' or END_OF_INSN. */
3546 if (*++l
== END_OF_INSN
)
3548 /* Just skip it, if it's \n complain. */
3549 goto expecting_operand_after_comma
;
3551 expecting_operand
= 1;
3558 swap_2_operands (int xchg1
, int xchg2
)
3560 union i386_op temp_op
;
3561 i386_operand_type temp_type
;
3562 enum bfd_reloc_code_real temp_reloc
;
3564 temp_type
= i
.types
[xchg2
];
3565 i
.types
[xchg2
] = i
.types
[xchg1
];
3566 i
.types
[xchg1
] = temp_type
;
3567 temp_op
= i
.op
[xchg2
];
3568 i
.op
[xchg2
] = i
.op
[xchg1
];
3569 i
.op
[xchg1
] = temp_op
;
3570 temp_reloc
= i
.reloc
[xchg2
];
3571 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3572 i
.reloc
[xchg1
] = temp_reloc
;
3576 swap_operands (void)
3582 swap_2_operands (1, i
.operands
- 2);
3585 swap_2_operands (0, i
.operands
- 1);
3591 if (i
.mem_operands
== 2)
3593 const seg_entry
*temp_seg
;
3594 temp_seg
= i
.seg
[0];
3595 i
.seg
[0] = i
.seg
[1];
3596 i
.seg
[1] = temp_seg
;
3600 /* Try to ensure constant immediates are represented in the smallest
3605 char guess_suffix
= 0;
3609 guess_suffix
= i
.suffix
;
3610 else if (i
.reg_operands
)
3612 /* Figure out a suffix from the last register operand specified.
3613 We can't do this properly yet, ie. excluding InOutPortReg,
3614 but the following works for instructions with immediates.
3615 In any case, we can't set i.suffix yet. */
3616 for (op
= i
.operands
; --op
>= 0;)
3617 if (i
.types
[op
].bitfield
.reg8
)
3619 guess_suffix
= BYTE_MNEM_SUFFIX
;
3622 else if (i
.types
[op
].bitfield
.reg16
)
3624 guess_suffix
= WORD_MNEM_SUFFIX
;
3627 else if (i
.types
[op
].bitfield
.reg32
)
3629 guess_suffix
= LONG_MNEM_SUFFIX
;
3632 else if (i
.types
[op
].bitfield
.reg64
)
3634 guess_suffix
= QWORD_MNEM_SUFFIX
;
3638 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3639 guess_suffix
= WORD_MNEM_SUFFIX
;
3641 for (op
= i
.operands
; --op
>= 0;)
3642 if (operand_type_check (i
.types
[op
], imm
))
3644 switch (i
.op
[op
].imms
->X_op
)
3647 /* If a suffix is given, this operand may be shortened. */
3648 switch (guess_suffix
)
3650 case LONG_MNEM_SUFFIX
:
3651 i
.types
[op
].bitfield
.imm32
= 1;
3652 i
.types
[op
].bitfield
.imm64
= 1;
3654 case WORD_MNEM_SUFFIX
:
3655 i
.types
[op
].bitfield
.imm16
= 1;
3656 i
.types
[op
].bitfield
.imm32
= 1;
3657 i
.types
[op
].bitfield
.imm32s
= 1;
3658 i
.types
[op
].bitfield
.imm64
= 1;
3660 case BYTE_MNEM_SUFFIX
:
3661 i
.types
[op
].bitfield
.imm8
= 1;
3662 i
.types
[op
].bitfield
.imm8s
= 1;
3663 i
.types
[op
].bitfield
.imm16
= 1;
3664 i
.types
[op
].bitfield
.imm32
= 1;
3665 i
.types
[op
].bitfield
.imm32s
= 1;
3666 i
.types
[op
].bitfield
.imm64
= 1;
3670 /* If this operand is at most 16 bits, convert it
3671 to a signed 16 bit number before trying to see
3672 whether it will fit in an even smaller size.
3673 This allows a 16-bit operand such as $0xffe0 to
3674 be recognised as within Imm8S range. */
3675 if ((i
.types
[op
].bitfield
.imm16
)
3676 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3678 i
.op
[op
].imms
->X_add_number
=
3679 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3681 if ((i
.types
[op
].bitfield
.imm32
)
3682 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3685 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3686 ^ ((offsetT
) 1 << 31))
3687 - ((offsetT
) 1 << 31));
3690 = operand_type_or (i
.types
[op
],
3691 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3693 /* We must avoid matching of Imm32 templates when 64bit
3694 only immediate is available. */
3695 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3696 i
.types
[op
].bitfield
.imm32
= 0;
3703 /* Symbols and expressions. */
3705 /* Convert symbolic operand to proper sizes for matching, but don't
3706 prevent matching a set of insns that only supports sizes other
3707 than those matching the insn suffix. */
3709 i386_operand_type mask
, allowed
;
3710 const insn_template
*t
;
3712 operand_type_set (&mask
, 0);
3713 operand_type_set (&allowed
, 0);
3715 for (t
= current_templates
->start
;
3716 t
< current_templates
->end
;
3718 allowed
= operand_type_or (allowed
,
3719 t
->operand_types
[op
]);
3720 switch (guess_suffix
)
3722 case QWORD_MNEM_SUFFIX
:
3723 mask
.bitfield
.imm64
= 1;
3724 mask
.bitfield
.imm32s
= 1;
3726 case LONG_MNEM_SUFFIX
:
3727 mask
.bitfield
.imm32
= 1;
3729 case WORD_MNEM_SUFFIX
:
3730 mask
.bitfield
.imm16
= 1;
3732 case BYTE_MNEM_SUFFIX
:
3733 mask
.bitfield
.imm8
= 1;
3738 allowed
= operand_type_and (mask
, allowed
);
3739 if (!operand_type_all_zero (&allowed
))
3740 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3747 /* Try to use the smallest displacement type too. */
3749 optimize_disp (void)
3753 for (op
= i
.operands
; --op
>= 0;)
3754 if (operand_type_check (i
.types
[op
], disp
))
3756 if (i
.op
[op
].disps
->X_op
== O_constant
)
3758 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3760 if (i
.types
[op
].bitfield
.disp16
3761 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3763 /* If this operand is at most 16 bits, convert
3764 to a signed 16 bit number and don't use 64bit
3766 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3767 i
.types
[op
].bitfield
.disp64
= 0;
3769 if (i
.types
[op
].bitfield
.disp32
3770 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3772 /* If this operand is at most 32 bits, convert
3773 to a signed 32 bit number and don't use 64bit
3775 op_disp
&= (((offsetT
) 2 << 31) - 1);
3776 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3777 i
.types
[op
].bitfield
.disp64
= 0;
3779 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3781 i
.types
[op
].bitfield
.disp8
= 0;
3782 i
.types
[op
].bitfield
.disp16
= 0;
3783 i
.types
[op
].bitfield
.disp32
= 0;
3784 i
.types
[op
].bitfield
.disp32s
= 0;
3785 i
.types
[op
].bitfield
.disp64
= 0;
3789 else if (flag_code
== CODE_64BIT
)
3791 if (fits_in_signed_long (op_disp
))
3793 i
.types
[op
].bitfield
.disp64
= 0;
3794 i
.types
[op
].bitfield
.disp32s
= 1;
3796 if (i
.prefix
[ADDR_PREFIX
]
3797 && fits_in_unsigned_long (op_disp
))
3798 i
.types
[op
].bitfield
.disp32
= 1;
3800 if ((i
.types
[op
].bitfield
.disp32
3801 || i
.types
[op
].bitfield
.disp32s
3802 || i
.types
[op
].bitfield
.disp16
)
3803 && fits_in_signed_byte (op_disp
))
3804 i
.types
[op
].bitfield
.disp8
= 1;
3806 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3807 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3809 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3810 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3811 i
.types
[op
].bitfield
.disp8
= 0;
3812 i
.types
[op
].bitfield
.disp16
= 0;
3813 i
.types
[op
].bitfield
.disp32
= 0;
3814 i
.types
[op
].bitfield
.disp32s
= 0;
3815 i
.types
[op
].bitfield
.disp64
= 0;
3818 /* We only support 64bit displacement on constants. */
3819 i
.types
[op
].bitfield
.disp64
= 0;
3823 /* Check if operands are valid for the instruction. Update VEX
3827 VEX_check_operands (const insn_template
*t
)
3829 if (!t
->opcode_modifier
.vex
)
3832 /* Only check VEX_Imm4, which must be the first operand. */
3833 if (t
->operand_types
[0].bitfield
.vec_imm4
)
3835 if (i
.op
[0].imms
->X_op
!= O_constant
3836 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3842 /* Turn off Imm8 so that update_imm won't complain. */
3843 i
.types
[0] = vec_imm4
;
3849 static const insn_template
*
3850 match_template (void)
3852 /* Points to template once we've found it. */
3853 const insn_template
*t
;
3854 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3855 i386_operand_type overlap4
;
3856 unsigned int found_reverse_match
;
3857 i386_opcode_modifier suffix_check
;
3858 i386_operand_type operand_types
[MAX_OPERANDS
];
3859 int addr_prefix_disp
;
3861 unsigned int found_cpu_match
;
3862 unsigned int check_register
;
3864 #if MAX_OPERANDS != 5
3865 # error "MAX_OPERANDS must be 5."
3868 found_reverse_match
= 0;
3869 addr_prefix_disp
= -1;
3871 memset (&suffix_check
, 0, sizeof (suffix_check
));
3872 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3873 suffix_check
.no_bsuf
= 1;
3874 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3875 suffix_check
.no_wsuf
= 1;
3876 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3877 suffix_check
.no_ssuf
= 1;
3878 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3879 suffix_check
.no_lsuf
= 1;
3880 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3881 suffix_check
.no_qsuf
= 1;
3882 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3883 suffix_check
.no_ldsuf
= 1;
3885 /* Must have right number of operands. */
3886 i
.error
= number_of_operands_mismatch
;
3888 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3890 addr_prefix_disp
= -1;
3892 if (i
.operands
!= t
->operands
)
3895 /* Check processor support. */
3896 i
.error
= unsupported
;
3897 found_cpu_match
= (cpu_flags_match (t
)
3898 == CPU_FLAGS_PERFECT_MATCH
);
3899 if (!found_cpu_match
)
3902 /* Check old gcc support. */
3903 i
.error
= old_gcc_only
;
3904 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3907 /* Check AT&T mnemonic. */
3908 i
.error
= unsupported_with_intel_mnemonic
;
3909 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3912 /* Check AT&T/Intel syntax. */
3913 i
.error
= unsupported_syntax
;
3914 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3915 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3918 /* Check the suffix, except for some instructions in intel mode. */
3919 i
.error
= invalid_instruction_suffix
;
3920 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3921 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3922 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3923 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3924 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3925 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3926 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3929 if (!operand_size_match (t
))
3932 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3933 operand_types
[j
] = t
->operand_types
[j
];
3935 /* In general, don't allow 64-bit operands in 32-bit mode. */
3936 if (i
.suffix
== QWORD_MNEM_SUFFIX
3937 && flag_code
!= CODE_64BIT
3939 ? (!t
->opcode_modifier
.ignoresize
3940 && !intel_float_operand (t
->name
))
3941 : intel_float_operand (t
->name
) != 2)
3942 && ((!operand_types
[0].bitfield
.regmmx
3943 && !operand_types
[0].bitfield
.regxmm
3944 && !operand_types
[0].bitfield
.regymm
)
3945 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3946 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3947 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3948 && (t
->base_opcode
!= 0x0fc7
3949 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3952 /* In general, don't allow 32-bit operands on pre-386. */
3953 else if (i
.suffix
== LONG_MNEM_SUFFIX
3954 && !cpu_arch_flags
.bitfield
.cpui386
3956 ? (!t
->opcode_modifier
.ignoresize
3957 && !intel_float_operand (t
->name
))
3958 : intel_float_operand (t
->name
) != 2)
3959 && ((!operand_types
[0].bitfield
.regmmx
3960 && !operand_types
[0].bitfield
.regxmm
)
3961 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3962 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3965 /* Do not verify operands when there are none. */
3969 /* We've found a match; break out of loop. */
3973 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3974 into Disp32/Disp16/Disp32 operand. */
3975 if (i
.prefix
[ADDR_PREFIX
] != 0)
3977 /* There should be only one Disp operand. */
3981 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3983 if (operand_types
[j
].bitfield
.disp16
)
3985 addr_prefix_disp
= j
;
3986 operand_types
[j
].bitfield
.disp32
= 1;
3987 operand_types
[j
].bitfield
.disp16
= 0;
3993 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3995 if (operand_types
[j
].bitfield
.disp32
)
3997 addr_prefix_disp
= j
;
3998 operand_types
[j
].bitfield
.disp32
= 0;
3999 operand_types
[j
].bitfield
.disp16
= 1;
4005 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4007 if (operand_types
[j
].bitfield
.disp64
)
4009 addr_prefix_disp
= j
;
4010 operand_types
[j
].bitfield
.disp64
= 0;
4011 operand_types
[j
].bitfield
.disp32
= 1;
4019 /* We check register size if needed. */
4020 check_register
= t
->opcode_modifier
.checkregsize
;
4021 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4022 switch (t
->operands
)
4025 if (!operand_type_match (overlap0
, i
.types
[0]))
4029 /* xchg %eax, %eax is a special case. It is an aliase for nop
4030 only in 32bit mode and we can use opcode 0x90. In 64bit
4031 mode, we can't use 0x90 for xchg %eax, %eax since it should
4032 zero-extend %eax to %rax. */
4033 if (flag_code
== CODE_64BIT
4034 && t
->base_opcode
== 0x90
4035 && operand_type_equal (&i
.types
[0], &acc32
)
4036 && operand_type_equal (&i
.types
[1], &acc32
))
4040 /* If we swap operand in encoding, we either match
4041 the next one or reverse direction of operands. */
4042 if (t
->opcode_modifier
.s
)
4044 else if (t
->opcode_modifier
.d
)
4049 /* If we swap operand in encoding, we match the next one. */
4050 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4054 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4055 if (!operand_type_match (overlap0
, i
.types
[0])
4056 || !operand_type_match (overlap1
, i
.types
[1])
4058 && !operand_type_register_match (overlap0
, i
.types
[0],
4060 overlap1
, i
.types
[1],
4063 /* Check if other direction is valid ... */
4064 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4068 /* Try reversing direction of operands. */
4069 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4070 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4071 if (!operand_type_match (overlap0
, i
.types
[0])
4072 || !operand_type_match (overlap1
, i
.types
[1])
4074 && !operand_type_register_match (overlap0
,
4081 /* Does not match either direction. */
4084 /* found_reverse_match holds which of D or FloatDR
4086 if (t
->opcode_modifier
.d
)
4087 found_reverse_match
= Opcode_D
;
4088 else if (t
->opcode_modifier
.floatd
)
4089 found_reverse_match
= Opcode_FloatD
;
4091 found_reverse_match
= 0;
4092 if (t
->opcode_modifier
.floatr
)
4093 found_reverse_match
|= Opcode_FloatR
;
4097 /* Found a forward 2 operand match here. */
4098 switch (t
->operands
)
4101 overlap4
= operand_type_and (i
.types
[4],
4104 overlap3
= operand_type_and (i
.types
[3],
4107 overlap2
= operand_type_and (i
.types
[2],
4112 switch (t
->operands
)
4115 if (!operand_type_match (overlap4
, i
.types
[4])
4116 || !operand_type_register_match (overlap3
,
4124 if (!operand_type_match (overlap3
, i
.types
[3])
4126 && !operand_type_register_match (overlap2
,
4134 /* Here we make use of the fact that there are no
4135 reverse match 3 operand instructions, and all 3
4136 operand instructions only need to be checked for
4137 register consistency between operands 2 and 3. */
4138 if (!operand_type_match (overlap2
, i
.types
[2])
4140 && !operand_type_register_match (overlap1
,
4150 /* Found either forward/reverse 2, 3 or 4 operand match here:
4151 slip through to break. */
4153 if (!found_cpu_match
)
4155 found_reverse_match
= 0;
4159 /* Check if VEX operands are valid. */
4160 if (VEX_check_operands (t
))
4163 /* We've found a match; break out of loop. */
4167 if (t
== current_templates
->end
)
4169 /* We found no match. */
4170 const char *err_msg
;
4175 case operand_size_mismatch
:
4176 err_msg
= _("operand size mismatch");
4178 case operand_type_mismatch
:
4179 err_msg
= _("operand type mismatch");
4181 case register_type_mismatch
:
4182 err_msg
= _("register type mismatch");
4184 case number_of_operands_mismatch
:
4185 err_msg
= _("number of operands mismatch");
4187 case invalid_instruction_suffix
:
4188 err_msg
= _("invalid instruction suffix");
4191 err_msg
= _("Imm4 isn't the first operand");
4194 err_msg
= _("only supported with old gcc");
4196 case unsupported_with_intel_mnemonic
:
4197 err_msg
= _("unsupported with Intel mnemonic");
4199 case unsupported_syntax
:
4200 err_msg
= _("unsupported syntax");
4203 err_msg
= _("unsupported");
4206 as_bad (_("%s for `%s'"), err_msg
,
4207 current_templates
->start
->name
);
4211 if (!quiet_warnings
)
4214 && (i
.types
[0].bitfield
.jumpabsolute
4215 != operand_types
[0].bitfield
.jumpabsolute
))
4217 as_warn (_("indirect %s without `*'"), t
->name
);
4220 if (t
->opcode_modifier
.isprefix
4221 && t
->opcode_modifier
.ignoresize
)
4223 /* Warn them that a data or address size prefix doesn't
4224 affect assembly of the next line of code. */
4225 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4229 /* Copy the template we found. */
4232 if (addr_prefix_disp
!= -1)
4233 i
.tm
.operand_types
[addr_prefix_disp
]
4234 = operand_types
[addr_prefix_disp
];
4236 if (found_reverse_match
)
4238 /* If we found a reverse match we must alter the opcode
4239 direction bit. found_reverse_match holds bits to change
4240 (different for int & float insns). */
4242 i
.tm
.base_opcode
^= found_reverse_match
;
4244 i
.tm
.operand_types
[0] = operand_types
[1];
4245 i
.tm
.operand_types
[1] = operand_types
[0];
4254 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4255 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4257 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4259 as_bad (_("`%s' operand %d must use `%ses' segment"),
4265 /* There's only ever one segment override allowed per instruction.
4266 This instruction possibly has a legal segment override on the
4267 second operand, so copy the segment to where non-string
4268 instructions store it, allowing common code. */
4269 i
.seg
[0] = i
.seg
[1];
4271 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4273 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4275 as_bad (_("`%s' operand %d must use `%ses' segment"),
4286 process_suffix (void)
4288 /* If matched instruction specifies an explicit instruction mnemonic
4290 if (i
.tm
.opcode_modifier
.size16
)
4291 i
.suffix
= WORD_MNEM_SUFFIX
;
4292 else if (i
.tm
.opcode_modifier
.size32
)
4293 i
.suffix
= LONG_MNEM_SUFFIX
;
4294 else if (i
.tm
.opcode_modifier
.size64
)
4295 i
.suffix
= QWORD_MNEM_SUFFIX
;
4296 else if (i
.reg_operands
)
4298 /* If there's no instruction mnemonic suffix we try to invent one
4299 based on register operands. */
4302 /* We take i.suffix from the last register operand specified,
4303 Destination register type is more significant than source
4304 register type. crc32 in SSE4.2 prefers source register
4306 if (i
.tm
.base_opcode
== 0xf20f38f1)
4308 if (i
.types
[0].bitfield
.reg16
)
4309 i
.suffix
= WORD_MNEM_SUFFIX
;
4310 else if (i
.types
[0].bitfield
.reg32
)
4311 i
.suffix
= LONG_MNEM_SUFFIX
;
4312 else if (i
.types
[0].bitfield
.reg64
)
4313 i
.suffix
= QWORD_MNEM_SUFFIX
;
4315 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4317 if (i
.types
[0].bitfield
.reg8
)
4318 i
.suffix
= BYTE_MNEM_SUFFIX
;
4325 if (i
.tm
.base_opcode
== 0xf20f38f1
4326 || i
.tm
.base_opcode
== 0xf20f38f0)
4328 /* We have to know the operand size for crc32. */
4329 as_bad (_("ambiguous memory operand size for `%s`"),
4334 for (op
= i
.operands
; --op
>= 0;)
4335 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4337 if (i
.types
[op
].bitfield
.reg8
)
4339 i
.suffix
= BYTE_MNEM_SUFFIX
;
4342 else if (i
.types
[op
].bitfield
.reg16
)
4344 i
.suffix
= WORD_MNEM_SUFFIX
;
4347 else if (i
.types
[op
].bitfield
.reg32
)
4349 i
.suffix
= LONG_MNEM_SUFFIX
;
4352 else if (i
.types
[op
].bitfield
.reg64
)
4354 i
.suffix
= QWORD_MNEM_SUFFIX
;
4360 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4363 && i
.tm
.opcode_modifier
.ignoresize
4364 && i
.tm
.opcode_modifier
.no_bsuf
)
4366 else if (!check_byte_reg ())
4369 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4372 && i
.tm
.opcode_modifier
.ignoresize
4373 && i
.tm
.opcode_modifier
.no_lsuf
)
4375 else if (!check_long_reg ())
4378 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4381 && i
.tm
.opcode_modifier
.ignoresize
4382 && i
.tm
.opcode_modifier
.no_qsuf
)
4384 else if (!check_qword_reg ())
4387 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4390 && i
.tm
.opcode_modifier
.ignoresize
4391 && i
.tm
.opcode_modifier
.no_wsuf
)
4393 else if (!check_word_reg ())
4396 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4397 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4399 /* Skip if the instruction has x/y suffix. match_template
4400 should check if it is a valid suffix. */
4402 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4403 /* Do nothing if the instruction is going to ignore the prefix. */
4408 else if (i
.tm
.opcode_modifier
.defaultsize
4410 /* exclude fldenv/frstor/fsave/fstenv */
4411 && i
.tm
.opcode_modifier
.no_ssuf
)
4413 i
.suffix
= stackop_size
;
4415 else if (intel_syntax
4417 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4418 || i
.tm
.opcode_modifier
.jumpbyte
4419 || i
.tm
.opcode_modifier
.jumpintersegment
4420 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4421 && i
.tm
.extension_opcode
<= 3)))
4426 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4428 i
.suffix
= QWORD_MNEM_SUFFIX
;
4432 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4433 i
.suffix
= LONG_MNEM_SUFFIX
;
4436 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4437 i
.suffix
= WORD_MNEM_SUFFIX
;
4446 if (i
.tm
.opcode_modifier
.w
)
4448 as_bad (_("no instruction mnemonic suffix given and "
4449 "no register operands; can't size instruction"));
4455 unsigned int suffixes
;
4457 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4458 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4460 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4462 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4464 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4466 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4469 /* There are more than suffix matches. */
4470 if (i
.tm
.opcode_modifier
.w
4471 || ((suffixes
& (suffixes
- 1))
4472 && !i
.tm
.opcode_modifier
.defaultsize
4473 && !i
.tm
.opcode_modifier
.ignoresize
))
4475 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4481 /* Change the opcode based on the operand size given by i.suffix;
4482 We don't need to change things for byte insns. */
4485 && i
.suffix
!= BYTE_MNEM_SUFFIX
4486 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4487 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4489 /* It's not a byte, select word/dword operation. */
4490 if (i
.tm
.opcode_modifier
.w
)
4492 if (i
.tm
.opcode_modifier
.shortform
)
4493 i
.tm
.base_opcode
|= 8;
4495 i
.tm
.base_opcode
|= 1;
4498 /* Now select between word & dword operations via the operand
4499 size prefix, except for instructions that will ignore this
4501 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4503 /* The address size override prefix changes the size of the
4505 if ((flag_code
== CODE_32BIT
4506 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4507 || (flag_code
!= CODE_32BIT
4508 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4509 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4512 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4513 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4514 && !i
.tm
.opcode_modifier
.ignoresize
4515 && !i
.tm
.opcode_modifier
.floatmf
4516 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4517 || (flag_code
== CODE_64BIT
4518 && i
.tm
.opcode_modifier
.jumpbyte
)))
4520 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4522 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4523 prefix
= ADDR_PREFIX_OPCODE
;
4525 if (!add_prefix (prefix
))
4529 /* Set mode64 for an operand. */
4530 if (i
.suffix
== QWORD_MNEM_SUFFIX
4531 && flag_code
== CODE_64BIT
4532 && !i
.tm
.opcode_modifier
.norex64
)
4534 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4535 need rex64. cmpxchg8b is also a special case. */
4536 if (! (i
.operands
== 2
4537 && i
.tm
.base_opcode
== 0x90
4538 && i
.tm
.extension_opcode
== None
4539 && operand_type_equal (&i
.types
[0], &acc64
)
4540 && operand_type_equal (&i
.types
[1], &acc64
))
4541 && ! (i
.operands
== 1
4542 && i
.tm
.base_opcode
== 0xfc7
4543 && i
.tm
.extension_opcode
== 1
4544 && !operand_type_check (i
.types
[0], reg
)
4545 && operand_type_check (i
.types
[0], anymem
)))
4549 /* Size floating point instruction. */
4550 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4551 if (i
.tm
.opcode_modifier
.floatmf
)
4552 i
.tm
.base_opcode
^= 4;
4559 check_byte_reg (void)
4563 for (op
= i
.operands
; --op
>= 0;)
4565 /* If this is an eight bit register, it's OK. If it's the 16 or
4566 32 bit version of an eight bit register, we will just use the
4567 low portion, and that's OK too. */
4568 if (i
.types
[op
].bitfield
.reg8
)
4571 /* crc32 doesn't generate this warning. */
4572 if (i
.tm
.base_opcode
== 0xf20f38f0)
4575 if ((i
.types
[op
].bitfield
.reg16
4576 || i
.types
[op
].bitfield
.reg32
4577 || i
.types
[op
].bitfield
.reg64
)
4578 && i
.op
[op
].regs
->reg_num
< 4)
4580 /* Prohibit these changes in the 64bit mode, since the
4581 lowering is more complicated. */
4582 if (flag_code
== CODE_64BIT
4583 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4585 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4586 register_prefix
, i
.op
[op
].regs
->reg_name
,
4590 #if REGISTER_WARNINGS
4592 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4593 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4595 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4596 ? REGNAM_AL
- REGNAM_AX
4597 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4599 i
.op
[op
].regs
->reg_name
,
4604 /* Any other register is bad. */
4605 if (i
.types
[op
].bitfield
.reg16
4606 || i
.types
[op
].bitfield
.reg32
4607 || i
.types
[op
].bitfield
.reg64
4608 || i
.types
[op
].bitfield
.regmmx
4609 || i
.types
[op
].bitfield
.regxmm
4610 || i
.types
[op
].bitfield
.regymm
4611 || i
.types
[op
].bitfield
.sreg2
4612 || i
.types
[op
].bitfield
.sreg3
4613 || i
.types
[op
].bitfield
.control
4614 || i
.types
[op
].bitfield
.debug
4615 || i
.types
[op
].bitfield
.test
4616 || i
.types
[op
].bitfield
.floatreg
4617 || i
.types
[op
].bitfield
.floatacc
)
4619 as_bad (_("`%s%s' not allowed with `%s%c'"),
4621 i
.op
[op
].regs
->reg_name
,
4631 check_long_reg (void)
4635 for (op
= i
.operands
; --op
>= 0;)
4636 /* Reject eight bit registers, except where the template requires
4637 them. (eg. movzb) */
4638 if (i
.types
[op
].bitfield
.reg8
4639 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4640 || i
.tm
.operand_types
[op
].bitfield
.reg32
4641 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4643 as_bad (_("`%s%s' not allowed with `%s%c'"),
4645 i
.op
[op
].regs
->reg_name
,
4650 /* Warn if the e prefix on a general reg is missing. */
4651 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4652 && i
.types
[op
].bitfield
.reg16
4653 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4654 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4656 /* Prohibit these changes in the 64bit mode, since the
4657 lowering is more complicated. */
4658 if (flag_code
== CODE_64BIT
)
4660 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4661 register_prefix
, i
.op
[op
].regs
->reg_name
,
4665 #if REGISTER_WARNINGS
4667 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4669 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4671 i
.op
[op
].regs
->reg_name
,
4675 /* Warn if the r prefix on a general reg is missing. */
4676 else if (i
.types
[op
].bitfield
.reg64
4677 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4678 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4681 && i
.tm
.opcode_modifier
.toqword
4682 && !i
.types
[0].bitfield
.regxmm
)
4684 /* Convert to QWORD. We want REX byte. */
4685 i
.suffix
= QWORD_MNEM_SUFFIX
;
4689 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4690 register_prefix
, i
.op
[op
].regs
->reg_name
,
4699 check_qword_reg (void)
4703 for (op
= i
.operands
; --op
>= 0; )
4704 /* Reject eight bit registers, except where the template requires
4705 them. (eg. movzb) */
4706 if (i
.types
[op
].bitfield
.reg8
4707 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4708 || i
.tm
.operand_types
[op
].bitfield
.reg32
4709 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4711 as_bad (_("`%s%s' not allowed with `%s%c'"),
4713 i
.op
[op
].regs
->reg_name
,
4718 /* Warn if the e prefix on a general reg is missing. */
4719 else if ((i
.types
[op
].bitfield
.reg16
4720 || i
.types
[op
].bitfield
.reg32
)
4721 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4722 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4724 /* Prohibit these changes in the 64bit mode, since the
4725 lowering is more complicated. */
4727 && i
.tm
.opcode_modifier
.todword
4728 && !i
.types
[0].bitfield
.regxmm
)
4730 /* Convert to DWORD. We don't want REX byte. */
4731 i
.suffix
= LONG_MNEM_SUFFIX
;
4735 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4736 register_prefix
, i
.op
[op
].regs
->reg_name
,
4745 check_word_reg (void)
4748 for (op
= i
.operands
; --op
>= 0;)
4749 /* Reject eight bit registers, except where the template requires
4750 them. (eg. movzb) */
4751 if (i
.types
[op
].bitfield
.reg8
4752 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4753 || i
.tm
.operand_types
[op
].bitfield
.reg32
4754 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4756 as_bad (_("`%s%s' not allowed with `%s%c'"),
4758 i
.op
[op
].regs
->reg_name
,
4763 /* Warn if the e prefix on a general reg is present. */
4764 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4765 && i
.types
[op
].bitfield
.reg32
4766 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4767 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4769 /* Prohibit these changes in the 64bit mode, since the
4770 lowering is more complicated. */
4771 if (flag_code
== CODE_64BIT
)
4773 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4774 register_prefix
, i
.op
[op
].regs
->reg_name
,
4779 #if REGISTER_WARNINGS
4780 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4782 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4784 i
.op
[op
].regs
->reg_name
,
4792 update_imm (unsigned int j
)
4794 i386_operand_type overlap
= i
.types
[j
];
4795 if ((overlap
.bitfield
.imm8
4796 || overlap
.bitfield
.imm8s
4797 || overlap
.bitfield
.imm16
4798 || overlap
.bitfield
.imm32
4799 || overlap
.bitfield
.imm32s
4800 || overlap
.bitfield
.imm64
)
4801 && !operand_type_equal (&overlap
, &imm8
)
4802 && !operand_type_equal (&overlap
, &imm8s
)
4803 && !operand_type_equal (&overlap
, &imm16
)
4804 && !operand_type_equal (&overlap
, &imm32
)
4805 && !operand_type_equal (&overlap
, &imm32s
)
4806 && !operand_type_equal (&overlap
, &imm64
))
4810 i386_operand_type temp
;
4812 operand_type_set (&temp
, 0);
4813 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4815 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4816 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4818 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4819 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4820 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4822 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4823 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4826 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4829 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4830 || operand_type_equal (&overlap
, &imm16_32
)
4831 || operand_type_equal (&overlap
, &imm16_32s
))
4833 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4838 if (!operand_type_equal (&overlap
, &imm8
)
4839 && !operand_type_equal (&overlap
, &imm8s
)
4840 && !operand_type_equal (&overlap
, &imm16
)
4841 && !operand_type_equal (&overlap
, &imm32
)
4842 && !operand_type_equal (&overlap
, &imm32s
)
4843 && !operand_type_equal (&overlap
, &imm64
))
4845 as_bad (_("no instruction mnemonic suffix given; "
4846 "can't determine immediate size"));
4850 i
.types
[j
] = overlap
;
4860 /* Update the first 2 immediate operands. */
4861 n
= i
.operands
> 2 ? 2 : i
.operands
;
4864 for (j
= 0; j
< n
; j
++)
4865 if (update_imm (j
) == 0)
4868 /* The 3rd operand can't be immediate operand. */
4869 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4876 bad_implicit_operand (int xmm
)
4878 const char *ireg
= xmm
? "xmm0" : "ymm0";
4881 as_bad (_("the last operand of `%s' must be `%s%s'"),
4882 i
.tm
.name
, register_prefix
, ireg
);
4884 as_bad (_("the first operand of `%s' must be `%s%s'"),
4885 i
.tm
.name
, register_prefix
, ireg
);
4890 process_operands (void)
4892 /* Default segment register this instruction will use for memory
4893 accesses. 0 means unknown. This is only for optimizing out
4894 unnecessary segment overrides. */
4895 const seg_entry
*default_seg
= 0;
4897 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
4899 unsigned int dupl
= i
.operands
;
4900 unsigned int dest
= dupl
- 1;
4903 /* The destination must be an xmm register. */
4904 gas_assert (i
.reg_operands
4905 && MAX_OPERANDS
> dupl
4906 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4908 if (i
.tm
.opcode_modifier
.firstxmm0
)
4910 /* The first operand is implicit and must be xmm0. */
4911 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4912 if (i
.op
[0].regs
->reg_num
!= 0)
4913 return bad_implicit_operand (1);
4915 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4917 /* Keep xmm0 for instructions with VEX prefix and 3
4923 /* We remove the first xmm0 and keep the number of
4924 operands unchanged, which in fact duplicates the
4926 for (j
= 1; j
< i
.operands
; j
++)
4928 i
.op
[j
- 1] = i
.op
[j
];
4929 i
.types
[j
- 1] = i
.types
[j
];
4930 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4934 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4936 gas_assert ((MAX_OPERANDS
- 1) > dupl
4937 && (i
.tm
.opcode_modifier
.vexsources
4940 /* Add the implicit xmm0 for instructions with VEX prefix
4942 for (j
= i
.operands
; j
> 0; j
--)
4944 i
.op
[j
] = i
.op
[j
- 1];
4945 i
.types
[j
] = i
.types
[j
- 1];
4946 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4949 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4950 i
.types
[0] = regxmm
;
4951 i
.tm
.operand_types
[0] = regxmm
;
4954 i
.reg_operands
+= 2;
4959 i
.op
[dupl
] = i
.op
[dest
];
4960 i
.types
[dupl
] = i
.types
[dest
];
4961 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4970 i
.op
[dupl
] = i
.op
[dest
];
4971 i
.types
[dupl
] = i
.types
[dest
];
4972 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4975 if (i
.tm
.opcode_modifier
.immext
)
4978 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4982 /* The first operand is implicit and must be xmm0/ymm0. */
4983 gas_assert (i
.reg_operands
4984 && (operand_type_equal (&i
.types
[0], ®xmm
)
4985 || operand_type_equal (&i
.types
[0], ®ymm
)));
4986 if (i
.op
[0].regs
->reg_num
!= 0)
4987 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4989 for (j
= 1; j
< i
.operands
; j
++)
4991 i
.op
[j
- 1] = i
.op
[j
];
4992 i
.types
[j
- 1] = i
.types
[j
];
4994 /* We need to adjust fields in i.tm since they are used by
4995 build_modrm_byte. */
4996 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5003 else if (i
.tm
.opcode_modifier
.regkludge
)
5005 /* The imul $imm, %reg instruction is converted into
5006 imul $imm, %reg, %reg, and the clr %reg instruction
5007 is converted into xor %reg, %reg. */
5009 unsigned int first_reg_op
;
5011 if (operand_type_check (i
.types
[0], reg
))
5015 /* Pretend we saw the extra register operand. */
5016 gas_assert (i
.reg_operands
== 1
5017 && i
.op
[first_reg_op
+ 1].regs
== 0);
5018 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5019 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5024 if (i
.tm
.opcode_modifier
.shortform
)
5026 if (i
.types
[0].bitfield
.sreg2
5027 || i
.types
[0].bitfield
.sreg3
)
5029 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5030 && i
.op
[0].regs
->reg_num
== 1)
5032 as_bad (_("you can't `pop %scs'"), register_prefix
);
5035 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5036 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5041 /* The register or float register operand is in operand
5045 if (i
.types
[0].bitfield
.floatreg
5046 || operand_type_check (i
.types
[0], reg
))
5050 /* Register goes in low 3 bits of opcode. */
5051 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5052 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5054 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5056 /* Warn about some common errors, but press on regardless.
5057 The first case can be generated by gcc (<= 2.8.1). */
5058 if (i
.operands
== 2)
5060 /* Reversed arguments on faddp, fsubp, etc. */
5061 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5062 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5063 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5067 /* Extraneous `l' suffix on fp insn. */
5068 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5069 register_prefix
, i
.op
[0].regs
->reg_name
);
5074 else if (i
.tm
.opcode_modifier
.modrm
)
5076 /* The opcode is completed (modulo i.tm.extension_opcode which
5077 must be put into the modrm byte). Now, we make the modrm and
5078 index base bytes based on all the info we've collected. */
5080 default_seg
= build_modrm_byte ();
5082 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5086 else if (i
.tm
.opcode_modifier
.isstring
)
5088 /* For the string instructions that allow a segment override
5089 on one of their operands, the default segment is ds. */
5093 if (i
.tm
.base_opcode
== 0x8d /* lea */
5096 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5098 /* If a segment was explicitly specified, and the specified segment
5099 is not the default, use an opcode prefix to select it. If we
5100 never figured out what the default segment is, then default_seg
5101 will be zero at this point, and the specified segment prefix will
5103 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5105 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5111 static const seg_entry
*
5112 build_modrm_byte (void)
5114 const seg_entry
*default_seg
= 0;
5115 unsigned int source
, dest
;
5118 /* The first operand of instructions with VEX prefix and 3 sources
5119 must be VEX_Imm4. */
5120 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5123 unsigned int nds
, reg_slot
;
5126 if (i
.tm
.opcode_modifier
.veximmext
5127 && i
.tm
.opcode_modifier
.immext
)
5129 dest
= i
.operands
- 2;
5130 gas_assert (dest
== 3);
5133 dest
= i
.operands
- 1;
5136 /* There are 2 kinds of instructions:
5137 1. 5 operands: 4 register operands or 3 register operands
5138 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5139 VexW0 or VexW1. The destination must be either XMM or YMM
5141 2. 4 operands: 4 register operands or 3 register operands
5142 plus 1 memory operand, VexXDS, and VexImmExt */
5143 gas_assert ((i
.reg_operands
== 4
5144 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5145 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5146 && (i
.tm
.opcode_modifier
.veximmext
5147 || (i
.imm_operands
== 1
5148 && i
.types
[0].bitfield
.vec_imm4
5149 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5150 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5151 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5152 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5154 if (i
.imm_operands
== 0)
5156 /* When there is no immediate operand, generate an 8bit
5157 immediate operand to encode the first operand. */
5158 exp
= &im_expressions
[i
.imm_operands
++];
5159 i
.op
[i
.operands
].imms
= exp
;
5160 i
.types
[i
.operands
] = imm8
;
5162 /* If VexW1 is set, the first operand is the source and
5163 the second operand is encoded in the immediate operand. */
5164 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5175 /* FMA swaps REG and NDS. */
5176 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5184 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5186 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5188 exp
->X_op
= O_constant
;
5190 = ((i
.op
[reg_slot
].regs
->reg_num
5191 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5196 unsigned int imm_slot
;
5198 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5200 /* If VexW0 is set, the third operand is the source and
5201 the second operand is encoded in the immediate
5208 /* VexW1 is set, the second operand is the source and
5209 the third operand is encoded in the immediate
5215 if (i
.tm
.opcode_modifier
.immext
)
5217 /* When ImmExt is set, the immdiate byte is the last
5219 imm_slot
= i
.operands
- 1;
5227 /* Turn on Imm8 so that output_imm will generate it. */
5228 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5231 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5233 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5235 i
.op
[imm_slot
].imms
->X_add_number
5236 |= ((i
.op
[reg_slot
].regs
->reg_num
5237 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5241 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5242 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5244 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5249 /* i.reg_operands MUST be the number of real register operands;
5250 implicit registers do not count. If there are 3 register
5251 operands, it must be a instruction with VexNDS. For a
5252 instruction with VexNDD, the destination register is encoded
5253 in VEX prefix. If there are 4 register operands, it must be
5254 a instruction with VEX prefix and 3 sources. */
5255 if (i
.mem_operands
== 0
5256 && ((i
.reg_operands
== 2
5257 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5258 || (i
.reg_operands
== 3
5259 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5260 || (i
.reg_operands
== 4 && vex_3_sources
)))
5268 /* When there are 3 operands, one of them may be immediate,
5269 which may be the first or the last operand. Otherwise,
5270 the first operand must be shift count register (cl) or it
5271 is an instruction with VexNDS. */
5272 gas_assert (i
.imm_operands
== 1
5273 || (i
.imm_operands
== 0
5274 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5275 || i
.types
[0].bitfield
.shiftcount
)));
5276 if (operand_type_check (i
.types
[0], imm
)
5277 || i
.types
[0].bitfield
.shiftcount
)
5283 /* When there are 4 operands, the first two must be 8bit
5284 immediate operands. The source operand will be the 3rd
5287 For instructions with VexNDS, if the first operand
5288 an imm8, the source operand is the 2nd one. If the last
5289 operand is imm8, the source operand is the first one. */
5290 gas_assert ((i
.imm_operands
== 2
5291 && i
.types
[0].bitfield
.imm8
5292 && i
.types
[1].bitfield
.imm8
)
5293 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5294 && i
.imm_operands
== 1
5295 && (i
.types
[0].bitfield
.imm8
5296 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5297 if (i
.imm_operands
== 2)
5301 if (i
.types
[0].bitfield
.imm8
)
5317 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5319 /* For instructions with VexNDS, the register-only
5320 source operand must be 32/64bit integer, XMM or
5321 YMM register. It is encoded in VEX prefix. We
5322 need to clear RegMem bit before calling
5323 operand_type_equal. */
5325 i386_operand_type op
;
5328 /* Check register-only source operand when two source
5329 operands are swapped. */
5330 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
5331 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
5339 op
= i
.tm
.operand_types
[vvvv
];
5340 op
.bitfield
.regmem
= 0;
5341 if ((dest
+ 1) >= i
.operands
5342 || (op
.bitfield
.reg32
!= 1
5343 && !op
.bitfield
.reg64
!= 1
5344 && !operand_type_equal (&op
, ®xmm
)
5345 && !operand_type_equal (&op
, ®ymm
)))
5347 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
5353 /* One of the register operands will be encoded in the i.tm.reg
5354 field, the other in the combined i.tm.mode and i.tm.regmem
5355 fields. If no form of this instruction supports a memory
5356 destination operand, then we assume the source operand may
5357 sometimes be a memory operand and so we need to store the
5358 destination in the i.rm.reg field. */
5359 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5360 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5362 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5363 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5364 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5366 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5371 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5372 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5373 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5375 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5378 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5380 if (!i
.types
[0].bitfield
.control
5381 && !i
.types
[1].bitfield
.control
)
5383 i
.rex
&= ~(REX_R
| REX_B
);
5384 add_prefix (LOCK_PREFIX_OPCODE
);
5388 { /* If it's not 2 reg operands... */
5393 unsigned int fake_zero_displacement
= 0;
5396 for (op
= 0; op
< i
.operands
; op
++)
5397 if (operand_type_check (i
.types
[op
], anymem
))
5399 gas_assert (op
< i
.operands
);
5403 if (i
.base_reg
== 0)
5406 if (!i
.disp_operands
)
5407 fake_zero_displacement
= 1;
5408 if (i
.index_reg
== 0)
5410 /* Operand is just <disp> */
5411 if (flag_code
== CODE_64BIT
)
5413 /* 64bit mode overwrites the 32bit absolute
5414 addressing by RIP relative addressing and
5415 absolute addressing is encoded by one of the
5416 redundant SIB forms. */
5417 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5418 i
.sib
.base
= NO_BASE_REGISTER
;
5419 i
.sib
.index
= NO_INDEX_REGISTER
;
5420 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5421 ? disp32s
: disp32
);
5423 else if ((flag_code
== CODE_16BIT
)
5424 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5426 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5427 i
.types
[op
] = disp16
;
5431 i
.rm
.regmem
= NO_BASE_REGISTER
;
5432 i
.types
[op
] = disp32
;
5435 else /* !i.base_reg && i.index_reg */
5437 if (i
.index_reg
->reg_num
== RegEiz
5438 || i
.index_reg
->reg_num
== RegRiz
)
5439 i
.sib
.index
= NO_INDEX_REGISTER
;
5441 i
.sib
.index
= i
.index_reg
->reg_num
;
5442 i
.sib
.base
= NO_BASE_REGISTER
;
5443 i
.sib
.scale
= i
.log2_scale_factor
;
5444 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5445 i
.types
[op
].bitfield
.disp8
= 0;
5446 i
.types
[op
].bitfield
.disp16
= 0;
5447 i
.types
[op
].bitfield
.disp64
= 0;
5448 if (flag_code
!= CODE_64BIT
)
5450 /* Must be 32 bit */
5451 i
.types
[op
].bitfield
.disp32
= 1;
5452 i
.types
[op
].bitfield
.disp32s
= 0;
5456 i
.types
[op
].bitfield
.disp32
= 0;
5457 i
.types
[op
].bitfield
.disp32s
= 1;
5459 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5463 /* RIP addressing for 64bit mode. */
5464 else if (i
.base_reg
->reg_num
== RegRip
||
5465 i
.base_reg
->reg_num
== RegEip
)
5467 i
.rm
.regmem
= NO_BASE_REGISTER
;
5468 i
.types
[op
].bitfield
.disp8
= 0;
5469 i
.types
[op
].bitfield
.disp16
= 0;
5470 i
.types
[op
].bitfield
.disp32
= 0;
5471 i
.types
[op
].bitfield
.disp32s
= 1;
5472 i
.types
[op
].bitfield
.disp64
= 0;
5473 i
.flags
[op
] |= Operand_PCrel
;
5474 if (! i
.disp_operands
)
5475 fake_zero_displacement
= 1;
5477 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5479 switch (i
.base_reg
->reg_num
)
5482 if (i
.index_reg
== 0)
5484 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5485 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5489 if (i
.index_reg
== 0)
5492 if (operand_type_check (i
.types
[op
], disp
) == 0)
5494 /* fake (%bp) into 0(%bp) */
5495 i
.types
[op
].bitfield
.disp8
= 1;
5496 fake_zero_displacement
= 1;
5499 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5500 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5502 default: /* (%si) -> 4 or (%di) -> 5 */
5503 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5505 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5507 else /* i.base_reg and 32/64 bit mode */
5509 if (flag_code
== CODE_64BIT
5510 && operand_type_check (i
.types
[op
], disp
))
5512 i386_operand_type temp
;
5513 operand_type_set (&temp
, 0);
5514 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5516 if (i
.prefix
[ADDR_PREFIX
] == 0)
5517 i
.types
[op
].bitfield
.disp32s
= 1;
5519 i
.types
[op
].bitfield
.disp32
= 1;
5522 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5523 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5525 i
.sib
.base
= i
.base_reg
->reg_num
;
5526 /* x86-64 ignores REX prefix bit here to avoid decoder
5528 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5531 if (i
.disp_operands
== 0)
5533 fake_zero_displacement
= 1;
5534 i
.types
[op
].bitfield
.disp8
= 1;
5537 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5541 i
.sib
.scale
= i
.log2_scale_factor
;
5542 if (i
.index_reg
== 0)
5544 /* <disp>(%esp) becomes two byte modrm with no index
5545 register. We've already stored the code for esp
5546 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5547 Any base register besides %esp will not use the
5548 extra modrm byte. */
5549 i
.sib
.index
= NO_INDEX_REGISTER
;
5553 if (i
.index_reg
->reg_num
== RegEiz
5554 || i
.index_reg
->reg_num
== RegRiz
)
5555 i
.sib
.index
= NO_INDEX_REGISTER
;
5557 i
.sib
.index
= i
.index_reg
->reg_num
;
5558 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5559 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5564 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5565 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5568 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5571 if (fake_zero_displacement
)
5573 /* Fakes a zero displacement assuming that i.types[op]
5574 holds the correct displacement size. */
5577 gas_assert (i
.op
[op
].disps
== 0);
5578 exp
= &disp_expressions
[i
.disp_operands
++];
5579 i
.op
[op
].disps
= exp
;
5580 exp
->X_op
= O_constant
;
5581 exp
->X_add_number
= 0;
5582 exp
->X_add_symbol
= (symbolS
*) 0;
5583 exp
->X_op_symbol
= (symbolS
*) 0;
5591 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5593 if (operand_type_check (i
.types
[0], imm
))
5594 i
.vex
.register_specifier
= NULL
;
5597 /* VEX.vvvv encodes one of the sources when the first
5598 operand is not an immediate. */
5599 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5600 i
.vex
.register_specifier
= i
.op
[0].regs
;
5602 i
.vex
.register_specifier
= i
.op
[1].regs
;
5605 /* Destination is a XMM register encoded in the ModRM.reg
5607 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5608 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5611 /* ModRM.rm and VEX.B encodes the other source. */
5612 if (!i
.mem_operands
)
5616 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5617 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5619 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5621 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5625 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5627 i
.vex
.register_specifier
= i
.op
[2].regs
;
5628 if (!i
.mem_operands
)
5631 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5632 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5636 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5637 (if any) based on i.tm.extension_opcode. Again, we must be
5638 careful to make sure that segment/control/debug/test/MMX
5639 registers are coded into the i.rm.reg field. */
5640 else if (i
.reg_operands
)
5643 unsigned int vex_reg
= ~0;
5645 for (op
= 0; op
< i
.operands
; op
++)
5646 if (i
.types
[op
].bitfield
.reg8
5647 || i
.types
[op
].bitfield
.reg16
5648 || i
.types
[op
].bitfield
.reg32
5649 || i
.types
[op
].bitfield
.reg64
5650 || i
.types
[op
].bitfield
.regmmx
5651 || i
.types
[op
].bitfield
.regxmm
5652 || i
.types
[op
].bitfield
.regymm
5653 || i
.types
[op
].bitfield
.sreg2
5654 || i
.types
[op
].bitfield
.sreg3
5655 || i
.types
[op
].bitfield
.control
5656 || i
.types
[op
].bitfield
.debug
5657 || i
.types
[op
].bitfield
.test
)
5662 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5664 /* For instructions with VexNDS, the register-only
5665 source operand is encoded in VEX prefix. */
5666 gas_assert (mem
!= (unsigned int) ~0);
5671 gas_assert (op
< i
.operands
);
5675 /* Check register-only source operand when two source
5676 operands are swapped. */
5677 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
5678 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
5682 gas_assert (mem
== (vex_reg
+ 1)
5683 && op
< i
.operands
);
5688 gas_assert (vex_reg
< i
.operands
);
5692 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5694 /* For instructions with VexNDD, the register destination
5695 is encoded in VEX prefix. */
5696 if (i
.mem_operands
== 0)
5698 /* There is no memory operand. */
5699 gas_assert ((op
+ 2) == i
.operands
);
5704 /* There are only 2 operands. */
5705 gas_assert (op
< 2 && i
.operands
== 2);
5710 gas_assert (op
< i
.operands
);
5712 if (vex_reg
!= (unsigned int) ~0)
5714 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
5716 if (type
->bitfield
.reg32
!= 1
5717 && type
->bitfield
.reg64
!= 1
5718 && !operand_type_equal (type
, ®xmm
)
5719 && !operand_type_equal (type
, ®ymm
))
5722 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5725 /* Don't set OP operand twice. */
5728 /* If there is an extension opcode to put here, the
5729 register number must be put into the regmem field. */
5730 if (i
.tm
.extension_opcode
!= None
)
5732 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5733 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5738 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5739 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5744 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5745 must set it to 3 to indicate this is a register operand
5746 in the regmem field. */
5747 if (!i
.mem_operands
)
5751 /* Fill in i.rm.reg field with extension opcode (if any). */
5752 if (i
.tm
.extension_opcode
!= None
)
5753 i
.rm
.reg
= i
.tm
.extension_opcode
;
5759 output_branch (void)
5765 relax_substateT subtype
;
5769 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
5770 size
= i
.disp32_encoding
? BIG
: SMALL
;
5773 if (i
.prefix
[DATA_PREFIX
] != 0)
5779 /* Pentium4 branch hints. */
5780 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5781 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5786 if (i
.prefix
[REX_PREFIX
] != 0)
5792 if (i
.prefixes
!= 0 && !intel_syntax
)
5793 as_warn (_("skipping prefixes on this instruction"));
5795 /* It's always a symbol; End frag & setup for relax.
5796 Make sure there is enough room in this frag for the largest
5797 instruction we may generate in md_convert_frag. This is 2
5798 bytes for the opcode and room for the prefix and largest
5800 frag_grow (prefix
+ 2 + 4);
5801 /* Prefix and 1 opcode byte go in fr_fix. */
5802 p
= frag_more (prefix
+ 1);
5803 if (i
.prefix
[DATA_PREFIX
] != 0)
5804 *p
++ = DATA_PREFIX_OPCODE
;
5805 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5806 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5807 *p
++ = i
.prefix
[SEG_PREFIX
];
5808 if (i
.prefix
[REX_PREFIX
] != 0)
5809 *p
++ = i
.prefix
[REX_PREFIX
];
5810 *p
= i
.tm
.base_opcode
;
5812 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5813 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
5814 else if (cpu_arch_flags
.bitfield
.cpui386
)
5815 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
5817 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
5820 sym
= i
.op
[0].disps
->X_add_symbol
;
5821 off
= i
.op
[0].disps
->X_add_number
;
5823 if (i
.op
[0].disps
->X_op
!= O_constant
5824 && i
.op
[0].disps
->X_op
!= O_symbol
)
5826 /* Handle complex expressions. */
5827 sym
= make_expr_symbol (i
.op
[0].disps
);
5831 /* 1 possible extra opcode + 4 byte displacement go in var part.
5832 Pass reloc in fr_var. */
5833 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5843 if (i
.tm
.opcode_modifier
.jumpbyte
)
5845 /* This is a loop or jecxz type instruction. */
5847 if (i
.prefix
[ADDR_PREFIX
] != 0)
5849 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5852 /* Pentium4 branch hints. */
5853 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5854 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5856 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5865 if (flag_code
== CODE_16BIT
)
5868 if (i
.prefix
[DATA_PREFIX
] != 0)
5870 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5880 if (i
.prefix
[REX_PREFIX
] != 0)
5882 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5886 if (i
.prefixes
!= 0 && !intel_syntax
)
5887 as_warn (_("skipping prefixes on this instruction"));
5889 p
= frag_more (1 + size
);
5890 *p
++ = i
.tm
.base_opcode
;
5892 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5893 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5895 /* All jumps handled here are signed, but don't use a signed limit
5896 check for 32 and 16 bit jumps as we want to allow wrap around at
5897 4G and 64k respectively. */
5899 fixP
->fx_signed
= 1;
5903 output_interseg_jump (void)
5911 if (flag_code
== CODE_16BIT
)
5915 if (i
.prefix
[DATA_PREFIX
] != 0)
5921 if (i
.prefix
[REX_PREFIX
] != 0)
5931 if (i
.prefixes
!= 0 && !intel_syntax
)
5932 as_warn (_("skipping prefixes on this instruction"));
5934 /* 1 opcode; 2 segment; offset */
5935 p
= frag_more (prefix
+ 1 + 2 + size
);
5937 if (i
.prefix
[DATA_PREFIX
] != 0)
5938 *p
++ = DATA_PREFIX_OPCODE
;
5940 if (i
.prefix
[REX_PREFIX
] != 0)
5941 *p
++ = i
.prefix
[REX_PREFIX
];
5943 *p
++ = i
.tm
.base_opcode
;
5944 if (i
.op
[1].imms
->X_op
== O_constant
)
5946 offsetT n
= i
.op
[1].imms
->X_add_number
;
5949 && !fits_in_unsigned_word (n
)
5950 && !fits_in_signed_word (n
))
5952 as_bad (_("16-bit jump out of range"));
5955 md_number_to_chars (p
, n
, size
);
5958 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5959 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5960 if (i
.op
[0].imms
->X_op
!= O_constant
)
5961 as_bad (_("can't handle non absolute segment in `%s'"),
5963 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5969 fragS
*insn_start_frag
;
5970 offsetT insn_start_off
;
5972 /* Tie dwarf2 debug info to the address at the start of the insn.
5973 We can't do this after the insn has been output as the current
5974 frag may have been closed off. eg. by frag_var. */
5975 dwarf2_emit_insn (0);
5977 insn_start_frag
= frag_now
;
5978 insn_start_off
= frag_now_fix ();
5981 if (i
.tm
.opcode_modifier
.jump
)
5983 else if (i
.tm
.opcode_modifier
.jumpbyte
5984 || i
.tm
.opcode_modifier
.jumpdword
)
5986 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5987 output_interseg_jump ();
5990 /* Output normal instructions here. */
5994 unsigned int prefix
;
5996 /* Since the VEX prefix contains the implicit prefix, we don't
5997 need the explicit prefix. */
5998 if (!i
.tm
.opcode_modifier
.vex
)
6000 switch (i
.tm
.opcode_length
)
6003 if (i
.tm
.base_opcode
& 0xff000000)
6005 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6010 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6012 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6013 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6016 if (prefix
!= REPE_PREFIX_OPCODE
6017 || (i
.prefix
[REP_PREFIX
]
6018 != REPE_PREFIX_OPCODE
))
6019 add_prefix (prefix
);
6022 add_prefix (prefix
);
6031 /* The prefix bytes. */
6032 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6034 FRAG_APPEND_1_CHAR (*q
);
6037 if (i
.tm
.opcode_modifier
.vex
)
6039 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6044 /* REX byte is encoded in VEX prefix. */
6048 FRAG_APPEND_1_CHAR (*q
);
6051 /* There should be no other prefixes for instructions
6056 /* Now the VEX prefix. */
6057 p
= frag_more (i
.vex
.length
);
6058 for (j
= 0; j
< i
.vex
.length
; j
++)
6059 p
[j
] = i
.vex
.bytes
[j
];
6062 /* Now the opcode; be careful about word order here! */
6063 if (i
.tm
.opcode_length
== 1)
6065 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6069 switch (i
.tm
.opcode_length
)
6073 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6083 /* Put out high byte first: can't use md_number_to_chars! */
6084 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6085 *p
= i
.tm
.base_opcode
& 0xff;
6088 /* Now the modrm byte and sib byte (if present). */
6089 if (i
.tm
.opcode_modifier
.modrm
)
6091 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6094 /* If i.rm.regmem == ESP (4)
6095 && i.rm.mode != (Register mode)
6097 ==> need second modrm byte. */
6098 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6100 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6101 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6103 | i
.sib
.scale
<< 6));
6106 if (i
.disp_operands
)
6107 output_disp (insn_start_frag
, insn_start_off
);
6110 output_imm (insn_start_frag
, insn_start_off
);
6116 pi ("" /*line*/, &i
);
6118 #endif /* DEBUG386 */
6121 /* Return the size of the displacement operand N. */
6124 disp_size (unsigned int n
)
6127 if (i
.types
[n
].bitfield
.disp64
)
6129 else if (i
.types
[n
].bitfield
.disp8
)
6131 else if (i
.types
[n
].bitfield
.disp16
)
6136 /* Return the size of the immediate operand N. */
6139 imm_size (unsigned int n
)
6142 if (i
.types
[n
].bitfield
.imm64
)
6144 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6146 else if (i
.types
[n
].bitfield
.imm16
)
6152 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6157 for (n
= 0; n
< i
.operands
; n
++)
6159 if (operand_type_check (i
.types
[n
], disp
))
6161 if (i
.op
[n
].disps
->X_op
== O_constant
)
6163 int size
= disp_size (n
);
6166 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6168 p
= frag_more (size
);
6169 md_number_to_chars (p
, val
, size
);
6173 enum bfd_reloc_code_real reloc_type
;
6174 int size
= disp_size (n
);
6175 int sign
= i
.types
[n
].bitfield
.disp32s
;
6176 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6178 /* We can't have 8 bit displacement here. */
6179 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6181 /* The PC relative address is computed relative
6182 to the instruction boundary, so in case immediate
6183 fields follows, we need to adjust the value. */
6184 if (pcrel
&& i
.imm_operands
)
6189 for (n1
= 0; n1
< i
.operands
; n1
++)
6190 if (operand_type_check (i
.types
[n1
], imm
))
6192 /* Only one immediate is allowed for PC
6193 relative address. */
6194 gas_assert (sz
== 0);
6196 i
.op
[n
].disps
->X_add_number
-= sz
;
6198 /* We should find the immediate. */
6199 gas_assert (sz
!= 0);
6202 p
= frag_more (size
);
6203 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6205 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6206 && (((reloc_type
== BFD_RELOC_32
6207 || reloc_type
== BFD_RELOC_X86_64_32S
6208 || (reloc_type
== BFD_RELOC_64
6210 && (i
.op
[n
].disps
->X_op
== O_symbol
6211 || (i
.op
[n
].disps
->X_op
== O_add
6212 && ((symbol_get_value_expression
6213 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6215 || reloc_type
== BFD_RELOC_32_PCREL
))
6219 if (insn_start_frag
== frag_now
)
6220 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6225 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6226 for (fr
= insn_start_frag
->fr_next
;
6227 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6229 add
+= p
- frag_now
->fr_literal
;
6234 reloc_type
= BFD_RELOC_386_GOTPC
;
6235 i
.op
[n
].imms
->X_add_number
+= add
;
6237 else if (reloc_type
== BFD_RELOC_64
)
6238 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6240 /* Don't do the adjustment for x86-64, as there
6241 the pcrel addressing is relative to the _next_
6242 insn, and that is taken care of in other code. */
6243 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6245 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6246 i
.op
[n
].disps
, pcrel
, reloc_type
);
6253 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6258 for (n
= 0; n
< i
.operands
; n
++)
6260 if (operand_type_check (i
.types
[n
], imm
))
6262 if (i
.op
[n
].imms
->X_op
== O_constant
)
6264 int size
= imm_size (n
);
6267 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6269 p
= frag_more (size
);
6270 md_number_to_chars (p
, val
, size
);
6274 /* Not absolute_section.
6275 Need a 32-bit fixup (don't support 8bit
6276 non-absolute imms). Try to support other
6278 enum bfd_reloc_code_real reloc_type
;
6279 int size
= imm_size (n
);
6282 if (i
.types
[n
].bitfield
.imm32s
6283 && (i
.suffix
== QWORD_MNEM_SUFFIX
6284 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6289 p
= frag_more (size
);
6290 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6292 /* This is tough to explain. We end up with this one if we
6293 * have operands that look like
6294 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6295 * obtain the absolute address of the GOT, and it is strongly
6296 * preferable from a performance point of view to avoid using
6297 * a runtime relocation for this. The actual sequence of
6298 * instructions often look something like:
6303 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6305 * The call and pop essentially return the absolute address
6306 * of the label .L66 and store it in %ebx. The linker itself
6307 * will ultimately change the first operand of the addl so
6308 * that %ebx points to the GOT, but to keep things simple, the
6309 * .o file must have this operand set so that it generates not
6310 * the absolute address of .L66, but the absolute address of
6311 * itself. This allows the linker itself simply treat a GOTPC
6312 * relocation as asking for a pcrel offset to the GOT to be
6313 * added in, and the addend of the relocation is stored in the
6314 * operand field for the instruction itself.
6316 * Our job here is to fix the operand so that it would add
6317 * the correct offset so that %ebx would point to itself. The
6318 * thing that is tricky is that .-.L66 will point to the
6319 * beginning of the instruction, so we need to further modify
6320 * the operand so that it will point to itself. There are
6321 * other cases where you have something like:
6323 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6325 * and here no correction would be required. Internally in
6326 * the assembler we treat operands of this form as not being
6327 * pcrel since the '.' is explicitly mentioned, and I wonder
6328 * whether it would simplify matters to do it this way. Who
6329 * knows. In earlier versions of the PIC patches, the
6330 * pcrel_adjust field was used to store the correction, but
6331 * since the expression is not pcrel, I felt it would be
6332 * confusing to do it this way. */
6334 if ((reloc_type
== BFD_RELOC_32
6335 || reloc_type
== BFD_RELOC_X86_64_32S
6336 || reloc_type
== BFD_RELOC_64
)
6338 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6339 && (i
.op
[n
].imms
->X_op
== O_symbol
6340 || (i
.op
[n
].imms
->X_op
== O_add
6341 && ((symbol_get_value_expression
6342 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6347 if (insn_start_frag
== frag_now
)
6348 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6353 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6354 for (fr
= insn_start_frag
->fr_next
;
6355 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6357 add
+= p
- frag_now
->fr_literal
;
6361 reloc_type
= BFD_RELOC_386_GOTPC
;
6363 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6365 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6366 i
.op
[n
].imms
->X_add_number
+= add
;
6368 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6369 i
.op
[n
].imms
, 0, reloc_type
);
6375 /* x86_cons_fix_new is called via the expression parsing code when a
6376 reloc is needed. We use this hook to get the correct .got reloc. */
6377 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6378 static int cons_sign
= -1;
6381 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6384 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6386 got_reloc
= NO_RELOC
;
6389 if (exp
->X_op
== O_secrel
)
6391 exp
->X_op
= O_symbol
;
6392 r
= BFD_RELOC_32_SECREL
;
6396 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6399 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6400 # define lex_got(reloc, adjust, types) NULL
6402 /* Parse operands of the form
6403 <symbol>@GOTOFF+<nnn>
6404 and similar .plt or .got references.
6406 If we find one, set up the correct relocation in RELOC and copy the
6407 input string, minus the `@GOTOFF' into a malloc'd buffer for
6408 parsing by the calling routine. Return this buffer, and if ADJUST
6409 is non-null set it to the length of the string we removed from the
6410 input line. Otherwise return NULL. */
6412 lex_got (enum bfd_reloc_code_real
*rel
,
6414 i386_operand_type
*types
)
6416 /* Some of the relocations depend on the size of what field is to
6417 be relocated. But in our callers i386_immediate and i386_displacement
6418 we don't yet know the operand size (this will be set by insn
6419 matching). Hence we record the word32 relocation here,
6420 and adjust the reloc according to the real size in reloc(). */
6421 static const struct {
6424 const enum bfd_reloc_code_real rel
[2];
6425 const i386_operand_type types64
;
6427 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6428 BFD_RELOC_X86_64_PLTOFF64
},
6429 OPERAND_TYPE_IMM64
},
6430 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6431 BFD_RELOC_X86_64_PLT32
},
6432 OPERAND_TYPE_IMM32_32S_DISP32
},
6433 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6434 BFD_RELOC_X86_64_GOTPLT64
},
6435 OPERAND_TYPE_IMM64_DISP64
},
6436 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6437 BFD_RELOC_X86_64_GOTOFF64
},
6438 OPERAND_TYPE_IMM64_DISP64
},
6439 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6440 BFD_RELOC_X86_64_GOTPCREL
},
6441 OPERAND_TYPE_IMM32_32S_DISP32
},
6442 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6443 BFD_RELOC_X86_64_TLSGD
},
6444 OPERAND_TYPE_IMM32_32S_DISP32
},
6445 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6446 _dummy_first_bfd_reloc_code_real
},
6447 OPERAND_TYPE_NONE
},
6448 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6449 BFD_RELOC_X86_64_TLSLD
},
6450 OPERAND_TYPE_IMM32_32S_DISP32
},
6451 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6452 BFD_RELOC_X86_64_GOTTPOFF
},
6453 OPERAND_TYPE_IMM32_32S_DISP32
},
6454 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6455 BFD_RELOC_X86_64_TPOFF32
},
6456 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6457 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6458 _dummy_first_bfd_reloc_code_real
},
6459 OPERAND_TYPE_NONE
},
6460 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6461 BFD_RELOC_X86_64_DTPOFF32
},
6462 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6463 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6464 _dummy_first_bfd_reloc_code_real
},
6465 OPERAND_TYPE_NONE
},
6466 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6467 _dummy_first_bfd_reloc_code_real
},
6468 OPERAND_TYPE_NONE
},
6469 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6470 BFD_RELOC_X86_64_GOT32
},
6471 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6472 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6473 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6474 OPERAND_TYPE_IMM32_32S_DISP32
},
6475 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6476 BFD_RELOC_X86_64_TLSDESC_CALL
},
6477 OPERAND_TYPE_IMM32_32S_DISP32
},
6485 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6486 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6489 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6491 int len
= gotrel
[j
].len
;
6492 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6494 if (gotrel
[j
].rel
[object_64bit
] != 0)
6497 char *tmpbuf
, *past_reloc
;
6499 *rel
= gotrel
[j
].rel
[object_64bit
];
6505 if (flag_code
!= CODE_64BIT
)
6507 types
->bitfield
.imm32
= 1;
6508 types
->bitfield
.disp32
= 1;
6511 *types
= gotrel
[j
].types64
;
6514 if (GOT_symbol
== NULL
)
6515 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6517 /* The length of the first part of our input line. */
6518 first
= cp
- input_line_pointer
;
6520 /* The second part goes from after the reloc token until
6521 (and including) an end_of_line char or comma. */
6522 past_reloc
= cp
+ 1 + len
;
6524 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6526 second
= cp
+ 1 - past_reloc
;
6528 /* Allocate and copy string. The trailing NUL shouldn't
6529 be necessary, but be safe. */
6530 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6531 memcpy (tmpbuf
, input_line_pointer
, first
);
6532 if (second
!= 0 && *past_reloc
!= ' ')
6533 /* Replace the relocation token with ' ', so that
6534 errors like foo@GOTOFF1 will be detected. */
6535 tmpbuf
[first
++] = ' ';
6536 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6537 tmpbuf
[first
+ second
] = '\0';
6541 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6542 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6547 /* Might be a symbol version string. Don't as_bad here. */
6552 x86_cons (expressionS
*exp
, int size
)
6554 intel_syntax
= -intel_syntax
;
6557 if (size
== 4 || (object_64bit
&& size
== 8))
6559 /* Handle @GOTOFF and the like in an expression. */
6561 char *gotfree_input_line
;
6564 save
= input_line_pointer
;
6565 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6566 if (gotfree_input_line
)
6567 input_line_pointer
= gotfree_input_line
;
6571 if (gotfree_input_line
)
6573 /* expression () has merrily parsed up to the end of line,
6574 or a comma - in the wrong buffer. Transfer how far
6575 input_line_pointer has moved to the right buffer. */
6576 input_line_pointer
= (save
6577 + (input_line_pointer
- gotfree_input_line
)
6579 free (gotfree_input_line
);
6580 if (exp
->X_op
== O_constant
6581 || exp
->X_op
== O_absent
6582 || exp
->X_op
== O_illegal
6583 || exp
->X_op
== O_register
6584 || exp
->X_op
== O_big
)
6586 char c
= *input_line_pointer
;
6587 *input_line_pointer
= 0;
6588 as_bad (_("missing or invalid expression `%s'"), save
);
6589 *input_line_pointer
= c
;
6596 intel_syntax
= -intel_syntax
;
6599 i386_intel_simplify (exp
);
6604 signed_cons (int size
)
6606 if (flag_code
== CODE_64BIT
)
6614 pe_directive_secrel (dummy
)
6615 int dummy ATTRIBUTE_UNUSED
;
6622 if (exp
.X_op
== O_symbol
)
6623 exp
.X_op
= O_secrel
;
6625 emit_expr (&exp
, 4);
6627 while (*input_line_pointer
++ == ',');
6629 input_line_pointer
--;
6630 demand_empty_rest_of_line ();
6635 i386_immediate (char *imm_start
)
6637 char *save_input_line_pointer
;
6638 char *gotfree_input_line
;
6641 i386_operand_type types
;
6643 operand_type_set (&types
, ~0);
6645 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6647 as_bad (_("at most %d immediate operands are allowed"),
6648 MAX_IMMEDIATE_OPERANDS
);
6652 exp
= &im_expressions
[i
.imm_operands
++];
6653 i
.op
[this_operand
].imms
= exp
;
6655 if (is_space_char (*imm_start
))
6658 save_input_line_pointer
= input_line_pointer
;
6659 input_line_pointer
= imm_start
;
6661 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6662 if (gotfree_input_line
)
6663 input_line_pointer
= gotfree_input_line
;
6665 exp_seg
= expression (exp
);
6668 if (*input_line_pointer
)
6669 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6671 input_line_pointer
= save_input_line_pointer
;
6672 if (gotfree_input_line
)
6674 free (gotfree_input_line
);
6676 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6677 exp
->X_op
= O_illegal
;
6680 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6684 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6685 i386_operand_type types
, const char *imm_start
)
6687 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6690 as_bad (_("missing or invalid immediate expression `%s'"),
6694 else if (exp
->X_op
== O_constant
)
6696 /* Size it properly later. */
6697 i
.types
[this_operand
].bitfield
.imm64
= 1;
6698 /* If not 64bit, sign extend val. */
6699 if (flag_code
!= CODE_64BIT
6700 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6702 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6704 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6705 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6706 && exp_seg
!= absolute_section
6707 && exp_seg
!= text_section
6708 && exp_seg
!= data_section
6709 && exp_seg
!= bss_section
6710 && exp_seg
!= undefined_section
6711 && !bfd_is_com_section (exp_seg
))
6713 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6717 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6720 as_bad (_("illegal immediate register operand %s"), imm_start
);
6725 /* This is an address. The size of the address will be
6726 determined later, depending on destination register,
6727 suffix, or the default for the section. */
6728 i
.types
[this_operand
].bitfield
.imm8
= 1;
6729 i
.types
[this_operand
].bitfield
.imm16
= 1;
6730 i
.types
[this_operand
].bitfield
.imm32
= 1;
6731 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6732 i
.types
[this_operand
].bitfield
.imm64
= 1;
6733 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6741 i386_scale (char *scale
)
6744 char *save
= input_line_pointer
;
6746 input_line_pointer
= scale
;
6747 val
= get_absolute_expression ();
6752 i
.log2_scale_factor
= 0;
6755 i
.log2_scale_factor
= 1;
6758 i
.log2_scale_factor
= 2;
6761 i
.log2_scale_factor
= 3;
6765 char sep
= *input_line_pointer
;
6767 *input_line_pointer
= '\0';
6768 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6770 *input_line_pointer
= sep
;
6771 input_line_pointer
= save
;
6775 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6777 as_warn (_("scale factor of %d without an index register"),
6778 1 << i
.log2_scale_factor
);
6779 i
.log2_scale_factor
= 0;
6781 scale
= input_line_pointer
;
6782 input_line_pointer
= save
;
6787 i386_displacement (char *disp_start
, char *disp_end
)
6791 char *save_input_line_pointer
;
6792 char *gotfree_input_line
;
6794 i386_operand_type bigdisp
, types
= anydisp
;
6797 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6799 as_bad (_("at most %d displacement operands are allowed"),
6800 MAX_MEMORY_OPERANDS
);
6804 operand_type_set (&bigdisp
, 0);
6805 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6806 || (!current_templates
->start
->opcode_modifier
.jump
6807 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6809 bigdisp
.bitfield
.disp32
= 1;
6810 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6811 if (flag_code
== CODE_64BIT
)
6815 bigdisp
.bitfield
.disp32s
= 1;
6816 bigdisp
.bitfield
.disp64
= 1;
6819 else if ((flag_code
== CODE_16BIT
) ^ override
)
6821 bigdisp
.bitfield
.disp32
= 0;
6822 bigdisp
.bitfield
.disp16
= 1;
6827 /* For PC-relative branches, the width of the displacement
6828 is dependent upon data size, not address size. */
6829 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6830 if (flag_code
== CODE_64BIT
)
6832 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6833 bigdisp
.bitfield
.disp16
= 1;
6836 bigdisp
.bitfield
.disp32
= 1;
6837 bigdisp
.bitfield
.disp32s
= 1;
6843 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6845 : LONG_MNEM_SUFFIX
));
6846 bigdisp
.bitfield
.disp32
= 1;
6847 if ((flag_code
== CODE_16BIT
) ^ override
)
6849 bigdisp
.bitfield
.disp32
= 0;
6850 bigdisp
.bitfield
.disp16
= 1;
6854 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6857 exp
= &disp_expressions
[i
.disp_operands
];
6858 i
.op
[this_operand
].disps
= exp
;
6860 save_input_line_pointer
= input_line_pointer
;
6861 input_line_pointer
= disp_start
;
6862 END_STRING_AND_SAVE (disp_end
);
6864 #ifndef GCC_ASM_O_HACK
6865 #define GCC_ASM_O_HACK 0
6868 END_STRING_AND_SAVE (disp_end
+ 1);
6869 if (i
.types
[this_operand
].bitfield
.baseIndex
6870 && displacement_string_end
[-1] == '+')
6872 /* This hack is to avoid a warning when using the "o"
6873 constraint within gcc asm statements.
6876 #define _set_tssldt_desc(n,addr,limit,type) \
6877 __asm__ __volatile__ ( \
6879 "movw %w1,2+%0\n\t" \
6881 "movb %b1,4+%0\n\t" \
6882 "movb %4,5+%0\n\t" \
6883 "movb $0,6+%0\n\t" \
6884 "movb %h1,7+%0\n\t" \
6886 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6888 This works great except that the output assembler ends
6889 up looking a bit weird if it turns out that there is
6890 no offset. You end up producing code that looks like:
6903 So here we provide the missing zero. */
6905 *displacement_string_end
= '0';
6908 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6909 if (gotfree_input_line
)
6910 input_line_pointer
= gotfree_input_line
;
6912 exp_seg
= expression (exp
);
6915 if (*input_line_pointer
)
6916 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6918 RESTORE_END_STRING (disp_end
+ 1);
6920 input_line_pointer
= save_input_line_pointer
;
6921 if (gotfree_input_line
)
6923 free (gotfree_input_line
);
6925 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6926 exp
->X_op
= O_illegal
;
6929 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6931 RESTORE_END_STRING (disp_end
);
6937 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6938 i386_operand_type types
, const char *disp_start
)
6940 i386_operand_type bigdisp
;
6943 /* We do this to make sure that the section symbol is in
6944 the symbol table. We will ultimately change the relocation
6945 to be relative to the beginning of the section. */
6946 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6947 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6948 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6950 if (exp
->X_op
!= O_symbol
)
6953 if (S_IS_LOCAL (exp
->X_add_symbol
)
6954 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
6955 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
6956 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6957 exp
->X_op
= O_subtract
;
6958 exp
->X_op_symbol
= GOT_symbol
;
6959 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6960 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6961 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6962 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6964 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6967 else if (exp
->X_op
== O_absent
6968 || exp
->X_op
== O_illegal
6969 || exp
->X_op
== O_big
)
6972 as_bad (_("missing or invalid displacement expression `%s'"),
6977 else if (flag_code
== CODE_64BIT
6978 && !i
.prefix
[ADDR_PREFIX
]
6979 && exp
->X_op
== O_constant
)
6981 /* Since displacement is signed extended to 64bit, don't allow
6982 disp32 and turn off disp32s if they are out of range. */
6983 i
.types
[this_operand
].bitfield
.disp32
= 0;
6984 if (!fits_in_signed_long (exp
->X_add_number
))
6986 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6987 if (i
.types
[this_operand
].bitfield
.baseindex
)
6989 as_bad (_("0x%lx out range of signed 32bit displacement"),
6990 (long) exp
->X_add_number
);
6996 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6997 else if (exp
->X_op
!= O_constant
6998 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6999 && exp_seg
!= absolute_section
7000 && exp_seg
!= text_section
7001 && exp_seg
!= data_section
7002 && exp_seg
!= bss_section
7003 && exp_seg
!= undefined_section
7004 && !bfd_is_com_section (exp_seg
))
7006 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7011 /* Check if this is a displacement only operand. */
7012 bigdisp
= i
.types
[this_operand
];
7013 bigdisp
.bitfield
.disp8
= 0;
7014 bigdisp
.bitfield
.disp16
= 0;
7015 bigdisp
.bitfield
.disp32
= 0;
7016 bigdisp
.bitfield
.disp32s
= 0;
7017 bigdisp
.bitfield
.disp64
= 0;
7018 if (operand_type_all_zero (&bigdisp
))
7019 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7025 /* Make sure the memory operand we've been dealt is valid.
7026 Return 1 on success, 0 on a failure. */
7029 i386_index_check (const char *operand_string
)
7032 const char *kind
= "base/index";
7033 #if INFER_ADDR_PREFIX
7039 if (current_templates
->start
->opcode_modifier
.isstring
7040 && !current_templates
->start
->opcode_modifier
.immext
7041 && (current_templates
->end
[-1].opcode_modifier
.isstring
7044 /* Memory operands of string insns are special in that they only allow
7045 a single register (rDI, rSI, or rBX) as their memory address. */
7046 unsigned int expected
;
7048 kind
= "string address";
7050 if (current_templates
->start
->opcode_modifier
.w
)
7052 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
7054 if (!type
.bitfield
.baseindex
7055 || ((!i
.mem_operands
!= !intel_syntax
)
7056 && current_templates
->end
[-1].operand_types
[1]
7057 .bitfield
.baseindex
))
7058 type
= current_templates
->end
[-1].operand_types
[1];
7059 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
7062 expected
= 3 /* rBX */;
7064 if (!i
.base_reg
|| i
.index_reg
7065 || operand_type_check (i
.types
[this_operand
], disp
))
7067 else if (!(flag_code
== CODE_64BIT
7068 ? i
.prefix
[ADDR_PREFIX
]
7069 ? i
.base_reg
->reg_type
.bitfield
.reg32
7070 : i
.base_reg
->reg_type
.bitfield
.reg64
7071 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7072 ? i
.base_reg
->reg_type
.bitfield
.reg32
7073 : i
.base_reg
->reg_type
.bitfield
.reg16
))
7075 else if (i
.base_reg
->reg_num
!= expected
)
7082 for (j
= 0; j
< i386_regtab_size
; ++j
)
7083 if ((flag_code
== CODE_64BIT
7084 ? i
.prefix
[ADDR_PREFIX
]
7085 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7086 : i386_regtab
[j
].reg_type
.bitfield
.reg64
7087 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7088 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7089 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
7090 && i386_regtab
[j
].reg_num
== expected
)
7092 gas_assert (j
< i386_regtab_size
);
7093 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7095 intel_syntax
? '[' : '(',
7097 i386_regtab
[j
].reg_name
,
7098 intel_syntax
? ']' : ')');
7102 else if (flag_code
== CODE_64BIT
)
7105 && ((i
.prefix
[ADDR_PREFIX
] == 0
7106 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7107 || (i
.prefix
[ADDR_PREFIX
]
7108 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7110 || i
.base_reg
->reg_num
!=
7111 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7113 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7114 || (i
.prefix
[ADDR_PREFIX
] == 0
7115 && i
.index_reg
->reg_num
!= RegRiz
7116 && !i
.index_reg
->reg_type
.bitfield
.reg64
7118 || (i
.prefix
[ADDR_PREFIX
]
7119 && i
.index_reg
->reg_num
!= RegEiz
7120 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7125 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7129 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7130 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7132 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7133 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7135 && i
.base_reg
->reg_num
< 6
7136 && i
.index_reg
->reg_num
>= 6
7137 && i
.log2_scale_factor
== 0))))
7144 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7146 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7147 && i
.index_reg
->reg_num
!= RegEiz
)
7148 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7154 #if INFER_ADDR_PREFIX
7155 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7157 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7159 /* Change the size of any displacement too. At most one of
7160 Disp16 or Disp32 is set.
7161 FIXME. There doesn't seem to be any real need for separate
7162 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7163 Removing them would probably clean up the code quite a lot. */
7164 if (flag_code
!= CODE_64BIT
7165 && (i
.types
[this_operand
].bitfield
.disp16
7166 || i
.types
[this_operand
].bitfield
.disp32
))
7167 i
.types
[this_operand
]
7168 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7173 as_bad (_("`%s' is not a valid %s expression"),
7178 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7180 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7181 ? flag_code
== CODE_32BIT
7190 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7194 i386_att_operand (char *operand_string
)
7198 char *op_string
= operand_string
;
7200 if (is_space_char (*op_string
))
7203 /* We check for an absolute prefix (differentiating,
7204 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7205 if (*op_string
== ABSOLUTE_PREFIX
)
7208 if (is_space_char (*op_string
))
7210 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7213 /* Check if operand is a register. */
7214 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7216 i386_operand_type temp
;
7218 /* Check for a segment override by searching for ':' after a
7219 segment register. */
7221 if (is_space_char (*op_string
))
7223 if (*op_string
== ':'
7224 && (r
->reg_type
.bitfield
.sreg2
7225 || r
->reg_type
.bitfield
.sreg3
))
7230 i
.seg
[i
.mem_operands
] = &es
;
7233 i
.seg
[i
.mem_operands
] = &cs
;
7236 i
.seg
[i
.mem_operands
] = &ss
;
7239 i
.seg
[i
.mem_operands
] = &ds
;
7242 i
.seg
[i
.mem_operands
] = &fs
;
7245 i
.seg
[i
.mem_operands
] = &gs
;
7249 /* Skip the ':' and whitespace. */
7251 if (is_space_char (*op_string
))
7254 if (!is_digit_char (*op_string
)
7255 && !is_identifier_char (*op_string
)
7256 && *op_string
!= '('
7257 && *op_string
!= ABSOLUTE_PREFIX
)
7259 as_bad (_("bad memory operand `%s'"), op_string
);
7262 /* Handle case of %es:*foo. */
7263 if (*op_string
== ABSOLUTE_PREFIX
)
7266 if (is_space_char (*op_string
))
7268 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7270 goto do_memory_reference
;
7274 as_bad (_("junk `%s' after register"), op_string
);
7278 temp
.bitfield
.baseindex
= 0;
7279 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7281 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7282 i
.op
[this_operand
].regs
= r
;
7285 else if (*op_string
== REGISTER_PREFIX
)
7287 as_bad (_("bad register name `%s'"), op_string
);
7290 else if (*op_string
== IMMEDIATE_PREFIX
)
7293 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7295 as_bad (_("immediate operand illegal with absolute jump"));
7298 if (!i386_immediate (op_string
))
7301 else if (is_digit_char (*op_string
)
7302 || is_identifier_char (*op_string
)
7303 || *op_string
== '(')
7305 /* This is a memory reference of some sort. */
7308 /* Start and end of displacement string expression (if found). */
7309 char *displacement_string_start
;
7310 char *displacement_string_end
;
7312 do_memory_reference
:
7313 if ((i
.mem_operands
== 1
7314 && !current_templates
->start
->opcode_modifier
.isstring
)
7315 || i
.mem_operands
== 2)
7317 as_bad (_("too many memory references for `%s'"),
7318 current_templates
->start
->name
);
7322 /* Check for base index form. We detect the base index form by
7323 looking for an ')' at the end of the operand, searching
7324 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7326 base_string
= op_string
+ strlen (op_string
);
7329 if (is_space_char (*base_string
))
7332 /* If we only have a displacement, set-up for it to be parsed later. */
7333 displacement_string_start
= op_string
;
7334 displacement_string_end
= base_string
+ 1;
7336 if (*base_string
== ')')
7339 unsigned int parens_balanced
= 1;
7340 /* We've already checked that the number of left & right ()'s are
7341 equal, so this loop will not be infinite. */
7345 if (*base_string
== ')')
7347 if (*base_string
== '(')
7350 while (parens_balanced
);
7352 temp_string
= base_string
;
7354 /* Skip past '(' and whitespace. */
7356 if (is_space_char (*base_string
))
7359 if (*base_string
== ','
7360 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7363 displacement_string_end
= temp_string
;
7365 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7369 base_string
= end_op
;
7370 if (is_space_char (*base_string
))
7374 /* There may be an index reg or scale factor here. */
7375 if (*base_string
== ',')
7378 if (is_space_char (*base_string
))
7381 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7384 base_string
= end_op
;
7385 if (is_space_char (*base_string
))
7387 if (*base_string
== ',')
7390 if (is_space_char (*base_string
))
7393 else if (*base_string
!= ')')
7395 as_bad (_("expecting `,' or `)' "
7396 "after index register in `%s'"),
7401 else if (*base_string
== REGISTER_PREFIX
)
7403 as_bad (_("bad register name `%s'"), base_string
);
7407 /* Check for scale factor. */
7408 if (*base_string
!= ')')
7410 char *end_scale
= i386_scale (base_string
);
7415 base_string
= end_scale
;
7416 if (is_space_char (*base_string
))
7418 if (*base_string
!= ')')
7420 as_bad (_("expecting `)' "
7421 "after scale factor in `%s'"),
7426 else if (!i
.index_reg
)
7428 as_bad (_("expecting index register or scale factor "
7429 "after `,'; got '%c'"),
7434 else if (*base_string
!= ')')
7436 as_bad (_("expecting `,' or `)' "
7437 "after base register in `%s'"),
7442 else if (*base_string
== REGISTER_PREFIX
)
7444 as_bad (_("bad register name `%s'"), base_string
);
7449 /* If there's an expression beginning the operand, parse it,
7450 assuming displacement_string_start and
7451 displacement_string_end are meaningful. */
7452 if (displacement_string_start
!= displacement_string_end
)
7454 if (!i386_displacement (displacement_string_start
,
7455 displacement_string_end
))
7459 /* Special case for (%dx) while doing input/output op. */
7461 && operand_type_equal (&i
.base_reg
->reg_type
,
7462 ®16_inoutportreg
)
7464 && i
.log2_scale_factor
== 0
7465 && i
.seg
[i
.mem_operands
] == 0
7466 && !operand_type_check (i
.types
[this_operand
], disp
))
7468 i
.types
[this_operand
] = inoutportreg
;
7472 if (i386_index_check (operand_string
) == 0)
7474 i
.types
[this_operand
].bitfield
.mem
= 1;
7479 /* It's not a memory operand; argh! */
7480 as_bad (_("invalid char %s beginning operand %d `%s'"),
7481 output_invalid (*op_string
),
7486 return 1; /* Normal return. */
7489 /* md_estimate_size_before_relax()
7491 Called just before relax() for rs_machine_dependent frags. The x86
7492 assembler uses these frags to handle variable size jump
7495 Any symbol that is now undefined will not become defined.
7496 Return the correct fr_subtype in the frag.
7497 Return the initial "guess for variable size of frag" to caller.
7498 The guess is actually the growth beyond the fixed part. Whatever
7499 we do to grow the fixed or variable part contributes to our
7503 md_estimate_size_before_relax (fragP
, segment
)
7507 /* We've already got fragP->fr_subtype right; all we have to do is
7508 check for un-relaxable symbols. On an ELF system, we can't relax
7509 an externally visible symbol, because it may be overridden by a
7511 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7512 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7514 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7515 || S_IS_WEAK (fragP
->fr_symbol
)
7516 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7517 & BSF_GNU_INDIRECT_FUNCTION
))))
7519 #if defined (OBJ_COFF) && defined (TE_PE)
7520 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7521 && S_IS_WEAK (fragP
->fr_symbol
))
7525 /* Symbol is undefined in this segment, or we need to keep a
7526 reloc so that weak symbols can be overridden. */
7527 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7528 enum bfd_reloc_code_real reloc_type
;
7529 unsigned char *opcode
;
7532 if (fragP
->fr_var
!= NO_RELOC
)
7533 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7535 reloc_type
= BFD_RELOC_16_PCREL
;
7537 reloc_type
= BFD_RELOC_32_PCREL
;
7539 old_fr_fix
= fragP
->fr_fix
;
7540 opcode
= (unsigned char *) fragP
->fr_opcode
;
7542 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7545 /* Make jmp (0xeb) a (d)word displacement jump. */
7547 fragP
->fr_fix
+= size
;
7548 fix_new (fragP
, old_fr_fix
, size
,
7550 fragP
->fr_offset
, 1,
7556 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7558 /* Negate the condition, and branch past an
7559 unconditional jump. */
7562 /* Insert an unconditional jump. */
7564 /* We added two extra opcode bytes, and have a two byte
7566 fragP
->fr_fix
+= 2 + 2;
7567 fix_new (fragP
, old_fr_fix
+ 2, 2,
7569 fragP
->fr_offset
, 1,
7576 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7581 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7583 fragP
->fr_offset
, 1,
7585 fixP
->fx_signed
= 1;
7589 /* This changes the byte-displacement jump 0x7N
7590 to the (d)word-displacement jump 0x0f,0x8N. */
7591 opcode
[1] = opcode
[0] + 0x10;
7592 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7593 /* We've added an opcode byte. */
7594 fragP
->fr_fix
+= 1 + size
;
7595 fix_new (fragP
, old_fr_fix
+ 1, size
,
7597 fragP
->fr_offset
, 1,
7602 BAD_CASE (fragP
->fr_subtype
);
7606 return fragP
->fr_fix
- old_fr_fix
;
7609 /* Guess size depending on current relax state. Initially the relax
7610 state will correspond to a short jump and we return 1, because
7611 the variable part of the frag (the branch offset) is one byte
7612 long. However, we can relax a section more than once and in that
7613 case we must either set fr_subtype back to the unrelaxed state,
7614 or return the value for the appropriate branch. */
7615 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7618 /* Called after relax() is finished.
7620 In: Address of frag.
7621 fr_type == rs_machine_dependent.
7622 fr_subtype is what the address relaxed to.
7624 Out: Any fixSs and constants are set up.
7625 Caller will turn frag into a ".space 0". */
7628 md_convert_frag (abfd
, sec
, fragP
)
7629 bfd
*abfd ATTRIBUTE_UNUSED
;
7630 segT sec ATTRIBUTE_UNUSED
;
7633 unsigned char *opcode
;
7634 unsigned char *where_to_put_displacement
= NULL
;
7635 offsetT target_address
;
7636 offsetT opcode_address
;
7637 unsigned int extension
= 0;
7638 offsetT displacement_from_opcode_start
;
7640 opcode
= (unsigned char *) fragP
->fr_opcode
;
7642 /* Address we want to reach in file space. */
7643 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7645 /* Address opcode resides at in file space. */
7646 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7648 /* Displacement from opcode start to fill into instruction. */
7649 displacement_from_opcode_start
= target_address
- opcode_address
;
7651 if ((fragP
->fr_subtype
& BIG
) == 0)
7653 /* Don't have to change opcode. */
7654 extension
= 1; /* 1 opcode + 1 displacement */
7655 where_to_put_displacement
= &opcode
[1];
7659 if (no_cond_jump_promotion
7660 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7661 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7662 _("long jump required"));
7664 switch (fragP
->fr_subtype
)
7666 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7667 extension
= 4; /* 1 opcode + 4 displacement */
7669 where_to_put_displacement
= &opcode
[1];
7672 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7673 extension
= 2; /* 1 opcode + 2 displacement */
7675 where_to_put_displacement
= &opcode
[1];
7678 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7679 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7680 extension
= 5; /* 2 opcode + 4 displacement */
7681 opcode
[1] = opcode
[0] + 0x10;
7682 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7683 where_to_put_displacement
= &opcode
[2];
7686 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7687 extension
= 3; /* 2 opcode + 2 displacement */
7688 opcode
[1] = opcode
[0] + 0x10;
7689 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7690 where_to_put_displacement
= &opcode
[2];
7693 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7698 where_to_put_displacement
= &opcode
[3];
7702 BAD_CASE (fragP
->fr_subtype
);
7707 /* If size if less then four we are sure that the operand fits,
7708 but if it's 4, then it could be that the displacement is larger
7710 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7712 && ((addressT
) (displacement_from_opcode_start
- extension
7713 + ((addressT
) 1 << 31))
7714 > (((addressT
) 2 << 31) - 1)))
7716 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7717 _("jump target out of range"));
7718 /* Make us emit 0. */
7719 displacement_from_opcode_start
= extension
;
7721 /* Now put displacement after opcode. */
7722 md_number_to_chars ((char *) where_to_put_displacement
,
7723 (valueT
) (displacement_from_opcode_start
- extension
),
7724 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7725 fragP
->fr_fix
+= extension
;
7728 /* Apply a fixup (fixS) to segment data, once it has been determined
7729 by our caller that we have all the info we need to fix it up.
7731 On the 386, immediates, displacements, and data pointers are all in
7732 the same (little-endian) format, so we don't need to care about which
7736 md_apply_fix (fixP
, valP
, seg
)
7737 /* The fix we're to put in. */
7739 /* Pointer to the value of the bits. */
7741 /* Segment fix is from. */
7742 segT seg ATTRIBUTE_UNUSED
;
7744 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7745 valueT value
= *valP
;
7747 #if !defined (TE_Mach)
7750 switch (fixP
->fx_r_type
)
7756 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7759 case BFD_RELOC_X86_64_32S
:
7760 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7763 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7766 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7771 if (fixP
->fx_addsy
!= NULL
7772 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7773 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7774 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7775 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7776 && !use_rela_relocations
)
7778 /* This is a hack. There should be a better way to handle this.
7779 This covers for the fact that bfd_install_relocation will
7780 subtract the current location (for partial_inplace, PC relative
7781 relocations); see more below. */
7785 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7788 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7790 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7793 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7796 || (symbol_section_p (fixP
->fx_addsy
)
7797 && sym_seg
!= absolute_section
))
7798 && !generic_force_reloc (fixP
))
7800 /* Yes, we add the values in twice. This is because
7801 bfd_install_relocation subtracts them out again. I think
7802 bfd_install_relocation is broken, but I don't dare change
7804 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7808 #if defined (OBJ_COFF) && defined (TE_PE)
7809 /* For some reason, the PE format does not store a
7810 section address offset for a PC relative symbol. */
7811 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7812 || S_IS_WEAK (fixP
->fx_addsy
))
7813 value
+= md_pcrel_from (fixP
);
7816 #if defined (OBJ_COFF) && defined (TE_PE)
7817 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7819 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7823 /* Fix a few things - the dynamic linker expects certain values here,
7824 and we must not disappoint it. */
7825 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7826 if (IS_ELF
&& fixP
->fx_addsy
)
7827 switch (fixP
->fx_r_type
)
7829 case BFD_RELOC_386_PLT32
:
7830 case BFD_RELOC_X86_64_PLT32
:
7831 /* Make the jump instruction point to the address of the operand. At
7832 runtime we merely add the offset to the actual PLT entry. */
7836 case BFD_RELOC_386_TLS_GD
:
7837 case BFD_RELOC_386_TLS_LDM
:
7838 case BFD_RELOC_386_TLS_IE_32
:
7839 case BFD_RELOC_386_TLS_IE
:
7840 case BFD_RELOC_386_TLS_GOTIE
:
7841 case BFD_RELOC_386_TLS_GOTDESC
:
7842 case BFD_RELOC_X86_64_TLSGD
:
7843 case BFD_RELOC_X86_64_TLSLD
:
7844 case BFD_RELOC_X86_64_GOTTPOFF
:
7845 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7846 value
= 0; /* Fully resolved at runtime. No addend. */
7848 case BFD_RELOC_386_TLS_LE
:
7849 case BFD_RELOC_386_TLS_LDO_32
:
7850 case BFD_RELOC_386_TLS_LE_32
:
7851 case BFD_RELOC_X86_64_DTPOFF32
:
7852 case BFD_RELOC_X86_64_DTPOFF64
:
7853 case BFD_RELOC_X86_64_TPOFF32
:
7854 case BFD_RELOC_X86_64_TPOFF64
:
7855 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7858 case BFD_RELOC_386_TLS_DESC_CALL
:
7859 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7860 value
= 0; /* Fully resolved at runtime. No addend. */
7861 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7865 case BFD_RELOC_386_GOT32
:
7866 case BFD_RELOC_X86_64_GOT32
:
7867 value
= 0; /* Fully resolved at runtime. No addend. */
7870 case BFD_RELOC_VTABLE_INHERIT
:
7871 case BFD_RELOC_VTABLE_ENTRY
:
7878 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7880 #endif /* !defined (TE_Mach) */
7882 /* Are we finished with this relocation now? */
7883 if (fixP
->fx_addsy
== NULL
)
7885 #if defined (OBJ_COFF) && defined (TE_PE)
7886 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7889 /* Remember value for tc_gen_reloc. */
7890 fixP
->fx_addnumber
= value
;
7891 /* Clear out the frag for now. */
7895 else if (use_rela_relocations
)
7897 fixP
->fx_no_overflow
= 1;
7898 /* Remember value for tc_gen_reloc. */
7899 fixP
->fx_addnumber
= value
;
7903 md_number_to_chars (p
, value
, fixP
->fx_size
);
7907 md_atof (int type
, char *litP
, int *sizeP
)
7909 /* This outputs the LITTLENUMs in REVERSE order;
7910 in accord with the bigendian 386. */
7911 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7914 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7917 output_invalid (int c
)
7920 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7923 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7924 "(0x%x)", (unsigned char) c
);
7925 return output_invalid_buf
;
7928 /* REG_STRING starts *before* REGISTER_PREFIX. */
7930 static const reg_entry
*
7931 parse_real_register (char *reg_string
, char **end_op
)
7933 char *s
= reg_string
;
7935 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7938 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7939 if (*s
== REGISTER_PREFIX
)
7942 if (is_space_char (*s
))
7946 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7948 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7949 return (const reg_entry
*) NULL
;
7953 /* For naked regs, make sure that we are not dealing with an identifier.
7954 This prevents confusing an identifier like `eax_var' with register
7956 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7957 return (const reg_entry
*) NULL
;
7961 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7963 /* Handle floating point regs, allowing spaces in the (i) part. */
7964 if (r
== i386_regtab
/* %st is first entry of table */)
7966 if (is_space_char (*s
))
7971 if (is_space_char (*s
))
7973 if (*s
>= '0' && *s
<= '7')
7977 if (is_space_char (*s
))
7982 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7987 /* We have "%st(" then garbage. */
7988 return (const reg_entry
*) NULL
;
7992 if (r
== NULL
|| allow_pseudo_reg
)
7995 if (operand_type_all_zero (&r
->reg_type
))
7996 return (const reg_entry
*) NULL
;
7998 if ((r
->reg_type
.bitfield
.reg32
7999 || r
->reg_type
.bitfield
.sreg3
8000 || r
->reg_type
.bitfield
.control
8001 || r
->reg_type
.bitfield
.debug
8002 || r
->reg_type
.bitfield
.test
)
8003 && !cpu_arch_flags
.bitfield
.cpui386
)
8004 return (const reg_entry
*) NULL
;
8006 if (r
->reg_type
.bitfield
.floatreg
8007 && !cpu_arch_flags
.bitfield
.cpu8087
8008 && !cpu_arch_flags
.bitfield
.cpu287
8009 && !cpu_arch_flags
.bitfield
.cpu387
)
8010 return (const reg_entry
*) NULL
;
8012 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
8013 return (const reg_entry
*) NULL
;
8015 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
8016 return (const reg_entry
*) NULL
;
8018 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
8019 return (const reg_entry
*) NULL
;
8021 /* Don't allow fake index register unless allow_index_reg isn't 0. */
8022 if (!allow_index_reg
8023 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
8024 return (const reg_entry
*) NULL
;
8026 if (((r
->reg_flags
& (RegRex64
| RegRex
))
8027 || r
->reg_type
.bitfield
.reg64
)
8028 && (!cpu_arch_flags
.bitfield
.cpulm
8029 || !operand_type_equal (&r
->reg_type
, &control
))
8030 && flag_code
!= CODE_64BIT
)
8031 return (const reg_entry
*) NULL
;
8033 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
8034 return (const reg_entry
*) NULL
;
8039 /* REG_STRING starts *before* REGISTER_PREFIX. */
8041 static const reg_entry
*
8042 parse_register (char *reg_string
, char **end_op
)
8046 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
8047 r
= parse_real_register (reg_string
, end_op
);
8052 char *save
= input_line_pointer
;
8056 input_line_pointer
= reg_string
;
8057 c
= get_symbol_end ();
8058 symbolP
= symbol_find (reg_string
);
8059 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
8061 const expressionS
*e
= symbol_get_value_expression (symbolP
);
8063 know (e
->X_op
== O_register
);
8064 know (e
->X_add_number
>= 0
8065 && (valueT
) e
->X_add_number
< i386_regtab_size
);
8066 r
= i386_regtab
+ e
->X_add_number
;
8067 *end_op
= input_line_pointer
;
8069 *input_line_pointer
= c
;
8070 input_line_pointer
= save
;
8076 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8079 char *end
= input_line_pointer
;
8082 r
= parse_register (name
, &input_line_pointer
);
8083 if (r
&& end
<= input_line_pointer
)
8085 *nextcharP
= *input_line_pointer
;
8086 *input_line_pointer
= 0;
8087 e
->X_op
= O_register
;
8088 e
->X_add_number
= r
- i386_regtab
;
8091 input_line_pointer
= end
;
8093 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8097 md_operand (expressionS
*e
)
8102 switch (*input_line_pointer
)
8104 case REGISTER_PREFIX
:
8105 r
= parse_real_register (input_line_pointer
, &end
);
8108 e
->X_op
= O_register
;
8109 e
->X_add_number
= r
- i386_regtab
;
8110 input_line_pointer
= end
;
8115 gas_assert (intel_syntax
);
8116 end
= input_line_pointer
++;
8118 if (*input_line_pointer
== ']')
8120 ++input_line_pointer
;
8121 e
->X_op_symbol
= make_expr_symbol (e
);
8122 e
->X_add_symbol
= NULL
;
8123 e
->X_add_number
= 0;
8129 input_line_pointer
= end
;
8136 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8137 const char *md_shortopts
= "kVQ:sqn";
8139 const char *md_shortopts
= "qn";
8142 #define OPTION_32 (OPTION_MD_BASE + 0)
8143 #define OPTION_64 (OPTION_MD_BASE + 1)
8144 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8145 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8146 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8147 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8148 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8149 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8150 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8151 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8152 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8153 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8154 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
8155 #define OPTION_N32 (OPTION_MD_BASE + 13)
8157 struct option md_longopts
[] =
8159 {"32", no_argument
, NULL
, OPTION_32
},
8160 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8161 || defined (TE_PE) || defined (TE_PEP))
8162 {"64", no_argument
, NULL
, OPTION_64
},
8164 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8165 {"n32", no_argument
, NULL
, OPTION_N32
},
8167 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8168 {"march", required_argument
, NULL
, OPTION_MARCH
},
8169 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8170 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8171 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8172 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8173 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8174 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8175 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8176 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8177 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8178 {NULL
, no_argument
, NULL
, 0}
8180 size_t md_longopts_size
= sizeof (md_longopts
);
8183 md_parse_option (int c
, char *arg
)
8191 optimize_align_code
= 0;
8198 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8199 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8200 should be emitted or not. FIXME: Not implemented. */
8204 /* -V: SVR4 argument to print version ID. */
8206 print_version_id ();
8209 /* -k: Ignore for FreeBSD compatibility. */
8214 /* -s: On i386 Solaris, this tells the native assembler to use
8215 .stab instead of .stab.excl. We always use .stab anyhow. */
8218 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8219 || defined (TE_PE) || defined (TE_PEP))
8222 const char **list
, **l
;
8224 list
= bfd_target_list ();
8225 for (l
= list
; *l
!= NULL
; l
++)
8226 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8227 || strcmp (*l
, "coff-x86-64") == 0
8228 || strcmp (*l
, "pe-x86-64") == 0
8229 || strcmp (*l
, "pei-x86-64") == 0)
8231 default_arch
= "x86_64";
8235 as_fatal (_("No compiled in support for x86_64"));
8241 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8245 const char **list
, **l
;
8247 list
= bfd_target_list ();
8248 for (l
= list
; *l
!= NULL
; l
++)
8249 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
8251 default_arch
= "x86_64:32";
8255 as_fatal (_("No compiled in support for 32bit x86_64"));
8259 as_fatal (_("32bit x86_64 is only supported for ELF"));
8264 default_arch
= "i386";
8268 #ifdef SVR4_COMMENT_CHARS
8273 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8275 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8279 i386_comment_chars
= n
;
8285 arch
= xstrdup (arg
);
8289 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8290 next
= strchr (arch
, '+');
8293 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8295 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8298 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8301 cpu_arch_name
= cpu_arch
[j
].name
;
8302 cpu_sub_arch_name
= NULL
;
8303 cpu_arch_flags
= cpu_arch
[j
].flags
;
8304 cpu_arch_isa
= cpu_arch
[j
].type
;
8305 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8306 if (!cpu_arch_tune_set
)
8308 cpu_arch_tune
= cpu_arch_isa
;
8309 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8313 else if (*cpu_arch
[j
].name
== '.'
8314 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8316 /* ISA entension. */
8317 i386_cpu_flags flags
;
8319 if (!cpu_arch
[j
].negated
)
8320 flags
= cpu_flags_or (cpu_arch_flags
,
8323 flags
= cpu_flags_and_not (cpu_arch_flags
,
8325 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8327 if (cpu_sub_arch_name
)
8329 char *name
= cpu_sub_arch_name
;
8330 cpu_sub_arch_name
= concat (name
,
8332 (const char *) NULL
);
8336 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8337 cpu_arch_flags
= flags
;
8343 if (j
>= ARRAY_SIZE (cpu_arch
))
8344 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8348 while (next
!= NULL
);
8353 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8354 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8356 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8358 cpu_arch_tune_set
= 1;
8359 cpu_arch_tune
= cpu_arch
[j
].type
;
8360 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8364 if (j
>= ARRAY_SIZE (cpu_arch
))
8365 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8368 case OPTION_MMNEMONIC
:
8369 if (strcasecmp (arg
, "att") == 0)
8371 else if (strcasecmp (arg
, "intel") == 0)
8374 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8377 case OPTION_MSYNTAX
:
8378 if (strcasecmp (arg
, "att") == 0)
8380 else if (strcasecmp (arg
, "intel") == 0)
8383 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8386 case OPTION_MINDEX_REG
:
8387 allow_index_reg
= 1;
8390 case OPTION_MNAKED_REG
:
8391 allow_naked_reg
= 1;
8394 case OPTION_MOLD_GCC
:
8398 case OPTION_MSSE2AVX
:
8402 case OPTION_MSSE_CHECK
:
8403 if (strcasecmp (arg
, "error") == 0)
8404 sse_check
= sse_check_error
;
8405 else if (strcasecmp (arg
, "warning") == 0)
8406 sse_check
= sse_check_warning
;
8407 else if (strcasecmp (arg
, "none") == 0)
8408 sse_check
= sse_check_none
;
8410 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8413 case OPTION_MAVXSCALAR
:
8414 if (strcasecmp (arg
, "128") == 0)
8416 else if (strcasecmp (arg
, "256") == 0)
8419 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg
);
8428 #define MESSAGE_TEMPLATE \
8432 show_arch (FILE *stream
, int ext
, int check
)
8434 static char message
[] = MESSAGE_TEMPLATE
;
8435 char *start
= message
+ 27;
8437 int size
= sizeof (MESSAGE_TEMPLATE
);
8444 left
= size
- (start
- message
);
8445 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8447 /* Should it be skipped? */
8448 if (cpu_arch
[j
].skip
)
8451 name
= cpu_arch
[j
].name
;
8452 len
= cpu_arch
[j
].len
;
8455 /* It is an extension. Skip if we aren't asked to show it. */
8466 /* It is an processor. Skip if we show only extension. */
8469 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8471 /* It is an impossible processor - skip. */
8475 /* Reserve 2 spaces for ", " or ",\0" */
8478 /* Check if there is any room. */
8486 p
= mempcpy (p
, name
, len
);
8490 /* Output the current message now and start a new one. */
8493 fprintf (stream
, "%s\n", message
);
8495 left
= size
- (start
- message
) - len
- 2;
8497 gas_assert (left
>= 0);
8499 p
= mempcpy (p
, name
, len
);
8504 fprintf (stream
, "%s\n", message
);
8508 md_show_usage (FILE *stream
)
8510 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8511 fprintf (stream
, _("\
8513 -V print assembler version number\n\
8516 fprintf (stream
, _("\
8517 -n Do not optimize code alignment\n\
8518 -q quieten some warnings\n"));
8519 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8520 fprintf (stream
, _("\
8523 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8524 || defined (TE_PE) || defined (TE_PEP))
8525 fprintf (stream
, _("\
8526 --32/--64/--n32 generate 32bit/64bit/n32bit code\n"));
8528 #ifdef SVR4_COMMENT_CHARS
8529 fprintf (stream
, _("\
8530 --divide do not treat `/' as a comment character\n"));
8532 fprintf (stream
, _("\
8533 --divide ignored\n"));
8535 fprintf (stream
, _("\
8536 -march=CPU[,+EXTENSION...]\n\
8537 generate code for CPU and EXTENSION, CPU is one of:\n"));
8538 show_arch (stream
, 0, 1);
8539 fprintf (stream
, _("\
8540 EXTENSION is combination of:\n"));
8541 show_arch (stream
, 1, 0);
8542 fprintf (stream
, _("\
8543 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8544 show_arch (stream
, 0, 0);
8545 fprintf (stream
, _("\
8546 -msse2avx encode SSE instructions with VEX prefix\n"));
8547 fprintf (stream
, _("\
8548 -msse-check=[none|error|warning]\n\
8549 check SSE instructions\n"));
8550 fprintf (stream
, _("\
8551 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8553 fprintf (stream
, _("\
8554 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8555 fprintf (stream
, _("\
8556 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8557 fprintf (stream
, _("\
8558 -mindex-reg support pseudo index registers\n"));
8559 fprintf (stream
, _("\
8560 -mnaked-reg don't require `%%' prefix for registers\n"));
8561 fprintf (stream
, _("\
8562 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8565 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8566 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8567 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8569 /* Pick the target format to use. */
8572 i386_target_format (void)
8574 if (!strncmp (default_arch
, "x86_64", 6))
8576 update_code_flag (CODE_64BIT
, 1);
8577 if (default_arch
[6] == '\0')
8578 x86_elf_abi
= X86_64_LP64_ABI
;
8580 x86_elf_abi
= X86_64_ILP32_ABI
;
8582 else if (!strcmp (default_arch
, "i386"))
8583 update_code_flag (CODE_32BIT
, 1);
8585 as_fatal (_("Unknown architecture"));
8587 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8588 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8589 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8590 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8592 switch (OUTPUT_FLAVOR
)
8594 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8595 case bfd_target_aout_flavour
:
8596 return AOUT_TARGET_FORMAT
;
8598 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8599 # if defined (TE_PE) || defined (TE_PEP)
8600 case bfd_target_coff_flavour
:
8601 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8602 # elif defined (TE_GO32)
8603 case bfd_target_coff_flavour
:
8606 case bfd_target_coff_flavour
:
8610 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8611 case bfd_target_elf_flavour
:
8615 switch (x86_elf_abi
)
8618 format
= ELF_TARGET_FORMAT
;
8620 case X86_64_LP64_ABI
:
8621 use_rela_relocations
= 1;
8623 format
= ELF_TARGET_FORMAT64
;
8625 case X86_64_ILP32_ABI
:
8626 use_rela_relocations
= 1;
8628 format
= ELF_TARGET_FORMAT32
;
8631 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8633 if (x86_elf_abi
!= X86_64_LP64_ABI
)
8634 as_fatal (_("Intel L1OM is 64bit only"));
8635 return ELF_TARGET_L1OM_FORMAT
;
8641 #if defined (OBJ_MACH_O)
8642 case bfd_target_mach_o_flavour
:
8643 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8651 #endif /* OBJ_MAYBE_ more than one */
8653 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8655 i386_elf_emit_arch_note (void)
8657 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8660 asection
*seg
= now_seg
;
8661 subsegT subseg
= now_subseg
;
8662 Elf_Internal_Note i_note
;
8663 Elf_External_Note e_note
;
8664 asection
*note_secp
;
8667 /* Create the .note section. */
8668 note_secp
= subseg_new (".note", 0);
8669 bfd_set_section_flags (stdoutput
,
8671 SEC_HAS_CONTENTS
| SEC_READONLY
);
8673 /* Process the arch string. */
8674 len
= strlen (cpu_arch_name
);
8676 i_note
.namesz
= len
+ 1;
8678 i_note
.type
= NT_ARCH
;
8679 p
= frag_more (sizeof (e_note
.namesz
));
8680 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8681 p
= frag_more (sizeof (e_note
.descsz
));
8682 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8683 p
= frag_more (sizeof (e_note
.type
));
8684 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8685 p
= frag_more (len
+ 1);
8686 strcpy (p
, cpu_arch_name
);
8688 frag_align (2, 0, 0);
8690 subseg_set (seg
, subseg
);
8696 md_undefined_symbol (name
)
8699 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8700 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8701 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8702 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8706 if (symbol_find (name
))
8707 as_bad (_("GOT already in symbol table"));
8708 GOT_symbol
= symbol_new (name
, undefined_section
,
8709 (valueT
) 0, &zero_address_frag
);
8716 /* Round up a section size to the appropriate boundary. */
8719 md_section_align (segment
, size
)
8720 segT segment ATTRIBUTE_UNUSED
;
8723 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8724 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8726 /* For a.out, force the section size to be aligned. If we don't do
8727 this, BFD will align it for us, but it will not write out the
8728 final bytes of the section. This may be a bug in BFD, but it is
8729 easier to fix it here since that is how the other a.out targets
8733 align
= bfd_get_section_alignment (stdoutput
, segment
);
8734 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8741 /* On the i386, PC-relative offsets are relative to the start of the
8742 next instruction. That is, the address of the offset, plus its
8743 size, since the offset is always the last part of the insn. */
8746 md_pcrel_from (fixS
*fixP
)
8748 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8754 s_bss (int ignore ATTRIBUTE_UNUSED
)
8758 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8760 obj_elf_section_change_hook ();
8762 temp
= get_absolute_expression ();
8763 subseg_set (bss_section
, (subsegT
) temp
);
8764 demand_empty_rest_of_line ();
8770 i386_validate_fix (fixS
*fixp
)
8772 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8774 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8778 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8783 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8785 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8792 tc_gen_reloc (section
, fixp
)
8793 asection
*section ATTRIBUTE_UNUSED
;
8797 bfd_reloc_code_real_type code
;
8799 switch (fixp
->fx_r_type
)
8801 case BFD_RELOC_X86_64_PLT32
:
8802 case BFD_RELOC_X86_64_GOT32
:
8803 case BFD_RELOC_X86_64_GOTPCREL
:
8804 case BFD_RELOC_386_PLT32
:
8805 case BFD_RELOC_386_GOT32
:
8806 case BFD_RELOC_386_GOTOFF
:
8807 case BFD_RELOC_386_GOTPC
:
8808 case BFD_RELOC_386_TLS_GD
:
8809 case BFD_RELOC_386_TLS_LDM
:
8810 case BFD_RELOC_386_TLS_LDO_32
:
8811 case BFD_RELOC_386_TLS_IE_32
:
8812 case BFD_RELOC_386_TLS_IE
:
8813 case BFD_RELOC_386_TLS_GOTIE
:
8814 case BFD_RELOC_386_TLS_LE_32
:
8815 case BFD_RELOC_386_TLS_LE
:
8816 case BFD_RELOC_386_TLS_GOTDESC
:
8817 case BFD_RELOC_386_TLS_DESC_CALL
:
8818 case BFD_RELOC_X86_64_TLSGD
:
8819 case BFD_RELOC_X86_64_TLSLD
:
8820 case BFD_RELOC_X86_64_DTPOFF32
:
8821 case BFD_RELOC_X86_64_DTPOFF64
:
8822 case BFD_RELOC_X86_64_GOTTPOFF
:
8823 case BFD_RELOC_X86_64_TPOFF32
:
8824 case BFD_RELOC_X86_64_TPOFF64
:
8825 case BFD_RELOC_X86_64_GOTOFF64
:
8826 case BFD_RELOC_X86_64_GOTPC32
:
8827 case BFD_RELOC_X86_64_GOT64
:
8828 case BFD_RELOC_X86_64_GOTPCREL64
:
8829 case BFD_RELOC_X86_64_GOTPC64
:
8830 case BFD_RELOC_X86_64_GOTPLT64
:
8831 case BFD_RELOC_X86_64_PLTOFF64
:
8832 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8833 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8835 case BFD_RELOC_VTABLE_ENTRY
:
8836 case BFD_RELOC_VTABLE_INHERIT
:
8838 case BFD_RELOC_32_SECREL
:
8840 code
= fixp
->fx_r_type
;
8842 case BFD_RELOC_X86_64_32S
:
8843 if (!fixp
->fx_pcrel
)
8845 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8846 code
= fixp
->fx_r_type
;
8852 switch (fixp
->fx_size
)
8855 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8856 _("can not do %d byte pc-relative relocation"),
8858 code
= BFD_RELOC_32_PCREL
;
8860 case 1: code
= BFD_RELOC_8_PCREL
; break;
8861 case 2: code
= BFD_RELOC_16_PCREL
; break;
8862 case 4: code
= BFD_RELOC_32_PCREL
; break;
8864 case 8: code
= BFD_RELOC_64_PCREL
; break;
8870 switch (fixp
->fx_size
)
8873 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8874 _("can not do %d byte relocation"),
8876 code
= BFD_RELOC_32
;
8878 case 1: code
= BFD_RELOC_8
; break;
8879 case 2: code
= BFD_RELOC_16
; break;
8880 case 4: code
= BFD_RELOC_32
; break;
8882 case 8: code
= BFD_RELOC_64
; break;
8889 if ((code
== BFD_RELOC_32
8890 || code
== BFD_RELOC_32_PCREL
8891 || code
== BFD_RELOC_X86_64_32S
)
8893 && fixp
->fx_addsy
== GOT_symbol
)
8896 code
= BFD_RELOC_386_GOTPC
;
8898 code
= BFD_RELOC_X86_64_GOTPC32
;
8900 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8902 && fixp
->fx_addsy
== GOT_symbol
)
8904 code
= BFD_RELOC_X86_64_GOTPC64
;
8907 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8908 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8909 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8911 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8913 if (!use_rela_relocations
)
8915 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8916 vtable entry to be used in the relocation's section offset. */
8917 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8918 rel
->address
= fixp
->fx_offset
;
8919 #if defined (OBJ_COFF) && defined (TE_PE)
8920 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8921 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8926 /* Use the rela in 64bit mode. */
8929 if (!fixp
->fx_pcrel
)
8930 rel
->addend
= fixp
->fx_offset
;
8934 case BFD_RELOC_X86_64_PLT32
:
8935 case BFD_RELOC_X86_64_GOT32
:
8936 case BFD_RELOC_X86_64_GOTPCREL
:
8937 case BFD_RELOC_X86_64_TLSGD
:
8938 case BFD_RELOC_X86_64_TLSLD
:
8939 case BFD_RELOC_X86_64_GOTTPOFF
:
8940 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8941 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8942 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8945 rel
->addend
= (section
->vma
8947 + fixp
->fx_addnumber
8948 + md_pcrel_from (fixp
));
8953 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8954 if (rel
->howto
== NULL
)
8956 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8957 _("cannot represent relocation type %s"),
8958 bfd_get_reloc_code_name (code
));
8959 /* Set howto to a garbage value so that we can keep going. */
8960 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8961 gas_assert (rel
->howto
!= NULL
);
8967 #include "tc-i386-intel.c"
8970 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8972 int saved_naked_reg
;
8973 char saved_register_dot
;
8975 saved_naked_reg
= allow_naked_reg
;
8976 allow_naked_reg
= 1;
8977 saved_register_dot
= register_chars
['.'];
8978 register_chars
['.'] = '.';
8979 allow_pseudo_reg
= 1;
8980 expression_and_evaluate (exp
);
8981 allow_pseudo_reg
= 0;
8982 register_chars
['.'] = saved_register_dot
;
8983 allow_naked_reg
= saved_naked_reg
;
8985 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8987 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8989 exp
->X_op
= O_constant
;
8990 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8991 .dw2_regnum
[flag_code
>> 1];
8994 exp
->X_op
= O_illegal
;
8999 tc_x86_frame_initial_instructions (void)
9001 static unsigned int sp_regno
[2];
9003 if (!sp_regno
[flag_code
>> 1])
9005 char *saved_input
= input_line_pointer
;
9006 char sp
[][4] = {"esp", "rsp"};
9009 input_line_pointer
= sp
[flag_code
>> 1];
9010 tc_x86_parse_to_dw2regnum (&exp
);
9011 gas_assert (exp
.X_op
== O_constant
);
9012 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9013 input_line_pointer
= saved_input
;
9016 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9017 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9021 i386_elf_section_type (const char *str
, size_t len
)
9023 if (flag_code
== CODE_64BIT
9024 && len
== sizeof ("unwind") - 1
9025 && strncmp (str
, "unwind", 6) == 0)
9026 return SHT_X86_64_UNWIND
;
9033 i386_solaris_fix_up_eh_frame (segT sec
)
9035 if (flag_code
== CODE_64BIT
)
9036 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
9042 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9046 exp
.X_op
= O_secrel
;
9047 exp
.X_add_symbol
= symbol
;
9048 exp
.X_add_number
= 0;
9049 emit_expr (&exp
, size
);
9053 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9054 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9057 x86_64_section_letter (int letter
, char **ptr_msg
)
9059 if (flag_code
== CODE_64BIT
)
9062 return SHF_X86_64_LARGE
;
9064 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
9067 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
9072 x86_64_section_word (char *str
, size_t len
)
9074 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9075 return SHF_X86_64_LARGE
;
9081 handle_large_common (int small ATTRIBUTE_UNUSED
)
9083 if (flag_code
!= CODE_64BIT
)
9085 s_comm_internal (0, elf_common_parse
);
9086 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9090 static segT lbss_section
;
9091 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9092 asection
*saved_bss_section
= bss_section
;
9094 if (lbss_section
== NULL
)
9096 flagword applicable
;
9098 subsegT subseg
= now_subseg
;
9100 /* The .lbss section is for local .largecomm symbols. */
9101 lbss_section
= subseg_new (".lbss", 0);
9102 applicable
= bfd_applicable_section_flags (stdoutput
);
9103 bfd_set_section_flags (stdoutput
, lbss_section
,
9104 applicable
& SEC_ALLOC
);
9105 seg_info (lbss_section
)->bss
= 1;
9107 subseg_set (seg
, subseg
);
9110 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9111 bss_section
= lbss_section
;
9113 s_comm_internal (0, elf_common_parse
);
9115 elf_com_section_ptr
= saved_com_section_ptr
;
9116 bss_section
= saved_bss_section
;
9119 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */