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opcodes: blackfin: catch invalid loopsetup insns
[binutils.git] / opcodes / bfin-dis.c
blob312138a147c276d378abcd1cdf96b67c1504f2ef
1 /* Disassemble ADI Blackfin Instructions.
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4
5 This file is part of libopcodes.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #include <stdio.h>
23 #include <stdlib.h>
24 #include <string.h>
25
26 #include "opcode/bfin.h"
27
28 #ifndef PRINTF
29 #define PRINTF printf
30 #endif
31
32 #ifndef EXIT
33 #define EXIT exit
34 #endif
35
36 typedef long TIword;
37
38 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
39 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
40 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
41 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
42
43 #include "dis-asm.h"
44
45 typedef unsigned int bu32;
46
47 static char comment = 0;
48 static char parallel = 0;
49
50 typedef enum
51 {
52 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
53 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
54 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
55 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
56 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
57 } const_forms_t;
58
59 static const struct
60 {
61 const char *name;
62 const int nbits;
63 const char reloc;
64 const char issigned;
65 const char pcrel;
66 const char scale;
67 const char offset;
68 const char negative;
69 const char positive;
70 const char decimal;
71 const char leading;
72 const char exact;
73 } constant_formats[] =
74 {
75 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
76 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
78 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
79 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
80 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
81 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
82 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
83 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
84 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
85 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
86 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
88 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
89 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
91 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
92 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
94 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
95 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
97 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
98 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
99 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
100 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
101 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
102 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
103 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
104 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
107 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
108 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
109 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
110 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
111 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
112 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
113 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
114 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
118 };
119
120 static const char *
121 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
122 {
123 static char buf[60];
124
125 if (constant_formats[cf].reloc)
126 {
127 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
128 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
129 if (constant_formats[cf].pcrel)
130 ea += pc;
131
132 /* truncate to 32-bits for proper symbol lookup/matching */
133 ea = (bu32)ea;
134
135 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
136 {
137 outf->print_address_func (ea, outf);
138 return "";
139 }
140 else
141 {
142 sprintf (buf, "%lx", (unsigned long) x);
143 return buf;
144 }
145 }
146
147 /* Negative constants have an implied sign bit. */
148 if (constant_formats[cf].negative)
149 {
150 int nb = constant_formats[cf].nbits + 1;
151
152 x = x | (1 << constant_formats[cf].nbits);
153 x = SIGNEXTEND (x, nb);
154 }
155 else
156 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
157
158 if (constant_formats[cf].offset)
159 x += constant_formats[cf].offset;
160
161 if (constant_formats[cf].scale)
162 x <<= constant_formats[cf].scale;
163
164 if (constant_formats[cf].decimal)
165 {
166 if (constant_formats[cf].leading)
167 {
168 char ps[10];
169 sprintf (ps, "%%%ii", constant_formats[cf].leading);
170 sprintf (buf, ps, x);
171 }
172 else
173 sprintf (buf, "%li", x);
174 }
175 else
176 {
177 if (constant_formats[cf].issigned && x < 0)
178 sprintf (buf, "-0x%x", abs (x));
179 else
180 sprintf (buf, "0x%lx", (unsigned long) x);
181 }
182
183 return buf;
184 }
185
186 static bu32
187 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
188 {
189 if (0 && constant_formats[cf].reloc)
190 {
191 bu32 ea = (((constant_formats[cf].pcrel
192 ? SIGNEXTEND (x, constant_formats[cf].nbits)
193 : x) + constant_formats[cf].offset)
194 << constant_formats[cf].scale);
195 if (constant_formats[cf].pcrel)
196 ea += pc;
197
198 return ea;
199 }
200
201 /* Negative constants have an implied sign bit. */
202 if (constant_formats[cf].negative)
203 {
204 int nb = constant_formats[cf].nbits + 1;
205 x = x | (1 << constant_formats[cf].nbits);
206 x = SIGNEXTEND (x, nb);
207 }
208 else if (constant_formats[cf].issigned)
209 x = SIGNEXTEND (x, constant_formats[cf].nbits);
210
211 x += constant_formats[cf].offset;
212 x <<= constant_formats[cf].scale;
213
214 return x;
215 }
216
217 enum machine_registers
218 {
219 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
220 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
221 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
222 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
223 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
224 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
225 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
226 REG_L2, REG_L3,
227 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
228 REG_AQ, REG_V, REG_VS,
229 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
230 REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
231 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
232 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
233 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
234 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
235 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
236 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
237 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
238 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
239 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
240 REG_LASTREG,
241 };
242
243 enum reg_class
244 {
245 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
246 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
247 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
248 rc_sysregs3, rc_allregs,
249 LIM_REG_CLASSES
250 };
251
252 static const char * const reg_names[] =
253 {
254 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
255 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
256 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
257 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
258 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
259 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
260 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
261 "L2", "L3",
262 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
263 "AQ", "V", "VS",
264 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
265 "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
266 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
267 "RETE", "EMUDAT",
268 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
269 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
270 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
271 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
272 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
273 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
274 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
275 "AC0_COPY", "V_COPY", "RND_MOD",
276 "LASTREG",
277 0
278 };
279
280 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
281
282 /* RL(0..7). */
283 static const enum machine_registers decode_dregs_lo[] =
284 {
285 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
286 };
287
288 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
289
290 /* RH(0..7). */
291 static const enum machine_registers decode_dregs_hi[] =
292 {
293 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
294 };
295
296 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
297
298 /* R(0..7). */
299 static const enum machine_registers decode_dregs[] =
300 {
301 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
302 };
303
304 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
305
306 /* R BYTE(0..7). */
307 static const enum machine_registers decode_dregs_byte[] =
308 {
309 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
310 };
311
312 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
313
314 /* P(0..5) SP FP. */
315 static const enum machine_registers decode_pregs[] =
316 {
317 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
318 };
319
320 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
321 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
322 #define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
323 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
324 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
325 #define accum(x) REGNAME (decode_accum[(x) & 1])
326
327 /* I(0..3). */
328 static const enum machine_registers decode_iregs[] =
329 {
330 REG_I0, REG_I1, REG_I2, REG_I3,
331 };
332
333 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
334
335 /* M(0..3). */
336 static const enum machine_registers decode_mregs[] =
337 {
338 REG_M0, REG_M1, REG_M2, REG_M3,
339 };
340
341 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
342 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
343 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
344
345 /* dregs pregs. */
346 static const enum machine_registers decode_dpregs[] =
347 {
348 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
349 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
350 };
351
352 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
353
354 /* [dregs pregs]. */
355 static const enum machine_registers decode_gregs[] =
356 {
357 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
358 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
359 };
360
361 #define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
362
363 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
364 static const enum machine_registers decode_regs[] =
365 {
366 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
367 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
368 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
369 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
370 };
371
372 #define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
373
374 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
375 static const enum machine_registers decode_regs_lo[] =
376 {
377 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
378 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
379 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
380 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
381 };
382
383 #define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
384 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
385 static const enum machine_registers decode_regs_hi[] =
386 {
387 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
388 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
389 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
390 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
391 };
392
393 #define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
394
395 static const enum machine_registers decode_statbits[] =
396 {
397 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
398 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
399 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
400 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
401 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
402 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
403 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
404 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
405 };
406
407 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
408
409 /* LC0 LC1. */
410 static const enum machine_registers decode_counters[] =
411 {
412 REG_LC0, REG_LC1,
413 };
414
415 #define counters(x) REGNAME (decode_counters[(x) & 1])
416 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
417
418 /* [dregs pregs (iregs mregs) (bregs lregs)
419 dregs2_sysregs1 open sysregs2 sysregs3]. */
420 static const enum machine_registers decode_allregs[] =
421 {
422 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
423 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
424 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
425 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
426 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS,
427 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
428 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
429 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
430 REG_LASTREG,
431 };
432
433 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
434 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
435 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
436 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
437 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
438 #define IS_SYSREG(g,r) \
439 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
440 #define IS_RESERVEDREG(g,r) \
441 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
442
443 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
444 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
445
446 #define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
447 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
448 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
449 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
450 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
451 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
452 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
453 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
454 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
455 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
456 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
457 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
458 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
459 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
460 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
461 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
462 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
463 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
464 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
465 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
466 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
467 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
468 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
469 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
470 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
471 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
472 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
473 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
474 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
475 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
476 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
477 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
478 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
479 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
480 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
481 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
482 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
483 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
484 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
485 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
486 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
487 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
488 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
489
490 /* (arch.pm)arch_disassembler_functions. */
491 #ifndef OUTS
492 #define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
493 #endif
494
495 static void
496 amod0 (int s0, int x0, disassemble_info *outf)
497 {
498 if (s0 == 1 && x0 == 0)
499 OUTS (outf, " (S)");
500 else if (s0 == 0 && x0 == 1)
501 OUTS (outf, " (CO)");
502 else if (s0 == 1 && x0 == 1)
503 OUTS (outf, " (SCO)");
504 }
505
506 static void
507 amod1 (int s0, int x0, disassemble_info *outf)
508 {
509 if (s0 == 0 && x0 == 0)
510 OUTS (outf, " (NS)");
511 else if (s0 == 1 && x0 == 0)
512 OUTS (outf, " (S)");
513 }
514
515 static void
516 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
517 {
518 if (s0 == 1 && x0 == 0 && aop0 == 0)
519 OUTS (outf, " (S)");
520 else if (s0 == 0 && x0 == 1 && aop0 == 0)
521 OUTS (outf, " (CO)");
522 else if (s0 == 1 && x0 == 1 && aop0 == 0)
523 OUTS (outf, " (SCO)");
524 else if (s0 == 0 && x0 == 0 && aop0 == 2)
525 OUTS (outf, " (ASR)");
526 else if (s0 == 1 && x0 == 0 && aop0 == 2)
527 OUTS (outf, " (S, ASR)");
528 else if (s0 == 0 && x0 == 1 && aop0 == 2)
529 OUTS (outf, " (CO, ASR)");
530 else if (s0 == 1 && x0 == 1 && aop0 == 2)
531 OUTS (outf, " (SCO, ASR)");
532 else if (s0 == 0 && x0 == 0 && aop0 == 3)
533 OUTS (outf, " (ASL)");
534 else if (s0 == 1 && x0 == 0 && aop0 == 3)
535 OUTS (outf, " (S, ASL)");
536 else if (s0 == 0 && x0 == 1 && aop0 == 3)
537 OUTS (outf, " (CO, ASL)");
538 else if (s0 == 1 && x0 == 1 && aop0 == 3)
539 OUTS (outf, " (SCO, ASL)");
540 }
541
542 static void
543 searchmod (int r0, disassemble_info *outf)
544 {
545 if (r0 == 0)
546 OUTS (outf, "GT");
547 else if (r0 == 1)
548 OUTS (outf, "GE");
549 else if (r0 == 2)
550 OUTS (outf, "LT");
551 else if (r0 == 3)
552 OUTS (outf, "LE");
553 }
554
555 static void
556 aligndir (int r0, disassemble_info *outf)
557 {
558 if (r0 == 1)
559 OUTS (outf, " (R)");
560 }
561
562 static int
563 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
564 {
565 const char *s0, *s1;
566
567 if (h0)
568 s0 = dregs_hi (src0);
569 else
570 s0 = dregs_lo (src0);
571
572 if (h1)
573 s1 = dregs_hi (src1);
574 else
575 s1 = dregs_lo (src1);
576
577 OUTS (outf, s0);
578 OUTS (outf, " * ");
579 OUTS (outf, s1);
580 return 0;
581 }
582
583 static int
584 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
585 {
586 const char *a;
587 const char *sop = "<unknown op>";
588
589 if (which)
590 a = "A1";
591 else
592 a = "A0";
593
594 if (op == 3)
595 {
596 OUTS (outf, a);
597 return 0;
598 }
599
600 switch (op)
601 {
602 case 0: sop = " = "; break;
603 case 1: sop = " += "; break;
604 case 2: sop = " -= "; break;
605 default: break;
606 }
607
608 OUTS (outf, a);
609 OUTS (outf, sop);
610 decode_multfunc (h0, h1, src0, src1, outf);
611
612 return 0;
613 }
614
615 static void
616 decode_optmode (int mod, int MM, disassemble_info *outf)
617 {
618 if (mod == 0 && MM == 0)
619 return;
620
621 OUTS (outf, " (");
622
623 if (MM && !mod)
624 {
625 OUTS (outf, "M)");
626 return;
627 }
628
629 if (MM)
630 OUTS (outf, "M, ");
631
632 if (mod == M_S2RND)
633 OUTS (outf, "S2RND");
634 else if (mod == M_T)
635 OUTS (outf, "T");
636 else if (mod == M_W32)
637 OUTS (outf, "W32");
638 else if (mod == M_FU)
639 OUTS (outf, "FU");
640 else if (mod == M_TFU)
641 OUTS (outf, "TFU");
642 else if (mod == M_IS)
643 OUTS (outf, "IS");
644 else if (mod == M_ISS2)
645 OUTS (outf, "ISS2");
646 else if (mod == M_IH)
647 OUTS (outf, "IH");
648 else if (mod == M_IU)
649 OUTS (outf, "IU");
650 else
651 abort ();
652
653 OUTS (outf, ")");
654 }
655
656 struct saved_state
657 {
658 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
659 bu32 a0x, a0w, a1x, a1w;
660 bu32 lt[2], lc[2], lb[2];
661 int ac0, ac0_copy, ac1, an, aq;
662 int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
663 int rnd_mod;
664 int v_internal;
665 bu32 pc, rets;
666
667 int ticks;
668 int insts;
669
670 int exception;
671
672 int end_of_registers;
673
674 int msize;
675 unsigned char *memory;
676 unsigned long bfd_mach;
677 } saved_state;
678
679 #define DREG(x) (saved_state.dpregs[x])
680 #define GREG(x,i) DPREG ((x) | (i << 3))
681 #define DPREG(x) (saved_state.dpregs[x])
682 #define DREG(x) (saved_state.dpregs[x])
683 #define PREG(x) (saved_state.dpregs[x + 8])
684 #define SPREG PREG (6)
685 #define FPREG PREG (7)
686 #define IREG(x) (saved_state.iregs[x])
687 #define MREG(x) (saved_state.mregs[x])
688 #define BREG(x) (saved_state.bregs[x])
689 #define LREG(x) (saved_state.lregs[x])
690 #define A0XREG (saved_state.a0x)
691 #define A0WREG (saved_state.a0w)
692 #define A1XREG (saved_state.a1x)
693 #define A1WREG (saved_state.a1w)
694 #define CCREG (saved_state.cc)
695 #define LC0REG (saved_state.lc[0])
696 #define LT0REG (saved_state.lt[0])
697 #define LB0REG (saved_state.lb[0])
698 #define LC1REG (saved_state.lc[1])
699 #define LT1REG (saved_state.lt[1])
700 #define LB1REG (saved_state.lb[1])
701 #define RETSREG (saved_state.rets)
702 #define PCREG (saved_state.pc)
703
704 static bu32 *
705 get_allreg (int grp, int reg)
706 {
707 int fullreg = (grp << 3) | reg;
708 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
709 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
710 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
711 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
712 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
713 , , , , , , , ,
714 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
715 REG_CYCLES2,
716 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
717 REG_LASTREG */
718 switch (fullreg >> 2)
719 {
720 case 0: case 1: return &DREG (reg); break;
721 case 2: case 3: return &PREG (reg); break;
722 case 4: return &IREG (reg & 3); break;
723 case 5: return &MREG (reg & 3); break;
724 case 6: return &BREG (reg & 3); break;
725 case 7: return &LREG (reg & 3); break;
726 default:
727 switch (fullreg)
728 {
729 case 32: return &saved_state.a0x;
730 case 33: return &saved_state.a0w;
731 case 34: return &saved_state.a1x;
732 case 35: return &saved_state.a1w;
733 case 39: return &saved_state.rets;
734 case 48: return &LC0REG;
735 case 49: return &LT0REG;
736 case 50: return &LB0REG;
737 case 51: return &LC1REG;
738 case 52: return &LT1REG;
739 case 53: return &LB1REG;
740 }
741 return 0;
742 }
743 }
744
745 static int
746 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
747 {
748 /* ProgCtrl
749 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
750 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
751 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
752 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
753 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
754
755 if (prgfunc == 0 && poprnd == 0)
756 OUTS (outf, "NOP");
757 else if (parallel)
758 return 0;
759 else if (prgfunc == 1 && poprnd == 0)
760 OUTS (outf, "RTS");
761 else if (prgfunc == 1 && poprnd == 1)
762 OUTS (outf, "RTI");
763 else if (prgfunc == 1 && poprnd == 2)
764 OUTS (outf, "RTX");
765 else if (prgfunc == 1 && poprnd == 3)
766 OUTS (outf, "RTN");
767 else if (prgfunc == 1 && poprnd == 4)
768 OUTS (outf, "RTE");
769 else if (prgfunc == 2 && poprnd == 0)
770 OUTS (outf, "IDLE");
771 else if (prgfunc == 2 && poprnd == 3)
772 OUTS (outf, "CSYNC");
773 else if (prgfunc == 2 && poprnd == 4)
774 OUTS (outf, "SSYNC");
775 else if (prgfunc == 2 && poprnd == 5)
776 OUTS (outf, "EMUEXCPT");
777 else if (prgfunc == 3 && IS_DREG (0, poprnd))
778 {
779 OUTS (outf, "CLI ");
780 OUTS (outf, dregs (poprnd));
781 }
782 else if (prgfunc == 4 && IS_DREG (0, poprnd))
783 {
784 OUTS (outf, "STI ");
785 OUTS (outf, dregs (poprnd));
786 }
787 else if (prgfunc == 5 && IS_PREG (1, poprnd))
788 {
789 OUTS (outf, "JUMP (");
790 OUTS (outf, pregs (poprnd));
791 OUTS (outf, ")");
792 }
793 else if (prgfunc == 6 && IS_PREG (1, poprnd))
794 {
795 OUTS (outf, "CALL (");
796 OUTS (outf, pregs (poprnd));
797 OUTS (outf, ")");
798 }
799 else if (prgfunc == 7 && IS_PREG (1, poprnd))
800 {
801 OUTS (outf, "CALL (PC + ");
802 OUTS (outf, pregs (poprnd));
803 OUTS (outf, ")");
804 }
805 else if (prgfunc == 8 && IS_PREG (1, poprnd))
806 {
807 OUTS (outf, "JUMP (PC + ");
808 OUTS (outf, pregs (poprnd));
809 OUTS (outf, ")");
810 }
811 else if (prgfunc == 9)
812 {
813 OUTS (outf, "RAISE ");
814 OUTS (outf, uimm4 (poprnd));
815 }
816 else if (prgfunc == 10)
817 {
818 OUTS (outf, "EXCPT ");
819 OUTS (outf, uimm4 (poprnd));
820 }
821 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
822 {
823 OUTS (outf, "TESTSET (");
824 OUTS (outf, pregs (poprnd));
825 OUTS (outf, ")");
826 }
827 else
828 return 0;
829 return 2;
830 }
831
832 static int
833 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
834 {
835 /* CaCTRL
836 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
837 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
838 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
839 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
840 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
841 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
842
843 if (parallel)
844 return 0;
845
846 if (a == 0 && op == 0)
847 {
848 OUTS (outf, "PREFETCH[");
849 OUTS (outf, pregs (reg));
850 OUTS (outf, "]");
851 }
852 else if (a == 0 && op == 1)
853 {
854 OUTS (outf, "FLUSHINV[");
855 OUTS (outf, pregs (reg));
856 OUTS (outf, "]");
857 }
858 else if (a == 0 && op == 2)
859 {
860 OUTS (outf, "FLUSH[");
861 OUTS (outf, pregs (reg));
862 OUTS (outf, "]");
863 }
864 else if (a == 0 && op == 3)
865 {
866 OUTS (outf, "IFLUSH[");
867 OUTS (outf, pregs (reg));
868 OUTS (outf, "]");
869 }
870 else if (a == 1 && op == 0)
871 {
872 OUTS (outf, "PREFETCH[");
873 OUTS (outf, pregs (reg));
874 OUTS (outf, "++]");
875 }
876 else if (a == 1 && op == 1)
877 {
878 OUTS (outf, "FLUSHINV[");
879 OUTS (outf, pregs (reg));
880 OUTS (outf, "++]");
881 }
882 else if (a == 1 && op == 2)
883 {
884 OUTS (outf, "FLUSH[");
885 OUTS (outf, pregs (reg));
886 OUTS (outf, "++]");
887 }
888 else if (a == 1 && op == 3)
889 {
890 OUTS (outf, "IFLUSH[");
891 OUTS (outf, pregs (reg));
892 OUTS (outf, "++]");
893 }
894 else
895 return 0;
896 return 2;
897 }
898
899 static int
900 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
901 {
902 /* PushPopReg
903 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
904 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
905 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
906 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
907 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
908 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
909
910 if (parallel)
911 return 0;
912
913 if (W == 0 && mostreg (reg, grp))
914 {
915 OUTS (outf, allregs (reg, grp));
916 OUTS (outf, " = [SP++]");
917 }
918 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
919 {
920 OUTS (outf, "[--SP] = ");
921 OUTS (outf, allregs (reg, grp));
922 }
923 else
924 return 0;
925 return 2;
926 }
927
928 static int
929 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
930 {
931 /* PushPopMultiple
932 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
933 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
934 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
935 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
936 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
937 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
938 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
939 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
940
941 if (parallel)
942 return 0;
943
944 if (pr > 5)
945 return 0;
946
947 if (W == 1 && d == 1 && p == 1)
948 {
949 OUTS (outf, "[--SP] = (R7:");
950 OUTS (outf, imm5d (dr));
951 OUTS (outf, ", P5:");
952 OUTS (outf, imm5d (pr));
953 OUTS (outf, ")");
954 }
955 else if (W == 1 && d == 1 && p == 0 && pr == 0)
956 {
957 OUTS (outf, "[--SP] = (R7:");
958 OUTS (outf, imm5d (dr));
959 OUTS (outf, ")");
960 }
961 else if (W == 1 && d == 0 && p == 1 && dr == 0)
962 {
963 OUTS (outf, "[--SP] = (P5:");
964 OUTS (outf, imm5d (pr));
965 OUTS (outf, ")");
966 }
967 else if (W == 0 && d == 1 && p == 1)
968 {
969 OUTS (outf, "(R7:");
970 OUTS (outf, imm5d (dr));
971 OUTS (outf, ", P5:");
972 OUTS (outf, imm5d (pr));
973 OUTS (outf, ") = [SP++]");
974 }
975 else if (W == 0 && d == 1 && p == 0 && pr == 0)
976 {
977 OUTS (outf, "(R7:");
978 OUTS (outf, imm5d (dr));
979 OUTS (outf, ") = [SP++]");
980 }
981 else if (W == 0 && d == 0 && p == 1 && dr == 0)
982 {
983 OUTS (outf, "(P5:");
984 OUTS (outf, imm5d (pr));
985 OUTS (outf, ") = [SP++]");
986 }
987 else
988 return 0;
989 return 2;
990 }
991
992 static int
993 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
994 {
995 /* ccMV
996 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
997 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
998 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
999 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
1000 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
1001 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
1002 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
1003 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
1004
1005 if (parallel)
1006 return 0;
1007
1008 if (T == 1)
1009 {
1010 OUTS (outf, "IF CC ");
1011 OUTS (outf, gregs (dst, d));
1012 OUTS (outf, " = ");
1013 OUTS (outf, gregs (src, s));
1014 }
1015 else if (T == 0)
1016 {
1017 OUTS (outf, "IF !CC ");
1018 OUTS (outf, gregs (dst, d));
1019 OUTS (outf, " = ");
1020 OUTS (outf, gregs (src, s));
1021 }
1022 else
1023 return 0;
1024 return 2;
1025 }
1026
1027 static int
1028 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1029 {
1030 /* CCflag
1031 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1032 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1033 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1034 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1035 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1036 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1037 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1038 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1039
1040 if (parallel)
1041 return 0;
1042
1043 if (opc == 0 && I == 0 && G == 0)
1044 {
1045 OUTS (outf, "CC = ");
1046 OUTS (outf, dregs (x));
1047 OUTS (outf, " == ");
1048 OUTS (outf, dregs (y));
1049 }
1050 else if (opc == 1 && I == 0 && G == 0)
1051 {
1052 OUTS (outf, "CC = ");
1053 OUTS (outf, dregs (x));
1054 OUTS (outf, " < ");
1055 OUTS (outf, dregs (y));
1056 }
1057 else if (opc == 2 && I == 0 && G == 0)
1058 {
1059 OUTS (outf, "CC = ");
1060 OUTS (outf, dregs (x));
1061 OUTS (outf, " <= ");
1062 OUTS (outf, dregs (y));
1063 }
1064 else if (opc == 3 && I == 0 && G == 0)
1065 {
1066 OUTS (outf, "CC = ");
1067 OUTS (outf, dregs (x));
1068 OUTS (outf, " < ");
1069 OUTS (outf, dregs (y));
1070 OUTS (outf, " (IU)");
1071 }
1072 else if (opc == 4 && I == 0 && G == 0)
1073 {
1074 OUTS (outf, "CC = ");
1075 OUTS (outf, dregs (x));
1076 OUTS (outf, " <= ");
1077 OUTS (outf, dregs (y));
1078 OUTS (outf, " (IU)");
1079 }
1080 else if (opc == 0 && I == 1 && G == 0)
1081 {
1082 OUTS (outf, "CC = ");
1083 OUTS (outf, dregs (x));
1084 OUTS (outf, " == ");
1085 OUTS (outf, imm3 (y));
1086 }
1087 else if (opc == 1 && I == 1 && G == 0)
1088 {
1089 OUTS (outf, "CC = ");
1090 OUTS (outf, dregs (x));
1091 OUTS (outf, " < ");
1092 OUTS (outf, imm3 (y));
1093 }
1094 else if (opc == 2 && I == 1 && G == 0)
1095 {
1096 OUTS (outf, "CC = ");
1097 OUTS (outf, dregs (x));
1098 OUTS (outf, " <= ");
1099 OUTS (outf, imm3 (y));
1100 }
1101 else if (opc == 3 && I == 1 && G == 0)
1102 {
1103 OUTS (outf, "CC = ");
1104 OUTS (outf, dregs (x));
1105 OUTS (outf, " < ");
1106 OUTS (outf, uimm3 (y));
1107 OUTS (outf, " (IU)");
1108 }
1109 else if (opc == 4 && I == 1 && G == 0)
1110 {
1111 OUTS (outf, "CC = ");
1112 OUTS (outf, dregs (x));
1113 OUTS (outf, " <= ");
1114 OUTS (outf, uimm3 (y));
1115 OUTS (outf, " (IU)");
1116 }
1117 else if (opc == 0 && I == 0 && G == 1)
1118 {
1119 OUTS (outf, "CC = ");
1120 OUTS (outf, pregs (x));
1121 OUTS (outf, " == ");
1122 OUTS (outf, pregs (y));
1123 }
1124 else if (opc == 1 && I == 0 && G == 1)
1125 {
1126 OUTS (outf, "CC = ");
1127 OUTS (outf, pregs (x));
1128 OUTS (outf, " < ");
1129 OUTS (outf, pregs (y));
1130 }
1131 else if (opc == 2 && I == 0 && G == 1)
1132 {
1133 OUTS (outf, "CC = ");
1134 OUTS (outf, pregs (x));
1135 OUTS (outf, " <= ");
1136 OUTS (outf, pregs (y));
1137 }
1138 else if (opc == 3 && I == 0 && G == 1)
1139 {
1140 OUTS (outf, "CC = ");
1141 OUTS (outf, pregs (x));
1142 OUTS (outf, " < ");
1143 OUTS (outf, pregs (y));
1144 OUTS (outf, " (IU)");
1145 }
1146 else if (opc == 4 && I == 0 && G == 1)
1147 {
1148 OUTS (outf, "CC = ");
1149 OUTS (outf, pregs (x));
1150 OUTS (outf, " <= ");
1151 OUTS (outf, pregs (y));
1152 OUTS (outf, " (IU)");
1153 }
1154 else if (opc == 0 && I == 1 && G == 1)
1155 {
1156 OUTS (outf, "CC = ");
1157 OUTS (outf, pregs (x));
1158 OUTS (outf, " == ");
1159 OUTS (outf, imm3 (y));
1160 }
1161 else if (opc == 1 && I == 1 && G == 1)
1162 {
1163 OUTS (outf, "CC = ");
1164 OUTS (outf, pregs (x));
1165 OUTS (outf, " < ");
1166 OUTS (outf, imm3 (y));
1167 }
1168 else if (opc == 2 && I == 1 && G == 1)
1169 {
1170 OUTS (outf, "CC = ");
1171 OUTS (outf, pregs (x));
1172 OUTS (outf, " <= ");
1173 OUTS (outf, imm3 (y));
1174 }
1175 else if (opc == 3 && I == 1 && G == 1)
1176 {
1177 OUTS (outf, "CC = ");
1178 OUTS (outf, pregs (x));
1179 OUTS (outf, " < ");
1180 OUTS (outf, uimm3 (y));
1181 OUTS (outf, " (IU)");
1182 }
1183 else if (opc == 4 && I == 1 && G == 1)
1184 {
1185 OUTS (outf, "CC = ");
1186 OUTS (outf, pregs (x));
1187 OUTS (outf, " <= ");
1188 OUTS (outf, uimm3 (y));
1189 OUTS (outf, " (IU)");
1190 }
1191 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
1192 OUTS (outf, "CC = A0 == A1");
1193
1194 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
1195 OUTS (outf, "CC = A0 < A1");
1196
1197 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
1198 OUTS (outf, "CC = A0 <= A1");
1199
1200 else
1201 return 0;
1202 return 2;
1203 }
1204
1205 static int
1206 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1207 {
1208 /* CC2dreg
1209 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1210 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1211 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1212 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1213 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1214
1215 if (parallel)
1216 return 0;
1217
1218 if (op == 0)
1219 {
1220 OUTS (outf, dregs (reg));
1221 OUTS (outf, " = CC");
1222 }
1223 else if (op == 1)
1224 {
1225 OUTS (outf, "CC = ");
1226 OUTS (outf, dregs (reg));
1227 }
1228 else if (op == 3 && reg == 0)
1229 OUTS (outf, "CC = !CC");
1230 else
1231 return 0;
1232
1233 return 2;
1234 }
1235
1236 static int
1237 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1238 {
1239 /* CC2stat
1240 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1241 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1242 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1243 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1244 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1245 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1246
1247 const char *bitname = statbits (cbit);
1248
1249 if (parallel)
1250 return 0;
1251
1252 if (decode_statbits[cbit] == REG_LASTREG)
1253 {
1254 /* All ASTAT bits except CC may be operated on in hardware, but may
1255 not have a dedicated insn, so still decode "valid" insns. */
1256 static char bitnames[64];
1257 if (cbit != 5)
1258 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1259 else
1260 return 0;
1261
1262 bitname = bitnames;
1263 }
1264
1265 if (op == 0 && D == 0)
1266 {
1267 OUTS (outf, "CC = ");
1268 OUTS (outf, bitname);
1269 }
1270 else if (op == 1 && D == 0)
1271 {
1272 OUTS (outf, "CC |= ");
1273 OUTS (outf, bitname);
1274 }
1275 else if (op == 2 && D == 0)
1276 {
1277 OUTS (outf, "CC &= ");
1278 OUTS (outf, bitname);
1279 }
1280 else if (op == 3 && D == 0)
1281 {
1282 OUTS (outf, "CC ^= ");
1283 OUTS (outf, bitname);
1284 }
1285 else if (op == 0 && D == 1)
1286 {
1287 OUTS (outf, bitname);
1288 OUTS (outf, " = CC");
1289 }
1290 else if (op == 1 && D == 1)
1291 {
1292 OUTS (outf, bitname);
1293 OUTS (outf, " |= CC");
1294 }
1295 else if (op == 2 && D == 1)
1296 {
1297 OUTS (outf, bitname);
1298 OUTS (outf, " &= CC");
1299 }
1300 else if (op == 3 && D == 1)
1301 {
1302 OUTS (outf, bitname);
1303 OUTS (outf, " ^= CC");
1304 }
1305 else
1306 return 0;
1307
1308 return 2;
1309 }
1310
1311 static int
1312 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1313 {
1314 /* BRCC
1315 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1316 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1317 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1318 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1319 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1320 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1321
1322 if (parallel)
1323 return 0;
1324
1325 if (T == 1 && B == 1)
1326 {
1327 OUTS (outf, "IF CC JUMP 0x");
1328 OUTS (outf, pcrel10 (offset));
1329 OUTS (outf, " (BP)");
1330 }
1331 else if (T == 0 && B == 1)
1332 {
1333 OUTS (outf, "IF !CC JUMP 0x");
1334 OUTS (outf, pcrel10 (offset));
1335 OUTS (outf, " (BP)");
1336 }
1337 else if (T == 1)
1338 {
1339 OUTS (outf, "IF CC JUMP 0x");
1340 OUTS (outf, pcrel10 (offset));
1341 }
1342 else if (T == 0)
1343 {
1344 OUTS (outf, "IF !CC JUMP 0x");
1345 OUTS (outf, pcrel10 (offset));
1346 }
1347 else
1348 return 0;
1349
1350 return 2;
1351 }
1352
1353 static int
1354 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1355 {
1356 /* UJUMP
1357 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1358 | 0 | 0 | 1 | 0 |.offset........................................|
1359 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1360 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1361
1362 if (parallel)
1363 return 0;
1364
1365 OUTS (outf, "JUMP.S 0x");
1366 OUTS (outf, pcrel12 (offset));
1367 return 2;
1368 }
1369
1370 static int
1371 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1372 {
1373 /* REGMV
1374 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1375 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1376 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1377 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1378 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1379 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1380 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1381
1382 /* Reserved slots cannot be a src/dst. */
1383 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1384 goto invalid_move;
1385
1386 /* Standard register moves */
1387 if ((gs < 2) || /* Dregs/Pregs as source */
1388 (gd < 2) || /* Dregs/Pregs as dest */
1389 (gs == 4 && src < 4) || /* Accumulators as source */
1390 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1391 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1392 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1393 goto valid_move;
1394
1395 /* dareg = dareg (IMBL) */
1396 if (gs < 4 && gd < 4)
1397 goto valid_move;
1398
1399 /* USP can be src to sysregs, but not dagregs. */
1400 if ((gs == 7 && src == 0) && (gd >= 4))
1401 goto valid_move;
1402
1403 /* USP can move between genregs (only check Accumulators). */
1404 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1405 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1406 goto valid_move;
1407
1408 /* Still here ? Invalid reg pair. */
1409 invalid_move:
1410 return 0;
1411
1412 valid_move:
1413 OUTS (outf, allregs (dst, gd));
1414 OUTS (outf, " = ");
1415 OUTS (outf, allregs (src, gs));
1416 return 2;
1417 }
1418
1419 static int
1420 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1421 {
1422 /* ALU2op
1423 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1424 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1425 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1426 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1427 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1428 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1429
1430 if (opc == 0)
1431 {
1432 OUTS (outf, dregs (dst));
1433 OUTS (outf, " >>>= ");
1434 OUTS (outf, dregs (src));
1435 }
1436 else if (opc == 1)
1437 {
1438 OUTS (outf, dregs (dst));
1439 OUTS (outf, " >>= ");
1440 OUTS (outf, dregs (src));
1441 }
1442 else if (opc == 2)
1443 {
1444 OUTS (outf, dregs (dst));
1445 OUTS (outf, " <<= ");
1446 OUTS (outf, dregs (src));
1447 }
1448 else if (opc == 3)
1449 {
1450 OUTS (outf, dregs (dst));
1451 OUTS (outf, " *= ");
1452 OUTS (outf, dregs (src));
1453 }
1454 else if (opc == 4)
1455 {
1456 OUTS (outf, dregs (dst));
1457 OUTS (outf, " = (");
1458 OUTS (outf, dregs (dst));
1459 OUTS (outf, " + ");
1460 OUTS (outf, dregs (src));
1461 OUTS (outf, ") << 0x1");
1462 }
1463 else if (opc == 5)
1464 {
1465 OUTS (outf, dregs (dst));
1466 OUTS (outf, " = (");
1467 OUTS (outf, dregs (dst));
1468 OUTS (outf, " + ");
1469 OUTS (outf, dregs (src));
1470 OUTS (outf, ") << 0x2");
1471 }
1472 else if (opc == 8)
1473 {
1474 OUTS (outf, "DIVQ (");
1475 OUTS (outf, dregs (dst));
1476 OUTS (outf, ", ");
1477 OUTS (outf, dregs (src));
1478 OUTS (outf, ")");
1479 }
1480 else if (opc == 9)
1481 {
1482 OUTS (outf, "DIVS (");
1483 OUTS (outf, dregs (dst));
1484 OUTS (outf, ", ");
1485 OUTS (outf, dregs (src));
1486 OUTS (outf, ")");
1487 }
1488 else if (opc == 10)
1489 {
1490 OUTS (outf, dregs (dst));
1491 OUTS (outf, " = ");
1492 OUTS (outf, dregs_lo (src));
1493 OUTS (outf, " (X)");
1494 }
1495 else if (opc == 11)
1496 {
1497 OUTS (outf, dregs (dst));
1498 OUTS (outf, " = ");
1499 OUTS (outf, dregs_lo (src));
1500 OUTS (outf, " (Z)");
1501 }
1502 else if (opc == 12)
1503 {
1504 OUTS (outf, dregs (dst));
1505 OUTS (outf, " = ");
1506 OUTS (outf, dregs_byte (src));
1507 OUTS (outf, " (X)");
1508 }
1509 else if (opc == 13)
1510 {
1511 OUTS (outf, dregs (dst));
1512 OUTS (outf, " = ");
1513 OUTS (outf, dregs_byte (src));
1514 OUTS (outf, " (Z)");
1515 }
1516 else if (opc == 14)
1517 {
1518 OUTS (outf, dregs (dst));
1519 OUTS (outf, " = -");
1520 OUTS (outf, dregs (src));
1521 }
1522 else if (opc == 15)
1523 {
1524 OUTS (outf, dregs (dst));
1525 OUTS (outf, " =~ ");
1526 OUTS (outf, dregs (src));
1527 }
1528 else
1529 return 0;
1530
1531 return 2;
1532 }
1533
1534 static int
1535 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1536 {
1537 /* PTR2op
1538 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1539 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1540 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1541 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1542 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1543 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1544
1545 if (opc == 0)
1546 {
1547 OUTS (outf, pregs (dst));
1548 OUTS (outf, " -= ");
1549 OUTS (outf, pregs (src));
1550 }
1551 else if (opc == 1)
1552 {
1553 OUTS (outf, pregs (dst));
1554 OUTS (outf, " = ");
1555 OUTS (outf, pregs (src));
1556 OUTS (outf, " << 0x2");
1557 }
1558 else if (opc == 3)
1559 {
1560 OUTS (outf, pregs (dst));
1561 OUTS (outf, " = ");
1562 OUTS (outf, pregs (src));
1563 OUTS (outf, " >> 0x2");
1564 }
1565 else if (opc == 4)
1566 {
1567 OUTS (outf, pregs (dst));
1568 OUTS (outf, " = ");
1569 OUTS (outf, pregs (src));
1570 OUTS (outf, " >> 0x1");
1571 }
1572 else if (opc == 5)
1573 {
1574 OUTS (outf, pregs (dst));
1575 OUTS (outf, " += ");
1576 OUTS (outf, pregs (src));
1577 OUTS (outf, " (BREV)");
1578 }
1579 else if (opc == 6)
1580 {
1581 OUTS (outf, pregs (dst));
1582 OUTS (outf, " = (");
1583 OUTS (outf, pregs (dst));
1584 OUTS (outf, " + ");
1585 OUTS (outf, pregs (src));
1586 OUTS (outf, ") << 0x1");
1587 }
1588 else if (opc == 7)
1589 {
1590 OUTS (outf, pregs (dst));
1591 OUTS (outf, " = (");
1592 OUTS (outf, pregs (dst));
1593 OUTS (outf, " + ");
1594 OUTS (outf, pregs (src));
1595 OUTS (outf, ") << 0x2");
1596 }
1597 else
1598 return 0;
1599
1600 return 2;
1601 }
1602
1603 static int
1604 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1605 {
1606 /* LOGI2op
1607 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1608 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1609 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1610 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1611 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1612 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1613
1614 if (parallel)
1615 return 0;
1616
1617 if (opc == 0)
1618 {
1619 OUTS (outf, "CC = !BITTST (");
1620 OUTS (outf, dregs (dst));
1621 OUTS (outf, ", ");
1622 OUTS (outf, uimm5 (src));
1623 OUTS (outf, ");\t\t/* bit");
1624 OUTS (outf, imm7d (src));
1625 OUTS (outf, " */");
1626 comment = 1;
1627 }
1628 else if (opc == 1)
1629 {
1630 OUTS (outf, "CC = BITTST (");
1631 OUTS (outf, dregs (dst));
1632 OUTS (outf, ", ");
1633 OUTS (outf, uimm5 (src));
1634 OUTS (outf, ");\t\t/* bit");
1635 OUTS (outf, imm7d (src));
1636 OUTS (outf, " */");
1637 comment = 1;
1638 }
1639 else if (opc == 2)
1640 {
1641 OUTS (outf, "BITSET (");
1642 OUTS (outf, dregs (dst));
1643 OUTS (outf, ", ");
1644 OUTS (outf, uimm5 (src));
1645 OUTS (outf, ");\t\t/* bit");
1646 OUTS (outf, imm7d (src));
1647 OUTS (outf, " */");
1648 comment = 1;
1649 }
1650 else if (opc == 3)
1651 {
1652 OUTS (outf, "BITTGL (");
1653 OUTS (outf, dregs (dst));
1654 OUTS (outf, ", ");
1655 OUTS (outf, uimm5 (src));
1656 OUTS (outf, ");\t\t/* bit");
1657 OUTS (outf, imm7d (src));
1658 OUTS (outf, " */");
1659 comment = 1;
1660 }
1661 else if (opc == 4)
1662 {
1663 OUTS (outf, "BITCLR (");
1664 OUTS (outf, dregs (dst));
1665 OUTS (outf, ", ");
1666 OUTS (outf, uimm5 (src));
1667 OUTS (outf, ");\t\t/* bit");
1668 OUTS (outf, imm7d (src));
1669 OUTS (outf, " */");
1670 comment = 1;
1671 }
1672 else if (opc == 5)
1673 {
1674 OUTS (outf, dregs (dst));
1675 OUTS (outf, " >>>= ");
1676 OUTS (outf, uimm5 (src));
1677 }
1678 else if (opc == 6)
1679 {
1680 OUTS (outf, dregs (dst));
1681 OUTS (outf, " >>= ");
1682 OUTS (outf, uimm5 (src));
1683 }
1684 else if (opc == 7)
1685 {
1686 OUTS (outf, dregs (dst));
1687 OUTS (outf, " <<= ");
1688 OUTS (outf, uimm5 (src));
1689 }
1690 else
1691 return 0;
1692
1693 return 2;
1694 }
1695
1696 static int
1697 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1698 {
1699 /* COMP3op
1700 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1701 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1702 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1703 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1704 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1705 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1706 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1707
1708 if (opc == 5 && src1 == src0)
1709 {
1710 OUTS (outf, pregs (dst));
1711 OUTS (outf, " = ");
1712 OUTS (outf, pregs (src0));
1713 OUTS (outf, " << 0x1");
1714 }
1715 else if (opc == 1)
1716 {
1717 OUTS (outf, dregs (dst));
1718 OUTS (outf, " = ");
1719 OUTS (outf, dregs (src0));
1720 OUTS (outf, " - ");
1721 OUTS (outf, dregs (src1));
1722 }
1723 else if (opc == 2)
1724 {
1725 OUTS (outf, dregs (dst));
1726 OUTS (outf, " = ");
1727 OUTS (outf, dregs (src0));
1728 OUTS (outf, " & ");
1729 OUTS (outf, dregs (src1));
1730 }
1731 else if (opc == 3)
1732 {
1733 OUTS (outf, dregs (dst));
1734 OUTS (outf, " = ");
1735 OUTS (outf, dregs (src0));
1736 OUTS (outf, " | ");
1737 OUTS (outf, dregs (src1));
1738 }
1739 else if (opc == 4)
1740 {
1741 OUTS (outf, dregs (dst));
1742 OUTS (outf, " = ");
1743 OUTS (outf, dregs (src0));
1744 OUTS (outf, " ^ ");
1745 OUTS (outf, dregs (src1));
1746 }
1747 else if (opc == 5)
1748 {
1749 OUTS (outf, pregs (dst));
1750 OUTS (outf, " = ");
1751 OUTS (outf, pregs (src0));
1752 OUTS (outf, " + ");
1753 OUTS (outf, pregs (src1));
1754 }
1755 else if (opc == 6)
1756 {
1757 OUTS (outf, pregs (dst));
1758 OUTS (outf, " = ");
1759 OUTS (outf, pregs (src0));
1760 OUTS (outf, " + (");
1761 OUTS (outf, pregs (src1));
1762 OUTS (outf, " << 0x1)");
1763 }
1764 else if (opc == 7)
1765 {
1766 OUTS (outf, pregs (dst));
1767 OUTS (outf, " = ");
1768 OUTS (outf, pregs (src0));
1769 OUTS (outf, " + (");
1770 OUTS (outf, pregs (src1));
1771 OUTS (outf, " << 0x2)");
1772 }
1773 else if (opc == 0)
1774 {
1775 OUTS (outf, dregs (dst));
1776 OUTS (outf, " = ");
1777 OUTS (outf, dregs (src0));
1778 OUTS (outf, " + ");
1779 OUTS (outf, dregs (src1));
1780 }
1781 else
1782 return 0;
1783
1784 return 2;
1785 }
1786
1787 static int
1788 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1789 {
1790 /* COMPI2opD
1791 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1792 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1793 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1794 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1795 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1796 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1797
1798 bu32 *pval = get_allreg (0, dst);
1799
1800 if (parallel)
1801 return 0;
1802
1803 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1804 to combine them, so it prints out the right values.
1805 Here we keep track of the registers. */
1806 if (op == 0)
1807 {
1808 *pval = imm7_val (src);
1809 if (src & 0x40)
1810 *pval |= 0xFFFFFF80;
1811 else
1812 *pval &= 0x7F;
1813 }
1814
1815 if (op == 0)
1816 {
1817 OUTS (outf, dregs (dst));
1818 OUTS (outf, " = ");
1819 OUTS (outf, imm7 (src));
1820 OUTS (outf, " (X);\t\t/*\t\t");
1821 OUTS (outf, dregs (dst));
1822 OUTS (outf, "=");
1823 OUTS (outf, uimm32 (*pval));
1824 OUTS (outf, "(");
1825 OUTS (outf, imm32 (*pval));
1826 OUTS (outf, ") */");
1827 comment = 1;
1828 }
1829 else if (op == 1)
1830 {
1831 OUTS (outf, dregs (dst));
1832 OUTS (outf, " += ");
1833 OUTS (outf, imm7 (src));
1834 OUTS (outf, ";\t\t/* (");
1835 OUTS (outf, imm7d (src));
1836 OUTS (outf, ") */");
1837 comment = 1;
1838 }
1839 else
1840 return 0;
1841
1842 return 2;
1843 }
1844
1845 static int
1846 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1847 {
1848 /* COMPI2opP
1849 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1850 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1851 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1852 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1853 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1854 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1855
1856 bu32 *pval = get_allreg (1, dst);
1857
1858 if (parallel)
1859 return 0;
1860
1861 if (op == 0)
1862 {
1863 *pval = imm7_val (src);
1864 if (src & 0x40)
1865 *pval |= 0xFFFFFF80;
1866 else
1867 *pval &= 0x7F;
1868 }
1869
1870 if (op == 0)
1871 {
1872 OUTS (outf, pregs (dst));
1873 OUTS (outf, " = ");
1874 OUTS (outf, imm7 (src));
1875 OUTS (outf, " (X);\t\t/*\t\t");
1876 OUTS (outf, pregs (dst));
1877 OUTS (outf, "=");
1878 OUTS (outf, uimm32 (*pval));
1879 OUTS (outf, "(");
1880 OUTS (outf, imm32 (*pval));
1881 OUTS (outf, ") */");
1882 comment = 1;
1883 }
1884 else if (op == 1)
1885 {
1886 OUTS (outf, pregs (dst));
1887 OUTS (outf, " += ");
1888 OUTS (outf, imm7 (src));
1889 OUTS (outf, ";\t\t/* (");
1890 OUTS (outf, imm7d (src));
1891 OUTS (outf, ") */");
1892 comment = 1;
1893 }
1894 else
1895 return 0;
1896
1897 return 2;
1898 }
1899
1900 static int
1901 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1902 {
1903 /* LDSTpmod
1904 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1905 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1906 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1907 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1908 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1909 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1910 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1911 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1912
1913 if (aop == 1 && W == 0 && idx == ptr)
1914 {
1915 OUTS (outf, dregs_lo (reg));
1916 OUTS (outf, " = W[");
1917 OUTS (outf, pregs (ptr));
1918 OUTS (outf, "]");
1919 }
1920 else if (aop == 2 && W == 0 && idx == ptr)
1921 {
1922 OUTS (outf, dregs_hi (reg));
1923 OUTS (outf, " = W[");
1924 OUTS (outf, pregs (ptr));
1925 OUTS (outf, "]");
1926 }
1927 else if (aop == 1 && W == 1 && idx == ptr)
1928 {
1929 OUTS (outf, "W[");
1930 OUTS (outf, pregs (ptr));
1931 OUTS (outf, "] = ");
1932 OUTS (outf, dregs_lo (reg));
1933 }
1934 else if (aop == 2 && W == 1 && idx == ptr)
1935 {
1936 OUTS (outf, "W[");
1937 OUTS (outf, pregs (ptr));
1938 OUTS (outf, "] = ");
1939 OUTS (outf, dregs_hi (reg));
1940 }
1941 else if (aop == 0 && W == 0)
1942 {
1943 OUTS (outf, dregs (reg));
1944 OUTS (outf, " = [");
1945 OUTS (outf, pregs (ptr));
1946 OUTS (outf, " ++ ");
1947 OUTS (outf, pregs (idx));
1948 OUTS (outf, "]");
1949 }
1950 else if (aop == 1 && W == 0)
1951 {
1952 OUTS (outf, dregs_lo (reg));
1953 OUTS (outf, " = W[");
1954 OUTS (outf, pregs (ptr));
1955 OUTS (outf, " ++ ");
1956 OUTS (outf, pregs (idx));
1957 OUTS (outf, "]");
1958 }
1959 else if (aop == 2 && W == 0)
1960 {
1961 OUTS (outf, dregs_hi (reg));
1962 OUTS (outf, " = W[");
1963 OUTS (outf, pregs (ptr));
1964 OUTS (outf, " ++ ");
1965 OUTS (outf, pregs (idx));
1966 OUTS (outf, "]");
1967 }
1968 else if (aop == 3 && W == 0)
1969 {
1970 OUTS (outf, dregs (reg));
1971 OUTS (outf, " = W[");
1972 OUTS (outf, pregs (ptr));
1973 OUTS (outf, " ++ ");
1974 OUTS (outf, pregs (idx));
1975 OUTS (outf, "] (Z)");
1976 }
1977 else if (aop == 3 && W == 1)
1978 {
1979 OUTS (outf, dregs (reg));
1980 OUTS (outf, " = W[");
1981 OUTS (outf, pregs (ptr));
1982 OUTS (outf, " ++ ");
1983 OUTS (outf, pregs (idx));
1984 OUTS (outf, "] (X)");
1985 }
1986 else if (aop == 0 && W == 1)
1987 {
1988 OUTS (outf, "[");
1989 OUTS (outf, pregs (ptr));
1990 OUTS (outf, " ++ ");
1991 OUTS (outf, pregs (idx));
1992 OUTS (outf, "] = ");
1993 OUTS (outf, dregs (reg));
1994 }
1995 else if (aop == 1 && W == 1)
1996 {
1997 OUTS (outf, "W[");
1998 OUTS (outf, pregs (ptr));
1999 OUTS (outf, " ++ ");
2000 OUTS (outf, pregs (idx));
2001 OUTS (outf, "] = ");
2002 OUTS (outf, dregs_lo (reg));
2003 }
2004 else if (aop == 2 && W == 1)
2005 {
2006 OUTS (outf, "W[");
2007 OUTS (outf, pregs (ptr));
2008 OUTS (outf, " ++ ");
2009 OUTS (outf, pregs (idx));
2010 OUTS (outf, "] = ");
2011 OUTS (outf, dregs_hi (reg));
2012 }
2013 else
2014 return 0;
2015
2016 return 2;
2017 }
2018
2019 static int
2020 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
2021 {
2022 /* dagMODim
2023 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2024 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2025 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2026 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
2027 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
2028 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
2029 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2030
2031 if (op == 0 && br == 1)
2032 {
2033 OUTS (outf, iregs (i));
2034 OUTS (outf, " += ");
2035 OUTS (outf, mregs (m));
2036 OUTS (outf, " (BREV)");
2037 }
2038 else if (op == 0)
2039 {
2040 OUTS (outf, iregs (i));
2041 OUTS (outf, " += ");
2042 OUTS (outf, mregs (m));
2043 }
2044 else if (op == 1 && br == 0)
2045 {
2046 OUTS (outf, iregs (i));
2047 OUTS (outf, " -= ");
2048 OUTS (outf, mregs (m));
2049 }
2050 else
2051 return 0;
2052
2053 return 2;
2054 }
2055
2056 static int
2057 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2058 {
2059 /* dagMODik
2060 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2061 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2062 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2063 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2064 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2065
2066 if (op == 0)
2067 {
2068 OUTS (outf, iregs (i));
2069 OUTS (outf, " += 0x2");
2070 }
2071 else if (op == 1)
2072 {
2073 OUTS (outf, iregs (i));
2074 OUTS (outf, " -= 0x2");
2075 }
2076 else if (op == 2)
2077 {
2078 OUTS (outf, iregs (i));
2079 OUTS (outf, " += 0x4");
2080 }
2081 else if (op == 3)
2082 {
2083 OUTS (outf, iregs (i));
2084 OUTS (outf, " -= 0x4");
2085 }
2086 else
2087 return 0;
2088
2089 if (! parallel )
2090 {
2091 OUTS (outf, ";\t\t/* ( ");
2092 if (op == 0 || op == 1)
2093 OUTS (outf, "2");
2094 else if (op == 2 || op == 3)
2095 OUTS (outf, "4");
2096 OUTS (outf, ") */");
2097 comment = 1;
2098 }
2099
2100 return 2;
2101 }
2102
2103 static int
2104 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2105 {
2106 /* dspLDST
2107 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2108 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2109 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2110 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2111 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2112 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2113 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2114 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2115
2116 if (aop == 0 && W == 0 && m == 0)
2117 {
2118 OUTS (outf, dregs (reg));
2119 OUTS (outf, " = [");
2120 OUTS (outf, iregs (i));
2121 OUTS (outf, "++]");
2122 }
2123 else if (aop == 0 && W == 0 && m == 1)
2124 {
2125 OUTS (outf, dregs_lo (reg));
2126 OUTS (outf, " = W[");
2127 OUTS (outf, iregs (i));
2128 OUTS (outf, "++]");
2129 }
2130 else if (aop == 0 && W == 0 && m == 2)
2131 {
2132 OUTS (outf, dregs_hi (reg));
2133 OUTS (outf, " = W[");
2134 OUTS (outf, iregs (i));
2135 OUTS (outf, "++]");
2136 }
2137 else if (aop == 1 && W == 0 && m == 0)
2138 {
2139 OUTS (outf, dregs (reg));
2140 OUTS (outf, " = [");
2141 OUTS (outf, iregs (i));
2142 OUTS (outf, "--]");
2143 }
2144 else if (aop == 1 && W == 0 && m == 1)
2145 {
2146 OUTS (outf, dregs_lo (reg));
2147 OUTS (outf, " = W[");
2148 OUTS (outf, iregs (i));
2149 OUTS (outf, "--]");
2150 }
2151 else if (aop == 1 && W == 0 && m == 2)
2152 {
2153 OUTS (outf, dregs_hi (reg));
2154 OUTS (outf, " = W[");
2155 OUTS (outf, iregs (i));
2156 OUTS (outf, "--]");
2157 }
2158 else if (aop == 2 && W == 0 && m == 0)
2159 {
2160 OUTS (outf, dregs (reg));
2161 OUTS (outf, " = [");
2162 OUTS (outf, iregs (i));
2163 OUTS (outf, "]");
2164 }
2165 else if (aop == 2 && W == 0 && m == 1)
2166 {
2167 OUTS (outf, dregs_lo (reg));
2168 OUTS (outf, " = W[");
2169 OUTS (outf, iregs (i));
2170 OUTS (outf, "]");
2171 }
2172 else if (aop == 2 && W == 0 && m == 2)
2173 {
2174 OUTS (outf, dregs_hi (reg));
2175 OUTS (outf, " = W[");
2176 OUTS (outf, iregs (i));
2177 OUTS (outf, "]");
2178 }
2179 else if (aop == 0 && W == 1 && m == 0)
2180 {
2181 OUTS (outf, "[");
2182 OUTS (outf, iregs (i));
2183 OUTS (outf, "++] = ");
2184 OUTS (outf, dregs (reg));
2185 }
2186 else if (aop == 0 && W == 1 && m == 1)
2187 {
2188 OUTS (outf, "W[");
2189 OUTS (outf, iregs (i));
2190 OUTS (outf, "++] = ");
2191 OUTS (outf, dregs_lo (reg));
2192 }
2193 else if (aop == 0 && W == 1 && m == 2)
2194 {
2195 OUTS (outf, "W[");
2196 OUTS (outf, iregs (i));
2197 OUTS (outf, "++] = ");
2198 OUTS (outf, dregs_hi (reg));
2199 }
2200 else if (aop == 1 && W == 1 && m == 0)
2201 {
2202 OUTS (outf, "[");
2203 OUTS (outf, iregs (i));
2204 OUTS (outf, "--] = ");
2205 OUTS (outf, dregs (reg));
2206 }
2207 else if (aop == 1 && W == 1 && m == 1)
2208 {
2209 OUTS (outf, "W[");
2210 OUTS (outf, iregs (i));
2211 OUTS (outf, "--] = ");
2212 OUTS (outf, dregs_lo (reg));
2213 }
2214 else if (aop == 1 && W == 1 && m == 2)
2215 {
2216 OUTS (outf, "W[");
2217 OUTS (outf, iregs (i));
2218 OUTS (outf, "--] = ");
2219 OUTS (outf, dregs_hi (reg));
2220 }
2221 else if (aop == 2 && W == 1 && m == 0)
2222 {
2223 OUTS (outf, "[");
2224 OUTS (outf, iregs (i));
2225 OUTS (outf, "] = ");
2226 OUTS (outf, dregs (reg));
2227 }
2228 else if (aop == 2 && W == 1 && m == 1)
2229 {
2230 OUTS (outf, "W[");
2231 OUTS (outf, iregs (i));
2232 OUTS (outf, "] = ");
2233 OUTS (outf, dregs_lo (reg));
2234 }
2235 else if (aop == 2 && W == 1 && m == 2)
2236 {
2237 OUTS (outf, "W[");
2238 OUTS (outf, iregs (i));
2239 OUTS (outf, "] = ");
2240 OUTS (outf, dregs_hi (reg));
2241 }
2242 else if (aop == 3 && W == 0)
2243 {
2244 OUTS (outf, dregs (reg));
2245 OUTS (outf, " = [");
2246 OUTS (outf, iregs (i));
2247 OUTS (outf, " ++ ");
2248 OUTS (outf, mregs (m));
2249 OUTS (outf, "]");
2250 }
2251 else if (aop == 3 && W == 1)
2252 {
2253 OUTS (outf, "[");
2254 OUTS (outf, iregs (i));
2255 OUTS (outf, " ++ ");
2256 OUTS (outf, mregs (m));
2257 OUTS (outf, "] = ");
2258 OUTS (outf, dregs (reg));
2259 }
2260 else
2261 return 0;
2262
2263 return 2;
2264 }
2265
2266 static int
2267 decode_LDST_0 (TIword iw0, disassemble_info *outf)
2268 {
2269 /* LDST
2270 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2271 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2272 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2273 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2274 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2275 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2276 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2277 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2278 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2279
2280 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2281 {
2282 OUTS (outf, dregs (reg));
2283 OUTS (outf, " = [");
2284 OUTS (outf, pregs (ptr));
2285 OUTS (outf, "++]");
2286 }
2287 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2288 {
2289 OUTS (outf, pregs (reg));
2290 OUTS (outf, " = [");
2291 OUTS (outf, pregs (ptr));
2292 OUTS (outf, "++]");
2293 }
2294 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2295 {
2296 OUTS (outf, dregs (reg));
2297 OUTS (outf, " = W[");
2298 OUTS (outf, pregs (ptr));
2299 OUTS (outf, "++] (Z)");
2300 }
2301 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2302 {
2303 OUTS (outf, dregs (reg));
2304 OUTS (outf, " = W[");
2305 OUTS (outf, pregs (ptr));
2306 OUTS (outf, "++] (X)");
2307 }
2308 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2309 {
2310 OUTS (outf, dregs (reg));
2311 OUTS (outf, " = B[");
2312 OUTS (outf, pregs (ptr));
2313 OUTS (outf, "++] (Z)");
2314 }
2315 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2316 {
2317 OUTS (outf, dregs (reg));
2318 OUTS (outf, " = B[");
2319 OUTS (outf, pregs (ptr));
2320 OUTS (outf, "++] (X)");
2321 }
2322 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2323 {
2324 OUTS (outf, dregs (reg));
2325 OUTS (outf, " = [");
2326 OUTS (outf, pregs (ptr));
2327 OUTS (outf, "--]");
2328 }
2329 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2330 {
2331 OUTS (outf, pregs (reg));
2332 OUTS (outf, " = [");
2333 OUTS (outf, pregs (ptr));
2334 OUTS (outf, "--]");
2335 }
2336 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2337 {
2338 OUTS (outf, dregs (reg));
2339 OUTS (outf, " = W[");
2340 OUTS (outf, pregs (ptr));
2341 OUTS (outf, "--] (Z)");
2342 }
2343 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2344 {
2345 OUTS (outf, dregs (reg));
2346 OUTS (outf, " = W[");
2347 OUTS (outf, pregs (ptr));
2348 OUTS (outf, "--] (X)");
2349 }
2350 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2351 {
2352 OUTS (outf, dregs (reg));
2353 OUTS (outf, " = B[");
2354 OUTS (outf, pregs (ptr));
2355 OUTS (outf, "--] (Z)");
2356 }
2357 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2358 {
2359 OUTS (outf, dregs (reg));
2360 OUTS (outf, " = B[");
2361 OUTS (outf, pregs (ptr));
2362 OUTS (outf, "--] (X)");
2363 }
2364 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2365 {
2366 OUTS (outf, dregs (reg));
2367 OUTS (outf, " = [");
2368 OUTS (outf, pregs (ptr));
2369 OUTS (outf, "]");
2370 }
2371 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2372 {
2373 OUTS (outf, pregs (reg));
2374 OUTS (outf, " = [");
2375 OUTS (outf, pregs (ptr));
2376 OUTS (outf, "]");
2377 }
2378 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2379 {
2380 OUTS (outf, dregs (reg));
2381 OUTS (outf, " = W[");
2382 OUTS (outf, pregs (ptr));
2383 OUTS (outf, "] (Z)");
2384 }
2385 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2386 {
2387 OUTS (outf, dregs (reg));
2388 OUTS (outf, " = W[");
2389 OUTS (outf, pregs (ptr));
2390 OUTS (outf, "] (X)");
2391 }
2392 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2393 {
2394 OUTS (outf, dregs (reg));
2395 OUTS (outf, " = B[");
2396 OUTS (outf, pregs (ptr));
2397 OUTS (outf, "] (Z)");
2398 }
2399 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2400 {
2401 OUTS (outf, dregs (reg));
2402 OUTS (outf, " = B[");
2403 OUTS (outf, pregs (ptr));
2404 OUTS (outf, "] (X)");
2405 }
2406 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2407 {
2408 OUTS (outf, "[");
2409 OUTS (outf, pregs (ptr));
2410 OUTS (outf, "++] = ");
2411 OUTS (outf, dregs (reg));
2412 }
2413 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2414 {
2415 OUTS (outf, "[");
2416 OUTS (outf, pregs (ptr));
2417 OUTS (outf, "++] = ");
2418 OUTS (outf, pregs (reg));
2419 }
2420 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2421 {
2422 OUTS (outf, "W[");
2423 OUTS (outf, pregs (ptr));
2424 OUTS (outf, "++] = ");
2425 OUTS (outf, dregs (reg));
2426 }
2427 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2428 {
2429 OUTS (outf, "B[");
2430 OUTS (outf, pregs (ptr));
2431 OUTS (outf, "++] = ");
2432 OUTS (outf, dregs (reg));
2433 }
2434 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2435 {
2436 OUTS (outf, "[");
2437 OUTS (outf, pregs (ptr));
2438 OUTS (outf, "--] = ");
2439 OUTS (outf, dregs (reg));
2440 }
2441 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2442 {
2443 OUTS (outf, "[");
2444 OUTS (outf, pregs (ptr));
2445 OUTS (outf, "--] = ");
2446 OUTS (outf, pregs (reg));
2447 }
2448 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2449 {
2450 OUTS (outf, "W[");
2451 OUTS (outf, pregs (ptr));
2452 OUTS (outf, "--] = ");
2453 OUTS (outf, dregs (reg));
2454 }
2455 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2456 {
2457 OUTS (outf, "B[");
2458 OUTS (outf, pregs (ptr));
2459 OUTS (outf, "--] = ");
2460 OUTS (outf, dregs (reg));
2461 }
2462 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2463 {
2464 OUTS (outf, "[");
2465 OUTS (outf, pregs (ptr));
2466 OUTS (outf, "] = ");
2467 OUTS (outf, dregs (reg));
2468 }
2469 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2470 {
2471 OUTS (outf, "[");
2472 OUTS (outf, pregs (ptr));
2473 OUTS (outf, "] = ");
2474 OUTS (outf, pregs (reg));
2475 }
2476 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2477 {
2478 OUTS (outf, "W[");
2479 OUTS (outf, pregs (ptr));
2480 OUTS (outf, "] = ");
2481 OUTS (outf, dregs (reg));
2482 }
2483 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2484 {
2485 OUTS (outf, "B[");
2486 OUTS (outf, pregs (ptr));
2487 OUTS (outf, "] = ");
2488 OUTS (outf, dregs (reg));
2489 }
2490 else
2491 return 0;
2492
2493 return 2;
2494 }
2495
2496 static int
2497 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2498 {
2499 /* LDSTiiFP
2500 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2501 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2502 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2503 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2504 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2505 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2506
2507 if (W == 0)
2508 {
2509 OUTS (outf, dpregs (reg));
2510 OUTS (outf, " = [FP ");
2511 OUTS (outf, negimm5s4 (offset));
2512 OUTS (outf, "]");
2513 }
2514 else if (W == 1)
2515 {
2516 OUTS (outf, "[FP ");
2517 OUTS (outf, negimm5s4 (offset));
2518 OUTS (outf, "] = ");
2519 OUTS (outf, dpregs (reg));
2520 }
2521 else
2522 return 0;
2523
2524 return 2;
2525 }
2526
2527 static int
2528 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2529 {
2530 /* LDSTii
2531 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2532 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2533 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2534 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2535 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2536 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2537 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2538 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2539
2540 if (W == 0 && op == 0)
2541 {
2542 OUTS (outf, dregs (reg));
2543 OUTS (outf, " = [");
2544 OUTS (outf, pregs (ptr));
2545 OUTS (outf, " + ");
2546 OUTS (outf, uimm4s4 (offset));
2547 OUTS (outf, "]");
2548 }
2549 else if (W == 0 && op == 1)
2550 {
2551 OUTS (outf, dregs (reg));
2552 OUTS (outf, " = W[");
2553 OUTS (outf, pregs (ptr));
2554 OUTS (outf, " + ");
2555 OUTS (outf, uimm4s2 (offset));
2556 OUTS (outf, "] (Z)");
2557 }
2558 else if (W == 0 && op == 2)
2559 {
2560 OUTS (outf, dregs (reg));
2561 OUTS (outf, " = W[");
2562 OUTS (outf, pregs (ptr));
2563 OUTS (outf, " + ");
2564 OUTS (outf, uimm4s2 (offset));
2565 OUTS (outf, "] (X)");
2566 }
2567 else if (W == 0 && op == 3)
2568 {
2569 OUTS (outf, pregs (reg));
2570 OUTS (outf, " = [");
2571 OUTS (outf, pregs (ptr));
2572 OUTS (outf, " + ");
2573 OUTS (outf, uimm4s4 (offset));
2574 OUTS (outf, "]");
2575 }
2576 else if (W == 1 && op == 0)
2577 {
2578 OUTS (outf, "[");
2579 OUTS (outf, pregs (ptr));
2580 OUTS (outf, " + ");
2581 OUTS (outf, uimm4s4 (offset));
2582 OUTS (outf, "] = ");
2583 OUTS (outf, dregs (reg));
2584 }
2585 else if (W == 1 && op == 1)
2586 {
2587 OUTS (outf, "W[");
2588 OUTS (outf, pregs (ptr));
2589 OUTS (outf, " + ");
2590 OUTS (outf, uimm4s2 (offset));
2591 OUTS (outf, "] = ");
2592 OUTS (outf, dregs (reg));
2593 }
2594 else if (W == 1 && op == 3)
2595 {
2596 OUTS (outf, "[");
2597 OUTS (outf, pregs (ptr));
2598 OUTS (outf, " + ");
2599 OUTS (outf, uimm4s4 (offset));
2600 OUTS (outf, "] = ");
2601 OUTS (outf, pregs (reg));
2602 }
2603 else
2604 return 0;
2605
2606 return 2;
2607 }
2608
2609 static int
2610 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2611 {
2612 /* LoopSetup
2613 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2614 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2615 |.reg...........| - | - |.eoffset...............................|
2616 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2617 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2618 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2619 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2620 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2621 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2622
2623 if (parallel)
2624 return 0;
2625
2626 if (reg > 7)
2627 return 0;
2628
2629 if (rop == 0)
2630 {
2631 OUTS (outf, "LSETUP");
2632 OUTS (outf, "(0x");
2633 OUTS (outf, pcrel4 (soffset));
2634 OUTS (outf, ", 0x");
2635 OUTS (outf, lppcrel10 (eoffset));
2636 OUTS (outf, ") ");
2637 OUTS (outf, counters (c));
2638 }
2639 else if (rop == 1)
2640 {
2641 OUTS (outf, "LSETUP");
2642 OUTS (outf, "(0x");
2643 OUTS (outf, pcrel4 (soffset));
2644 OUTS (outf, ", 0x");
2645 OUTS (outf, lppcrel10 (eoffset));
2646 OUTS (outf, ") ");
2647 OUTS (outf, counters (c));
2648 OUTS (outf, " = ");
2649 OUTS (outf, pregs (reg));
2650 }
2651 else if (rop == 3)
2652 {
2653 OUTS (outf, "LSETUP");
2654 OUTS (outf, "(0x");
2655 OUTS (outf, pcrel4 (soffset));
2656 OUTS (outf, ", 0x");
2657 OUTS (outf, lppcrel10 (eoffset));
2658 OUTS (outf, ") ");
2659 OUTS (outf, counters (c));
2660 OUTS (outf, " = ");
2661 OUTS (outf, pregs (reg));
2662 OUTS (outf, " >> 0x1");
2663 }
2664 else
2665 return 0;
2666
2667 return 4;
2668 }
2669
2670 static int
2671 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2672 {
2673 /* LDIMMhalf
2674 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2675 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2676 |.hword.........................................................|
2677 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2678 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2679 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2680 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2681 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2682 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2683 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2684
2685 bu32 *pval = get_allreg (grp, reg);
2686
2687 if (parallel)
2688 return 0;
2689
2690 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2691 to combine them, so it prints out the right values.
2692 Here we keep track of the registers. */
2693 if (H == 0 && S == 1 && Z == 0)
2694 {
2695 /* regs = imm16 (x) */
2696 *pval = imm16_val (hword);
2697 if (hword & 0x8000)
2698 *pval |= 0xFFFF0000;
2699 else
2700 *pval &= 0xFFFF;
2701 }
2702 else if (H == 0 && S == 0 && Z == 1)
2703 {
2704 /* regs = luimm16 (Z) */
2705 *pval = luimm16_val (hword);
2706 *pval &= 0xFFFF;
2707 }
2708 else if (H == 0 && S == 0 && Z == 0)
2709 {
2710 /* regs_lo = luimm16 */
2711 *pval &= 0xFFFF0000;
2712 *pval |= luimm16_val (hword);
2713 }
2714 else if (H == 1 && S == 0 && Z == 0)
2715 {
2716 /* regs_hi = huimm16 */
2717 *pval &= 0xFFFF;
2718 *pval |= luimm16_val (hword) << 16;
2719 }
2720
2721 /* Here we do the disassembly */
2722 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2723 {
2724 OUTS (outf, dregs_lo (reg));
2725 OUTS (outf, " = ");
2726 OUTS (outf, uimm16 (hword));
2727 }
2728 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2729 {
2730 OUTS (outf, dregs_hi (reg));
2731 OUTS (outf, " = ");
2732 OUTS (outf, uimm16 (hword));
2733 }
2734 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2735 {
2736 OUTS (outf, dregs (reg));
2737 OUTS (outf, " = ");
2738 OUTS (outf, imm16 (hword));
2739 OUTS (outf, " (X)");
2740 }
2741 else if (H == 0 && S == 1 && Z == 0)
2742 {
2743 OUTS (outf, regs (reg, grp));
2744 OUTS (outf, " = ");
2745 OUTS (outf, imm16 (hword));
2746 OUTS (outf, " (X)");
2747 }
2748 else if (H == 0 && S == 0 && Z == 1)
2749 {
2750 OUTS (outf, regs (reg, grp));
2751 OUTS (outf, " = ");
2752 OUTS (outf, uimm16 (hword));
2753 OUTS (outf, " (Z)");
2754 }
2755 else if (H == 0 && S == 0 && Z == 0)
2756 {
2757 OUTS (outf, regs_lo (reg, grp));
2758 OUTS (outf, " = ");
2759 OUTS (outf, uimm16 (hword));
2760 }
2761 else if (H == 1 && S == 0 && Z == 0)
2762 {
2763 OUTS (outf, regs_hi (reg, grp));
2764 OUTS (outf, " = ");
2765 OUTS (outf, uimm16 (hword));
2766 }
2767 else
2768 return 0;
2769
2770 /* And we print out the 32-bit value if it is a pointer. */
2771 if (S == 0 && Z == 0)
2772 {
2773 OUTS (outf, ";\t\t/* (");
2774 OUTS (outf, imm16d (hword));
2775 OUTS (outf, ")\t");
2776
2777 /* If it is an MMR, don't print the symbol. */
2778 if (*pval < 0xFFC00000 && grp == 1)
2779 {
2780 OUTS (outf, regs (reg, grp));
2781 OUTS (outf, "=0x");
2782 OUTS (outf, huimm32e (*pval));
2783 }
2784 else
2785 {
2786 OUTS (outf, regs (reg, grp));
2787 OUTS (outf, "=0x");
2788 OUTS (outf, huimm32e (*pval));
2789 OUTS (outf, "(");
2790 OUTS (outf, imm32 (*pval));
2791 OUTS (outf, ")");
2792 }
2793
2794 OUTS (outf, " */");
2795 comment = 1;
2796 }
2797 if (S == 1 || Z == 1)
2798 {
2799 OUTS (outf, ";\t\t/*\t\t");
2800 OUTS (outf, regs (reg, grp));
2801 OUTS (outf, "=0x");
2802 OUTS (outf, huimm32e (*pval));
2803 OUTS (outf, "(");
2804 OUTS (outf, imm32 (*pval));
2805 OUTS (outf, ") */");
2806 comment = 1;
2807 }
2808 return 4;
2809 }
2810
2811 static int
2812 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2813 {
2814 /* CALLa
2815 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2816 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2817 |.lsw...........................................................|
2818 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2819 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2820 int lsw = ((iw1 >> 0) & 0xffff);
2821 int msw = ((iw0 >> 0) & 0xff);
2822
2823 if (parallel)
2824 return 0;
2825
2826 if (S == 1)
2827 OUTS (outf, "CALL 0x");
2828 else if (S == 0)
2829 OUTS (outf, "JUMP.L 0x");
2830 else
2831 return 0;
2832
2833 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2834 return 4;
2835 }
2836
2837 static int
2838 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2839 {
2840 /* LDSTidxI
2841 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2842 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2843 |.offset........................................................|
2844 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2845 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2846 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2847 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2848 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2849 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2850 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2851
2852 if (W == 0 && sz == 0 && Z == 0)
2853 {
2854 OUTS (outf, dregs (reg));
2855 OUTS (outf, " = [");
2856 OUTS (outf, pregs (ptr));
2857 OUTS (outf, " + ");
2858 OUTS (outf, imm16s4 (offset));
2859 OUTS (outf, "]");
2860 }
2861 else if (W == 0 && sz == 0 && Z == 1)
2862 {
2863 OUTS (outf, pregs (reg));
2864 OUTS (outf, " = [");
2865 OUTS (outf, pregs (ptr));
2866 OUTS (outf, " + ");
2867 OUTS (outf, imm16s4 (offset));
2868 OUTS (outf, "]");
2869 }
2870 else if (W == 0 && sz == 1 && Z == 0)
2871 {
2872 OUTS (outf, dregs (reg));
2873 OUTS (outf, " = W[");
2874 OUTS (outf, pregs (ptr));
2875 OUTS (outf, " + ");
2876 OUTS (outf, imm16s2 (offset));
2877 OUTS (outf, "] (Z)");
2878 }
2879 else if (W == 0 && sz == 1 && Z == 1)
2880 {
2881 OUTS (outf, dregs (reg));
2882 OUTS (outf, " = W[");
2883 OUTS (outf, pregs (ptr));
2884 OUTS (outf, " + ");
2885 OUTS (outf, imm16s2 (offset));
2886 OUTS (outf, "] (X)");
2887 }
2888 else if (W == 0 && sz == 2 && Z == 0)
2889 {
2890 OUTS (outf, dregs (reg));
2891 OUTS (outf, " = B[");
2892 OUTS (outf, pregs (ptr));
2893 OUTS (outf, " + ");
2894 OUTS (outf, imm16 (offset));
2895 OUTS (outf, "] (Z)");
2896 }
2897 else if (W == 0 && sz == 2 && Z == 1)
2898 {
2899 OUTS (outf, dregs (reg));
2900 OUTS (outf, " = B[");
2901 OUTS (outf, pregs (ptr));
2902 OUTS (outf, " + ");
2903 OUTS (outf, imm16 (offset));
2904 OUTS (outf, "] (X)");
2905 }
2906 else if (W == 1 && sz == 0 && Z == 0)
2907 {
2908 OUTS (outf, "[");
2909 OUTS (outf, pregs (ptr));
2910 OUTS (outf, " + ");
2911 OUTS (outf, imm16s4 (offset));
2912 OUTS (outf, "] = ");
2913 OUTS (outf, dregs (reg));
2914 }
2915 else if (W == 1 && sz == 0 && Z == 1)
2916 {
2917 OUTS (outf, "[");
2918 OUTS (outf, pregs (ptr));
2919 OUTS (outf, " + ");
2920 OUTS (outf, imm16s4 (offset));
2921 OUTS (outf, "] = ");
2922 OUTS (outf, pregs (reg));
2923 }
2924 else if (W == 1 && sz == 1 && Z == 0)
2925 {
2926 OUTS (outf, "W[");
2927 OUTS (outf, pregs (ptr));
2928 OUTS (outf, " + ");
2929 OUTS (outf, imm16s2 (offset));
2930 OUTS (outf, "] = ");
2931 OUTS (outf, dregs (reg));
2932 }
2933 else if (W == 1 && sz == 2 && Z == 0)
2934 {
2935 OUTS (outf, "B[");
2936 OUTS (outf, pregs (ptr));
2937 OUTS (outf, " + ");
2938 OUTS (outf, imm16 (offset));
2939 OUTS (outf, "] = ");
2940 OUTS (outf, dregs (reg));
2941 }
2942 else
2943 return 0;
2944
2945 return 4;
2946 }
2947
2948 static int
2949 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2950 {
2951 /* linkage
2952 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2953 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2954 |.framesize.....................................................|
2955 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2956 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2957 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2958
2959 if (parallel)
2960 return 0;
2961
2962 if (R == 0)
2963 {
2964 OUTS (outf, "LINK ");
2965 OUTS (outf, uimm16s4 (framesize));
2966 OUTS (outf, ";\t\t/* (");
2967 OUTS (outf, uimm16s4d (framesize));
2968 OUTS (outf, ") */");
2969 comment = 1;
2970 }
2971 else if (R == 1)
2972 OUTS (outf, "UNLINK");
2973 else
2974 return 0;
2975
2976 return 4;
2977 }
2978
2979 static int
2980 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2981 {
2982 /* dsp32mac
2983 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2984 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2985 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2986 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2987 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2988 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2989 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2990 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2991 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2992 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2993 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2994 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2995 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2996 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2997 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2998 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2999 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3000 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3001
3002 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
3003 return 0;
3004
3005 if (op1 == 3 && MM)
3006 return 0;
3007
3008 if ((w1 || w0) && mmod == M_W32)
3009 return 0;
3010
3011 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
3012 return 0;
3013
3014 if (w1 == 1 || op1 != 3)
3015 {
3016 if (w1)
3017 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3018
3019 if (op1 == 3)
3020 OUTS (outf, " = A1");
3021 else
3022 {
3023 if (w1)
3024 OUTS (outf, " = (");
3025 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
3026 if (w1)
3027 OUTS (outf, ")");
3028 }
3029
3030 if (w0 == 1 || op0 != 3)
3031 {
3032 if (MM)
3033 OUTS (outf, " (M)");
3034 MM = 0;
3035 OUTS (outf, ", ");
3036 }
3037 }
3038
3039 if (w0 == 1 || op0 != 3)
3040 {
3041 if (w0)
3042 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3043
3044 if (op0 == 3)
3045 OUTS (outf, " = A0");
3046 else
3047 {
3048 if (w0)
3049 OUTS (outf, " = (");
3050 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3051 if (w0)
3052 OUTS (outf, ")");
3053 }
3054 }
3055
3056 decode_optmode (mmod, MM, outf);
3057
3058 return 4;
3059 }
3060
3061 static int
3062 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3063 {
3064 /* dsp32mult
3065 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3066 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3067 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3068 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3069 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3070 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3071 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
3072 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
3073 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3074 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3075 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3076 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3077 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3078 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3079 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3080 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3081
3082 if (w1 == 0 && w0 == 0)
3083 return 0;
3084
3085 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3086 return 0;
3087
3088 if (w1)
3089 {
3090 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3091 OUTS (outf, " = ");
3092 decode_multfunc (h01, h11, src0, src1, outf);
3093
3094 if (w0)
3095 {
3096 if (MM)
3097 OUTS (outf, " (M)");
3098 MM = 0;
3099 OUTS (outf, ", ");
3100 }
3101 }
3102
3103 if (w0)
3104 {
3105 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3106 OUTS (outf, " = ");
3107 decode_multfunc (h00, h10, src0, src1, outf);
3108 }
3109
3110 decode_optmode (mmod, MM, outf);
3111 return 4;
3112 }
3113
3114 static int
3115 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3116 {
3117 /* dsp32alu
3118 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3119 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3120 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3121 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3122 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3123 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3124 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3125 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3126 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3127 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3128 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3129 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3130 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3131
3132 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3133 {
3134 OUTS (outf, "A0.L = ");
3135 OUTS (outf, dregs_lo (src0));
3136 }
3137 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3138 {
3139 OUTS (outf, "A1.H = ");
3140 OUTS (outf, dregs_hi (src0));
3141 }
3142 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3143 {
3144 OUTS (outf, "A1.L = ");
3145 OUTS (outf, dregs_lo (src0));
3146 }
3147 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3148 {
3149 OUTS (outf, "A0.H = ");
3150 OUTS (outf, dregs_hi (src0));
3151 }
3152 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3153 {
3154 OUTS (outf, dregs_hi (dst0));
3155 OUTS (outf, " = ");
3156 OUTS (outf, dregs (src0));
3157 OUTS (outf, " - ");
3158 OUTS (outf, dregs (src1));
3159 OUTS (outf, " (RND20)");
3160 }
3161 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3162 {
3163 OUTS (outf, dregs_hi (dst0));
3164 OUTS (outf, " = ");
3165 OUTS (outf, dregs (src0));
3166 OUTS (outf, " + ");
3167 OUTS (outf, dregs (src1));
3168 OUTS (outf, " (RND20)");
3169 }
3170 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3171 {
3172 OUTS (outf, dregs_lo (dst0));
3173 OUTS (outf, " = ");
3174 OUTS (outf, dregs (src0));
3175 OUTS (outf, " - ");
3176 OUTS (outf, dregs (src1));
3177 OUTS (outf, " (RND12)");
3178 }
3179 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3180 {
3181 OUTS (outf, dregs_lo (dst0));
3182 OUTS (outf, " = ");
3183 OUTS (outf, dregs (src0));
3184 OUTS (outf, " + ");
3185 OUTS (outf, dregs (src1));
3186 OUTS (outf, " (RND12)");
3187 }
3188 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3189 {
3190 OUTS (outf, dregs_lo (dst0));
3191 OUTS (outf, " = ");
3192 OUTS (outf, dregs (src0));
3193 OUTS (outf, " - ");
3194 OUTS (outf, dregs (src1));
3195 OUTS (outf, " (RND20)");
3196 }
3197 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3198 {
3199 OUTS (outf, dregs_hi (dst0));
3200 OUTS (outf, " = ");
3201 OUTS (outf, dregs (src0));
3202 OUTS (outf, " + ");
3203 OUTS (outf, dregs (src1));
3204 OUTS (outf, " (RND12)");
3205 }
3206 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3207 {
3208 OUTS (outf, dregs_lo (dst0));
3209 OUTS (outf, " = ");
3210 OUTS (outf, dregs (src0));
3211 OUTS (outf, " + ");
3212 OUTS (outf, dregs (src1));
3213 OUTS (outf, " (RND20)");
3214 }
3215 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3216 {
3217 OUTS (outf, dregs_hi (dst0));
3218 OUTS (outf, " = ");
3219 OUTS (outf, dregs (src0));
3220 OUTS (outf, " - ");
3221 OUTS (outf, dregs (src1));
3222 OUTS (outf, " (RND12)");
3223 }
3224 else if (HL == 1 && aop == 0 && aopcde == 2)
3225 {
3226 OUTS (outf, dregs_hi (dst0));
3227 OUTS (outf, " = ");
3228 OUTS (outf, dregs_lo (src0));
3229 OUTS (outf, " + ");
3230 OUTS (outf, dregs_lo (src1));
3231 amod1 (s, x, outf);
3232 }
3233 else if (HL == 1 && aop == 1 && aopcde == 2)
3234 {
3235 OUTS (outf, dregs_hi (dst0));
3236 OUTS (outf, " = ");
3237 OUTS (outf, dregs_lo (src0));
3238 OUTS (outf, " + ");
3239 OUTS (outf, dregs_hi (src1));
3240 amod1 (s, x, outf);
3241 }
3242 else if (HL == 1 && aop == 2 && aopcde == 2)
3243 {
3244 OUTS (outf, dregs_hi (dst0));
3245 OUTS (outf, " = ");
3246 OUTS (outf, dregs_hi (src0));
3247 OUTS (outf, " + ");
3248 OUTS (outf, dregs_lo (src1));
3249 amod1 (s, x, outf);
3250 }
3251 else if (HL == 1 && aop == 3 && aopcde == 2)
3252 {
3253 OUTS (outf, dregs_hi (dst0));
3254 OUTS (outf, " = ");
3255 OUTS (outf, dregs_hi (src0));
3256 OUTS (outf, " + ");
3257 OUTS (outf, dregs_hi (src1));
3258 amod1 (s, x, outf);
3259 }
3260 else if (HL == 0 && aop == 0 && aopcde == 3)
3261 {
3262 OUTS (outf, dregs_lo (dst0));
3263 OUTS (outf, " = ");
3264 OUTS (outf, dregs_lo (src0));
3265 OUTS (outf, " - ");
3266 OUTS (outf, dregs_lo (src1));
3267 amod1 (s, x, outf);
3268 }
3269 else if (HL == 0 && aop == 1 && aopcde == 3)
3270 {
3271 OUTS (outf, dregs_lo (dst0));
3272 OUTS (outf, " = ");
3273 OUTS (outf, dregs_lo (src0));
3274 OUTS (outf, " - ");
3275 OUTS (outf, dregs_hi (src1));
3276 amod1 (s, x, outf);
3277 }
3278 else if (HL == 0 && aop == 3 && aopcde == 2)
3279 {
3280 OUTS (outf, dregs_lo (dst0));
3281 OUTS (outf, " = ");
3282 OUTS (outf, dregs_hi (src0));
3283 OUTS (outf, " + ");
3284 OUTS (outf, dregs_hi (src1));
3285 amod1 (s, x, outf);
3286 }
3287 else if (HL == 1 && aop == 0 && aopcde == 3)
3288 {
3289 OUTS (outf, dregs_hi (dst0));
3290 OUTS (outf, " = ");
3291 OUTS (outf, dregs_lo (src0));
3292 OUTS (outf, " - ");
3293 OUTS (outf, dregs_lo (src1));
3294 amod1 (s, x, outf);
3295 }
3296 else if (HL == 1 && aop == 1 && aopcde == 3)
3297 {
3298 OUTS (outf, dregs_hi (dst0));
3299 OUTS (outf, " = ");
3300 OUTS (outf, dregs_lo (src0));
3301 OUTS (outf, " - ");
3302 OUTS (outf, dregs_hi (src1));
3303 amod1 (s, x, outf);
3304 }
3305 else if (HL == 1 && aop == 2 && aopcde == 3)
3306 {
3307 OUTS (outf, dregs_hi (dst0));
3308 OUTS (outf, " = ");
3309 OUTS (outf, dregs_hi (src0));
3310 OUTS (outf, " - ");
3311 OUTS (outf, dregs_lo (src1));
3312 amod1 (s, x, outf);
3313 }
3314 else if (HL == 1 && aop == 3 && aopcde == 3)
3315 {
3316 OUTS (outf, dregs_hi (dst0));
3317 OUTS (outf, " = ");
3318 OUTS (outf, dregs_hi (src0));
3319 OUTS (outf, " - ");
3320 OUTS (outf, dregs_hi (src1));
3321 amod1 (s, x, outf);
3322 }
3323 else if (HL == 0 && aop == 2 && aopcde == 2)
3324 {
3325 OUTS (outf, dregs_lo (dst0));
3326 OUTS (outf, " = ");
3327 OUTS (outf, dregs_hi (src0));
3328 OUTS (outf, " + ");
3329 OUTS (outf, dregs_lo (src1));
3330 amod1 (s, x, outf);
3331 }
3332 else if (HL == 0 && aop == 1 && aopcde == 2)
3333 {
3334 OUTS (outf, dregs_lo (dst0));
3335 OUTS (outf, " = ");
3336 OUTS (outf, dregs_lo (src0));
3337 OUTS (outf, " + ");
3338 OUTS (outf, dregs_hi (src1));
3339 amod1 (s, x, outf);
3340 }
3341 else if (HL == 0 && aop == 2 && aopcde == 3)
3342 {
3343 OUTS (outf, dregs_lo (dst0));
3344 OUTS (outf, " = ");
3345 OUTS (outf, dregs_hi (src0));
3346 OUTS (outf, " - ");
3347 OUTS (outf, dregs_lo (src1));
3348 amod1 (s, x, outf);
3349 }
3350 else if (HL == 0 && aop == 3 && aopcde == 3)
3351 {
3352 OUTS (outf, dregs_lo (dst0));
3353 OUTS (outf, " = ");
3354 OUTS (outf, dregs_hi (src0));
3355 OUTS (outf, " - ");
3356 OUTS (outf, dregs_hi (src1));
3357 amod1 (s, x, outf);
3358 }
3359 else if (HL == 0 && aop == 0 && aopcde == 2)
3360 {
3361 OUTS (outf, dregs_lo (dst0));
3362 OUTS (outf, " = ");
3363 OUTS (outf, dregs_lo (src0));
3364 OUTS (outf, " + ");
3365 OUTS (outf, dregs_lo (src1));
3366 amod1 (s, x, outf);
3367 }
3368 else if (aop == 0 && aopcde == 9 && s == 1)
3369 {
3370 OUTS (outf, "A0 = ");
3371 OUTS (outf, dregs (src0));
3372 }
3373 else if (aop == 3 && aopcde == 11 && s == 0)
3374 OUTS (outf, "A0 -= A1");
3375
3376 else if (aop == 3 && aopcde == 11 && s == 1)
3377 OUTS (outf, "A0 -= A1 (W32)");
3378
3379 else if (aop == 1 && aopcde == 22 && HL == 1)
3380 {
3381 OUTS (outf, dregs (dst0));
3382 OUTS (outf, " = BYTEOP2P (");
3383 OUTS (outf, dregs (src0 + 1));
3384 OUTS (outf, ":");
3385 OUTS (outf, imm5d (src0));
3386 OUTS (outf, ", ");
3387 OUTS (outf, dregs (src1 + 1));
3388 OUTS (outf, ":");
3389 OUTS (outf, imm5d (src1));
3390 OUTS (outf, ") (TH");
3391 if (s == 1)
3392 OUTS (outf, ", R)");
3393 else
3394 OUTS (outf, ")");
3395 }
3396 else if (aop == 1 && aopcde == 22 && HL == 0)
3397 {
3398 OUTS (outf, dregs (dst0));
3399 OUTS (outf, " = BYTEOP2P (");
3400 OUTS (outf, dregs (src0 + 1));
3401 OUTS (outf, ":");
3402 OUTS (outf, imm5d (src0));
3403 OUTS (outf, ", ");
3404 OUTS (outf, dregs (src1 + 1));
3405 OUTS (outf, ":");
3406 OUTS (outf, imm5d (src1));
3407 OUTS (outf, ") (TL");
3408 if (s == 1)
3409 OUTS (outf, ", R)");
3410 else
3411 OUTS (outf, ")");
3412 }
3413 else if (aop == 0 && aopcde == 22 && HL == 1)
3414 {
3415 OUTS (outf, dregs (dst0));
3416 OUTS (outf, " = BYTEOP2P (");
3417 OUTS (outf, dregs (src0 + 1));
3418 OUTS (outf, ":");
3419 OUTS (outf, imm5d (src0));
3420 OUTS (outf, ", ");
3421 OUTS (outf, dregs (src1 + 1));
3422 OUTS (outf, ":");
3423 OUTS (outf, imm5d (src1));
3424 OUTS (outf, ") (RNDH");
3425 if (s == 1)
3426 OUTS (outf, ", R)");
3427 else
3428 OUTS (outf, ")");
3429 }
3430 else if (aop == 0 && aopcde == 22 && HL == 0)
3431 {
3432 OUTS (outf, dregs (dst0));
3433 OUTS (outf, " = BYTEOP2P (");
3434 OUTS (outf, dregs (src0 + 1));
3435 OUTS (outf, ":");
3436 OUTS (outf, imm5d (src0));
3437 OUTS (outf, ", ");
3438 OUTS (outf, dregs (src1 + 1));
3439 OUTS (outf, ":");
3440 OUTS (outf, imm5d (src1));
3441 OUTS (outf, ") (RNDL");
3442 if (s == 1)
3443 OUTS (outf, ", R)");
3444 else
3445 OUTS (outf, ")");
3446 }
3447 else if (aop == 0 && s == 0 && aopcde == 8)
3448 OUTS (outf, "A0 = 0");
3449
3450 else if (aop == 0 && s == 1 && aopcde == 8)
3451 OUTS (outf, "A0 = A0 (S)");
3452
3453 else if (aop == 1 && s == 0 && aopcde == 8)
3454 OUTS (outf, "A1 = 0");
3455
3456 else if (aop == 1 && s == 1 && aopcde == 8)
3457 OUTS (outf, "A1 = A1 (S)");
3458
3459 else if (aop == 2 && s == 0 && aopcde == 8)
3460 OUTS (outf, "A1 = A0 = 0");
3461
3462 else if (aop == 2 && s == 1 && aopcde == 8)
3463 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3464
3465 else if (aop == 3 && s == 0 && aopcde == 8)
3466 OUTS (outf, "A0 = A1");
3467
3468 else if (aop == 3 && s == 1 && aopcde == 8)
3469 OUTS (outf, "A1 = A0");
3470
3471 else if (aop == 1 && aopcde == 9 && s == 0)
3472 {
3473 OUTS (outf, "A0.X = ");
3474 OUTS (outf, dregs_lo (src0));
3475 }
3476 else if (aop == 1 && HL == 0 && aopcde == 11)
3477 {
3478 OUTS (outf, dregs_lo (dst0));
3479 OUTS (outf, " = (A0 += A1)");
3480 }
3481 else if (aop == 3 && HL == 0 && aopcde == 16)
3482 OUTS (outf, "A1 = ABS A1, A0 = ABS A0");
3483
3484 else if (aop == 0 && aopcde == 23 && HL == 1)
3485 {
3486 OUTS (outf, dregs (dst0));
3487 OUTS (outf, " = BYTEOP3P (");
3488 OUTS (outf, dregs (src0 + 1));
3489 OUTS (outf, ":");
3490 OUTS (outf, imm5d (src0));
3491 OUTS (outf, ", ");
3492 OUTS (outf, dregs (src1 + 1));
3493 OUTS (outf, ":");
3494 OUTS (outf, imm5d (src1));
3495 OUTS (outf, ") (HI");
3496 if (s == 1)
3497 OUTS (outf, ", R)");
3498 else
3499 OUTS (outf, ")");
3500 }
3501 else if (aop == 3 && aopcde == 9 && s == 0)
3502 {
3503 OUTS (outf, "A1.X = ");
3504 OUTS (outf, dregs_lo (src0));
3505 }
3506 else if (aop == 1 && HL == 1 && aopcde == 16)
3507 OUTS (outf, "A1 = ABS A1");
3508
3509 else if (aop == 0 && HL == 1 && aopcde == 16)
3510 OUTS (outf, "A1 = ABS A0");
3511
3512 else if (aop == 2 && aopcde == 9 && s == 1)
3513 {
3514 OUTS (outf, "A1 = ");
3515 OUTS (outf, dregs (src0));
3516 }
3517 else if (HL == 0 && aop == 3 && aopcde == 12)
3518 {
3519 OUTS (outf, dregs_lo (dst0));
3520 OUTS (outf, " = ");
3521 OUTS (outf, dregs (src0));
3522 OUTS (outf, " (RND)");
3523 }
3524 else if (aop == 1 && HL == 0 && aopcde == 16)
3525 OUTS (outf, "A0 = ABS A1");
3526
3527 else if (aop == 0 && HL == 0 && aopcde == 16)
3528 OUTS (outf, "A0 = ABS A0");
3529
3530 else if (aop == 3 && HL == 0 && aopcde == 15)
3531 {
3532 OUTS (outf, dregs (dst0));
3533 OUTS (outf, " = -");
3534 OUTS (outf, dregs (src0));
3535 OUTS (outf, " (V)");
3536 }
3537 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3538 {
3539 OUTS (outf, dregs (dst0));
3540 OUTS (outf, " = -");
3541 OUTS (outf, dregs (src0));
3542 OUTS (outf, " (S)");
3543 }
3544 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3545 {
3546 OUTS (outf, dregs (dst0));
3547 OUTS (outf, " = -");
3548 OUTS (outf, dregs (src0));
3549 OUTS (outf, " (NS)");
3550 }
3551 else if (aop == 1 && HL == 1 && aopcde == 11)
3552 {
3553 OUTS (outf, dregs_hi (dst0));
3554 OUTS (outf, " = (A0 += A1)");
3555 }
3556 else if (aop == 2 && aopcde == 11 && s == 0)
3557 OUTS (outf, "A0 += A1");
3558
3559 else if (aop == 2 && aopcde == 11 && s == 1)
3560 OUTS (outf, "A0 += A1 (W32)");
3561
3562 else if (aop == 3 && HL == 0 && aopcde == 14)
3563 OUTS (outf, "A1 = -A1, A0 = -A0");
3564
3565 else if (HL == 1 && aop == 3 && aopcde == 12)
3566 {
3567 OUTS (outf, dregs_hi (dst0));
3568 OUTS (outf, " = ");
3569 OUTS (outf, dregs (src0));
3570 OUTS (outf, " (RND)");
3571 }
3572 else if (aop == 0 && aopcde == 23 && HL == 0)
3573 {
3574 OUTS (outf, dregs (dst0));
3575 OUTS (outf, " = BYTEOP3P (");
3576 OUTS (outf, dregs (src0 + 1));
3577 OUTS (outf, ":");
3578 OUTS (outf, imm5d (src0));
3579 OUTS (outf, ", ");
3580 OUTS (outf, dregs (src1 + 1));
3581 OUTS (outf, ":");
3582 OUTS (outf, imm5d (src1));
3583 OUTS (outf, ") (LO");
3584 if (s == 1)
3585 OUTS (outf, ", R)");
3586 else
3587 OUTS (outf, ")");
3588 }
3589 else if (aop == 0 && HL == 0 && aopcde == 14)
3590 OUTS (outf, "A0 = -A0");
3591
3592 else if (aop == 1 && HL == 0 && aopcde == 14)
3593 OUTS (outf, "A0 = -A1");
3594
3595 else if (aop == 0 && HL == 1 && aopcde == 14)
3596 OUTS (outf, "A1 = -A0");
3597
3598 else if (aop == 1 && HL == 1 && aopcde == 14)
3599 OUTS (outf, "A1 = -A1");
3600
3601 else if (aop == 0 && aopcde == 12)
3602 {
3603 OUTS (outf, dregs_hi (dst0));
3604 OUTS (outf, " = ");
3605 OUTS (outf, dregs_lo (dst0));
3606 OUTS (outf, " = SIGN (");
3607 OUTS (outf, dregs_hi (src0));
3608 OUTS (outf, ") * ");
3609 OUTS (outf, dregs_hi (src1));
3610 OUTS (outf, " + SIGN (");
3611 OUTS (outf, dregs_lo (src0));
3612 OUTS (outf, ") * ");
3613 OUTS (outf, dregs_lo (src1));
3614 }
3615 else if (aop == 2 && aopcde == 0)
3616 {
3617 OUTS (outf, dregs (dst0));
3618 OUTS (outf, " = ");
3619 OUTS (outf, dregs (src0));
3620 OUTS (outf, " -|+ ");
3621 OUTS (outf, dregs (src1));
3622 amod0 (s, x, outf);
3623 }
3624 else if (aop == 1 && aopcde == 12)
3625 {
3626 OUTS (outf, dregs (dst1));
3627 OUTS (outf, " = A1.L + A1.H, ");
3628 OUTS (outf, dregs (dst0));
3629 OUTS (outf, " = A0.L + A0.H");
3630 }
3631 else if (aop == 2 && aopcde == 4)
3632 {
3633 OUTS (outf, dregs (dst1));
3634 OUTS (outf, " = ");
3635 OUTS (outf, dregs (src0));
3636 OUTS (outf, " + ");
3637 OUTS (outf, dregs (src1));
3638 OUTS (outf, ", ");
3639 OUTS (outf, dregs (dst0));
3640 OUTS (outf, " = ");
3641 OUTS (outf, dregs (src0));
3642 OUTS (outf, " - ");
3643 OUTS (outf, dregs (src1));
3644 amod1 (s, x, outf);
3645 }
3646 else if (HL == 0 && aopcde == 1)
3647 {
3648 OUTS (outf, dregs (dst1));
3649 OUTS (outf, " = ");
3650 OUTS (outf, dregs (src0));
3651 OUTS (outf, " +|+ ");
3652 OUTS (outf, dregs (src1));
3653 OUTS (outf, ", ");
3654 OUTS (outf, dregs (dst0));
3655 OUTS (outf, " = ");
3656 OUTS (outf, dregs (src0));
3657 OUTS (outf, " -|- ");
3658 OUTS (outf, dregs (src1));
3659 amod0amod2 (s, x, aop, outf);
3660 }
3661 else if (aop == 0 && aopcde == 11)
3662 {
3663 OUTS (outf, dregs (dst0));
3664 OUTS (outf, " = (A0 += A1)");
3665 }
3666 else if (aop == 0 && aopcde == 10)
3667 {
3668 OUTS (outf, dregs_lo (dst0));
3669 OUTS (outf, " = A0.X");
3670 }
3671 else if (aop == 1 && aopcde == 10)
3672 {
3673 OUTS (outf, dregs_lo (dst0));
3674 OUTS (outf, " = A1.X");
3675 }
3676 else if (aop == 1 && aopcde == 0)
3677 {
3678 OUTS (outf, dregs (dst0));
3679 OUTS (outf, " = ");
3680 OUTS (outf, dregs (src0));
3681 OUTS (outf, " +|- ");
3682 OUTS (outf, dregs (src1));
3683 amod0 (s, x, outf);
3684 }
3685 else if (aop == 3 && aopcde == 0)
3686 {
3687 OUTS (outf, dregs (dst0));
3688 OUTS (outf, " = ");
3689 OUTS (outf, dregs (src0));
3690 OUTS (outf, " -|- ");
3691 OUTS (outf, dregs (src1));
3692 amod0 (s, x, outf);
3693 }
3694 else if (aop == 1 && aopcde == 4)
3695 {
3696 OUTS (outf, dregs (dst0));
3697 OUTS (outf, " = ");
3698 OUTS (outf, dregs (src0));
3699 OUTS (outf, " - ");
3700 OUTS (outf, dregs (src1));
3701 amod1 (s, x, outf);
3702 }
3703 else if (aop == 0 && aopcde == 17)
3704 {
3705 OUTS (outf, dregs (dst1));
3706 OUTS (outf, " = A1 + A0, ");
3707 OUTS (outf, dregs (dst0));
3708 OUTS (outf, " = A1 - A0");
3709 amod1 (s, x, outf);
3710 }
3711 else if (aop == 1 && aopcde == 17)
3712 {
3713 OUTS (outf, dregs (dst1));
3714 OUTS (outf, " = A0 + A1, ");
3715 OUTS (outf, dregs (dst0));
3716 OUTS (outf, " = A0 - A1");
3717 amod1 (s, x, outf);
3718 }
3719 else if (aop == 0 && aopcde == 18)
3720 {
3721 OUTS (outf, "SAA (");
3722 OUTS (outf, dregs (src0 + 1));
3723 OUTS (outf, ":");
3724 OUTS (outf, imm5d (src0));
3725 OUTS (outf, ", ");
3726 OUTS (outf, dregs (src1 + 1));
3727 OUTS (outf, ":");
3728 OUTS (outf, imm5d (src1));
3729 OUTS (outf, ")");
3730 aligndir (s, outf);
3731 }
3732 else if (aop == 3 && aopcde == 18)
3733 OUTS (outf, "DISALGNEXCPT");
3734
3735 else if (aop == 0 && aopcde == 20)
3736 {
3737 OUTS (outf, dregs (dst0));
3738 OUTS (outf, " = BYTEOP1P (");
3739 OUTS (outf, dregs (src0 + 1));
3740 OUTS (outf, ":");
3741 OUTS (outf, imm5d (src0));
3742 OUTS (outf, ", ");
3743 OUTS (outf, dregs (src1 + 1));
3744 OUTS (outf, ":");
3745 OUTS (outf, imm5d (src1));
3746 OUTS (outf, ")");
3747 aligndir (s, outf);
3748 }
3749 else if (aop == 1 && aopcde == 20)
3750 {
3751 OUTS (outf, dregs (dst0));
3752 OUTS (outf, " = BYTEOP1P (");
3753 OUTS (outf, dregs (src0 + 1));
3754 OUTS (outf, ":");
3755 OUTS (outf, imm5d (src0));
3756 OUTS (outf, ", ");
3757 OUTS (outf, dregs (src1 + 1));
3758 OUTS (outf, ":");
3759 OUTS (outf, imm5d (src1));
3760 OUTS (outf, ") (T");
3761 if (s == 1)
3762 OUTS (outf, ", R)");
3763 else
3764 OUTS (outf, ")");
3765 }
3766 else if (aop == 0 && aopcde == 21)
3767 {
3768 OUTS (outf, "(");
3769 OUTS (outf, dregs (dst1));
3770 OUTS (outf, ", ");
3771 OUTS (outf, dregs (dst0));
3772 OUTS (outf, ") = BYTEOP16P (");
3773 OUTS (outf, dregs (src0 + 1));
3774 OUTS (outf, ":");
3775 OUTS (outf, imm5d (src0));
3776 OUTS (outf, ", ");
3777 OUTS (outf, dregs (src1 + 1));
3778 OUTS (outf, ":");
3779 OUTS (outf, imm5d (src1));
3780 OUTS (outf, ")");
3781 aligndir (s, outf);
3782 }
3783 else if (aop == 1 && aopcde == 21)
3784 {
3785 OUTS (outf, "(");
3786 OUTS (outf, dregs (dst1));
3787 OUTS (outf, ", ");
3788 OUTS (outf, dregs (dst0));
3789 OUTS (outf, ") = BYTEOP16M (");
3790 OUTS (outf, dregs (src0 + 1));
3791 OUTS (outf, ":");
3792 OUTS (outf, imm5d (src0));
3793 OUTS (outf, ", ");
3794 OUTS (outf, dregs (src1 + 1));
3795 OUTS (outf, ":");
3796 OUTS (outf, imm5d (src1));
3797 OUTS (outf, ")");
3798 aligndir (s, outf);
3799 }
3800 else if (aop == 2 && aopcde == 7)
3801 {
3802 OUTS (outf, dregs (dst0));
3803 OUTS (outf, " = ABS ");
3804 OUTS (outf, dregs (src0));
3805 }
3806 else if (aop == 1 && aopcde == 7)
3807 {
3808 OUTS (outf, dregs (dst0));
3809 OUTS (outf, " = MIN (");
3810 OUTS (outf, dregs (src0));
3811 OUTS (outf, ", ");
3812 OUTS (outf, dregs (src1));
3813 OUTS (outf, ")");
3814 }
3815 else if (aop == 0 && aopcde == 7)
3816 {
3817 OUTS (outf, dregs (dst0));
3818 OUTS (outf, " = MAX (");
3819 OUTS (outf, dregs (src0));
3820 OUTS (outf, ", ");
3821 OUTS (outf, dregs (src1));
3822 OUTS (outf, ")");
3823 }
3824 else if (aop == 2 && aopcde == 6)
3825 {
3826 OUTS (outf, dregs (dst0));
3827 OUTS (outf, " = ABS ");
3828 OUTS (outf, dregs (src0));
3829 OUTS (outf, " (V)");
3830 }
3831 else if (aop == 1 && aopcde == 6)
3832 {
3833 OUTS (outf, dregs (dst0));
3834 OUTS (outf, " = MIN (");
3835 OUTS (outf, dregs (src0));
3836 OUTS (outf, ", ");
3837 OUTS (outf, dregs (src1));
3838 OUTS (outf, ") (V)");
3839 }
3840 else if (aop == 0 && aopcde == 6)
3841 {
3842 OUTS (outf, dregs (dst0));
3843 OUTS (outf, " = MAX (");
3844 OUTS (outf, dregs (src0));
3845 OUTS (outf, ", ");
3846 OUTS (outf, dregs (src1));
3847 OUTS (outf, ") (V)");
3848 }
3849 else if (HL == 1 && aopcde == 1)
3850 {
3851 OUTS (outf, dregs (dst1));
3852 OUTS (outf, " = ");
3853 OUTS (outf, dregs (src0));
3854 OUTS (outf, " +|- ");
3855 OUTS (outf, dregs (src1));
3856 OUTS (outf, ", ");
3857 OUTS (outf, dregs (dst0));
3858 OUTS (outf, " = ");
3859 OUTS (outf, dregs (src0));
3860 OUTS (outf, " -|+ ");
3861 OUTS (outf, dregs (src1));
3862 amod0amod2 (s, x, aop, outf);
3863 }
3864 else if (aop == 0 && aopcde == 4)
3865 {
3866 OUTS (outf, dregs (dst0));
3867 OUTS (outf, " = ");
3868 OUTS (outf, dregs (src0));
3869 OUTS (outf, " + ");
3870 OUTS (outf, dregs (src1));
3871 amod1 (s, x, outf);
3872 }
3873 else if (aop == 0 && aopcde == 0)
3874 {
3875 OUTS (outf, dregs (dst0));
3876 OUTS (outf, " = ");
3877 OUTS (outf, dregs (src0));
3878 OUTS (outf, " +|+ ");
3879 OUTS (outf, dregs (src1));
3880 amod0 (s, x, outf);
3881 }
3882 else if (aop == 0 && aopcde == 24)
3883 {
3884 OUTS (outf, dregs (dst0));
3885 OUTS (outf, " = BYTEPACK (");
3886 OUTS (outf, dregs (src0));
3887 OUTS (outf, ", ");
3888 OUTS (outf, dregs (src1));
3889 OUTS (outf, ")");
3890 }
3891 else if (aop == 1 && aopcde == 24)
3892 {
3893 OUTS (outf, "(");
3894 OUTS (outf, dregs (dst1));
3895 OUTS (outf, ", ");
3896 OUTS (outf, dregs (dst0));
3897 OUTS (outf, ") = BYTEUNPACK ");
3898 OUTS (outf, dregs (src0 + 1));
3899 OUTS (outf, ":");
3900 OUTS (outf, imm5d (src0));
3901 aligndir (s, outf);
3902 }
3903 else if (aopcde == 13)
3904 {
3905 OUTS (outf, "(");
3906 OUTS (outf, dregs (dst1));
3907 OUTS (outf, ", ");
3908 OUTS (outf, dregs (dst0));
3909 OUTS (outf, ") = SEARCH ");
3910 OUTS (outf, dregs (src0));
3911 OUTS (outf, " (");
3912 searchmod (aop, outf);
3913 OUTS (outf, ")");
3914 }
3915 else
3916 return 0;
3917
3918 return 4;
3919 }
3920
3921 static int
3922 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3923 {
3924 /* dsp32shift
3925 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3926 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3927 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3928 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3929 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3930 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3931 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3932 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3933 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3934 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3935 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3936
3937 if (HLs == 0 && sop == 0 && sopcde == 0)
3938 {
3939 OUTS (outf, dregs_lo (dst0));
3940 OUTS (outf, " = ASHIFT ");
3941 OUTS (outf, dregs_lo (src1));
3942 OUTS (outf, " BY ");
3943 OUTS (outf, dregs_lo (src0));
3944 }
3945 else if (HLs == 1 && sop == 0 && sopcde == 0)
3946 {
3947 OUTS (outf, dregs_lo (dst0));
3948 OUTS (outf, " = ASHIFT ");
3949 OUTS (outf, dregs_hi (src1));
3950 OUTS (outf, " BY ");
3951 OUTS (outf, dregs_lo (src0));
3952 }
3953 else if (HLs == 2 && sop == 0 && sopcde == 0)
3954 {
3955 OUTS (outf, dregs_hi (dst0));
3956 OUTS (outf, " = ASHIFT ");
3957 OUTS (outf, dregs_lo (src1));
3958 OUTS (outf, " BY ");
3959 OUTS (outf, dregs_lo (src0));
3960 }
3961 else if (HLs == 3 && sop == 0 && sopcde == 0)
3962 {
3963 OUTS (outf, dregs_hi (dst0));
3964 OUTS (outf, " = ASHIFT ");
3965 OUTS (outf, dregs_hi (src1));
3966 OUTS (outf, " BY ");
3967 OUTS (outf, dregs_lo (src0));
3968 }
3969 else if (HLs == 0 && sop == 1 && sopcde == 0)
3970 {
3971 OUTS (outf, dregs_lo (dst0));
3972 OUTS (outf, " = ASHIFT ");
3973 OUTS (outf, dregs_lo (src1));
3974 OUTS (outf, " BY ");
3975 OUTS (outf, dregs_lo (src0));
3976 OUTS (outf, " (S)");
3977 }
3978 else if (HLs == 1 && sop == 1 && sopcde == 0)
3979 {
3980 OUTS (outf, dregs_lo (dst0));
3981 OUTS (outf, " = ASHIFT ");
3982 OUTS (outf, dregs_hi (src1));
3983 OUTS (outf, " BY ");
3984 OUTS (outf, dregs_lo (src0));
3985 OUTS (outf, " (S)");
3986 }
3987 else if (HLs == 2 && sop == 1 && sopcde == 0)
3988 {
3989 OUTS (outf, dregs_hi (dst0));
3990 OUTS (outf, " = ASHIFT ");
3991 OUTS (outf, dregs_lo (src1));
3992 OUTS (outf, " BY ");
3993 OUTS (outf, dregs_lo (src0));
3994 OUTS (outf, " (S)");
3995 }
3996 else if (HLs == 3 && sop == 1 && sopcde == 0)
3997 {
3998 OUTS (outf, dregs_hi (dst0));
3999 OUTS (outf, " = ASHIFT ");
4000 OUTS (outf, dregs_hi (src1));
4001 OUTS (outf, " BY ");
4002 OUTS (outf, dregs_lo (src0));
4003 OUTS (outf, " (S)");
4004 }
4005 else if (sop == 2 && sopcde == 0)
4006 {
4007 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
4008 OUTS (outf, " = LSHIFT ");
4009 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
4010 OUTS (outf, " BY ");
4011 OUTS (outf, dregs_lo (src0));
4012 }
4013 else if (sop == 0 && sopcde == 3)
4014 {
4015 OUTS (outf, acc01);
4016 OUTS (outf, " = ASHIFT ");
4017 OUTS (outf, acc01);
4018 OUTS (outf, " BY ");
4019 OUTS (outf, dregs_lo (src0));
4020 }
4021 else if (sop == 1 && sopcde == 3)
4022 {
4023 OUTS (outf, acc01);
4024 OUTS (outf, " = LSHIFT ");
4025 OUTS (outf, acc01);
4026 OUTS (outf, " BY ");
4027 OUTS (outf, dregs_lo (src0));
4028 }
4029 else if (sop == 2 && sopcde == 3)
4030 {
4031 OUTS (outf, acc01);
4032 OUTS (outf, " = ROT ");
4033 OUTS (outf, acc01);
4034 OUTS (outf, " BY ");
4035 OUTS (outf, dregs_lo (src0));
4036 }
4037 else if (sop == 3 && sopcde == 3)
4038 {
4039 OUTS (outf, dregs (dst0));
4040 OUTS (outf, " = ROT ");
4041 OUTS (outf, dregs (src1));
4042 OUTS (outf, " BY ");
4043 OUTS (outf, dregs_lo (src0));
4044 }
4045 else if (sop == 1 && sopcde == 1)
4046 {
4047 OUTS (outf, dregs (dst0));
4048 OUTS (outf, " = ASHIFT ");
4049 OUTS (outf, dregs (src1));
4050 OUTS (outf, " BY ");
4051 OUTS (outf, dregs_lo (src0));
4052 OUTS (outf, " (V, S)");
4053 }
4054 else if (sop == 0 && sopcde == 1)
4055 {
4056 OUTS (outf, dregs (dst0));
4057 OUTS (outf, " = ASHIFT ");
4058 OUTS (outf, dregs (src1));
4059 OUTS (outf, " BY ");
4060 OUTS (outf, dregs_lo (src0));
4061 OUTS (outf, " (V)");
4062 }
4063 else if (sop == 0 && sopcde == 2)
4064 {
4065 OUTS (outf, dregs (dst0));
4066 OUTS (outf, " = ASHIFT ");
4067 OUTS (outf, dregs (src1));
4068 OUTS (outf, " BY ");
4069 OUTS (outf, dregs_lo (src0));
4070 }
4071 else if (sop == 1 && sopcde == 2)
4072 {
4073 OUTS (outf, dregs (dst0));
4074 OUTS (outf, " = ASHIFT ");
4075 OUTS (outf, dregs (src1));
4076 OUTS (outf, " BY ");
4077 OUTS (outf, dregs_lo (src0));
4078 OUTS (outf, " (S)");
4079 }
4080 else if (sop == 2 && sopcde == 2)
4081 {
4082 OUTS (outf, dregs (dst0));
4083 OUTS (outf, " = LSHIFT ");
4084 OUTS (outf, dregs (src1));
4085 OUTS (outf, " BY ");
4086 OUTS (outf, dregs_lo (src0));
4087 }
4088 else if (sop == 3 && sopcde == 2)
4089 {
4090 OUTS (outf, dregs (dst0));
4091 OUTS (outf, " = ROT ");
4092 OUTS (outf, dregs (src1));
4093 OUTS (outf, " BY ");
4094 OUTS (outf, dregs_lo (src0));
4095 }
4096 else if (sop == 2 && sopcde == 1)
4097 {
4098 OUTS (outf, dregs (dst0));
4099 OUTS (outf, " = LSHIFT ");
4100 OUTS (outf, dregs (src1));
4101 OUTS (outf, " BY ");
4102 OUTS (outf, dregs_lo (src0));
4103 OUTS (outf, " (V)");
4104 }
4105 else if (sop == 0 && sopcde == 4)
4106 {
4107 OUTS (outf, dregs (dst0));
4108 OUTS (outf, " = PACK (");
4109 OUTS (outf, dregs_lo (src1));
4110 OUTS (outf, ", ");
4111 OUTS (outf, dregs_lo (src0));
4112 OUTS (outf, ")");
4113 }
4114 else if (sop == 1 && sopcde == 4)
4115 {
4116 OUTS (outf, dregs (dst0));
4117 OUTS (outf, " = PACK (");
4118 OUTS (outf, dregs_lo (src1));
4119 OUTS (outf, ", ");
4120 OUTS (outf, dregs_hi (src0));
4121 OUTS (outf, ")");
4122 }
4123 else if (sop == 2 && sopcde == 4)
4124 {
4125 OUTS (outf, dregs (dst0));
4126 OUTS (outf, " = PACK (");
4127 OUTS (outf, dregs_hi (src1));
4128 OUTS (outf, ", ");
4129 OUTS (outf, dregs_lo (src0));
4130 OUTS (outf, ")");
4131 }
4132 else if (sop == 3 && sopcde == 4)
4133 {
4134 OUTS (outf, dregs (dst0));
4135 OUTS (outf, " = PACK (");
4136 OUTS (outf, dregs_hi (src1));
4137 OUTS (outf, ", ");
4138 OUTS (outf, dregs_hi (src0));
4139 OUTS (outf, ")");
4140 }
4141 else if (sop == 0 && sopcde == 5)
4142 {
4143 OUTS (outf, dregs_lo (dst0));
4144 OUTS (outf, " = SIGNBITS ");
4145 OUTS (outf, dregs (src1));
4146 }
4147 else if (sop == 1 && sopcde == 5)
4148 {
4149 OUTS (outf, dregs_lo (dst0));
4150 OUTS (outf, " = SIGNBITS ");
4151 OUTS (outf, dregs_lo (src1));
4152 }
4153 else if (sop == 2 && sopcde == 5)
4154 {
4155 OUTS (outf, dregs_lo (dst0));
4156 OUTS (outf, " = SIGNBITS ");
4157 OUTS (outf, dregs_hi (src1));
4158 }
4159 else if (sop == 0 && sopcde == 6)
4160 {
4161 OUTS (outf, dregs_lo (dst0));
4162 OUTS (outf, " = SIGNBITS A0");
4163 }
4164 else if (sop == 1 && sopcde == 6)
4165 {
4166 OUTS (outf, dregs_lo (dst0));
4167 OUTS (outf, " = SIGNBITS A1");
4168 }
4169 else if (sop == 3 && sopcde == 6)
4170 {
4171 OUTS (outf, dregs_lo (dst0));
4172 OUTS (outf, " = ONES ");
4173 OUTS (outf, dregs (src1));
4174 }
4175 else if (sop == 0 && sopcde == 7)
4176 {
4177 OUTS (outf, dregs_lo (dst0));
4178 OUTS (outf, " = EXPADJ (");
4179 OUTS (outf, dregs (src1));
4180 OUTS (outf, ", ");
4181 OUTS (outf, dregs_lo (src0));
4182 OUTS (outf, ")");
4183 }
4184 else if (sop == 1 && sopcde == 7)
4185 {
4186 OUTS (outf, dregs_lo (dst0));
4187 OUTS (outf, " = EXPADJ (");
4188 OUTS (outf, dregs (src1));
4189 OUTS (outf, ", ");
4190 OUTS (outf, dregs_lo (src0));
4191 OUTS (outf, ") (V)");
4192 }
4193 else if (sop == 2 && sopcde == 7)
4194 {
4195 OUTS (outf, dregs_lo (dst0));
4196 OUTS (outf, " = EXPADJ (");
4197 OUTS (outf, dregs_lo (src1));
4198 OUTS (outf, ", ");
4199 OUTS (outf, dregs_lo (src0));
4200 OUTS (outf, ")");
4201 }
4202 else if (sop == 3 && sopcde == 7)
4203 {
4204 OUTS (outf, dregs_lo (dst0));
4205 OUTS (outf, " = EXPADJ (");
4206 OUTS (outf, dregs_hi (src1));
4207 OUTS (outf, ", ");
4208 OUTS (outf, dregs_lo (src0));
4209 OUTS (outf, ")");
4210 }
4211 else if (sop == 0 && sopcde == 8)
4212 {
4213 OUTS (outf, "BITMUX (");
4214 OUTS (outf, dregs (src0));
4215 OUTS (outf, ", ");
4216 OUTS (outf, dregs (src1));
4217 OUTS (outf, ", A0) (ASR)");
4218 }
4219 else if (sop == 1 && sopcde == 8)
4220 {
4221 OUTS (outf, "BITMUX (");
4222 OUTS (outf, dregs (src0));
4223 OUTS (outf, ", ");
4224 OUTS (outf, dregs (src1));
4225 OUTS (outf, ", A0) (ASL)");
4226 }
4227 else if (sop == 0 && sopcde == 9)
4228 {
4229 OUTS (outf, dregs_lo (dst0));
4230 OUTS (outf, " = VIT_MAX (");
4231 OUTS (outf, dregs (src1));
4232 OUTS (outf, ") (ASL)");
4233 }
4234 else if (sop == 1 && sopcde == 9)
4235 {
4236 OUTS (outf, dregs_lo (dst0));
4237 OUTS (outf, " = VIT_MAX (");
4238 OUTS (outf, dregs (src1));
4239 OUTS (outf, ") (ASR)");
4240 }
4241 else if (sop == 2 && sopcde == 9)
4242 {
4243 OUTS (outf, dregs (dst0));
4244 OUTS (outf, " = VIT_MAX (");
4245 OUTS (outf, dregs (src1));
4246 OUTS (outf, ", ");
4247 OUTS (outf, dregs (src0));
4248 OUTS (outf, ") (ASL)");
4249 }
4250 else if (sop == 3 && sopcde == 9)
4251 {
4252 OUTS (outf, dregs (dst0));
4253 OUTS (outf, " = VIT_MAX (");
4254 OUTS (outf, dregs (src1));
4255 OUTS (outf, ", ");
4256 OUTS (outf, dregs (src0));
4257 OUTS (outf, ") (ASR)");
4258 }
4259 else if (sop == 0 && sopcde == 10)
4260 {
4261 OUTS (outf, dregs (dst0));
4262 OUTS (outf, " = EXTRACT (");
4263 OUTS (outf, dregs (src1));
4264 OUTS (outf, ", ");
4265 OUTS (outf, dregs_lo (src0));
4266 OUTS (outf, ") (Z)");
4267 }
4268 else if (sop == 1 && sopcde == 10)
4269 {
4270 OUTS (outf, dregs (dst0));
4271 OUTS (outf, " = EXTRACT (");
4272 OUTS (outf, dregs (src1));
4273 OUTS (outf, ", ");
4274 OUTS (outf, dregs_lo (src0));
4275 OUTS (outf, ") (X)");
4276 }
4277 else if (sop == 2 && sopcde == 10)
4278 {
4279 OUTS (outf, dregs (dst0));
4280 OUTS (outf, " = DEPOSIT (");
4281 OUTS (outf, dregs (src1));
4282 OUTS (outf, ", ");
4283 OUTS (outf, dregs (src0));
4284 OUTS (outf, ")");
4285 }
4286 else if (sop == 3 && sopcde == 10)
4287 {
4288 OUTS (outf, dregs (dst0));
4289 OUTS (outf, " = DEPOSIT (");
4290 OUTS (outf, dregs (src1));
4291 OUTS (outf, ", ");
4292 OUTS (outf, dregs (src0));
4293 OUTS (outf, ") (X)");
4294 }
4295 else if (sop == 0 && sopcde == 11)
4296 {
4297 OUTS (outf, dregs_lo (dst0));
4298 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4299 OUTS (outf, dregs (src0));
4300 OUTS (outf, ")");
4301 }
4302 else if (sop == 1 && sopcde == 11)
4303 {
4304 OUTS (outf, dregs_lo (dst0));
4305 OUTS (outf, " = CC = BXOR (A0, ");
4306 OUTS (outf, dregs (src0));
4307 OUTS (outf, ")");
4308 }
4309 else if (sop == 0 && sopcde == 12)
4310 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4311
4312 else if (sop == 1 && sopcde == 12)
4313 {
4314 OUTS (outf, dregs_lo (dst0));
4315 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4316 }
4317 else if (sop == 0 && sopcde == 13)
4318 {
4319 OUTS (outf, dregs (dst0));
4320 OUTS (outf, " = ALIGN8 (");
4321 OUTS (outf, dregs (src1));
4322 OUTS (outf, ", ");
4323 OUTS (outf, dregs (src0));
4324 OUTS (outf, ")");
4325 }
4326 else if (sop == 1 && sopcde == 13)
4327 {
4328 OUTS (outf, dregs (dst0));
4329 OUTS (outf, " = ALIGN16 (");
4330 OUTS (outf, dregs (src1));
4331 OUTS (outf, ", ");
4332 OUTS (outf, dregs (src0));
4333 OUTS (outf, ")");
4334 }
4335 else if (sop == 2 && sopcde == 13)
4336 {
4337 OUTS (outf, dregs (dst0));
4338 OUTS (outf, " = ALIGN24 (");
4339 OUTS (outf, dregs (src1));
4340 OUTS (outf, ", ");
4341 OUTS (outf, dregs (src0));
4342 OUTS (outf, ")");
4343 }
4344 else
4345 return 0;
4346
4347 return 4;
4348 }
4349
4350 static int
4351 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4352 {
4353 /* dsp32shiftimm
4354 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4355 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4356 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4357 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4358 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4359 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4360 int bit8 = ((iw1 >> 8) & 0x1);
4361 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4362 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4363 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4364 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4365 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4366
4367
4368 if (sop == 0 && sopcde == 0)
4369 {
4370 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4371 OUTS (outf, " = ");
4372 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4373 OUTS (outf, " >>> ");
4374 OUTS (outf, uimm4 (newimmag));
4375 }
4376 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4377 {
4378 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4379 OUTS (outf, " = ");
4380 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4381 OUTS (outf, " << ");
4382 OUTS (outf, uimm4 (immag));
4383 OUTS (outf, " (S)");
4384 }
4385 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4386 {
4387 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4388 OUTS (outf, " = ");
4389 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4390 OUTS (outf, " >>> ");
4391 OUTS (outf, uimm4 (newimmag));
4392 OUTS (outf, " (S)");
4393 }
4394 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4395 {
4396 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4397 OUTS (outf, " = ");
4398 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4399 OUTS (outf, " << ");
4400 OUTS (outf, uimm4 (immag));
4401 }
4402 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4403 {
4404 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4405 OUTS (outf, " = ");
4406 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4407 OUTS (outf, " >> ");
4408 OUTS (outf, uimm4 (newimmag));
4409 }
4410 else if (sop == 2 && sopcde == 3 && HLs == 1)
4411 {
4412 OUTS (outf, "A1 = ROT A1 BY ");
4413 OUTS (outf, imm6 (immag));
4414 }
4415 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4416 {
4417 OUTS (outf, "A0 = A0 << ");
4418 OUTS (outf, uimm5 (immag));
4419 }
4420 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4421 {
4422 OUTS (outf, "A0 = A0 >>> ");
4423 OUTS (outf, uimm5 (newimmag));
4424 }
4425 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4426 {
4427 OUTS (outf, "A1 = A1 << ");
4428 OUTS (outf, uimm5 (immag));
4429 }
4430 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4431 {
4432 OUTS (outf, "A1 = A1 >>> ");
4433 OUTS (outf, uimm5 (newimmag));
4434 }
4435 else if (sop == 1 && sopcde == 3 && HLs == 0)
4436 {
4437 OUTS (outf, "A0 = A0 >> ");
4438 OUTS (outf, uimm5 (newimmag));
4439 }
4440 else if (sop == 1 && sopcde == 3 && HLs == 1)
4441 {
4442 OUTS (outf, "A1 = A1 >> ");
4443 OUTS (outf, uimm5 (newimmag));
4444 }
4445 else if (sop == 2 && sopcde == 3 && HLs == 0)
4446 {
4447 OUTS (outf, "A0 = ROT A0 BY ");
4448 OUTS (outf, imm6 (immag));
4449 }
4450 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4451 {
4452 OUTS (outf, dregs (dst0));
4453 OUTS (outf, " = ");
4454 OUTS (outf, dregs (src1));
4455 OUTS (outf, " << ");
4456 OUTS (outf, uimm5 (immag));
4457 OUTS (outf, " (V, S)");
4458 }
4459 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4460 {
4461 OUTS (outf, dregs (dst0));
4462 OUTS (outf, " = ");
4463 OUTS (outf, dregs (src1));
4464 OUTS (outf, " >>> ");
4465 OUTS (outf, imm5 (-immag));
4466 OUTS (outf, " (V, S)");
4467 }
4468 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4469 {
4470 OUTS (outf, dregs (dst0));
4471 OUTS (outf, " = ");
4472 OUTS (outf, dregs (src1));
4473 OUTS (outf, " >> ");
4474 OUTS (outf, uimm5 (newimmag));
4475 OUTS (outf, " (V)");
4476 }
4477 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4478 {
4479 OUTS (outf, dregs (dst0));
4480 OUTS (outf, " = ");
4481 OUTS (outf, dregs (src1));
4482 OUTS (outf, " << ");
4483 OUTS (outf, imm5 (immag));
4484 OUTS (outf, " (V)");
4485 }
4486 else if (sop == 0 && sopcde == 1)
4487 {
4488 OUTS (outf, dregs (dst0));
4489 OUTS (outf, " = ");
4490 OUTS (outf, dregs (src1));
4491 OUTS (outf, " >>> ");
4492 OUTS (outf, uimm5 (newimmag));
4493 OUTS (outf, " (V)");
4494 }
4495 else if (sop == 1 && sopcde == 2)
4496 {
4497 OUTS (outf, dregs (dst0));
4498 OUTS (outf, " = ");
4499 OUTS (outf, dregs (src1));
4500 OUTS (outf, " << ");
4501 OUTS (outf, uimm5 (immag));
4502 OUTS (outf, " (S)");
4503 }
4504 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4505 {
4506 OUTS (outf, dregs (dst0));
4507 OUTS (outf, " = ");
4508 OUTS (outf, dregs (src1));
4509 OUTS (outf, " >> ");
4510 OUTS (outf, uimm5 (newimmag));
4511 }
4512 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4513 {
4514 OUTS (outf, dregs (dst0));
4515 OUTS (outf, " = ");
4516 OUTS (outf, dregs (src1));
4517 OUTS (outf, " << ");
4518 OUTS (outf, uimm5 (immag));
4519 }
4520 else if (sop == 3 && sopcde == 2)
4521 {
4522 OUTS (outf, dregs (dst0));
4523 OUTS (outf, " = ROT ");
4524 OUTS (outf, dregs (src1));
4525 OUTS (outf, " BY ");
4526 OUTS (outf, imm6 (immag));
4527 }
4528 else if (sop == 0 && sopcde == 2)
4529 {
4530 OUTS (outf, dregs (dst0));
4531 OUTS (outf, " = ");
4532 OUTS (outf, dregs (src1));
4533 OUTS (outf, " >>> ");
4534 OUTS (outf, uimm5 (newimmag));
4535 }
4536 else
4537 return 0;
4538
4539 return 4;
4540 }
4541
4542 static int
4543 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4544 {
4545 /* pseudoDEBUG
4546 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4547 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4548 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4549 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4550 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4551 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4552
4553 if (parallel)
4554 return 0;
4555
4556 if (reg == 0 && fn == 3)
4557 OUTS (outf, "DBG A0");
4558
4559 else if (reg == 1 && fn == 3)
4560 OUTS (outf, "DBG A1");
4561
4562 else if (reg == 3 && fn == 3)
4563 OUTS (outf, "ABORT");
4564
4565 else if (reg == 4 && fn == 3)
4566 OUTS (outf, "HLT");
4567
4568 else if (reg == 5 && fn == 3)
4569 OUTS (outf, "DBGHALT");
4570
4571 else if (reg == 6 && fn == 3)
4572 {
4573 OUTS (outf, "DBGCMPLX (");
4574 OUTS (outf, dregs (grp));
4575 OUTS (outf, ")");
4576 }
4577 else if (reg == 7 && fn == 3)
4578 OUTS (outf, "DBG");
4579
4580 else if (grp == 0 && fn == 2)
4581 {
4582 OUTS (outf, "OUTC ");
4583 OUTS (outf, dregs (reg));
4584 }
4585 else if (fn == 0)
4586 {
4587 OUTS (outf, "DBG ");
4588 OUTS (outf, allregs (reg, grp));
4589 }
4590 else if (fn == 1)
4591 {
4592 OUTS (outf, "PRNT ");
4593 OUTS (outf, allregs (reg, grp));
4594 }
4595 else
4596 return 0;
4597
4598 return 2;
4599 }
4600
4601 static int
4602 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4603 {
4604 /* psedoOChar
4605 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4606 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4607 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4608 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4609
4610 if (parallel)
4611 return 0;
4612
4613 OUTS (outf, "OUTC ");
4614 OUTS (outf, uimm8 (ch));
4615
4616 return 2;
4617 }
4618
4619 static int
4620 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4621 {
4622 /* pseudodbg_assert
4623 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4624 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4625 |.expected......................................................|
4626 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4627 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4628 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4629 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4630 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4631
4632 if (parallel)
4633 return 0;
4634
4635 if (dbgop == 0)
4636 {
4637 OUTS (outf, "DBGA (");
4638 OUTS (outf, regs_lo (regtest, grp));
4639 OUTS (outf, ", ");
4640 OUTS (outf, uimm16 (expected));
4641 OUTS (outf, ")");
4642 }
4643 else if (dbgop == 1)
4644 {
4645 OUTS (outf, "DBGA (");
4646 OUTS (outf, regs_hi (regtest, grp));
4647 OUTS (outf, ", ");
4648 OUTS (outf, uimm16 (expected));
4649 OUTS (outf, ")");
4650 }
4651 else if (dbgop == 2)
4652 {
4653 OUTS (outf, "DBGAL (");
4654 OUTS (outf, allregs (regtest, grp));
4655 OUTS (outf, ", ");
4656 OUTS (outf, uimm16 (expected));
4657 OUTS (outf, ")");
4658 }
4659 else if (dbgop == 3)
4660 {
4661 OUTS (outf, "DBGAH (");
4662 OUTS (outf, allregs (regtest, grp));
4663 OUTS (outf, ", ");
4664 OUTS (outf, uimm16 (expected));
4665 OUTS (outf, ")");
4666 }
4667 else
4668 return 0;
4669 return 4;
4670 }
4671
4672 static int
4673 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4674 {
4675 bfd_byte buf[4];
4676 TIword iw0;
4677 TIword iw1;
4678 int status;
4679 int rv = 0;
4680
4681 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4682 /* FIXME */
4683 (void) status;
4684 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4685 /* FIXME */
4686 (void) status;
4687
4688 iw0 = bfd_getl16 (buf);
4689 iw1 = bfd_getl16 (buf + 2);
4690
4691 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4692 {
4693 if (parallel)
4694 {
4695 OUTS (outf, "ILLEGAL");
4696 return 0;
4697 }
4698 OUTS (outf, "MNOP");
4699 return 4;
4700 }
4701 else if ((iw0 & 0xff00) == 0x0000)
4702 rv = decode_ProgCtrl_0 (iw0, outf);
4703 else if ((iw0 & 0xffc0) == 0x0240)
4704 rv = decode_CaCTRL_0 (iw0, outf);
4705 else if ((iw0 & 0xff80) == 0x0100)
4706 rv = decode_PushPopReg_0 (iw0, outf);
4707 else if ((iw0 & 0xfe00) == 0x0400)
4708 rv = decode_PushPopMultiple_0 (iw0, outf);
4709 else if ((iw0 & 0xfe00) == 0x0600)
4710 rv = decode_ccMV_0 (iw0, outf);
4711 else if ((iw0 & 0xf800) == 0x0800)
4712 rv = decode_CCflag_0 (iw0, outf);
4713 else if ((iw0 & 0xffe0) == 0x0200)
4714 rv = decode_CC2dreg_0 (iw0, outf);
4715 else if ((iw0 & 0xff00) == 0x0300)
4716 rv = decode_CC2stat_0 (iw0, outf);
4717 else if ((iw0 & 0xf000) == 0x1000)
4718 rv = decode_BRCC_0 (iw0, pc, outf);
4719 else if ((iw0 & 0xf000) == 0x2000)
4720 rv = decode_UJUMP_0 (iw0, pc, outf);
4721 else if ((iw0 & 0xf000) == 0x3000)
4722 rv = decode_REGMV_0 (iw0, outf);
4723 else if ((iw0 & 0xfc00) == 0x4000)
4724 rv = decode_ALU2op_0 (iw0, outf);
4725 else if ((iw0 & 0xfe00) == 0x4400)
4726 rv = decode_PTR2op_0 (iw0, outf);
4727 else if ((iw0 & 0xf800) == 0x4800)
4728 rv = decode_LOGI2op_0 (iw0, outf);
4729 else if ((iw0 & 0xf000) == 0x5000)
4730 rv = decode_COMP3op_0 (iw0, outf);
4731 else if ((iw0 & 0xf800) == 0x6000)
4732 rv = decode_COMPI2opD_0 (iw0, outf);
4733 else if ((iw0 & 0xf800) == 0x6800)
4734 rv = decode_COMPI2opP_0 (iw0, outf);
4735 else if ((iw0 & 0xf000) == 0x8000)
4736 rv = decode_LDSTpmod_0 (iw0, outf);
4737 else if ((iw0 & 0xff60) == 0x9e60)
4738 rv = decode_dagMODim_0 (iw0, outf);
4739 else if ((iw0 & 0xfff0) == 0x9f60)
4740 rv = decode_dagMODik_0 (iw0, outf);
4741 else if ((iw0 & 0xfc00) == 0x9c00)
4742 rv = decode_dspLDST_0 (iw0, outf);
4743 else if ((iw0 & 0xf000) == 0x9000)
4744 rv = decode_LDST_0 (iw0, outf);
4745 else if ((iw0 & 0xfc00) == 0xb800)
4746 rv = decode_LDSTiiFP_0 (iw0, outf);
4747 else if ((iw0 & 0xe000) == 0xA000)
4748 rv = decode_LDSTii_0 (iw0, outf);
4749 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4750 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4751 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4752 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4753 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4754 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4755 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4756 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4757 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4758 rv = decode_linkage_0 (iw0, iw1, outf);
4759 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4760 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4761 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4762 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4763 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4764 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4765 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4766 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4767 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4768 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4769 else if ((iw0 & 0xff00) == 0xf800)
4770 rv = decode_pseudoDEBUG_0 (iw0, outf);
4771 else if ((iw0 & 0xFF00) == 0xF900)
4772 rv = decode_pseudoOChar_0 (iw0, outf);
4773 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4774 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4775
4776 if (rv == 0)
4777 OUTS (outf, "ILLEGAL");
4778
4779 return rv;
4780 }
4781
4782
4783 int
4784 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4785 {
4786 bfd_byte buf[2];
4787 unsigned short iw0;
4788 int status;
4789 int count = 0;
4790
4791 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4792 /* FIXME */
4793 (void) status;
4794 iw0 = bfd_getl16 (buf);
4795
4796 count += _print_insn_bfin (pc, outf);
4797
4798 /* Proper display of multiple issue instructions. */
4799
4800 if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4801 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4802 {
4803 int legal = 1;
4804 int len;
4805
4806 parallel = 1;
4807 outf->fprintf_func (outf->stream, " || ");
4808 len = _print_insn_bfin (pc + 4, outf);
4809 outf->fprintf_func (outf->stream, " || ");
4810 if (len != 2)
4811 legal = 0;
4812 len = _print_insn_bfin (pc + 6, outf);
4813 if (len != 2)
4814 legal = 0;
4815
4816 if (legal)
4817 count = 8;
4818 else
4819 {
4820 outf->fprintf_func (outf->stream, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4821 comment = 1;
4822 count = 0;
4823 }
4824 parallel = 0;
4825 }
4826
4827 if (!comment)
4828 outf->fprintf_func (outf->stream, ";");
4829
4830 if (count == 0)
4831 return 2;
4832
4833 comment = 0;
4834
4835 return count;
4836 }
git-cvsimport of binutils cvsroot