opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_XMM_Vex (int, int);
  95 static void OP_XMM_VexW (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void CMPXCHG8B_Fixup (int, int);
 111 static void XMM_Fixup (int, int);
 112 static void CRC32_Fixup (int, int);
 113 static void FXSAVE_Fixup (int, int);
 114 static void OP_LWPCB_E (int, int);
 115 static void OP_LWP_E (int, int);
 116 static void OP_LWP_I (int, int);
 117 static void OP_Vex_2src_1 (int, int);
 118 static void OP_Vex_2src_2 (int, int);
 119
 120 static void MOVBE_Fixup (int, int);
 121
 122 struct dis_private {
 123   /* Points to first byte not fetched.  */
 124   bfd_byte *max_fetched;
 125   bfd_byte the_buffer[MAX_MNEM_SIZE];
 126   bfd_vma insn_start;
 127   int orig_sizeflag;
 128   jmp_buf bailout;
 129 };
 130
 131 enum address_mode
 132 {
 133   mode_16bit,
 134   mode_32bit,
 135   mode_64bit
 136 };
 137
 138 enum address_mode address_mode;
 139
 140 /* Flags for the prefixes for the current instruction.  See below.  */
 141 static int prefixes;
 142
 143 /* REX prefix the current instruction.  See below.  */
 144 static int rex;
 145 /* Bits of REX we've already used.  */
 146 static int rex_used;
 147 /* REX bits in original REX prefix ignored.  */
 148 static int rex_ignored;
 149 /* Mark parts used in the REX prefix.  When we are testing for
 150    empty prefix (for 8bit register REX extension), just mask it
 151    out.  Otherwise test for REX bit is excuse for existence of REX
 152    only in case value is nonzero.  */
 153 #define USED_REX(value)                                 \
 154   {                                                     \
 155     if (value)                                          \
 156       {                                                 \
 157         if ((rex & value))                              \
 158           rex_used |= (value) | REX_OPCODE;             \
 159       }                                                 \
 160     else                                                \
 161       rex_used |= REX_OPCODE;                           \
 162   }
 163
 164 /* Flags for prefixes which we somehow handled when printing the
 165    current instruction.  */
 166 static int used_prefixes;
 167
 168 /* Flags stored in PREFIXES.  */
 169 #define PREFIX_REPZ 1
 170 #define PREFIX_REPNZ 2
 171 #define PREFIX_LOCK 4
 172 #define PREFIX_CS 8
 173 #define PREFIX_SS 0x10
 174 #define PREFIX_DS 0x20
 175 #define PREFIX_ES 0x40
 176 #define PREFIX_FS 0x80
 177 #define PREFIX_GS 0x100
 178 #define PREFIX_DATA 0x200
 179 #define PREFIX_ADDR 0x400
 180 #define PREFIX_FWAIT 0x800
 181
 182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 183    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 184    on error.  */
 185 #define FETCH_DATA(info, addr) \
 186   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 187    ? 1 : fetch_data ((info), (addr)))
 188
 189 static int
 190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 191 {
 192   int status;
 193   struct dis_private *priv = (struct dis_private *) info->private_data;
 194   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 195
 196   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 197     status = (*info->read_memory_func) (start,
 198                                         priv->max_fetched,
 199                                         addr - priv->max_fetched,
 200                                         info);
 201   else
 202     status = -1;
 203   if (status != 0)
 204     {
 205       /* If we did manage to read at least one byte, then
 206          print_insn_i386 will do something sensible.  Otherwise, print
 207          an error.  We do that here because this is where we know
 208          STATUS.  */
 209       if (priv->max_fetched == priv->the_buffer)
 210         (*info->memory_error_func) (status, start, info);
 211       longjmp (priv->bailout, 1);
 212     }
 213   else
 214     priv->max_fetched = addr;
 215   return 1;
 216 }
 217
 218 #define XX { NULL, 0 }
 219 #define Bad_Opcode NULL, { { NULL, 0 } }
 220
 221 #define Eb { OP_E, b_mode }
 222 #define EbS { OP_E, b_swap_mode }
 223 #define Ev { OP_E, v_mode }
 224 #define EvS { OP_E, v_swap_mode }
 225 #define Ed { OP_E, d_mode }
 226 #define Edq { OP_E, dq_mode }
 227 #define Edqw { OP_E, dqw_mode }
 228 #define Edqb { OP_E, dqb_mode }
 229 #define Edqd { OP_E, dqd_mode }
 230 #define Eq { OP_E, q_mode }
 231 #define indirEv { OP_indirE, stack_v_mode }
 232 #define indirEp { OP_indirE, f_mode }
 233 #define stackEv { OP_E, stack_v_mode }
 234 #define Em { OP_E, m_mode }
 235 #define Ew { OP_E, w_mode }
 236 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 237 #define Ma { OP_M, a_mode }
 238 #define Mb { OP_M, b_mode }
 239 #define Md { OP_M, d_mode }
 240 #define Mo { OP_M, o_mode }
 241 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 242 #define Mq { OP_M, q_mode }
 243 #define Mx { OP_M, x_mode }
 244 #define Mxmm { OP_M, xmm_mode }
 245 #define Gb { OP_G, b_mode }
 246 #define Gv { OP_G, v_mode }
 247 #define Gd { OP_G, d_mode }
 248 #define Gdq { OP_G, dq_mode }
 249 #define Gm { OP_G, m_mode }
 250 #define Gw { OP_G, w_mode }
 251 #define Rd { OP_R, d_mode }
 252 #define Rm { OP_R, m_mode }
 253 #define Ib { OP_I, b_mode }
 254 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 255 #define Iv { OP_I, v_mode }
 256 #define Iq { OP_I, q_mode }
 257 #define Iv64 { OP_I64, v_mode }
 258 #define Iw { OP_I, w_mode }
 259 #define I1 { OP_I, const_1_mode }
 260 #define Jb { OP_J, b_mode }
 261 #define Jv { OP_J, v_mode }
 262 #define Cm { OP_C, m_mode }
 263 #define Dm { OP_D, m_mode }
 264 #define Td { OP_T, d_mode }
 265 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 266
 267 #define RMeAX { OP_REG, eAX_reg }
 268 #define RMeBX { OP_REG, eBX_reg }
 269 #define RMeCX { OP_REG, eCX_reg }
 270 #define RMeDX { OP_REG, eDX_reg }
 271 #define RMeSP { OP_REG, eSP_reg }
 272 #define RMeBP { OP_REG, eBP_reg }
 273 #define RMeSI { OP_REG, eSI_reg }
 274 #define RMeDI { OP_REG, eDI_reg }
 275 #define RMrAX { OP_REG, rAX_reg }
 276 #define RMrBX { OP_REG, rBX_reg }
 277 #define RMrCX { OP_REG, rCX_reg }
 278 #define RMrDX { OP_REG, rDX_reg }
 279 #define RMrSP { OP_REG, rSP_reg }
 280 #define RMrBP { OP_REG, rBP_reg }
 281 #define RMrSI { OP_REG, rSI_reg }
 282 #define RMrDI { OP_REG, rDI_reg }
 283 #define RMAL { OP_REG, al_reg }
 284 #define RMAL { OP_REG, al_reg }
 285 #define RMCL { OP_REG, cl_reg }
 286 #define RMDL { OP_REG, dl_reg }
 287 #define RMBL { OP_REG, bl_reg }
 288 #define RMAH { OP_REG, ah_reg }
 289 #define RMCH { OP_REG, ch_reg }
 290 #define RMDH { OP_REG, dh_reg }
 291 #define RMBH { OP_REG, bh_reg }
 292 #define RMAX { OP_REG, ax_reg }
 293 #define RMDX { OP_REG, dx_reg }
 294
 295 #define eAX { OP_IMREG, eAX_reg }
 296 #define eBX { OP_IMREG, eBX_reg }
 297 #define eCX { OP_IMREG, eCX_reg }
 298 #define eDX { OP_IMREG, eDX_reg }
 299 #define eSP { OP_IMREG, eSP_reg }
 300 #define eBP { OP_IMREG, eBP_reg }
 301 #define eSI { OP_IMREG, eSI_reg }
 302 #define eDI { OP_IMREG, eDI_reg }
 303 #define AL { OP_IMREG, al_reg }
 304 #define CL { OP_IMREG, cl_reg }
 305 #define DL { OP_IMREG, dl_reg }
 306 #define BL { OP_IMREG, bl_reg }
 307 #define AH { OP_IMREG, ah_reg }
 308 #define CH { OP_IMREG, ch_reg }
 309 #define DH { OP_IMREG, dh_reg }
 310 #define BH { OP_IMREG, bh_reg }
 311 #define AX { OP_IMREG, ax_reg }
 312 #define DX { OP_IMREG, dx_reg }
 313 #define zAX { OP_IMREG, z_mode_ax_reg }
 314 #define indirDX { OP_IMREG, indir_dx_reg }
 315
 316 #define Sw { OP_SEG, w_mode }
 317 #define Sv { OP_SEG, v_mode }
 318 #define Ap { OP_DIR, 0 }
 319 #define Ob { OP_OFF64, b_mode }
 320 #define Ov { OP_OFF64, v_mode }
 321 #define Xb { OP_DSreg, eSI_reg }
 322 #define Xv { OP_DSreg, eSI_reg }
 323 #define Xz { OP_DSreg, eSI_reg }
 324 #define Yb { OP_ESreg, eDI_reg }
 325 #define Yv { OP_ESreg, eDI_reg }
 326 #define DSBX { OP_DSreg, eBX_reg }
 327
 328 #define es { OP_REG, es_reg }
 329 #define ss { OP_REG, ss_reg }
 330 #define cs { OP_REG, cs_reg }
 331 #define ds { OP_REG, ds_reg }
 332 #define fs { OP_REG, fs_reg }
 333 #define gs { OP_REG, gs_reg }
 334
 335 #define MX { OP_MMX, 0 }
 336 #define XM { OP_XMM, 0 }
 337 #define XMScalar { OP_XMM, scalar_mode }
 338 #define XMM { OP_XMM, xmm_mode }
 339 #define EM { OP_EM, v_mode }
 340 #define EMS { OP_EM, v_swap_mode }
 341 #define EMd { OP_EM, d_mode }
 342 #define EMx { OP_EM, x_mode }
 343 #define EXw { OP_EX, w_mode }
 344 #define EXd { OP_EX, d_mode }
 345 #define EXdScalar { OP_EX, d_scalar_mode }
 346 #define EXdS { OP_EX, d_swap_mode }
 347 #define EXq { OP_EX, q_mode }
 348 #define EXqScalar { OP_EX, q_scalar_mode }
 349 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 350 #define EXqS { OP_EX, q_swap_mode }
 351 #define EXx { OP_EX, x_mode }
 352 #define EXxS { OP_EX, x_swap_mode }
 353 #define EXxmm { OP_EX, xmm_mode }
 354 #define EXxmmq { OP_EX, xmmq_mode }
 355 #define EXymmq { OP_EX, ymmq_mode }
 356 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 357 #define MS { OP_MS, v_mode }
 358 #define XS { OP_XS, v_mode }
 359 #define EMCq { OP_EMC, q_mode }
 360 #define MXC { OP_MXC, 0 }
 361 #define OPSUF { OP_3DNowSuffix, 0 }
 362 #define CMP { CMP_Fixup, 0 }
 363 #define XMM0 { XMM_Fixup, 0 }
 364 #define FXSAVE { FXSAVE_Fixup, 0 }
 365 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 366 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 367
 368 #define Vex { OP_VEX, vex_mode }
 369 #define VexScalar { OP_VEX, vex_scalar_mode }
 370 #define Vex128 { OP_VEX, vex128_mode }
 371 #define Vex256 { OP_VEX, vex256_mode }
 372 #define VexI4 { VEXI4_Fixup, 0}
 373 #define EXdVex { OP_EX_Vex, d_mode }
 374 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 375 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 376 #define EXqVex { OP_EX_Vex, q_mode }
 377 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 378 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 379 #define EXVexW { OP_EX_VexW, x_mode }
 380 #define EXdVexW { OP_EX_VexW, d_mode }
 381 #define EXqVexW { OP_EX_VexW, q_mode }
 382 #define XMVex { OP_XMM_Vex, 0 }
 383 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 384 #define XMVexW { OP_XMM_VexW, 0 }
 385 #define XMVexI4 { OP_REG_VexI4, x_mode }
 386 #define PCLMUL { PCLMUL_Fixup, 0 }
 387 #define VZERO { VZERO_Fixup, 0 }
 388 #define VCMP { VCMP_Fixup, 0 }
 389
 390 /* Used handle "rep" prefix for string instructions.  */
 391 #define Xbr { REP_Fixup, eSI_reg }
 392 #define Xvr { REP_Fixup, eSI_reg }
 393 #define Ybr { REP_Fixup, eDI_reg }
 394 #define Yvr { REP_Fixup, eDI_reg }
 395 #define Yzr { REP_Fixup, eDI_reg }
 396 #define indirDXr { REP_Fixup, indir_dx_reg }
 397 #define ALr { REP_Fixup, al_reg }
 398 #define eAXr { REP_Fixup, eAX_reg }
 399
 400 #define cond_jump_flag { NULL, cond_jump_mode }
 401 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 402
 403 /* bits in sizeflag */
 404 #define SUFFIX_ALWAYS 4
 405 #define AFLAG 2
 406 #define DFLAG 1
 407
 408 enum
 409 {
 410   /* byte operand */
 411   b_mode = 1,
 412   /* byte operand with operand swapped */
 413   b_swap_mode,
 414   /* operand size depends on prefixes */
 415   v_mode,
 416   /* operand size depends on prefixes with operand swapped */
 417   v_swap_mode,
 418   /* word operand */
 419   w_mode,
 420   /* double word operand  */
 421   d_mode,
 422   /* double word operand with operand swapped */
 423   d_swap_mode,
 424   /* quad word operand */
 425   q_mode,
 426   /* quad word operand with operand swapped */
 427   q_swap_mode,
 428   /* ten-byte operand */
 429   t_mode,
 430   /* 16-byte XMM or 32-byte YMM operand */
 431   x_mode,
 432   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 433   x_swap_mode,
 434   /* 16-byte XMM operand */
 435   xmm_mode,
 436   /* 16-byte XMM or quad word operand */
 437   xmmq_mode,
 438   /* 32-byte YMM or quad word operand */
 439   ymmq_mode,
 440   /* d_mode in 32bit, q_mode in 64bit mode.  */
 441   m_mode,
 442   /* pair of v_mode operands */
 443   a_mode,
 444   cond_jump_mode,
 445   loop_jcxz_mode,
 446   /* operand size depends on REX prefixes.  */
 447   dq_mode,
 448   /* registers like dq_mode, memory like w_mode.  */
 449   dqw_mode,
 450   /* 4- or 6-byte pointer operand */
 451   f_mode,
 452   const_1_mode,
 453   /* v_mode for stack-related opcodes.  */
 454   stack_v_mode,
 455   /* non-quad operand size depends on prefixes */
 456   z_mode,
 457   /* 16-byte operand */
 458   o_mode,
 459   /* registers like dq_mode, memory like b_mode.  */
 460   dqb_mode,
 461   /* registers like dq_mode, memory like d_mode.  */
 462   dqd_mode,
 463   /* normal vex mode */
 464   vex_mode,
 465   /* 128bit vex mode */
 466   vex128_mode,
 467   /* 256bit vex mode */
 468   vex256_mode,
 469   /* operand size depends on the VEX.W bit.  */
 470   vex_w_dq_mode,
 471
 472   /* scalar, ignore vector length.  */
 473   scalar_mode,
 474   /* like d_mode, ignore vector length.  */
 475   d_scalar_mode,
 476   /* like d_swap_mode, ignore vector length.  */
 477   d_scalar_swap_mode,
 478   /* like q_mode, ignore vector length.  */
 479   q_scalar_mode,
 480   /* like q_swap_mode, ignore vector length.  */
 481   q_scalar_swap_mode,
 482   /* like vex_mode, ignore vector length.  */
 483   vex_scalar_mode,
 484
 485   es_reg,
 486   cs_reg,
 487   ss_reg,
 488   ds_reg,
 489   fs_reg,
 490   gs_reg,
 491
 492   eAX_reg,
 493   eCX_reg,
 494   eDX_reg,
 495   eBX_reg,
 496   eSP_reg,
 497   eBP_reg,
 498   eSI_reg,
 499   eDI_reg,
 500
 501   al_reg,
 502   cl_reg,
 503   dl_reg,
 504   bl_reg,
 505   ah_reg,
 506   ch_reg,
 507   dh_reg,
 508   bh_reg,
 509
 510   ax_reg,
 511   cx_reg,
 512   dx_reg,
 513   bx_reg,
 514   sp_reg,
 515   bp_reg,
 516   si_reg,
 517   di_reg,
 518
 519   rAX_reg,
 520   rCX_reg,
 521   rDX_reg,
 522   rBX_reg,
 523   rSP_reg,
 524   rBP_reg,
 525   rSI_reg,
 526   rDI_reg,
 527
 528   z_mode_ax_reg,
 529   indir_dx_reg
 530 };
 531
 532 enum
 533 {
 534   FLOATCODE = 1,
 535   USE_REG_TABLE,
 536   USE_MOD_TABLE,
 537   USE_RM_TABLE,
 538   USE_PREFIX_TABLE,
 539   USE_X86_64_TABLE,
 540   USE_3BYTE_TABLE,
 541   USE_XOP_8F_TABLE,
 542   USE_VEX_C4_TABLE,
 543   USE_VEX_C5_TABLE,
 544   USE_VEX_LEN_TABLE,
 545   USE_VEX_W_TABLE
 546 };
 547
 548 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 549
 550 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 551 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 552 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 553 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 554 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 555 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 556 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 557 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 558 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 559 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 560 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 561 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 562
 563 enum
 564 {
 565   REG_80 = 0,
 566   REG_81,
 567   REG_82,
 568   REG_8F,
 569   REG_C0,
 570   REG_C1,
 571   REG_C6,
 572   REG_C7,
 573   REG_D0,
 574   REG_D1,
 575   REG_D2,
 576   REG_D3,
 577   REG_F6,
 578   REG_F7,
 579   REG_FE,
 580   REG_FF,
 581   REG_0F00,
 582   REG_0F01,
 583   REG_0F0D,
 584   REG_0F18,
 585   REG_0F71,
 586   REG_0F72,
 587   REG_0F73,
 588   REG_0FA6,
 589   REG_0FA7,
 590   REG_0FAE,
 591   REG_0FBA,
 592   REG_0FC7,
 593   REG_VEX_71,
 594   REG_VEX_72,
 595   REG_VEX_73,
 596   REG_VEX_AE,
 597   REG_XOP_LWPCB,
 598   REG_XOP_LWP
 599 };
 600
 601 enum
 602 {
 603   MOD_8D = 0,
 604   MOD_0F01_REG_0,
 605   MOD_0F01_REG_1,
 606   MOD_0F01_REG_2,
 607   MOD_0F01_REG_3,
 608   MOD_0F01_REG_7,
 609   MOD_0F12_PREFIX_0,
 610   MOD_0F13,
 611   MOD_0F16_PREFIX_0,
 612   MOD_0F17,
 613   MOD_0F18_REG_0,
 614   MOD_0F18_REG_1,
 615   MOD_0F18_REG_2,
 616   MOD_0F18_REG_3,
 617   MOD_0F20,
 618   MOD_0F21,
 619   MOD_0F22,
 620   MOD_0F23,
 621   MOD_0F24,
 622   MOD_0F26,
 623   MOD_0F2B_PREFIX_0,
 624   MOD_0F2B_PREFIX_1,
 625   MOD_0F2B_PREFIX_2,
 626   MOD_0F2B_PREFIX_3,
 627   MOD_0F51,
 628   MOD_0F71_REG_2,
 629   MOD_0F71_REG_4,
 630   MOD_0F71_REG_6,
 631   MOD_0F72_REG_2,
 632   MOD_0F72_REG_4,
 633   MOD_0F72_REG_6,
 634   MOD_0F73_REG_2,
 635   MOD_0F73_REG_3,
 636   MOD_0F73_REG_6,
 637   MOD_0F73_REG_7,
 638   MOD_0FAE_REG_0,
 639   MOD_0FAE_REG_1,
 640   MOD_0FAE_REG_2,
 641   MOD_0FAE_REG_3,
 642   MOD_0FAE_REG_4,
 643   MOD_0FAE_REG_5,
 644   MOD_0FAE_REG_6,
 645   MOD_0FAE_REG_7,
 646   MOD_0FB2,
 647   MOD_0FB4,
 648   MOD_0FB5,
 649   MOD_0FC7_REG_6,
 650   MOD_0FC7_REG_7,
 651   MOD_0FD7,
 652   MOD_0FE7_PREFIX_2,
 653   MOD_0FF0_PREFIX_3,
 654   MOD_0F382A_PREFIX_2,
 655   MOD_62_32BIT,
 656   MOD_C4_32BIT,
 657   MOD_C5_32BIT,
 658   MOD_VEX_12_PREFIX_0,
 659   MOD_VEX_13,
 660   MOD_VEX_16_PREFIX_0,
 661   MOD_VEX_17,
 662   MOD_VEX_2B,
 663   MOD_VEX_50,
 664   MOD_VEX_71_REG_2,
 665   MOD_VEX_71_REG_4,
 666   MOD_VEX_71_REG_6,
 667   MOD_VEX_72_REG_2,
 668   MOD_VEX_72_REG_4,
 669   MOD_VEX_72_REG_6,
 670   MOD_VEX_73_REG_2,
 671   MOD_VEX_73_REG_3,
 672   MOD_VEX_73_REG_6,
 673   MOD_VEX_73_REG_7,
 674   MOD_VEX_AE_REG_2,
 675   MOD_VEX_AE_REG_3,
 676   MOD_VEX_D7_PREFIX_2,
 677   MOD_VEX_E7_PREFIX_2,
 678   MOD_VEX_F0_PREFIX_3,
 679   MOD_VEX_3818_PREFIX_2,
 680   MOD_VEX_3819_PREFIX_2,
 681   MOD_VEX_381A_PREFIX_2,
 682   MOD_VEX_382A_PREFIX_2,
 683   MOD_VEX_382C_PREFIX_2,
 684   MOD_VEX_382D_PREFIX_2,
 685   MOD_VEX_382E_PREFIX_2,
 686   MOD_VEX_382F_PREFIX_2
 687 };
 688
 689 enum
 690 {
 691   RM_0F01_REG_0 = 0,
 692   RM_0F01_REG_1,
 693   RM_0F01_REG_2,
 694   RM_0F01_REG_3,
 695   RM_0F01_REG_7,
 696   RM_0FAE_REG_5,
 697   RM_0FAE_REG_6,
 698   RM_0FAE_REG_7
 699 };
 700
 701 enum
 702 {
 703   PREFIX_90 = 0,
 704   PREFIX_0F10,
 705   PREFIX_0F11,
 706   PREFIX_0F12,
 707   PREFIX_0F16,
 708   PREFIX_0F2A,
 709   PREFIX_0F2B,
 710   PREFIX_0F2C,
 711   PREFIX_0F2D,
 712   PREFIX_0F2E,
 713   PREFIX_0F2F,
 714   PREFIX_0F51,
 715   PREFIX_0F52,
 716   PREFIX_0F53,
 717   PREFIX_0F58,
 718   PREFIX_0F59,
 719   PREFIX_0F5A,
 720   PREFIX_0F5B,
 721   PREFIX_0F5C,
 722   PREFIX_0F5D,
 723   PREFIX_0F5E,
 724   PREFIX_0F5F,
 725   PREFIX_0F60,
 726   PREFIX_0F61,
 727   PREFIX_0F62,
 728   PREFIX_0F6C,
 729   PREFIX_0F6D,
 730   PREFIX_0F6F,
 731   PREFIX_0F70,
 732   PREFIX_0F73_REG_3,
 733   PREFIX_0F73_REG_7,
 734   PREFIX_0F78,
 735   PREFIX_0F79,
 736   PREFIX_0F7C,
 737   PREFIX_0F7D,
 738   PREFIX_0F7E,
 739   PREFIX_0F7F,
 740   PREFIX_0FB8,
 741   PREFIX_0FBD,
 742   PREFIX_0FC2,
 743   PREFIX_0FC3,
 744   PREFIX_0FC7_REG_6,
 745   PREFIX_0FD0,
 746   PREFIX_0FD6,
 747   PREFIX_0FE6,
 748   PREFIX_0FE7,
 749   PREFIX_0FF0,
 750   PREFIX_0FF7,
 751   PREFIX_0F3810,
 752   PREFIX_0F3814,
 753   PREFIX_0F3815,
 754   PREFIX_0F3817,
 755   PREFIX_0F3820,
 756   PREFIX_0F3821,
 757   PREFIX_0F3822,
 758   PREFIX_0F3823,
 759   PREFIX_0F3824,
 760   PREFIX_0F3825,
 761   PREFIX_0F3828,
 762   PREFIX_0F3829,
 763   PREFIX_0F382A,
 764   PREFIX_0F382B,
 765   PREFIX_0F3830,
 766   PREFIX_0F3831,
 767   PREFIX_0F3832,
 768   PREFIX_0F3833,
 769   PREFIX_0F3834,
 770   PREFIX_0F3835,
 771   PREFIX_0F3837,
 772   PREFIX_0F3838,
 773   PREFIX_0F3839,
 774   PREFIX_0F383A,
 775   PREFIX_0F383B,
 776   PREFIX_0F383C,
 777   PREFIX_0F383D,
 778   PREFIX_0F383E,
 779   PREFIX_0F383F,
 780   PREFIX_0F3840,
 781   PREFIX_0F3841,
 782   PREFIX_0F3880,
 783   PREFIX_0F3881,
 784   PREFIX_0F38DB,
 785   PREFIX_0F38DC,
 786   PREFIX_0F38DD,
 787   PREFIX_0F38DE,
 788   PREFIX_0F38DF,
 789   PREFIX_0F38F0,
 790   PREFIX_0F38F1,
 791   PREFIX_0F3A08,
 792   PREFIX_0F3A09,
 793   PREFIX_0F3A0A,
 794   PREFIX_0F3A0B,
 795   PREFIX_0F3A0C,
 796   PREFIX_0F3A0D,
 797   PREFIX_0F3A0E,
 798   PREFIX_0F3A14,
 799   PREFIX_0F3A15,
 800   PREFIX_0F3A16,
 801   PREFIX_0F3A17,
 802   PREFIX_0F3A20,
 803   PREFIX_0F3A21,
 804   PREFIX_0F3A22,
 805   PREFIX_0F3A40,
 806   PREFIX_0F3A41,
 807   PREFIX_0F3A42,
 808   PREFIX_0F3A44,
 809   PREFIX_0F3A60,
 810   PREFIX_0F3A61,
 811   PREFIX_0F3A62,
 812   PREFIX_0F3A63,
 813   PREFIX_0F3ADF,
 814   PREFIX_VEX_10,
 815   PREFIX_VEX_11,
 816   PREFIX_VEX_12,
 817   PREFIX_VEX_16,
 818   PREFIX_VEX_2A,
 819   PREFIX_VEX_2C,
 820   PREFIX_VEX_2D,
 821   PREFIX_VEX_2E,
 822   PREFIX_VEX_2F,
 823   PREFIX_VEX_51,
 824   PREFIX_VEX_52,
 825   PREFIX_VEX_53,
 826   PREFIX_VEX_58,
 827   PREFIX_VEX_59,
 828   PREFIX_VEX_5A,
 829   PREFIX_VEX_5B,
 830   PREFIX_VEX_5C,
 831   PREFIX_VEX_5D,
 832   PREFIX_VEX_5E,
 833   PREFIX_VEX_5F,
 834   PREFIX_VEX_60,
 835   PREFIX_VEX_61,
 836   PREFIX_VEX_62,
 837   PREFIX_VEX_63,
 838   PREFIX_VEX_64,
 839   PREFIX_VEX_65,
 840   PREFIX_VEX_66,
 841   PREFIX_VEX_67,
 842   PREFIX_VEX_68,
 843   PREFIX_VEX_69,
 844   PREFIX_VEX_6A,
 845   PREFIX_VEX_6B,
 846   PREFIX_VEX_6C,
 847   PREFIX_VEX_6D,
 848   PREFIX_VEX_6E,
 849   PREFIX_VEX_6F,
 850   PREFIX_VEX_70,
 851   PREFIX_VEX_71_REG_2,
 852   PREFIX_VEX_71_REG_4,
 853   PREFIX_VEX_71_REG_6,
 854   PREFIX_VEX_72_REG_2,
 855   PREFIX_VEX_72_REG_4,
 856   PREFIX_VEX_72_REG_6,
 857   PREFIX_VEX_73_REG_2,
 858   PREFIX_VEX_73_REG_3,
 859   PREFIX_VEX_73_REG_6,
 860   PREFIX_VEX_73_REG_7,
 861   PREFIX_VEX_74,
 862   PREFIX_VEX_75,
 863   PREFIX_VEX_76,
 864   PREFIX_VEX_77,
 865   PREFIX_VEX_7C,
 866   PREFIX_VEX_7D,
 867   PREFIX_VEX_7E,
 868   PREFIX_VEX_7F,
 869   PREFIX_VEX_C2,
 870   PREFIX_VEX_C4,
 871   PREFIX_VEX_C5,
 872   PREFIX_VEX_D0,
 873   PREFIX_VEX_D1,
 874   PREFIX_VEX_D2,
 875   PREFIX_VEX_D3,
 876   PREFIX_VEX_D4,
 877   PREFIX_VEX_D5,
 878   PREFIX_VEX_D6,
 879   PREFIX_VEX_D7,
 880   PREFIX_VEX_D8,
 881   PREFIX_VEX_D9,
 882   PREFIX_VEX_DA,
 883   PREFIX_VEX_DB,
 884   PREFIX_VEX_DC,
 885   PREFIX_VEX_DD,
 886   PREFIX_VEX_DE,
 887   PREFIX_VEX_DF,
 888   PREFIX_VEX_E0,
 889   PREFIX_VEX_E1,
 890   PREFIX_VEX_E2,
 891   PREFIX_VEX_E3,
 892   PREFIX_VEX_E4,
 893   PREFIX_VEX_E5,
 894   PREFIX_VEX_E6,
 895   PREFIX_VEX_E7,
 896   PREFIX_VEX_E8,
 897   PREFIX_VEX_E9,
 898   PREFIX_VEX_EA,
 899   PREFIX_VEX_EB,
 900   PREFIX_VEX_EC,
 901   PREFIX_VEX_ED,
 902   PREFIX_VEX_EE,
 903   PREFIX_VEX_EF,
 904   PREFIX_VEX_F0,
 905   PREFIX_VEX_F1,
 906   PREFIX_VEX_F2,
 907   PREFIX_VEX_F3,
 908   PREFIX_VEX_F4,
 909   PREFIX_VEX_F5,
 910   PREFIX_VEX_F6,
 911   PREFIX_VEX_F7,
 912   PREFIX_VEX_F8,
 913   PREFIX_VEX_F9,
 914   PREFIX_VEX_FA,
 915   PREFIX_VEX_FB,
 916   PREFIX_VEX_FC,
 917   PREFIX_VEX_FD,
 918   PREFIX_VEX_FE,
 919   PREFIX_VEX_3800,
 920   PREFIX_VEX_3801,
 921   PREFIX_VEX_3802,
 922   PREFIX_VEX_3803,
 923   PREFIX_VEX_3804,
 924   PREFIX_VEX_3805,
 925   PREFIX_VEX_3806,
 926   PREFIX_VEX_3807,
 927   PREFIX_VEX_3808,
 928   PREFIX_VEX_3809,
 929   PREFIX_VEX_380A,
 930   PREFIX_VEX_380B,
 931   PREFIX_VEX_380C,
 932   PREFIX_VEX_380D,
 933   PREFIX_VEX_380E,
 934   PREFIX_VEX_380F,
 935   PREFIX_VEX_3817,
 936   PREFIX_VEX_3818,
 937   PREFIX_VEX_3819,
 938   PREFIX_VEX_381A,
 939   PREFIX_VEX_381C,
 940   PREFIX_VEX_381D,
 941   PREFIX_VEX_381E,
 942   PREFIX_VEX_3820,
 943   PREFIX_VEX_3821,
 944   PREFIX_VEX_3822,
 945   PREFIX_VEX_3823,
 946   PREFIX_VEX_3824,
 947   PREFIX_VEX_3825,
 948   PREFIX_VEX_3828,
 949   PREFIX_VEX_3829,
 950   PREFIX_VEX_382A,
 951   PREFIX_VEX_382B,
 952   PREFIX_VEX_382C,
 953   PREFIX_VEX_382D,
 954   PREFIX_VEX_382E,
 955   PREFIX_VEX_382F,
 956   PREFIX_VEX_3830,
 957   PREFIX_VEX_3831,
 958   PREFIX_VEX_3832,
 959   PREFIX_VEX_3833,
 960   PREFIX_VEX_3834,
 961   PREFIX_VEX_3835,
 962   PREFIX_VEX_3837,
 963   PREFIX_VEX_3838,
 964   PREFIX_VEX_3839,
 965   PREFIX_VEX_383A,
 966   PREFIX_VEX_383B,
 967   PREFIX_VEX_383C,
 968   PREFIX_VEX_383D,
 969   PREFIX_VEX_383E,
 970   PREFIX_VEX_383F,
 971   PREFIX_VEX_3840,
 972   PREFIX_VEX_3841,
 973   PREFIX_VEX_3896,
 974   PREFIX_VEX_3897,
 975   PREFIX_VEX_3898,
 976   PREFIX_VEX_3899,
 977   PREFIX_VEX_389A,
 978   PREFIX_VEX_389B,
 979   PREFIX_VEX_389C,
 980   PREFIX_VEX_389D,
 981   PREFIX_VEX_389E,
 982   PREFIX_VEX_389F,
 983   PREFIX_VEX_38A6,
 984   PREFIX_VEX_38A7,
 985   PREFIX_VEX_38A8,
 986   PREFIX_VEX_38A9,
 987   PREFIX_VEX_38AA,
 988   PREFIX_VEX_38AB,
 989   PREFIX_VEX_38AC,
 990   PREFIX_VEX_38AD,
 991   PREFIX_VEX_38AE,
 992   PREFIX_VEX_38AF,
 993   PREFIX_VEX_38B6,
 994   PREFIX_VEX_38B7,
 995   PREFIX_VEX_38B8,
 996   PREFIX_VEX_38B9,
 997   PREFIX_VEX_38BA,
 998   PREFIX_VEX_38BB,
 999   PREFIX_VEX_38BC,
1000   PREFIX_VEX_38BD,
1001   PREFIX_VEX_38BE,
1002   PREFIX_VEX_38BF,
1003   PREFIX_VEX_38DB,
1004   PREFIX_VEX_38DC,
1005   PREFIX_VEX_38DD,
1006   PREFIX_VEX_38DE,
1007   PREFIX_VEX_38DF,
1008   PREFIX_VEX_3A04,
1009   PREFIX_VEX_3A05,
1010   PREFIX_VEX_3A06,
1011   PREFIX_VEX_3A08,
1012   PREFIX_VEX_3A09,
1013   PREFIX_VEX_3A0A,
1014   PREFIX_VEX_3A0B,
1015   PREFIX_VEX_3A0C,
1016   PREFIX_VEX_3A0D,
1017   PREFIX_VEX_3A0E,
1018   PREFIX_VEX_3A0F,
1019   PREFIX_VEX_3A14,
1020   PREFIX_VEX_3A15,
1021   PREFIX_VEX_3A16,
1022   PREFIX_VEX_3A17,
1023   PREFIX_VEX_3A18,
1024   PREFIX_VEX_3A19,
1025   PREFIX_VEX_3A20,
1026   PREFIX_VEX_3A21,
1027   PREFIX_VEX_3A22,
1028   PREFIX_VEX_3A40,
1029   PREFIX_VEX_3A41,
1030   PREFIX_VEX_3A42,
1031   PREFIX_VEX_3A44,
1032   PREFIX_VEX_3A4A,
1033   PREFIX_VEX_3A4B,
1034   PREFIX_VEX_3A4C,
1035   PREFIX_VEX_3A5C,
1036   PREFIX_VEX_3A5D,
1037   PREFIX_VEX_3A5E,
1038   PREFIX_VEX_3A5F,
1039   PREFIX_VEX_3A60,
1040   PREFIX_VEX_3A61,
1041   PREFIX_VEX_3A62,
1042   PREFIX_VEX_3A63,
1043   PREFIX_VEX_3A68,
1044   PREFIX_VEX_3A69,
1045   PREFIX_VEX_3A6A,
1046   PREFIX_VEX_3A6B,
1047   PREFIX_VEX_3A6C,
1048   PREFIX_VEX_3A6D,
1049   PREFIX_VEX_3A6E,
1050   PREFIX_VEX_3A6F,
1051   PREFIX_VEX_3A78,
1052   PREFIX_VEX_3A79,
1053   PREFIX_VEX_3A7A,
1054   PREFIX_VEX_3A7B,
1055   PREFIX_VEX_3A7C,
1056   PREFIX_VEX_3A7D,
1057   PREFIX_VEX_3A7E,
1058   PREFIX_VEX_3A7F,
1059   PREFIX_VEX_3ADF
1060 };
1061
1062 enum
1063 {
1064   X86_64_06 = 0,
1065   X86_64_07,
1066   X86_64_0D,
1067   X86_64_16,
1068   X86_64_17,
1069   X86_64_1E,
1070   X86_64_1F,
1071   X86_64_27,
1072   X86_64_2F,
1073   X86_64_37,
1074   X86_64_3F,
1075   X86_64_60,
1076   X86_64_61,
1077   X86_64_62,
1078   X86_64_63,
1079   X86_64_6D,
1080   X86_64_6F,
1081   X86_64_9A,
1082   X86_64_C4,
1083   X86_64_C5,
1084   X86_64_CE,
1085   X86_64_D4,
1086   X86_64_D5,
1087   X86_64_EA,
1088   X86_64_0F01_REG_0,
1089   X86_64_0F01_REG_1,
1090   X86_64_0F01_REG_2,
1091   X86_64_0F01_REG_3
1092 };
1093
1094 enum
1095 {
1096   THREE_BYTE_0F38 = 0,
1097   THREE_BYTE_0F3A,
1098   THREE_BYTE_0F7A
1099 };
1100
1101 enum
1102 {
1103   XOP_08 = 0,
1104   XOP_09,
1105   XOP_0A
1106 };
1107
1108 enum
1109 {
1110   VEX_0F = 0,
1111   VEX_0F38,
1112   VEX_0F3A
1113 };
1114
1115 enum
1116 {
1117   VEX_LEN_10_P_1 = 0,
1118   VEX_LEN_10_P_3,
1119   VEX_LEN_11_P_1,
1120   VEX_LEN_11_P_3,
1121   VEX_LEN_12_P_0_M_0,
1122   VEX_LEN_12_P_0_M_1,
1123   VEX_LEN_12_P_2,
1124   VEX_LEN_13_M_0,
1125   VEX_LEN_16_P_0_M_0,
1126   VEX_LEN_16_P_0_M_1,
1127   VEX_LEN_16_P_2,
1128   VEX_LEN_17_M_0,
1129   VEX_LEN_2A_P_1,
1130   VEX_LEN_2A_P_3,
1131   VEX_LEN_2C_P_1,
1132   VEX_LEN_2C_P_3,
1133   VEX_LEN_2D_P_1,
1134   VEX_LEN_2D_P_3,
1135   VEX_LEN_2E_P_0,
1136   VEX_LEN_2E_P_2,
1137   VEX_LEN_2F_P_0,
1138   VEX_LEN_2F_P_2,
1139   VEX_LEN_51_P_1,
1140   VEX_LEN_51_P_3,
1141   VEX_LEN_52_P_1,
1142   VEX_LEN_53_P_1,
1143   VEX_LEN_58_P_1,
1144   VEX_LEN_58_P_3,
1145   VEX_LEN_59_P_1,
1146   VEX_LEN_59_P_3,
1147   VEX_LEN_5A_P_1,
1148   VEX_LEN_5A_P_3,
1149   VEX_LEN_5C_P_1,
1150   VEX_LEN_5C_P_3,
1151   VEX_LEN_5D_P_1,
1152   VEX_LEN_5D_P_3,
1153   VEX_LEN_5E_P_1,
1154   VEX_LEN_5E_P_3,
1155   VEX_LEN_5F_P_1,
1156   VEX_LEN_5F_P_3,
1157   VEX_LEN_60_P_2,
1158   VEX_LEN_61_P_2,
1159   VEX_LEN_62_P_2,
1160   VEX_LEN_63_P_2,
1161   VEX_LEN_64_P_2,
1162   VEX_LEN_65_P_2,
1163   VEX_LEN_66_P_2,
1164   VEX_LEN_67_P_2,
1165   VEX_LEN_68_P_2,
1166   VEX_LEN_69_P_2,
1167   VEX_LEN_6A_P_2,
1168   VEX_LEN_6B_P_2,
1169   VEX_LEN_6C_P_2,
1170   VEX_LEN_6D_P_2,
1171   VEX_LEN_6E_P_2,
1172   VEX_LEN_70_P_1,
1173   VEX_LEN_70_P_2,
1174   VEX_LEN_70_P_3,
1175   VEX_LEN_71_R_2_P_2,
1176   VEX_LEN_71_R_4_P_2,
1177   VEX_LEN_71_R_6_P_2,
1178   VEX_LEN_72_R_2_P_2,
1179   VEX_LEN_72_R_4_P_2,
1180   VEX_LEN_72_R_6_P_2,
1181   VEX_LEN_73_R_2_P_2,
1182   VEX_LEN_73_R_3_P_2,
1183   VEX_LEN_73_R_6_P_2,
1184   VEX_LEN_73_R_7_P_2,
1185   VEX_LEN_74_P_2,
1186   VEX_LEN_75_P_2,
1187   VEX_LEN_76_P_2,
1188   VEX_LEN_7E_P_1,
1189   VEX_LEN_7E_P_2,
1190   VEX_LEN_AE_R_2_M_0,
1191   VEX_LEN_AE_R_3_M_0,
1192   VEX_LEN_C2_P_1,
1193   VEX_LEN_C2_P_3,
1194   VEX_LEN_C4_P_2,
1195   VEX_LEN_C5_P_2,
1196   VEX_LEN_D1_P_2,
1197   VEX_LEN_D2_P_2,
1198   VEX_LEN_D3_P_2,
1199   VEX_LEN_D4_P_2,
1200   VEX_LEN_D5_P_2,
1201   VEX_LEN_D6_P_2,
1202   VEX_LEN_D7_P_2_M_1,
1203   VEX_LEN_D8_P_2,
1204   VEX_LEN_D9_P_2,
1205   VEX_LEN_DA_P_2,
1206   VEX_LEN_DB_P_2,
1207   VEX_LEN_DC_P_2,
1208   VEX_LEN_DD_P_2,
1209   VEX_LEN_DE_P_2,
1210   VEX_LEN_DF_P_2,
1211   VEX_LEN_E0_P_2,
1212   VEX_LEN_E1_P_2,
1213   VEX_LEN_E2_P_2,
1214   VEX_LEN_E3_P_2,
1215   VEX_LEN_E4_P_2,
1216   VEX_LEN_E5_P_2,
1217   VEX_LEN_E8_P_2,
1218   VEX_LEN_E9_P_2,
1219   VEX_LEN_EA_P_2,
1220   VEX_LEN_EB_P_2,
1221   VEX_LEN_EC_P_2,
1222   VEX_LEN_ED_P_2,
1223   VEX_LEN_EE_P_2,
1224   VEX_LEN_EF_P_2,
1225   VEX_LEN_F1_P_2,
1226   VEX_LEN_F2_P_2,
1227   VEX_LEN_F3_P_2,
1228   VEX_LEN_F4_P_2,
1229   VEX_LEN_F5_P_2,
1230   VEX_LEN_F6_P_2,
1231   VEX_LEN_F7_P_2,
1232   VEX_LEN_F8_P_2,
1233   VEX_LEN_F9_P_2,
1234   VEX_LEN_FA_P_2,
1235   VEX_LEN_FB_P_2,
1236   VEX_LEN_FC_P_2,
1237   VEX_LEN_FD_P_2,
1238   VEX_LEN_FE_P_2,
1239   VEX_LEN_3800_P_2,
1240   VEX_LEN_3801_P_2,
1241   VEX_LEN_3802_P_2,
1242   VEX_LEN_3803_P_2,
1243   VEX_LEN_3804_P_2,
1244   VEX_LEN_3805_P_2,
1245   VEX_LEN_3806_P_2,
1246   VEX_LEN_3807_P_2,
1247   VEX_LEN_3808_P_2,
1248   VEX_LEN_3809_P_2,
1249   VEX_LEN_380A_P_2,
1250   VEX_LEN_380B_P_2,
1251   VEX_LEN_3819_P_2_M_0,
1252   VEX_LEN_381A_P_2_M_0,
1253   VEX_LEN_381C_P_2,
1254   VEX_LEN_381D_P_2,
1255   VEX_LEN_381E_P_2,
1256   VEX_LEN_3820_P_2,
1257   VEX_LEN_3821_P_2,
1258   VEX_LEN_3822_P_2,
1259   VEX_LEN_3823_P_2,
1260   VEX_LEN_3824_P_2,
1261   VEX_LEN_3825_P_2,
1262   VEX_LEN_3828_P_2,
1263   VEX_LEN_3829_P_2,
1264   VEX_LEN_382A_P_2_M_0,
1265   VEX_LEN_382B_P_2,
1266   VEX_LEN_3830_P_2,
1267   VEX_LEN_3831_P_2,
1268   VEX_LEN_3832_P_2,
1269   VEX_LEN_3833_P_2,
1270   VEX_LEN_3834_P_2,
1271   VEX_LEN_3835_P_2,
1272   VEX_LEN_3837_P_2,
1273   VEX_LEN_3838_P_2,
1274   VEX_LEN_3839_P_2,
1275   VEX_LEN_383A_P_2,
1276   VEX_LEN_383B_P_2,
1277   VEX_LEN_383C_P_2,
1278   VEX_LEN_383D_P_2,
1279   VEX_LEN_383E_P_2,
1280   VEX_LEN_383F_P_2,
1281   VEX_LEN_3840_P_2,
1282   VEX_LEN_3841_P_2,
1283   VEX_LEN_38DB_P_2,
1284   VEX_LEN_38DC_P_2,
1285   VEX_LEN_38DD_P_2,
1286   VEX_LEN_38DE_P_2,
1287   VEX_LEN_38DF_P_2,
1288   VEX_LEN_3A06_P_2,
1289   VEX_LEN_3A0A_P_2,
1290   VEX_LEN_3A0B_P_2,
1291   VEX_LEN_3A0E_P_2,
1292   VEX_LEN_3A0F_P_2,
1293   VEX_LEN_3A14_P_2,
1294   VEX_LEN_3A15_P_2,
1295   VEX_LEN_3A16_P_2,
1296   VEX_LEN_3A17_P_2,
1297   VEX_LEN_3A18_P_2,
1298   VEX_LEN_3A19_P_2,
1299   VEX_LEN_3A20_P_2,
1300   VEX_LEN_3A21_P_2,
1301   VEX_LEN_3A22_P_2,
1302   VEX_LEN_3A41_P_2,
1303   VEX_LEN_3A42_P_2,
1304   VEX_LEN_3A44_P_2,
1305   VEX_LEN_3A4C_P_2,
1306   VEX_LEN_3A60_P_2,
1307   VEX_LEN_3A61_P_2,
1308   VEX_LEN_3A62_P_2,
1309   VEX_LEN_3A63_P_2,
1310   VEX_LEN_3A6A_P_2,
1311   VEX_LEN_3A6B_P_2,
1312   VEX_LEN_3A6E_P_2,
1313   VEX_LEN_3A6F_P_2,
1314   VEX_LEN_3A7A_P_2,
1315   VEX_LEN_3A7B_P_2,
1316   VEX_LEN_3A7E_P_2,
1317   VEX_LEN_3A7F_P_2,
1318   VEX_LEN_3ADF_P_2,
1319   VEX_LEN_XOP_09_80,
1320   VEX_LEN_XOP_09_81
1321 };
1322
1323 enum
1324 {
1325   VEX_W_10_P_0 = 0,
1326   VEX_W_10_P_1,
1327   VEX_W_10_P_2,
1328   VEX_W_10_P_3,
1329   VEX_W_11_P_0,
1330   VEX_W_11_P_1,
1331   VEX_W_11_P_2,
1332   VEX_W_11_P_3,
1333   VEX_W_12_P_0_M_0,
1334   VEX_W_12_P_0_M_1,
1335   VEX_W_12_P_1,
1336   VEX_W_12_P_2,
1337   VEX_W_12_P_3,
1338   VEX_W_13_M_0,
1339   VEX_W_14,
1340   VEX_W_15,
1341   VEX_W_16_P_0_M_0,
1342   VEX_W_16_P_0_M_1,
1343   VEX_W_16_P_1,
1344   VEX_W_16_P_2,
1345   VEX_W_17_M_0,
1346   VEX_W_28,
1347   VEX_W_29,
1348   VEX_W_2B_M_0,
1349   VEX_W_2E_P_0,
1350   VEX_W_2E_P_2,
1351   VEX_W_2F_P_0,
1352   VEX_W_2F_P_2,
1353   VEX_W_50_M_0,
1354   VEX_W_51_P_0,
1355   VEX_W_51_P_1,
1356   VEX_W_51_P_2,
1357   VEX_W_51_P_3,
1358   VEX_W_52_P_0,
1359   VEX_W_52_P_1,
1360   VEX_W_53_P_0,
1361   VEX_W_53_P_1,
1362   VEX_W_58_P_0,
1363   VEX_W_58_P_1,
1364   VEX_W_58_P_2,
1365   VEX_W_58_P_3,
1366   VEX_W_59_P_0,
1367   VEX_W_59_P_1,
1368   VEX_W_59_P_2,
1369   VEX_W_59_P_3,
1370   VEX_W_5A_P_0,
1371   VEX_W_5A_P_1,
1372   VEX_W_5A_P_3,
1373   VEX_W_5B_P_0,
1374   VEX_W_5B_P_1,
1375   VEX_W_5B_P_2,
1376   VEX_W_5C_P_0,
1377   VEX_W_5C_P_1,
1378   VEX_W_5C_P_2,
1379   VEX_W_5C_P_3,
1380   VEX_W_5D_P_0,
1381   VEX_W_5D_P_1,
1382   VEX_W_5D_P_2,
1383   VEX_W_5D_P_3,
1384   VEX_W_5E_P_0,
1385   VEX_W_5E_P_1,
1386   VEX_W_5E_P_2,
1387   VEX_W_5E_P_3,
1388   VEX_W_5F_P_0,
1389   VEX_W_5F_P_1,
1390   VEX_W_5F_P_2,
1391   VEX_W_5F_P_3,
1392   VEX_W_60_P_2,
1393   VEX_W_61_P_2,
1394   VEX_W_62_P_2,
1395   VEX_W_63_P_2,
1396   VEX_W_64_P_2,
1397   VEX_W_65_P_2,
1398   VEX_W_66_P_2,
1399   VEX_W_67_P_2,
1400   VEX_W_68_P_2,
1401   VEX_W_69_P_2,
1402   VEX_W_6A_P_2,
1403   VEX_W_6B_P_2,
1404   VEX_W_6C_P_2,
1405   VEX_W_6D_P_2,
1406   VEX_W_6F_P_1,
1407   VEX_W_6F_P_2,
1408   VEX_W_70_P_1,
1409   VEX_W_70_P_2,
1410   VEX_W_70_P_3,
1411   VEX_W_71_R_2_P_2,
1412   VEX_W_71_R_4_P_2,
1413   VEX_W_71_R_6_P_2,
1414   VEX_W_72_R_2_P_2,
1415   VEX_W_72_R_4_P_2,
1416   VEX_W_72_R_6_P_2,
1417   VEX_W_73_R_2_P_2,
1418   VEX_W_73_R_3_P_2,
1419   VEX_W_73_R_6_P_2,
1420   VEX_W_73_R_7_P_2,
1421   VEX_W_74_P_2,
1422   VEX_W_75_P_2,
1423   VEX_W_76_P_2,
1424   VEX_W_77_P_0,
1425   VEX_W_7C_P_2,
1426   VEX_W_7C_P_3,
1427   VEX_W_7D_P_2,
1428   VEX_W_7D_P_3,
1429   VEX_W_7E_P_1,
1430   VEX_W_7F_P_1,
1431   VEX_W_7F_P_2,
1432   VEX_W_AE_R_2_M_0,
1433   VEX_W_AE_R_3_M_0,
1434   VEX_W_C2_P_0,
1435   VEX_W_C2_P_1,
1436   VEX_W_C2_P_2,
1437   VEX_W_C2_P_3,
1438   VEX_W_C4_P_2,
1439   VEX_W_C5_P_2,
1440   VEX_W_D0_P_2,
1441   VEX_W_D0_P_3,
1442   VEX_W_D1_P_2,
1443   VEX_W_D2_P_2,
1444   VEX_W_D3_P_2,
1445   VEX_W_D4_P_2,
1446   VEX_W_D5_P_2,
1447   VEX_W_D6_P_2,
1448   VEX_W_D7_P_2_M_1,
1449   VEX_W_D8_P_2,
1450   VEX_W_D9_P_2,
1451   VEX_W_DA_P_2,
1452   VEX_W_DB_P_2,
1453   VEX_W_DC_P_2,
1454   VEX_W_DD_P_2,
1455   VEX_W_DE_P_2,
1456   VEX_W_DF_P_2,
1457   VEX_W_E0_P_2,
1458   VEX_W_E1_P_2,
1459   VEX_W_E2_P_2,
1460   VEX_W_E3_P_2,
1461   VEX_W_E4_P_2,
1462   VEX_W_E5_P_2,
1463   VEX_W_E6_P_1,
1464   VEX_W_E6_P_2,
1465   VEX_W_E6_P_3,
1466   VEX_W_E7_P_2_M_0,
1467   VEX_W_E8_P_2,
1468   VEX_W_E9_P_2,
1469   VEX_W_EA_P_2,
1470   VEX_W_EB_P_2,
1471   VEX_W_EC_P_2,
1472   VEX_W_ED_P_2,
1473   VEX_W_EE_P_2,
1474   VEX_W_EF_P_2,
1475   VEX_W_F0_P_3_M_0,
1476   VEX_W_F1_P_2,
1477   VEX_W_F2_P_2,
1478   VEX_W_F3_P_2,
1479   VEX_W_F4_P_2,
1480   VEX_W_F5_P_2,
1481   VEX_W_F6_P_2,
1482   VEX_W_F7_P_2,
1483   VEX_W_F8_P_2,
1484   VEX_W_F9_P_2,
1485   VEX_W_FA_P_2,
1486   VEX_W_FB_P_2,
1487   VEX_W_FC_P_2,
1488   VEX_W_FD_P_2,
1489   VEX_W_FE_P_2,
1490   VEX_W_3800_P_2,
1491   VEX_W_3801_P_2,
1492   VEX_W_3802_P_2,
1493   VEX_W_3803_P_2,
1494   VEX_W_3804_P_2,
1495   VEX_W_3805_P_2,
1496   VEX_W_3806_P_2,
1497   VEX_W_3807_P_2,
1498   VEX_W_3808_P_2,
1499   VEX_W_3809_P_2,
1500   VEX_W_380A_P_2,
1501   VEX_W_380B_P_2,
1502   VEX_W_380C_P_2,
1503   VEX_W_380D_P_2,
1504   VEX_W_380E_P_2,
1505   VEX_W_380F_P_2,
1506   VEX_W_3817_P_2,
1507   VEX_W_3818_P_2_M_0,
1508   VEX_W_3819_P_2_M_0,
1509   VEX_W_381A_P_2_M_0,
1510   VEX_W_381C_P_2,
1511   VEX_W_381D_P_2,
1512   VEX_W_381E_P_2,
1513   VEX_W_3820_P_2,
1514   VEX_W_3821_P_2,
1515   VEX_W_3822_P_2,
1516   VEX_W_3823_P_2,
1517   VEX_W_3824_P_2,
1518   VEX_W_3825_P_2,
1519   VEX_W_3828_P_2,
1520   VEX_W_3829_P_2,
1521   VEX_W_382A_P_2_M_0,
1522   VEX_W_382B_P_2,
1523   VEX_W_382C_P_2_M_0,
1524   VEX_W_382D_P_2_M_0,
1525   VEX_W_382E_P_2_M_0,
1526   VEX_W_382F_P_2_M_0,
1527   VEX_W_3830_P_2,
1528   VEX_W_3831_P_2,
1529   VEX_W_3832_P_2,
1530   VEX_W_3833_P_2,
1531   VEX_W_3834_P_2,
1532   VEX_W_3835_P_2,
1533   VEX_W_3837_P_2,
1534   VEX_W_3838_P_2,
1535   VEX_W_3839_P_2,
1536   VEX_W_383A_P_2,
1537   VEX_W_383B_P_2,
1538   VEX_W_383C_P_2,
1539   VEX_W_383D_P_2,
1540   VEX_W_383E_P_2,
1541   VEX_W_383F_P_2,
1542   VEX_W_3840_P_2,
1543   VEX_W_3841_P_2,
1544   VEX_W_38DB_P_2,
1545   VEX_W_38DC_P_2,
1546   VEX_W_38DD_P_2,
1547   VEX_W_38DE_P_2,
1548   VEX_W_38DF_P_2,
1549   VEX_W_3A04_P_2,
1550   VEX_W_3A05_P_2,
1551   VEX_W_3A06_P_2,
1552   VEX_W_3A08_P_2,
1553   VEX_W_3A09_P_2,
1554   VEX_W_3A0A_P_2,
1555   VEX_W_3A0B_P_2,
1556   VEX_W_3A0C_P_2,
1557   VEX_W_3A0D_P_2,
1558   VEX_W_3A0E_P_2,
1559   VEX_W_3A0F_P_2,
1560   VEX_W_3A14_P_2,
1561   VEX_W_3A15_P_2,
1562   VEX_W_3A18_P_2,
1563   VEX_W_3A19_P_2,
1564   VEX_W_3A20_P_2,
1565   VEX_W_3A21_P_2,
1566   VEX_W_3A40_P_2,
1567   VEX_W_3A41_P_2,
1568   VEX_W_3A42_P_2,
1569   VEX_W_3A44_P_2,
1570   VEX_W_3A4A_P_2,
1571   VEX_W_3A4B_P_2,
1572   VEX_W_3A4C_P_2,
1573   VEX_W_3A60_P_2,
1574   VEX_W_3A61_P_2,
1575   VEX_W_3A62_P_2,
1576   VEX_W_3A63_P_2,
1577   VEX_W_3ADF_P_2
1578 };
1579
1580 typedef void (*op_rtn) (int bytemode, int sizeflag);
1581
1582 struct dis386 {
1583   const char *name;
1584   struct
1585     {
1586       op_rtn rtn;
1587       int bytemode;
1588     } op[MAX_OPERANDS];
1589 };
1590
1591 /* Upper case letters in the instruction names here are macros.
1592    'A' => print 'b' if no register operands or suffix_always is true
1593    'B' => print 'b' if suffix_always is true
1594    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1595           size prefix
1596    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1597           suffix_always is true
1598    'E' => print 'e' if 32-bit form of jcxz
1599    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1600    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1601    'H' => print ",pt" or ",pn" branch hint
1602    'I' => honor following macro letter even in Intel mode (implemented only
1603           for some of the macro letters)
1604    'J' => print 'l'
1605    'K' => print 'd' or 'q' if rex prefix is present.
1606    'L' => print 'l' if suffix_always is true
1607    'M' => print 'r' if intel_mnemonic is false.
1608    'N' => print 'n' if instruction has no wait "prefix"
1609    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1610    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1611           or suffix_always is true.  print 'q' if rex prefix is present.
1612    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1613           is true
1614    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1615    'S' => print 'w', 'l' or 'q' if suffix_always is true
1616    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1617    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1618    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1619    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1620    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1621    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1622           suffix_always is true.
1623    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1624    '!' => change condition from true to false or from false to true.
1625    '%' => add 1 upper case letter to the macro.
1626
1627    2 upper case letter macros:
1628    "XY" => print 'x' or 'y' if no register operands or suffix_always
1629            is true.
1630    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1631    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1632            or suffix_always is true
1633    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1634    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1635    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1636
1637    Many of the above letters print nothing in Intel mode.  See "putop"
1638    for the details.
1639
1640    Braces '{' and '}', and vertical bars '|', indicate alternative
1641    mnemonic strings for AT&T and Intel.  */
1642
1643 static const struct dis386 dis386[] = {
1644   /* 00 */
1645   { "addB",             { Eb, Gb } },
1646   { "addS",             { Ev, Gv } },
1647   { "addB",             { Gb, EbS } },
1648   { "addS",             { Gv, EvS } },
1649   { "addB",             { AL, Ib } },
1650   { "addS",             { eAX, Iv } },
1651   { X86_64_TABLE (X86_64_06) },
1652   { X86_64_TABLE (X86_64_07) },
1653   /* 08 */
1654   { "orB",              { Eb, Gb } },
1655   { "orS",              { Ev, Gv } },
1656   { "orB",              { Gb, EbS } },
1657   { "orS",              { Gv, EvS } },
1658   { "orB",              { AL, Ib } },
1659   { "orS",              { eAX, Iv } },
1660   { X86_64_TABLE (X86_64_0D) },
1661   { Bad_Opcode },       /* 0x0f extended opcode escape */
1662   /* 10 */
1663   { "adcB",             { Eb, Gb } },
1664   { "adcS",             { Ev, Gv } },
1665   { "adcB",             { Gb, EbS } },
1666   { "adcS",             { Gv, EvS } },
1667   { "adcB",             { AL, Ib } },
1668   { "adcS",             { eAX, Iv } },
1669   { X86_64_TABLE (X86_64_16) },
1670   { X86_64_TABLE (X86_64_17) },
1671   /* 18 */
1672   { "sbbB",             { Eb, Gb } },
1673   { "sbbS",             { Ev, Gv } },
1674   { "sbbB",             { Gb, EbS } },
1675   { "sbbS",             { Gv, EvS } },
1676   { "sbbB",             { AL, Ib } },
1677   { "sbbS",             { eAX, Iv } },
1678   { X86_64_TABLE (X86_64_1E) },
1679   { X86_64_TABLE (X86_64_1F) },
1680   /* 20 */
1681   { "andB",             { Eb, Gb } },
1682   { "andS",             { Ev, Gv } },
1683   { "andB",             { Gb, EbS } },
1684   { "andS",             { Gv, EvS } },
1685   { "andB",             { AL, Ib } },
1686   { "andS",             { eAX, Iv } },
1687   { Bad_Opcode },       /* SEG ES prefix */
1688   { X86_64_TABLE (X86_64_27) },
1689   /* 28 */
1690   { "subB",             { Eb, Gb } },
1691   { "subS",             { Ev, Gv } },
1692   { "subB",             { Gb, EbS } },
1693   { "subS",             { Gv, EvS } },
1694   { "subB",             { AL, Ib } },
1695   { "subS",             { eAX, Iv } },
1696   { Bad_Opcode },       /* SEG CS prefix */
1697   { X86_64_TABLE (X86_64_2F) },
1698   /* 30 */
1699   { "xorB",             { Eb, Gb } },
1700   { "xorS",             { Ev, Gv } },
1701   { "xorB",             { Gb, EbS } },
1702   { "xorS",             { Gv, EvS } },
1703   { "xorB",             { AL, Ib } },
1704   { "xorS",             { eAX, Iv } },
1705   { Bad_Opcode },       /* SEG SS prefix */
1706   { X86_64_TABLE (X86_64_37) },
1707   /* 38 */
1708   { "cmpB",             { Eb, Gb } },
1709   { "cmpS",             { Ev, Gv } },
1710   { "cmpB",             { Gb, EbS } },
1711   { "cmpS",             { Gv, EvS } },
1712   { "cmpB",             { AL, Ib } },
1713   { "cmpS",             { eAX, Iv } },
1714   { Bad_Opcode },       /* SEG DS prefix */
1715   { X86_64_TABLE (X86_64_3F) },
1716   /* 40 */
1717   { "inc{S|}",          { RMeAX } },
1718   { "inc{S|}",          { RMeCX } },
1719   { "inc{S|}",          { RMeDX } },
1720   { "inc{S|}",          { RMeBX } },
1721   { "inc{S|}",          { RMeSP } },
1722   { "inc{S|}",          { RMeBP } },
1723   { "inc{S|}",          { RMeSI } },
1724   { "inc{S|}",          { RMeDI } },
1725   /* 48 */
1726   { "dec{S|}",          { RMeAX } },
1727   { "dec{S|}",          { RMeCX } },
1728   { "dec{S|}",          { RMeDX } },
1729   { "dec{S|}",          { RMeBX } },
1730   { "dec{S|}",          { RMeSP } },
1731   { "dec{S|}",          { RMeBP } },
1732   { "dec{S|}",          { RMeSI } },
1733   { "dec{S|}",          { RMeDI } },
1734   /* 50 */
1735   { "pushV",            { RMrAX } },
1736   { "pushV",            { RMrCX } },
1737   { "pushV",            { RMrDX } },
1738   { "pushV",            { RMrBX } },
1739   { "pushV",            { RMrSP } },
1740   { "pushV",            { RMrBP } },
1741   { "pushV",            { RMrSI } },
1742   { "pushV",            { RMrDI } },
1743   /* 58 */
1744   { "popV",             { RMrAX } },
1745   { "popV",             { RMrCX } },
1746   { "popV",             { RMrDX } },
1747   { "popV",             { RMrBX } },
1748   { "popV",             { RMrSP } },
1749   { "popV",             { RMrBP } },
1750   { "popV",             { RMrSI } },
1751   { "popV",             { RMrDI } },
1752   /* 60 */
1753   { X86_64_TABLE (X86_64_60) },
1754   { X86_64_TABLE (X86_64_61) },
1755   { X86_64_TABLE (X86_64_62) },
1756   { X86_64_TABLE (X86_64_63) },
1757   { Bad_Opcode },       /* seg fs */
1758   { Bad_Opcode },       /* seg gs */
1759   { Bad_Opcode },       /* op size prefix */
1760   { Bad_Opcode },       /* adr size prefix */
1761   /* 68 */
1762   { "pushT",            { Iq } },
1763   { "imulS",            { Gv, Ev, Iv } },
1764   { "pushT",            { sIb } },
1765   { "imulS",            { Gv, Ev, sIb } },
1766   { "ins{b|}",          { Ybr, indirDX } },
1767   { X86_64_TABLE (X86_64_6D) },
1768   { "outs{b|}",         { indirDXr, Xb } },
1769   { X86_64_TABLE (X86_64_6F) },
1770   /* 70 */
1771   { "joH",              { Jb, XX, cond_jump_flag } },
1772   { "jnoH",             { Jb, XX, cond_jump_flag } },
1773   { "jbH",              { Jb, XX, cond_jump_flag } },
1774   { "jaeH",             { Jb, XX, cond_jump_flag } },
1775   { "jeH",              { Jb, XX, cond_jump_flag } },
1776   { "jneH",             { Jb, XX, cond_jump_flag } },
1777   { "jbeH",             { Jb, XX, cond_jump_flag } },
1778   { "jaH",              { Jb, XX, cond_jump_flag } },
1779   /* 78 */
1780   { "jsH",              { Jb, XX, cond_jump_flag } },
1781   { "jnsH",             { Jb, XX, cond_jump_flag } },
1782   { "jpH",              { Jb, XX, cond_jump_flag } },
1783   { "jnpH",             { Jb, XX, cond_jump_flag } },
1784   { "jlH",              { Jb, XX, cond_jump_flag } },
1785   { "jgeH",             { Jb, XX, cond_jump_flag } },
1786   { "jleH",             { Jb, XX, cond_jump_flag } },
1787   { "jgH",              { Jb, XX, cond_jump_flag } },
1788   /* 80 */
1789   { REG_TABLE (REG_80) },
1790   { REG_TABLE (REG_81) },
1791   { Bad_Opcode },
1792   { REG_TABLE (REG_82) },
1793   { "testB",            { Eb, Gb } },
1794   { "testS",            { Ev, Gv } },
1795   { "xchgB",            { Eb, Gb } },
1796   { "xchgS",            { Ev, Gv } },
1797   /* 88 */
1798   { "movB",             { Eb, Gb } },
1799   { "movS",             { Ev, Gv } },
1800   { "movB",             { Gb, EbS } },
1801   { "movS",             { Gv, EvS } },
1802   { "movD",             { Sv, Sw } },
1803   { MOD_TABLE (MOD_8D) },
1804   { "movD",             { Sw, Sv } },
1805   { REG_TABLE (REG_8F) },
1806   /* 90 */
1807   { PREFIX_TABLE (PREFIX_90) },
1808   { "xchgS",            { RMeCX, eAX } },
1809   { "xchgS",            { RMeDX, eAX } },
1810   { "xchgS",            { RMeBX, eAX } },
1811   { "xchgS",            { RMeSP, eAX } },
1812   { "xchgS",            { RMeBP, eAX } },
1813   { "xchgS",            { RMeSI, eAX } },
1814   { "xchgS",            { RMeDI, eAX } },
1815   /* 98 */
1816   { "cW{t|}R",          { XX } },
1817   { "cR{t|}O",          { XX } },
1818   { X86_64_TABLE (X86_64_9A) },
1819   { Bad_Opcode },       /* fwait */
1820   { "pushfT",           { XX } },
1821   { "popfT",            { XX } },
1822   { "sahf",             { XX } },
1823   { "lahf",             { XX } },
1824   /* a0 */
1825   { "mov%LB",           { AL, Ob } },
1826   { "mov%LS",           { eAX, Ov } },
1827   { "mov%LB",           { Ob, AL } },
1828   { "mov%LS",           { Ov, eAX } },
1829   { "movs{b|}",         { Ybr, Xb } },
1830   { "movs{R|}",         { Yvr, Xv } },
1831   { "cmps{b|}",         { Xb, Yb } },
1832   { "cmps{R|}",         { Xv, Yv } },
1833   /* a8 */
1834   { "testB",            { AL, Ib } },
1835   { "testS",            { eAX, Iv } },
1836   { "stosB",            { Ybr, AL } },
1837   { "stosS",            { Yvr, eAX } },
1838   { "lodsB",            { ALr, Xb } },
1839   { "lodsS",            { eAXr, Xv } },
1840   { "scasB",            { AL, Yb } },
1841   { "scasS",            { eAX, Yv } },
1842   /* b0 */
1843   { "movB",             { RMAL, Ib } },
1844   { "movB",             { RMCL, Ib } },
1845   { "movB",             { RMDL, Ib } },
1846   { "movB",             { RMBL, Ib } },
1847   { "movB",             { RMAH, Ib } },
1848   { "movB",             { RMCH, Ib } },
1849   { "movB",             { RMDH, Ib } },
1850   { "movB",             { RMBH, Ib } },
1851   /* b8 */
1852   { "mov%LV",           { RMeAX, Iv64 } },
1853   { "mov%LV",           { RMeCX, Iv64 } },
1854   { "mov%LV",           { RMeDX, Iv64 } },
1855   { "mov%LV",           { RMeBX, Iv64 } },
1856   { "mov%LV",           { RMeSP, Iv64 } },
1857   { "mov%LV",           { RMeBP, Iv64 } },
1858   { "mov%LV",           { RMeSI, Iv64 } },
1859   { "mov%LV",           { RMeDI, Iv64 } },
1860   /* c0 */
1861   { REG_TABLE (REG_C0) },
1862   { REG_TABLE (REG_C1) },
1863   { "retT",             { Iw } },
1864   { "retT",             { XX } },
1865   { X86_64_TABLE (X86_64_C4) },
1866   { X86_64_TABLE (X86_64_C5) },
1867   { REG_TABLE (REG_C6) },
1868   { REG_TABLE (REG_C7) },
1869   /* c8 */
1870   { "enterT",           { Iw, Ib } },
1871   { "leaveT",           { XX } },
1872   { "Jret{|f}P",        { Iw } },
1873   { "Jret{|f}P",        { XX } },
1874   { "int3",             { XX } },
1875   { "int",              { Ib } },
1876   { X86_64_TABLE (X86_64_CE) },
1877   { "iretP",            { XX } },
1878   /* d0 */
1879   { REG_TABLE (REG_D0) },
1880   { REG_TABLE (REG_D1) },
1881   { REG_TABLE (REG_D2) },
1882   { REG_TABLE (REG_D3) },
1883   { X86_64_TABLE (X86_64_D4) },
1884   { X86_64_TABLE (X86_64_D5) },
1885   { Bad_Opcode },
1886   { "xlat",             { DSBX } },
1887   /* d8 */
1888   { FLOAT },
1889   { FLOAT },
1890   { FLOAT },
1891   { FLOAT },
1892   { FLOAT },
1893   { FLOAT },
1894   { FLOAT },
1895   { FLOAT },
1896   /* e0 */
1897   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1898   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1899   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1900   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1901   { "inB",              { AL, Ib } },
1902   { "inG",              { zAX, Ib } },
1903   { "outB",             { Ib, AL } },
1904   { "outG",             { Ib, zAX } },
1905   /* e8 */
1906   { "callT",            { Jv } },
1907   { "jmpT",             { Jv } },
1908   { X86_64_TABLE (X86_64_EA) },
1909   { "jmp",              { Jb } },
1910   { "inB",              { AL, indirDX } },
1911   { "inG",              { zAX, indirDX } },
1912   { "outB",             { indirDX, AL } },
1913   { "outG",             { indirDX, zAX } },
1914   /* f0 */
1915   { Bad_Opcode },       /* lock prefix */
1916   { "icebp",            { XX } },
1917   { Bad_Opcode },       /* repne */
1918   { Bad_Opcode },       /* repz */
1919   { "hlt",              { XX } },
1920   { "cmc",              { XX } },
1921   { REG_TABLE (REG_F6) },
1922   { REG_TABLE (REG_F7) },
1923   /* f8 */
1924   { "clc",              { XX } },
1925   { "stc",              { XX } },
1926   { "cli",              { XX } },
1927   { "sti",              { XX } },
1928   { "cld",              { XX } },
1929   { "std",              { XX } },
1930   { REG_TABLE (REG_FE) },
1931   { REG_TABLE (REG_FF) },
1932 };
1933
1934 static const struct dis386 dis386_twobyte[] = {
1935   /* 00 */
1936   { REG_TABLE (REG_0F00 ) },
1937   { REG_TABLE (REG_0F01 ) },
1938   { "larS",             { Gv, Ew } },
1939   { "lslS",             { Gv, Ew } },
1940   { Bad_Opcode },
1941   { "syscall",          { XX } },
1942   { "clts",             { XX } },
1943   { "sysretP",          { XX } },
1944   /* 08 */
1945   { "invd",             { XX } },
1946   { "wbinvd",           { XX } },
1947   { Bad_Opcode },
1948   { "ud2a",             { XX } },
1949   { Bad_Opcode },
1950   { REG_TABLE (REG_0F0D) },
1951   { "femms",            { XX } },
1952   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1953   /* 10 */
1954   { PREFIX_TABLE (PREFIX_0F10) },
1955   { PREFIX_TABLE (PREFIX_0F11) },
1956   { PREFIX_TABLE (PREFIX_0F12) },
1957   { MOD_TABLE (MOD_0F13) },
1958   { "unpcklpX",         { XM, EXx } },
1959   { "unpckhpX",         { XM, EXx } },
1960   { PREFIX_TABLE (PREFIX_0F16) },
1961   { MOD_TABLE (MOD_0F17) },
1962   /* 18 */
1963   { REG_TABLE (REG_0F18) },
1964   { "nopQ",             { Ev } },
1965   { "nopQ",             { Ev } },
1966   { "nopQ",             { Ev } },
1967   { "nopQ",             { Ev } },
1968   { "nopQ",             { Ev } },
1969   { "nopQ",             { Ev } },
1970   { "nopQ",             { Ev } },
1971   /* 20 */
1972   { MOD_TABLE (MOD_0F20) },
1973   { MOD_TABLE (MOD_0F21) },
1974   { MOD_TABLE (MOD_0F22) },
1975   { MOD_TABLE (MOD_0F23) },
1976   { MOD_TABLE (MOD_0F24) },
1977   { Bad_Opcode },
1978   { MOD_TABLE (MOD_0F26) },
1979   { Bad_Opcode },
1980   /* 28 */
1981   { "movapX",           { XM, EXx } },
1982   { "movapX",           { EXxS, XM } },
1983   { PREFIX_TABLE (PREFIX_0F2A) },
1984   { PREFIX_TABLE (PREFIX_0F2B) },
1985   { PREFIX_TABLE (PREFIX_0F2C) },
1986   { PREFIX_TABLE (PREFIX_0F2D) },
1987   { PREFIX_TABLE (PREFIX_0F2E) },
1988   { PREFIX_TABLE (PREFIX_0F2F) },
1989   /* 30 */
1990   { "wrmsr",            { XX } },
1991   { "rdtsc",            { XX } },
1992   { "rdmsr",            { XX } },
1993   { "rdpmc",            { XX } },
1994   { "sysenter",         { XX } },
1995   { "sysexit",          { XX } },
1996   { Bad_Opcode },
1997   { "getsec",           { XX } },
1998   /* 38 */
1999   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2000   { Bad_Opcode },
2001   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2002   { Bad_Opcode },
2003   { Bad_Opcode },
2004   { Bad_Opcode },
2005   { Bad_Opcode },
2006   { Bad_Opcode },
2007   /* 40 */
2008   { "cmovoS",           { Gv, Ev } },
2009   { "cmovnoS",          { Gv, Ev } },
2010   { "cmovbS",           { Gv, Ev } },
2011   { "cmovaeS",          { Gv, Ev } },
2012   { "cmoveS",           { Gv, Ev } },
2013   { "cmovneS",          { Gv, Ev } },
2014   { "cmovbeS",          { Gv, Ev } },
2015   { "cmovaS",           { Gv, Ev } },
2016   /* 48 */
2017   { "cmovsS",           { Gv, Ev } },
2018   { "cmovnsS",          { Gv, Ev } },
2019   { "cmovpS",           { Gv, Ev } },
2020   { "cmovnpS",          { Gv, Ev } },
2021   { "cmovlS",           { Gv, Ev } },
2022   { "cmovgeS",          { Gv, Ev } },
2023   { "cmovleS",          { Gv, Ev } },
2024   { "cmovgS",           { Gv, Ev } },
2025   /* 50 */
2026   { MOD_TABLE (MOD_0F51) },
2027   { PREFIX_TABLE (PREFIX_0F51) },
2028   { PREFIX_TABLE (PREFIX_0F52) },
2029   { PREFIX_TABLE (PREFIX_0F53) },
2030   { "andpX",            { XM, EXx } },
2031   { "andnpX",           { XM, EXx } },
2032   { "orpX",             { XM, EXx } },
2033   { "xorpX",            { XM, EXx } },
2034   /* 58 */
2035   { PREFIX_TABLE (PREFIX_0F58) },
2036   { PREFIX_TABLE (PREFIX_0F59) },
2037   { PREFIX_TABLE (PREFIX_0F5A) },
2038   { PREFIX_TABLE (PREFIX_0F5B) },
2039   { PREFIX_TABLE (PREFIX_0F5C) },
2040   { PREFIX_TABLE (PREFIX_0F5D) },
2041   { PREFIX_TABLE (PREFIX_0F5E) },
2042   { PREFIX_TABLE (PREFIX_0F5F) },
2043   /* 60 */
2044   { PREFIX_TABLE (PREFIX_0F60) },
2045   { PREFIX_TABLE (PREFIX_0F61) },
2046   { PREFIX_TABLE (PREFIX_0F62) },
2047   { "packsswb",         { MX, EM } },
2048   { "pcmpgtb",          { MX, EM } },
2049   { "pcmpgtw",          { MX, EM } },
2050   { "pcmpgtd",          { MX, EM } },
2051   { "packuswb",         { MX, EM } },
2052   /* 68 */
2053   { "punpckhbw",        { MX, EM } },
2054   { "punpckhwd",        { MX, EM } },
2055   { "punpckhdq",        { MX, EM } },
2056   { "packssdw",         { MX, EM } },
2057   { PREFIX_TABLE (PREFIX_0F6C) },
2058   { PREFIX_TABLE (PREFIX_0F6D) },
2059   { "movK",             { MX, Edq } },
2060   { PREFIX_TABLE (PREFIX_0F6F) },
2061   /* 70 */
2062   { PREFIX_TABLE (PREFIX_0F70) },
2063   { REG_TABLE (REG_0F71) },
2064   { REG_TABLE (REG_0F72) },
2065   { REG_TABLE (REG_0F73) },
2066   { "pcmpeqb",          { MX, EM } },
2067   { "pcmpeqw",          { MX, EM } },
2068   { "pcmpeqd",          { MX, EM } },
2069   { "emms",             { XX } },
2070   /* 78 */
2071   { PREFIX_TABLE (PREFIX_0F78) },
2072   { PREFIX_TABLE (PREFIX_0F79) },
2073   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2074   { Bad_Opcode },
2075   { PREFIX_TABLE (PREFIX_0F7C) },
2076   { PREFIX_TABLE (PREFIX_0F7D) },
2077   { PREFIX_TABLE (PREFIX_0F7E) },
2078   { PREFIX_TABLE (PREFIX_0F7F) },
2079   /* 80 */
2080   { "joH",              { Jv, XX, cond_jump_flag } },
2081   { "jnoH",             { Jv, XX, cond_jump_flag } },
2082   { "jbH",              { Jv, XX, cond_jump_flag } },
2083   { "jaeH",             { Jv, XX, cond_jump_flag } },
2084   { "jeH",              { Jv, XX, cond_jump_flag } },
2085   { "jneH",             { Jv, XX, cond_jump_flag } },
2086   { "jbeH",             { Jv, XX, cond_jump_flag } },
2087   { "jaH",              { Jv, XX, cond_jump_flag } },
2088   /* 88 */
2089   { "jsH",              { Jv, XX, cond_jump_flag } },
2090   { "jnsH",             { Jv, XX, cond_jump_flag } },
2091   { "jpH",              { Jv, XX, cond_jump_flag } },
2092   { "jnpH",             { Jv, XX, cond_jump_flag } },
2093   { "jlH",              { Jv, XX, cond_jump_flag } },
2094   { "jgeH",             { Jv, XX, cond_jump_flag } },
2095   { "jleH",             { Jv, XX, cond_jump_flag } },
2096   { "jgH",              { Jv, XX, cond_jump_flag } },
2097   /* 90 */
2098   { "seto",             { Eb } },
2099   { "setno",            { Eb } },
2100   { "setb",             { Eb } },
2101   { "setae",            { Eb } },
2102   { "sete",             { Eb } },
2103   { "setne",            { Eb } },
2104   { "setbe",            { Eb } },
2105   { "seta",             { Eb } },
2106   /* 98 */
2107   { "sets",             { Eb } },
2108   { "setns",            { Eb } },
2109   { "setp",             { Eb } },
2110   { "setnp",            { Eb } },
2111   { "setl",             { Eb } },
2112   { "setge",            { Eb } },
2113   { "setle",            { Eb } },
2114   { "setg",             { Eb } },
2115   /* a0 */
2116   { "pushT",            { fs } },
2117   { "popT",             { fs } },
2118   { "cpuid",            { XX } },
2119   { "btS",              { Ev, Gv } },
2120   { "shldS",            { Ev, Gv, Ib } },
2121   { "shldS",            { Ev, Gv, CL } },
2122   { REG_TABLE (REG_0FA6) },
2123   { REG_TABLE (REG_0FA7) },
2124   /* a8 */
2125   { "pushT",            { gs } },
2126   { "popT",             { gs } },
2127   { "rsm",              { XX } },
2128   { "btsS",             { Ev, Gv } },
2129   { "shrdS",            { Ev, Gv, Ib } },
2130   { "shrdS",            { Ev, Gv, CL } },
2131   { REG_TABLE (REG_0FAE) },
2132   { "imulS",            { Gv, Ev } },
2133   /* b0 */
2134   { "cmpxchgB",         { Eb, Gb } },
2135   { "cmpxchgS",         { Ev, Gv } },
2136   { MOD_TABLE (MOD_0FB2) },
2137   { "btrS",             { Ev, Gv } },
2138   { MOD_TABLE (MOD_0FB4) },
2139   { MOD_TABLE (MOD_0FB5) },
2140   { "movz{bR|x}",       { Gv, Eb } },
2141   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2142   /* b8 */
2143   { PREFIX_TABLE (PREFIX_0FB8) },
2144   { "ud2b",             { XX } },
2145   { REG_TABLE (REG_0FBA) },
2146   { "btcS",             { Ev, Gv } },
2147   { "bsfS",             { Gv, Ev } },
2148   { PREFIX_TABLE (PREFIX_0FBD) },
2149   { "movs{bR|x}",       { Gv, Eb } },
2150   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2151   /* c0 */
2152   { "xaddB",            { Eb, Gb } },
2153   { "xaddS",            { Ev, Gv } },
2154   { PREFIX_TABLE (PREFIX_0FC2) },
2155   { PREFIX_TABLE (PREFIX_0FC3) },
2156   { "pinsrw",           { MX, Edqw, Ib } },
2157   { "pextrw",           { Gdq, MS, Ib } },
2158   { "shufpX",           { XM, EXx, Ib } },
2159   { REG_TABLE (REG_0FC7) },
2160   /* c8 */
2161   { "bswap",            { RMeAX } },
2162   { "bswap",            { RMeCX } },
2163   { "bswap",            { RMeDX } },
2164   { "bswap",            { RMeBX } },
2165   { "bswap",            { RMeSP } },
2166   { "bswap",            { RMeBP } },
2167   { "bswap",            { RMeSI } },
2168   { "bswap",            { RMeDI } },
2169   /* d0 */
2170   { PREFIX_TABLE (PREFIX_0FD0) },
2171   { "psrlw",            { MX, EM } },
2172   { "psrld",            { MX, EM } },
2173   { "psrlq",            { MX, EM } },
2174   { "paddq",            { MX, EM } },
2175   { "pmullw",           { MX, EM } },
2176   { PREFIX_TABLE (PREFIX_0FD6) },
2177   { MOD_TABLE (MOD_0FD7) },
2178   /* d8 */
2179   { "psubusb",          { MX, EM } },
2180   { "psubusw",          { MX, EM } },
2181   { "pminub",           { MX, EM } },
2182   { "pand",             { MX, EM } },
2183   { "paddusb",          { MX, EM } },
2184   { "paddusw",          { MX, EM } },
2185   { "pmaxub",           { MX, EM } },
2186   { "pandn",            { MX, EM } },
2187   /* e0 */
2188   { "pavgb",            { MX, EM } },
2189   { "psraw",            { MX, EM } },
2190   { "psrad",            { MX, EM } },
2191   { "pavgw",            { MX, EM } },
2192   { "pmulhuw",          { MX, EM } },
2193   { "pmulhw",           { MX, EM } },
2194   { PREFIX_TABLE (PREFIX_0FE6) },
2195   { PREFIX_TABLE (PREFIX_0FE7) },
2196   /* e8 */
2197   { "psubsb",           { MX, EM } },
2198   { "psubsw",           { MX, EM } },
2199   { "pminsw",           { MX, EM } },
2200   { "por",              { MX, EM } },
2201   { "paddsb",           { MX, EM } },
2202   { "paddsw",           { MX, EM } },
2203   { "pmaxsw",           { MX, EM } },
2204   { "pxor",             { MX, EM } },
2205   /* f0 */
2206   { PREFIX_TABLE (PREFIX_0FF0) },
2207   { "psllw",            { MX, EM } },
2208   { "pslld",            { MX, EM } },
2209   { "psllq",            { MX, EM } },
2210   { "pmuludq",          { MX, EM } },
2211   { "pmaddwd",          { MX, EM } },
2212   { "psadbw",           { MX, EM } },
2213   { PREFIX_TABLE (PREFIX_0FF7) },
2214   /* f8 */
2215   { "psubb",            { MX, EM } },
2216   { "psubw",            { MX, EM } },
2217   { "psubd",            { MX, EM } },
2218   { "psubq",            { MX, EM } },
2219   { "paddb",            { MX, EM } },
2220   { "paddw",            { MX, EM } },
2221   { "paddd",            { MX, EM } },
2222   { Bad_Opcode },
2223 };
2224
2225 static const unsigned char onebyte_has_modrm[256] = {
2226   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2227   /*       -------------------------------        */
2228   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2229   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2230   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2231   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2232   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2233   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2234   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2235   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2236   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2237   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2238   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2239   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2240   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2241   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2242   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2243   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2244   /*       -------------------------------        */
2245   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2246 };
2247
2248 static const unsigned char twobyte_has_modrm[256] = {
2249   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2250   /*       -------------------------------        */
2251   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2252   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2253   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2254   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2255   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2256   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2257   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2258   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2259   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2260   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2261   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2262   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2263   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2264   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2265   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2266   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2267   /*       -------------------------------        */
2268   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2269 };
2270
2271 static char obuf[100];
2272 static char *obufp;
2273 static char *mnemonicendp;
2274 static char scratchbuf[100];
2275 static unsigned char *start_codep;
2276 static unsigned char *insn_codep;
2277 static unsigned char *codep;
2278 static int last_lock_prefix;
2279 static int last_repz_prefix;
2280 static int last_repnz_prefix;
2281 static int last_data_prefix;
2282 static int last_addr_prefix;
2283 static int last_rex_prefix;
2284 static int last_seg_prefix;
2285 #define MAX_CODE_LENGTH 15
2286 /* We can up to 14 prefixes since the maximum instruction length is
2287    15bytes.  */
2288 static int all_prefixes[MAX_CODE_LENGTH - 1];
2289 static disassemble_info *the_info;
2290 static struct
2291   {
2292     int mod;
2293     int reg;
2294     int rm;
2295   }
2296 modrm;
2297 static unsigned char need_modrm;
2298 static struct
2299   {
2300     int register_specifier;
2301     int length;
2302     int prefix;
2303     int w;
2304   }
2305 vex;
2306 static unsigned char need_vex;
2307 static unsigned char need_vex_reg;
2308 static unsigned char vex_w_done;
2309
2310 struct op
2311   {
2312     const char *name;
2313     unsigned int len;
2314   };
2315
2316 /* If we are accessing mod/rm/reg without need_modrm set, then the
2317    values are stale.  Hitting this abort likely indicates that you
2318    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2319 #define MODRM_CHECK  if (!need_modrm) abort ()
2320
2321 static const char **names64;
2322 static const char **names32;
2323 static const char **names16;
2324 static const char **names8;
2325 static const char **names8rex;
2326 static const char **names_seg;
2327 static const char *index64;
2328 static const char *index32;
2329 static const char **index16;
2330
2331 static const char *intel_names64[] = {
2332   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2333   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2334 };
2335 static const char *intel_names32[] = {
2336   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2337   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2338 };
2339 static const char *intel_names16[] = {
2340   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2341   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2342 };
2343 static const char *intel_names8[] = {
2344   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2345 };
2346 static const char *intel_names8rex[] = {
2347   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2348   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2349 };
2350 static const char *intel_names_seg[] = {
2351   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2352 };
2353 static const char *intel_index64 = "riz";
2354 static const char *intel_index32 = "eiz";
2355 static const char *intel_index16[] = {
2356   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2357 };
2358
2359 static const char *att_names64[] = {
2360   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2361   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2362 };
2363 static const char *att_names32[] = {
2364   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2365   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2366 };
2367 static const char *att_names16[] = {
2368   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2369   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2370 };
2371 static const char *att_names8[] = {
2372   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2373 };
2374 static const char *att_names8rex[] = {
2375   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2376   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2377 };
2378 static const char *att_names_seg[] = {
2379   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2380 };
2381 static const char *att_index64 = "%riz";
2382 static const char *att_index32 = "%eiz";
2383 static const char *att_index16[] = {
2384   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2385 };
2386
2387 static const char **names_mm;
2388 static const char *intel_names_mm[] = {
2389   "mm0", "mm1", "mm2", "mm3",
2390   "mm4", "mm5", "mm6", "mm7"
2391 };
2392 static const char *att_names_mm[] = {
2393   "%mm0", "%mm1", "%mm2", "%mm3",
2394   "%mm4", "%mm5", "%mm6", "%mm7"
2395 };
2396
2397 static const char **names_xmm;
2398 static const char *intel_names_xmm[] = {
2399   "xmm0", "xmm1", "xmm2", "xmm3",
2400   "xmm4", "xmm5", "xmm6", "xmm7",
2401   "xmm8", "xmm9", "xmm10", "xmm11",
2402   "xmm12", "xmm13", "xmm14", "xmm15"
2403 };
2404 static const char *att_names_xmm[] = {
2405   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2406   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2407   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2408   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2409 };
2410
2411 static const char **names_ymm;
2412 static const char *intel_names_ymm[] = {
2413   "ymm0", "ymm1", "ymm2", "ymm3",
2414   "ymm4", "ymm5", "ymm6", "ymm7",
2415   "ymm8", "ymm9", "ymm10", "ymm11",
2416   "ymm12", "ymm13", "ymm14", "ymm15"
2417 };
2418 static const char *att_names_ymm[] = {
2419   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2420   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2421   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2422   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2423 };
2424
2425 static const struct dis386 reg_table[][8] = {
2426   /* REG_80 */
2427   {
2428     { "addA",   { Eb, Ib } },
2429     { "orA",    { Eb, Ib } },
2430     { "adcA",   { Eb, Ib } },
2431     { "sbbA",   { Eb, Ib } },
2432     { "andA",   { Eb, Ib } },
2433     { "subA",   { Eb, Ib } },
2434     { "xorA",   { Eb, Ib } },
2435     { "cmpA",   { Eb, Ib } },
2436   },
2437   /* REG_81 */
2438   {
2439     { "addQ",   { Ev, Iv } },
2440     { "orQ",    { Ev, Iv } },
2441     { "adcQ",   { Ev, Iv } },
2442     { "sbbQ",   { Ev, Iv } },
2443     { "andQ",   { Ev, Iv } },
2444     { "subQ",   { Ev, Iv } },
2445     { "xorQ",   { Ev, Iv } },
2446     { "cmpQ",   { Ev, Iv } },
2447   },
2448   /* REG_82 */
2449   {
2450     { "addQ",   { Ev, sIb } },
2451     { "orQ",    { Ev, sIb } },
2452     { "adcQ",   { Ev, sIb } },
2453     { "sbbQ",   { Ev, sIb } },
2454     { "andQ",   { Ev, sIb } },
2455     { "subQ",   { Ev, sIb } },
2456     { "xorQ",   { Ev, sIb } },
2457     { "cmpQ",   { Ev, sIb } },
2458   },
2459   /* REG_8F */
2460   {
2461     { "popU",   { stackEv } },
2462     { XOP_8F_TABLE (XOP_09) },
2463     { Bad_Opcode },
2464     { Bad_Opcode },
2465     { Bad_Opcode },
2466     { XOP_8F_TABLE (XOP_09) },
2467   },
2468   /* REG_C0 */
2469   {
2470     { "rolA",   { Eb, Ib } },
2471     { "rorA",   { Eb, Ib } },
2472     { "rclA",   { Eb, Ib } },
2473     { "rcrA",   { Eb, Ib } },
2474     { "shlA",   { Eb, Ib } },
2475     { "shrA",   { Eb, Ib } },
2476     { Bad_Opcode },
2477     { "sarA",   { Eb, Ib } },
2478   },
2479   /* REG_C1 */
2480   {
2481     { "rolQ",   { Ev, Ib } },
2482     { "rorQ",   { Ev, Ib } },
2483     { "rclQ",   { Ev, Ib } },
2484     { "rcrQ",   { Ev, Ib } },
2485     { "shlQ",   { Ev, Ib } },
2486     { "shrQ",   { Ev, Ib } },
2487     { Bad_Opcode },
2488     { "sarQ",   { Ev, Ib } },
2489   },
2490   /* REG_C6 */
2491   {
2492     { "movA",   { Eb, Ib } },
2493   },
2494   /* REG_C7 */
2495   {
2496     { "movQ",   { Ev, Iv } },
2497   },
2498   /* REG_D0 */
2499   {
2500     { "rolA",   { Eb, I1 } },
2501     { "rorA",   { Eb, I1 } },
2502     { "rclA",   { Eb, I1 } },
2503     { "rcrA",   { Eb, I1 } },
2504     { "shlA",   { Eb, I1 } },
2505     { "shrA",   { Eb, I1 } },
2506     { Bad_Opcode },
2507     { "sarA",   { Eb, I1 } },
2508   },
2509   /* REG_D1 */
2510   {
2511     { "rolQ",   { Ev, I1 } },
2512     { "rorQ",   { Ev, I1 } },
2513     { "rclQ",   { Ev, I1 } },
2514     { "rcrQ",   { Ev, I1 } },
2515     { "shlQ",   { Ev, I1 } },
2516     { "shrQ",   { Ev, I1 } },
2517     { Bad_Opcode },
2518     { "sarQ",   { Ev, I1 } },
2519   },
2520   /* REG_D2 */
2521   {
2522     { "rolA",   { Eb, CL } },
2523     { "rorA",   { Eb, CL } },
2524     { "rclA",   { Eb, CL } },
2525     { "rcrA",   { Eb, CL } },
2526     { "shlA",   { Eb, CL } },
2527     { "shrA",   { Eb, CL } },
2528     { Bad_Opcode },
2529     { "sarA",   { Eb, CL } },
2530   },
2531   /* REG_D3 */
2532   {
2533     { "rolQ",   { Ev, CL } },
2534     { "rorQ",   { Ev, CL } },
2535     { "rclQ",   { Ev, CL } },
2536     { "rcrQ",   { Ev, CL } },
2537     { "shlQ",   { Ev, CL } },
2538     { "shrQ",   { Ev, CL } },
2539     { Bad_Opcode },
2540     { "sarQ",   { Ev, CL } },
2541   },
2542   /* REG_F6 */
2543   {
2544     { "testA",  { Eb, Ib } },
2545     { Bad_Opcode },
2546     { "notA",   { Eb } },
2547     { "negA",   { Eb } },
2548     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2549     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2550     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2551     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2552   },
2553   /* REG_F7 */
2554   {
2555     { "testQ",  { Ev, Iv } },
2556     { Bad_Opcode },
2557     { "notQ",   { Ev } },
2558     { "negQ",   { Ev } },
2559     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2560     { "imulQ",  { Ev } },
2561     { "divQ",   { Ev } },
2562     { "idivQ",  { Ev } },
2563   },
2564   /* REG_FE */
2565   {
2566     { "incA",   { Eb } },
2567     { "decA",   { Eb } },
2568   },
2569   /* REG_FF */
2570   {
2571     { "incQ",   { Ev } },
2572     { "decQ",   { Ev } },
2573     { "callT",  { indirEv } },
2574     { "JcallT", { indirEp } },
2575     { "jmpT",   { indirEv } },
2576     { "JjmpT",  { indirEp } },
2577     { "pushU",  { stackEv } },
2578     { Bad_Opcode },
2579   },
2580   /* REG_0F00 */
2581   {
2582     { "sldtD",  { Sv } },
2583     { "strD",   { Sv } },
2584     { "lldt",   { Ew } },
2585     { "ltr",    { Ew } },
2586     { "verr",   { Ew } },
2587     { "verw",   { Ew } },
2588     { Bad_Opcode },
2589     { Bad_Opcode },
2590   },
2591   /* REG_0F01 */
2592   {
2593     { MOD_TABLE (MOD_0F01_REG_0) },
2594     { MOD_TABLE (MOD_0F01_REG_1) },
2595     { MOD_TABLE (MOD_0F01_REG_2) },
2596     { MOD_TABLE (MOD_0F01_REG_3) },
2597     { "smswD",  { Sv } },
2598     { Bad_Opcode },
2599     { "lmsw",   { Ew } },
2600     { MOD_TABLE (MOD_0F01_REG_7) },
2601   },
2602   /* REG_0F0D */
2603   {
2604     { "prefetch",       { Eb } },
2605     { "prefetchw",      { Eb } },
2606   },
2607   /* REG_0F18 */
2608   {
2609     { MOD_TABLE (MOD_0F18_REG_0) },
2610     { MOD_TABLE (MOD_0F18_REG_1) },
2611     { MOD_TABLE (MOD_0F18_REG_2) },
2612     { MOD_TABLE (MOD_0F18_REG_3) },
2613   },
2614   /* REG_0F71 */
2615   {
2616     { Bad_Opcode },
2617     { Bad_Opcode },
2618     { MOD_TABLE (MOD_0F71_REG_2) },
2619     { Bad_Opcode },
2620     { MOD_TABLE (MOD_0F71_REG_4) },
2621     { Bad_Opcode },
2622     { MOD_TABLE (MOD_0F71_REG_6) },
2623   },
2624   /* REG_0F72 */
2625   {
2626     { Bad_Opcode },
2627     { Bad_Opcode },
2628     { MOD_TABLE (MOD_0F72_REG_2) },
2629     { Bad_Opcode },
2630     { MOD_TABLE (MOD_0F72_REG_4) },
2631     { Bad_Opcode },
2632     { MOD_TABLE (MOD_0F72_REG_6) },
2633   },
2634   /* REG_0F73 */
2635   {
2636     { Bad_Opcode },
2637     { Bad_Opcode },
2638     { MOD_TABLE (MOD_0F73_REG_2) },
2639     { MOD_TABLE (MOD_0F73_REG_3) },
2640     { Bad_Opcode },
2641     { Bad_Opcode },
2642     { MOD_TABLE (MOD_0F73_REG_6) },
2643     { MOD_TABLE (MOD_0F73_REG_7) },
2644   },
2645   /* REG_0FA6 */
2646   {
2647     { "montmul",        { { OP_0f07, 0 } } },
2648     { "xsha1",          { { OP_0f07, 0 } } },
2649     { "xsha256",        { { OP_0f07, 0 } } },
2650   },
2651   /* REG_0FA7 */
2652   {
2653     { "xstore-rng",     { { OP_0f07, 0 } } },
2654     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2655     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2656     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2657     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2658     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2659   },
2660   /* REG_0FAE */
2661   {
2662     { MOD_TABLE (MOD_0FAE_REG_0) },
2663     { MOD_TABLE (MOD_0FAE_REG_1) },
2664     { MOD_TABLE (MOD_0FAE_REG_2) },
2665     { MOD_TABLE (MOD_0FAE_REG_3) },
2666     { MOD_TABLE (MOD_0FAE_REG_4) },
2667     { MOD_TABLE (MOD_0FAE_REG_5) },
2668     { MOD_TABLE (MOD_0FAE_REG_6) },
2669     { MOD_TABLE (MOD_0FAE_REG_7) },
2670   },
2671   /* REG_0FBA */
2672   {
2673     { Bad_Opcode },
2674     { Bad_Opcode },
2675     { Bad_Opcode },
2676     { Bad_Opcode },
2677     { "btQ",    { Ev, Ib } },
2678     { "btsQ",   { Ev, Ib } },
2679     { "btrQ",   { Ev, Ib } },
2680     { "btcQ",   { Ev, Ib } },
2681   },
2682   /* REG_0FC7 */
2683   {
2684     { Bad_Opcode },
2685     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2686     { Bad_Opcode },
2687     { Bad_Opcode },
2688     { Bad_Opcode },
2689     { Bad_Opcode },
2690     { MOD_TABLE (MOD_0FC7_REG_6) },
2691     { MOD_TABLE (MOD_0FC7_REG_7) },
2692   },
2693   /* REG_VEX_71 */
2694   {
2695     { Bad_Opcode },
2696     { Bad_Opcode },
2697     { MOD_TABLE (MOD_VEX_71_REG_2) },
2698     { Bad_Opcode },
2699     { MOD_TABLE (MOD_VEX_71_REG_4) },
2700     { Bad_Opcode },
2701     { MOD_TABLE (MOD_VEX_71_REG_6) },
2702   },
2703   /* REG_VEX_72 */
2704   {
2705     { Bad_Opcode },
2706     { Bad_Opcode },
2707     { MOD_TABLE (MOD_VEX_72_REG_2) },
2708     { Bad_Opcode },
2709     { MOD_TABLE (MOD_VEX_72_REG_4) },
2710     { Bad_Opcode },
2711     { MOD_TABLE (MOD_VEX_72_REG_6) },
2712   },
2713   /* REG_VEX_73 */
2714   {
2715     { Bad_Opcode },
2716     { Bad_Opcode },
2717     { MOD_TABLE (MOD_VEX_73_REG_2) },
2718     { MOD_TABLE (MOD_VEX_73_REG_3) },
2719     { Bad_Opcode },
2720     { Bad_Opcode },
2721     { MOD_TABLE (MOD_VEX_73_REG_6) },
2722     { MOD_TABLE (MOD_VEX_73_REG_7) },
2723   },
2724   /* REG_VEX_AE */
2725   {
2726     { Bad_Opcode },
2727     { Bad_Opcode },
2728     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2729     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2730   },
2731   /* REG_XOP_LWPCB */
2732   {
2733     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2734     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2735   },
2736   /* REG_XOP_LWP */
2737   {
2738     { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2739     { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2740   },
2741 };
2742
2743 static const struct dis386 prefix_table[][4] = {
2744   /* PREFIX_90 */
2745   {
2746     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2747     { "pause", { XX } },
2748     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2749   },
2750
2751   /* PREFIX_0F10 */
2752   {
2753     { "movups", { XM, EXx } },
2754     { "movss",  { XM, EXd } },
2755     { "movupd", { XM, EXx } },
2756     { "movsd",  { XM, EXq } },
2757   },
2758
2759   /* PREFIX_0F11 */
2760   {
2761     { "movups", { EXxS, XM } },
2762     { "movss",  { EXdS, XM } },
2763     { "movupd", { EXxS, XM } },
2764     { "movsd",  { EXqS, XM } },
2765   },
2766
2767   /* PREFIX_0F12 */
2768   {
2769     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2770     { "movsldup", { XM, EXx } },
2771     { "movlpd", { XM, EXq } },
2772     { "movddup", { XM, EXq } },
2773   },
2774
2775   /* PREFIX_0F16 */
2776   {
2777     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2778     { "movshdup", { XM, EXx } },
2779     { "movhpd", { XM, EXq } },
2780   },
2781
2782   /* PREFIX_0F2A */
2783   {
2784     { "cvtpi2ps", { XM, EMCq } },
2785     { "cvtsi2ss%LQ", { XM, Ev } },
2786     { "cvtpi2pd", { XM, EMCq } },
2787     { "cvtsi2sd%LQ", { XM, Ev } },
2788   },
2789
2790   /* PREFIX_0F2B */
2791   {
2792     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2793     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2794     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2795     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2796   },
2797
2798   /* PREFIX_0F2C */
2799   {
2800     { "cvttps2pi", { MXC, EXq } },
2801     { "cvttss2siY", { Gv, EXd } },
2802     { "cvttpd2pi", { MXC, EXx } },
2803     { "cvttsd2siY", { Gv, EXq } },
2804   },
2805
2806   /* PREFIX_0F2D */
2807   {
2808     { "cvtps2pi", { MXC, EXq } },
2809     { "cvtss2siY", { Gv, EXd } },
2810     { "cvtpd2pi", { MXC, EXx } },
2811     { "cvtsd2siY", { Gv, EXq } },
2812   },
2813
2814   /* PREFIX_0F2E */
2815   {
2816     { "ucomiss",{ XM, EXd } },
2817     { Bad_Opcode },
2818     { "ucomisd",{ XM, EXq } },
2819   },
2820
2821   /* PREFIX_0F2F */
2822   {
2823     { "comiss", { XM, EXd } },
2824     { Bad_Opcode },
2825     { "comisd", { XM, EXq } },
2826   },
2827
2828   /* PREFIX_0F51 */
2829   {
2830     { "sqrtps", { XM, EXx } },
2831     { "sqrtss", { XM, EXd } },
2832     { "sqrtpd", { XM, EXx } },
2833     { "sqrtsd", { XM, EXq } },
2834   },
2835
2836   /* PREFIX_0F52 */
2837   {
2838     { "rsqrtps",{ XM, EXx } },
2839     { "rsqrtss",{ XM, EXd } },
2840   },
2841
2842   /* PREFIX_0F53 */
2843   {
2844     { "rcpps",  { XM, EXx } },
2845     { "rcpss",  { XM, EXd } },
2846   },
2847
2848   /* PREFIX_0F58 */
2849   {
2850     { "addps", { XM, EXx } },
2851     { "addss", { XM, EXd } },
2852     { "addpd", { XM, EXx } },
2853     { "addsd", { XM, EXq } },
2854   },
2855
2856   /* PREFIX_0F59 */
2857   {
2858     { "mulps",  { XM, EXx } },
2859     { "mulss",  { XM, EXd } },
2860     { "mulpd",  { XM, EXx } },
2861     { "mulsd",  { XM, EXq } },
2862   },
2863
2864   /* PREFIX_0F5A */
2865   {
2866     { "cvtps2pd", { XM, EXq } },
2867     { "cvtss2sd", { XM, EXd } },
2868     { "cvtpd2ps", { XM, EXx } },
2869     { "cvtsd2ss", { XM, EXq } },
2870   },
2871
2872   /* PREFIX_0F5B */
2873   {
2874     { "cvtdq2ps", { XM, EXx } },
2875     { "cvttps2dq", { XM, EXx } },
2876     { "cvtps2dq", { XM, EXx } },
2877   },
2878
2879   /* PREFIX_0F5C */
2880   {
2881     { "subps",  { XM, EXx } },
2882     { "subss",  { XM, EXd } },
2883     { "subpd",  { XM, EXx } },
2884     { "subsd",  { XM, EXq } },
2885   },
2886
2887   /* PREFIX_0F5D */
2888   {
2889     { "minps",  { XM, EXx } },
2890     { "minss",  { XM, EXd } },
2891     { "minpd",  { XM, EXx } },
2892     { "minsd",  { XM, EXq } },
2893   },
2894
2895   /* PREFIX_0F5E */
2896   {
2897     { "divps",  { XM, EXx } },
2898     { "divss",  { XM, EXd } },
2899     { "divpd",  { XM, EXx } },
2900     { "divsd",  { XM, EXq } },
2901   },
2902
2903   /* PREFIX_0F5F */
2904   {
2905     { "maxps",  { XM, EXx } },
2906     { "maxss",  { XM, EXd } },
2907     { "maxpd",  { XM, EXx } },
2908     { "maxsd",  { XM, EXq } },
2909   },
2910
2911   /* PREFIX_0F60 */
2912   {
2913     { "punpcklbw",{ MX, EMd } },
2914     { Bad_Opcode },
2915     { "punpcklbw",{ MX, EMx } },
2916   },
2917
2918   /* PREFIX_0F61 */
2919   {
2920     { "punpcklwd",{ MX, EMd } },
2921     { Bad_Opcode },
2922     { "punpcklwd",{ MX, EMx } },
2923   },
2924
2925   /* PREFIX_0F62 */
2926   {
2927     { "punpckldq",{ MX, EMd } },
2928     { Bad_Opcode },
2929     { "punpckldq",{ MX, EMx } },
2930   },
2931
2932   /* PREFIX_0F6C */
2933   {
2934     { Bad_Opcode },
2935     { Bad_Opcode },
2936     { "punpcklqdq", { XM, EXx } },
2937   },
2938
2939   /* PREFIX_0F6D */
2940   {
2941     { Bad_Opcode },
2942     { Bad_Opcode },
2943     { "punpckhqdq", { XM, EXx } },
2944   },
2945
2946   /* PREFIX_0F6F */
2947   {
2948     { "movq",   { MX, EM } },
2949     { "movdqu", { XM, EXx } },
2950     { "movdqa", { XM, EXx } },
2951   },
2952
2953   /* PREFIX_0F70 */
2954   {
2955     { "pshufw", { MX, EM, Ib } },
2956     { "pshufhw",{ XM, EXx, Ib } },
2957     { "pshufd", { XM, EXx, Ib } },
2958     { "pshuflw",{ XM, EXx, Ib } },
2959   },
2960
2961   /* PREFIX_0F73_REG_3 */
2962   {
2963     { Bad_Opcode },
2964     { Bad_Opcode },
2965     { "psrldq", { XS, Ib } },
2966   },
2967
2968   /* PREFIX_0F73_REG_7 */
2969   {
2970     { Bad_Opcode },
2971     { Bad_Opcode },
2972     { "pslldq", { XS, Ib } },
2973   },
2974
2975   /* PREFIX_0F78 */
2976   {
2977     {"vmread",  { Em, Gm } },
2978     { Bad_Opcode },
2979     {"extrq",   { XS, Ib, Ib } },
2980     {"insertq", { XM, XS, Ib, Ib } },
2981   },
2982
2983   /* PREFIX_0F79 */
2984   {
2985     {"vmwrite", { Gm, Em } },
2986     { Bad_Opcode },
2987     {"extrq",   { XM, XS } },
2988     {"insertq", { XM, XS } },
2989   },
2990
2991   /* PREFIX_0F7C */
2992   {
2993     { Bad_Opcode },
2994     { Bad_Opcode },
2995     { "haddpd", { XM, EXx } },
2996     { "haddps", { XM, EXx } },
2997   },
2998
2999   /* PREFIX_0F7D */
3000   {
3001     { Bad_Opcode },
3002     { Bad_Opcode },
3003     { "hsubpd", { XM, EXx } },
3004     { "hsubps", { XM, EXx } },
3005   },
3006
3007   /* PREFIX_0F7E */
3008   {
3009     { "movK",   { Edq, MX } },
3010     { "movq",   { XM, EXq } },
3011     { "movK",   { Edq, XM } },
3012   },
3013
3014   /* PREFIX_0F7F */
3015   {
3016     { "movq",   { EMS, MX } },
3017     { "movdqu", { EXxS, XM } },
3018     { "movdqa", { EXxS, XM } },
3019   },
3020
3021   /* PREFIX_0FB8 */
3022   {
3023     { Bad_Opcode },
3024     { "popcntS", { Gv, Ev } },
3025   },
3026
3027   /* PREFIX_0FBD */
3028   {
3029     { "bsrS",   { Gv, Ev } },
3030     { "lzcntS", { Gv, Ev } },
3031     { "bsrS",   { Gv, Ev } },
3032   },
3033
3034   /* PREFIX_0FC2 */
3035   {
3036     { "cmpps",  { XM, EXx, CMP } },
3037     { "cmpss",  { XM, EXd, CMP } },
3038     { "cmppd",  { XM, EXx, CMP } },
3039     { "cmpsd",  { XM, EXq, CMP } },
3040   },
3041
3042   /* PREFIX_0FC3 */
3043   {
3044     { "movntiS", { Ma, Gv } },
3045   },
3046
3047   /* PREFIX_0FC7_REG_6 */
3048   {
3049     { "vmptrld",{ Mq } },
3050     { "vmxon",  { Mq } },
3051     { "vmclear",{ Mq } },
3052   },
3053
3054   /* PREFIX_0FD0 */
3055   {
3056     { Bad_Opcode },
3057     { Bad_Opcode },
3058     { "addsubpd", { XM, EXx } },
3059     { "addsubps", { XM, EXx } },
3060   },
3061
3062   /* PREFIX_0FD6 */
3063   {
3064     { Bad_Opcode },
3065     { "movq2dq",{ XM, MS } },
3066     { "movq",   { EXqS, XM } },
3067     { "movdq2q",{ MX, XS } },
3068   },
3069
3070   /* PREFIX_0FE6 */
3071   {
3072     { Bad_Opcode },
3073     { "cvtdq2pd", { XM, EXq } },
3074     { "cvttpd2dq", { XM, EXx } },
3075     { "cvtpd2dq", { XM, EXx } },
3076   },
3077
3078   /* PREFIX_0FE7 */
3079   {
3080     { "movntq", { Mq, MX } },
3081     { Bad_Opcode },
3082     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3083   },
3084
3085   /* PREFIX_0FF0 */
3086   {
3087     { Bad_Opcode },
3088     { Bad_Opcode },
3089     { Bad_Opcode },
3090     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3091   },
3092
3093   /* PREFIX_0FF7 */
3094   {
3095     { "maskmovq", { MX, MS } },
3096     { Bad_Opcode },
3097     { "maskmovdqu", { XM, XS } },
3098   },
3099
3100   /* PREFIX_0F3810 */
3101   {
3102     { Bad_Opcode },
3103     { Bad_Opcode },
3104     { "pblendvb", { XM, EXx, XMM0 } },
3105   },
3106
3107   /* PREFIX_0F3814 */
3108   {
3109     { Bad_Opcode },
3110     { Bad_Opcode },
3111     { "blendvps", { XM, EXx, XMM0 } },
3112   },
3113
3114   /* PREFIX_0F3815 */
3115   {
3116     { Bad_Opcode },
3117     { Bad_Opcode },
3118     { "blendvpd", { XM, EXx, XMM0 } },
3119   },
3120
3121   /* PREFIX_0F3817 */
3122   {
3123     { Bad_Opcode },
3124     { Bad_Opcode },
3125     { "ptest",  { XM, EXx } },
3126   },
3127
3128   /* PREFIX_0F3820 */
3129   {
3130     { Bad_Opcode },
3131     { Bad_Opcode },
3132     { "pmovsxbw", { XM, EXq } },
3133   },
3134
3135   /* PREFIX_0F3821 */
3136   {
3137     { Bad_Opcode },
3138     { Bad_Opcode },
3139     { "pmovsxbd", { XM, EXd } },
3140   },
3141
3142   /* PREFIX_0F3822 */
3143   {
3144     { Bad_Opcode },
3145     { Bad_Opcode },
3146     { "pmovsxbq", { XM, EXw } },
3147   },
3148
3149   /* PREFIX_0F3823 */
3150   {
3151     { Bad_Opcode },
3152     { Bad_Opcode },
3153     { "pmovsxwd", { XM, EXq } },
3154   },
3155
3156   /* PREFIX_0F3824 */
3157   {
3158     { Bad_Opcode },
3159     { Bad_Opcode },
3160     { "pmovsxwq", { XM, EXd } },
3161   },
3162
3163   /* PREFIX_0F3825 */
3164   {
3165     { Bad_Opcode },
3166     { Bad_Opcode },
3167     { "pmovsxdq", { XM, EXq } },
3168   },
3169
3170   /* PREFIX_0F3828 */
3171   {
3172     { Bad_Opcode },
3173     { Bad_Opcode },
3174     { "pmuldq", { XM, EXx } },
3175   },
3176
3177   /* PREFIX_0F3829 */
3178   {
3179     { Bad_Opcode },
3180     { Bad_Opcode },
3181     { "pcmpeqq", { XM, EXx } },
3182   },
3183
3184   /* PREFIX_0F382A */
3185   {
3186     { Bad_Opcode },
3187     { Bad_Opcode },
3188     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3189   },
3190
3191   /* PREFIX_0F382B */
3192   {
3193     { Bad_Opcode },
3194     { Bad_Opcode },
3195     { "packusdw", { XM, EXx } },
3196   },
3197
3198   /* PREFIX_0F3830 */
3199   {
3200     { Bad_Opcode },
3201     { Bad_Opcode },
3202     { "pmovzxbw", { XM, EXq } },
3203   },
3204
3205   /* PREFIX_0F3831 */
3206   {
3207     { Bad_Opcode },
3208     { Bad_Opcode },
3209     { "pmovzxbd", { XM, EXd } },
3210   },
3211
3212   /* PREFIX_0F3832 */
3213   {
3214     { Bad_Opcode },
3215     { Bad_Opcode },
3216     { "pmovzxbq", { XM, EXw } },
3217   },
3218
3219   /* PREFIX_0F3833 */
3220   {
3221     { Bad_Opcode },
3222     { Bad_Opcode },
3223     { "pmovzxwd", { XM, EXq } },
3224   },
3225
3226   /* PREFIX_0F3834 */
3227   {
3228     { Bad_Opcode },
3229     { Bad_Opcode },
3230     { "pmovzxwq", { XM, EXd } },
3231   },
3232
3233   /* PREFIX_0F3835 */
3234   {
3235     { Bad_Opcode },
3236     { Bad_Opcode },
3237     { "pmovzxdq", { XM, EXq } },
3238   },
3239
3240   /* PREFIX_0F3837 */
3241   {
3242     { Bad_Opcode },
3243     { Bad_Opcode },
3244     { "pcmpgtq", { XM, EXx } },
3245   },
3246
3247   /* PREFIX_0F3838 */
3248   {
3249     { Bad_Opcode },
3250     { Bad_Opcode },
3251     { "pminsb", { XM, EXx } },
3252   },
3253
3254   /* PREFIX_0F3839 */
3255   {
3256     { Bad_Opcode },
3257     { Bad_Opcode },
3258     { "pminsd", { XM, EXx } },
3259   },
3260
3261   /* PREFIX_0F383A */
3262   {
3263     { Bad_Opcode },
3264     { Bad_Opcode },
3265     { "pminuw", { XM, EXx } },
3266   },
3267
3268   /* PREFIX_0F383B */
3269   {
3270     { Bad_Opcode },
3271     { Bad_Opcode },
3272     { "pminud", { XM, EXx } },
3273   },
3274
3275   /* PREFIX_0F383C */
3276   {
3277     { Bad_Opcode },
3278     { Bad_Opcode },
3279     { "pmaxsb", { XM, EXx } },
3280   },
3281
3282   /* PREFIX_0F383D */
3283   {
3284     { Bad_Opcode },
3285     { Bad_Opcode },
3286     { "pmaxsd", { XM, EXx } },
3287   },
3288
3289   /* PREFIX_0F383E */
3290   {
3291     { Bad_Opcode },
3292     { Bad_Opcode },
3293     { "pmaxuw", { XM, EXx } },
3294   },
3295
3296   /* PREFIX_0F383F */
3297   {
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { "pmaxud", { XM, EXx } },
3301   },
3302
3303   /* PREFIX_0F3840 */
3304   {
3305     { Bad_Opcode },
3306     { Bad_Opcode },
3307     { "pmulld", { XM, EXx } },
3308   },
3309
3310   /* PREFIX_0F3841 */
3311   {
3312     { Bad_Opcode },
3313     { Bad_Opcode },
3314     { "phminposuw", { XM, EXx } },
3315   },
3316
3317   /* PREFIX_0F3880 */
3318   {
3319     { Bad_Opcode },
3320     { Bad_Opcode },
3321     { "invept", { Gm, Mo } },
3322   },
3323
3324   /* PREFIX_0F3881 */
3325   {
3326     { Bad_Opcode },
3327     { Bad_Opcode },
3328     { "invvpid", { Gm, Mo } },
3329   },
3330
3331   /* PREFIX_0F38DB */
3332   {
3333     { Bad_Opcode },
3334     { Bad_Opcode },
3335     { "aesimc", { XM, EXx } },
3336   },
3337
3338   /* PREFIX_0F38DC */
3339   {
3340     { Bad_Opcode },
3341     { Bad_Opcode },
3342     { "aesenc", { XM, EXx } },
3343   },
3344
3345   /* PREFIX_0F38DD */
3346   {
3347     { Bad_Opcode },
3348     { Bad_Opcode },
3349     { "aesenclast", { XM, EXx } },
3350   },
3351
3352   /* PREFIX_0F38DE */
3353   {
3354     { Bad_Opcode },
3355     { Bad_Opcode },
3356     { "aesdec", { XM, EXx } },
3357   },
3358
3359   /* PREFIX_0F38DF */
3360   {
3361     { Bad_Opcode },
3362     { Bad_Opcode },
3363     { "aesdeclast", { XM, EXx } },
3364   },
3365
3366   /* PREFIX_0F38F0 */
3367   {
3368     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3369     { Bad_Opcode },
3370     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3371     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3372   },
3373
3374   /* PREFIX_0F38F1 */
3375   {
3376     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3377     { Bad_Opcode },
3378     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3379     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3380   },
3381
3382   /* PREFIX_0F3A08 */
3383   {
3384     { Bad_Opcode },
3385     { Bad_Opcode },
3386     { "roundps", { XM, EXx, Ib } },
3387   },
3388
3389   /* PREFIX_0F3A09 */
3390   {
3391     { Bad_Opcode },
3392     { Bad_Opcode },
3393     { "roundpd", { XM, EXx, Ib } },
3394   },
3395
3396   /* PREFIX_0F3A0A */
3397   {
3398     { Bad_Opcode },
3399     { Bad_Opcode },
3400     { "roundss", { XM, EXd, Ib } },
3401   },
3402
3403   /* PREFIX_0F3A0B */
3404   {
3405     { Bad_Opcode },
3406     { Bad_Opcode },
3407     { "roundsd", { XM, EXq, Ib } },
3408   },
3409
3410   /* PREFIX_0F3A0C */
3411   {
3412     { Bad_Opcode },
3413     { Bad_Opcode },
3414     { "blendps", { XM, EXx, Ib } },
3415   },
3416
3417   /* PREFIX_0F3A0D */
3418   {
3419     { Bad_Opcode },
3420     { Bad_Opcode },
3421     { "blendpd", { XM, EXx, Ib } },
3422   },
3423
3424   /* PREFIX_0F3A0E */
3425   {
3426     { Bad_Opcode },
3427     { Bad_Opcode },
3428     { "pblendw", { XM, EXx, Ib } },
3429   },
3430
3431   /* PREFIX_0F3A14 */
3432   {
3433     { Bad_Opcode },
3434     { Bad_Opcode },
3435     { "pextrb", { Edqb, XM, Ib } },
3436   },
3437
3438   /* PREFIX_0F3A15 */
3439   {
3440     { Bad_Opcode },
3441     { Bad_Opcode },
3442     { "pextrw", { Edqw, XM, Ib } },
3443   },
3444
3445   /* PREFIX_0F3A16 */
3446   {
3447     { Bad_Opcode },
3448     { Bad_Opcode },
3449     { "pextrK", { Edq, XM, Ib } },
3450   },
3451
3452   /* PREFIX_0F3A17 */
3453   {
3454     { Bad_Opcode },
3455     { Bad_Opcode },
3456     { "extractps", { Edqd, XM, Ib } },
3457   },
3458
3459   /* PREFIX_0F3A20 */
3460   {
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { "pinsrb", { XM, Edqb, Ib } },
3464   },
3465
3466   /* PREFIX_0F3A21 */
3467   {
3468     { Bad_Opcode },
3469     { Bad_Opcode },
3470     { "insertps", { XM, EXd, Ib } },
3471   },
3472
3473   /* PREFIX_0F3A22 */
3474   {
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { "pinsrK", { XM, Edq, Ib } },
3478   },
3479
3480   /* PREFIX_0F3A40 */
3481   {
3482     { Bad_Opcode },
3483     { Bad_Opcode },
3484     { "dpps",   { XM, EXx, Ib } },
3485   },
3486
3487   /* PREFIX_0F3A41 */
3488   {
3489     { Bad_Opcode },
3490     { Bad_Opcode },
3491     { "dppd",   { XM, EXx, Ib } },
3492   },
3493
3494   /* PREFIX_0F3A42 */
3495   {
3496     { Bad_Opcode },
3497     { Bad_Opcode },
3498     { "mpsadbw", { XM, EXx, Ib } },
3499   },
3500
3501   /* PREFIX_0F3A44 */
3502   {
3503     { Bad_Opcode },
3504     { Bad_Opcode },
3505     { "pclmulqdq", { XM, EXx, PCLMUL } },
3506   },
3507
3508   /* PREFIX_0F3A60 */
3509   {
3510     { Bad_Opcode },
3511     { Bad_Opcode },
3512     { "pcmpestrm", { XM, EXx, Ib } },
3513   },
3514
3515   /* PREFIX_0F3A61 */
3516   {
3517     { Bad_Opcode },
3518     { Bad_Opcode },
3519     { "pcmpestri", { XM, EXx, Ib } },
3520   },
3521
3522   /* PREFIX_0F3A62 */
3523   {
3524     { Bad_Opcode },
3525     { Bad_Opcode },
3526     { "pcmpistrm", { XM, EXx, Ib } },
3527   },
3528
3529   /* PREFIX_0F3A63 */
3530   {
3531     { Bad_Opcode },
3532     { Bad_Opcode },
3533     { "pcmpistri", { XM, EXx, Ib } },
3534   },
3535
3536   /* PREFIX_0F3ADF */
3537   {
3538     { Bad_Opcode },
3539     { Bad_Opcode },
3540     { "aeskeygenassist", { XM, EXx, Ib } },
3541   },
3542
3543   /* PREFIX_VEX_10 */
3544   {
3545     { VEX_W_TABLE (VEX_W_10_P_0) },
3546     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3547     { VEX_W_TABLE (VEX_W_10_P_2) },
3548     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3549   },
3550
3551   /* PREFIX_VEX_11 */
3552   {
3553     { VEX_W_TABLE (VEX_W_11_P_0) },
3554     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3555     { VEX_W_TABLE (VEX_W_11_P_2) },
3556     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3557   },
3558
3559   /* PREFIX_VEX_12 */
3560   {
3561     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3562     { VEX_W_TABLE (VEX_W_12_P_1) },
3563     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3564     { VEX_W_TABLE (VEX_W_12_P_3) },
3565   },
3566
3567   /* PREFIX_VEX_16 */
3568   {
3569     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3570     { VEX_W_TABLE (VEX_W_16_P_1) },
3571     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3572   },
3573
3574   /* PREFIX_VEX_2A */
3575   {
3576     { Bad_Opcode },
3577     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3578     { Bad_Opcode },
3579     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3580   },
3581
3582   /* PREFIX_VEX_2C */
3583   {
3584     { Bad_Opcode },
3585     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3586     { Bad_Opcode },
3587     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3588   },
3589
3590   /* PREFIX_VEX_2D */
3591   {
3592     { Bad_Opcode },
3593     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3594     { Bad_Opcode },
3595     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3596   },
3597
3598   /* PREFIX_VEX_2E */
3599   {
3600     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3601     { Bad_Opcode },
3602     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3603   },
3604
3605   /* PREFIX_VEX_2F */
3606   {
3607     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3608     { Bad_Opcode },
3609     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3610   },
3611
3612   /* PREFIX_VEX_51 */
3613   {
3614     { VEX_W_TABLE (VEX_W_51_P_0) },
3615     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3616     { VEX_W_TABLE (VEX_W_51_P_2) },
3617     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3618   },
3619
3620   /* PREFIX_VEX_52 */
3621   {
3622     { VEX_W_TABLE (VEX_W_52_P_0) },
3623     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3624   },
3625
3626   /* PREFIX_VEX_53 */
3627   {
3628     { VEX_W_TABLE (VEX_W_53_P_0) },
3629     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3630   },
3631
3632   /* PREFIX_VEX_58 */
3633   {
3634     { VEX_W_TABLE (VEX_W_58_P_0) },
3635     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3636     { VEX_W_TABLE (VEX_W_58_P_2) },
3637     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3638   },
3639
3640   /* PREFIX_VEX_59 */
3641   {
3642     { VEX_W_TABLE (VEX_W_59_P_0) },
3643     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3644     { VEX_W_TABLE (VEX_W_59_P_2) },
3645     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3646   },
3647
3648   /* PREFIX_VEX_5A */
3649   {
3650     { VEX_W_TABLE (VEX_W_5A_P_0) },
3651     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3652     { "vcvtpd2ps%XY", { XMM, EXx } },
3653     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3654   },
3655
3656   /* PREFIX_VEX_5B */
3657   {
3658     { VEX_W_TABLE (VEX_W_5B_P_0) },
3659     { VEX_W_TABLE (VEX_W_5B_P_1) },
3660     { VEX_W_TABLE (VEX_W_5B_P_2) },
3661   },
3662
3663   /* PREFIX_VEX_5C */
3664   {
3665     { VEX_W_TABLE (VEX_W_5C_P_0) },
3666     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3667     { VEX_W_TABLE (VEX_W_5C_P_2) },
3668     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3669   },
3670
3671   /* PREFIX_VEX_5D */
3672   {
3673     { VEX_W_TABLE (VEX_W_5D_P_0) },
3674     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3675     { VEX_W_TABLE (VEX_W_5D_P_2) },
3676     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3677   },
3678
3679   /* PREFIX_VEX_5E */
3680   {
3681     { VEX_W_TABLE (VEX_W_5E_P_0) },
3682     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3683     { VEX_W_TABLE (VEX_W_5E_P_2) },
3684     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3685   },
3686
3687   /* PREFIX_VEX_5F */
3688   {
3689     { VEX_W_TABLE (VEX_W_5F_P_0) },
3690     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3691     { VEX_W_TABLE (VEX_W_5F_P_2) },
3692     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3693   },
3694
3695   /* PREFIX_VEX_60 */
3696   {
3697     { Bad_Opcode },
3698     { Bad_Opcode },
3699     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3700   },
3701
3702   /* PREFIX_VEX_61 */
3703   {
3704     { Bad_Opcode },
3705     { Bad_Opcode },
3706     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3707   },
3708
3709   /* PREFIX_VEX_62 */
3710   {
3711     { Bad_Opcode },
3712     { Bad_Opcode },
3713     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3714   },
3715
3716   /* PREFIX_VEX_63 */
3717   {
3718     { Bad_Opcode },
3719     { Bad_Opcode },
3720     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3721   },
3722
3723   /* PREFIX_VEX_64 */
3724   {
3725     { Bad_Opcode },
3726     { Bad_Opcode },
3727     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3728   },
3729
3730   /* PREFIX_VEX_65 */
3731   {
3732     { Bad_Opcode },
3733     { Bad_Opcode },
3734     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3735   },
3736
3737   /* PREFIX_VEX_66 */
3738   {
3739     { Bad_Opcode },
3740     { Bad_Opcode },
3741     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3742   },
3743
3744   /* PREFIX_VEX_67 */
3745   {
3746     { Bad_Opcode },
3747     { Bad_Opcode },
3748     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3749   },
3750
3751   /* PREFIX_VEX_68 */
3752   {
3753     { Bad_Opcode },
3754     { Bad_Opcode },
3755     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3756   },
3757
3758   /* PREFIX_VEX_69 */
3759   {
3760     { Bad_Opcode },
3761     { Bad_Opcode },
3762     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3763   },
3764
3765   /* PREFIX_VEX_6A */
3766   {
3767     { Bad_Opcode },
3768     { Bad_Opcode },
3769     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3770   },
3771
3772   /* PREFIX_VEX_6B */
3773   {
3774     { Bad_Opcode },
3775     { Bad_Opcode },
3776     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3777   },
3778
3779   /* PREFIX_VEX_6C */
3780   {
3781     { Bad_Opcode },
3782     { Bad_Opcode },
3783     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3784   },
3785
3786   /* PREFIX_VEX_6D */
3787   {
3788     { Bad_Opcode },
3789     { Bad_Opcode },
3790     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3791   },
3792
3793   /* PREFIX_VEX_6E */
3794   {
3795     { Bad_Opcode },
3796     { Bad_Opcode },
3797     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3798   },
3799
3800   /* PREFIX_VEX_6F */
3801   {
3802     { Bad_Opcode },
3803     { VEX_W_TABLE (VEX_W_6F_P_1) },
3804     { VEX_W_TABLE (VEX_W_6F_P_2) },
3805   },
3806
3807   /* PREFIX_VEX_70 */
3808   {
3809     { Bad_Opcode },
3810     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3811     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3812     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3813   },
3814
3815   /* PREFIX_VEX_71_REG_2 */
3816   {
3817     { Bad_Opcode },
3818     { Bad_Opcode },
3819     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3820   },
3821
3822   /* PREFIX_VEX_71_REG_4 */
3823   {
3824     { Bad_Opcode },
3825     { Bad_Opcode },
3826     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3827   },
3828
3829   /* PREFIX_VEX_71_REG_6 */
3830   {
3831     { Bad_Opcode },
3832     { Bad_Opcode },
3833     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3834   },
3835
3836   /* PREFIX_VEX_72_REG_2 */
3837   {
3838     { Bad_Opcode },
3839     { Bad_Opcode },
3840     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3841   },
3842
3843   /* PREFIX_VEX_72_REG_4 */
3844   {
3845     { Bad_Opcode },
3846     { Bad_Opcode },
3847     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3848   },
3849
3850   /* PREFIX_VEX_72_REG_6 */
3851   {
3852     { Bad_Opcode },
3853     { Bad_Opcode },
3854     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3855   },
3856
3857   /* PREFIX_VEX_73_REG_2 */
3858   {
3859     { Bad_Opcode },
3860     { Bad_Opcode },
3861     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3862   },
3863
3864   /* PREFIX_VEX_73_REG_3 */
3865   {
3866     { Bad_Opcode },
3867     { Bad_Opcode },
3868     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3869   },
3870
3871   /* PREFIX_VEX_73_REG_6 */
3872   {
3873     { Bad_Opcode },
3874     { Bad_Opcode },
3875     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3876   },
3877
3878   /* PREFIX_VEX_73_REG_7 */
3879   {
3880     { Bad_Opcode },
3881     { Bad_Opcode },
3882     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3883   },
3884
3885   /* PREFIX_VEX_74 */
3886   {
3887     { Bad_Opcode },
3888     { Bad_Opcode },
3889     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3890   },
3891
3892   /* PREFIX_VEX_75 */
3893   {
3894     { Bad_Opcode },
3895     { Bad_Opcode },
3896     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3897   },
3898
3899   /* PREFIX_VEX_76 */
3900   {
3901     { Bad_Opcode },
3902     { Bad_Opcode },
3903     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3904   },
3905
3906   /* PREFIX_VEX_77 */
3907   {
3908     { VEX_W_TABLE (VEX_W_77_P_0) },
3909   },
3910
3911   /* PREFIX_VEX_7C */
3912   {
3913     { Bad_Opcode },
3914     { Bad_Opcode },
3915     { VEX_W_TABLE (VEX_W_7C_P_2) },
3916     { VEX_W_TABLE (VEX_W_7C_P_3) },
3917   },
3918
3919   /* PREFIX_VEX_7D */
3920   {
3921     { Bad_Opcode },
3922     { Bad_Opcode },
3923     { VEX_W_TABLE (VEX_W_7D_P_2) },
3924     { VEX_W_TABLE (VEX_W_7D_P_3) },
3925   },
3926
3927   /* PREFIX_VEX_7E */
3928   {
3929     { Bad_Opcode },
3930     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3931     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3932   },
3933
3934   /* PREFIX_VEX_7F */
3935   {
3936     { Bad_Opcode },
3937     { VEX_W_TABLE (VEX_W_7F_P_1) },
3938     { VEX_W_TABLE (VEX_W_7F_P_2) },
3939   },
3940
3941   /* PREFIX_VEX_C2 */
3942   {
3943     { VEX_W_TABLE (VEX_W_C2_P_0) },
3944     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3945     { VEX_W_TABLE (VEX_W_C2_P_2) },
3946     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3947   },
3948
3949   /* PREFIX_VEX_C4 */
3950   {
3951     { Bad_Opcode },
3952     { Bad_Opcode },
3953     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3954   },
3955
3956   /* PREFIX_VEX_C5 */
3957   {
3958     { Bad_Opcode },
3959     { Bad_Opcode },
3960     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3961   },
3962
3963   /* PREFIX_VEX_D0 */
3964   {
3965     { Bad_Opcode },
3966     { Bad_Opcode },
3967     { VEX_W_TABLE (VEX_W_D0_P_2) },
3968     { VEX_W_TABLE (VEX_W_D0_P_3) },
3969   },
3970
3971   /* PREFIX_VEX_D1 */
3972   {
3973     { Bad_Opcode },
3974     { Bad_Opcode },
3975     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3976   },
3977
3978   /* PREFIX_VEX_D2 */
3979   {
3980     { Bad_Opcode },
3981     { Bad_Opcode },
3982     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3983   },
3984
3985   /* PREFIX_VEX_D3 */
3986   {
3987     { Bad_Opcode },
3988     { Bad_Opcode },
3989     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3990   },
3991
3992   /* PREFIX_VEX_D4 */
3993   {
3994     { Bad_Opcode },
3995     { Bad_Opcode },
3996     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3997   },
3998
3999   /* PREFIX_VEX_D5 */
4000   {
4001     { Bad_Opcode },
4002     { Bad_Opcode },
4003     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
4004   },
4005
4006   /* PREFIX_VEX_D6 */
4007   {
4008     { Bad_Opcode },
4009     { Bad_Opcode },
4010     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
4011   },
4012
4013   /* PREFIX_VEX_D7 */
4014   {
4015     { Bad_Opcode },
4016     { Bad_Opcode },
4017     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
4018   },
4019
4020   /* PREFIX_VEX_D8 */
4021   {
4022     { Bad_Opcode },
4023     { Bad_Opcode },
4024     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
4025   },
4026
4027   /* PREFIX_VEX_D9 */
4028   {
4029     { Bad_Opcode },
4030     { Bad_Opcode },
4031     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
4032   },
4033
4034   /* PREFIX_VEX_DA */
4035   {
4036     { Bad_Opcode },
4037     { Bad_Opcode },
4038     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
4039   },
4040
4041   /* PREFIX_VEX_DB */
4042   {
4043     { Bad_Opcode },
4044     { Bad_Opcode },
4045     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
4046   },
4047
4048   /* PREFIX_VEX_DC */
4049   {
4050     { Bad_Opcode },
4051     { Bad_Opcode },
4052     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
4053   },
4054
4055   /* PREFIX_VEX_DD */
4056   {
4057     { Bad_Opcode },
4058     { Bad_Opcode },
4059     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
4060   },
4061
4062   /* PREFIX_VEX_DE */
4063   {
4064     { Bad_Opcode },
4065     { Bad_Opcode },
4066     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
4067   },
4068
4069   /* PREFIX_VEX_DF */
4070   {
4071     { Bad_Opcode },
4072     { Bad_Opcode },
4073     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
4074   },
4075
4076   /* PREFIX_VEX_E0 */
4077   {
4078     { Bad_Opcode },
4079     { Bad_Opcode },
4080     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
4081   },
4082
4083   /* PREFIX_VEX_E1 */
4084   {
4085     { Bad_Opcode },
4086     { Bad_Opcode },
4087     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
4088   },
4089
4090   /* PREFIX_VEX_E2 */
4091   {
4092     { Bad_Opcode },
4093     { Bad_Opcode },
4094     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
4095   },
4096
4097   /* PREFIX_VEX_E3 */
4098   {
4099     { Bad_Opcode },
4100     { Bad_Opcode },
4101     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
4102   },
4103
4104   /* PREFIX_VEX_E4 */
4105   {
4106     { Bad_Opcode },
4107     { Bad_Opcode },
4108     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
4109   },
4110
4111   /* PREFIX_VEX_E5 */
4112   {
4113     { Bad_Opcode },
4114     { Bad_Opcode },
4115     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4116   },
4117
4118   /* PREFIX_VEX_E6 */
4119   {
4120     { Bad_Opcode },
4121     { VEX_W_TABLE (VEX_W_E6_P_1) },
4122     { VEX_W_TABLE (VEX_W_E6_P_2) },
4123     { VEX_W_TABLE (VEX_W_E6_P_3) },
4124   },
4125
4126   /* PREFIX_VEX_E7 */
4127   {
4128     { Bad_Opcode },
4129     { Bad_Opcode },
4130     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4131   },
4132
4133   /* PREFIX_VEX_E8 */
4134   {
4135     { Bad_Opcode },
4136     { Bad_Opcode },
4137     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4138   },
4139
4140   /* PREFIX_VEX_E9 */
4141   {
4142     { Bad_Opcode },
4143     { Bad_Opcode },
4144     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4145   },
4146
4147   /* PREFIX_VEX_EA */
4148   {
4149     { Bad_Opcode },
4150     { Bad_Opcode },
4151     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4152   },
4153
4154   /* PREFIX_VEX_EB */
4155   {
4156     { Bad_Opcode },
4157     { Bad_Opcode },
4158     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4159   },
4160
4161   /* PREFIX_VEX_EC */
4162   {
4163     { Bad_Opcode },
4164     { Bad_Opcode },
4165     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4166   },
4167
4168   /* PREFIX_VEX_ED */
4169   {
4170     { Bad_Opcode },
4171     { Bad_Opcode },
4172     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4173   },
4174
4175   /* PREFIX_VEX_EE */
4176   {
4177     { Bad_Opcode },
4178     { Bad_Opcode },
4179     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4180   },
4181
4182   /* PREFIX_VEX_EF */
4183   {
4184     { Bad_Opcode },
4185     { Bad_Opcode },
4186     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4187   },
4188
4189   /* PREFIX_VEX_F0 */
4190   {
4191     { Bad_Opcode },
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4195   },
4196
4197   /* PREFIX_VEX_F1 */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4202   },
4203
4204   /* PREFIX_VEX_F2 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4209   },
4210
4211   /* PREFIX_VEX_F3 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4216   },
4217
4218   /* PREFIX_VEX_F4 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4223   },
4224
4225   /* PREFIX_VEX_F5 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4230   },
4231
4232   /* PREFIX_VEX_F6 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4237   },
4238
4239   /* PREFIX_VEX_F7 */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4244   },
4245
4246   /* PREFIX_VEX_F8 */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4251   },
4252
4253   /* PREFIX_VEX_F9 */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4258   },
4259
4260   /* PREFIX_VEX_FA */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4265   },
4266
4267   /* PREFIX_VEX_FB */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4272   },
4273
4274   /* PREFIX_VEX_FC */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4279   },
4280
4281   /* PREFIX_VEX_FD */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4286   },
4287
4288   /* PREFIX_VEX_FE */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4293   },
4294
4295   /* PREFIX_VEX_3800 */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4300   },
4301
4302   /* PREFIX_VEX_3801 */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4307   },
4308
4309   /* PREFIX_VEX_3802 */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4314   },
4315
4316   /* PREFIX_VEX_3803 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4321   },
4322
4323   /* PREFIX_VEX_3804 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4328   },
4329
4330   /* PREFIX_VEX_3805 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4335   },
4336
4337   /* PREFIX_VEX_3806 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4342   },
4343
4344   /* PREFIX_VEX_3807 */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4349   },
4350
4351   /* PREFIX_VEX_3808 */
4352   {
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4356   },
4357
4358   /* PREFIX_VEX_3809 */
4359   {
4360     { Bad_Opcode },
4361     { Bad_Opcode },
4362     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4363   },
4364
4365   /* PREFIX_VEX_380A */
4366   {
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4370   },
4371
4372   /* PREFIX_VEX_380B */
4373   {
4374     { Bad_Opcode },
4375     { Bad_Opcode },
4376     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4377   },
4378
4379   /* PREFIX_VEX_380C */
4380   {
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { VEX_W_TABLE (VEX_W_380C_P_2) },
4384   },
4385
4386   /* PREFIX_VEX_380D */
4387   {
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { VEX_W_TABLE (VEX_W_380D_P_2) },
4391   },
4392
4393   /* PREFIX_VEX_380E */
4394   {
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { VEX_W_TABLE (VEX_W_380E_P_2) },
4398   },
4399
4400   /* PREFIX_VEX_380F */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { VEX_W_TABLE (VEX_W_380F_P_2) },
4405   },
4406
4407   /* PREFIX_VEX_3817 */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { VEX_W_TABLE (VEX_W_3817_P_2) },
4412   },
4413
4414   /* PREFIX_VEX_3818 */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4419   },
4420
4421   /* PREFIX_VEX_3819 */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4426   },
4427
4428   /* PREFIX_VEX_381A */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4433   },
4434
4435   /* PREFIX_VEX_381C */
4436   {
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4440   },
4441
4442   /* PREFIX_VEX_381D */
4443   {
4444     { Bad_Opcode },
4445     { Bad_Opcode },
4446     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4447   },
4448
4449   /* PREFIX_VEX_381E */
4450   {
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4454   },
4455
4456   /* PREFIX_VEX_3820 */
4457   {
4458     { Bad_Opcode },
4459     { Bad_Opcode },
4460     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4461   },
4462
4463   /* PREFIX_VEX_3821 */
4464   {
4465     { Bad_Opcode },
4466     { Bad_Opcode },
4467     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4468   },
4469
4470   /* PREFIX_VEX_3822 */
4471   {
4472     { Bad_Opcode },
4473     { Bad_Opcode },
4474     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4475   },
4476
4477   /* PREFIX_VEX_3823 */
4478   {
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4482   },
4483
4484   /* PREFIX_VEX_3824 */
4485   {
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4489   },
4490
4491   /* PREFIX_VEX_3825 */
4492   {
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4496   },
4497
4498   /* PREFIX_VEX_3828 */
4499   {
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4503   },
4504
4505   /* PREFIX_VEX_3829 */
4506   {
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4510   },
4511
4512   /* PREFIX_VEX_382A */
4513   {
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4517   },
4518
4519   /* PREFIX_VEX_382B */
4520   {
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4524   },
4525
4526   /* PREFIX_VEX_382C */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4531   },
4532
4533   /* PREFIX_VEX_382D */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4538   },
4539
4540   /* PREFIX_VEX_382E */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4545   },
4546
4547   /* PREFIX_VEX_382F */
4548   {
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4552   },
4553
4554   /* PREFIX_VEX_3830 */
4555   {
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4559   },
4560
4561   /* PREFIX_VEX_3831 */
4562   {
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4566   },
4567
4568   /* PREFIX_VEX_3832 */
4569   {
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4573   },
4574
4575   /* PREFIX_VEX_3833 */
4576   {
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4580   },
4581
4582   /* PREFIX_VEX_3834 */
4583   {
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4587   },
4588
4589   /* PREFIX_VEX_3835 */
4590   {
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4594   },
4595
4596   /* PREFIX_VEX_3837 */
4597   {
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4601   },
4602
4603   /* PREFIX_VEX_3838 */
4604   {
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4608   },
4609
4610   /* PREFIX_VEX_3839 */
4611   {
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4615   },
4616
4617   /* PREFIX_VEX_383A */
4618   {
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4622   },
4623
4624   /* PREFIX_VEX_383B */
4625   {
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4629   },
4630
4631   /* PREFIX_VEX_383C */
4632   {
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4636   },
4637
4638   /* PREFIX_VEX_383D */
4639   {
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4643   },
4644
4645   /* PREFIX_VEX_383E */
4646   {
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4650   },
4651
4652   /* PREFIX_VEX_383F */
4653   {
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4657   },
4658
4659   /* PREFIX_VEX_3840 */
4660   {
4661     { Bad_Opcode },
4662     { Bad_Opcode },
4663     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4664   },
4665
4666   /* PREFIX_VEX_3841 */
4667   {
4668     { Bad_Opcode },
4669     { Bad_Opcode },
4670     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4671   },
4672
4673   /* PREFIX_VEX_3896 */
4674   {
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4678   },
4679
4680   /* PREFIX_VEX_3897 */
4681   {
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4685   },
4686
4687   /* PREFIX_VEX_3898 */
4688   {
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { "vfmadd132p%XW", { XM, Vex, EXx } },
4692   },
4693
4694   /* PREFIX_VEX_3899 */
4695   {
4696     { Bad_Opcode },
4697     { Bad_Opcode },
4698     { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4699   },
4700
4701   /* PREFIX_VEX_389A */
4702   {
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { "vfmsub132p%XW", { XM, Vex, EXx } },
4706   },
4707
4708   /* PREFIX_VEX_389B */
4709   {
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4713   },
4714
4715   /* PREFIX_VEX_389C */
4716   {
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4720   },
4721
4722   /* PREFIX_VEX_389D */
4723   {
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4727   },
4728
4729   /* PREFIX_VEX_389E */
4730   {
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4734   },
4735
4736   /* PREFIX_VEX_389F */
4737   {
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4741   },
4742
4743   /* PREFIX_VEX_38A6 */
4744   {
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4748     { Bad_Opcode },
4749   },
4750
4751   /* PREFIX_VEX_38A7 */
4752   {
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4756   },
4757
4758   /* PREFIX_VEX_38A8 */
4759   {
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { "vfmadd213p%XW", { XM, Vex, EXx } },
4763   },
4764
4765   /* PREFIX_VEX_38A9 */
4766   {
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4770   },
4771
4772   /* PREFIX_VEX_38AA */
4773   {
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { "vfmsub213p%XW", { XM, Vex, EXx } },
4777   },
4778
4779   /* PREFIX_VEX_38AB */
4780   {
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4784   },
4785
4786   /* PREFIX_VEX_38AC */
4787   {
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4791   },
4792
4793   /* PREFIX_VEX_38AD */
4794   {
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4798   },
4799
4800   /* PREFIX_VEX_38AE */
4801   {
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4805   },
4806
4807   /* PREFIX_VEX_38AF */
4808   {
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4812   },
4813
4814   /* PREFIX_VEX_38B6 */
4815   {
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4819   },
4820
4821   /* PREFIX_VEX_38B7 */
4822   {
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4826   },
4827
4828   /* PREFIX_VEX_38B8 */
4829   {
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { "vfmadd231p%XW", { XM, Vex, EXx } },
4833   },
4834
4835   /* PREFIX_VEX_38B9 */
4836   {
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4840   },
4841
4842   /* PREFIX_VEX_38BA */
4843   {
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { "vfmsub231p%XW", { XM, Vex, EXx } },
4847   },
4848
4849   /* PREFIX_VEX_38BB */
4850   {
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4854   },
4855
4856   /* PREFIX_VEX_38BC */
4857   {
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4861   },
4862
4863   /* PREFIX_VEX_38BD */
4864   {
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4868   },
4869
4870   /* PREFIX_VEX_38BE */
4871   {
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4875   },
4876
4877   /* PREFIX_VEX_38BF */
4878   {
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4882   },
4883
4884   /* PREFIX_VEX_38DB */
4885   {
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4889   },
4890
4891   /* PREFIX_VEX_38DC */
4892   {
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4896   },
4897
4898   /* PREFIX_VEX_38DD */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4903   },
4904
4905   /* PREFIX_VEX_38DE */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4910   },
4911
4912   /* PREFIX_VEX_38DF */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4917   },
4918
4919   /* PREFIX_VEX_3A04 */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { VEX_W_TABLE (VEX_W_3A04_P_2) },
4924   },
4925
4926   /* PREFIX_VEX_3A05 */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { VEX_W_TABLE (VEX_W_3A05_P_2) },
4931   },
4932
4933   /* PREFIX_VEX_3A06 */
4934   {
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4938   },
4939
4940   /* PREFIX_VEX_3A08 */
4941   {
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { VEX_W_TABLE (VEX_W_3A08_P_2) },
4945   },
4946
4947   /* PREFIX_VEX_3A09 */
4948   {
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { VEX_W_TABLE (VEX_W_3A09_P_2) },
4952   },
4953
4954   /* PREFIX_VEX_3A0A */
4955   {
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4959   },
4960
4961   /* PREFIX_VEX_3A0B */
4962   {
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4966   },
4967
4968   /* PREFIX_VEX_3A0C */
4969   {
4970     { Bad_Opcode },
4971     { Bad_Opcode },
4972     { VEX_W_TABLE (VEX_W_3A0C_P_2) },
4973   },
4974
4975   /* PREFIX_VEX_3A0D */
4976   {
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { VEX_W_TABLE (VEX_W_3A0D_P_2) },
4980   },
4981
4982   /* PREFIX_VEX_3A0E */
4983   {
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4987   },
4988
4989   /* PREFIX_VEX_3A0F */
4990   {
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4994   },
4995
4996   /* PREFIX_VEX_3A14 */
4997   {
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5001   },
5002
5003   /* PREFIX_VEX_3A15 */
5004   {
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5008   },
5009
5010   /* PREFIX_VEX_3A16 */
5011   {
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
5015   },
5016
5017   /* PREFIX_VEX_3A17 */
5018   {
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5022   },
5023
5024   /* PREFIX_VEX_3A18 */
5025   {
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5029   },
5030
5031   /* PREFIX_VEX_3A19 */
5032   {
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5036   },
5037
5038   /* PREFIX_VEX_3A20 */
5039   {
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5043   },
5044
5045   /* PREFIX_VEX_3A21 */
5046   {
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5050   },
5051
5052   /* PREFIX_VEX_3A22 */
5053   {
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5057   },
5058
5059   /* PREFIX_VEX_3A40 */
5060   {
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { VEX_W_TABLE (VEX_W_3A40_P_2) },
5064   },
5065
5066   /* PREFIX_VEX_3A41 */
5067   {
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5071   },
5072
5073   /* PREFIX_VEX_3A42 */
5074   {
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5078   },
5079
5080   /* PREFIX_VEX_3A44 */
5081   {
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5085   },
5086
5087   /* PREFIX_VEX_3A4A */
5088   {
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { VEX_W_TABLE (VEX_W_3A4A_P_2) },
5092   },
5093
5094   /* PREFIX_VEX_3A4B */
5095   {
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { VEX_W_TABLE (VEX_W_3A4B_P_2) },
5099   },
5100
5101   /* PREFIX_VEX_3A4C */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5106   },
5107
5108   /* PREFIX_VEX_3A5C */
5109   {
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5113   },
5114
5115   /* PREFIX_VEX_3A5D */
5116   {
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5120   },
5121
5122   /* PREFIX_VEX_3A5E */
5123   {
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5127   },
5128
5129   /* PREFIX_VEX_3A5F */
5130   {
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5134   },
5135
5136   /* PREFIX_VEX_3A60 */
5137   {
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5141     { Bad_Opcode },
5142   },
5143
5144   /* PREFIX_VEX_3A61 */
5145   {
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5149   },
5150
5151   /* PREFIX_VEX_3A62 */
5152   {
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5156   },
5157
5158   /* PREFIX_VEX_3A63 */
5159   {
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5163   },
5164
5165   /* PREFIX_VEX_3A68 */
5166   {
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5170   },
5171
5172   /* PREFIX_VEX_3A69 */
5173   {
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5177   },
5178
5179   /* PREFIX_VEX_3A6A */
5180   {
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5184   },
5185
5186   /* PREFIX_VEX_3A6B */
5187   {
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5191   },
5192
5193   /* PREFIX_VEX_3A6C */
5194   {
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5198   },
5199
5200   /* PREFIX_VEX_3A6D */
5201   {
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5205   },
5206
5207   /* PREFIX_VEX_3A6E */
5208   {
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5212   },
5213
5214   /* PREFIX_VEX_3A6F */
5215   {
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5219   },
5220
5221   /* PREFIX_VEX_3A78 */
5222   {
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5226   },
5227
5228   /* PREFIX_VEX_3A79 */
5229   {
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5233   },
5234
5235   /* PREFIX_VEX_3A7A */
5236   {
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5240   },
5241
5242   /* PREFIX_VEX_3A7B */
5243   {
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5247   },
5248
5249   /* PREFIX_VEX_3A7C */
5250   {
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5254     { Bad_Opcode },
5255   },
5256
5257   /* PREFIX_VEX_3A7D */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5262   },
5263
5264   /* PREFIX_VEX_3A7E */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5269   },
5270
5271   /* PREFIX_VEX_3A7F */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5276   },
5277
5278   /* PREFIX_VEX_3ADF */
5279   {
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5283   },
5284 };
5285
5286 static const struct dis386 x86_64_table[][2] = {
5287   /* X86_64_06 */
5288   {
5289     { "push{T|}", { es } },
5290   },
5291
5292   /* X86_64_07 */
5293   {
5294     { "pop{T|}", { es } },
5295   },
5296
5297   /* X86_64_0D */
5298   {
5299     { "push{T|}", { cs } },
5300   },
5301
5302   /* X86_64_16 */
5303   {
5304     { "push{T|}", { ss } },
5305   },
5306
5307   /* X86_64_17 */
5308   {
5309     { "pop{T|}", { ss } },
5310   },
5311
5312   /* X86_64_1E */
5313   {
5314     { "push{T|}", { ds } },
5315   },
5316
5317   /* X86_64_1F */
5318   {
5319     { "pop{T|}", { ds } },
5320   },
5321
5322   /* X86_64_27 */
5323   {
5324     { "daa", { XX } },
5325   },
5326
5327   /* X86_64_2F */
5328   {
5329     { "das", { XX } },
5330   },
5331
5332   /* X86_64_37 */
5333   {
5334     { "aaa", { XX } },
5335   },
5336
5337   /* X86_64_3F */
5338   {
5339     { "aas", { XX } },
5340   },
5341
5342   /* X86_64_60 */
5343   {
5344     { "pusha{P|}", { XX } },
5345   },
5346
5347   /* X86_64_61 */
5348   {
5349     { "popa{P|}", { XX } },
5350   },
5351
5352   /* X86_64_62 */
5353   {
5354     { MOD_TABLE (MOD_62_32BIT) },
5355   },
5356
5357   /* X86_64_63 */
5358   {
5359     { "arpl", { Ew, Gw } },
5360     { "movs{lq|xd}", { Gv, Ed } },
5361   },
5362
5363   /* X86_64_6D */
5364   {
5365     { "ins{R|}", { Yzr, indirDX } },
5366     { "ins{G|}", { Yzr, indirDX } },
5367   },
5368
5369   /* X86_64_6F */
5370   {
5371     { "outs{R|}", { indirDXr, Xz } },
5372     { "outs{G|}", { indirDXr, Xz } },
5373   },
5374
5375   /* X86_64_9A */
5376   {
5377     { "Jcall{T|}", { Ap } },
5378   },
5379
5380   /* X86_64_C4 */
5381   {
5382     { MOD_TABLE (MOD_C4_32BIT) },
5383     { VEX_C4_TABLE (VEX_0F) },
5384   },
5385
5386   /* X86_64_C5 */
5387   {
5388     { MOD_TABLE (MOD_C5_32BIT) },
5389     { VEX_C5_TABLE (VEX_0F) },
5390   },
5391
5392   /* X86_64_CE */
5393   {
5394     { "into", { XX } },
5395   },
5396
5397   /* X86_64_D4 */
5398   {
5399     { "aam", { sIb } },
5400   },
5401
5402   /* X86_64_D5 */
5403   {
5404     { "aad", { sIb } },
5405   },
5406
5407   /* X86_64_EA */
5408   {
5409     { "Jjmp{T|}", { Ap } },
5410   },
5411
5412   /* X86_64_0F01_REG_0 */
5413   {
5414     { "sgdt{Q|IQ}", { M } },
5415     { "sgdt", { M } },
5416   },
5417
5418   /* X86_64_0F01_REG_1 */
5419   {
5420     { "sidt{Q|IQ}", { M } },
5421     { "sidt", { M } },
5422   },
5423
5424   /* X86_64_0F01_REG_2 */
5425   {
5426     { "lgdt{Q|Q}", { M } },
5427     { "lgdt", { M } },
5428   },
5429
5430   /* X86_64_0F01_REG_3 */
5431   {
5432     { "lidt{Q|Q}", { M } },
5433     { "lidt", { M } },
5434   },
5435 };
5436
5437 static const struct dis386 three_byte_table[][256] = {
5438
5439   /* THREE_BYTE_0F38 */
5440   {
5441     /* 00 */
5442     { "pshufb",         { MX, EM } },
5443     { "phaddw",         { MX, EM } },
5444     { "phaddd",         { MX, EM } },
5445     { "phaddsw",        { MX, EM } },
5446     { "pmaddubsw",      { MX, EM } },
5447     { "phsubw",         { MX, EM } },
5448     { "phsubd",         { MX, EM } },
5449     { "phsubsw",        { MX, EM } },
5450     /* 08 */
5451     { "psignb",         { MX, EM } },
5452     { "psignw",         { MX, EM } },
5453     { "psignd",         { MX, EM } },
5454     { "pmulhrsw",       { MX, EM } },
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     /* 10 */
5460     { PREFIX_TABLE (PREFIX_0F3810) },
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { PREFIX_TABLE (PREFIX_0F3814) },
5465     { PREFIX_TABLE (PREFIX_0F3815) },
5466     { Bad_Opcode },
5467     { PREFIX_TABLE (PREFIX_0F3817) },
5468     /* 18 */
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { "pabsb",          { MX, EM } },
5474     { "pabsw",          { MX, EM } },
5475     { "pabsd",          { MX, EM } },
5476     { Bad_Opcode },
5477     /* 20 */
5478     { PREFIX_TABLE (PREFIX_0F3820) },
5479     { PREFIX_TABLE (PREFIX_0F3821) },
5480     { PREFIX_TABLE (PREFIX_0F3822) },
5481     { PREFIX_TABLE (PREFIX_0F3823) },
5482     { PREFIX_TABLE (PREFIX_0F3824) },
5483     { PREFIX_TABLE (PREFIX_0F3825) },
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     /* 28 */
5487     { PREFIX_TABLE (PREFIX_0F3828) },
5488     { PREFIX_TABLE (PREFIX_0F3829) },
5489     { PREFIX_TABLE (PREFIX_0F382A) },
5490     { PREFIX_TABLE (PREFIX_0F382B) },
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     /* 30 */
5496     { PREFIX_TABLE (PREFIX_0F3830) },
5497     { PREFIX_TABLE (PREFIX_0F3831) },
5498     { PREFIX_TABLE (PREFIX_0F3832) },
5499     { PREFIX_TABLE (PREFIX_0F3833) },
5500     { PREFIX_TABLE (PREFIX_0F3834) },
5501     { PREFIX_TABLE (PREFIX_0F3835) },
5502     { Bad_Opcode },
5503     { PREFIX_TABLE (PREFIX_0F3837) },
5504     /* 38 */
5505     { PREFIX_TABLE (PREFIX_0F3838) },
5506     { PREFIX_TABLE (PREFIX_0F3839) },
5507     { PREFIX_TABLE (PREFIX_0F383A) },
5508     { PREFIX_TABLE (PREFIX_0F383B) },
5509     { PREFIX_TABLE (PREFIX_0F383C) },
5510     { PREFIX_TABLE (PREFIX_0F383D) },
5511     { PREFIX_TABLE (PREFIX_0F383E) },
5512     { PREFIX_TABLE (PREFIX_0F383F) },
5513     /* 40 */
5514     { PREFIX_TABLE (PREFIX_0F3840) },
5515     { PREFIX_TABLE (PREFIX_0F3841) },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     /* 48 */
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     /* 50 */
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     /* 58 */
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     /* 60 */
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     /* 68 */
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     /* 70 */
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     /* 78 */
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     /* 80 */
5586     { PREFIX_TABLE (PREFIX_0F3880) },
5587     { PREFIX_TABLE (PREFIX_0F3881) },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     /* 88 */
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     /* 90 */
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     /* 98 */
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     /* a0 */
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     /* a8 */
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     /* b0 */
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     /* b8 */
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     /* c0 */
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     /* c8 */
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     /* d0 */
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     /* d8 */
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { PREFIX_TABLE (PREFIX_0F38DB) },
5689     { PREFIX_TABLE (PREFIX_0F38DC) },
5690     { PREFIX_TABLE (PREFIX_0F38DD) },
5691     { PREFIX_TABLE (PREFIX_0F38DE) },
5692     { PREFIX_TABLE (PREFIX_0F38DF) },
5693     /* e0 */
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     /* e8 */
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     /* f0 */
5712     { PREFIX_TABLE (PREFIX_0F38F0) },
5713     { PREFIX_TABLE (PREFIX_0F38F1) },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     /* f8 */
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729   },
5730   /* THREE_BYTE_0F3A */
5731   {
5732     /* 00 */
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     /* 08 */
5742     { PREFIX_TABLE (PREFIX_0F3A08) },
5743     { PREFIX_TABLE (PREFIX_0F3A09) },
5744     { PREFIX_TABLE (PREFIX_0F3A0A) },
5745     { PREFIX_TABLE (PREFIX_0F3A0B) },
5746     { PREFIX_TABLE (PREFIX_0F3A0C) },
5747     { PREFIX_TABLE (PREFIX_0F3A0D) },
5748     { PREFIX_TABLE (PREFIX_0F3A0E) },
5749     { "palignr",        { MX, EM, Ib } },
5750     /* 10 */
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { PREFIX_TABLE (PREFIX_0F3A14) },
5756     { PREFIX_TABLE (PREFIX_0F3A15) },
5757     { PREFIX_TABLE (PREFIX_0F3A16) },
5758     { PREFIX_TABLE (PREFIX_0F3A17) },
5759     /* 18 */
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     /* 20 */
5769     { PREFIX_TABLE (PREFIX_0F3A20) },
5770     { PREFIX_TABLE (PREFIX_0F3A21) },
5771     { PREFIX_TABLE (PREFIX_0F3A22) },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     /* 28 */
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     /* 30 */
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     /* 38 */
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     /* 40 */
5805     { PREFIX_TABLE (PREFIX_0F3A40) },
5806     { PREFIX_TABLE (PREFIX_0F3A41) },
5807     { PREFIX_TABLE (PREFIX_0F3A42) },
5808     { Bad_Opcode },
5809     { PREFIX_TABLE (PREFIX_0F3A44) },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     /* 48 */
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     /* 50 */
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     /* 58 */
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     /* 60 */
5841     { PREFIX_TABLE (PREFIX_0F3A60) },
5842     { PREFIX_TABLE (PREFIX_0F3A61) },
5843     { PREFIX_TABLE (PREFIX_0F3A62) },
5844     { PREFIX_TABLE (PREFIX_0F3A63) },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     /* 68 */
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     /* 70 */
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     /* 78 */
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     /* 80 */
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     /* 88 */
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     /* 90 */
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     /* 98 */
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     /* a0 */
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     /* a8 */
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     /* b0 */
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     /* b8 */
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     /* c0 */
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     /* c8 */
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     /* d0 */
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     /* d8 */
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { PREFIX_TABLE (PREFIX_0F3ADF) },
5984     /* e0 */
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     /* e8 */
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     /* f0 */
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     /* f8 */
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020   },
6021
6022   /* THREE_BYTE_0F7A */
6023   {
6024     /* 00 */
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     /* 08 */
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     /* 10 */
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     /* 18 */
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     /* 20 */
6061     { "ptest",          { XX } },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     /* 28 */
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     /* 30 */
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     /* 38 */
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     /* 40 */
6097     { Bad_Opcode },
6098     { "phaddbw",        { XM, EXq } },
6099     { "phaddbd",        { XM, EXq } },
6100     { "phaddbq",        { XM, EXq } },
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { "phaddwd",        { XM, EXq } },
6104     { "phaddwq",        { XM, EXq } },
6105     /* 48 */
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { "phadddq",        { XM, EXq } },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     /* 50 */
6115     { Bad_Opcode },
6116     { "phaddubw",       { XM, EXq } },
6117     { "phaddubd",       { XM, EXq } },
6118     { "phaddubq",       { XM, EXq } },
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { "phadduwd",       { XM, EXq } },
6122     { "phadduwq",       { XM, EXq } },
6123     /* 58 */
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { "phaddudq",       { XM, EXq } },
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     /* 60 */
6133     { Bad_Opcode },
6134     { "phsubbw",        { XM, EXq } },
6135     { "phsubbd",        { XM, EXq } },
6136     { "phsubbq",        { XM, EXq } },
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     /* 68 */
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     /* 70 */
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { Bad_Opcode },
6159     /* 78 */
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     /* 80 */
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     /* 88 */
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     /* 90 */
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     /* 98 */
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     /* a0 */
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     /* a8 */
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     /* b0 */
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     /* b8 */
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     /* c0 */
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     /* c8 */
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     /* d0 */
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     /* d8 */
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     /* e0 */
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     /* e8 */
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     /* f0 */
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     /* f8 */
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312   },
6313 };
6314
6315 static const struct dis386 xop_table[][256] = {
6316   /* XOP_08 */
6317   {
6318     /* 00 */
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     /* 08 */
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { Bad_Opcode },
6336     /* 10 */
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     /* 18 */
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     /* 20 */
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     /* 28 */
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     /* 30 */
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     /* 38 */
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     /* 40 */
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     /* 48 */
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     /* 50 */
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     /* 58 */
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     /* 60 */
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     /* 68 */
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     /* 70 */
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     /* 78 */
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     /* 80 */
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6469     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6470     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6471     /* 88 */
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6479     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6480     /* 90 */
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6487     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6488     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6489     /* 98 */
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6497     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6498     /* a0 */
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6502     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6506     { Bad_Opcode },
6507     /* a8 */
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     /* b0 */
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6524     { Bad_Opcode },
6525     /* b8 */
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     /* c0 */
6535     { "vprotb",         { XM, Vex_2src_1, Ib } },
6536     { "vprotw",         { XM, Vex_2src_1, Ib } },
6537     { "vprotd",         { XM, Vex_2src_1, Ib } },
6538     { "vprotq",         { XM, Vex_2src_1, Ib } },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     /* c8 */
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { "vpcomb",         { XM, Vex128, EXx, Ib } },
6549     { "vpcomw",         { XM, Vex128, EXx, Ib } },
6550     { "vpcomd",         { XM, Vex128, EXx, Ib } },
6551     { "vpcomq",         { XM, Vex128, EXx, Ib } },
6552     /* d0 */
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     /* d8 */
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     /* e0 */
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     /* e8 */
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { "vpcomub",        { XM, Vex128, EXx, Ib } },
6585     { "vpcomuw",        { XM, Vex128, EXx, Ib } },
6586     { "vpcomud",        { XM, Vex128, EXx, Ib } },
6587     { "vpcomuq",        { XM, Vex128, EXx, Ib } },
6588     /* f0 */
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     /* f8 */
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606   },
6607   /* XOP_09 */
6608   {
6609     /* 00 */
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     /* 08 */
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     /* 10 */
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { REG_TABLE (REG_XOP_LWPCB) },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     /* 18 */
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     /* 20 */
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     /* 28 */
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     /* 30 */
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     /* 38 */
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     /* 40 */
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     /* 48 */
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     /* 50 */
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     /* 58 */
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     /* 60 */
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     /* 68 */
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     /* 70 */
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     /* 78 */
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     /* 80 */
6754     { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
6755     { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
6756     { "vfrczss",        { XM, EXd } },
6757     { "vfrczsd",        { XM, EXq } },
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     /* 88 */
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     /* 90 */
6772     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
6773     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
6774     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
6775     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
6776     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
6777     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
6778     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
6779     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
6780     /* 98 */
6781     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
6782     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
6783     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
6784     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     /* a0 */
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     /* a8 */
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     /* b0 */
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     /* b8 */
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     /* c0 */
6826     { Bad_Opcode },
6827     { "vphaddbw",       { XM, EXxmm } },
6828     { "vphaddbd",       { XM, EXxmm } },
6829     { "vphaddbq",       { XM, EXxmm } },
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { "vphaddwd",       { XM, EXxmm } },
6833     { "vphaddwq",       { XM, EXxmm } },
6834     /* c8 */
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { "vphadddq",       { XM, EXxmm } },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     /* d0 */
6844     { Bad_Opcode },
6845     { "vphaddubw",      { XM, EXxmm } },
6846     { "vphaddubd",      { XM, EXxmm } },
6847     { "vphaddubq",      { XM, EXxmm } },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { "vphadduwd",      { XM, EXxmm } },
6851     { "vphadduwq",      { XM, EXxmm } },
6852     /* d8 */
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { "vphaddudq",      { XM, EXxmm } },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     /* e0 */
6862     { Bad_Opcode },
6863     { "vphsubbw",       { XM, EXxmm } },
6864     { "vphsubwd",       { XM, EXxmm } },
6865     { "vphsubdq",       { XM, EXxmm } },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     /* e8 */
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     /* f0 */
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     /* f8 */
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897   },
6898   /* XOP_0A */
6899   {
6900     /* 00 */
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     /* 08 */
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     /* 10 */
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { REG_TABLE (REG_XOP_LWP) },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     /* 18 */
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     /* 20 */
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     /* 28 */
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     /* 30 */
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     /* 38 */
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     /* 40 */
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     /* 48 */
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     /* 50 */
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     /* 58 */
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     /* 60 */
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     /* 68 */
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     /* 70 */
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     /* 78 */
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     /* 80 */
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     /* 88 */
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     /* 90 */
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     /* 98 */
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     /* a0 */
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     /* a8 */
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     /* b0 */
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     /* b8 */
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     /* c0 */
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     /* c8 */
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     /* d0 */
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     /* d8 */
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     /* e0 */
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     /* e8 */
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     /* f0 */
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     /* f8 */
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188   },
7189 };
7190
7191 static const struct dis386 vex_table[][256] = {
7192   /* VEX_0F */
7193   {
7194     /* 00 */
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     /* 08 */
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     /* 10 */
7213     { PREFIX_TABLE (PREFIX_VEX_10) },
7214     { PREFIX_TABLE (PREFIX_VEX_11) },
7215     { PREFIX_TABLE (PREFIX_VEX_12) },
7216     { MOD_TABLE (MOD_VEX_13) },
7217     { VEX_W_TABLE (VEX_W_14) },
7218     { VEX_W_TABLE (VEX_W_15) },
7219     { PREFIX_TABLE (PREFIX_VEX_16) },
7220     { MOD_TABLE (MOD_VEX_17) },
7221     /* 18 */
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     /* 20 */
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     /* 28 */
7240     { VEX_W_TABLE (VEX_W_28) },
7241     { VEX_W_TABLE (VEX_W_29) },
7242     { PREFIX_TABLE (PREFIX_VEX_2A) },
7243     { MOD_TABLE (MOD_VEX_2B) },
7244     { PREFIX_TABLE (PREFIX_VEX_2C) },
7245     { PREFIX_TABLE (PREFIX_VEX_2D) },
7246     { PREFIX_TABLE (PREFIX_VEX_2E) },
7247     { PREFIX_TABLE (PREFIX_VEX_2F) },
7248     /* 30 */
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     /* 38 */
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     /* 40 */
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     /* 48 */
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     /* 50 */
7285     { MOD_TABLE (MOD_VEX_50) },
7286     { PREFIX_TABLE (PREFIX_VEX_51) },
7287     { PREFIX_TABLE (PREFIX_VEX_52) },
7288     { PREFIX_TABLE (PREFIX_VEX_53) },
7289     { "vandpX",         { XM, Vex, EXx } },
7290     { "vandnpX",        { XM, Vex, EXx } },
7291     { "vorpX",          { XM, Vex, EXx } },
7292     { "vxorpX",         { XM, Vex, EXx } },
7293     /* 58 */
7294     { PREFIX_TABLE (PREFIX_VEX_58) },
7295     { PREFIX_TABLE (PREFIX_VEX_59) },
7296     { PREFIX_TABLE (PREFIX_VEX_5A) },
7297     { PREFIX_TABLE (PREFIX_VEX_5B) },
7298     { PREFIX_TABLE (PREFIX_VEX_5C) },
7299     { PREFIX_TABLE (PREFIX_VEX_5D) },
7300     { PREFIX_TABLE (PREFIX_VEX_5E) },
7301     { PREFIX_TABLE (PREFIX_VEX_5F) },
7302     /* 60 */
7303     { PREFIX_TABLE (PREFIX_VEX_60) },
7304     { PREFIX_TABLE (PREFIX_VEX_61) },
7305     { PREFIX_TABLE (PREFIX_VEX_62) },
7306     { PREFIX_TABLE (PREFIX_VEX_63) },
7307     { PREFIX_TABLE (PREFIX_VEX_64) },
7308     { PREFIX_TABLE (PREFIX_VEX_65) },
7309     { PREFIX_TABLE (PREFIX_VEX_66) },
7310     { PREFIX_TABLE (PREFIX_VEX_67) },
7311     /* 68 */
7312     { PREFIX_TABLE (PREFIX_VEX_68) },
7313     { PREFIX_TABLE (PREFIX_VEX_69) },
7314     { PREFIX_TABLE (PREFIX_VEX_6A) },
7315     { PREFIX_TABLE (PREFIX_VEX_6B) },
7316     { PREFIX_TABLE (PREFIX_VEX_6C) },
7317     { PREFIX_TABLE (PREFIX_VEX_6D) },
7318     { PREFIX_TABLE (PREFIX_VEX_6E) },
7319     { PREFIX_TABLE (PREFIX_VEX_6F) },
7320     /* 70 */
7321     { PREFIX_TABLE (PREFIX_VEX_70) },
7322     { REG_TABLE (REG_VEX_71) },
7323     { REG_TABLE (REG_VEX_72) },
7324     { REG_TABLE (REG_VEX_73) },
7325     { PREFIX_TABLE (PREFIX_VEX_74) },
7326     { PREFIX_TABLE (PREFIX_VEX_75) },
7327     { PREFIX_TABLE (PREFIX_VEX_76) },
7328     { PREFIX_TABLE (PREFIX_VEX_77) },
7329     /* 78 */
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { PREFIX_TABLE (PREFIX_VEX_7C) },
7335     { PREFIX_TABLE (PREFIX_VEX_7D) },
7336     { PREFIX_TABLE (PREFIX_VEX_7E) },
7337     { PREFIX_TABLE (PREFIX_VEX_7F) },
7338     /* 80 */
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     /* 88 */
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     /* 90 */
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     /* 98 */
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     /* a0 */
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     /* a8 */
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { REG_TABLE (REG_VEX_AE) },
7391     { Bad_Opcode },
7392     /* b0 */
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     /* b8 */
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     /* c0 */
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { PREFIX_TABLE (PREFIX_VEX_C2) },
7414     { Bad_Opcode },
7415     { PREFIX_TABLE (PREFIX_VEX_C4) },
7416     { PREFIX_TABLE (PREFIX_VEX_C5) },
7417     { "vshufpX",        { XM, Vex, EXx, Ib } },
7418     { Bad_Opcode },
7419     /* c8 */
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     /* d0 */
7429     { PREFIX_TABLE (PREFIX_VEX_D0) },
7430     { PREFIX_TABLE (PREFIX_VEX_D1) },
7431     { PREFIX_TABLE (PREFIX_VEX_D2) },
7432     { PREFIX_TABLE (PREFIX_VEX_D3) },
7433     { PREFIX_TABLE (PREFIX_VEX_D4) },
7434     { PREFIX_TABLE (PREFIX_VEX_D5) },
7435     { PREFIX_TABLE (PREFIX_VEX_D6) },
7436     { PREFIX_TABLE (PREFIX_VEX_D7) },
7437     /* d8 */
7438     { PREFIX_TABLE (PREFIX_VEX_D8) },
7439     { PREFIX_TABLE (PREFIX_VEX_D9) },
7440     { PREFIX_TABLE (PREFIX_VEX_DA) },
7441     { PREFIX_TABLE (PREFIX_VEX_DB) },
7442     { PREFIX_TABLE (PREFIX_VEX_DC) },
7443     { PREFIX_TABLE (PREFIX_VEX_DD) },
7444     { PREFIX_TABLE (PREFIX_VEX_DE) },
7445     { PREFIX_TABLE (PREFIX_VEX_DF) },
7446     /* e0 */
7447     { PREFIX_TABLE (PREFIX_VEX_E0) },
7448     { PREFIX_TABLE (PREFIX_VEX_E1) },
7449     { PREFIX_TABLE (PREFIX_VEX_E2) },
7450     { PREFIX_TABLE (PREFIX_VEX_E3) },
7451     { PREFIX_TABLE (PREFIX_VEX_E4) },
7452     { PREFIX_TABLE (PREFIX_VEX_E5) },
7453     { PREFIX_TABLE (PREFIX_VEX_E6) },
7454     { PREFIX_TABLE (PREFIX_VEX_E7) },
7455     /* e8 */
7456     { PREFIX_TABLE (PREFIX_VEX_E8) },
7457     { PREFIX_TABLE (PREFIX_VEX_E9) },
7458     { PREFIX_TABLE (PREFIX_VEX_EA) },
7459     { PREFIX_TABLE (PREFIX_VEX_EB) },
7460     { PREFIX_TABLE (PREFIX_VEX_EC) },
7461     { PREFIX_TABLE (PREFIX_VEX_ED) },
7462     { PREFIX_TABLE (PREFIX_VEX_EE) },
7463     { PREFIX_TABLE (PREFIX_VEX_EF) },
7464     /* f0 */
7465     { PREFIX_TABLE (PREFIX_VEX_F0) },
7466     { PREFIX_TABLE (PREFIX_VEX_F1) },
7467     { PREFIX_TABLE (PREFIX_VEX_F2) },
7468     { PREFIX_TABLE (PREFIX_VEX_F3) },
7469     { PREFIX_TABLE (PREFIX_VEX_F4) },
7470     { PREFIX_TABLE (PREFIX_VEX_F5) },
7471     { PREFIX_TABLE (PREFIX_VEX_F6) },
7472     { PREFIX_TABLE (PREFIX_VEX_F7) },
7473     /* f8 */
7474     { PREFIX_TABLE (PREFIX_VEX_F8) },
7475     { PREFIX_TABLE (PREFIX_VEX_F9) },
7476     { PREFIX_TABLE (PREFIX_VEX_FA) },
7477     { PREFIX_TABLE (PREFIX_VEX_FB) },
7478     { PREFIX_TABLE (PREFIX_VEX_FC) },
7479     { PREFIX_TABLE (PREFIX_VEX_FD) },
7480     { PREFIX_TABLE (PREFIX_VEX_FE) },
7481     { Bad_Opcode },
7482   },
7483   /* VEX_0F38 */
7484   {
7485     /* 00 */
7486     { PREFIX_TABLE (PREFIX_VEX_3800) },
7487     { PREFIX_TABLE (PREFIX_VEX_3801) },
7488     { PREFIX_TABLE (PREFIX_VEX_3802) },
7489     { PREFIX_TABLE (PREFIX_VEX_3803) },
7490     { PREFIX_TABLE (PREFIX_VEX_3804) },
7491     { PREFIX_TABLE (PREFIX_VEX_3805) },
7492     { PREFIX_TABLE (PREFIX_VEX_3806) },
7493     { PREFIX_TABLE (PREFIX_VEX_3807) },
7494     /* 08 */
7495     { PREFIX_TABLE (PREFIX_VEX_3808) },
7496     { PREFIX_TABLE (PREFIX_VEX_3809) },
7497     { PREFIX_TABLE (PREFIX_VEX_380A) },
7498     { PREFIX_TABLE (PREFIX_VEX_380B) },
7499     { PREFIX_TABLE (PREFIX_VEX_380C) },
7500     { PREFIX_TABLE (PREFIX_VEX_380D) },
7501     { PREFIX_TABLE (PREFIX_VEX_380E) },
7502     { PREFIX_TABLE (PREFIX_VEX_380F) },
7503     /* 10 */
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { PREFIX_TABLE (PREFIX_VEX_3817) },
7512     /* 18 */
7513     { PREFIX_TABLE (PREFIX_VEX_3818) },
7514     { PREFIX_TABLE (PREFIX_VEX_3819) },
7515     { PREFIX_TABLE (PREFIX_VEX_381A) },
7516     { Bad_Opcode },
7517     { PREFIX_TABLE (PREFIX_VEX_381C) },
7518     { PREFIX_TABLE (PREFIX_VEX_381D) },
7519     { PREFIX_TABLE (PREFIX_VEX_381E) },
7520     { Bad_Opcode },
7521     /* 20 */
7522     { PREFIX_TABLE (PREFIX_VEX_3820) },
7523     { PREFIX_TABLE (PREFIX_VEX_3821) },
7524     { PREFIX_TABLE (PREFIX_VEX_3822) },
7525     { PREFIX_TABLE (PREFIX_VEX_3823) },
7526     { PREFIX_TABLE (PREFIX_VEX_3824) },
7527     { PREFIX_TABLE (PREFIX_VEX_3825) },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     /* 28 */
7531     { PREFIX_TABLE (PREFIX_VEX_3828) },
7532     { PREFIX_TABLE (PREFIX_VEX_3829) },
7533     { PREFIX_TABLE (PREFIX_VEX_382A) },
7534     { PREFIX_TABLE (PREFIX_VEX_382B) },
7535     { PREFIX_TABLE (PREFIX_VEX_382C) },
7536     { PREFIX_TABLE (PREFIX_VEX_382D) },
7537     { PREFIX_TABLE (PREFIX_VEX_382E) },
7538     { PREFIX_TABLE (PREFIX_VEX_382F) },
7539     /* 30 */
7540     { PREFIX_TABLE (PREFIX_VEX_3830) },
7541     { PREFIX_TABLE (PREFIX_VEX_3831) },
7542     { PREFIX_TABLE (PREFIX_VEX_3832) },
7543     { PREFIX_TABLE (PREFIX_VEX_3833) },
7544     { PREFIX_TABLE (PREFIX_VEX_3834) },
7545     { PREFIX_TABLE (PREFIX_VEX_3835) },
7546     { Bad_Opcode },
7547     { PREFIX_TABLE (PREFIX_VEX_3837) },
7548     /* 38 */
7549     { PREFIX_TABLE (PREFIX_VEX_3838) },
7550     { PREFIX_TABLE (PREFIX_VEX_3839) },
7551     { PREFIX_TABLE (PREFIX_VEX_383A) },
7552     { PREFIX_TABLE (PREFIX_VEX_383B) },
7553     { PREFIX_TABLE (PREFIX_VEX_383C) },
7554     { PREFIX_TABLE (PREFIX_VEX_383D) },
7555     { PREFIX_TABLE (PREFIX_VEX_383E) },
7556     { PREFIX_TABLE (PREFIX_VEX_383F) },
7557     /* 40 */
7558     { PREFIX_TABLE (PREFIX_VEX_3840) },
7559     { PREFIX_TABLE (PREFIX_VEX_3841) },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     /* 48 */
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     /* 50 */
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     /* 58 */
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     /* 60 */
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     /* 68 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     /* 70 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     /* 78 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     /* 80 */
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     /* 88 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     /* 90 */
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { PREFIX_TABLE (PREFIX_VEX_3896) },
7655     { PREFIX_TABLE (PREFIX_VEX_3897) },
7656     /* 98 */
7657     { PREFIX_TABLE (PREFIX_VEX_3898) },
7658     { PREFIX_TABLE (PREFIX_VEX_3899) },
7659     { PREFIX_TABLE (PREFIX_VEX_389A) },
7660     { PREFIX_TABLE (PREFIX_VEX_389B) },
7661     { PREFIX_TABLE (PREFIX_VEX_389C) },
7662     { PREFIX_TABLE (PREFIX_VEX_389D) },
7663     { PREFIX_TABLE (PREFIX_VEX_389E) },
7664     { PREFIX_TABLE (PREFIX_VEX_389F) },
7665     /* a0 */
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { PREFIX_TABLE (PREFIX_VEX_38A6) },
7673     { PREFIX_TABLE (PREFIX_VEX_38A7) },
7674     /* a8 */
7675     { PREFIX_TABLE (PREFIX_VEX_38A8) },
7676     { PREFIX_TABLE (PREFIX_VEX_38A9) },
7677     { PREFIX_TABLE (PREFIX_VEX_38AA) },
7678     { PREFIX_TABLE (PREFIX_VEX_38AB) },
7679     { PREFIX_TABLE (PREFIX_VEX_38AC) },
7680     { PREFIX_TABLE (PREFIX_VEX_38AD) },
7681     { PREFIX_TABLE (PREFIX_VEX_38AE) },
7682     { PREFIX_TABLE (PREFIX_VEX_38AF) },
7683     /* b0 */
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { PREFIX_TABLE (PREFIX_VEX_38B6) },
7691     { PREFIX_TABLE (PREFIX_VEX_38B7) },
7692     /* b8 */
7693     { PREFIX_TABLE (PREFIX_VEX_38B8) },
7694     { PREFIX_TABLE (PREFIX_VEX_38B9) },
7695     { PREFIX_TABLE (PREFIX_VEX_38BA) },
7696     { PREFIX_TABLE (PREFIX_VEX_38BB) },
7697     { PREFIX_TABLE (PREFIX_VEX_38BC) },
7698     { PREFIX_TABLE (PREFIX_VEX_38BD) },
7699     { PREFIX_TABLE (PREFIX_VEX_38BE) },
7700     { PREFIX_TABLE (PREFIX_VEX_38BF) },
7701     /* c0 */
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     /* c8 */
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     /* d0 */
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     /* d8 */
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7733     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7734     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7735     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7736     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7737     /* e0 */
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     /* e8 */
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     /* f0 */
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     /* f8 */
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773   },
7774   /* VEX_0F3A */
7775   {
7776     /* 00 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7782     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7783     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7784     { Bad_Opcode },
7785     /* 08 */
7786     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7787     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7788     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7789     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7790     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7791     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7792     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7793     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7794     /* 10 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7800     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7801     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7802     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7803     /* 18 */
7804     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7805     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     /* 20 */
7813     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7814     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7815     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     /* 28 */
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     /* 30 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* 38 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     /* 40 */
7849     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7850     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7851     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7852     { Bad_Opcode },
7853     { PREFIX_TABLE (PREFIX_VEX_3A44) },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     /* 48 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7861     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7862     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     /* 50 */
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     /* 58 */
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7881     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7882     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7883     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7884     /* 60 */
7885     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7886     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7887     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7888     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     /* 68 */
7894     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7895     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7896     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7897     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7898     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7899     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7900     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7901     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7902     /* 70 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     /* 78 */
7912     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7913     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7914     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7915     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7916     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7917     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7918     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7919     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7920     /* 80 */
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     /* 88 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     /* 90 */
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     /* 98 */
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     /* a0 */
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     /* a8 */
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     /* b0 */
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     /* b8 */
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     /* c0 */
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     /* c8 */
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     /* d0 */
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     /* d8 */
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
8028     /* e0 */
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     /* e8 */
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     /* f0 */
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     /* f8 */
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064   },
8065 };
8066
8067 static const struct dis386 vex_len_table[][2] = {
8068   /* VEX_LEN_10_P_1 */
8069   {
8070     { VEX_W_TABLE (VEX_W_10_P_1) },
8071     { VEX_W_TABLE (VEX_W_10_P_1) },
8072   },
8073
8074   /* VEX_LEN_10_P_3 */
8075   {
8076     { VEX_W_TABLE (VEX_W_10_P_3) },
8077     { VEX_W_TABLE (VEX_W_10_P_3) },
8078   },
8079
8080   /* VEX_LEN_11_P_1 */
8081   {
8082     { VEX_W_TABLE (VEX_W_11_P_1) },
8083     { VEX_W_TABLE (VEX_W_11_P_1) },
8084   },
8085
8086   /* VEX_LEN_11_P_3 */
8087   {
8088     { VEX_W_TABLE (VEX_W_11_P_3) },
8089     { VEX_W_TABLE (VEX_W_11_P_3) },
8090   },
8091
8092   /* VEX_LEN_12_P_0_M_0 */
8093   {
8094     { VEX_W_TABLE (VEX_W_12_P_0_M_0) },
8095   },
8096
8097   /* VEX_LEN_12_P_0_M_1 */
8098   {
8099     { VEX_W_TABLE (VEX_W_12_P_0_M_1) },
8100   },
8101
8102   /* VEX_LEN_12_P_2 */
8103   {
8104     { VEX_W_TABLE (VEX_W_12_P_2) },
8105   },
8106
8107   /* VEX_LEN_13_M_0 */
8108   {
8109     { VEX_W_TABLE (VEX_W_13_M_0) },
8110   },
8111
8112   /* VEX_LEN_16_P_0_M_0 */
8113   {
8114     { VEX_W_TABLE (VEX_W_16_P_0_M_0) },
8115   },
8116
8117   /* VEX_LEN_16_P_0_M_1 */
8118   {
8119     { VEX_W_TABLE (VEX_W_16_P_0_M_1) },
8120   },
8121
8122   /* VEX_LEN_16_P_2 */
8123   {
8124     { VEX_W_TABLE (VEX_W_16_P_2) },
8125   },
8126
8127   /* VEX_LEN_17_M_0 */
8128   {
8129     { VEX_W_TABLE (VEX_W_17_M_0) },
8130   },
8131
8132   /* VEX_LEN_2A_P_1 */
8133   {
8134     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8135     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8136   },
8137
8138   /* VEX_LEN_2A_P_3 */
8139   {
8140     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8141     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8142   },
8143
8144   /* VEX_LEN_2C_P_1 */
8145   {
8146     { "vcvttss2siY",    { Gv, EXdScalar } },
8147     { "vcvttss2siY",    { Gv, EXdScalar } },
8148   },
8149
8150   /* VEX_LEN_2C_P_3 */
8151   {
8152     { "vcvttsd2siY",    { Gv, EXqScalar } },
8153     { "vcvttsd2siY",    { Gv, EXqScalar } },
8154   },
8155
8156   /* VEX_LEN_2D_P_1 */
8157   {
8158     { "vcvtss2siY",     { Gv, EXdScalar } },
8159     { "vcvtss2siY",     { Gv, EXdScalar } },
8160   },
8161
8162   /* VEX_LEN_2D_P_3 */
8163   {
8164     { "vcvtsd2siY",     { Gv, EXqScalar } },
8165     { "vcvtsd2siY",     { Gv, EXqScalar } },
8166   },
8167
8168   /* VEX_LEN_2E_P_0 */
8169   {
8170     { VEX_W_TABLE (VEX_W_2E_P_0) },
8171     { VEX_W_TABLE (VEX_W_2E_P_0) },
8172   },
8173
8174   /* VEX_LEN_2E_P_2 */
8175   {
8176     { VEX_W_TABLE (VEX_W_2E_P_2) },
8177     { VEX_W_TABLE (VEX_W_2E_P_2) },
8178   },
8179
8180   /* VEX_LEN_2F_P_0 */
8181   {
8182     { VEX_W_TABLE (VEX_W_2F_P_0) },
8183     { VEX_W_TABLE (VEX_W_2F_P_0) },
8184   },
8185
8186   /* VEX_LEN_2F_P_2 */
8187   {
8188     { VEX_W_TABLE (VEX_W_2F_P_2) },
8189     { VEX_W_TABLE (VEX_W_2F_P_2) },
8190   },
8191
8192   /* VEX_LEN_51_P_1 */
8193   {
8194     { VEX_W_TABLE (VEX_W_51_P_1) },
8195     { VEX_W_TABLE (VEX_W_51_P_1) },
8196   },
8197
8198   /* VEX_LEN_51_P_3 */
8199   {
8200     { VEX_W_TABLE (VEX_W_51_P_3) },
8201     { VEX_W_TABLE (VEX_W_51_P_3) },
8202   },
8203
8204   /* VEX_LEN_52_P_1 */
8205   {
8206     { VEX_W_TABLE (VEX_W_52_P_1) },
8207     { VEX_W_TABLE (VEX_W_52_P_1) },
8208   },
8209
8210   /* VEX_LEN_53_P_1 */
8211   {
8212     { VEX_W_TABLE (VEX_W_53_P_1) },
8213     { VEX_W_TABLE (VEX_W_53_P_1) },
8214   },
8215
8216   /* VEX_LEN_58_P_1 */
8217   {
8218     { VEX_W_TABLE (VEX_W_58_P_1) },
8219     { VEX_W_TABLE (VEX_W_58_P_1) },
8220   },
8221
8222   /* VEX_LEN_58_P_3 */
8223   {
8224     { VEX_W_TABLE (VEX_W_58_P_3) },
8225     { VEX_W_TABLE (VEX_W_58_P_3) },
8226   },
8227
8228   /* VEX_LEN_59_P_1 */
8229   {
8230     { VEX_W_TABLE (VEX_W_59_P_1) },
8231     { VEX_W_TABLE (VEX_W_59_P_1) },
8232   },
8233
8234   /* VEX_LEN_59_P_3 */
8235   {
8236     { VEX_W_TABLE (VEX_W_59_P_3) },
8237     { VEX_W_TABLE (VEX_W_59_P_3) },
8238   },
8239
8240   /* VEX_LEN_5A_P_1 */
8241   {
8242     { VEX_W_TABLE (VEX_W_5A_P_1) },
8243     { VEX_W_TABLE (VEX_W_5A_P_1) },
8244   },
8245
8246   /* VEX_LEN_5A_P_3 */
8247   {
8248     { VEX_W_TABLE (VEX_W_5A_P_3) },
8249     { VEX_W_TABLE (VEX_W_5A_P_3) },
8250   },
8251
8252   /* VEX_LEN_5C_P_1 */
8253   {
8254     { VEX_W_TABLE (VEX_W_5C_P_1) },
8255     { VEX_W_TABLE (VEX_W_5C_P_1) },
8256   },
8257
8258   /* VEX_LEN_5C_P_3 */
8259   {
8260     { VEX_W_TABLE (VEX_W_5C_P_3) },
8261     { VEX_W_TABLE (VEX_W_5C_P_3) },
8262   },
8263
8264   /* VEX_LEN_5D_P_1 */
8265   {
8266     { VEX_W_TABLE (VEX_W_5D_P_1) },
8267     { VEX_W_TABLE (VEX_W_5D_P_1) },
8268   },
8269
8270   /* VEX_LEN_5D_P_3 */
8271   {
8272     { VEX_W_TABLE (VEX_W_5D_P_3) },
8273     { VEX_W_TABLE (VEX_W_5D_P_3) },
8274   },
8275
8276   /* VEX_LEN_5E_P_1 */
8277   {
8278     { VEX_W_TABLE (VEX_W_5E_P_1) },
8279     { VEX_W_TABLE (VEX_W_5E_P_1) },
8280   },
8281
8282   /* VEX_LEN_5E_P_3 */
8283   {
8284     { VEX_W_TABLE (VEX_W_5E_P_3) },
8285     { VEX_W_TABLE (VEX_W_5E_P_3) },
8286   },
8287
8288   /* VEX_LEN_5F_P_1 */
8289   {
8290     { VEX_W_TABLE (VEX_W_5F_P_1) },
8291     { VEX_W_TABLE (VEX_W_5F_P_1) },
8292   },
8293
8294   /* VEX_LEN_5F_P_3 */
8295   {
8296     { VEX_W_TABLE (VEX_W_5F_P_3) },
8297     { VEX_W_TABLE (VEX_W_5F_P_3) },
8298   },
8299
8300   /* VEX_LEN_60_P_2 */
8301   {
8302     { VEX_W_TABLE (VEX_W_60_P_2) },
8303   },
8304
8305   /* VEX_LEN_61_P_2 */
8306   {
8307     { VEX_W_TABLE (VEX_W_61_P_2) },
8308   },
8309
8310   /* VEX_LEN_62_P_2 */
8311   {
8312     { VEX_W_TABLE (VEX_W_62_P_2) },
8313   },
8314
8315   /* VEX_LEN_63_P_2 */
8316   {
8317     { VEX_W_TABLE (VEX_W_63_P_2) },
8318   },
8319
8320   /* VEX_LEN_64_P_2 */
8321   {
8322     { VEX_W_TABLE (VEX_W_64_P_2) },
8323   },
8324
8325   /* VEX_LEN_65_P_2 */
8326   {
8327     { VEX_W_TABLE (VEX_W_65_P_2) },
8328   },
8329
8330   /* VEX_LEN_66_P_2 */
8331   {
8332     { VEX_W_TABLE (VEX_W_66_P_2) },
8333   },
8334
8335   /* VEX_LEN_67_P_2 */
8336   {
8337     { VEX_W_TABLE (VEX_W_67_P_2) },
8338   },
8339
8340   /* VEX_LEN_68_P_2 */
8341   {
8342     { VEX_W_TABLE (VEX_W_68_P_2) },
8343   },
8344
8345   /* VEX_LEN_69_P_2 */
8346   {
8347     { VEX_W_TABLE (VEX_W_69_P_2) },
8348   },
8349
8350   /* VEX_LEN_6A_P_2 */
8351   {
8352     { VEX_W_TABLE (VEX_W_6A_P_2) },
8353   },
8354
8355   /* VEX_LEN_6B_P_2 */
8356   {
8357     { VEX_W_TABLE (VEX_W_6B_P_2) },
8358   },
8359
8360   /* VEX_LEN_6C_P_2 */
8361   {
8362     { VEX_W_TABLE (VEX_W_6C_P_2) },
8363   },
8364
8365   /* VEX_LEN_6D_P_2 */
8366   {
8367     { VEX_W_TABLE (VEX_W_6D_P_2) },
8368   },
8369
8370   /* VEX_LEN_6E_P_2 */
8371   {
8372     { "vmovK",          { XMScalar, Edq } },
8373     { "vmovK",          { XMScalar, Edq } },
8374   },
8375
8376   /* VEX_LEN_70_P_1 */
8377   {
8378     { VEX_W_TABLE (VEX_W_70_P_1) },
8379   },
8380
8381   /* VEX_LEN_70_P_2 */
8382   {
8383     { VEX_W_TABLE (VEX_W_70_P_2) },
8384   },
8385
8386   /* VEX_LEN_70_P_3 */
8387   {
8388     { VEX_W_TABLE (VEX_W_70_P_3) },
8389   },
8390
8391   /* VEX_LEN_71_R_2_P_2 */
8392   {
8393     { VEX_W_TABLE (VEX_W_71_R_2_P_2) },
8394   },
8395
8396   /* VEX_LEN_71_R_4_P_2 */
8397   {
8398     { VEX_W_TABLE (VEX_W_71_R_4_P_2) },
8399   },
8400
8401   /* VEX_LEN_71_R_6_P_2 */
8402   {
8403     { VEX_W_TABLE (VEX_W_71_R_6_P_2) },
8404   },
8405
8406   /* VEX_LEN_72_R_2_P_2 */
8407   {
8408     { VEX_W_TABLE (VEX_W_72_R_2_P_2) },
8409   },
8410
8411   /* VEX_LEN_72_R_4_P_2 */
8412   {
8413     { VEX_W_TABLE (VEX_W_72_R_4_P_2) },
8414   },
8415
8416   /* VEX_LEN_72_R_6_P_2 */
8417   {
8418     { VEX_W_TABLE (VEX_W_72_R_6_P_2) },
8419   },
8420
8421   /* VEX_LEN_73_R_2_P_2 */
8422   {
8423     { VEX_W_TABLE (VEX_W_73_R_2_P_2) },
8424   },
8425
8426   /* VEX_LEN_73_R_3_P_2 */
8427   {
8428     { VEX_W_TABLE (VEX_W_73_R_3_P_2) },
8429   },
8430
8431   /* VEX_LEN_73_R_6_P_2 */
8432   {
8433     { VEX_W_TABLE (VEX_W_73_R_6_P_2) },
8434   },
8435
8436   /* VEX_LEN_73_R_7_P_2 */
8437   {
8438     { VEX_W_TABLE (VEX_W_73_R_7_P_2) },
8439   },
8440
8441   /* VEX_LEN_74_P_2 */
8442   {
8443     { VEX_W_TABLE (VEX_W_74_P_2) },
8444   },
8445
8446   /* VEX_LEN_75_P_2 */
8447   {
8448     { VEX_W_TABLE (VEX_W_75_P_2) },
8449   },
8450
8451   /* VEX_LEN_76_P_2 */
8452   {
8453     { VEX_W_TABLE (VEX_W_76_P_2) },
8454   },
8455
8456   /* VEX_LEN_7E_P_1 */
8457   {
8458     { VEX_W_TABLE (VEX_W_7E_P_1) },
8459     { VEX_W_TABLE (VEX_W_7E_P_1) },
8460   },
8461
8462   /* VEX_LEN_7E_P_2 */
8463   {
8464     { "vmovK",          { Edq, XMScalar } },
8465     { "vmovK",          { Edq, XMScalar } },
8466   },
8467
8468   /* VEX_LEN_AE_R_2_M_0 */
8469   {
8470     { VEX_W_TABLE (VEX_W_AE_R_2_M_0) },
8471   },
8472
8473   /* VEX_LEN_AE_R_3_M_0 */
8474   {
8475     { VEX_W_TABLE (VEX_W_AE_R_3_M_0) },
8476   },
8477
8478   /* VEX_LEN_C2_P_1 */
8479   {
8480     { VEX_W_TABLE (VEX_W_C2_P_1) },
8481     { VEX_W_TABLE (VEX_W_C2_P_1) },
8482   },
8483
8484   /* VEX_LEN_C2_P_3 */
8485   {
8486     { VEX_W_TABLE (VEX_W_C2_P_3) },
8487     { VEX_W_TABLE (VEX_W_C2_P_3) },
8488   },
8489
8490   /* VEX_LEN_C4_P_2 */
8491   {
8492     { VEX_W_TABLE (VEX_W_C4_P_2) },
8493   },
8494
8495   /* VEX_LEN_C5_P_2 */
8496   {
8497     { VEX_W_TABLE (VEX_W_C5_P_2) },
8498   },
8499
8500   /* VEX_LEN_D1_P_2 */
8501   {
8502     { VEX_W_TABLE (VEX_W_D1_P_2) },
8503   },
8504
8505   /* VEX_LEN_D2_P_2 */
8506   {
8507     { VEX_W_TABLE (VEX_W_D2_P_2) },
8508   },
8509
8510   /* VEX_LEN_D3_P_2 */
8511   {
8512     { VEX_W_TABLE (VEX_W_D3_P_2) },
8513   },
8514
8515   /* VEX_LEN_D4_P_2 */
8516   {
8517     { VEX_W_TABLE (VEX_W_D4_P_2) },
8518   },
8519
8520   /* VEX_LEN_D5_P_2 */
8521   {
8522     { VEX_W_TABLE (VEX_W_D5_P_2) },
8523   },
8524
8525   /* VEX_LEN_D6_P_2 */
8526   {
8527     { VEX_W_TABLE (VEX_W_D6_P_2) },
8528     { VEX_W_TABLE (VEX_W_D6_P_2) },
8529   },
8530
8531   /* VEX_LEN_D7_P_2_M_1 */
8532   {
8533     { VEX_W_TABLE (VEX_W_D7_P_2_M_1) },
8534   },
8535
8536   /* VEX_LEN_D8_P_2 */
8537   {
8538     { VEX_W_TABLE (VEX_W_D8_P_2) },
8539   },
8540
8541   /* VEX_LEN_D9_P_2 */
8542   {
8543     { VEX_W_TABLE (VEX_W_D9_P_2) },
8544   },
8545
8546   /* VEX_LEN_DA_P_2 */
8547   {
8548     { VEX_W_TABLE (VEX_W_DA_P_2) },
8549   },
8550
8551   /* VEX_LEN_DB_P_2 */
8552   {
8553     { VEX_W_TABLE (VEX_W_DB_P_2) },
8554   },
8555
8556   /* VEX_LEN_DC_P_2 */
8557   {
8558     { VEX_W_TABLE (VEX_W_DC_P_2) },
8559   },
8560
8561   /* VEX_LEN_DD_P_2 */
8562   {
8563     { VEX_W_TABLE (VEX_W_DD_P_2) },
8564   },
8565
8566   /* VEX_LEN_DE_P_2 */
8567   {
8568     { VEX_W_TABLE (VEX_W_DE_P_2) },
8569   },
8570
8571   /* VEX_LEN_DF_P_2 */
8572   {
8573     { VEX_W_TABLE (VEX_W_DF_P_2) },
8574   },
8575
8576   /* VEX_LEN_E0_P_2 */
8577   {
8578     { VEX_W_TABLE (VEX_W_E0_P_2) },
8579   },
8580
8581   /* VEX_LEN_E1_P_2 */
8582   {
8583     { VEX_W_TABLE (VEX_W_E1_P_2) },
8584   },
8585
8586   /* VEX_LEN_E2_P_2 */
8587   {
8588     { VEX_W_TABLE (VEX_W_E2_P_2) },
8589   },
8590
8591   /* VEX_LEN_E3_P_2 */
8592   {
8593     { VEX_W_TABLE (VEX_W_E3_P_2) },
8594   },
8595
8596   /* VEX_LEN_E4_P_2 */
8597   {
8598     { VEX_W_TABLE (VEX_W_E4_P_2) },
8599   },
8600
8601   /* VEX_LEN_E5_P_2 */
8602   {
8603     { VEX_W_TABLE (VEX_W_E5_P_2) },
8604   },
8605
8606   /* VEX_LEN_E8_P_2 */
8607   {
8608     { VEX_W_TABLE (VEX_W_E8_P_2) },
8609   },
8610
8611   /* VEX_LEN_E9_P_2 */
8612   {
8613     { VEX_W_TABLE (VEX_W_E9_P_2) },
8614   },
8615
8616   /* VEX_LEN_EA_P_2 */
8617   {
8618     { VEX_W_TABLE (VEX_W_EA_P_2) },
8619   },
8620
8621   /* VEX_LEN_EB_P_2 */
8622   {
8623     { VEX_W_TABLE (VEX_W_EB_P_2) },
8624   },
8625
8626   /* VEX_LEN_EC_P_2 */
8627   {
8628     { VEX_W_TABLE (VEX_W_EC_P_2) },
8629   },
8630
8631   /* VEX_LEN_ED_P_2 */
8632   {
8633     { VEX_W_TABLE (VEX_W_ED_P_2) },
8634   },
8635
8636   /* VEX_LEN_EE_P_2 */
8637   {
8638     { VEX_W_TABLE (VEX_W_EE_P_2) },
8639   },
8640
8641   /* VEX_LEN_EF_P_2 */
8642   {
8643     { VEX_W_TABLE (VEX_W_EF_P_2) },
8644   },
8645
8646   /* VEX_LEN_F1_P_2 */
8647   {
8648     { VEX_W_TABLE (VEX_W_F1_P_2) },
8649   },
8650
8651   /* VEX_LEN_F2_P_2 */
8652   {
8653     { VEX_W_TABLE (VEX_W_F2_P_2) },
8654   },
8655
8656   /* VEX_LEN_F3_P_2 */
8657   {
8658     { VEX_W_TABLE (VEX_W_F3_P_2) },
8659   },
8660
8661   /* VEX_LEN_F4_P_2 */
8662   {
8663     { VEX_W_TABLE (VEX_W_F4_P_2) },
8664   },
8665
8666   /* VEX_LEN_F5_P_2 */
8667   {
8668     { VEX_W_TABLE (VEX_W_F5_P_2) },
8669   },
8670
8671   /* VEX_LEN_F6_P_2 */
8672   {
8673     { VEX_W_TABLE (VEX_W_F6_P_2) },
8674   },
8675
8676   /* VEX_LEN_F7_P_2 */
8677   {
8678     { VEX_W_TABLE (VEX_W_F7_P_2) },
8679   },
8680
8681   /* VEX_LEN_F8_P_2 */
8682   {
8683     { VEX_W_TABLE (VEX_W_F8_P_2) },
8684   },
8685
8686   /* VEX_LEN_F9_P_2 */
8687   {
8688     { VEX_W_TABLE (VEX_W_F9_P_2) },
8689   },
8690
8691   /* VEX_LEN_FA_P_2 */
8692   {
8693     { VEX_W_TABLE (VEX_W_FA_P_2) },
8694   },
8695
8696   /* VEX_LEN_FB_P_2 */
8697   {
8698     { VEX_W_TABLE (VEX_W_FB_P_2) },
8699   },
8700
8701   /* VEX_LEN_FC_P_2 */
8702   {
8703     { VEX_W_TABLE (VEX_W_FC_P_2) },
8704   },
8705
8706   /* VEX_LEN_FD_P_2 */
8707   {
8708     { VEX_W_TABLE (VEX_W_FD_P_2) },
8709   },
8710
8711   /* VEX_LEN_FE_P_2 */
8712   {
8713     { VEX_W_TABLE (VEX_W_FE_P_2) },
8714   },
8715
8716   /* VEX_LEN_3800_P_2 */
8717   {
8718     { VEX_W_TABLE (VEX_W_3800_P_2) },
8719   },
8720
8721   /* VEX_LEN_3801_P_2 */
8722   {
8723     { VEX_W_TABLE (VEX_W_3801_P_2) },
8724   },
8725
8726   /* VEX_LEN_3802_P_2 */
8727   {
8728     { VEX_W_TABLE (VEX_W_3802_P_2) },
8729   },
8730
8731   /* VEX_LEN_3803_P_2 */
8732   {
8733     { VEX_W_TABLE (VEX_W_3803_P_2) },
8734   },
8735
8736   /* VEX_LEN_3804_P_2 */
8737   {
8738     { VEX_W_TABLE (VEX_W_3804_P_2) },
8739   },
8740
8741   /* VEX_LEN_3805_P_2 */
8742   {
8743     { VEX_W_TABLE (VEX_W_3805_P_2) },
8744   },
8745
8746   /* VEX_LEN_3806_P_2 */
8747   {
8748     { VEX_W_TABLE (VEX_W_3806_P_2) },
8749   },
8750
8751   /* VEX_LEN_3807_P_2 */
8752   {
8753     { VEX_W_TABLE (VEX_W_3807_P_2) },
8754   },
8755
8756   /* VEX_LEN_3808_P_2 */
8757   {
8758     { VEX_W_TABLE (VEX_W_3808_P_2) },
8759   },
8760
8761   /* VEX_LEN_3809_P_2 */
8762   {
8763     { VEX_W_TABLE (VEX_W_3809_P_2) },
8764   },
8765
8766   /* VEX_LEN_380A_P_2 */
8767   {
8768     { VEX_W_TABLE (VEX_W_380A_P_2) },
8769   },
8770
8771   /* VEX_LEN_380B_P_2 */
8772   {
8773     { VEX_W_TABLE (VEX_W_380B_P_2) },
8774   },
8775
8776   /* VEX_LEN_3819_P_2_M_0 */
8777   {
8778     { Bad_Opcode },
8779     { VEX_W_TABLE (VEX_W_3819_P_2_M_0) },
8780   },
8781
8782   /* VEX_LEN_381A_P_2_M_0 */
8783   {
8784     { Bad_Opcode },
8785     { VEX_W_TABLE (VEX_W_381A_P_2_M_0) },
8786   },
8787
8788   /* VEX_LEN_381C_P_2 */
8789   {
8790     { VEX_W_TABLE (VEX_W_381C_P_2) },
8791   },
8792
8793   /* VEX_LEN_381D_P_2 */
8794   {
8795     { VEX_W_TABLE (VEX_W_381D_P_2) },
8796   },
8797
8798   /* VEX_LEN_381E_P_2 */
8799   {
8800     { VEX_W_TABLE (VEX_W_381E_P_2) },
8801   },
8802
8803   /* VEX_LEN_3820_P_2 */
8804   {
8805     { VEX_W_TABLE (VEX_W_3820_P_2) },
8806   },
8807
8808   /* VEX_LEN_3821_P_2 */
8809   {
8810     { VEX_W_TABLE (VEX_W_3821_P_2) },
8811   },
8812
8813   /* VEX_LEN_3822_P_2 */
8814   {
8815     { VEX_W_TABLE (VEX_W_3822_P_2) },
8816   },
8817
8818   /* VEX_LEN_3823_P_2 */
8819   {
8820     { VEX_W_TABLE (VEX_W_3823_P_2) },
8821   },
8822
8823   /* VEX_LEN_3824_P_2 */
8824   {
8825     { VEX_W_TABLE (VEX_W_3824_P_2) },
8826   },
8827
8828   /* VEX_LEN_3825_P_2 */
8829   {
8830     { VEX_W_TABLE (VEX_W_3825_P_2) },
8831   },
8832
8833   /* VEX_LEN_3828_P_2 */
8834   {
8835     { VEX_W_TABLE (VEX_W_3828_P_2) },
8836   },
8837
8838   /* VEX_LEN_3829_P_2 */
8839   {
8840     { VEX_W_TABLE (VEX_W_3829_P_2) },
8841   },
8842
8843   /* VEX_LEN_382A_P_2_M_0 */
8844   {
8845     { VEX_W_TABLE (VEX_W_382A_P_2_M_0) },
8846   },
8847
8848   /* VEX_LEN_382B_P_2 */
8849   {
8850     { VEX_W_TABLE (VEX_W_382B_P_2) },
8851   },
8852
8853   /* VEX_LEN_3830_P_2 */
8854   {
8855     { VEX_W_TABLE (VEX_W_3830_P_2) },
8856   },
8857
8858   /* VEX_LEN_3831_P_2 */
8859   {
8860     { VEX_W_TABLE (VEX_W_3831_P_2) },
8861   },
8862
8863   /* VEX_LEN_3832_P_2 */
8864   {
8865     { VEX_W_TABLE (VEX_W_3832_P_2) },
8866   },
8867
8868   /* VEX_LEN_3833_P_2 */
8869   {
8870     { VEX_W_TABLE (VEX_W_3833_P_2) },
8871   },
8872
8873   /* VEX_LEN_3834_P_2 */
8874   {
8875     { VEX_W_TABLE (VEX_W_3834_P_2) },
8876   },
8877
8878   /* VEX_LEN_3835_P_2 */
8879   {
8880     { VEX_W_TABLE (VEX_W_3835_P_2) },
8881   },
8882
8883   /* VEX_LEN_3837_P_2 */
8884   {
8885     { VEX_W_TABLE (VEX_W_3837_P_2) },
8886   },
8887
8888   /* VEX_LEN_3838_P_2 */
8889   {
8890     { VEX_W_TABLE (VEX_W_3838_P_2) },
8891   },
8892
8893   /* VEX_LEN_3839_P_2 */
8894   {
8895     { VEX_W_TABLE (VEX_W_3839_P_2) },
8896   },
8897
8898   /* VEX_LEN_383A_P_2 */
8899   {
8900     { VEX_W_TABLE (VEX_W_383A_P_2) },
8901   },
8902
8903   /* VEX_LEN_383B_P_2 */
8904   {
8905     { VEX_W_TABLE (VEX_W_383B_P_2) },
8906   },
8907
8908   /* VEX_LEN_383C_P_2 */
8909   {
8910     { VEX_W_TABLE (VEX_W_383C_P_2) },
8911   },
8912
8913   /* VEX_LEN_383D_P_2 */
8914   {
8915     { VEX_W_TABLE (VEX_W_383D_P_2) },
8916   },
8917
8918   /* VEX_LEN_383E_P_2 */
8919   {
8920     { VEX_W_TABLE (VEX_W_383E_P_2) },
8921   },
8922
8923   /* VEX_LEN_383F_P_2 */
8924   {
8925     { VEX_W_TABLE (VEX_W_383F_P_2) },
8926   },
8927
8928   /* VEX_LEN_3840_P_2 */
8929   {
8930     { VEX_W_TABLE (VEX_W_3840_P_2) },
8931   },
8932
8933   /* VEX_LEN_3841_P_2 */
8934   {
8935     { VEX_W_TABLE (VEX_W_3841_P_2) },
8936   },
8937
8938   /* VEX_LEN_38DB_P_2 */
8939   {
8940     { VEX_W_TABLE (VEX_W_38DB_P_2) },
8941   },
8942
8943   /* VEX_LEN_38DC_P_2 */
8944   {
8945     { VEX_W_TABLE (VEX_W_38DC_P_2) },
8946   },
8947
8948   /* VEX_LEN_38DD_P_2 */
8949   {
8950     { VEX_W_TABLE (VEX_W_38DD_P_2) },
8951   },
8952
8953   /* VEX_LEN_38DE_P_2 */
8954   {
8955     { VEX_W_TABLE (VEX_W_38DE_P_2) },
8956   },
8957
8958   /* VEX_LEN_38DF_P_2 */
8959   {
8960     { VEX_W_TABLE (VEX_W_38DF_P_2) },
8961   },
8962
8963   /* VEX_LEN_3A06_P_2 */
8964   {
8965     { Bad_Opcode },
8966     { VEX_W_TABLE (VEX_W_3A06_P_2) },
8967   },
8968
8969   /* VEX_LEN_3A0A_P_2 */
8970   {
8971     { VEX_W_TABLE (VEX_W_3A0A_P_2) },
8972     { VEX_W_TABLE (VEX_W_3A0A_P_2) },
8973   },
8974
8975   /* VEX_LEN_3A0B_P_2 */
8976   {
8977     { VEX_W_TABLE (VEX_W_3A0B_P_2) },
8978     { VEX_W_TABLE (VEX_W_3A0B_P_2) },
8979   },
8980
8981   /* VEX_LEN_3A0E_P_2 */
8982   {
8983     { VEX_W_TABLE (VEX_W_3A0E_P_2) },
8984   },
8985
8986   /* VEX_LEN_3A0F_P_2 */
8987   {
8988     { VEX_W_TABLE (VEX_W_3A0F_P_2) },
8989   },
8990
8991   /* VEX_LEN_3A14_P_2 */
8992   {
8993     { VEX_W_TABLE (VEX_W_3A14_P_2) },
8994   },
8995
8996   /* VEX_LEN_3A15_P_2 */
8997   {
8998     { VEX_W_TABLE (VEX_W_3A15_P_2) },
8999   },
9000
9001   /* VEX_LEN_3A16_P_2  */
9002   {
9003     { "vpextrK",        { Edq, XM, Ib } },
9004   },
9005
9006   /* VEX_LEN_3A17_P_2 */
9007   {
9008     { "vextractps",     { Edqd, XM, Ib } },
9009   },
9010
9011   /* VEX_LEN_3A18_P_2 */
9012   {
9013     { Bad_Opcode },
9014     { VEX_W_TABLE (VEX_W_3A18_P_2) },
9015   },
9016
9017   /* VEX_LEN_3A19_P_2 */
9018   {
9019     { Bad_Opcode },
9020     { VEX_W_TABLE (VEX_W_3A19_P_2) },
9021   },
9022
9023   /* VEX_LEN_3A20_P_2 */
9024   {
9025     { VEX_W_TABLE (VEX_W_3A20_P_2) },
9026   },
9027
9028   /* VEX_LEN_3A21_P_2 */
9029   {
9030     { VEX_W_TABLE (VEX_W_3A21_P_2) },
9031   },
9032
9033   /* VEX_LEN_3A22_P_2 */
9034   {
9035     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9036   },
9037
9038   /* VEX_LEN_3A41_P_2 */
9039   {
9040     { VEX_W_TABLE (VEX_W_3A41_P_2) },
9041   },
9042
9043   /* VEX_LEN_3A42_P_2 */
9044   {
9045     { VEX_W_TABLE (VEX_W_3A42_P_2) },
9046   },
9047
9048   /* VEX_LEN_3A44_P_2 */
9049   {
9050     { VEX_W_TABLE (VEX_W_3A44_P_2) },
9051   },
9052
9053   /* VEX_LEN_3A4C_P_2 */
9054   {
9055     { VEX_W_TABLE (VEX_W_3A4C_P_2) },
9056   },
9057
9058   /* VEX_LEN_3A60_P_2 */
9059   {
9060     { VEX_W_TABLE (VEX_W_3A60_P_2) },
9061   },
9062
9063   /* VEX_LEN_3A61_P_2 */
9064   {
9065     { VEX_W_TABLE (VEX_W_3A61_P_2) },
9066   },
9067
9068   /* VEX_LEN_3A62_P_2 */
9069   {
9070     { VEX_W_TABLE (VEX_W_3A62_P_2) },
9071   },
9072
9073   /* VEX_LEN_3A63_P_2 */
9074   {
9075     { VEX_W_TABLE (VEX_W_3A63_P_2) },
9076   },
9077
9078   /* VEX_LEN_3A6A_P_2 */
9079   {
9080     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9081   },
9082
9083   /* VEX_LEN_3A6B_P_2 */
9084   {
9085     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9086   },
9087
9088   /* VEX_LEN_3A6E_P_2 */
9089   {
9090     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9091   },
9092
9093   /* VEX_LEN_3A6F_P_2 */
9094   {
9095     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9096   },
9097
9098   /* VEX_LEN_3A7A_P_2 */
9099   {
9100     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9101   },
9102
9103   /* VEX_LEN_3A7B_P_2 */
9104   {
9105     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9106   },
9107
9108   /* VEX_LEN_3A7E_P_2 */
9109   {
9110     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9111   },
9112
9113   /* VEX_LEN_3A7F_P_2 */
9114   {
9115     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9116   },
9117
9118   /* VEX_LEN_3ADF_P_2 */
9119   {
9120     { VEX_W_TABLE (VEX_W_3ADF_P_2) },
9121   },
9122
9123   /* VEX_LEN_XOP_09_80 */
9124   {
9125     { "vfrczps",        { XM, EXxmm } },
9126     { "vfrczps",        { XM, EXymmq } },
9127   },
9128
9129   /* VEX_LEN_XOP_09_81 */
9130   {
9131     { "vfrczpd",        { XM, EXxmm } },
9132     { "vfrczpd",        { XM, EXymmq } },
9133   },
9134 };
9135
9136 static const struct dis386 vex_w_table[][2] = {
9137   {
9138     /* VEX_W_10_P_0 */
9139     { "vmovups",        { XM, EXx } },
9140   },
9141   {
9142     /* VEX_W_10_P_1 */
9143     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9144   },
9145   {
9146     /* VEX_W_10_P_2 */
9147     { "vmovupd",        { XM, EXx } },
9148   },
9149   {
9150     /* VEX_W_10_P_3 */
9151     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9152   },
9153   {
9154     /* VEX_W_11_P_0 */
9155     { "vmovups",        { EXxS, XM } },
9156   },
9157   {
9158     /* VEX_W_11_P_1 */
9159     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9160   },
9161   {
9162     /* VEX_W_11_P_2 */
9163     { "vmovupd",        { EXxS, XM } },
9164   },
9165   {
9166     /* VEX_W_11_P_3 */
9167     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9168   },
9169   {
9170     /* VEX_W_12_P_0_M_0 */
9171     { "vmovlps",        { XM, Vex128, EXq } },
9172   },
9173   {
9174     /* VEX_W_12_P_0_M_1 */
9175     { "vmovhlps",       { XM, Vex128, EXq } },
9176   },
9177   {
9178     /* VEX_W_12_P_1 */
9179     { "vmovsldup",      { XM, EXx } },
9180   },
9181   {
9182     /* VEX_W_12_P_2 */
9183     { "vmovlpd",        { XM, Vex128, EXq } },
9184   },
9185   {
9186     /* VEX_W_12_P_3 */
9187     { "vmovddup",       { XM, EXymmq } },
9188   },
9189   {
9190     /* VEX_W_13_M_0 */
9191     { "vmovlpX",        { EXq, XM } },
9192   },
9193   {
9194     /* VEX_W_14 */
9195     { "vunpcklpX",      { XM, Vex, EXx } },
9196   },
9197   {
9198     /* VEX_W_15 */
9199     { "vunpckhpX",      { XM, Vex, EXx } },
9200   },
9201   {
9202     /* VEX_W_16_P_0_M_0 */
9203     { "vmovhps",        { XM, Vex128, EXq } },
9204   },
9205   {
9206     /* VEX_W_16_P_0_M_1 */
9207     { "vmovlhps",       { XM, Vex128, EXq } },
9208   },
9209   {
9210     /* VEX_W_16_P_1 */
9211     { "vmovshdup",      { XM, EXx } },
9212   },
9213   {
9214     /* VEX_W_16_P_2 */
9215     { "vmovhpd",        { XM, Vex128, EXq } },
9216   },
9217   {
9218     /* VEX_W_17_M_0 */
9219     { "vmovhpX",        { EXq, XM } },
9220   },
9221   {
9222     /* VEX_W_28 */
9223     { "vmovapX",        { XM, EXx } },
9224   },
9225   {
9226     /* VEX_W_29 */
9227     { "vmovapX",        { EXxS, XM } },
9228   },
9229   {
9230     /* VEX_W_2B_M_0 */
9231     { "vmovntpX",       { Mx, XM } },
9232   },
9233   {
9234     /* VEX_W_2E_P_0 */
9235     { "vucomiss",       { XMScalar, EXdScalar } },
9236   },
9237   {
9238     /* VEX_W_2E_P_2 */
9239     { "vucomisd",       { XMScalar, EXqScalar } },
9240   },
9241   {
9242     /* VEX_W_2F_P_0 */
9243     { "vcomiss",        { XMScalar, EXdScalar } },
9244   },
9245   {
9246     /* VEX_W_2F_P_2 */
9247     { "vcomisd",        { XMScalar, EXqScalar } },
9248   },
9249   {
9250     /* VEX_W_50_M_0 */
9251     { "vmovmskpX",      { Gdq, XS } },
9252   },
9253   {
9254     /* VEX_W_51_P_0 */
9255     { "vsqrtps",        { XM, EXx } },
9256   },
9257   {
9258     /* VEX_W_51_P_1 */
9259     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
9260   },
9261   {
9262     /* VEX_W_51_P_2  */
9263     { "vsqrtpd",        { XM, EXx } },
9264   },
9265   {
9266     /* VEX_W_51_P_3 */
9267     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
9268   },
9269   {
9270     /* VEX_W_52_P_0 */
9271     { "vrsqrtps",       { XM, EXx } },
9272   },
9273   {
9274     /* VEX_W_52_P_1 */
9275     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
9276   },
9277   {
9278     /* VEX_W_53_P_0  */
9279     { "vrcpps",         { XM, EXx } },
9280   },
9281   {
9282     /* VEX_W_53_P_1  */
9283     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
9284   },
9285   {
9286     /* VEX_W_58_P_0  */
9287     { "vaddps",         { XM, Vex, EXx } },
9288   },
9289   {
9290     /* VEX_W_58_P_1  */
9291     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
9292   },
9293   {
9294     /* VEX_W_58_P_2  */
9295     { "vaddpd",         { XM, Vex, EXx } },
9296   },
9297   {
9298     /* VEX_W_58_P_3  */
9299     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
9300   },
9301   {
9302     /* VEX_W_59_P_0  */
9303     { "vmulps",         { XM, Vex, EXx } },
9304   },
9305   {
9306     /* VEX_W_59_P_1  */
9307     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
9308   },
9309   {
9310     /* VEX_W_59_P_2  */
9311     { "vmulpd",         { XM, Vex, EXx } },
9312   },
9313   {
9314     /* VEX_W_59_P_3  */
9315     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
9316   },
9317   {
9318     /* VEX_W_5A_P_0  */
9319     { "vcvtps2pd",      { XM, EXxmmq } },
9320   },
9321   {
9322     /* VEX_W_5A_P_1  */
9323     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
9324   },
9325   {
9326     /* VEX_W_5A_P_3  */
9327     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
9328   },
9329   {
9330     /* VEX_W_5B_P_0  */
9331     { "vcvtdq2ps",      { XM, EXx } },
9332   },
9333   {
9334     /* VEX_W_5B_P_1  */
9335     { "vcvttps2dq",     { XM, EXx } },
9336   },
9337   {
9338     /* VEX_W_5B_P_2  */
9339     { "vcvtps2dq",      { XM, EXx } },
9340   },
9341   {
9342     /* VEX_W_5C_P_0  */
9343     { "vsubps",         { XM, Vex, EXx } },
9344   },
9345   {
9346     /* VEX_W_5C_P_1  */
9347     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
9348   },
9349   {
9350     /* VEX_W_5C_P_2  */
9351     { "vsubpd",         { XM, Vex, EXx } },
9352   },
9353   {
9354     /* VEX_W_5C_P_3  */
9355     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
9356   },
9357   {
9358     /* VEX_W_5D_P_0  */
9359     { "vminps",         { XM, Vex, EXx } },
9360   },
9361   {
9362     /* VEX_W_5D_P_1  */
9363     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
9364   },
9365   {
9366     /* VEX_W_5D_P_2  */
9367     { "vminpd",         { XM, Vex, EXx } },
9368   },
9369   {
9370     /* VEX_W_5D_P_3  */
9371     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
9372   },
9373   {
9374     /* VEX_W_5E_P_0  */
9375     { "vdivps",         { XM, Vex, EXx } },
9376   },
9377   {
9378     /* VEX_W_5E_P_1  */
9379     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
9380   },
9381   {
9382     /* VEX_W_5E_P_2  */
9383     { "vdivpd",         { XM, Vex, EXx } },
9384   },
9385   {
9386     /* VEX_W_5E_P_3  */
9387     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
9388   },
9389   {
9390     /* VEX_W_5F_P_0  */
9391     { "vmaxps",         { XM, Vex, EXx } },
9392   },
9393   {
9394     /* VEX_W_5F_P_1  */
9395     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
9396   },
9397   {
9398     /* VEX_W_5F_P_2  */
9399     { "vmaxpd",         { XM, Vex, EXx } },
9400   },
9401   {
9402     /* VEX_W_5F_P_3  */
9403     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
9404   },
9405   {
9406     /* VEX_W_60_P_2  */
9407     { "vpunpcklbw",     { XM, Vex128, EXx } },
9408   },
9409   {
9410     /* VEX_W_61_P_2  */
9411     { "vpunpcklwd",     { XM, Vex128, EXx } },
9412   },
9413   {
9414     /* VEX_W_62_P_2  */
9415     { "vpunpckldq",     { XM, Vex128, EXx } },
9416   },
9417   {
9418     /* VEX_W_63_P_2  */
9419     { "vpacksswb",      { XM, Vex128, EXx } },
9420   },
9421   {
9422     /* VEX_W_64_P_2  */
9423     { "vpcmpgtb",       { XM, Vex128, EXx } },
9424   },
9425   {
9426     /* VEX_W_65_P_2  */
9427     { "vpcmpgtw",       { XM, Vex128, EXx } },
9428   },
9429   {
9430     /* VEX_W_66_P_2  */
9431     { "vpcmpgtd",       { XM, Vex128, EXx } },
9432   },
9433   {
9434     /* VEX_W_67_P_2  */
9435     { "vpackuswb",      { XM, Vex128, EXx } },
9436   },
9437   {
9438     /* VEX_W_68_P_2  */
9439     { "vpunpckhbw",     { XM, Vex128, EXx } },
9440   },
9441   {
9442     /* VEX_W_69_P_2  */
9443     { "vpunpckhwd",     { XM, Vex128, EXx } },
9444   },
9445   {
9446     /* VEX_W_6A_P_2  */
9447     { "vpunpckhdq",     { XM, Vex128, EXx } },
9448   },
9449   {
9450     /* VEX_W_6B_P_2  */
9451     { "vpackssdw",      { XM, Vex128, EXx } },
9452   },
9453   {
9454     /* VEX_W_6C_P_2  */
9455     { "vpunpcklqdq",    { XM, Vex128, EXx } },
9456   },
9457   {
9458     /* VEX_W_6D_P_2  */
9459     { "vpunpckhqdq",    { XM, Vex128, EXx } },
9460   },
9461   {
9462     /* VEX_W_6F_P_1  */
9463     { "vmovdqu",        { XM, EXx } },
9464   },
9465   {
9466     /* VEX_W_6F_P_2  */
9467     { "vmovdqa",        { XM, EXx } },
9468   },
9469   {
9470     /* VEX_W_70_P_1 */
9471     { "vpshufhw",       { XM, EXx, Ib } },
9472   },
9473   {
9474     /* VEX_W_70_P_2 */
9475     { "vpshufd",        { XM, EXx, Ib } },
9476   },
9477   {
9478     /* VEX_W_70_P_3 */
9479     { "vpshuflw",       { XM, EXx, Ib } },
9480   },
9481   {
9482     /* VEX_W_71_R_2_P_2  */
9483     { "vpsrlw",         { Vex128, XS, Ib } },
9484   },
9485   {
9486     /* VEX_W_71_R_4_P_2  */
9487     { "vpsraw",         { Vex128, XS, Ib } },
9488   },
9489   {
9490     /* VEX_W_71_R_6_P_2  */
9491     { "vpsllw",         { Vex128, XS, Ib } },
9492   },
9493   {
9494     /* VEX_W_72_R_2_P_2  */
9495     { "vpsrld",         { Vex128, XS, Ib } },
9496   },
9497   {
9498     /* VEX_W_72_R_4_P_2  */
9499     { "vpsrad",         { Vex128, XS, Ib } },
9500   },
9501   {
9502     /* VEX_W_72_R_6_P_2  */
9503     { "vpslld",         { Vex128, XS, Ib } },
9504   },
9505   {
9506     /* VEX_W_73_R_2_P_2  */
9507     { "vpsrlq",         { Vex128, XS, Ib } },
9508   },
9509   {
9510     /* VEX_W_73_R_3_P_2  */
9511     { "vpsrldq",        { Vex128, XS, Ib } },
9512   },
9513   {
9514     /* VEX_W_73_R_6_P_2  */
9515     { "vpsllq",         { Vex128, XS, Ib } },
9516   },
9517   {
9518     /* VEX_W_73_R_7_P_2  */
9519     { "vpslldq",        { Vex128, XS, Ib } },
9520   },
9521   {
9522     /* VEX_W_74_P_2 */
9523     { "vpcmpeqb",       { XM, Vex128, EXx } },
9524   },
9525   {
9526     /* VEX_W_75_P_2 */
9527     { "vpcmpeqw",       { XM, Vex128, EXx } },
9528   },
9529   {
9530     /* VEX_W_76_P_2 */
9531     { "vpcmpeqd",       { XM, Vex128, EXx } },
9532   },
9533   {
9534     /* VEX_W_77_P_0 */
9535     { "",               { VZERO } },
9536   },
9537   {
9538     /* VEX_W_7C_P_2 */
9539     { "vhaddpd",        { XM, Vex, EXx } },
9540   },
9541   {
9542     /* VEX_W_7C_P_3 */
9543     { "vhaddps",        { XM, Vex, EXx } },
9544   },
9545   {
9546     /* VEX_W_7D_P_2 */
9547     { "vhsubpd",        { XM, Vex, EXx } },
9548   },
9549   {
9550     /* VEX_W_7D_P_3 */
9551     { "vhsubps",        { XM, Vex, EXx } },
9552   },
9553   {
9554     /* VEX_W_7E_P_1 */
9555     { "vmovq",          { XMScalar, EXqScalar } },
9556   },
9557   {
9558     /* VEX_W_7F_P_1 */
9559     { "vmovdqu",        { EXxS, XM } },
9560   },
9561   {
9562     /* VEX_W_7F_P_2 */
9563     { "vmovdqa",        { EXxS, XM } },
9564   },
9565   {
9566     /* VEX_W_AE_R_2_M_0 */
9567     { "vldmxcsr",       { Md } },
9568   },
9569   {
9570     /* VEX_W_AE_R_3_M_0 */
9571     { "vstmxcsr",       { Md } },
9572   },
9573   {
9574     /* VEX_W_C2_P_0 */
9575     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9576   },
9577   {
9578     /* VEX_W_C2_P_1 */
9579     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
9580   },
9581   {
9582     /* VEX_W_C2_P_2 */
9583     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9584   },
9585   {
9586     /* VEX_W_C2_P_3 */
9587     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
9588   },
9589   {
9590     /* VEX_W_C4_P_2 */
9591     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9592   },
9593   {
9594     /* VEX_W_C5_P_2 */
9595     { "vpextrw",        { Gdq, XS, Ib } },
9596   },
9597   {
9598     /* VEX_W_D0_P_2 */
9599     { "vaddsubpd",      { XM, Vex, EXx } },
9600   },
9601   {
9602     /* VEX_W_D0_P_3 */
9603     { "vaddsubps",      { XM, Vex, EXx } },
9604   },
9605   {
9606     /* VEX_W_D1_P_2 */
9607     { "vpsrlw",         { XM, Vex128, EXx } },
9608   },
9609   {
9610     /* VEX_W_D2_P_2 */
9611     { "vpsrld",         { XM, Vex128, EXx } },
9612   },
9613   {
9614     /* VEX_W_D3_P_2 */
9615     { "vpsrlq",         { XM, Vex128, EXx } },
9616   },
9617   {
9618     /* VEX_W_D4_P_2 */
9619     { "vpaddq",         { XM, Vex128, EXx } },
9620   },
9621   {
9622     /* VEX_W_D5_P_2 */
9623     { "vpmullw",        { XM, Vex128, EXx } },
9624   },
9625   {
9626     /* VEX_W_D6_P_2 */
9627     { "vmovq",          { EXqScalarS, XMScalar } },
9628   },
9629   {
9630     /* VEX_W_D7_P_2_M_1 */
9631     { "vpmovmskb",      { Gdq, XS } },
9632   },
9633   {
9634     /* VEX_W_D8_P_2 */
9635     { "vpsubusb",       { XM, Vex128, EXx } },
9636   },
9637   {
9638     /* VEX_W_D9_P_2 */
9639     { "vpsubusw",       { XM, Vex128, EXx } },
9640   },
9641   {
9642     /* VEX_W_DA_P_2 */
9643     { "vpminub",        { XM, Vex128, EXx } },
9644   },
9645   {
9646     /* VEX_W_DB_P_2 */
9647     { "vpand",          { XM, Vex128, EXx } },
9648   },
9649   {
9650     /* VEX_W_DC_P_2 */
9651     { "vpaddusb",       { XM, Vex128, EXx } },
9652   },
9653   {
9654     /* VEX_W_DD_P_2 */
9655     { "vpaddusw",       { XM, Vex128, EXx } },
9656   },
9657   {
9658     /* VEX_W_DE_P_2 */
9659     { "vpmaxub",        { XM, Vex128, EXx } },
9660   },
9661   {
9662     /* VEX_W_DF_P_2 */
9663     { "vpandn",         { XM, Vex128, EXx } },
9664   },
9665   {
9666     /* VEX_W_E0_P_2  */
9667     { "vpavgb",         { XM, Vex128, EXx } },
9668   },
9669   {
9670     /* VEX_W_E1_P_2  */
9671     { "vpsraw",         { XM, Vex128, EXx } },
9672   },
9673   {
9674     /* VEX_W_E2_P_2  */
9675     { "vpsrad",         { XM, Vex128, EXx } },
9676   },
9677   {
9678     /* VEX_W_E3_P_2  */
9679     { "vpavgw",         { XM, Vex128, EXx } },
9680   },
9681   {
9682     /* VEX_W_E4_P_2  */
9683     { "vpmulhuw",       { XM, Vex128, EXx } },
9684   },
9685   {
9686     /* VEX_W_E5_P_2  */
9687     { "vpmulhw",        { XM, Vex128, EXx } },
9688   },
9689   {
9690     /* VEX_W_E6_P_1  */
9691     { "vcvtdq2pd",      { XM, EXxmmq } },
9692   },
9693   {
9694     /* VEX_W_E6_P_2  */
9695     { "vcvttpd2dq%XY",  { XMM, EXx } },
9696   },
9697   {
9698     /* VEX_W_E6_P_3  */
9699     { "vcvtpd2dq%XY",   { XMM, EXx } },
9700   },
9701   {
9702     /* VEX_W_E7_P_2_M_0 */
9703     { "vmovntdq",       { Mx, XM } },
9704   },
9705   {
9706     /* VEX_W_E8_P_2  */
9707     { "vpsubsb",        { XM, Vex128, EXx } },
9708   },
9709   {
9710     /* VEX_W_E9_P_2  */
9711     { "vpsubsw",        { XM, Vex128, EXx } },
9712   },
9713   {
9714     /* VEX_W_EA_P_2  */
9715     { "vpminsw",        { XM, Vex128, EXx } },
9716   },
9717   {
9718     /* VEX_W_EB_P_2  */
9719     { "vpor",           { XM, Vex128, EXx } },
9720   },
9721   {
9722     /* VEX_W_EC_P_2  */
9723     { "vpaddsb",        { XM, Vex128, EXx } },
9724   },
9725   {
9726     /* VEX_W_ED_P_2  */
9727     { "vpaddsw",        { XM, Vex128, EXx } },
9728   },
9729   {
9730     /* VEX_W_EE_P_2  */
9731     { "vpmaxsw",        { XM, Vex128, EXx } },
9732   },
9733   {
9734     /* VEX_W_EF_P_2  */
9735     { "vpxor",          { XM, Vex128, EXx } },
9736   },
9737   {
9738     /* VEX_W_F0_P_3_M_0 */
9739     { "vlddqu",         { XM, M } },
9740   },
9741   {
9742     /* VEX_W_F1_P_2 */
9743     { "vpsllw",         { XM, Vex128, EXx } },
9744   },
9745   {
9746     /* VEX_W_F2_P_2 */
9747     { "vpslld",         { XM, Vex128, EXx } },
9748   },
9749   {
9750     /* VEX_W_F3_P_2 */
9751     { "vpsllq",         { XM, Vex128, EXx } },
9752   },
9753   {
9754     /* VEX_W_F4_P_2 */
9755     { "vpmuludq",       { XM, Vex128, EXx } },
9756   },
9757   {
9758     /* VEX_W_F5_P_2 */
9759     { "vpmaddwd",       { XM, Vex128, EXx } },
9760   },
9761   {
9762     /* VEX_W_F6_P_2 */
9763     { "vpsadbw",        { XM, Vex128, EXx } },
9764   },
9765   {
9766     /* VEX_W_F7_P_2 */
9767     { "vmaskmovdqu",    { XM, XS } },
9768   },
9769   {
9770     /* VEX_W_F8_P_2 */
9771     { "vpsubb",         { XM, Vex128, EXx } },
9772   },
9773   {
9774     /* VEX_W_F9_P_2 */
9775     { "vpsubw",         { XM, Vex128, EXx } },
9776   },
9777   {
9778     /* VEX_W_FA_P_2 */
9779     { "vpsubd",         { XM, Vex128, EXx } },
9780   },
9781   {
9782     /* VEX_W_FB_P_2 */
9783     { "vpsubq",         { XM, Vex128, EXx } },
9784   },
9785   {
9786     /* VEX_W_FC_P_2 */
9787     { "vpaddb",         { XM, Vex128, EXx } },
9788   },
9789   {
9790     /* VEX_W_FD_P_2 */
9791     { "vpaddw",         { XM, Vex128, EXx } },
9792   },
9793   {
9794     /* VEX_W_FE_P_2 */
9795     { "vpaddd",         { XM, Vex128, EXx } },
9796   },
9797   {
9798     /* VEX_W_3800_P_2  */
9799     { "vpshufb",        { XM, Vex128, EXx } },
9800   },
9801   {
9802     /* VEX_W_3801_P_2  */
9803     { "vphaddw",        { XM, Vex128, EXx } },
9804   },
9805   {
9806     /* VEX_W_3802_P_2  */
9807     { "vphaddd",        { XM, Vex128, EXx } },
9808   },
9809   {
9810     /* VEX_W_3803_P_2  */
9811     { "vphaddsw",       { XM, Vex128, EXx } },
9812   },
9813   {
9814     /* VEX_W_3804_P_2  */
9815     { "vpmaddubsw",     { XM, Vex128, EXx } },
9816   },
9817   {
9818     /* VEX_W_3805_P_2  */
9819     { "vphsubw",        { XM, Vex128, EXx } },
9820   },
9821   {
9822     /* VEX_W_3806_P_2  */
9823     { "vphsubd",        { XM, Vex128, EXx } },
9824   },
9825   {
9826     /* VEX_W_3807_P_2  */
9827     { "vphsubsw",       { XM, Vex128, EXx } },
9828   },
9829   {
9830     /* VEX_W_3808_P_2  */
9831     { "vpsignb",        { XM, Vex128, EXx } },
9832   },
9833   {
9834     /* VEX_W_3809_P_2  */
9835     { "vpsignw",        { XM, Vex128, EXx } },
9836   },
9837   {
9838     /* VEX_W_380A_P_2  */
9839     { "vpsignd",        { XM, Vex128, EXx } },
9840   },
9841   {
9842     /* VEX_W_380B_P_2  */
9843     { "vpmulhrsw",      { XM, Vex128, EXx } },
9844   },
9845   {
9846     /* VEX_W_380C_P_2  */
9847     { "vpermilps",      { XM, Vex, EXx } },
9848   },
9849   {
9850     /* VEX_W_380D_P_2  */
9851     { "vpermilpd",      { XM, Vex, EXx } },
9852   },
9853   {
9854     /* VEX_W_380E_P_2  */
9855     { "vtestps",        { XM, EXx } },
9856   },
9857   {
9858     /* VEX_W_380F_P_2  */
9859     { "vtestpd",        { XM, EXx } },
9860   },
9861   {
9862     /* VEX_W_3817_P_2 */
9863     { "vptest",         { XM, EXx } },
9864   },
9865   {
9866     /* VEX_W_3818_P_2_M_0 */
9867     { "vbroadcastss",   { XM, Md } },
9868   },
9869   {
9870     /* VEX_W_3819_P_2_M_0 */
9871     { "vbroadcastsd",   { XM, Mq } },
9872   },
9873   {
9874     /* VEX_W_381A_P_2_M_0 */
9875     { "vbroadcastf128", { XM, Mxmm } },
9876   },
9877   {
9878     /* VEX_W_381C_P_2 */
9879     { "vpabsb",         { XM, EXx } },
9880   },
9881   {
9882     /* VEX_W_381D_P_2 */
9883     { "vpabsw",         { XM, EXx } },
9884   },
9885   {
9886     /* VEX_W_381E_P_2 */
9887     { "vpabsd",         { XM, EXx } },
9888   },
9889   {
9890     /* VEX_W_3820_P_2 */
9891     { "vpmovsxbw",      { XM, EXq } },
9892   },
9893   {
9894     /* VEX_W_3821_P_2 */
9895     { "vpmovsxbd",      { XM, EXd } },
9896   },
9897   {
9898     /* VEX_W_3822_P_2 */
9899     { "vpmovsxbq",      { XM, EXw } },
9900   },
9901   {
9902     /* VEX_W_3823_P_2 */
9903     { "vpmovsxwd",      { XM, EXq } },
9904   },
9905   {
9906     /* VEX_W_3824_P_2 */
9907     { "vpmovsxwq",      { XM, EXd } },
9908   },
9909   {
9910     /* VEX_W_3825_P_2 */
9911     { "vpmovsxdq",      { XM, EXq } },
9912   },
9913   {
9914     /* VEX_W_3828_P_2 */
9915     { "vpmuldq",        { XM, Vex128, EXx } },
9916   },
9917   {
9918     /* VEX_W_3829_P_2 */
9919     { "vpcmpeqq",       { XM, Vex128, EXx } },
9920   },
9921   {
9922     /* VEX_W_382A_P_2_M_0 */
9923     { "vmovntdqa",      { XM, Mx } },
9924   },
9925   {
9926     /* VEX_W_382B_P_2 */
9927     { "vpackusdw",      { XM, Vex128, EXx } },
9928   },
9929   {
9930     /* VEX_W_382C_P_2_M_0 */
9931     { "vmaskmovps",     { XM, Vex, Mx } },
9932   },
9933   {
9934     /* VEX_W_382D_P_2_M_0 */
9935     { "vmaskmovpd",     { XM, Vex, Mx } },
9936   },
9937   {
9938     /* VEX_W_382E_P_2_M_0 */
9939     { "vmaskmovps",     { Mx, Vex, XM } },
9940   },
9941   {
9942     /* VEX_W_382F_P_2_M_0 */
9943     { "vmaskmovpd",     { Mx, Vex, XM } },
9944   },
9945   {
9946     /* VEX_W_3830_P_2 */
9947     { "vpmovzxbw",      { XM, EXq } },
9948   },
9949   {
9950     /* VEX_W_3831_P_2 */
9951     { "vpmovzxbd",      { XM, EXd } },
9952   },
9953   {
9954     /* VEX_W_3832_P_2 */
9955     { "vpmovzxbq",      { XM, EXw } },
9956   },
9957   {
9958     /* VEX_W_3833_P_2 */
9959     { "vpmovzxwd",      { XM, EXq } },
9960   },
9961   {
9962     /* VEX_W_3834_P_2 */
9963     { "vpmovzxwq",      { XM, EXd } },
9964   },
9965   {
9966     /* VEX_W_3835_P_2 */
9967     { "vpmovzxdq",      { XM, EXq } },
9968   },
9969   {
9970     /* VEX_W_3837_P_2 */
9971     { "vpcmpgtq",       { XM, Vex128, EXx } },
9972   },
9973   {
9974     /* VEX_W_3838_P_2 */
9975     { "vpminsb",        { XM, Vex128, EXx } },
9976   },
9977   {
9978     /* VEX_W_3839_P_2 */
9979     { "vpminsd",        { XM, Vex128, EXx } },
9980   },
9981   {
9982     /* VEX_W_383A_P_2 */
9983     { "vpminuw",        { XM, Vex128, EXx } },
9984   },
9985   {
9986     /* VEX_W_383B_P_2 */
9987     { "vpminud",        { XM, Vex128, EXx } },
9988   },
9989   {
9990     /* VEX_W_383C_P_2 */
9991     { "vpmaxsb",        { XM, Vex128, EXx } },
9992   },
9993   {
9994     /* VEX_W_383D_P_2 */
9995     { "vpmaxsd",        { XM, Vex128, EXx } },
9996   },
9997   {
9998     /* VEX_W_383E_P_2 */
9999     { "vpmaxuw",        { XM, Vex128, EXx } },
10000   },
10001   {
10002     /* VEX_W_383F_P_2 */
10003     { "vpmaxud",        { XM, Vex128, EXx } },
10004   },
10005   {
10006     /* VEX_W_3840_P_2 */
10007     { "vpmulld",        { XM, Vex128, EXx } },
10008   },
10009   {
10010     /* VEX_W_3841_P_2 */
10011     { "vphminposuw",    { XM, EXx } },
10012   },
10013   {
10014     /* VEX_W_38DB_P_2 */
10015     { "vaesimc",        { XM, EXx } },
10016   },
10017   {
10018     /* VEX_W_38DC_P_2 */
10019     { "vaesenc",        { XM, Vex128, EXx } },
10020   },
10021   {
10022     /* VEX_W_38DD_P_2 */
10023     { "vaesenclast",    { XM, Vex128, EXx } },
10024   },
10025   {
10026     /* VEX_W_38DE_P_2 */
10027     { "vaesdec",        { XM, Vex128, EXx } },
10028   },
10029   {
10030     /* VEX_W_38DF_P_2 */
10031     { "vaesdeclast",    { XM, Vex128, EXx } },
10032   },
10033   {
10034     /* VEX_W_3A04_P_2 */
10035     { "vpermilps",      { XM, EXx, Ib } },
10036   },
10037   {
10038     /* VEX_W_3A05_P_2 */
10039     { "vpermilpd",      { XM, EXx, Ib } },
10040   },
10041   {
10042     /* VEX_W_3A06_P_2 */
10043     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10044   },
10045   {
10046     /* VEX_W_3A08_P_2 */
10047     { "vroundps",       { XM, EXx, Ib } },
10048   },
10049   {
10050     /* VEX_W_3A09_P_2 */
10051     { "vroundpd",       { XM, EXx, Ib } },
10052   },
10053   {
10054     /* VEX_W_3A0A_P_2 */
10055     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10056   },
10057   {
10058     /* VEX_W_3A0B_P_2 */
10059     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10060   },
10061   {
10062     /* VEX_W_3A0C_P_2 */
10063     { "vblendps",       { XM, Vex, EXx, Ib } },
10064   },
10065   {
10066     /* VEX_W_3A0D_P_2 */
10067     { "vblendpd",       { XM, Vex, EXx, Ib } },
10068   },
10069   {
10070     /* VEX_W_3A0E_P_2 */
10071     { "vpblendw",       { XM, Vex128, EXx, Ib } },
10072   },
10073   {
10074     /* VEX_W_3A0F_P_2 */
10075     { "vpalignr",       { XM, Vex128, EXx, Ib } },
10076   },
10077   {
10078     /* VEX_W_3A14_P_2 */
10079     { "vpextrb",        { Edqb, XM, Ib } },
10080   },
10081   {
10082     /* VEX_W_3A15_P_2 */
10083     { "vpextrw",        { Edqw, XM, Ib } },
10084   },
10085   {
10086     /* VEX_W_3A18_P_2 */
10087     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10088   },
10089   {
10090     /* VEX_W_3A19_P_2 */
10091     { "vextractf128",   { EXxmm, XM, Ib } },
10092   },
10093   {
10094     /* VEX_W_3A20_P_2 */
10095     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10096   },
10097   {
10098     /* VEX_W_3A21_P_2 */
10099     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10100   },
10101   {
10102     /* VEX_W_3A40_P_2 */
10103     { "vdpps",          { XM, Vex, EXx, Ib } },
10104   },
10105   {
10106     /* VEX_W_3A41_P_2 */
10107     { "vdppd",          { XM, Vex128, EXx, Ib } },
10108   },
10109   {
10110     /* VEX_W_3A42_P_2 */
10111     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
10112   },
10113   {
10114     /* VEX_W_3A44_P_2 */
10115     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10116   },
10117   {
10118     /* VEX_W_3A4A_P_2 */
10119     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10120   },
10121   {
10122     /* VEX_W_3A4B_P_2 */
10123     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10124   },
10125   {
10126     /* VEX_W_3A4C_P_2 */
10127     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
10128   },
10129   {
10130     /* VEX_W_3A60_P_2 */
10131     { "vpcmpestrm",     { XM, EXx, Ib } },
10132   },
10133   {
10134     /* VEX_W_3A61_P_2 */
10135     { "vpcmpestri",     { XM, EXx, Ib } },
10136   },
10137   {
10138     /* VEX_W_3A62_P_2 */
10139     { "vpcmpistrm",     { XM, EXx, Ib } },
10140   },
10141   {
10142     /* VEX_W_3A63_P_2 */
10143     { "vpcmpistri",     { XM, EXx, Ib } },
10144   },
10145   {
10146     /* VEX_W_3ADF_P_2 */
10147     { "vaeskeygenassist", { XM, EXx, Ib } },
10148   },
10149 };
10150
10151 static const struct dis386 mod_table[][2] = {
10152   {
10153     /* MOD_8D */
10154     { "leaS",           { Gv, M } },
10155   },
10156   {
10157     /* MOD_0F01_REG_0 */
10158     { X86_64_TABLE (X86_64_0F01_REG_0) },
10159     { RM_TABLE (RM_0F01_REG_0) },
10160   },
10161   {
10162     /* MOD_0F01_REG_1 */
10163     { X86_64_TABLE (X86_64_0F01_REG_1) },
10164     { RM_TABLE (RM_0F01_REG_1) },
10165   },
10166   {
10167     /* MOD_0F01_REG_2 */
10168     { X86_64_TABLE (X86_64_0F01_REG_2) },
10169     { RM_TABLE (RM_0F01_REG_2) },
10170   },
10171   {
10172     /* MOD_0F01_REG_3 */
10173     { X86_64_TABLE (X86_64_0F01_REG_3) },
10174     { RM_TABLE (RM_0F01_REG_3) },
10175   },
10176   {
10177     /* MOD_0F01_REG_7 */
10178     { "invlpg",         { Mb } },
10179     { RM_TABLE (RM_0F01_REG_7) },
10180   },
10181   {
10182     /* MOD_0F12_PREFIX_0 */
10183     { "movlps",         { XM, EXq } },
10184     { "movhlps",        { XM, EXq } },
10185   },
10186   {
10187     /* MOD_0F13 */
10188     { "movlpX",         { EXq, XM } },
10189   },
10190   {
10191     /* MOD_0F16_PREFIX_0 */
10192     { "movhps",         { XM, EXq } },
10193     { "movlhps",        { XM, EXq } },
10194   },
10195   {
10196     /* MOD_0F17 */
10197     { "movhpX",         { EXq, XM } },
10198   },
10199   {
10200     /* MOD_0F18_REG_0 */
10201     { "prefetchnta",    { Mb } },
10202   },
10203   {
10204     /* MOD_0F18_REG_1 */
10205     { "prefetcht0",     { Mb } },
10206   },
10207   {
10208     /* MOD_0F18_REG_2 */
10209     { "prefetcht1",     { Mb } },
10210   },
10211   {
10212     /* MOD_0F18_REG_3 */
10213     { "prefetcht2",     { Mb } },
10214   },
10215   {
10216     /* MOD_0F20 */
10217     { Bad_Opcode },
10218     { "movZ",           { Rm, Cm } },
10219   },
10220   {
10221     /* MOD_0F21 */
10222     { Bad_Opcode },
10223     { "movZ",           { Rm, Dm } },
10224   },
10225   {
10226     /* MOD_0F22 */
10227     { Bad_Opcode },
10228     { "movZ",           { Cm, Rm } },
10229   },
10230   {
10231     /* MOD_0F23 */
10232     { Bad_Opcode },
10233     { "movZ",           { Dm, Rm } },
10234   },
10235   {
10236     /* MOD_0F24 */
10237     { Bad_Opcode },
10238     { "movL",           { Rd, Td } },
10239   },
10240   {
10241     /* MOD_0F26 */
10242     { Bad_Opcode },
10243     { "movL",           { Td, Rd } },
10244   },
10245   {
10246     /* MOD_0F2B_PREFIX_0 */
10247     {"movntps",         { Mx, XM } },
10248   },
10249   {
10250     /* MOD_0F2B_PREFIX_1 */
10251     {"movntss",         { Md, XM } },
10252   },
10253   {
10254     /* MOD_0F2B_PREFIX_2 */
10255     {"movntpd",         { Mx, XM } },
10256   },
10257   {
10258     /* MOD_0F2B_PREFIX_3 */
10259     {"movntsd",         { Mq, XM } },
10260   },
10261   {
10262     /* MOD_0F51 */
10263     { Bad_Opcode },
10264     { "movmskpX",       { Gdq, XS } },
10265   },
10266   {
10267     /* MOD_0F71_REG_2 */
10268     { Bad_Opcode },
10269     { "psrlw",          { MS, Ib } },
10270   },
10271   {
10272     /* MOD_0F71_REG_4 */
10273     { Bad_Opcode },
10274     { "psraw",          { MS, Ib } },
10275   },
10276   {
10277     /* MOD_0F71_REG_6 */
10278     { Bad_Opcode },
10279     { "psllw",          { MS, Ib } },
10280   },
10281   {
10282     /* MOD_0F72_REG_2 */
10283     { Bad_Opcode },
10284     { "psrld",          { MS, Ib } },
10285   },
10286   {
10287     /* MOD_0F72_REG_4 */
10288     { Bad_Opcode },
10289     { "psrad",          { MS, Ib } },
10290   },
10291   {
10292     /* MOD_0F72_REG_6 */
10293     { Bad_Opcode },
10294     { "pslld",          { MS, Ib } },
10295   },
10296   {
10297     /* MOD_0F73_REG_2 */
10298     { Bad_Opcode },
10299     { "psrlq",          { MS, Ib } },
10300   },
10301   {
10302     /* MOD_0F73_REG_3 */
10303     { Bad_Opcode },
10304     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10305   },
10306   {
10307     /* MOD_0F73_REG_6 */
10308     { Bad_Opcode },
10309     { "psllq",          { MS, Ib } },
10310   },
10311   {
10312     /* MOD_0F73_REG_7 */
10313     { Bad_Opcode },
10314     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10315   },
10316   {
10317     /* MOD_0FAE_REG_0 */
10318     { "fxsave",         { FXSAVE } },
10319   },
10320   {
10321     /* MOD_0FAE_REG_1 */
10322     { "fxrstor",        { FXSAVE } },
10323   },
10324   {
10325     /* MOD_0FAE_REG_2 */
10326     { "ldmxcsr",        { Md } },
10327   },
10328   {
10329     /* MOD_0FAE_REG_3 */
10330     { "stmxcsr",        { Md } },
10331   },
10332   {
10333     /* MOD_0FAE_REG_4 */
10334     { "xsave",          { FXSAVE } },
10335   },
10336   {
10337     /* MOD_0FAE_REG_5 */
10338     { "xrstor",         { FXSAVE } },
10339     { RM_TABLE (RM_0FAE_REG_5) },
10340   },
10341   {
10342     /* MOD_0FAE_REG_6 */
10343     { Bad_Opcode },
10344     { RM_TABLE (RM_0FAE_REG_6) },
10345   },
10346   {
10347     /* MOD_0FAE_REG_7 */
10348     { "clflush",        { Mb } },
10349     { RM_TABLE (RM_0FAE_REG_7) },
10350   },
10351   {
10352     /* MOD_0FB2 */
10353     { "lssS",           { Gv, Mp } },
10354   },
10355   {
10356     /* MOD_0FB4 */
10357     { "lfsS",           { Gv, Mp } },
10358   },
10359   {
10360     /* MOD_0FB5 */
10361     { "lgsS",           { Gv, Mp } },
10362   },
10363   {
10364     /* MOD_0FC7_REG_6 */
10365     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10366   },
10367   {
10368     /* MOD_0FC7_REG_7 */
10369     { "vmptrst",        { Mq } },
10370   },
10371   {
10372     /* MOD_0FD7 */
10373     { Bad_Opcode },
10374     { "pmovmskb",       { Gdq, MS } },
10375   },
10376   {
10377     /* MOD_0FE7_PREFIX_2 */
10378     { "movntdq",        { Mx, XM } },
10379   },
10380   {
10381     /* MOD_0FF0_PREFIX_3 */
10382     { "lddqu",          { XM, M } },
10383   },
10384   {
10385     /* MOD_0F382A_PREFIX_2 */
10386     { "movntdqa",       { XM, Mx } },
10387   },
10388   {
10389     /* MOD_62_32BIT */
10390     { "bound{S|}",      { Gv, Ma } },
10391   },
10392   {
10393     /* MOD_C4_32BIT */
10394     { "lesS",           { Gv, Mp } },
10395     { VEX_C4_TABLE (VEX_0F) },
10396   },
10397   {
10398     /* MOD_C5_32BIT */
10399     { "ldsS",           { Gv, Mp } },
10400     { VEX_C5_TABLE (VEX_0F) },
10401   },
10402   {
10403     /* MOD_VEX_12_PREFIX_0 */
10404     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
10405     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
10406   },
10407   {
10408     /* MOD_VEX_13 */
10409     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
10410   },
10411   {
10412     /* MOD_VEX_16_PREFIX_0 */
10413     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
10414     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
10415   },
10416   {
10417     /* MOD_VEX_17 */
10418     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
10419   },
10420   {
10421     /* MOD_VEX_2B */
10422     { VEX_W_TABLE (VEX_W_2B_M_0) },
10423   },
10424   {
10425     /* MOD_VEX_50 */
10426     { Bad_Opcode },
10427     { VEX_W_TABLE (VEX_W_50_M_0) },
10428   },
10429   {
10430     /* MOD_VEX_71_REG_2 */
10431     { Bad_Opcode },
10432     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
10433   },
10434   {
10435     /* MOD_VEX_71_REG_4 */
10436     { Bad_Opcode },
10437     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
10438   },
10439   {
10440     /* MOD_VEX_71_REG_6 */
10441     { Bad_Opcode },
10442     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
10443   },
10444   {
10445     /* MOD_VEX_72_REG_2 */
10446     { Bad_Opcode },
10447     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
10448   },
10449   {
10450     /* MOD_VEX_72_REG_4 */
10451     { Bad_Opcode },
10452     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
10453   },
10454   {
10455     /* MOD_VEX_72_REG_6 */
10456     { Bad_Opcode },
10457     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
10458   },
10459   {
10460     /* MOD_VEX_73_REG_2 */
10461     { Bad_Opcode },
10462     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
10463   },
10464   {
10465     /* MOD_VEX_73_REG_3 */
10466     { Bad_Opcode },
10467     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
10468   },
10469   {
10470     /* MOD_VEX_73_REG_6 */
10471     { Bad_Opcode },
10472     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
10473   },
10474   {
10475     /* MOD_VEX_73_REG_7 */
10476     { Bad_Opcode },
10477     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
10478   },
10479   {
10480     /* MOD_VEX_AE_REG_2 */
10481     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
10482   },
10483   {
10484     /* MOD_VEX_AE_REG_3 */
10485     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
10486   },
10487   {
10488     /* MOD_VEX_D7_PREFIX_2 */
10489     { Bad_Opcode },
10490     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
10491   },
10492   {
10493     /* MOD_VEX_E7_PREFIX_2 */
10494     { VEX_W_TABLE (VEX_W_E7_P_2_M_0) },
10495   },
10496   {
10497     /* MOD_VEX_F0_PREFIX_3 */
10498     { VEX_W_TABLE (VEX_W_F0_P_3_M_0) },
10499   },
10500   {
10501     /* MOD_VEX_3818_PREFIX_2 */
10502     { VEX_W_TABLE (VEX_W_3818_P_2_M_0) },
10503   },
10504   {
10505     /* MOD_VEX_3819_PREFIX_2 */
10506     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
10507   },
10508   {
10509     /* MOD_VEX_381A_PREFIX_2 */
10510     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
10511   },
10512   {
10513     /* MOD_VEX_382A_PREFIX_2 */
10514     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
10515   },
10516   {
10517     /* MOD_VEX_382C_PREFIX_2 */
10518     { VEX_W_TABLE (VEX_W_382C_P_2_M_0) },
10519   },
10520   {
10521     /* MOD_VEX_382D_PREFIX_2 */
10522     { VEX_W_TABLE (VEX_W_382D_P_2_M_0) },
10523   },
10524   {
10525     /* MOD_VEX_382E_PREFIX_2 */
10526     { VEX_W_TABLE (VEX_W_382E_P_2_M_0) },
10527   },
10528   {
10529     /* MOD_VEX_382F_PREFIX_2 */
10530     { VEX_W_TABLE (VEX_W_382F_P_2_M_0) },
10531   },
10532 };
10533
10534 static const struct dis386 rm_table[][8] = {
10535   {
10536     /* RM_0F01_REG_0 */
10537     { Bad_Opcode },
10538     { "vmcall",         { Skip_MODRM } },
10539     { "vmlaunch",       { Skip_MODRM } },
10540     { "vmresume",       { Skip_MODRM } },
10541     { "vmxoff",         { Skip_MODRM } },
10542   },
10543   {
10544     /* RM_0F01_REG_1 */
10545     { "monitor",        { { OP_Monitor, 0 } } },
10546     { "mwait",          { { OP_Mwait, 0 } } },
10547   },
10548   {
10549     /* RM_0F01_REG_2 */
10550     { "xgetbv",         { Skip_MODRM } },
10551     { "xsetbv",         { Skip_MODRM } },
10552   },
10553   {
10554     /* RM_0F01_REG_3 */
10555     { "vmrun",          { Skip_MODRM } },
10556     { "vmmcall",        { Skip_MODRM } },
10557     { "vmload",         { Skip_MODRM } },
10558     { "vmsave",         { Skip_MODRM } },
10559     { "stgi",           { Skip_MODRM } },
10560     { "clgi",           { Skip_MODRM } },
10561     { "skinit",         { Skip_MODRM } },
10562     { "invlpga",        { Skip_MODRM } },
10563   },
10564   {
10565     /* RM_0F01_REG_7 */
10566     { "swapgs",         { Skip_MODRM } },
10567     { "rdtscp",         { Skip_MODRM } },
10568   },
10569   {
10570     /* RM_0FAE_REG_5 */
10571     { "lfence",         { Skip_MODRM } },
10572   },
10573   {
10574     /* RM_0FAE_REG_6 */
10575     { "mfence",         { Skip_MODRM } },
10576   },
10577   {
10578     /* RM_0FAE_REG_7 */
10579     { "sfence",         { Skip_MODRM } },
10580   },
10581 };
10582
10583 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10584
10585 /* We use the high bit to indicate different name for the same
10586    prefix.  */
10587 #define ADDR16_PREFIX   (0x67 | 0x100)
10588 #define ADDR32_PREFIX   (0x67 | 0x200)
10589 #define DATA16_PREFIX   (0x66 | 0x100)
10590 #define DATA32_PREFIX   (0x66 | 0x200)
10591 #define REP_PREFIX      (0xf3 | 0x100)
10592
10593 static int
10594 ckprefix (void)
10595 {
10596   int newrex, i, length;
10597   rex = 0;
10598   rex_ignored = 0;
10599   prefixes = 0;
10600   used_prefixes = 0;
10601   rex_used = 0;
10602   last_lock_prefix = -1;
10603   last_repz_prefix = -1;
10604   last_repnz_prefix = -1;
10605   last_data_prefix = -1;
10606   last_addr_prefix = -1;
10607   last_rex_prefix = -1;
10608   last_seg_prefix = -1;
10609   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10610     all_prefixes[i] = 0;
10611   i = 0;
10612   length = 0;
10613   /* The maximum instruction length is 15bytes.  */
10614   while (length < MAX_CODE_LENGTH - 1)
10615     {
10616       FETCH_DATA (the_info, codep + 1);
10617       newrex = 0;
10618       switch (*codep)
10619         {
10620         /* REX prefixes family.  */
10621         case 0x40:
10622         case 0x41:
10623         case 0x42:
10624         case 0x43:
10625         case 0x44:
10626         case 0x45:
10627         case 0x46:
10628         case 0x47:
10629         case 0x48:
10630         case 0x49:
10631         case 0x4a:
10632         case 0x4b:
10633         case 0x4c:
10634         case 0x4d:
10635         case 0x4e:
10636         case 0x4f:
10637           if (address_mode == mode_64bit)
10638             newrex = *codep;
10639           else
10640             return 1;
10641           last_rex_prefix = i;
10642           break;
10643         case 0xf3:
10644           prefixes |= PREFIX_REPZ;
10645           last_repz_prefix = i;
10646           break;
10647         case 0xf2:
10648           prefixes |= PREFIX_REPNZ;
10649           last_repnz_prefix = i;
10650           break;
10651         case 0xf0:
10652           prefixes |= PREFIX_LOCK;
10653           last_lock_prefix = i;
10654           break;
10655         case 0x2e:
10656           prefixes |= PREFIX_CS;
10657           last_seg_prefix = i;
10658           break;
10659         case 0x36:
10660           prefixes |= PREFIX_SS;
10661           last_seg_prefix = i;
10662           break;
10663         case 0x3e:
10664           prefixes |= PREFIX_DS;
10665           last_seg_prefix = i;
10666           break;
10667         case 0x26:
10668           prefixes |= PREFIX_ES;
10669           last_seg_prefix = i;
10670           break;
10671         case 0x64:
10672           prefixes |= PREFIX_FS;
10673           last_seg_prefix = i;
10674           break;
10675         case 0x65:
10676           prefixes |= PREFIX_GS;
10677           last_seg_prefix = i;
10678           break;
10679         case 0x66:
10680           prefixes |= PREFIX_DATA;
10681           last_data_prefix = i;
10682           break;
10683         case 0x67:
10684           prefixes |= PREFIX_ADDR;
10685           last_addr_prefix = i;
10686           break;
10687         case FWAIT_OPCODE:
10688           /* fwait is really an instruction.  If there are prefixes
10689              before the fwait, they belong to the fwait, *not* to the
10690              following instruction.  */
10691           if (prefixes || rex)
10692             {
10693               prefixes |= PREFIX_FWAIT;
10694               codep++;
10695               return 1;
10696             }
10697           prefixes = PREFIX_FWAIT;
10698           break;
10699         default:
10700           return 1;
10701         }
10702       /* Rex is ignored when followed by another prefix.  */
10703       if (rex)
10704         {
10705           rex_used = rex;
10706           return 1;
10707         }
10708       if (*codep != FWAIT_OPCODE)
10709         all_prefixes[i++] = *codep;
10710       rex = newrex;
10711       codep++;
10712       length++;
10713     }
10714   return 0;
10715 }
10716
10717 static int
10718 seg_prefix (int pref)
10719 {
10720   switch (pref)
10721     {
10722     case 0x2e:
10723       return PREFIX_CS;
10724     case 0x36:
10725       return PREFIX_SS;
10726     case 0x3e:
10727       return PREFIX_DS;
10728     case 0x26:
10729       return PREFIX_ES;
10730     case 0x64:
10731       return PREFIX_FS;
10732     case 0x65:
10733       return PREFIX_GS;
10734     default:
10735       return 0;
10736     }
10737 }
10738
10739 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10740    prefix byte.  */
10741
10742 static const char *
10743 prefix_name (int pref, int sizeflag)
10744 {
10745   static const char *rexes [16] =
10746     {
10747       "rex",            /* 0x40 */
10748       "rex.B",          /* 0x41 */
10749       "rex.X",          /* 0x42 */
10750       "rex.XB",         /* 0x43 */
10751       "rex.R",          /* 0x44 */
10752       "rex.RB",         /* 0x45 */
10753       "rex.RX",         /* 0x46 */
10754       "rex.RXB",        /* 0x47 */
10755       "rex.W",          /* 0x48 */
10756       "rex.WB",         /* 0x49 */
10757       "rex.WX",         /* 0x4a */
10758       "rex.WXB",        /* 0x4b */
10759       "rex.WR",         /* 0x4c */
10760       "rex.WRB",        /* 0x4d */
10761       "rex.WRX",        /* 0x4e */
10762       "rex.WRXB",       /* 0x4f */
10763     };
10764
10765   switch (pref)
10766     {
10767     /* REX prefixes family.  */
10768     case 0x40:
10769     case 0x41:
10770     case 0x42:
10771     case 0x43:
10772     case 0x44:
10773     case 0x45:
10774     case 0x46:
10775     case 0x47:
10776     case 0x48:
10777     case 0x49:
10778     case 0x4a:
10779     case 0x4b:
10780     case 0x4c:
10781     case 0x4d:
10782     case 0x4e:
10783     case 0x4f:
10784       return rexes [pref - 0x40];
10785     case 0xf3:
10786       return "repz";
10787     case 0xf2:
10788       return "repnz";
10789     case 0xf0:
10790       return "lock";
10791     case 0x2e:
10792       return "cs";
10793     case 0x36:
10794       return "ss";
10795     case 0x3e:
10796       return "ds";
10797     case 0x26:
10798       return "es";
10799     case 0x64:
10800       return "fs";
10801     case 0x65:
10802       return "gs";
10803     case 0x66:
10804       return (sizeflag & DFLAG) ? "data16" : "data32";
10805     case 0x67:
10806       if (address_mode == mode_64bit)
10807         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10808       else
10809         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10810     case FWAIT_OPCODE:
10811       return "fwait";
10812     case ADDR16_PREFIX:
10813       return "addr16";
10814     case ADDR32_PREFIX:
10815       return "addr32";
10816     case DATA16_PREFIX:
10817       return "data16";
10818     case DATA32_PREFIX:
10819       return "data32";
10820     case REP_PREFIX:
10821       return "rep";
10822     default:
10823       return NULL;
10824     }
10825 }
10826
10827 static char op_out[MAX_OPERANDS][100];
10828 static int op_ad, op_index[MAX_OPERANDS];
10829 static int two_source_ops;
10830 static bfd_vma op_address[MAX_OPERANDS];
10831 static bfd_vma op_riprel[MAX_OPERANDS];
10832 static bfd_vma start_pc;
10833
10834 /*
10835  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10836  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10837  *   section of the "Virtual 8086 Mode" chapter.)
10838  * 'pc' should be the address of this instruction, it will
10839  *   be used to print the target address if this is a relative jump or call
10840  * The function returns the length of this instruction in bytes.
10841  */
10842
10843 static char intel_syntax;
10844 static char intel_mnemonic = !SYSV386_COMPAT;
10845 static char open_char;
10846 static char close_char;
10847 static char separator_char;
10848 static char scale_char;
10849
10850 /* Here for backwards compatibility.  When gdb stops using
10851    print_insn_i386_att and print_insn_i386_intel these functions can
10852    disappear, and print_insn_i386 be merged into print_insn.  */
10853 int
10854 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10855 {
10856   intel_syntax = 0;
10857
10858   return print_insn (pc, info);
10859 }
10860
10861 int
10862 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10863 {
10864   intel_syntax = 1;
10865
10866   return print_insn (pc, info);
10867 }
10868
10869 int
10870 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10871 {
10872   intel_syntax = -1;
10873
10874   return print_insn (pc, info);
10875 }
10876
10877 void
10878 print_i386_disassembler_options (FILE *stream)
10879 {
10880   fprintf (stream, _("\n\
10881 The following i386/x86-64 specific disassembler options are supported for use\n\
10882 with the -M switch (multiple options should be separated by commas):\n"));
10883
10884   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
10885   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
10886   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
10887   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
10888   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
10889   fprintf (stream, _("  att-mnemonic\n"
10890                      "              Display instruction in AT&T mnemonic\n"));
10891   fprintf (stream, _("  intel-mnemonic\n"
10892                      "              Display instruction in Intel mnemonic\n"));
10893   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
10894   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
10895   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
10896   fprintf (stream, _("  data32      Assume 32bit data size\n"));
10897   fprintf (stream, _("  data16      Assume 16bit data size\n"));
10898   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
10899 }
10900
10901 /* Bad opcode.  */
10902 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10903
10904 /* Get a pointer to struct dis386 with a valid name.  */
10905
10906 static const struct dis386 *
10907 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10908 {
10909   int vindex, vex_table_index;
10910
10911   if (dp->name != NULL)
10912     return dp;
10913
10914   switch (dp->op[0].bytemode)
10915     {
10916     case USE_REG_TABLE:
10917       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
10918       break;
10919
10920     case USE_MOD_TABLE:
10921       vindex = modrm.mod == 0x3 ? 1 : 0;
10922       dp = &mod_table[dp->op[1].bytemode][vindex];
10923       break;
10924
10925     case USE_RM_TABLE:
10926       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10927       break;
10928
10929     case USE_PREFIX_TABLE:
10930       if (need_vex)
10931         {
10932           /* The prefix in VEX is implicit.  */
10933           switch (vex.prefix)
10934             {
10935             case 0:
10936               vindex = 0;
10937               break;
10938             case REPE_PREFIX_OPCODE:
10939               vindex = 1;
10940               break;
10941             case DATA_PREFIX_OPCODE:
10942               vindex = 2;
10943               break;
10944             case REPNE_PREFIX_OPCODE:
10945               vindex = 3;
10946               break;
10947             default:
10948               abort ();
10949               break;
10950             }
10951         }
10952       else
10953         {
10954           vindex = 0;
10955           used_prefixes |= (prefixes & PREFIX_REPZ);
10956           if (prefixes & PREFIX_REPZ)
10957             {
10958               vindex = 1;
10959               all_prefixes[last_repz_prefix] = 0;
10960             }
10961           else
10962             {
10963               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10964                  PREFIX_DATA.  */
10965               used_prefixes |= (prefixes & PREFIX_REPNZ);
10966               if (prefixes & PREFIX_REPNZ)
10967                 {
10968                   vindex = 3;
10969                   all_prefixes[last_repnz_prefix] = 0;
10970                 }
10971               else
10972                 {
10973                   used_prefixes |= (prefixes & PREFIX_DATA);
10974                   if (prefixes & PREFIX_DATA)
10975                     {
10976                       vindex = 2;
10977                       all_prefixes[last_data_prefix] = 0;
10978                     }
10979                 }
10980             }
10981         }
10982       dp = &prefix_table[dp->op[1].bytemode][vindex];
10983       break;
10984
10985     case USE_X86_64_TABLE:
10986       vindex = address_mode == mode_64bit ? 1 : 0;
10987       dp = &x86_64_table[dp->op[1].bytemode][vindex];
10988       break;
10989
10990     case USE_3BYTE_TABLE:
10991       FETCH_DATA (info, codep + 2);
10992       vindex = *codep++;
10993       dp = &three_byte_table[dp->op[1].bytemode][vindex];
10994       modrm.mod = (*codep >> 6) & 3;
10995       modrm.reg = (*codep >> 3) & 7;
10996       modrm.rm = *codep & 7;
10997       break;
10998
10999     case USE_VEX_LEN_TABLE:
11000       if (!need_vex)
11001         abort ();
11002
11003       switch (vex.length)
11004         {
11005         case 128:
11006           vindex = 0;
11007           break;
11008         case 256:
11009           vindex = 1;
11010           break;
11011         default:
11012           abort ();
11013           break;
11014         }
11015
11016       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11017       break;
11018
11019     case USE_XOP_8F_TABLE:
11020       FETCH_DATA (info, codep + 3);
11021       /* All bits in the REX prefix are ignored.  */
11022       rex_ignored = rex;
11023       rex = ~(*codep >> 5) & 0x7;
11024
11025       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11026       switch ((*codep & 0x1f))
11027         {
11028         default:
11029           BadOp ();
11030         case 0x8:
11031           vex_table_index = XOP_08;
11032           break;
11033         case 0x9:
11034           vex_table_index = XOP_09;
11035           break;
11036         case 0xa:
11037           vex_table_index = XOP_0A;
11038           break;
11039         }
11040       codep++;
11041       vex.w = *codep & 0x80;
11042       if (vex.w && address_mode == mode_64bit)
11043         rex |= REX_W;
11044
11045       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11046       if (address_mode != mode_64bit
11047           && vex.register_specifier > 0x7)
11048         BadOp ();
11049
11050       vex.length = (*codep & 0x4) ? 256 : 128;
11051       switch ((*codep & 0x3))
11052         {
11053         case 0:
11054           vex.prefix = 0;
11055           break;
11056         case 1:
11057           vex.prefix = DATA_PREFIX_OPCODE;
11058           break;
11059         case 2:
11060           vex.prefix = REPE_PREFIX_OPCODE;
11061           break;
11062         case 3:
11063           vex.prefix = REPNE_PREFIX_OPCODE;
11064           break;
11065         }
11066       need_vex = 1;
11067       need_vex_reg = 1;
11068       codep++;
11069       vindex = *codep++;
11070       dp = &xop_table[vex_table_index][vindex];
11071
11072       FETCH_DATA (info, codep + 1);
11073       modrm.mod = (*codep >> 6) & 3;
11074       modrm.reg = (*codep >> 3) & 7;
11075       modrm.rm = *codep & 7;
11076       break;
11077
11078     case USE_VEX_C4_TABLE:
11079       FETCH_DATA (info, codep + 3);
11080       /* All bits in the REX prefix are ignored.  */
11081       rex_ignored = rex;
11082       rex = ~(*codep >> 5) & 0x7;
11083       switch ((*codep & 0x1f))
11084         {
11085         default:
11086           BadOp ();
11087         case 0x1:
11088           vex_table_index = VEX_0F;
11089           break;
11090         case 0x2:
11091           vex_table_index = VEX_0F38;
11092           break;
11093         case 0x3:
11094           vex_table_index = VEX_0F3A;
11095           break;
11096         }
11097       codep++;
11098       vex.w = *codep & 0x80;
11099       if (vex.w && address_mode == mode_64bit)
11100         rex |= REX_W;
11101
11102       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11103       if (address_mode != mode_64bit
11104           && vex.register_specifier > 0x7)
11105         BadOp ();
11106
11107       vex.length = (*codep & 0x4) ? 256 : 128;
11108       switch ((*codep & 0x3))
11109         {
11110         case 0:
11111           vex.prefix = 0;
11112           break;
11113         case 1:
11114           vex.prefix = DATA_PREFIX_OPCODE;
11115           break;
11116         case 2:
11117           vex.prefix = REPE_PREFIX_OPCODE;
11118           break;
11119         case 3:
11120           vex.prefix = REPNE_PREFIX_OPCODE;
11121           break;
11122         }
11123       need_vex = 1;
11124       need_vex_reg = 1;
11125       codep++;
11126       vindex = *codep++;
11127       dp = &vex_table[vex_table_index][vindex];
11128       /* There is no MODRM byte for VEX [82|77].  */
11129       if (vindex != 0x77 && vindex != 0x82)
11130         {
11131           FETCH_DATA (info, codep + 1);
11132           modrm.mod = (*codep >> 6) & 3;
11133           modrm.reg = (*codep >> 3) & 7;
11134           modrm.rm = *codep & 7;
11135         }
11136       break;
11137
11138     case USE_VEX_C5_TABLE:
11139       FETCH_DATA (info, codep + 2);
11140       /* All bits in the REX prefix are ignored.  */
11141       rex_ignored = rex;
11142       rex = (*codep & 0x80) ? 0 : REX_R;
11143
11144       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11145       if (address_mode != mode_64bit
11146           && vex.register_specifier > 0x7)
11147         BadOp ();
11148
11149       vex.w = 0;
11150
11151       vex.length = (*codep & 0x4) ? 256 : 128;
11152       switch ((*codep & 0x3))
11153         {
11154         case 0:
11155           vex.prefix = 0;
11156           break;
11157         case 1:
11158           vex.prefix = DATA_PREFIX_OPCODE;
11159           break;
11160         case 2:
11161           vex.prefix = REPE_PREFIX_OPCODE;
11162           break;
11163         case 3:
11164           vex.prefix = REPNE_PREFIX_OPCODE;
11165           break;
11166         }
11167       need_vex = 1;
11168       need_vex_reg = 1;
11169       codep++;
11170       vindex = *codep++;
11171       dp = &vex_table[dp->op[1].bytemode][vindex];
11172       /* There is no MODRM byte for VEX [82|77].  */
11173       if (vindex != 0x77 && vindex != 0x82)
11174         {
11175           FETCH_DATA (info, codep + 1);
11176           modrm.mod = (*codep >> 6) & 3;
11177           modrm.reg = (*codep >> 3) & 7;
11178           modrm.rm = *codep & 7;
11179         }
11180       break;
11181
11182     case USE_VEX_W_TABLE:
11183       if (!need_vex)
11184         abort ();
11185
11186       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11187       break;
11188
11189     case 0:
11190       dp = &bad_opcode;
11191       break;
11192
11193     default:
11194       abort ();
11195     }
11196
11197   if (dp->name != NULL)
11198     return dp;
11199   else
11200     return get_valid_dis386 (dp, info);
11201 }
11202
11203 static int
11204 print_insn (bfd_vma pc, disassemble_info *info)
11205 {
11206   const struct dis386 *dp;
11207   int i;
11208   char *op_txt[MAX_OPERANDS];
11209   int needcomma;
11210   int sizeflag;
11211   const char *p;
11212   struct dis_private priv;
11213   unsigned char op;
11214   int prefix_length;
11215   int default_prefixes;
11216
11217   if (info->mach == bfd_mach_x86_64_intel_syntax
11218       || info->mach == bfd_mach_x86_64
11219       || info->mach == bfd_mach_l1om
11220       || info->mach == bfd_mach_l1om_intel_syntax)
11221     address_mode = mode_64bit;
11222   else
11223     address_mode = mode_32bit;
11224
11225   if (intel_syntax == (char) -1)
11226     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11227                     || info->mach == bfd_mach_x86_64_intel_syntax
11228                     || info->mach == bfd_mach_l1om_intel_syntax);
11229
11230   if (info->mach == bfd_mach_i386_i386
11231       || info->mach == bfd_mach_x86_64
11232       || info->mach == bfd_mach_l1om
11233       || info->mach == bfd_mach_i386_i386_intel_syntax
11234       || info->mach == bfd_mach_x86_64_intel_syntax
11235       || info->mach == bfd_mach_l1om_intel_syntax)
11236     priv.orig_sizeflag = AFLAG | DFLAG;
11237   else if (info->mach == bfd_mach_i386_i8086)
11238     priv.orig_sizeflag = 0;
11239   else
11240     abort ();
11241
11242   for (p = info->disassembler_options; p != NULL; )
11243     {
11244       if (CONST_STRNEQ (p, "x86-64"))
11245         {
11246           address_mode = mode_64bit;
11247           priv.orig_sizeflag = AFLAG | DFLAG;
11248         }
11249       else if (CONST_STRNEQ (p, "i386"))
11250         {
11251           address_mode = mode_32bit;
11252           priv.orig_sizeflag = AFLAG | DFLAG;
11253         }
11254       else if (CONST_STRNEQ (p, "i8086"))
11255         {
11256           address_mode = mode_16bit;
11257           priv.orig_sizeflag = 0;
11258         }
11259       else if (CONST_STRNEQ (p, "intel"))
11260         {
11261           intel_syntax = 1;
11262           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11263             intel_mnemonic = 1;
11264         }
11265       else if (CONST_STRNEQ (p, "att"))
11266         {
11267           intel_syntax = 0;
11268           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11269             intel_mnemonic = 0;
11270         }
11271       else if (CONST_STRNEQ (p, "addr"))
11272         {
11273           if (address_mode == mode_64bit)
11274             {
11275               if (p[4] == '3' && p[5] == '2')
11276                 priv.orig_sizeflag &= ~AFLAG;
11277               else if (p[4] == '6' && p[5] == '4')
11278                 priv.orig_sizeflag |= AFLAG;
11279             }
11280           else
11281             {
11282               if (p[4] == '1' && p[5] == '6')
11283                 priv.orig_sizeflag &= ~AFLAG;
11284               else if (p[4] == '3' && p[5] == '2')
11285                 priv.orig_sizeflag |= AFLAG;
11286             }
11287         }
11288       else if (CONST_STRNEQ (p, "data"))
11289         {
11290           if (p[4] == '1' && p[5] == '6')
11291             priv.orig_sizeflag &= ~DFLAG;
11292           else if (p[4] == '3' && p[5] == '2')
11293             priv.orig_sizeflag |= DFLAG;
11294         }
11295       else if (CONST_STRNEQ (p, "suffix"))
11296         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11297
11298       p = strchr (p, ',');
11299       if (p != NULL)
11300         p++;
11301     }
11302
11303   if (intel_syntax)
11304     {
11305       names64 = intel_names64;
11306       names32 = intel_names32;
11307       names16 = intel_names16;
11308       names8 = intel_names8;
11309       names8rex = intel_names8rex;
11310       names_seg = intel_names_seg;
11311       names_mm = intel_names_mm;
11312       names_xmm = intel_names_xmm;
11313       names_ymm = intel_names_ymm;
11314       index64 = intel_index64;
11315       index32 = intel_index32;
11316       index16 = intel_index16;
11317       open_char = '[';
11318       close_char = ']';
11319       separator_char = '+';
11320       scale_char = '*';
11321     }
11322   else
11323     {
11324       names64 = att_names64;
11325       names32 = att_names32;
11326       names16 = att_names16;
11327       names8 = att_names8;
11328       names8rex = att_names8rex;
11329       names_seg = att_names_seg;
11330       names_mm = att_names_mm;
11331       names_xmm = att_names_xmm;
11332       names_ymm = att_names_ymm;
11333       index64 = att_index64;
11334       index32 = att_index32;
11335       index16 = att_index16;
11336       open_char = '(';
11337       close_char =  ')';
11338       separator_char = ',';
11339       scale_char = ',';
11340     }
11341
11342   /* The output looks better if we put 7 bytes on a line, since that
11343      puts most long word instructions on a single line.  Use 8 bytes
11344      for Intel L1OM.  */
11345   if (info->mach == bfd_mach_l1om
11346       || info->mach == bfd_mach_l1om_intel_syntax)
11347     info->bytes_per_line = 8;
11348   else
11349     info->bytes_per_line = 7;
11350
11351   info->private_data = &priv;
11352   priv.max_fetched = priv.the_buffer;
11353   priv.insn_start = pc;
11354
11355   obuf[0] = 0;
11356   for (i = 0; i < MAX_OPERANDS; ++i)
11357     {
11358       op_out[i][0] = 0;
11359       op_index[i] = -1;
11360     }
11361
11362   the_info = info;
11363   start_pc = pc;
11364   start_codep = priv.the_buffer;
11365   codep = priv.the_buffer;
11366
11367   if (setjmp (priv.bailout) != 0)
11368     {
11369       const char *name;
11370
11371       /* Getting here means we tried for data but didn't get it.  That
11372          means we have an incomplete instruction of some sort.  Just
11373          print the first byte as a prefix or a .byte pseudo-op.  */
11374       if (codep > priv.the_buffer)
11375         {
11376           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11377           if (name != NULL)
11378             (*info->fprintf_func) (info->stream, "%s", name);
11379           else
11380             {
11381               /* Just print the first byte as a .byte instruction.  */
11382               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11383                                      (unsigned int) priv.the_buffer[0]);
11384             }
11385
11386           return 1;
11387         }
11388
11389       return -1;
11390     }
11391
11392   obufp = obuf;
11393   sizeflag = priv.orig_sizeflag;
11394
11395   if (!ckprefix () || rex_used)
11396     {
11397       /* Too many prefixes or unused REX prefixes.  */
11398       for (i = 0;
11399            all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11400            i++)
11401         (*info->fprintf_func) (info->stream, "%s",
11402                                prefix_name (all_prefixes[i], sizeflag));
11403       return 1;
11404     }
11405
11406   insn_codep = codep;
11407
11408   FETCH_DATA (info, codep + 1);
11409   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11410
11411   if (((prefixes & PREFIX_FWAIT)
11412        && ((*codep < 0xd8) || (*codep > 0xdf))))
11413     {
11414       (*info->fprintf_func) (info->stream, "fwait");
11415       return 1;
11416     }
11417
11418   op = 0;
11419
11420   if (*codep == 0x0f)
11421     {
11422       unsigned char threebyte;
11423       FETCH_DATA (info, codep + 2);
11424       threebyte = *++codep;
11425       dp = &dis386_twobyte[threebyte];
11426       need_modrm = twobyte_has_modrm[*codep];
11427       codep++;
11428     }
11429   else
11430     {
11431       dp = &dis386[*codep];
11432       need_modrm = onebyte_has_modrm[*codep];
11433       codep++;
11434     }
11435
11436   if ((prefixes & PREFIX_REPZ))
11437     used_prefixes |= PREFIX_REPZ;
11438   if ((prefixes & PREFIX_REPNZ))
11439     used_prefixes |= PREFIX_REPNZ;
11440   if ((prefixes & PREFIX_LOCK))
11441     used_prefixes |= PREFIX_LOCK;
11442
11443   default_prefixes = 0;
11444   if (prefixes & PREFIX_ADDR)
11445     {
11446       sizeflag ^= AFLAG;
11447       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11448         {
11449           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11450             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11451           else
11452             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11453           default_prefixes |= PREFIX_ADDR;
11454         }
11455     }
11456
11457   if ((prefixes & PREFIX_DATA))
11458     {
11459       sizeflag ^= DFLAG;
11460       if (dp->op[2].bytemode == cond_jump_mode
11461           && dp->op[0].bytemode == v_mode
11462           && !intel_syntax)
11463         {
11464           if (sizeflag & DFLAG)
11465             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11466           else
11467             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11468           default_prefixes |= PREFIX_DATA;
11469         }
11470       else if (rex & REX_W)
11471         {
11472           /* REX_W will override PREFIX_DATA.  */
11473           default_prefixes |= PREFIX_DATA;
11474         }
11475     }
11476
11477   if (need_modrm)
11478     {
11479       FETCH_DATA (info, codep + 1);
11480       modrm.mod = (*codep >> 6) & 3;
11481       modrm.reg = (*codep >> 3) & 7;
11482       modrm.rm = *codep & 7;
11483     }
11484
11485    need_vex = 0;
11486    need_vex_reg = 0;
11487    vex_w_done = 0;
11488
11489   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11490     {
11491       dofloat (sizeflag);
11492     }
11493   else
11494     {
11495       dp = get_valid_dis386 (dp, info);
11496       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11497         {
11498           for (i = 0; i < MAX_OPERANDS; ++i)
11499             {
11500               obufp = op_out[i];
11501               op_ad = MAX_OPERANDS - 1 - i;
11502               if (dp->op[i].rtn)
11503                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11504             }
11505         }
11506     }
11507
11508   /* See if any prefixes were not used.  If so, print the first one
11509      separately.  If we don't do this, we'll wind up printing an
11510      instruction stream which does not precisely correspond to the
11511      bytes we are disassembling.  */
11512   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11513     {
11514       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11515         if (all_prefixes[i])
11516           {
11517             const char *name;
11518             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11519             if (name == NULL)
11520               name = INTERNAL_DISASSEMBLER_ERROR;
11521             (*info->fprintf_func) (info->stream, "%s", name);
11522             return 1;
11523           }
11524     }
11525
11526   /* Check if the REX prefix is used.  */
11527   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11528     all_prefixes[last_rex_prefix] = 0;
11529
11530   /* Check if the SEG prefix is used.  */
11531   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11532                    | PREFIX_FS | PREFIX_GS)) != 0
11533       && (used_prefixes
11534           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11535     all_prefixes[last_seg_prefix] = 0;
11536
11537   /* Check if the ADDR prefix is used.  */
11538   if ((prefixes & PREFIX_ADDR) != 0
11539       && (used_prefixes & PREFIX_ADDR) != 0)
11540     all_prefixes[last_addr_prefix] = 0;
11541
11542   /* Check if the DATA prefix is used.  */
11543   if ((prefixes & PREFIX_DATA) != 0
11544       && (used_prefixes & PREFIX_DATA) != 0)
11545     all_prefixes[last_data_prefix] = 0;
11546
11547   prefix_length = 0;
11548   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11549     if (all_prefixes[i])
11550       {
11551         const char *name;
11552         name = prefix_name (all_prefixes[i], sizeflag);
11553         if (name == NULL)
11554           abort ();
11555         prefix_length += strlen (name) + 1;
11556         (*info->fprintf_func) (info->stream, "%s ", name);
11557       }
11558
11559   /* Check maximum code length.  */
11560   if ((codep - start_codep) > MAX_CODE_LENGTH)
11561     {
11562       (*info->fprintf_func) (info->stream, "(bad)");
11563       return MAX_CODE_LENGTH;
11564     }
11565
11566   obufp = mnemonicendp;
11567   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11568     oappend (" ");
11569   oappend (" ");
11570   (*info->fprintf_func) (info->stream, "%s", obuf);
11571
11572   /* The enter and bound instructions are printed with operands in the same
11573      order as the intel book; everything else is printed in reverse order.  */
11574   if (intel_syntax || two_source_ops)
11575     {
11576       bfd_vma riprel;
11577
11578       for (i = 0; i < MAX_OPERANDS; ++i)
11579         op_txt[i] = op_out[i];
11580
11581       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11582         {
11583           op_ad = op_index[i];
11584           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11585           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11586           riprel = op_riprel[i];
11587           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11588           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11589         }
11590     }
11591   else
11592     {
11593       for (i = 0; i < MAX_OPERANDS; ++i)
11594         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11595     }
11596
11597   needcomma = 0;
11598   for (i = 0; i < MAX_OPERANDS; ++i)
11599     if (*op_txt[i])
11600       {
11601         if (needcomma)
11602           (*info->fprintf_func) (info->stream, ",");
11603         if (op_index[i] != -1 && !op_riprel[i])
11604           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11605         else
11606           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11607         needcomma = 1;
11608       }
11609
11610   for (i = 0; i < MAX_OPERANDS; i++)
11611     if (op_index[i] != -1 && op_riprel[i])
11612       {
11613         (*info->fprintf_func) (info->stream, "        # ");
11614         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11615                                                 + op_address[op_index[i]]), info);
11616         break;
11617       }
11618   return codep - priv.the_buffer;
11619 }
11620
11621 static const char *float_mem[] = {
11622   /* d8 */
11623   "fadd{s|}",
11624   "fmul{s|}",
11625   "fcom{s|}",
11626   "fcomp{s|}",
11627   "fsub{s|}",
11628   "fsubr{s|}",
11629   "fdiv{s|}",
11630   "fdivr{s|}",
11631   /* d9 */
11632   "fld{s|}",
11633   "(bad)",
11634   "fst{s|}",
11635   "fstp{s|}",
11636   "fldenvIC",
11637   "fldcw",
11638   "fNstenvIC",
11639   "fNstcw",
11640   /* da */
11641   "fiadd{l|}",
11642   "fimul{l|}",
11643   "ficom{l|}",
11644   "ficomp{l|}",
11645   "fisub{l|}",
11646   "fisubr{l|}",
11647   "fidiv{l|}",
11648   "fidivr{l|}",
11649   /* db */
11650   "fild{l|}",
11651   "fisttp{l|}",
11652   "fist{l|}",
11653   "fistp{l|}",
11654   "(bad)",
11655   "fld{t||t|}",
11656   "(bad)",
11657   "fstp{t||t|}",
11658   /* dc */
11659   "fadd{l|}",
11660   "fmul{l|}",
11661   "fcom{l|}",
11662   "fcomp{l|}",
11663   "fsub{l|}",
11664   "fsubr{l|}",
11665   "fdiv{l|}",
11666   "fdivr{l|}",
11667   /* dd */
11668   "fld{l|}",
11669   "fisttp{ll|}",
11670   "fst{l||}",
11671   "fstp{l|}",
11672   "frstorIC",
11673   "(bad)",
11674   "fNsaveIC",
11675   "fNstsw",
11676   /* de */
11677   "fiadd",
11678   "fimul",
11679   "ficom",
11680   "ficomp",
11681   "fisub",
11682   "fisubr",
11683   "fidiv",
11684   "fidivr",
11685   /* df */
11686   "fild",
11687   "fisttp",
11688   "fist",
11689   "fistp",
11690   "fbld",
11691   "fild{ll|}",
11692   "fbstp",
11693   "fistp{ll|}",
11694 };
11695
11696 static const unsigned char float_mem_mode[] = {
11697   /* d8 */
11698   d_mode,
11699   d_mode,
11700   d_mode,
11701   d_mode,
11702   d_mode,
11703   d_mode,
11704   d_mode,
11705   d_mode,
11706   /* d9 */
11707   d_mode,
11708   0,
11709   d_mode,
11710   d_mode,
11711   0,
11712   w_mode,
11713   0,
11714   w_mode,
11715   /* da */
11716   d_mode,
11717   d_mode,
11718   d_mode,
11719   d_mode,
11720   d_mode,
11721   d_mode,
11722   d_mode,
11723   d_mode,
11724   /* db */
11725   d_mode,
11726   d_mode,
11727   d_mode,
11728   d_mode,
11729   0,
11730   t_mode,
11731   0,
11732   t_mode,
11733   /* dc */
11734   q_mode,
11735   q_mode,
11736   q_mode,
11737   q_mode,
11738   q_mode,
11739   q_mode,
11740   q_mode,
11741   q_mode,
11742   /* dd */
11743   q_mode,
11744   q_mode,
11745   q_mode,
11746   q_mode,
11747   0,
11748   0,
11749   0,
11750   w_mode,
11751   /* de */
11752   w_mode,
11753   w_mode,
11754   w_mode,
11755   w_mode,
11756   w_mode,
11757   w_mode,
11758   w_mode,
11759   w_mode,
11760   /* df */
11761   w_mode,
11762   w_mode,
11763   w_mode,
11764   w_mode,
11765   t_mode,
11766   q_mode,
11767   t_mode,
11768   q_mode
11769 };
11770
11771 #define ST { OP_ST, 0 }
11772 #define STi { OP_STi, 0 }
11773
11774 #define FGRPd9_2 NULL, { { NULL, 0 } }
11775 #define FGRPd9_4 NULL, { { NULL, 1 } }
11776 #define FGRPd9_5 NULL, { { NULL, 2 } }
11777 #define FGRPd9_6 NULL, { { NULL, 3 } }
11778 #define FGRPd9_7 NULL, { { NULL, 4 } }
11779 #define FGRPda_5 NULL, { { NULL, 5 } }
11780 #define FGRPdb_4 NULL, { { NULL, 6 } }
11781 #define FGRPde_3 NULL, { { NULL, 7 } }
11782 #define FGRPdf_4 NULL, { { NULL, 8 } }
11783
11784 static const struct dis386 float_reg[][8] = {
11785   /* d8 */
11786   {
11787     { "fadd",   { ST, STi } },
11788     { "fmul",   { ST, STi } },
11789     { "fcom",   { STi } },
11790     { "fcomp",  { STi } },
11791     { "fsub",   { ST, STi } },
11792     { "fsubr",  { ST, STi } },
11793     { "fdiv",   { ST, STi } },
11794     { "fdivr",  { ST, STi } },
11795   },
11796   /* d9 */
11797   {
11798     { "fld",    { STi } },
11799     { "fxch",   { STi } },
11800     { FGRPd9_2 },
11801     { Bad_Opcode },
11802     { FGRPd9_4 },
11803     { FGRPd9_5 },
11804     { FGRPd9_6 },
11805     { FGRPd9_7 },
11806   },
11807   /* da */
11808   {
11809     { "fcmovb", { ST, STi } },
11810     { "fcmove", { ST, STi } },
11811     { "fcmovbe",{ ST, STi } },
11812     { "fcmovu", { ST, STi } },
11813     { Bad_Opcode },
11814     { FGRPda_5 },
11815     { Bad_Opcode },
11816     { Bad_Opcode },
11817   },
11818   /* db */
11819   {
11820     { "fcmovnb",{ ST, STi } },
11821     { "fcmovne",{ ST, STi } },
11822     { "fcmovnbe",{ ST, STi } },
11823     { "fcmovnu",{ ST, STi } },
11824     { FGRPdb_4 },
11825     { "fucomi", { ST, STi } },
11826     { "fcomi",  { ST, STi } },
11827     { Bad_Opcode },
11828   },
11829   /* dc */
11830   {
11831     { "fadd",   { STi, ST } },
11832     { "fmul",   { STi, ST } },
11833     { Bad_Opcode },
11834     { Bad_Opcode },
11835     { "fsub!M", { STi, ST } },
11836     { "fsubM",  { STi, ST } },
11837     { "fdiv!M", { STi, ST } },
11838     { "fdivM",  { STi, ST } },
11839   },
11840   /* dd */
11841   {
11842     { "ffree",  { STi } },
11843     { Bad_Opcode },
11844     { "fst",    { STi } },
11845     { "fstp",   { STi } },
11846     { "fucom",  { STi } },
11847     { "fucomp", { STi } },
11848     { Bad_Opcode },
11849     { Bad_Opcode },
11850   },
11851   /* de */
11852   {
11853     { "faddp",  { STi, ST } },
11854     { "fmulp",  { STi, ST } },
11855     { Bad_Opcode },
11856     { FGRPde_3 },
11857     { "fsub!Mp", { STi, ST } },
11858     { "fsubMp", { STi, ST } },
11859     { "fdiv!Mp", { STi, ST } },
11860     { "fdivMp", { STi, ST } },
11861   },
11862   /* df */
11863   {
11864     { "ffreep", { STi } },
11865     { Bad_Opcode },
11866     { Bad_Opcode },
11867     { Bad_Opcode },
11868     { FGRPdf_4 },
11869     { "fucomip", { ST, STi } },
11870     { "fcomip", { ST, STi } },
11871     { Bad_Opcode },
11872   },
11873 };
11874
11875 static char *fgrps[][8] = {
11876   /* d9_2  0 */
11877   {
11878     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11879   },
11880
11881   /* d9_4  1 */
11882   {
11883     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11884   },
11885
11886   /* d9_5  2 */
11887   {
11888     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11889   },
11890
11891   /* d9_6  3 */
11892   {
11893     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11894   },
11895
11896   /* d9_7  4 */
11897   {
11898     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11899   },
11900
11901   /* da_5  5 */
11902   {
11903     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11904   },
11905
11906   /* db_4  6 */
11907   {
11908     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11909     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11910   },
11911
11912   /* de_3  7 */
11913   {
11914     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11915   },
11916
11917   /* df_4  8 */
11918   {
11919     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11920   },
11921 };
11922
11923 static void
11924 swap_operand (void)
11925 {
11926   mnemonicendp[0] = '.';
11927   mnemonicendp[1] = 's';
11928   mnemonicendp += 2;
11929 }
11930
11931 static void
11932 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11933                int sizeflag ATTRIBUTE_UNUSED)
11934 {
11935   /* Skip mod/rm byte.  */
11936   MODRM_CHECK;
11937   codep++;
11938 }
11939
11940 static void
11941 dofloat (int sizeflag)
11942 {
11943   const struct dis386 *dp;
11944   unsigned char floatop;
11945
11946   floatop = codep[-1];
11947
11948   if (modrm.mod != 3)
11949     {
11950       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
11951
11952       putop (float_mem[fp_indx], sizeflag);
11953       obufp = op_out[0];
11954       op_ad = 2;
11955       OP_E (float_mem_mode[fp_indx], sizeflag);
11956       return;
11957     }
11958   /* Skip mod/rm byte.  */
11959   MODRM_CHECK;
11960   codep++;
11961
11962   dp = &float_reg[floatop - 0xd8][modrm.reg];
11963   if (dp->name == NULL)
11964     {
11965       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
11966
11967       /* Instruction fnstsw is only one with strange arg.  */
11968       if (floatop == 0xdf && codep[-1] == 0xe0)
11969         strcpy (op_out[0], names16[0]);
11970     }
11971   else
11972     {
11973       putop (dp->name, sizeflag);
11974
11975       obufp = op_out[0];
11976       op_ad = 2;
11977       if (dp->op[0].rtn)
11978         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
11979
11980       obufp = op_out[1];
11981       op_ad = 1;
11982       if (dp->op[1].rtn)
11983         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
11984     }
11985 }
11986
11987 static void
11988 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11989 {
11990   oappend ("%st" + intel_syntax);
11991 }
11992
11993 static void
11994 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11995 {
11996   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
11997   oappend (scratchbuf + intel_syntax);
11998 }
11999
12000 /* Capital letters in template are macros.  */
12001 static int
12002 putop (const char *in_template, int sizeflag)
12003 {
12004   const char *p;
12005   int alt = 0;
12006   int cond = 1;
12007   unsigned int l = 0, len = 1;
12008   char last[4];
12009
12010 #define SAVE_LAST(c)                    \
12011   if (l < len && l < sizeof (last))     \
12012     last[l++] = c;                      \
12013   else                                  \
12014     abort ();
12015
12016   for (p = in_template; *p; p++)
12017     {
12018       switch (*p)
12019         {
12020         default:
12021           *obufp++ = *p;
12022           break;
12023         case '%':
12024           len++;
12025           break;
12026         case '!':
12027           cond = 0;
12028           break;
12029         case '{':
12030           alt = 0;
12031           if (intel_syntax)
12032             {
12033               while (*++p != '|')
12034                 if (*p == '}' || *p == '\0')
12035                   abort ();
12036             }
12037           /* Fall through.  */
12038         case 'I':
12039           alt = 1;
12040           continue;
12041         case '|':
12042           while (*++p != '}')
12043             {
12044               if (*p == '\0')
12045                 abort ();
12046             }
12047           break;
12048         case '}':
12049           break;
12050         case 'A':
12051           if (intel_syntax)
12052             break;
12053           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12054             *obufp++ = 'b';
12055           break;
12056         case 'B':
12057           if (l == 0 && len == 1)
12058             {
12059 case_B:
12060               if (intel_syntax)
12061                 break;
12062               if (sizeflag & SUFFIX_ALWAYS)
12063                 *obufp++ = 'b';
12064             }
12065           else
12066             {
12067               if (l != 1
12068                   || len != 2
12069                   || last[0] != 'L')
12070                 {
12071                   SAVE_LAST (*p);
12072                   break;
12073                 }
12074
12075               if (address_mode == mode_64bit
12076                   && !(prefixes & PREFIX_ADDR))
12077                 {
12078                   *obufp++ = 'a';
12079                   *obufp++ = 'b';
12080                   *obufp++ = 's';
12081                 }
12082
12083               goto case_B;
12084             }
12085           break;
12086         case 'C':
12087           if (intel_syntax && !alt)
12088             break;
12089           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12090             {
12091               if (sizeflag & DFLAG)
12092                 *obufp++ = intel_syntax ? 'd' : 'l';
12093               else
12094                 *obufp++ = intel_syntax ? 'w' : 's';
12095               used_prefixes |= (prefixes & PREFIX_DATA);
12096             }
12097           break;
12098         case 'D':
12099           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12100             break;
12101           USED_REX (REX_W);
12102           if (modrm.mod == 3)
12103             {
12104               if (rex & REX_W)
12105                 *obufp++ = 'q';
12106               else
12107                 {
12108                   if (sizeflag & DFLAG)
12109                     *obufp++ = intel_syntax ? 'd' : 'l';
12110                   else
12111                     *obufp++ = 'w';
12112                   used_prefixes |= (prefixes & PREFIX_DATA);
12113                 }
12114             }
12115           else
12116             *obufp++ = 'w';
12117           break;
12118         case 'E':               /* For jcxz/jecxz */
12119           if (address_mode == mode_64bit)
12120             {
12121               if (sizeflag & AFLAG)
12122                 *obufp++ = 'r';
12123               else
12124                 *obufp++ = 'e';
12125             }
12126           else
12127             if (sizeflag & AFLAG)
12128               *obufp++ = 'e';
12129           used_prefixes |= (prefixes & PREFIX_ADDR);
12130           break;
12131         case 'F':
12132           if (intel_syntax)
12133             break;
12134           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12135             {
12136               if (sizeflag & AFLAG)
12137                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12138               else
12139                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12140               used_prefixes |= (prefixes & PREFIX_ADDR);
12141             }
12142           break;
12143         case 'G':
12144           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12145             break;
12146           if ((rex & REX_W) || (sizeflag & DFLAG))
12147             *obufp++ = 'l';
12148           else
12149             *obufp++ = 'w';
12150           if (!(rex & REX_W))
12151             used_prefixes |= (prefixes & PREFIX_DATA);
12152           break;
12153         case 'H':
12154           if (intel_syntax)
12155             break;
12156           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12157               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12158             {
12159               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12160               *obufp++ = ',';
12161               *obufp++ = 'p';
12162               if (prefixes & PREFIX_DS)
12163                 *obufp++ = 't';
12164               else
12165                 *obufp++ = 'n';
12166             }
12167           break;
12168         case 'J':
12169           if (intel_syntax)
12170             break;
12171           *obufp++ = 'l';
12172           break;
12173         case 'K':
12174           USED_REX (REX_W);
12175           if (rex & REX_W)
12176             *obufp++ = 'q';
12177           else
12178             *obufp++ = 'd';
12179           break;
12180         case 'Z':
12181           if (intel_syntax)
12182             break;
12183           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12184             {
12185               *obufp++ = 'q';
12186               break;
12187             }
12188           /* Fall through.  */
12189           goto case_L;
12190         case 'L':
12191           if (l != 0 || len != 1)
12192             {
12193               SAVE_LAST (*p);
12194               break;
12195             }
12196 case_L:
12197           if (intel_syntax)
12198             break;
12199           if (sizeflag & SUFFIX_ALWAYS)
12200             *obufp++ = 'l';
12201           break;
12202         case 'M':
12203           if (intel_mnemonic != cond)
12204             *obufp++ = 'r';
12205           break;
12206         case 'N':
12207           if ((prefixes & PREFIX_FWAIT) == 0)
12208             *obufp++ = 'n';
12209           else
12210             used_prefixes |= PREFIX_FWAIT;
12211           break;
12212         case 'O':
12213           USED_REX (REX_W);
12214           if (rex & REX_W)
12215             *obufp++ = 'o';
12216           else if (intel_syntax && (sizeflag & DFLAG))
12217             *obufp++ = 'q';
12218           else
12219             *obufp++ = 'd';
12220           if (!(rex & REX_W))
12221             used_prefixes |= (prefixes & PREFIX_DATA);
12222           break;
12223         case 'T':
12224           if (intel_syntax)
12225             break;
12226           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12227             {
12228               *obufp++ = 'q';
12229               break;
12230             }
12231           /* Fall through.  */
12232         case 'P':
12233           if (intel_syntax)
12234             break;
12235           if ((prefixes & PREFIX_DATA)
12236               || (rex & REX_W)
12237               || (sizeflag & SUFFIX_ALWAYS))
12238             {
12239               USED_REX (REX_W);
12240               if (rex & REX_W)
12241                 *obufp++ = 'q';
12242               else
12243                 {
12244                    if (sizeflag & DFLAG)
12245                       *obufp++ = 'l';
12246                    else
12247                      *obufp++ = 'w';
12248                    used_prefixes |= (prefixes & PREFIX_DATA);
12249                 }
12250             }
12251           break;
12252         case 'U':
12253           if (intel_syntax)
12254             break;
12255           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12256             {
12257               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12258                 *obufp++ = 'q';
12259               break;
12260             }
12261           /* Fall through.  */
12262           goto case_Q;
12263         case 'Q':
12264           if (l == 0 && len == 1)
12265             {
12266 case_Q:
12267               if (intel_syntax && !alt)
12268                 break;
12269               USED_REX (REX_W);
12270               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12271                 {
12272                   if (rex & REX_W)
12273                     *obufp++ = 'q';
12274                   else
12275                     {
12276                       if (sizeflag & DFLAG)
12277                         *obufp++ = intel_syntax ? 'd' : 'l';
12278                       else
12279                         *obufp++ = 'w';
12280                       used_prefixes |= (prefixes & PREFIX_DATA);
12281                     }
12282                 }
12283             }
12284           else
12285             {
12286               if (l != 1 || len != 2 || last[0] != 'L')
12287                 {
12288                   SAVE_LAST (*p);
12289                   break;
12290                 }
12291               if (intel_syntax
12292                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12293                 break;
12294               if ((rex & REX_W))
12295                 {
12296                   USED_REX (REX_W);
12297                   *obufp++ = 'q';
12298                 }
12299               else
12300                 *obufp++ = 'l';
12301             }
12302           break;
12303         case 'R':
12304           USED_REX (REX_W);
12305           if (rex & REX_W)
12306             *obufp++ = 'q';
12307           else if (sizeflag & DFLAG)
12308             {
12309               if (intel_syntax)
12310                   *obufp++ = 'd';
12311               else
12312                   *obufp++ = 'l';
12313             }
12314           else
12315             *obufp++ = 'w';
12316           if (intel_syntax && !p[1]
12317               && ((rex & REX_W) || (sizeflag & DFLAG)))
12318             *obufp++ = 'e';
12319           if (!(rex & REX_W))
12320             used_prefixes |= (prefixes & PREFIX_DATA);
12321           break;
12322         case 'V':
12323           if (l == 0 && len == 1)
12324             {
12325               if (intel_syntax)
12326                 break;
12327               if (address_mode == mode_64bit && (sizeflag & DFLAG))
12328                 {
12329                   if (sizeflag & SUFFIX_ALWAYS)
12330                     *obufp++ = 'q';
12331                   break;
12332                 }
12333             }
12334           else
12335             {
12336               if (l != 1
12337                   || len != 2
12338                   || last[0] != 'L')
12339                 {
12340                   SAVE_LAST (*p);
12341                   break;
12342                 }
12343
12344               if (rex & REX_W)
12345                 {
12346                   *obufp++ = 'a';
12347                   *obufp++ = 'b';
12348                   *obufp++ = 's';
12349                 }
12350             }
12351           /* Fall through.  */
12352           goto case_S;
12353         case 'S':
12354           if (l == 0 && len == 1)
12355             {
12356 case_S:
12357               if (intel_syntax)
12358                 break;
12359               if (sizeflag & SUFFIX_ALWAYS)
12360                 {
12361                   if (rex & REX_W)
12362                     *obufp++ = 'q';
12363                   else
12364                     {
12365                       if (sizeflag & DFLAG)
12366                         *obufp++ = 'l';
12367                       else
12368                         *obufp++ = 'w';
12369                       used_prefixes |= (prefixes & PREFIX_DATA);
12370                     }
12371                 }
12372             }
12373           else
12374             {
12375               if (l != 1
12376                   || len != 2
12377                   || last[0] != 'L')
12378                 {
12379                   SAVE_LAST (*p);
12380                   break;
12381                 }
12382
12383               if (address_mode == mode_64bit
12384                   && !(prefixes & PREFIX_ADDR))
12385                 {
12386                   *obufp++ = 'a';
12387                   *obufp++ = 'b';
12388                   *obufp++ = 's';
12389                 }
12390
12391               goto case_S;
12392             }
12393           break;
12394         case 'X':
12395           if (l != 0 || len != 1)
12396             {
12397               SAVE_LAST (*p);
12398               break;
12399             }
12400           if (need_vex && vex.prefix)
12401             {
12402               if (vex.prefix == DATA_PREFIX_OPCODE)
12403                 *obufp++ = 'd';
12404               else
12405                 *obufp++ = 's';
12406             }
12407           else
12408             {
12409               if (prefixes & PREFIX_DATA)
12410                 *obufp++ = 'd';
12411               else
12412                 *obufp++ = 's';
12413               used_prefixes |= (prefixes & PREFIX_DATA);
12414             }
12415           break;
12416         case 'Y':
12417           if (l == 0 && len == 1)
12418             {
12419               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12420                 break;
12421               if (rex & REX_W)
12422                 {
12423                   USED_REX (REX_W);
12424                   *obufp++ = 'q';
12425                 }
12426               break;
12427             }
12428           else
12429             {
12430               if (l != 1 || len != 2 || last[0] != 'X')
12431                 {
12432                   SAVE_LAST (*p);
12433                   break;
12434                 }
12435               if (!need_vex)
12436                 abort ();
12437               if (intel_syntax
12438                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12439                 break;
12440               switch (vex.length)
12441                 {
12442                 case 128:
12443                   *obufp++ = 'x';
12444                   break;
12445                 case 256:
12446                   *obufp++ = 'y';
12447                   break;
12448                 default:
12449                   abort ();
12450                 }
12451             }
12452           break;
12453         case 'W':
12454           if (l == 0 && len == 1)
12455             {
12456               /* operand size flag for cwtl, cbtw */
12457               USED_REX (REX_W);
12458               if (rex & REX_W)
12459                 {
12460                   if (intel_syntax)
12461                     *obufp++ = 'd';
12462                   else
12463                     *obufp++ = 'l';
12464                 }
12465               else if (sizeflag & DFLAG)
12466                 *obufp++ = 'w';
12467               else
12468                 *obufp++ = 'b';
12469               if (!(rex & REX_W))
12470                 used_prefixes |= (prefixes & PREFIX_DATA);
12471             }
12472           else
12473             {
12474               if (l != 1 || len != 2 || last[0] != 'X')
12475                 {
12476                   SAVE_LAST (*p);
12477                   break;
12478                 }
12479               if (!need_vex)
12480                 abort ();
12481               *obufp++ = vex.w ? 'd': 's';
12482             }
12483           break;
12484         }
12485       alt = 0;
12486     }
12487   *obufp = 0;
12488   mnemonicendp = obufp;
12489   return 0;
12490 }
12491
12492 static void
12493 oappend (const char *s)
12494 {
12495   obufp = stpcpy (obufp, s);
12496 }
12497
12498 static void
12499 append_seg (void)
12500 {
12501   if (prefixes & PREFIX_CS)
12502     {
12503       used_prefixes |= PREFIX_CS;
12504       oappend ("%cs:" + intel_syntax);
12505     }
12506   if (prefixes & PREFIX_DS)
12507     {
12508       used_prefixes |= PREFIX_DS;
12509       oappend ("%ds:" + intel_syntax);
12510     }
12511   if (prefixes & PREFIX_SS)
12512     {
12513       used_prefixes |= PREFIX_SS;
12514       oappend ("%ss:" + intel_syntax);
12515     }
12516   if (prefixes & PREFIX_ES)
12517     {
12518       used_prefixes |= PREFIX_ES;
12519       oappend ("%es:" + intel_syntax);
12520     }
12521   if (prefixes & PREFIX_FS)
12522     {
12523       used_prefixes |= PREFIX_FS;
12524       oappend ("%fs:" + intel_syntax);
12525     }
12526   if (prefixes & PREFIX_GS)
12527     {
12528       used_prefixes |= PREFIX_GS;
12529       oappend ("%gs:" + intel_syntax);
12530     }
12531 }
12532
12533 static void
12534 OP_indirE (int bytemode, int sizeflag)
12535 {
12536   if (!intel_syntax)
12537     oappend ("*");
12538   OP_E (bytemode, sizeflag);
12539 }
12540
12541 static void
12542 print_operand_value (char *buf, int hex, bfd_vma disp)
12543 {
12544   if (address_mode == mode_64bit)
12545     {
12546       if (hex)
12547         {
12548           char tmp[30];
12549           int i;
12550           buf[0] = '0';
12551           buf[1] = 'x';
12552           sprintf_vma (tmp, disp);
12553           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12554           strcpy (buf + 2, tmp + i);
12555         }
12556       else
12557         {
12558           bfd_signed_vma v = disp;
12559           char tmp[30];
12560           int i;
12561           if (v < 0)
12562             {
12563               *(buf++) = '-';
12564               v = -disp;
12565               /* Check for possible overflow on 0x8000000000000000.  */
12566               if (v < 0)
12567                 {
12568                   strcpy (buf, "9223372036854775808");
12569                   return;
12570                 }
12571             }
12572           if (!v)
12573             {
12574               strcpy (buf, "0");
12575               return;
12576             }
12577
12578           i = 0;
12579           tmp[29] = 0;
12580           while (v)
12581             {
12582               tmp[28 - i] = (v % 10) + '0';
12583               v /= 10;
12584               i++;
12585             }
12586           strcpy (buf, tmp + 29 - i);
12587         }
12588     }
12589   else
12590     {
12591       if (hex)
12592         sprintf (buf, "0x%x", (unsigned int) disp);
12593       else
12594         sprintf (buf, "%d", (int) disp);
12595     }
12596 }
12597
12598 /* Put DISP in BUF as signed hex number.  */
12599
12600 static void
12601 print_displacement (char *buf, bfd_vma disp)
12602 {
12603   bfd_signed_vma val = disp;
12604   char tmp[30];
12605   int i, j = 0;
12606
12607   if (val < 0)
12608     {
12609       buf[j++] = '-';
12610       val = -disp;
12611
12612       /* Check for possible overflow.  */
12613       if (val < 0)
12614         {
12615           switch (address_mode)
12616             {
12617             case mode_64bit:
12618               strcpy (buf + j, "0x8000000000000000");
12619               break;
12620             case mode_32bit:
12621               strcpy (buf + j, "0x80000000");
12622               break;
12623             case mode_16bit:
12624               strcpy (buf + j, "0x8000");
12625               break;
12626             }
12627           return;
12628         }
12629     }
12630
12631   buf[j++] = '0';
12632   buf[j++] = 'x';
12633
12634   sprintf_vma (tmp, (bfd_vma) val);
12635   for (i = 0; tmp[i] == '0'; i++)
12636     continue;
12637   if (tmp[i] == '\0')
12638     i--;
12639   strcpy (buf + j, tmp + i);
12640 }
12641
12642 static void
12643 intel_operand_size (int bytemode, int sizeflag)
12644 {
12645   switch (bytemode)
12646     {
12647     case b_mode:
12648     case b_swap_mode:
12649     case dqb_mode:
12650       oappend ("BYTE PTR ");
12651       break;
12652     case w_mode:
12653     case dqw_mode:
12654       oappend ("WORD PTR ");
12655       break;
12656     case stack_v_mode:
12657       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12658         {
12659           oappend ("QWORD PTR ");
12660           break;
12661         }
12662       /* FALLTHRU */
12663     case v_mode:
12664     case v_swap_mode:
12665     case dq_mode:
12666       USED_REX (REX_W);
12667       if (rex & REX_W)
12668         oappend ("QWORD PTR ");
12669       else
12670         {
12671           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12672             oappend ("DWORD PTR ");
12673           else
12674             oappend ("WORD PTR ");
12675           used_prefixes |= (prefixes & PREFIX_DATA);
12676         }
12677       break;
12678     case z_mode:
12679       if ((rex & REX_W) || (sizeflag & DFLAG))
12680         *obufp++ = 'D';
12681       oappend ("WORD PTR ");
12682       if (!(rex & REX_W))
12683         used_prefixes |= (prefixes & PREFIX_DATA);
12684       break;
12685     case a_mode:
12686       if (sizeflag & DFLAG)
12687         oappend ("QWORD PTR ");
12688       else
12689         oappend ("DWORD PTR ");
12690       used_prefixes |= (prefixes & PREFIX_DATA);
12691       break;
12692     case d_mode:
12693     case d_scalar_mode:
12694     case d_scalar_swap_mode:
12695     case d_swap_mode:
12696     case dqd_mode:
12697       oappend ("DWORD PTR ");
12698       break;
12699     case q_mode:
12700     case q_scalar_mode:
12701     case q_scalar_swap_mode:
12702     case q_swap_mode:
12703       oappend ("QWORD PTR ");
12704       break;
12705     case m_mode:
12706       if (address_mode == mode_64bit)
12707         oappend ("QWORD PTR ");
12708       else
12709         oappend ("DWORD PTR ");
12710       break;
12711     case f_mode:
12712       if (sizeflag & DFLAG)
12713         oappend ("FWORD PTR ");
12714       else
12715         oappend ("DWORD PTR ");
12716       used_prefixes |= (prefixes & PREFIX_DATA);
12717       break;
12718     case t_mode:
12719       oappend ("TBYTE PTR ");
12720       break;
12721     case x_mode:
12722     case x_swap_mode:
12723       if (need_vex)
12724         {
12725           switch (vex.length)
12726             {
12727             case 128:
12728               oappend ("XMMWORD PTR ");
12729               break;
12730             case 256:
12731               oappend ("YMMWORD PTR ");
12732               break;
12733             default:
12734               abort ();
12735             }
12736         }
12737       else
12738         oappend ("XMMWORD PTR ");
12739       break;
12740     case xmm_mode:
12741       oappend ("XMMWORD PTR ");
12742       break;
12743     case xmmq_mode:
12744       if (!need_vex)
12745         abort ();
12746
12747       switch (vex.length)
12748         {
12749         case 128:
12750           oappend ("QWORD PTR ");
12751           break;
12752         case 256:
12753           oappend ("XMMWORD PTR ");
12754           break;
12755         default:
12756           abort ();
12757         }
12758       break;
12759     case ymmq_mode:
12760       if (!need_vex)
12761         abort ();
12762
12763       switch (vex.length)
12764         {
12765         case 128:
12766           oappend ("QWORD PTR ");
12767           break;
12768         case 256:
12769           oappend ("YMMWORD PTR ");
12770           break;
12771         default:
12772           abort ();
12773         }
12774       break;
12775     case o_mode:
12776       oappend ("OWORD PTR ");
12777       break;
12778     case vex_w_dq_mode:
12779       if (!need_vex)
12780         abort ();
12781
12782       if (vex.w)
12783         oappend ("QWORD PTR ");
12784       else
12785         oappend ("DWORD PTR ");
12786       break;
12787     default:
12788       break;
12789     }
12790 }
12791
12792 static void
12793 OP_E_register (int bytemode, int sizeflag)
12794 {
12795   int reg = modrm.rm;
12796   const char **names;
12797
12798   USED_REX (REX_B);
12799   if ((rex & REX_B))
12800     reg += 8;
12801
12802   if ((sizeflag & SUFFIX_ALWAYS)
12803       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12804     swap_operand ();
12805
12806   switch (bytemode)
12807     {
12808     case b_mode:
12809     case b_swap_mode:
12810       USED_REX (0);
12811       if (rex)
12812         names = names8rex;
12813       else
12814         names = names8;
12815       break;
12816     case w_mode:
12817       names = names16;
12818       break;
12819     case d_mode:
12820       names = names32;
12821       break;
12822     case q_mode:
12823       names = names64;
12824       break;
12825     case m_mode:
12826       names = address_mode == mode_64bit ? names64 : names32;
12827       break;
12828     case stack_v_mode:
12829       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12830         {
12831           names = names64;
12832           break;
12833         }
12834       bytemode = v_mode;
12835       /* FALLTHRU */
12836     case v_mode:
12837     case v_swap_mode:
12838     case dq_mode:
12839     case dqb_mode:
12840     case dqd_mode:
12841     case dqw_mode:
12842       USED_REX (REX_W);
12843       if (rex & REX_W)
12844         names = names64;
12845       else
12846         {
12847           if ((sizeflag & DFLAG)
12848               || (bytemode != v_mode
12849                   && bytemode != v_swap_mode))
12850             names = names32;
12851           else
12852             names = names16;
12853           used_prefixes |= (prefixes & PREFIX_DATA);
12854         }
12855       break;
12856     case 0:
12857       return;
12858     default:
12859       oappend (INTERNAL_DISASSEMBLER_ERROR);
12860       return;
12861     }
12862   oappend (names[reg]);
12863 }
12864
12865 static void
12866 OP_E_memory (int bytemode, int sizeflag)
12867 {
12868   bfd_vma disp = 0;
12869   int add = (rex & REX_B) ? 8 : 0;
12870   int riprel = 0;
12871
12872   USED_REX (REX_B);
12873   if (intel_syntax)
12874     intel_operand_size (bytemode, sizeflag);
12875   append_seg ();
12876
12877   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12878     {
12879       /* 32/64 bit address mode */
12880       int havedisp;
12881       int havesib;
12882       int havebase;
12883       int haveindex;
12884       int needindex;
12885       int base, rbase;
12886       int vindex = 0;
12887       int scale = 0;
12888
12889       havesib = 0;
12890       havebase = 1;
12891       haveindex = 0;
12892       base = modrm.rm;
12893
12894       if (base == 4)
12895         {
12896           havesib = 1;
12897           FETCH_DATA (the_info, codep + 1);
12898           vindex = (*codep >> 3) & 7;
12899           scale = (*codep >> 6) & 3;
12900           base = *codep & 7;
12901           USED_REX (REX_X);
12902           if (rex & REX_X)
12903             vindex += 8;
12904           haveindex = vindex != 4;
12905           codep++;
12906         }
12907       rbase = base + add;
12908
12909       switch (modrm.mod)
12910         {
12911         case 0:
12912           if (base == 5)
12913             {
12914               havebase = 0;
12915               if (address_mode == mode_64bit && !havesib)
12916                 riprel = 1;
12917               disp = get32s ();
12918             }
12919           break;
12920         case 1:
12921           FETCH_DATA (the_info, codep + 1);
12922           disp = *codep++;
12923           if ((disp & 0x80) != 0)
12924             disp -= 0x100;
12925           break;
12926         case 2:
12927           disp = get32s ();
12928           break;
12929         }
12930
12931       /* In 32bit mode, we need index register to tell [offset] from
12932          [eiz*1 + offset].  */
12933       needindex = (havesib
12934                    && !havebase
12935                    && !haveindex
12936                    && address_mode == mode_32bit);
12937       havedisp = (havebase
12938                   || needindex
12939                   || (havesib && (haveindex || scale != 0)));
12940
12941       if (!intel_syntax)
12942         if (modrm.mod != 0 || base == 5)
12943           {
12944             if (havedisp || riprel)
12945               print_displacement (scratchbuf, disp);
12946             else
12947               print_operand_value (scratchbuf, 1, disp);
12948             oappend (scratchbuf);
12949             if (riprel)
12950               {
12951                 set_op (disp, 1);
12952                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
12953               }
12954           }
12955
12956       if (havebase || haveindex || riprel)
12957         used_prefixes |= PREFIX_ADDR;
12958
12959       if (havedisp || (intel_syntax && riprel))
12960         {
12961           *obufp++ = open_char;
12962           if (intel_syntax && riprel)
12963             {
12964               set_op (disp, 1);
12965               oappend (sizeflag & AFLAG ? "rip" : "eip");
12966             }
12967           *obufp = '\0';
12968           if (havebase)
12969             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
12970                      ? names64[rbase] : names32[rbase]);
12971           if (havesib)
12972             {
12973               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12974                  print index to tell base + index from base.  */
12975               if (scale != 0
12976                   || needindex
12977                   || haveindex
12978                   || (havebase && base != ESP_REG_NUM))
12979                 {
12980                   if (!intel_syntax || havebase)
12981                     {
12982                       *obufp++ = separator_char;
12983                       *obufp = '\0';
12984                     }
12985                   if (haveindex)
12986                     oappend (address_mode == mode_64bit
12987                              && (sizeflag & AFLAG)
12988                              ? names64[vindex] : names32[vindex]);
12989                   else
12990                     oappend (address_mode == mode_64bit
12991                              && (sizeflag & AFLAG)
12992                              ? index64 : index32);
12993
12994                   *obufp++ = scale_char;
12995                   *obufp = '\0';
12996                   sprintf (scratchbuf, "%d", 1 << scale);
12997                   oappend (scratchbuf);
12998                 }
12999             }
13000           if (intel_syntax
13001               && (disp || modrm.mod != 0 || base == 5))
13002             {
13003               if (!havedisp || (bfd_signed_vma) disp >= 0)
13004                 {
13005                   *obufp++ = '+';
13006                   *obufp = '\0';
13007                 }
13008               else if (modrm.mod != 1 && disp != -disp)
13009                 {
13010                   *obufp++ = '-';
13011                   *obufp = '\0';
13012                   disp = - (bfd_signed_vma) disp;
13013                 }
13014
13015               if (havedisp)
13016                 print_displacement (scratchbuf, disp);
13017               else
13018                 print_operand_value (scratchbuf, 1, disp);
13019               oappend (scratchbuf);
13020             }
13021
13022           *obufp++ = close_char;
13023           *obufp = '\0';
13024         }
13025       else if (intel_syntax)
13026         {
13027           if (modrm.mod != 0 || base == 5)
13028             {
13029               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13030                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13031                 ;
13032               else
13033                 {
13034                   oappend (names_seg[ds_reg - es_reg]);
13035                   oappend (":");
13036                 }
13037               print_operand_value (scratchbuf, 1, disp);
13038               oappend (scratchbuf);
13039             }
13040         }
13041     }
13042   else
13043     {
13044       /* 16 bit address mode */
13045       used_prefixes |= prefixes & PREFIX_ADDR;
13046       switch (modrm.mod)
13047         {
13048         case 0:
13049           if (modrm.rm == 6)
13050             {
13051               disp = get16 ();
13052               if ((disp & 0x8000) != 0)
13053                 disp -= 0x10000;
13054             }
13055           break;
13056         case 1:
13057           FETCH_DATA (the_info, codep + 1);
13058           disp = *codep++;
13059           if ((disp & 0x80) != 0)
13060             disp -= 0x100;
13061           break;
13062         case 2:
13063           disp = get16 ();
13064           if ((disp & 0x8000) != 0)
13065             disp -= 0x10000;
13066           break;
13067         }
13068
13069       if (!intel_syntax)
13070         if (modrm.mod != 0 || modrm.rm == 6)
13071           {
13072             print_displacement (scratchbuf, disp);
13073             oappend (scratchbuf);
13074           }
13075
13076       if (modrm.mod != 0 || modrm.rm != 6)
13077         {
13078           *obufp++ = open_char;
13079           *obufp = '\0';
13080           oappend (index16[modrm.rm]);
13081           if (intel_syntax
13082               && (disp || modrm.mod != 0 || modrm.rm == 6))
13083             {
13084               if ((bfd_signed_vma) disp >= 0)
13085                 {
13086                   *obufp++ = '+';
13087                   *obufp = '\0';
13088                 }
13089               else if (modrm.mod != 1)
13090                 {
13091                   *obufp++ = '-';
13092                   *obufp = '\0';
13093                   disp = - (bfd_signed_vma) disp;
13094                 }
13095
13096               print_displacement (scratchbuf, disp);
13097               oappend (scratchbuf);
13098             }
13099
13100           *obufp++ = close_char;
13101           *obufp = '\0';
13102         }
13103       else if (intel_syntax)
13104         {
13105           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13106                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13107             ;
13108           else
13109             {
13110               oappend (names_seg[ds_reg - es_reg]);
13111               oappend (":");
13112             }
13113           print_operand_value (scratchbuf, 1, disp & 0xffff);
13114           oappend (scratchbuf);
13115         }
13116     }
13117 }
13118
13119 static void
13120 OP_E (int bytemode, int sizeflag)
13121 {
13122   /* Skip mod/rm byte.  */
13123   MODRM_CHECK;
13124   codep++;
13125
13126   if (modrm.mod == 3)
13127     OP_E_register (bytemode, sizeflag);
13128   else
13129     OP_E_memory (bytemode, sizeflag);
13130 }
13131
13132 static void
13133 OP_G (int bytemode, int sizeflag)
13134 {
13135   int add = 0;
13136   USED_REX (REX_R);
13137   if (rex & REX_R)
13138     add += 8;
13139   switch (bytemode)
13140     {
13141     case b_mode:
13142       USED_REX (0);
13143       if (rex)
13144         oappend (names8rex[modrm.reg + add]);
13145       else
13146         oappend (names8[modrm.reg + add]);
13147       break;
13148     case w_mode:
13149       oappend (names16[modrm.reg + add]);
13150       break;
13151     case d_mode:
13152       oappend (names32[modrm.reg + add]);
13153       break;
13154     case q_mode:
13155       oappend (names64[modrm.reg + add]);
13156       break;
13157     case v_mode:
13158     case dq_mode:
13159     case dqb_mode:
13160     case dqd_mode:
13161     case dqw_mode:
13162       USED_REX (REX_W);
13163       if (rex & REX_W)
13164         oappend (names64[modrm.reg + add]);
13165       else
13166         {
13167           if ((sizeflag & DFLAG) || bytemode != v_mode)
13168             oappend (names32[modrm.reg + add]);
13169           else
13170             oappend (names16[modrm.reg + add]);
13171           used_prefixes |= (prefixes & PREFIX_DATA);
13172         }
13173       break;
13174     case m_mode:
13175       if (address_mode == mode_64bit)
13176         oappend (names64[modrm.reg + add]);
13177       else
13178         oappend (names32[modrm.reg + add]);
13179       break;
13180     default:
13181       oappend (INTERNAL_DISASSEMBLER_ERROR);
13182       break;
13183     }
13184 }
13185
13186 static bfd_vma
13187 get64 (void)
13188 {
13189   bfd_vma x;
13190 #ifdef BFD64
13191   unsigned int a;
13192   unsigned int b;
13193
13194   FETCH_DATA (the_info, codep + 8);
13195   a = *codep++ & 0xff;
13196   a |= (*codep++ & 0xff) << 8;
13197   a |= (*codep++ & 0xff) << 16;
13198   a |= (*codep++ & 0xff) << 24;
13199   b = *codep++ & 0xff;
13200   b |= (*codep++ & 0xff) << 8;
13201   b |= (*codep++ & 0xff) << 16;
13202   b |= (*codep++ & 0xff) << 24;
13203   x = a + ((bfd_vma) b << 32);
13204 #else
13205   abort ();
13206   x = 0;
13207 #endif
13208   return x;
13209 }
13210
13211 static bfd_signed_vma
13212 get32 (void)
13213 {
13214   bfd_signed_vma x = 0;
13215
13216   FETCH_DATA (the_info, codep + 4);
13217   x = *codep++ & (bfd_signed_vma) 0xff;
13218   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13219   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13220   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13221   return x;
13222 }
13223
13224 static bfd_signed_vma
13225 get32s (void)
13226 {
13227   bfd_signed_vma x = 0;
13228
13229   FETCH_DATA (the_info, codep + 4);
13230   x = *codep++ & (bfd_signed_vma) 0xff;
13231   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13232   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13233   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13234
13235   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13236
13237   return x;
13238 }
13239
13240 static int
13241 get16 (void)
13242 {
13243   int x = 0;
13244
13245   FETCH_DATA (the_info, codep + 2);
13246   x = *codep++ & 0xff;
13247   x |= (*codep++ & 0xff) << 8;
13248   return x;
13249 }
13250
13251 static void
13252 set_op (bfd_vma op, int riprel)
13253 {
13254   op_index[op_ad] = op_ad;
13255   if (address_mode == mode_64bit)
13256     {
13257       op_address[op_ad] = op;
13258       op_riprel[op_ad] = riprel;
13259     }
13260   else
13261     {
13262       /* Mask to get a 32-bit address.  */
13263       op_address[op_ad] = op & 0xffffffff;
13264       op_riprel[op_ad] = riprel & 0xffffffff;
13265     }
13266 }
13267
13268 static void
13269 OP_REG (int code, int sizeflag)
13270 {
13271   const char *s;
13272   int add;
13273   USED_REX (REX_B);
13274   if (rex & REX_B)
13275     add = 8;
13276   else
13277     add = 0;
13278
13279   switch (code)
13280     {
13281     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13282     case sp_reg: case bp_reg: case si_reg: case di_reg:
13283       s = names16[code - ax_reg + add];
13284       break;
13285     case es_reg: case ss_reg: case cs_reg:
13286     case ds_reg: case fs_reg: case gs_reg:
13287       s = names_seg[code - es_reg + add];
13288       break;
13289     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13290     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13291       USED_REX (0);
13292       if (rex)
13293         s = names8rex[code - al_reg + add];
13294       else
13295         s = names8[code - al_reg];
13296       break;
13297     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13298     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13299       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13300         {
13301           s = names64[code - rAX_reg + add];
13302           break;
13303         }
13304       code += eAX_reg - rAX_reg;
13305       /* Fall through.  */
13306     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13307     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13308       USED_REX (REX_W);
13309       if (rex & REX_W)
13310         s = names64[code - eAX_reg + add];
13311       else
13312         {
13313           if (sizeflag & DFLAG)
13314             s = names32[code - eAX_reg + add];
13315           else
13316             s = names16[code - eAX_reg + add];
13317           used_prefixes |= (prefixes & PREFIX_DATA);
13318         }
13319       break;
13320     default:
13321       s = INTERNAL_DISASSEMBLER_ERROR;
13322       break;
13323     }
13324   oappend (s);
13325 }
13326
13327 static void
13328 OP_IMREG (int code, int sizeflag)
13329 {
13330   const char *s;
13331
13332   switch (code)
13333     {
13334     case indir_dx_reg:
13335       if (intel_syntax)
13336         s = "dx";
13337       else
13338         s = "(%dx)";
13339       break;
13340     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13341     case sp_reg: case bp_reg: case si_reg: case di_reg:
13342       s = names16[code - ax_reg];
13343       break;
13344     case es_reg: case ss_reg: case cs_reg:
13345     case ds_reg: case fs_reg: case gs_reg:
13346       s = names_seg[code - es_reg];
13347       break;
13348     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13349     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13350       USED_REX (0);
13351       if (rex)
13352         s = names8rex[code - al_reg];
13353       else
13354         s = names8[code - al_reg];
13355       break;
13356     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13357     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13358       USED_REX (REX_W);
13359       if (rex & REX_W)
13360         s = names64[code - eAX_reg];
13361       else
13362         {
13363           if (sizeflag & DFLAG)
13364             s = names32[code - eAX_reg];
13365           else
13366             s = names16[code - eAX_reg];
13367           used_prefixes |= (prefixes & PREFIX_DATA);
13368         }
13369       break;
13370     case z_mode_ax_reg:
13371       if ((rex & REX_W) || (sizeflag & DFLAG))
13372         s = *names32;
13373       else
13374         s = *names16;
13375       if (!(rex & REX_W))
13376         used_prefixes |= (prefixes & PREFIX_DATA);
13377       break;
13378     default:
13379       s = INTERNAL_DISASSEMBLER_ERROR;
13380       break;
13381     }
13382   oappend (s);
13383 }
13384
13385 static void
13386 OP_I (int bytemode, int sizeflag)
13387 {
13388   bfd_signed_vma op;
13389   bfd_signed_vma mask = -1;
13390
13391   switch (bytemode)
13392     {
13393     case b_mode:
13394       FETCH_DATA (the_info, codep + 1);
13395       op = *codep++;
13396       mask = 0xff;
13397       break;
13398     case q_mode:
13399       if (address_mode == mode_64bit)
13400         {
13401           op = get32s ();
13402           break;
13403         }
13404       /* Fall through.  */
13405     case v_mode:
13406       USED_REX (REX_W);
13407       if (rex & REX_W)
13408         op = get32s ();
13409       else
13410         {
13411           if (sizeflag & DFLAG)
13412             {
13413               op = get32 ();
13414               mask = 0xffffffff;
13415             }
13416           else
13417             {
13418               op = get16 ();
13419               mask = 0xfffff;
13420             }
13421           used_prefixes |= (prefixes & PREFIX_DATA);
13422         }
13423       break;
13424     case w_mode:
13425       mask = 0xfffff;
13426       op = get16 ();
13427       break;
13428     case const_1_mode:
13429       if (intel_syntax)
13430         oappend ("1");
13431       return;
13432     default:
13433       oappend (INTERNAL_DISASSEMBLER_ERROR);
13434       return;
13435     }
13436
13437   op &= mask;
13438   scratchbuf[0] = '$';
13439   print_operand_value (scratchbuf + 1, 1, op);
13440   oappend (scratchbuf + intel_syntax);
13441   scratchbuf[0] = '\0';
13442 }
13443
13444 static void
13445 OP_I64 (int bytemode, int sizeflag)
13446 {
13447   bfd_signed_vma op;
13448   bfd_signed_vma mask = -1;
13449
13450   if (address_mode != mode_64bit)
13451     {
13452       OP_I (bytemode, sizeflag);
13453       return;
13454     }
13455
13456   switch (bytemode)
13457     {
13458     case b_mode:
13459       FETCH_DATA (the_info, codep + 1);
13460       op = *codep++;
13461       mask = 0xff;
13462       break;
13463     case v_mode:
13464       USED_REX (REX_W);
13465       if (rex & REX_W)
13466         op = get64 ();
13467       else
13468         {
13469           if (sizeflag & DFLAG)
13470             {
13471               op = get32 ();
13472               mask = 0xffffffff;
13473             }
13474           else
13475             {
13476               op = get16 ();
13477               mask = 0xfffff;
13478             }
13479           used_prefixes |= (prefixes & PREFIX_DATA);
13480         }
13481       break;
13482     case w_mode:
13483       mask = 0xfffff;
13484       op = get16 ();
13485       break;
13486     default:
13487       oappend (INTERNAL_DISASSEMBLER_ERROR);
13488       return;
13489     }
13490
13491   op &= mask;
13492   scratchbuf[0] = '$';
13493   print_operand_value (scratchbuf + 1, 1, op);
13494   oappend (scratchbuf + intel_syntax);
13495   scratchbuf[0] = '\0';
13496 }
13497
13498 static void
13499 OP_sI (int bytemode, int sizeflag)
13500 {
13501   bfd_signed_vma op;
13502   bfd_signed_vma mask = -1;
13503
13504   switch (bytemode)
13505     {
13506     case b_mode:
13507       FETCH_DATA (the_info, codep + 1);
13508       op = *codep++;
13509       if ((op & 0x80) != 0)
13510         op -= 0x100;
13511       mask = 0xffffffff;
13512       break;
13513     case v_mode:
13514       USED_REX (REX_W);
13515       if (rex & REX_W)
13516         op = get32s ();
13517       else
13518         {
13519           if (sizeflag & DFLAG)
13520             {
13521               op = get32s ();
13522               mask = 0xffffffff;
13523             }
13524           else
13525             {
13526               mask = 0xffffffff;
13527               op = get16 ();
13528               if ((op & 0x8000) != 0)
13529                 op -= 0x10000;
13530             }
13531           used_prefixes |= (prefixes & PREFIX_DATA);
13532         }
13533       break;
13534     case w_mode:
13535       op = get16 ();
13536       mask = 0xffffffff;
13537       if ((op & 0x8000) != 0)
13538         op -= 0x10000;
13539       break;
13540     default:
13541       oappend (INTERNAL_DISASSEMBLER_ERROR);
13542       return;
13543     }
13544
13545   scratchbuf[0] = '$';
13546   print_operand_value (scratchbuf + 1, 1, op);
13547   oappend (scratchbuf + intel_syntax);
13548 }
13549
13550 static void
13551 OP_J (int bytemode, int sizeflag)
13552 {
13553   bfd_vma disp;
13554   bfd_vma mask = -1;
13555   bfd_vma segment = 0;
13556
13557   switch (bytemode)
13558     {
13559     case b_mode:
13560       FETCH_DATA (the_info, codep + 1);
13561       disp = *codep++;
13562       if ((disp & 0x80) != 0)
13563         disp -= 0x100;
13564       break;
13565     case v_mode:
13566       USED_REX (REX_W);
13567       if ((sizeflag & DFLAG) || (rex & REX_W))
13568         disp = get32s ();
13569       else
13570         {
13571           disp = get16 ();
13572           if ((disp & 0x8000) != 0)
13573             disp -= 0x10000;
13574           /* In 16bit mode, address is wrapped around at 64k within
13575              the same segment.  Otherwise, a data16 prefix on a jump
13576              instruction means that the pc is masked to 16 bits after
13577              the displacement is added!  */
13578           mask = 0xffff;
13579           if ((prefixes & PREFIX_DATA) == 0)
13580             segment = ((start_pc + codep - start_codep)
13581                        & ~((bfd_vma) 0xffff));
13582         }
13583       if (!(rex & REX_W))
13584         used_prefixes |= (prefixes & PREFIX_DATA);
13585       break;
13586     default:
13587       oappend (INTERNAL_DISASSEMBLER_ERROR);
13588       return;
13589     }
13590   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
13591   set_op (disp, 0);
13592   print_operand_value (scratchbuf, 1, disp);
13593   oappend (scratchbuf);
13594 }
13595
13596 static void
13597 OP_SEG (int bytemode, int sizeflag)
13598 {
13599   if (bytemode == w_mode)
13600     oappend (names_seg[modrm.reg]);
13601   else
13602     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13603 }
13604
13605 static void
13606 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13607 {
13608   int seg, offset;
13609
13610   if (sizeflag & DFLAG)
13611     {
13612       offset = get32 ();
13613       seg = get16 ();
13614     }
13615   else
13616     {
13617       offset = get16 ();
13618       seg = get16 ();
13619     }
13620   used_prefixes |= (prefixes & PREFIX_DATA);
13621   if (intel_syntax)
13622     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13623   else
13624     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13625   oappend (scratchbuf);
13626 }
13627
13628 static void
13629 OP_OFF (int bytemode, int sizeflag)
13630 {
13631   bfd_vma off;
13632
13633   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13634     intel_operand_size (bytemode, sizeflag);
13635   append_seg ();
13636
13637   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13638     off = get32 ();
13639   else
13640     off = get16 ();
13641
13642   if (intel_syntax)
13643     {
13644       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13645                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13646         {
13647           oappend (names_seg[ds_reg - es_reg]);
13648           oappend (":");
13649         }
13650     }
13651   print_operand_value (scratchbuf, 1, off);
13652   oappend (scratchbuf);
13653 }
13654
13655 static void
13656 OP_OFF64 (int bytemode, int sizeflag)
13657 {
13658   bfd_vma off;
13659
13660   if (address_mode != mode_64bit
13661       || (prefixes & PREFIX_ADDR))
13662     {
13663       OP_OFF (bytemode, sizeflag);
13664       return;
13665     }
13666
13667   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13668     intel_operand_size (bytemode, sizeflag);
13669   append_seg ();
13670
13671   off = get64 ();
13672
13673   if (intel_syntax)
13674     {
13675       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13676                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13677         {
13678           oappend (names_seg[ds_reg - es_reg]);
13679           oappend (":");
13680         }
13681     }
13682   print_operand_value (scratchbuf, 1, off);
13683   oappend (scratchbuf);
13684 }
13685
13686 static void
13687 ptr_reg (int code, int sizeflag)
13688 {
13689   const char *s;
13690
13691   *obufp++ = open_char;
13692   used_prefixes |= (prefixes & PREFIX_ADDR);
13693   if (address_mode == mode_64bit)
13694     {
13695       if (!(sizeflag & AFLAG))
13696         s = names32[code - eAX_reg];
13697       else
13698         s = names64[code - eAX_reg];
13699     }
13700   else if (sizeflag & AFLAG)
13701     s = names32[code - eAX_reg];
13702   else
13703     s = names16[code - eAX_reg];
13704   oappend (s);
13705   *obufp++ = close_char;
13706   *obufp = 0;
13707 }
13708
13709 static void
13710 OP_ESreg (int code, int sizeflag)
13711 {
13712   if (intel_syntax)
13713     {
13714       switch (codep[-1])
13715         {
13716         case 0x6d:      /* insw/insl */
13717           intel_operand_size (z_mode, sizeflag);
13718           break;
13719         case 0xa5:      /* movsw/movsl/movsq */
13720         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13721         case 0xab:      /* stosw/stosl */
13722         case 0xaf:      /* scasw/scasl */
13723           intel_operand_size (v_mode, sizeflag);
13724           break;
13725         default:
13726           intel_operand_size (b_mode, sizeflag);
13727         }
13728     }
13729   oappend ("%es:" + intel_syntax);
13730   ptr_reg (code, sizeflag);
13731 }
13732
13733 static void
13734 OP_DSreg (int code, int sizeflag)
13735 {
13736   if (intel_syntax)
13737     {
13738       switch (codep[-1])
13739         {
13740         case 0x6f:      /* outsw/outsl */
13741           intel_operand_size (z_mode, sizeflag);
13742           break;
13743         case 0xa5:      /* movsw/movsl/movsq */
13744         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13745         case 0xad:      /* lodsw/lodsl/lodsq */
13746           intel_operand_size (v_mode, sizeflag);
13747           break;
13748         default:
13749           intel_operand_size (b_mode, sizeflag);
13750         }
13751     }
13752   if ((prefixes
13753        & (PREFIX_CS
13754           | PREFIX_DS
13755           | PREFIX_SS
13756           | PREFIX_ES
13757           | PREFIX_FS
13758           | PREFIX_GS)) == 0)
13759     prefixes |= PREFIX_DS;
13760   append_seg ();
13761   ptr_reg (code, sizeflag);
13762 }
13763
13764 static void
13765 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13766 {
13767   int add;
13768   if (rex & REX_R)
13769     {
13770       USED_REX (REX_R);
13771       add = 8;
13772     }
13773   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13774     {
13775       all_prefixes[last_lock_prefix] = 0;
13776       used_prefixes |= PREFIX_LOCK;
13777       add = 8;
13778     }
13779   else
13780     add = 0;
13781   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13782   oappend (scratchbuf + intel_syntax);
13783 }
13784
13785 static void
13786 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13787 {
13788   int add;
13789   USED_REX (REX_R);
13790   if (rex & REX_R)
13791     add = 8;
13792   else
13793     add = 0;
13794   if (intel_syntax)
13795     sprintf (scratchbuf, "db%d", modrm.reg + add);
13796   else
13797     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13798   oappend (scratchbuf);
13799 }
13800
13801 static void
13802 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13803 {
13804   sprintf (scratchbuf, "%%tr%d", modrm.reg);
13805   oappend (scratchbuf + intel_syntax);
13806 }
13807
13808 static void
13809 OP_R (int bytemode, int sizeflag)
13810 {
13811   if (modrm.mod == 3)
13812     OP_E (bytemode, sizeflag);
13813   else
13814     BadOp ();
13815 }
13816
13817 static void
13818 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13819 {
13820   int reg = modrm.reg;
13821   const char **names;
13822
13823   used_prefixes |= (prefixes & PREFIX_DATA);
13824   if (prefixes & PREFIX_DATA)
13825     {
13826       names = names_xmm;
13827       USED_REX (REX_R);
13828       if (rex & REX_R)
13829         reg += 8;
13830     }
13831   else
13832     names = names_mm;
13833   oappend (names[reg]);
13834 }
13835
13836 static void
13837 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13838 {
13839   int reg = modrm.reg;
13840   const char **names;
13841
13842   USED_REX (REX_R);
13843   if (rex & REX_R)
13844     reg += 8;
13845   if (need_vex
13846       && bytemode != xmm_mode
13847       && bytemode != scalar_mode)
13848     {
13849       switch (vex.length)
13850         {
13851         case 128:
13852           names = names_xmm;
13853           break;
13854         case 256:
13855           names = names_ymm;
13856           break;
13857         default:
13858           abort ();
13859         }
13860     }
13861   else
13862     names = names_xmm;
13863   oappend (names[reg]);
13864 }
13865
13866 static void
13867 OP_EM (int bytemode, int sizeflag)
13868 {
13869   int reg;
13870   const char **names;
13871
13872   if (modrm.mod != 3)
13873     {
13874       if (intel_syntax
13875           && (bytemode == v_mode || bytemode == v_swap_mode))
13876         {
13877           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13878           used_prefixes |= (prefixes & PREFIX_DATA);
13879         }
13880       OP_E (bytemode, sizeflag);
13881       return;
13882     }
13883
13884   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13885     swap_operand ();
13886
13887   /* Skip mod/rm byte.  */
13888   MODRM_CHECK;
13889   codep++;
13890   used_prefixes |= (prefixes & PREFIX_DATA);
13891   reg = modrm.rm;
13892   if (prefixes & PREFIX_DATA)
13893     {
13894       names = names_xmm;
13895       USED_REX (REX_B);
13896       if (rex & REX_B)
13897         reg += 8;
13898     }
13899   else
13900     names = names_mm;
13901   oappend (names[reg]);
13902 }
13903
13904 /* cvt* are the only instructions in sse2 which have
13905    both SSE and MMX operands and also have 0x66 prefix
13906    in their opcode. 0x66 was originally used to differentiate
13907    between SSE and MMX instruction(operands). So we have to handle the
13908    cvt* separately using OP_EMC and OP_MXC */
13909 static void
13910 OP_EMC (int bytemode, int sizeflag)
13911 {
13912   if (modrm.mod != 3)
13913     {
13914       if (intel_syntax && bytemode == v_mode)
13915         {
13916           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13917           used_prefixes |= (prefixes & PREFIX_DATA);
13918         }
13919       OP_E (bytemode, sizeflag);
13920       return;
13921     }
13922
13923   /* Skip mod/rm byte.  */
13924   MODRM_CHECK;
13925   codep++;
13926   used_prefixes |= (prefixes & PREFIX_DATA);
13927   oappend (names_mm[modrm.rm]);
13928 }
13929
13930 static void
13931 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13932 {
13933   used_prefixes |= (prefixes & PREFIX_DATA);
13934   oappend (names_mm[modrm.reg]);
13935 }
13936
13937 static void
13938 OP_EX (int bytemode, int sizeflag)
13939 {
13940   int reg;
13941   const char **names;
13942
13943   /* Skip mod/rm byte.  */
13944   MODRM_CHECK;
13945   codep++;
13946
13947   if (modrm.mod != 3)
13948     {
13949       OP_E_memory (bytemode, sizeflag);
13950       return;
13951     }
13952
13953   reg = modrm.rm;
13954   USED_REX (REX_B);
13955   if (rex & REX_B)
13956     reg += 8;
13957
13958   if ((sizeflag & SUFFIX_ALWAYS)
13959       && (bytemode == x_swap_mode
13960           || bytemode == d_swap_mode
13961           || bytemode == d_scalar_swap_mode
13962           || bytemode == q_swap_mode
13963           || bytemode == q_scalar_swap_mode))
13964     swap_operand ();
13965
13966   if (need_vex
13967       && bytemode != xmm_mode
13968       && bytemode != xmmq_mode
13969       && bytemode != d_scalar_mode
13970       && bytemode != d_scalar_swap_mode
13971       && bytemode != q_scalar_mode
13972       && bytemode != q_scalar_swap_mode)
13973     {
13974       switch (vex.length)
13975         {
13976         case 128:
13977           names = names_xmm;
13978           break;
13979         case 256:
13980           names = names_ymm;
13981           break;
13982         default:
13983           abort ();
13984         }
13985     }
13986   else
13987     names = names_xmm;
13988   oappend (names[reg]);
13989 }
13990
13991 static void
13992 OP_MS (int bytemode, int sizeflag)
13993 {
13994   if (modrm.mod == 3)
13995     OP_EM (bytemode, sizeflag);
13996   else
13997     BadOp ();
13998 }
13999
14000 static void
14001 OP_XS (int bytemode, int sizeflag)
14002 {
14003   if (modrm.mod == 3)
14004     OP_EX (bytemode, sizeflag);
14005   else
14006     BadOp ();
14007 }
14008
14009 static void
14010 OP_M (int bytemode, int sizeflag)
14011 {
14012   if (modrm.mod == 3)
14013     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14014     BadOp ();
14015   else
14016     OP_E (bytemode, sizeflag);
14017 }
14018
14019 static void
14020 OP_0f07 (int bytemode, int sizeflag)
14021 {
14022   if (modrm.mod != 3 || modrm.rm != 0)
14023     BadOp ();
14024   else
14025     OP_E (bytemode, sizeflag);
14026 }
14027
14028 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14029    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
14030
14031 static void
14032 NOP_Fixup1 (int bytemode, int sizeflag)
14033 {
14034   if ((prefixes & PREFIX_DATA) != 0
14035       || (rex != 0
14036           && rex != 0x48
14037           && address_mode == mode_64bit))
14038     OP_REG (bytemode, sizeflag);
14039   else
14040     strcpy (obuf, "nop");
14041 }
14042
14043 static void
14044 NOP_Fixup2 (int bytemode, int sizeflag)
14045 {
14046   if ((prefixes & PREFIX_DATA) != 0
14047       || (rex != 0
14048           && rex != 0x48
14049           && address_mode == mode_64bit))
14050     OP_IMREG (bytemode, sizeflag);
14051 }
14052
14053 static const char *const Suffix3DNow[] = {
14054 /* 00 */        NULL,           NULL,           NULL,           NULL,
14055 /* 04 */        NULL,           NULL,           NULL,           NULL,
14056 /* 08 */        NULL,           NULL,           NULL,           NULL,
14057 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
14058 /* 10 */        NULL,           NULL,           NULL,           NULL,
14059 /* 14 */        NULL,           NULL,           NULL,           NULL,
14060 /* 18 */        NULL,           NULL,           NULL,           NULL,
14061 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
14062 /* 20 */        NULL,           NULL,           NULL,           NULL,
14063 /* 24 */        NULL,           NULL,           NULL,           NULL,
14064 /* 28 */        NULL,           NULL,           NULL,           NULL,
14065 /* 2C */        NULL,           NULL,           NULL,           NULL,
14066 /* 30 */        NULL,           NULL,           NULL,           NULL,
14067 /* 34 */        NULL,           NULL,           NULL,           NULL,
14068 /* 38 */        NULL,           NULL,           NULL,           NULL,
14069 /* 3C */        NULL,           NULL,           NULL,           NULL,
14070 /* 40 */        NULL,           NULL,           NULL,           NULL,
14071 /* 44 */        NULL,           NULL,           NULL,           NULL,
14072 /* 48 */        NULL,           NULL,           NULL,           NULL,
14073 /* 4C */        NULL,           NULL,           NULL,           NULL,
14074 /* 50 */        NULL,           NULL,           NULL,           NULL,
14075 /* 54 */        NULL,           NULL,           NULL,           NULL,
14076 /* 58 */        NULL,           NULL,           NULL,           NULL,
14077 /* 5C */        NULL,           NULL,           NULL,           NULL,
14078 /* 60 */        NULL,           NULL,           NULL,           NULL,
14079 /* 64 */        NULL,           NULL,           NULL,           NULL,
14080 /* 68 */        NULL,           NULL,           NULL,           NULL,
14081 /* 6C */        NULL,           NULL,           NULL,           NULL,
14082 /* 70 */        NULL,           NULL,           NULL,           NULL,
14083 /* 74 */        NULL,           NULL,           NULL,           NULL,
14084 /* 78 */        NULL,           NULL,           NULL,           NULL,
14085 /* 7C */        NULL,           NULL,           NULL,           NULL,
14086 /* 80 */        NULL,           NULL,           NULL,           NULL,
14087 /* 84 */        NULL,           NULL,           NULL,           NULL,
14088 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14089 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14090 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14091 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14092 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14093 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14094 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14095 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14096 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14097 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14098 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14099 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14100 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14101 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14102 /* C0 */        NULL,           NULL,           NULL,           NULL,
14103 /* C4 */        NULL,           NULL,           NULL,           NULL,
14104 /* C8 */        NULL,           NULL,           NULL,           NULL,
14105 /* CC */        NULL,           NULL,           NULL,           NULL,
14106 /* D0 */        NULL,           NULL,           NULL,           NULL,
14107 /* D4 */        NULL,           NULL,           NULL,           NULL,
14108 /* D8 */        NULL,           NULL,           NULL,           NULL,
14109 /* DC */        NULL,           NULL,           NULL,           NULL,
14110 /* E0 */        NULL,           NULL,           NULL,           NULL,
14111 /* E4 */        NULL,           NULL,           NULL,           NULL,
14112 /* E8 */        NULL,           NULL,           NULL,           NULL,
14113 /* EC */        NULL,           NULL,           NULL,           NULL,
14114 /* F0 */        NULL,           NULL,           NULL,           NULL,
14115 /* F4 */        NULL,           NULL,           NULL,           NULL,
14116 /* F8 */        NULL,           NULL,           NULL,           NULL,
14117 /* FC */        NULL,           NULL,           NULL,           NULL,
14118 };
14119
14120 static void
14121 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14122 {
14123   const char *mnemonic;
14124
14125   FETCH_DATA (the_info, codep + 1);
14126   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14127      place where an 8-bit immediate would normally go.  ie. the last
14128      byte of the instruction.  */
14129   obufp = mnemonicendp;
14130   mnemonic = Suffix3DNow[*codep++ & 0xff];
14131   if (mnemonic)
14132     oappend (mnemonic);
14133   else
14134     {
14135       /* Since a variable sized modrm/sib chunk is between the start
14136          of the opcode (0x0f0f) and the opcode suffix, we need to do
14137          all the modrm processing first, and don't know until now that
14138          we have a bad opcode.  This necessitates some cleaning up.  */
14139       op_out[0][0] = '\0';
14140       op_out[1][0] = '\0';
14141       BadOp ();
14142     }
14143   mnemonicendp = obufp;
14144 }
14145
14146 static struct op simd_cmp_op[] =
14147 {
14148   { STRING_COMMA_LEN ("eq") },
14149   { STRING_COMMA_LEN ("lt") },
14150   { STRING_COMMA_LEN ("le") },
14151   { STRING_COMMA_LEN ("unord") },
14152   { STRING_COMMA_LEN ("neq") },
14153   { STRING_COMMA_LEN ("nlt") },
14154   { STRING_COMMA_LEN ("nle") },
14155   { STRING_COMMA_LEN ("ord") }
14156 };
14157
14158 static void
14159 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14160 {
14161   unsigned int cmp_type;
14162
14163   FETCH_DATA (the_info, codep + 1);
14164   cmp_type = *codep++ & 0xff;
14165   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14166     {
14167       char suffix [3];
14168       char *p = mnemonicendp - 2;
14169       suffix[0] = p[0];
14170       suffix[1] = p[1];
14171       suffix[2] = '\0';
14172       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14173       mnemonicendp += simd_cmp_op[cmp_type].len;
14174     }
14175   else
14176     {
14177       /* We have a reserved extension byte.  Output it directly.  */
14178       scratchbuf[0] = '$';
14179       print_operand_value (scratchbuf + 1, 1, cmp_type);
14180       oappend (scratchbuf + intel_syntax);
14181       scratchbuf[0] = '\0';
14182     }
14183 }
14184
14185 static void
14186 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14187           int sizeflag ATTRIBUTE_UNUSED)
14188 {
14189   /* mwait %eax,%ecx  */
14190   if (!intel_syntax)
14191     {
14192       const char **names = (address_mode == mode_64bit
14193                             ? names64 : names32);
14194       strcpy (op_out[0], names[0]);
14195       strcpy (op_out[1], names[1]);
14196       two_source_ops = 1;
14197     }
14198   /* Skip mod/rm byte.  */
14199   MODRM_CHECK;
14200   codep++;
14201 }
14202
14203 static void
14204 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14205             int sizeflag ATTRIBUTE_UNUSED)
14206 {
14207   /* monitor %eax,%ecx,%edx"  */
14208   if (!intel_syntax)
14209     {
14210       const char **op1_names;
14211       const char **names = (address_mode == mode_64bit
14212                             ? names64 : names32);
14213
14214       if (!(prefixes & PREFIX_ADDR))
14215         op1_names = (address_mode == mode_16bit
14216                      ? names16 : names);
14217       else
14218         {
14219           /* Remove "addr16/addr32".  */
14220           all_prefixes[last_addr_prefix] = 0;
14221           op1_names = (address_mode != mode_32bit
14222                        ? names32 : names16);
14223           used_prefixes |= PREFIX_ADDR;
14224         }
14225       strcpy (op_out[0], op1_names[0]);
14226       strcpy (op_out[1], names[1]);
14227       strcpy (op_out[2], names[2]);
14228       two_source_ops = 1;
14229     }
14230   /* Skip mod/rm byte.  */
14231   MODRM_CHECK;
14232   codep++;
14233 }
14234
14235 static void
14236 BadOp (void)
14237 {
14238   /* Throw away prefixes and 1st. opcode byte.  */
14239   codep = insn_codep + 1;
14240   oappend ("(bad)");
14241 }
14242
14243 static void
14244 REP_Fixup (int bytemode, int sizeflag)
14245 {
14246   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14247      lods and stos.  */
14248   if (prefixes & PREFIX_REPZ)
14249     all_prefixes[last_repz_prefix] = REP_PREFIX;
14250
14251   switch (bytemode)
14252     {
14253     case al_reg:
14254     case eAX_reg:
14255     case indir_dx_reg:
14256       OP_IMREG (bytemode, sizeflag);
14257       break;
14258     case eDI_reg:
14259       OP_ESreg (bytemode, sizeflag);
14260       break;
14261     case eSI_reg:
14262       OP_DSreg (bytemode, sizeflag);
14263       break;
14264     default:
14265       abort ();
14266       break;
14267     }
14268 }
14269
14270 static void
14271 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14272 {
14273   USED_REX (REX_W);
14274   if (rex & REX_W)
14275     {
14276       /* Change cmpxchg8b to cmpxchg16b.  */
14277       char *p = mnemonicendp - 2;
14278       mnemonicendp = stpcpy (p, "16b");
14279       bytemode = o_mode;
14280     }
14281   OP_M (bytemode, sizeflag);
14282 }
14283
14284 static void
14285 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14286 {
14287   const char **names;
14288
14289   if (need_vex)
14290     {
14291       switch (vex.length)
14292         {
14293         case 128:
14294           names = names_xmm;
14295           break;
14296         case 256:
14297           names = names_ymm;
14298           break;
14299         default:
14300           abort ();
14301         }
14302     }
14303   else
14304     names = names_xmm;
14305   oappend (names[reg]);
14306 }
14307
14308 static void
14309 CRC32_Fixup (int bytemode, int sizeflag)
14310 {
14311   /* Add proper suffix to "crc32".  */
14312   char *p = mnemonicendp;
14313
14314   switch (bytemode)
14315     {
14316     case b_mode:
14317       if (intel_syntax)
14318         goto skip;
14319
14320       *p++ = 'b';
14321       break;
14322     case v_mode:
14323       if (intel_syntax)
14324         goto skip;
14325
14326       USED_REX (REX_W);
14327       if (rex & REX_W)
14328         *p++ = 'q';
14329       else
14330         {
14331           if (sizeflag & DFLAG)
14332             *p++ = 'l';
14333           else
14334             *p++ = 'w';
14335           used_prefixes |= (prefixes & PREFIX_DATA);
14336         }
14337       break;
14338     default:
14339       oappend (INTERNAL_DISASSEMBLER_ERROR);
14340       break;
14341     }
14342   mnemonicendp = p;
14343   *p = '\0';
14344
14345 skip:
14346   if (modrm.mod == 3)
14347     {
14348       int add;
14349
14350       /* Skip mod/rm byte.  */
14351       MODRM_CHECK;
14352       codep++;
14353
14354       USED_REX (REX_B);
14355       add = (rex & REX_B) ? 8 : 0;
14356       if (bytemode == b_mode)
14357         {
14358           USED_REX (0);
14359           if (rex)
14360             oappend (names8rex[modrm.rm + add]);
14361           else
14362             oappend (names8[modrm.rm + add]);
14363         }
14364       else
14365         {
14366           USED_REX (REX_W);
14367           if (rex & REX_W)
14368             oappend (names64[modrm.rm + add]);
14369           else if ((prefixes & PREFIX_DATA))
14370             oappend (names16[modrm.rm + add]);
14371           else
14372             oappend (names32[modrm.rm + add]);
14373         }
14374     }
14375   else
14376     OP_E (bytemode, sizeflag);
14377 }
14378
14379 static void
14380 FXSAVE_Fixup (int bytemode, int sizeflag)
14381 {
14382   /* Add proper suffix to "fxsave" and "fxrstor".  */
14383   USED_REX (REX_W);
14384   if (rex & REX_W)
14385     {
14386       char *p = mnemonicendp;
14387       *p++ = '6';
14388       *p++ = '4';
14389       *p = '\0';
14390       mnemonicendp = p;
14391     }
14392   OP_M (bytemode, sizeflag);
14393 }
14394
14395 /* Display the destination register operand for instructions with
14396    VEX. */
14397
14398 static void
14399 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14400 {
14401   int reg;
14402   const char **names;
14403
14404   if (!need_vex)
14405     abort ();
14406
14407   if (!need_vex_reg)
14408     return;
14409
14410   reg = vex.register_specifier;
14411   if (bytemode == vex_scalar_mode)
14412     {
14413       oappend (names_xmm[reg]);
14414       return;
14415     }
14416
14417   switch (vex.length)
14418     {
14419     case 128:
14420       switch (bytemode)
14421         {
14422         case vex_mode:
14423         case vex128_mode:
14424           break;
14425         default:
14426           abort ();
14427           return;
14428         }
14429
14430       names = names_xmm;
14431       break;
14432     case 256:
14433       switch (bytemode)
14434         {
14435         case vex_mode:
14436         case vex256_mode:
14437           break;
14438         default:
14439           abort ();
14440           return;
14441         }
14442
14443       names = names_ymm;
14444       break;
14445     default:
14446       abort ();
14447       break;
14448     }
14449   oappend (names[reg]);
14450 }
14451
14452 /* Get the VEX immediate byte without moving codep.  */
14453
14454 static unsigned char
14455 get_vex_imm8 (int sizeflag, int opnum)
14456 {
14457   int bytes_before_imm = 0;
14458
14459   if (modrm.mod != 3)
14460     {
14461       /* There are SIB/displacement bytes.  */
14462       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14463         {
14464           /* 32/64 bit address mode */
14465           int base = modrm.rm;
14466
14467           /* Check SIB byte.  */
14468           if (base == 4)
14469             {
14470               FETCH_DATA (the_info, codep + 1);
14471               base = *codep & 7;
14472               /* When decoding the third source, don't increase
14473                  bytes_before_imm as this has already been incremented
14474                  by one in OP_E_memory while decoding the second
14475                  source operand.  */
14476               if (opnum == 0)
14477                 bytes_before_imm++;
14478             }
14479
14480           /* Don't increase bytes_before_imm when decoding the third source,
14481              it has already been incremented by OP_E_memory while decoding
14482              the second source operand.  */
14483           if (opnum == 0)
14484             {
14485               switch (modrm.mod)
14486                 {
14487                   case 0:
14488                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14489                        SIB == 5, there is a 4 byte displacement.  */
14490                     if (base != 5)
14491                       /* No displacement. */
14492                       break;
14493                   case 2:
14494                     /* 4 byte displacement.  */
14495                     bytes_before_imm += 4;
14496                     break;
14497                   case 1:
14498                     /* 1 byte displacement.  */
14499                     bytes_before_imm++;
14500                     break;
14501                 }
14502             }
14503         }
14504       else
14505         {
14506           /* 16 bit address mode */
14507           /* Don't increase bytes_before_imm when decoding the third source,
14508              it has already been incremented by OP_E_memory while decoding
14509              the second source operand.  */
14510           if (opnum == 0)
14511             {
14512               switch (modrm.mod)
14513                 {
14514                 case 0:
14515                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14516                   if (modrm.rm != 6)
14517                     /* No displacement. */
14518                     break;
14519                 case 2:
14520                   /* 2 byte displacement.  */
14521                   bytes_before_imm += 2;
14522                   break;
14523                 case 1:
14524                   /* 1 byte displacement: when decoding the third source,
14525                      don't increase bytes_before_imm as this has already
14526                      been incremented by one in OP_E_memory while decoding
14527                      the second source operand.  */
14528                   if (opnum == 0)
14529                     bytes_before_imm++;
14530
14531                   break;
14532                 }
14533             }
14534         }
14535     }
14536
14537   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14538   return codep [bytes_before_imm];
14539 }
14540
14541 static void
14542 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14543 {
14544   const char **names;
14545
14546   if (reg == -1 && modrm.mod != 3)
14547     {
14548       OP_E_memory (bytemode, sizeflag);
14549       return;
14550     }
14551   else
14552     {
14553       if (reg == -1)
14554         {
14555           reg = modrm.rm;
14556           USED_REX (REX_B);
14557           if (rex & REX_B)
14558             reg += 8;
14559         }
14560       else if (reg > 7 && address_mode != mode_64bit)
14561         BadOp ();
14562     }
14563
14564   switch (vex.length)
14565     {
14566     case 128:
14567       names = names_xmm;
14568       break;
14569     case 256:
14570       names = names_ymm;
14571       break;
14572     default:
14573       abort ();
14574     }
14575   oappend (names[reg]);
14576 }
14577
14578 static void
14579 OP_Vex_2src (int bytemode, int sizeflag)
14580 {
14581   if (modrm.mod == 3)
14582     {
14583       int reg = modrm.rm;
14584       USED_REX (REX_B);
14585       if (rex & REX_B)
14586         reg += 8;
14587       oappend (names_xmm[reg]);
14588     }
14589   else
14590     {
14591       if (intel_syntax
14592           && (bytemode == v_mode || bytemode == v_swap_mode))
14593         {
14594           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14595           used_prefixes |= (prefixes & PREFIX_DATA);
14596         }
14597       OP_E (bytemode, sizeflag);
14598     }
14599 }
14600
14601 static void
14602 OP_Vex_2src_1 (int bytemode, int sizeflag)
14603 {
14604   if (modrm.mod == 3)
14605     {
14606       /* Skip mod/rm byte.   */
14607       MODRM_CHECK;
14608       codep++;
14609     }
14610
14611   if (vex.w)
14612     oappend (names_xmm[vex.register_specifier]);
14613   else
14614     OP_Vex_2src (bytemode, sizeflag);
14615 }
14616
14617 static void
14618 OP_Vex_2src_2 (int bytemode, int sizeflag)
14619 {
14620   if (vex.w)
14621     OP_Vex_2src (bytemode, sizeflag);
14622   else
14623     oappend (names_xmm[vex.register_specifier]);
14624 }
14625
14626 static void
14627 OP_EX_VexW (int bytemode, int sizeflag)
14628 {
14629   int reg = -1;
14630
14631   if (!vex_w_done)
14632     {
14633       vex_w_done = 1;
14634
14635       /* Skip mod/rm byte.  */
14636       MODRM_CHECK;
14637       codep++;
14638
14639       if (vex.w)
14640         reg = get_vex_imm8 (sizeflag, 0) >> 4;
14641     }
14642   else
14643     {
14644       if (!vex.w)
14645         reg = get_vex_imm8 (sizeflag, 1) >> 4;
14646     }
14647
14648   OP_EX_VexReg (bytemode, sizeflag, reg);
14649 }
14650
14651 static void
14652 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14653              int sizeflag ATTRIBUTE_UNUSED)
14654 {
14655   /* Skip the immediate byte and check for invalid bits.  */
14656   FETCH_DATA (the_info, codep + 1);
14657   if (*codep++ & 0xf)
14658     BadOp ();
14659 }
14660
14661 static void
14662 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14663 {
14664   int reg;
14665   const char **names;
14666
14667   FETCH_DATA (the_info, codep + 1);
14668   reg = *codep++;
14669
14670   if (bytemode != x_mode)
14671     abort ();
14672
14673   if (reg & 0xf)
14674       BadOp ();
14675
14676   reg >>= 4;
14677   if (reg > 7 && address_mode != mode_64bit)
14678     BadOp ();
14679
14680   switch (vex.length)
14681     {
14682     case 128:
14683       names = names_xmm;
14684       break;
14685     case 256:
14686       names = names_ymm;
14687       break;
14688     default:
14689       abort ();
14690     }
14691   oappend (names[reg]);
14692 }
14693
14694 static void
14695 OP_XMM_VexW (int bytemode, int sizeflag)
14696 {
14697   /* Turn off the REX.W bit since it is used for swapping operands
14698      now.  */
14699   rex &= ~REX_W;
14700   OP_XMM (bytemode, sizeflag);
14701 }
14702
14703 static void
14704 OP_EX_Vex (int bytemode, int sizeflag)
14705 {
14706   if (modrm.mod != 3)
14707     {
14708       if (vex.register_specifier != 0)
14709         BadOp ();
14710       need_vex_reg = 0;
14711     }
14712   OP_EX (bytemode, sizeflag);
14713 }
14714
14715 static void
14716 OP_XMM_Vex (int bytemode, int sizeflag)
14717 {
14718   if (modrm.mod != 3)
14719     {
14720       if (vex.register_specifier != 0)
14721         BadOp ();
14722       need_vex_reg = 0;
14723     }
14724   OP_XMM (bytemode, sizeflag);
14725 }
14726
14727 static void
14728 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14729 {
14730   switch (vex.length)
14731     {
14732     case 128:
14733       mnemonicendp = stpcpy (obuf, "vzeroupper");
14734       break;
14735     case 256:
14736       mnemonicendp = stpcpy (obuf, "vzeroall");
14737       break;
14738     default:
14739       abort ();
14740     }
14741 }
14742
14743 static struct op vex_cmp_op[] =
14744 {
14745   { STRING_COMMA_LEN ("eq") },
14746   { STRING_COMMA_LEN ("lt") },
14747   { STRING_COMMA_LEN ("le") },
14748   { STRING_COMMA_LEN ("unord") },
14749   { STRING_COMMA_LEN ("neq") },
14750   { STRING_COMMA_LEN ("nlt") },
14751   { STRING_COMMA_LEN ("nle") },
14752   { STRING_COMMA_LEN ("ord") },
14753   { STRING_COMMA_LEN ("eq_uq") },
14754   { STRING_COMMA_LEN ("nge") },
14755   { STRING_COMMA_LEN ("ngt") },
14756   { STRING_COMMA_LEN ("false") },
14757   { STRING_COMMA_LEN ("neq_oq") },
14758   { STRING_COMMA_LEN ("ge") },
14759   { STRING_COMMA_LEN ("gt") },
14760   { STRING_COMMA_LEN ("true") },
14761   { STRING_COMMA_LEN ("eq_os") },
14762   { STRING_COMMA_LEN ("lt_oq") },
14763   { STRING_COMMA_LEN ("le_oq") },
14764   { STRING_COMMA_LEN ("unord_s") },
14765   { STRING_COMMA_LEN ("neq_us") },
14766   { STRING_COMMA_LEN ("nlt_uq") },
14767   { STRING_COMMA_LEN ("nle_uq") },
14768   { STRING_COMMA_LEN ("ord_s") },
14769   { STRING_COMMA_LEN ("eq_us") },
14770   { STRING_COMMA_LEN ("nge_uq") },
14771   { STRING_COMMA_LEN ("ngt_uq") },
14772   { STRING_COMMA_LEN ("false_os") },
14773   { STRING_COMMA_LEN ("neq_os") },
14774   { STRING_COMMA_LEN ("ge_oq") },
14775   { STRING_COMMA_LEN ("gt_oq") },
14776   { STRING_COMMA_LEN ("true_us") },
14777 };
14778
14779 static void
14780 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14781 {
14782   unsigned int cmp_type;
14783
14784   FETCH_DATA (the_info, codep + 1);
14785   cmp_type = *codep++ & 0xff;
14786   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14787     {
14788       char suffix [3];
14789       char *p = mnemonicendp - 2;
14790       suffix[0] = p[0];
14791       suffix[1] = p[1];
14792       suffix[2] = '\0';
14793       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14794       mnemonicendp += vex_cmp_op[cmp_type].len;
14795     }
14796   else
14797     {
14798       /* We have a reserved extension byte.  Output it directly.  */
14799       scratchbuf[0] = '$';
14800       print_operand_value (scratchbuf + 1, 1, cmp_type);
14801       oappend (scratchbuf + intel_syntax);
14802       scratchbuf[0] = '\0';
14803     }
14804 }
14805
14806 static const struct op pclmul_op[] =
14807 {
14808   { STRING_COMMA_LEN ("lql") },
14809   { STRING_COMMA_LEN ("hql") },
14810   { STRING_COMMA_LEN ("lqh") },
14811   { STRING_COMMA_LEN ("hqh") }
14812 };
14813
14814 static void
14815 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14816               int sizeflag ATTRIBUTE_UNUSED)
14817 {
14818   unsigned int pclmul_type;
14819
14820   FETCH_DATA (the_info, codep + 1);
14821   pclmul_type = *codep++ & 0xff;
14822   switch (pclmul_type)
14823     {
14824     case 0x10:
14825       pclmul_type = 2;
14826       break;
14827     case 0x11:
14828       pclmul_type = 3;
14829       break;
14830     default:
14831       break;
14832     }
14833   if (pclmul_type < ARRAY_SIZE (pclmul_op))
14834     {
14835       char suffix [4];
14836       char *p = mnemonicendp - 3;
14837       suffix[0] = p[0];
14838       suffix[1] = p[1];
14839       suffix[2] = p[2];
14840       suffix[3] = '\0';
14841       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14842       mnemonicendp += pclmul_op[pclmul_type].len;
14843     }
14844   else
14845     {
14846       /* We have a reserved extension byte.  Output it directly.  */
14847       scratchbuf[0] = '$';
14848       print_operand_value (scratchbuf + 1, 1, pclmul_type);
14849       oappend (scratchbuf + intel_syntax);
14850       scratchbuf[0] = '\0';
14851     }
14852 }
14853
14854 static void
14855 MOVBE_Fixup (int bytemode, int sizeflag)
14856 {
14857   /* Add proper suffix to "movbe".  */
14858   char *p = mnemonicendp;
14859
14860   switch (bytemode)
14861     {
14862     case v_mode:
14863       if (intel_syntax)
14864         goto skip;
14865
14866       USED_REX (REX_W);
14867       if (sizeflag & SUFFIX_ALWAYS)
14868         {
14869           if (rex & REX_W)
14870             *p++ = 'q';
14871           else
14872             {
14873               if (sizeflag & DFLAG)
14874                 *p++ = 'l';
14875               else
14876                 *p++ = 'w';
14877               used_prefixes |= (prefixes & PREFIX_DATA);
14878             }
14879         }
14880       break;
14881     default:
14882       oappend (INTERNAL_DISASSEMBLER_ERROR);
14883       break;
14884     }
14885   mnemonicendp = p;
14886   *p = '\0';
14887
14888 skip:
14889   OP_M (bytemode, sizeflag);
14890 }
14891
14892 static void
14893 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14894 {
14895   int reg;
14896   const char **names;
14897
14898   /* Skip mod/rm byte.  */
14899   MODRM_CHECK;
14900   codep++;
14901
14902   if (vex.w)
14903     names = names64;
14904   else if (vex.length == 256)
14905     names = names32;
14906   else
14907     names = names16;
14908
14909   reg = modrm.rm;
14910   USED_REX (REX_B);
14911   if (rex & REX_B)
14912     reg += 8;
14913
14914   oappend (names[reg]);
14915 }
14916
14917 static void
14918 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14919 {
14920   const char **names;
14921
14922   if (vex.w)
14923     names = names64;
14924   else if (vex.length == 256)
14925     names = names32;
14926   else
14927     names = names16;
14928
14929   oappend (names[vex.register_specifier]);
14930 }
14931
14932 static void
14933 OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
14934 {
14935   if (vex.w || vex.length == 256)
14936     OP_I (q_mode, sizeflag);
14937   else
14938     OP_I (w_mode, sizeflag);
14939 }
14940