opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VEXI4_Fixup (int, int);
 100 static void VZERO_Fixup (int, int);
 101 static void VCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void CMPXCHG8B_Fixup (int, int);
 112 static void XMM_Fixup (int, int);
 113 static void CRC32_Fixup (int, int);
 114 static void FXSAVE_Fixup (int, int);
 115 static void OP_LWPCB_E (int, int);
 116 static void OP_LWP_E (int, int);
 117 static void OP_Vex_2src_1 (int, int);
 118 static void OP_Vex_2src_2 (int, int);
 119
 120 static void MOVBE_Fixup (int, int);
 121
 122 struct dis_private {
 123   /* Points to first byte not fetched.  */
 124   bfd_byte *max_fetched;
 125   bfd_byte the_buffer[MAX_MNEM_SIZE];
 126   bfd_vma insn_start;
 127   int orig_sizeflag;
 128   jmp_buf bailout;
 129 };
 130
 131 enum address_mode
 132 {
 133   mode_16bit,
 134   mode_32bit,
 135   mode_64bit
 136 };
 137
 138 enum address_mode address_mode;
 139
 140 /* Flags for the prefixes for the current instruction.  See below.  */
 141 static int prefixes;
 142
 143 /* REX prefix the current instruction.  See below.  */
 144 static int rex;
 145 /* Bits of REX we've already used.  */
 146 static int rex_used;
 147 /* REX bits in original REX prefix ignored.  */
 148 static int rex_ignored;
 149 /* Mark parts used in the REX prefix.  When we are testing for
 150    empty prefix (for 8bit register REX extension), just mask it
 151    out.  Otherwise test for REX bit is excuse for existence of REX
 152    only in case value is nonzero.  */
 153 #define USED_REX(value)                                 \
 154   {                                                     \
 155     if (value)                                          \
 156       {                                                 \
 157         if ((rex & value))                              \
 158           rex_used |= (value) | REX_OPCODE;             \
 159       }                                                 \
 160     else                                                \
 161       rex_used |= REX_OPCODE;                           \
 162   }
 163
 164 /* Flags for prefixes which we somehow handled when printing the
 165    current instruction.  */
 166 static int used_prefixes;
 167
 168 /* Flags stored in PREFIXES.  */
 169 #define PREFIX_REPZ 1
 170 #define PREFIX_REPNZ 2
 171 #define PREFIX_LOCK 4
 172 #define PREFIX_CS 8
 173 #define PREFIX_SS 0x10
 174 #define PREFIX_DS 0x20
 175 #define PREFIX_ES 0x40
 176 #define PREFIX_FS 0x80
 177 #define PREFIX_GS 0x100
 178 #define PREFIX_DATA 0x200
 179 #define PREFIX_ADDR 0x400
 180 #define PREFIX_FWAIT 0x800
 181
 182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 183    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 184    on error.  */
 185 #define FETCH_DATA(info, addr) \
 186   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 187    ? 1 : fetch_data ((info), (addr)))
 188
 189 static int
 190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 191 {
 192   int status;
 193   struct dis_private *priv = (struct dis_private *) info->private_data;
 194   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 195
 196   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 197     status = (*info->read_memory_func) (start,
 198                                         priv->max_fetched,
 199                                         addr - priv->max_fetched,
 200                                         info);
 201   else
 202     status = -1;
 203   if (status != 0)
 204     {
 205       /* If we did manage to read at least one byte, then
 206          print_insn_i386 will do something sensible.  Otherwise, print
 207          an error.  We do that here because this is where we know
 208          STATUS.  */
 209       if (priv->max_fetched == priv->the_buffer)
 210         (*info->memory_error_func) (status, start, info);
 211       longjmp (priv->bailout, 1);
 212     }
 213   else
 214     priv->max_fetched = addr;
 215   return 1;
 216 }
 217
 218 #define XX { NULL, 0 }
 219 #define Bad_Opcode NULL, { { NULL, 0 } }
 220
 221 #define Eb { OP_E, b_mode }
 222 #define EbS { OP_E, b_swap_mode }
 223 #define Ev { OP_E, v_mode }
 224 #define EvS { OP_E, v_swap_mode }
 225 #define Ed { OP_E, d_mode }
 226 #define Edq { OP_E, dq_mode }
 227 #define Edqw { OP_E, dqw_mode }
 228 #define Edqb { OP_E, dqb_mode }
 229 #define Edqd { OP_E, dqd_mode }
 230 #define Eq { OP_E, q_mode }
 231 #define indirEv { OP_indirE, stack_v_mode }
 232 #define indirEp { OP_indirE, f_mode }
 233 #define stackEv { OP_E, stack_v_mode }
 234 #define Em { OP_E, m_mode }
 235 #define Ew { OP_E, w_mode }
 236 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 237 #define Ma { OP_M, a_mode }
 238 #define Mb { OP_M, b_mode }
 239 #define Md { OP_M, d_mode }
 240 #define Mo { OP_M, o_mode }
 241 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 242 #define Mq { OP_M, q_mode }
 243 #define Mx { OP_M, x_mode }
 244 #define Mxmm { OP_M, xmm_mode }
 245 #define Gb { OP_G, b_mode }
 246 #define Gv { OP_G, v_mode }
 247 #define Gd { OP_G, d_mode }
 248 #define Gdq { OP_G, dq_mode }
 249 #define Gm { OP_G, m_mode }
 250 #define Gw { OP_G, w_mode }
 251 #define Rd { OP_R, d_mode }
 252 #define Rm { OP_R, m_mode }
 253 #define Ib { OP_I, b_mode }
 254 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 255 #define Iv { OP_I, v_mode }
 256 #define sIv { OP_sI, v_mode }
 257 #define Iq { OP_I, q_mode }
 258 #define Iv64 { OP_I64, v_mode }
 259 #define Iw { OP_I, w_mode }
 260 #define I1 { OP_I, const_1_mode }
 261 #define Jb { OP_J, b_mode }
 262 #define Jv { OP_J, v_mode }
 263 #define Cm { OP_C, m_mode }
 264 #define Dm { OP_D, m_mode }
 265 #define Td { OP_T, d_mode }
 266 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 267
 268 #define RMeAX { OP_REG, eAX_reg }
 269 #define RMeBX { OP_REG, eBX_reg }
 270 #define RMeCX { OP_REG, eCX_reg }
 271 #define RMeDX { OP_REG, eDX_reg }
 272 #define RMeSP { OP_REG, eSP_reg }
 273 #define RMeBP { OP_REG, eBP_reg }
 274 #define RMeSI { OP_REG, eSI_reg }
 275 #define RMeDI { OP_REG, eDI_reg }
 276 #define RMrAX { OP_REG, rAX_reg }
 277 #define RMrBX { OP_REG, rBX_reg }
 278 #define RMrCX { OP_REG, rCX_reg }
 279 #define RMrDX { OP_REG, rDX_reg }
 280 #define RMrSP { OP_REG, rSP_reg }
 281 #define RMrBP { OP_REG, rBP_reg }
 282 #define RMrSI { OP_REG, rSI_reg }
 283 #define RMrDI { OP_REG, rDI_reg }
 284 #define RMAL { OP_REG, al_reg }
 285 #define RMCL { OP_REG, cl_reg }
 286 #define RMDL { OP_REG, dl_reg }
 287 #define RMBL { OP_REG, bl_reg }
 288 #define RMAH { OP_REG, ah_reg }
 289 #define RMCH { OP_REG, ch_reg }
 290 #define RMDH { OP_REG, dh_reg }
 291 #define RMBH { OP_REG, bh_reg }
 292 #define RMAX { OP_REG, ax_reg }
 293 #define RMDX { OP_REG, dx_reg }
 294
 295 #define eAX { OP_IMREG, eAX_reg }
 296 #define eBX { OP_IMREG, eBX_reg }
 297 #define eCX { OP_IMREG, eCX_reg }
 298 #define eDX { OP_IMREG, eDX_reg }
 299 #define eSP { OP_IMREG, eSP_reg }
 300 #define eBP { OP_IMREG, eBP_reg }
 301 #define eSI { OP_IMREG, eSI_reg }
 302 #define eDI { OP_IMREG, eDI_reg }
 303 #define AL { OP_IMREG, al_reg }
 304 #define CL { OP_IMREG, cl_reg }
 305 #define DL { OP_IMREG, dl_reg }
 306 #define BL { OP_IMREG, bl_reg }
 307 #define AH { OP_IMREG, ah_reg }
 308 #define CH { OP_IMREG, ch_reg }
 309 #define DH { OP_IMREG, dh_reg }
 310 #define BH { OP_IMREG, bh_reg }
 311 #define AX { OP_IMREG, ax_reg }
 312 #define DX { OP_IMREG, dx_reg }
 313 #define zAX { OP_IMREG, z_mode_ax_reg }
 314 #define indirDX { OP_IMREG, indir_dx_reg }
 315
 316 #define Sw { OP_SEG, w_mode }
 317 #define Sv { OP_SEG, v_mode }
 318 #define Ap { OP_DIR, 0 }
 319 #define Ob { OP_OFF64, b_mode }
 320 #define Ov { OP_OFF64, v_mode }
 321 #define Xb { OP_DSreg, eSI_reg }
 322 #define Xv { OP_DSreg, eSI_reg }
 323 #define Xz { OP_DSreg, eSI_reg }
 324 #define Yb { OP_ESreg, eDI_reg }
 325 #define Yv { OP_ESreg, eDI_reg }
 326 #define DSBX { OP_DSreg, eBX_reg }
 327
 328 #define es { OP_REG, es_reg }
 329 #define ss { OP_REG, ss_reg }
 330 #define cs { OP_REG, cs_reg }
 331 #define ds { OP_REG, ds_reg }
 332 #define fs { OP_REG, fs_reg }
 333 #define gs { OP_REG, gs_reg }
 334
 335 #define MX { OP_MMX, 0 }
 336 #define XM { OP_XMM, 0 }
 337 #define XMScalar { OP_XMM, scalar_mode }
 338 #define XMM { OP_XMM, xmm_mode }
 339 #define EM { OP_EM, v_mode }
 340 #define EMS { OP_EM, v_swap_mode }
 341 #define EMd { OP_EM, d_mode }
 342 #define EMx { OP_EM, x_mode }
 343 #define EXw { OP_EX, w_mode }
 344 #define EXd { OP_EX, d_mode }
 345 #define EXdScalar { OP_EX, d_scalar_mode }
 346 #define EXdS { OP_EX, d_swap_mode }
 347 #define EXq { OP_EX, q_mode }
 348 #define EXqScalar { OP_EX, q_scalar_mode }
 349 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 350 #define EXqS { OP_EX, q_swap_mode }
 351 #define EXx { OP_EX, x_mode }
 352 #define EXxS { OP_EX, x_swap_mode }
 353 #define EXxmm { OP_EX, xmm_mode }
 354 #define EXxmmq { OP_EX, xmmq_mode }
 355 #define EXymmq { OP_EX, ymmq_mode }
 356 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 357 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 358 #define MS { OP_MS, v_mode }
 359 #define XS { OP_XS, v_mode }
 360 #define EMCq { OP_EMC, q_mode }
 361 #define MXC { OP_MXC, 0 }
 362 #define OPSUF { OP_3DNowSuffix, 0 }
 363 #define CMP { CMP_Fixup, 0 }
 364 #define XMM0 { XMM_Fixup, 0 }
 365 #define FXSAVE { FXSAVE_Fixup, 0 }
 366 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 367 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 368
 369 #define Vex { OP_VEX, vex_mode }
 370 #define VexScalar { OP_VEX, vex_scalar_mode }
 371 #define Vex128 { OP_VEX, vex128_mode }
 372 #define Vex256 { OP_VEX, vex256_mode }
 373 #define VexGdq { OP_VEX, dq_mode }
 374 #define VexI4 { VEXI4_Fixup, 0}
 375 #define EXdVex { OP_EX_Vex, d_mode }
 376 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 377 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 378 #define EXqVex { OP_EX_Vex, q_mode }
 379 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 380 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 381 #define EXVexW { OP_EX_VexW, x_mode }
 382 #define EXdVexW { OP_EX_VexW, d_mode }
 383 #define EXqVexW { OP_EX_VexW, q_mode }
 384 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 385 #define XMVex { OP_XMM_Vex, 0 }
 386 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 387 #define XMVexW { OP_XMM_VexW, 0 }
 388 #define XMVexI4 { OP_REG_VexI4, x_mode }
 389 #define PCLMUL { PCLMUL_Fixup, 0 }
 390 #define VZERO { VZERO_Fixup, 0 }
 391 #define VCMP { VCMP_Fixup, 0 }
 392
 393 /* Used handle "rep" prefix for string instructions.  */
 394 #define Xbr { REP_Fixup, eSI_reg }
 395 #define Xvr { REP_Fixup, eSI_reg }
 396 #define Ybr { REP_Fixup, eDI_reg }
 397 #define Yvr { REP_Fixup, eDI_reg }
 398 #define Yzr { REP_Fixup, eDI_reg }
 399 #define indirDXr { REP_Fixup, indir_dx_reg }
 400 #define ALr { REP_Fixup, al_reg }
 401 #define eAXr { REP_Fixup, eAX_reg }
 402
 403 #define cond_jump_flag { NULL, cond_jump_mode }
 404 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 405
 406 /* bits in sizeflag */
 407 #define SUFFIX_ALWAYS 4
 408 #define AFLAG 2
 409 #define DFLAG 1
 410
 411 enum
 412 {
 413   /* byte operand */
 414   b_mode = 1,
 415   /* byte operand with operand swapped */
 416   b_swap_mode,
 417   /* operand size depends on prefixes */
 418   v_mode,
 419   /* operand size depends on prefixes with operand swapped */
 420   v_swap_mode,
 421   /* word operand */
 422   w_mode,
 423   /* double word operand  */
 424   d_mode,
 425   /* double word operand with operand swapped */
 426   d_swap_mode,
 427   /* quad word operand */
 428   q_mode,
 429   /* quad word operand with operand swapped */
 430   q_swap_mode,
 431   /* ten-byte operand */
 432   t_mode,
 433   /* 16-byte XMM or 32-byte YMM operand */
 434   x_mode,
 435   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 436   x_swap_mode,
 437   /* 16-byte XMM operand */
 438   xmm_mode,
 439   /* 16-byte XMM or quad word operand */
 440   xmmq_mode,
 441   /* 32-byte YMM or quad word operand */
 442   ymmq_mode,
 443   /* d_mode in 32bit, q_mode in 64bit mode.  */
 444   m_mode,
 445   /* pair of v_mode operands */
 446   a_mode,
 447   cond_jump_mode,
 448   loop_jcxz_mode,
 449   /* operand size depends on REX prefixes.  */
 450   dq_mode,
 451   /* registers like dq_mode, memory like w_mode.  */
 452   dqw_mode,
 453   /* 4- or 6-byte pointer operand */
 454   f_mode,
 455   const_1_mode,
 456   /* v_mode for stack-related opcodes.  */
 457   stack_v_mode,
 458   /* non-quad operand size depends on prefixes */
 459   z_mode,
 460   /* 16-byte operand */
 461   o_mode,
 462   /* registers like dq_mode, memory like b_mode.  */
 463   dqb_mode,
 464   /* registers like dq_mode, memory like d_mode.  */
 465   dqd_mode,
 466   /* normal vex mode */
 467   vex_mode,
 468   /* 128bit vex mode */
 469   vex128_mode,
 470   /* 256bit vex mode */
 471   vex256_mode,
 472   /* operand size depends on the VEX.W bit.  */
 473   vex_w_dq_mode,
 474
 475   /* scalar, ignore vector length.  */
 476   scalar_mode,
 477   /* like d_mode, ignore vector length.  */
 478   d_scalar_mode,
 479   /* like d_swap_mode, ignore vector length.  */
 480   d_scalar_swap_mode,
 481   /* like q_mode, ignore vector length.  */
 482   q_scalar_mode,
 483   /* like q_swap_mode, ignore vector length.  */
 484   q_scalar_swap_mode,
 485   /* like vex_mode, ignore vector length.  */
 486   vex_scalar_mode,
 487   /* like vex_w_dq_mode, ignore vector length.  */
 488   vex_scalar_w_dq_mode,
 489
 490   es_reg,
 491   cs_reg,
 492   ss_reg,
 493   ds_reg,
 494   fs_reg,
 495   gs_reg,
 496
 497   eAX_reg,
 498   eCX_reg,
 499   eDX_reg,
 500   eBX_reg,
 501   eSP_reg,
 502   eBP_reg,
 503   eSI_reg,
 504   eDI_reg,
 505
 506   al_reg,
 507   cl_reg,
 508   dl_reg,
 509   bl_reg,
 510   ah_reg,
 511   ch_reg,
 512   dh_reg,
 513   bh_reg,
 514
 515   ax_reg,
 516   cx_reg,
 517   dx_reg,
 518   bx_reg,
 519   sp_reg,
 520   bp_reg,
 521   si_reg,
 522   di_reg,
 523
 524   rAX_reg,
 525   rCX_reg,
 526   rDX_reg,
 527   rBX_reg,
 528   rSP_reg,
 529   rBP_reg,
 530   rSI_reg,
 531   rDI_reg,
 532
 533   z_mode_ax_reg,
 534   indir_dx_reg
 535 };
 536
 537 enum
 538 {
 539   FLOATCODE = 1,
 540   USE_REG_TABLE,
 541   USE_MOD_TABLE,
 542   USE_RM_TABLE,
 543   USE_PREFIX_TABLE,
 544   USE_X86_64_TABLE,
 545   USE_3BYTE_TABLE,
 546   USE_XOP_8F_TABLE,
 547   USE_VEX_C4_TABLE,
 548   USE_VEX_C5_TABLE,
 549   USE_VEX_LEN_TABLE,
 550   USE_VEX_W_TABLE
 551 };
 552
 553 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 554
 555 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 556 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 557 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 558 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 559 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 560 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 561 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 562 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 563 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 564 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 565 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 566 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 567
 568 enum
 569 {
 570   REG_80 = 0,
 571   REG_81,
 572   REG_82,
 573   REG_8F,
 574   REG_C0,
 575   REG_C1,
 576   REG_C6,
 577   REG_C7,
 578   REG_D0,
 579   REG_D1,
 580   REG_D2,
 581   REG_D3,
 582   REG_F6,
 583   REG_F7,
 584   REG_FE,
 585   REG_FF,
 586   REG_0F00,
 587   REG_0F01,
 588   REG_0F0D,
 589   REG_0F18,
 590   REG_0F71,
 591   REG_0F72,
 592   REG_0F73,
 593   REG_0FA6,
 594   REG_0FA7,
 595   REG_0FAE,
 596   REG_0FBA,
 597   REG_0FC7,
 598   REG_VEX_0F71,
 599   REG_VEX_0F72,
 600   REG_VEX_0F73,
 601   REG_VEX_0FAE,
 602   REG_VEX_0F38F3,
 603   REG_XOP_LWPCB,
 604   REG_XOP_LWP,
 605   REG_XOP_TBM_01,
 606   REG_XOP_TBM_02
 607 };
 608
 609 enum
 610 {
 611   MOD_8D = 0,
 612   MOD_0F01_REG_0,
 613   MOD_0F01_REG_1,
 614   MOD_0F01_REG_2,
 615   MOD_0F01_REG_3,
 616   MOD_0F01_REG_7,
 617   MOD_0F12_PREFIX_0,
 618   MOD_0F13,
 619   MOD_0F16_PREFIX_0,
 620   MOD_0F17,
 621   MOD_0F18_REG_0,
 622   MOD_0F18_REG_1,
 623   MOD_0F18_REG_2,
 624   MOD_0F18_REG_3,
 625   MOD_0F20,
 626   MOD_0F21,
 627   MOD_0F22,
 628   MOD_0F23,
 629   MOD_0F24,
 630   MOD_0F26,
 631   MOD_0F2B_PREFIX_0,
 632   MOD_0F2B_PREFIX_1,
 633   MOD_0F2B_PREFIX_2,
 634   MOD_0F2B_PREFIX_3,
 635   MOD_0F51,
 636   MOD_0F71_REG_2,
 637   MOD_0F71_REG_4,
 638   MOD_0F71_REG_6,
 639   MOD_0F72_REG_2,
 640   MOD_0F72_REG_4,
 641   MOD_0F72_REG_6,
 642   MOD_0F73_REG_2,
 643   MOD_0F73_REG_3,
 644   MOD_0F73_REG_6,
 645   MOD_0F73_REG_7,
 646   MOD_0FAE_REG_0,
 647   MOD_0FAE_REG_1,
 648   MOD_0FAE_REG_2,
 649   MOD_0FAE_REG_3,
 650   MOD_0FAE_REG_4,
 651   MOD_0FAE_REG_5,
 652   MOD_0FAE_REG_6,
 653   MOD_0FAE_REG_7,
 654   MOD_0FB2,
 655   MOD_0FB4,
 656   MOD_0FB5,
 657   MOD_0FC7_REG_6,
 658   MOD_0FC7_REG_7,
 659   MOD_0FD7,
 660   MOD_0FE7_PREFIX_2,
 661   MOD_0FF0_PREFIX_3,
 662   MOD_0F382A_PREFIX_2,
 663   MOD_62_32BIT,
 664   MOD_C4_32BIT,
 665   MOD_C5_32BIT,
 666   MOD_VEX_0F12_PREFIX_0,
 667   MOD_VEX_0F13,
 668   MOD_VEX_0F16_PREFIX_0,
 669   MOD_VEX_0F17,
 670   MOD_VEX_0F2B,
 671   MOD_VEX_0F50,
 672   MOD_VEX_0F71_REG_2,
 673   MOD_VEX_0F71_REG_4,
 674   MOD_VEX_0F71_REG_6,
 675   MOD_VEX_0F72_REG_2,
 676   MOD_VEX_0F72_REG_4,
 677   MOD_VEX_0F72_REG_6,
 678   MOD_VEX_0F73_REG_2,
 679   MOD_VEX_0F73_REG_3,
 680   MOD_VEX_0F73_REG_6,
 681   MOD_VEX_0F73_REG_7,
 682   MOD_VEX_0FAE_REG_2,
 683   MOD_VEX_0FAE_REG_3,
 684   MOD_VEX_0FD7_PREFIX_2,
 685   MOD_VEX_0FE7_PREFIX_2,
 686   MOD_VEX_0FF0_PREFIX_3,
 687   MOD_VEX_0F3818_PREFIX_2,
 688   MOD_VEX_0F3819_PREFIX_2,
 689   MOD_VEX_0F381A_PREFIX_2,
 690   MOD_VEX_0F382A_PREFIX_2,
 691   MOD_VEX_0F382C_PREFIX_2,
 692   MOD_VEX_0F382D_PREFIX_2,
 693   MOD_VEX_0F382E_PREFIX_2,
 694   MOD_VEX_0F382F_PREFIX_2
 695 };
 696
 697 enum
 698 {
 699   RM_0F01_REG_0 = 0,
 700   RM_0F01_REG_1,
 701   RM_0F01_REG_2,
 702   RM_0F01_REG_3,
 703   RM_0F01_REG_7,
 704   RM_0FAE_REG_5,
 705   RM_0FAE_REG_6,
 706   RM_0FAE_REG_7
 707 };
 708
 709 enum
 710 {
 711   PREFIX_90 = 0,
 712   PREFIX_0F10,
 713   PREFIX_0F11,
 714   PREFIX_0F12,
 715   PREFIX_0F16,
 716   PREFIX_0F2A,
 717   PREFIX_0F2B,
 718   PREFIX_0F2C,
 719   PREFIX_0F2D,
 720   PREFIX_0F2E,
 721   PREFIX_0F2F,
 722   PREFIX_0F51,
 723   PREFIX_0F52,
 724   PREFIX_0F53,
 725   PREFIX_0F58,
 726   PREFIX_0F59,
 727   PREFIX_0F5A,
 728   PREFIX_0F5B,
 729   PREFIX_0F5C,
 730   PREFIX_0F5D,
 731   PREFIX_0F5E,
 732   PREFIX_0F5F,
 733   PREFIX_0F60,
 734   PREFIX_0F61,
 735   PREFIX_0F62,
 736   PREFIX_0F6C,
 737   PREFIX_0F6D,
 738   PREFIX_0F6F,
 739   PREFIX_0F70,
 740   PREFIX_0F73_REG_3,
 741   PREFIX_0F73_REG_7,
 742   PREFIX_0F78,
 743   PREFIX_0F79,
 744   PREFIX_0F7C,
 745   PREFIX_0F7D,
 746   PREFIX_0F7E,
 747   PREFIX_0F7F,
 748   PREFIX_0FAE_REG_0,
 749   PREFIX_0FAE_REG_1,
 750   PREFIX_0FAE_REG_2,
 751   PREFIX_0FAE_REG_3,
 752   PREFIX_0FB8,
 753   PREFIX_0FBC,
 754   PREFIX_0FBD,
 755   PREFIX_0FC2,
 756   PREFIX_0FC3,
 757   PREFIX_0FC7_REG_6,
 758   PREFIX_0FD0,
 759   PREFIX_0FD6,
 760   PREFIX_0FE6,
 761   PREFIX_0FE7,
 762   PREFIX_0FF0,
 763   PREFIX_0FF7,
 764   PREFIX_0F3810,
 765   PREFIX_0F3814,
 766   PREFIX_0F3815,
 767   PREFIX_0F3817,
 768   PREFIX_0F3820,
 769   PREFIX_0F3821,
 770   PREFIX_0F3822,
 771   PREFIX_0F3823,
 772   PREFIX_0F3824,
 773   PREFIX_0F3825,
 774   PREFIX_0F3828,
 775   PREFIX_0F3829,
 776   PREFIX_0F382A,
 777   PREFIX_0F382B,
 778   PREFIX_0F3830,
 779   PREFIX_0F3831,
 780   PREFIX_0F3832,
 781   PREFIX_0F3833,
 782   PREFIX_0F3834,
 783   PREFIX_0F3835,
 784   PREFIX_0F3837,
 785   PREFIX_0F3838,
 786   PREFIX_0F3839,
 787   PREFIX_0F383A,
 788   PREFIX_0F383B,
 789   PREFIX_0F383C,
 790   PREFIX_0F383D,
 791   PREFIX_0F383E,
 792   PREFIX_0F383F,
 793   PREFIX_0F3840,
 794   PREFIX_0F3841,
 795   PREFIX_0F3880,
 796   PREFIX_0F3881,
 797   PREFIX_0F38DB,
 798   PREFIX_0F38DC,
 799   PREFIX_0F38DD,
 800   PREFIX_0F38DE,
 801   PREFIX_0F38DF,
 802   PREFIX_0F38F0,
 803   PREFIX_0F38F1,
 804   PREFIX_0F3A08,
 805   PREFIX_0F3A09,
 806   PREFIX_0F3A0A,
 807   PREFIX_0F3A0B,
 808   PREFIX_0F3A0C,
 809   PREFIX_0F3A0D,
 810   PREFIX_0F3A0E,
 811   PREFIX_0F3A14,
 812   PREFIX_0F3A15,
 813   PREFIX_0F3A16,
 814   PREFIX_0F3A17,
 815   PREFIX_0F3A20,
 816   PREFIX_0F3A21,
 817   PREFIX_0F3A22,
 818   PREFIX_0F3A40,
 819   PREFIX_0F3A41,
 820   PREFIX_0F3A42,
 821   PREFIX_0F3A44,
 822   PREFIX_0F3A60,
 823   PREFIX_0F3A61,
 824   PREFIX_0F3A62,
 825   PREFIX_0F3A63,
 826   PREFIX_0F3ADF,
 827   PREFIX_VEX_0F10,
 828   PREFIX_VEX_0F11,
 829   PREFIX_VEX_0F12,
 830   PREFIX_VEX_0F16,
 831   PREFIX_VEX_0F2A,
 832   PREFIX_VEX_0F2C,
 833   PREFIX_VEX_0F2D,
 834   PREFIX_VEX_0F2E,
 835   PREFIX_VEX_0F2F,
 836   PREFIX_VEX_0F51,
 837   PREFIX_VEX_0F52,
 838   PREFIX_VEX_0F53,
 839   PREFIX_VEX_0F58,
 840   PREFIX_VEX_0F59,
 841   PREFIX_VEX_0F5A,
 842   PREFIX_VEX_0F5B,
 843   PREFIX_VEX_0F5C,
 844   PREFIX_VEX_0F5D,
 845   PREFIX_VEX_0F5E,
 846   PREFIX_VEX_0F5F,
 847   PREFIX_VEX_0F60,
 848   PREFIX_VEX_0F61,
 849   PREFIX_VEX_0F62,
 850   PREFIX_VEX_0F63,
 851   PREFIX_VEX_0F64,
 852   PREFIX_VEX_0F65,
 853   PREFIX_VEX_0F66,
 854   PREFIX_VEX_0F67,
 855   PREFIX_VEX_0F68,
 856   PREFIX_VEX_0F69,
 857   PREFIX_VEX_0F6A,
 858   PREFIX_VEX_0F6B,
 859   PREFIX_VEX_0F6C,
 860   PREFIX_VEX_0F6D,
 861   PREFIX_VEX_0F6E,
 862   PREFIX_VEX_0F6F,
 863   PREFIX_VEX_0F70,
 864   PREFIX_VEX_0F71_REG_2,
 865   PREFIX_VEX_0F71_REG_4,
 866   PREFIX_VEX_0F71_REG_6,
 867   PREFIX_VEX_0F72_REG_2,
 868   PREFIX_VEX_0F72_REG_4,
 869   PREFIX_VEX_0F72_REG_6,
 870   PREFIX_VEX_0F73_REG_2,
 871   PREFIX_VEX_0F73_REG_3,
 872   PREFIX_VEX_0F73_REG_6,
 873   PREFIX_VEX_0F73_REG_7,
 874   PREFIX_VEX_0F74,
 875   PREFIX_VEX_0F75,
 876   PREFIX_VEX_0F76,
 877   PREFIX_VEX_0F77,
 878   PREFIX_VEX_0F7C,
 879   PREFIX_VEX_0F7D,
 880   PREFIX_VEX_0F7E,
 881   PREFIX_VEX_0F7F,
 882   PREFIX_VEX_0FC2,
 883   PREFIX_VEX_0FC4,
 884   PREFIX_VEX_0FC5,
 885   PREFIX_VEX_0FD0,
 886   PREFIX_VEX_0FD1,
 887   PREFIX_VEX_0FD2,
 888   PREFIX_VEX_0FD3,
 889   PREFIX_VEX_0FD4,
 890   PREFIX_VEX_0FD5,
 891   PREFIX_VEX_0FD6,
 892   PREFIX_VEX_0FD7,
 893   PREFIX_VEX_0FD8,
 894   PREFIX_VEX_0FD9,
 895   PREFIX_VEX_0FDA,
 896   PREFIX_VEX_0FDB,
 897   PREFIX_VEX_0FDC,
 898   PREFIX_VEX_0FDD,
 899   PREFIX_VEX_0FDE,
 900   PREFIX_VEX_0FDF,
 901   PREFIX_VEX_0FE0,
 902   PREFIX_VEX_0FE1,
 903   PREFIX_VEX_0FE2,
 904   PREFIX_VEX_0FE3,
 905   PREFIX_VEX_0FE4,
 906   PREFIX_VEX_0FE5,
 907   PREFIX_VEX_0FE6,
 908   PREFIX_VEX_0FE7,
 909   PREFIX_VEX_0FE8,
 910   PREFIX_VEX_0FE9,
 911   PREFIX_VEX_0FEA,
 912   PREFIX_VEX_0FEB,
 913   PREFIX_VEX_0FEC,
 914   PREFIX_VEX_0FED,
 915   PREFIX_VEX_0FEE,
 916   PREFIX_VEX_0FEF,
 917   PREFIX_VEX_0FF0,
 918   PREFIX_VEX_0FF1,
 919   PREFIX_VEX_0FF2,
 920   PREFIX_VEX_0FF3,
 921   PREFIX_VEX_0FF4,
 922   PREFIX_VEX_0FF5,
 923   PREFIX_VEX_0FF6,
 924   PREFIX_VEX_0FF7,
 925   PREFIX_VEX_0FF8,
 926   PREFIX_VEX_0FF9,
 927   PREFIX_VEX_0FFA,
 928   PREFIX_VEX_0FFB,
 929   PREFIX_VEX_0FFC,
 930   PREFIX_VEX_0FFD,
 931   PREFIX_VEX_0FFE,
 932   PREFIX_VEX_0F3800,
 933   PREFIX_VEX_0F3801,
 934   PREFIX_VEX_0F3802,
 935   PREFIX_VEX_0F3803,
 936   PREFIX_VEX_0F3804,
 937   PREFIX_VEX_0F3805,
 938   PREFIX_VEX_0F3806,
 939   PREFIX_VEX_0F3807,
 940   PREFIX_VEX_0F3808,
 941   PREFIX_VEX_0F3809,
 942   PREFIX_VEX_0F380A,
 943   PREFIX_VEX_0F380B,
 944   PREFIX_VEX_0F380C,
 945   PREFIX_VEX_0F380D,
 946   PREFIX_VEX_0F380E,
 947   PREFIX_VEX_0F380F,
 948   PREFIX_VEX_0F3813,
 949   PREFIX_VEX_0F3817,
 950   PREFIX_VEX_0F3818,
 951   PREFIX_VEX_0F3819,
 952   PREFIX_VEX_0F381A,
 953   PREFIX_VEX_0F381C,
 954   PREFIX_VEX_0F381D,
 955   PREFIX_VEX_0F381E,
 956   PREFIX_VEX_0F3820,
 957   PREFIX_VEX_0F3821,
 958   PREFIX_VEX_0F3822,
 959   PREFIX_VEX_0F3823,
 960   PREFIX_VEX_0F3824,
 961   PREFIX_VEX_0F3825,
 962   PREFIX_VEX_0F3828,
 963   PREFIX_VEX_0F3829,
 964   PREFIX_VEX_0F382A,
 965   PREFIX_VEX_0F382B,
 966   PREFIX_VEX_0F382C,
 967   PREFIX_VEX_0F382D,
 968   PREFIX_VEX_0F382E,
 969   PREFIX_VEX_0F382F,
 970   PREFIX_VEX_0F3830,
 971   PREFIX_VEX_0F3831,
 972   PREFIX_VEX_0F3832,
 973   PREFIX_VEX_0F3833,
 974   PREFIX_VEX_0F3834,
 975   PREFIX_VEX_0F3835,
 976   PREFIX_VEX_0F3837,
 977   PREFIX_VEX_0F3838,
 978   PREFIX_VEX_0F3839,
 979   PREFIX_VEX_0F383A,
 980   PREFIX_VEX_0F383B,
 981   PREFIX_VEX_0F383C,
 982   PREFIX_VEX_0F383D,
 983   PREFIX_VEX_0F383E,
 984   PREFIX_VEX_0F383F,
 985   PREFIX_VEX_0F3840,
 986   PREFIX_VEX_0F3841,
 987   PREFIX_VEX_0F3896,
 988   PREFIX_VEX_0F3897,
 989   PREFIX_VEX_0F3898,
 990   PREFIX_VEX_0F3899,
 991   PREFIX_VEX_0F389A,
 992   PREFIX_VEX_0F389B,
 993   PREFIX_VEX_0F389C,
 994   PREFIX_VEX_0F389D,
 995   PREFIX_VEX_0F389E,
 996   PREFIX_VEX_0F389F,
 997   PREFIX_VEX_0F38A6,
 998   PREFIX_VEX_0F38A7,
 999   PREFIX_VEX_0F38A8,
1000   PREFIX_VEX_0F38A9,
1001   PREFIX_VEX_0F38AA,
1002   PREFIX_VEX_0F38AB,
1003   PREFIX_VEX_0F38AC,
1004   PREFIX_VEX_0F38AD,
1005   PREFIX_VEX_0F38AE,
1006   PREFIX_VEX_0F38AF,
1007   PREFIX_VEX_0F38B6,
1008   PREFIX_VEX_0F38B7,
1009   PREFIX_VEX_0F38B8,
1010   PREFIX_VEX_0F38B9,
1011   PREFIX_VEX_0F38BA,
1012   PREFIX_VEX_0F38BB,
1013   PREFIX_VEX_0F38BC,
1014   PREFIX_VEX_0F38BD,
1015   PREFIX_VEX_0F38BE,
1016   PREFIX_VEX_0F38BF,
1017   PREFIX_VEX_0F38DB,
1018   PREFIX_VEX_0F38DC,
1019   PREFIX_VEX_0F38DD,
1020   PREFIX_VEX_0F38DE,
1021   PREFIX_VEX_0F38DF,
1022   PREFIX_VEX_0F38F2,
1023   PREFIX_VEX_0F38F3_REG_1,
1024   PREFIX_VEX_0F38F3_REG_2,
1025   PREFIX_VEX_0F38F3_REG_3,
1026   PREFIX_VEX_0F38F7,
1027   PREFIX_VEX_0F3A04,
1028   PREFIX_VEX_0F3A05,
1029   PREFIX_VEX_0F3A06,
1030   PREFIX_VEX_0F3A08,
1031   PREFIX_VEX_0F3A09,
1032   PREFIX_VEX_0F3A0A,
1033   PREFIX_VEX_0F3A0B,
1034   PREFIX_VEX_0F3A0C,
1035   PREFIX_VEX_0F3A0D,
1036   PREFIX_VEX_0F3A0E,
1037   PREFIX_VEX_0F3A0F,
1038   PREFIX_VEX_0F3A14,
1039   PREFIX_VEX_0F3A15,
1040   PREFIX_VEX_0F3A16,
1041   PREFIX_VEX_0F3A17,
1042   PREFIX_VEX_0F3A18,
1043   PREFIX_VEX_0F3A19,
1044   PREFIX_VEX_0F3A1D,
1045   PREFIX_VEX_0F3A20,
1046   PREFIX_VEX_0F3A21,
1047   PREFIX_VEX_0F3A22,
1048   PREFIX_VEX_0F3A40,
1049   PREFIX_VEX_0F3A41,
1050   PREFIX_VEX_0F3A42,
1051   PREFIX_VEX_0F3A44,
1052   PREFIX_VEX_0F3A48,
1053   PREFIX_VEX_0F3A49,
1054   PREFIX_VEX_0F3A4A,
1055   PREFIX_VEX_0F3A4B,
1056   PREFIX_VEX_0F3A4C,
1057   PREFIX_VEX_0F3A5C,
1058   PREFIX_VEX_0F3A5D,
1059   PREFIX_VEX_0F3A5E,
1060   PREFIX_VEX_0F3A5F,
1061   PREFIX_VEX_0F3A60,
1062   PREFIX_VEX_0F3A61,
1063   PREFIX_VEX_0F3A62,
1064   PREFIX_VEX_0F3A63,
1065   PREFIX_VEX_0F3A68,
1066   PREFIX_VEX_0F3A69,
1067   PREFIX_VEX_0F3A6A,
1068   PREFIX_VEX_0F3A6B,
1069   PREFIX_VEX_0F3A6C,
1070   PREFIX_VEX_0F3A6D,
1071   PREFIX_VEX_0F3A6E,
1072   PREFIX_VEX_0F3A6F,
1073   PREFIX_VEX_0F3A78,
1074   PREFIX_VEX_0F3A79,
1075   PREFIX_VEX_0F3A7A,
1076   PREFIX_VEX_0F3A7B,
1077   PREFIX_VEX_0F3A7C,
1078   PREFIX_VEX_0F3A7D,
1079   PREFIX_VEX_0F3A7E,
1080   PREFIX_VEX_0F3A7F,
1081   PREFIX_VEX_0F3ADF
1082 };
1083
1084 enum
1085 {
1086   X86_64_06 = 0,
1087   X86_64_07,
1088   X86_64_0D,
1089   X86_64_16,
1090   X86_64_17,
1091   X86_64_1E,
1092   X86_64_1F,
1093   X86_64_27,
1094   X86_64_2F,
1095   X86_64_37,
1096   X86_64_3F,
1097   X86_64_60,
1098   X86_64_61,
1099   X86_64_62,
1100   X86_64_63,
1101   X86_64_6D,
1102   X86_64_6F,
1103   X86_64_9A,
1104   X86_64_C4,
1105   X86_64_C5,
1106   X86_64_CE,
1107   X86_64_D4,
1108   X86_64_D5,
1109   X86_64_EA,
1110   X86_64_0F01_REG_0,
1111   X86_64_0F01_REG_1,
1112   X86_64_0F01_REG_2,
1113   X86_64_0F01_REG_3
1114 };
1115
1116 enum
1117 {
1118   THREE_BYTE_0F38 = 0,
1119   THREE_BYTE_0F3A,
1120   THREE_BYTE_0F7A
1121 };
1122
1123 enum
1124 {
1125   XOP_08 = 0,
1126   XOP_09,
1127   XOP_0A
1128 };
1129
1130 enum
1131 {
1132   VEX_0F = 0,
1133   VEX_0F38,
1134   VEX_0F3A
1135 };
1136
1137 enum
1138 {
1139   VEX_LEN_0F10_P_1 = 0,
1140   VEX_LEN_0F10_P_3,
1141   VEX_LEN_0F11_P_1,
1142   VEX_LEN_0F11_P_3,
1143   VEX_LEN_0F12_P_0_M_0,
1144   VEX_LEN_0F12_P_0_M_1,
1145   VEX_LEN_0F12_P_2,
1146   VEX_LEN_0F13_M_0,
1147   VEX_LEN_0F16_P_0_M_0,
1148   VEX_LEN_0F16_P_0_M_1,
1149   VEX_LEN_0F16_P_2,
1150   VEX_LEN_0F17_M_0,
1151   VEX_LEN_0F2A_P_1,
1152   VEX_LEN_0F2A_P_3,
1153   VEX_LEN_0F2C_P_1,
1154   VEX_LEN_0F2C_P_3,
1155   VEX_LEN_0F2D_P_1,
1156   VEX_LEN_0F2D_P_3,
1157   VEX_LEN_0F2E_P_0,
1158   VEX_LEN_0F2E_P_2,
1159   VEX_LEN_0F2F_P_0,
1160   VEX_LEN_0F2F_P_2,
1161   VEX_LEN_0F51_P_1,
1162   VEX_LEN_0F51_P_3,
1163   VEX_LEN_0F52_P_1,
1164   VEX_LEN_0F53_P_1,
1165   VEX_LEN_0F58_P_1,
1166   VEX_LEN_0F58_P_3,
1167   VEX_LEN_0F59_P_1,
1168   VEX_LEN_0F59_P_3,
1169   VEX_LEN_0F5A_P_1,
1170   VEX_LEN_0F5A_P_3,
1171   VEX_LEN_0F5C_P_1,
1172   VEX_LEN_0F5C_P_3,
1173   VEX_LEN_0F5D_P_1,
1174   VEX_LEN_0F5D_P_3,
1175   VEX_LEN_0F5E_P_1,
1176   VEX_LEN_0F5E_P_3,
1177   VEX_LEN_0F5F_P_1,
1178   VEX_LEN_0F5F_P_3,
1179   VEX_LEN_0F60_P_2,
1180   VEX_LEN_0F61_P_2,
1181   VEX_LEN_0F62_P_2,
1182   VEX_LEN_0F63_P_2,
1183   VEX_LEN_0F64_P_2,
1184   VEX_LEN_0F65_P_2,
1185   VEX_LEN_0F66_P_2,
1186   VEX_LEN_0F67_P_2,
1187   VEX_LEN_0F68_P_2,
1188   VEX_LEN_0F69_P_2,
1189   VEX_LEN_0F6A_P_2,
1190   VEX_LEN_0F6B_P_2,
1191   VEX_LEN_0F6C_P_2,
1192   VEX_LEN_0F6D_P_2,
1193   VEX_LEN_0F6E_P_2,
1194   VEX_LEN_0F70_P_1,
1195   VEX_LEN_0F70_P_2,
1196   VEX_LEN_0F70_P_3,
1197   VEX_LEN_0F71_R_2_P_2,
1198   VEX_LEN_0F71_R_4_P_2,
1199   VEX_LEN_0F71_R_6_P_2,
1200   VEX_LEN_0F72_R_2_P_2,
1201   VEX_LEN_0F72_R_4_P_2,
1202   VEX_LEN_0F72_R_6_P_2,
1203   VEX_LEN_0F73_R_2_P_2,
1204   VEX_LEN_0F73_R_3_P_2,
1205   VEX_LEN_0F73_R_6_P_2,
1206   VEX_LEN_0F73_R_7_P_2,
1207   VEX_LEN_0F74_P_2,
1208   VEX_LEN_0F75_P_2,
1209   VEX_LEN_0F76_P_2,
1210   VEX_LEN_0F7E_P_1,
1211   VEX_LEN_0F7E_P_2,
1212   VEX_LEN_0FAE_R_2_M_0,
1213   VEX_LEN_0FAE_R_3_M_0,
1214   VEX_LEN_0FC2_P_1,
1215   VEX_LEN_0FC2_P_3,
1216   VEX_LEN_0FC4_P_2,
1217   VEX_LEN_0FC5_P_2,
1218   VEX_LEN_0FD1_P_2,
1219   VEX_LEN_0FD2_P_2,
1220   VEX_LEN_0FD3_P_2,
1221   VEX_LEN_0FD4_P_2,
1222   VEX_LEN_0FD5_P_2,
1223   VEX_LEN_0FD6_P_2,
1224   VEX_LEN_0FD7_P_2_M_1,
1225   VEX_LEN_0FD8_P_2,
1226   VEX_LEN_0FD9_P_2,
1227   VEX_LEN_0FDA_P_2,
1228   VEX_LEN_0FDB_P_2,
1229   VEX_LEN_0FDC_P_2,
1230   VEX_LEN_0FDD_P_2,
1231   VEX_LEN_0FDE_P_2,
1232   VEX_LEN_0FDF_P_2,
1233   VEX_LEN_0FE0_P_2,
1234   VEX_LEN_0FE1_P_2,
1235   VEX_LEN_0FE2_P_2,
1236   VEX_LEN_0FE3_P_2,
1237   VEX_LEN_0FE4_P_2,
1238   VEX_LEN_0FE5_P_2,
1239   VEX_LEN_0FE8_P_2,
1240   VEX_LEN_0FE9_P_2,
1241   VEX_LEN_0FEA_P_2,
1242   VEX_LEN_0FEB_P_2,
1243   VEX_LEN_0FEC_P_2,
1244   VEX_LEN_0FED_P_2,
1245   VEX_LEN_0FEE_P_2,
1246   VEX_LEN_0FEF_P_2,
1247   VEX_LEN_0FF1_P_2,
1248   VEX_LEN_0FF2_P_2,
1249   VEX_LEN_0FF3_P_2,
1250   VEX_LEN_0FF4_P_2,
1251   VEX_LEN_0FF5_P_2,
1252   VEX_LEN_0FF6_P_2,
1253   VEX_LEN_0FF7_P_2,
1254   VEX_LEN_0FF8_P_2,
1255   VEX_LEN_0FF9_P_2,
1256   VEX_LEN_0FFA_P_2,
1257   VEX_LEN_0FFB_P_2,
1258   VEX_LEN_0FFC_P_2,
1259   VEX_LEN_0FFD_P_2,
1260   VEX_LEN_0FFE_P_2,
1261   VEX_LEN_0F3800_P_2,
1262   VEX_LEN_0F3801_P_2,
1263   VEX_LEN_0F3802_P_2,
1264   VEX_LEN_0F3803_P_2,
1265   VEX_LEN_0F3804_P_2,
1266   VEX_LEN_0F3805_P_2,
1267   VEX_LEN_0F3806_P_2,
1268   VEX_LEN_0F3807_P_2,
1269   VEX_LEN_0F3808_P_2,
1270   VEX_LEN_0F3809_P_2,
1271   VEX_LEN_0F380A_P_2,
1272   VEX_LEN_0F380B_P_2,
1273   VEX_LEN_0F3819_P_2_M_0,
1274   VEX_LEN_0F381A_P_2_M_0,
1275   VEX_LEN_0F381C_P_2,
1276   VEX_LEN_0F381D_P_2,
1277   VEX_LEN_0F381E_P_2,
1278   VEX_LEN_0F3820_P_2,
1279   VEX_LEN_0F3821_P_2,
1280   VEX_LEN_0F3822_P_2,
1281   VEX_LEN_0F3823_P_2,
1282   VEX_LEN_0F3824_P_2,
1283   VEX_LEN_0F3825_P_2,
1284   VEX_LEN_0F3828_P_2,
1285   VEX_LEN_0F3829_P_2,
1286   VEX_LEN_0F382A_P_2_M_0,
1287   VEX_LEN_0F382B_P_2,
1288   VEX_LEN_0F3830_P_2,
1289   VEX_LEN_0F3831_P_2,
1290   VEX_LEN_0F3832_P_2,
1291   VEX_LEN_0F3833_P_2,
1292   VEX_LEN_0F3834_P_2,
1293   VEX_LEN_0F3835_P_2,
1294   VEX_LEN_0F3837_P_2,
1295   VEX_LEN_0F3838_P_2,
1296   VEX_LEN_0F3839_P_2,
1297   VEX_LEN_0F383A_P_2,
1298   VEX_LEN_0F383B_P_2,
1299   VEX_LEN_0F383C_P_2,
1300   VEX_LEN_0F383D_P_2,
1301   VEX_LEN_0F383E_P_2,
1302   VEX_LEN_0F383F_P_2,
1303   VEX_LEN_0F3840_P_2,
1304   VEX_LEN_0F3841_P_2,
1305   VEX_LEN_0F38DB_P_2,
1306   VEX_LEN_0F38DC_P_2,
1307   VEX_LEN_0F38DD_P_2,
1308   VEX_LEN_0F38DE_P_2,
1309   VEX_LEN_0F38DF_P_2,
1310   VEX_LEN_0F38F2_P_0,
1311   VEX_LEN_0F38F3_R_1_P_0,
1312   VEX_LEN_0F38F3_R_2_P_0,
1313   VEX_LEN_0F38F3_R_3_P_0,
1314   VEX_LEN_0F38F7_P_0,
1315   VEX_LEN_0F3A06_P_2,
1316   VEX_LEN_0F3A0A_P_2,
1317   VEX_LEN_0F3A0B_P_2,
1318   VEX_LEN_0F3A0E_P_2,
1319   VEX_LEN_0F3A0F_P_2,
1320   VEX_LEN_0F3A14_P_2,
1321   VEX_LEN_0F3A15_P_2,
1322   VEX_LEN_0F3A16_P_2,
1323   VEX_LEN_0F3A17_P_2,
1324   VEX_LEN_0F3A18_P_2,
1325   VEX_LEN_0F3A19_P_2,
1326   VEX_LEN_0F3A20_P_2,
1327   VEX_LEN_0F3A21_P_2,
1328   VEX_LEN_0F3A22_P_2,
1329   VEX_LEN_0F3A41_P_2,
1330   VEX_LEN_0F3A42_P_2,
1331   VEX_LEN_0F3A44_P_2,
1332   VEX_LEN_0F3A4C_P_2,
1333   VEX_LEN_0F3A60_P_2,
1334   VEX_LEN_0F3A61_P_2,
1335   VEX_LEN_0F3A62_P_2,
1336   VEX_LEN_0F3A63_P_2,
1337   VEX_LEN_0F3A6A_P_2,
1338   VEX_LEN_0F3A6B_P_2,
1339   VEX_LEN_0F3A6E_P_2,
1340   VEX_LEN_0F3A6F_P_2,
1341   VEX_LEN_0F3A7A_P_2,
1342   VEX_LEN_0F3A7B_P_2,
1343   VEX_LEN_0F3A7E_P_2,
1344   VEX_LEN_0F3A7F_P_2,
1345   VEX_LEN_0F3ADF_P_2,
1346   VEX_LEN_0FXOP_09_80,
1347   VEX_LEN_0FXOP_09_81
1348 };
1349
1350 enum
1351 {
1352   VEX_W_0F10_P_0 = 0,
1353   VEX_W_0F10_P_1,
1354   VEX_W_0F10_P_2,
1355   VEX_W_0F10_P_3,
1356   VEX_W_0F11_P_0,
1357   VEX_W_0F11_P_1,
1358   VEX_W_0F11_P_2,
1359   VEX_W_0F11_P_3,
1360   VEX_W_0F12_P_0_M_0,
1361   VEX_W_0F12_P_0_M_1,
1362   VEX_W_0F12_P_1,
1363   VEX_W_0F12_P_2,
1364   VEX_W_0F12_P_3,
1365   VEX_W_0F13_M_0,
1366   VEX_W_0F14,
1367   VEX_W_0F15,
1368   VEX_W_0F16_P_0_M_0,
1369   VEX_W_0F16_P_0_M_1,
1370   VEX_W_0F16_P_1,
1371   VEX_W_0F16_P_2,
1372   VEX_W_0F17_M_0,
1373   VEX_W_0F28,
1374   VEX_W_0F29,
1375   VEX_W_0F2B_M_0,
1376   VEX_W_0F2E_P_0,
1377   VEX_W_0F2E_P_2,
1378   VEX_W_0F2F_P_0,
1379   VEX_W_0F2F_P_2,
1380   VEX_W_0F50_M_0,
1381   VEX_W_0F51_P_0,
1382   VEX_W_0F51_P_1,
1383   VEX_W_0F51_P_2,
1384   VEX_W_0F51_P_3,
1385   VEX_W_0F52_P_0,
1386   VEX_W_0F52_P_1,
1387   VEX_W_0F53_P_0,
1388   VEX_W_0F53_P_1,
1389   VEX_W_0F58_P_0,
1390   VEX_W_0F58_P_1,
1391   VEX_W_0F58_P_2,
1392   VEX_W_0F58_P_3,
1393   VEX_W_0F59_P_0,
1394   VEX_W_0F59_P_1,
1395   VEX_W_0F59_P_2,
1396   VEX_W_0F59_P_3,
1397   VEX_W_0F5A_P_0,
1398   VEX_W_0F5A_P_1,
1399   VEX_W_0F5A_P_3,
1400   VEX_W_0F5B_P_0,
1401   VEX_W_0F5B_P_1,
1402   VEX_W_0F5B_P_2,
1403   VEX_W_0F5C_P_0,
1404   VEX_W_0F5C_P_1,
1405   VEX_W_0F5C_P_2,
1406   VEX_W_0F5C_P_3,
1407   VEX_W_0F5D_P_0,
1408   VEX_W_0F5D_P_1,
1409   VEX_W_0F5D_P_2,
1410   VEX_W_0F5D_P_3,
1411   VEX_W_0F5E_P_0,
1412   VEX_W_0F5E_P_1,
1413   VEX_W_0F5E_P_2,
1414   VEX_W_0F5E_P_3,
1415   VEX_W_0F5F_P_0,
1416   VEX_W_0F5F_P_1,
1417   VEX_W_0F5F_P_2,
1418   VEX_W_0F5F_P_3,
1419   VEX_W_0F60_P_2,
1420   VEX_W_0F61_P_2,
1421   VEX_W_0F62_P_2,
1422   VEX_W_0F63_P_2,
1423   VEX_W_0F64_P_2,
1424   VEX_W_0F65_P_2,
1425   VEX_W_0F66_P_2,
1426   VEX_W_0F67_P_2,
1427   VEX_W_0F68_P_2,
1428   VEX_W_0F69_P_2,
1429   VEX_W_0F6A_P_2,
1430   VEX_W_0F6B_P_2,
1431   VEX_W_0F6C_P_2,
1432   VEX_W_0F6D_P_2,
1433   VEX_W_0F6F_P_1,
1434   VEX_W_0F6F_P_2,
1435   VEX_W_0F70_P_1,
1436   VEX_W_0F70_P_2,
1437   VEX_W_0F70_P_3,
1438   VEX_W_0F71_R_2_P_2,
1439   VEX_W_0F71_R_4_P_2,
1440   VEX_W_0F71_R_6_P_2,
1441   VEX_W_0F72_R_2_P_2,
1442   VEX_W_0F72_R_4_P_2,
1443   VEX_W_0F72_R_6_P_2,
1444   VEX_W_0F73_R_2_P_2,
1445   VEX_W_0F73_R_3_P_2,
1446   VEX_W_0F73_R_6_P_2,
1447   VEX_W_0F73_R_7_P_2,
1448   VEX_W_0F74_P_2,
1449   VEX_W_0F75_P_2,
1450   VEX_W_0F76_P_2,
1451   VEX_W_0F77_P_0,
1452   VEX_W_0F7C_P_2,
1453   VEX_W_0F7C_P_3,
1454   VEX_W_0F7D_P_2,
1455   VEX_W_0F7D_P_3,
1456   VEX_W_0F7E_P_1,
1457   VEX_W_0F7F_P_1,
1458   VEX_W_0F7F_P_2,
1459   VEX_W_0FAE_R_2_M_0,
1460   VEX_W_0FAE_R_3_M_0,
1461   VEX_W_0FC2_P_0,
1462   VEX_W_0FC2_P_1,
1463   VEX_W_0FC2_P_2,
1464   VEX_W_0FC2_P_3,
1465   VEX_W_0FC4_P_2,
1466   VEX_W_0FC5_P_2,
1467   VEX_W_0FD0_P_2,
1468   VEX_W_0FD0_P_3,
1469   VEX_W_0FD1_P_2,
1470   VEX_W_0FD2_P_2,
1471   VEX_W_0FD3_P_2,
1472   VEX_W_0FD4_P_2,
1473   VEX_W_0FD5_P_2,
1474   VEX_W_0FD6_P_2,
1475   VEX_W_0FD7_P_2_M_1,
1476   VEX_W_0FD8_P_2,
1477   VEX_W_0FD9_P_2,
1478   VEX_W_0FDA_P_2,
1479   VEX_W_0FDB_P_2,
1480   VEX_W_0FDC_P_2,
1481   VEX_W_0FDD_P_2,
1482   VEX_W_0FDE_P_2,
1483   VEX_W_0FDF_P_2,
1484   VEX_W_0FE0_P_2,
1485   VEX_W_0FE1_P_2,
1486   VEX_W_0FE2_P_2,
1487   VEX_W_0FE3_P_2,
1488   VEX_W_0FE4_P_2,
1489   VEX_W_0FE5_P_2,
1490   VEX_W_0FE6_P_1,
1491   VEX_W_0FE6_P_2,
1492   VEX_W_0FE6_P_3,
1493   VEX_W_0FE7_P_2_M_0,
1494   VEX_W_0FE8_P_2,
1495   VEX_W_0FE9_P_2,
1496   VEX_W_0FEA_P_2,
1497   VEX_W_0FEB_P_2,
1498   VEX_W_0FEC_P_2,
1499   VEX_W_0FED_P_2,
1500   VEX_W_0FEE_P_2,
1501   VEX_W_0FEF_P_2,
1502   VEX_W_0FF0_P_3_M_0,
1503   VEX_W_0FF1_P_2,
1504   VEX_W_0FF2_P_2,
1505   VEX_W_0FF3_P_2,
1506   VEX_W_0FF4_P_2,
1507   VEX_W_0FF5_P_2,
1508   VEX_W_0FF6_P_2,
1509   VEX_W_0FF7_P_2,
1510   VEX_W_0FF8_P_2,
1511   VEX_W_0FF9_P_2,
1512   VEX_W_0FFA_P_2,
1513   VEX_W_0FFB_P_2,
1514   VEX_W_0FFC_P_2,
1515   VEX_W_0FFD_P_2,
1516   VEX_W_0FFE_P_2,
1517   VEX_W_0F3800_P_2,
1518   VEX_W_0F3801_P_2,
1519   VEX_W_0F3802_P_2,
1520   VEX_W_0F3803_P_2,
1521   VEX_W_0F3804_P_2,
1522   VEX_W_0F3805_P_2,
1523   VEX_W_0F3806_P_2,
1524   VEX_W_0F3807_P_2,
1525   VEX_W_0F3808_P_2,
1526   VEX_W_0F3809_P_2,
1527   VEX_W_0F380A_P_2,
1528   VEX_W_0F380B_P_2,
1529   VEX_W_0F380C_P_2,
1530   VEX_W_0F380D_P_2,
1531   VEX_W_0F380E_P_2,
1532   VEX_W_0F380F_P_2,
1533   VEX_W_0F3817_P_2,
1534   VEX_W_0F3818_P_2_M_0,
1535   VEX_W_0F3819_P_2_M_0,
1536   VEX_W_0F381A_P_2_M_0,
1537   VEX_W_0F381C_P_2,
1538   VEX_W_0F381D_P_2,
1539   VEX_W_0F381E_P_2,
1540   VEX_W_0F3820_P_2,
1541   VEX_W_0F3821_P_2,
1542   VEX_W_0F3822_P_2,
1543   VEX_W_0F3823_P_2,
1544   VEX_W_0F3824_P_2,
1545   VEX_W_0F3825_P_2,
1546   VEX_W_0F3828_P_2,
1547   VEX_W_0F3829_P_2,
1548   VEX_W_0F382A_P_2_M_0,
1549   VEX_W_0F382B_P_2,
1550   VEX_W_0F382C_P_2_M_0,
1551   VEX_W_0F382D_P_2_M_0,
1552   VEX_W_0F382E_P_2_M_0,
1553   VEX_W_0F382F_P_2_M_0,
1554   VEX_W_0F3830_P_2,
1555   VEX_W_0F3831_P_2,
1556   VEX_W_0F3832_P_2,
1557   VEX_W_0F3833_P_2,
1558   VEX_W_0F3834_P_2,
1559   VEX_W_0F3835_P_2,
1560   VEX_W_0F3837_P_2,
1561   VEX_W_0F3838_P_2,
1562   VEX_W_0F3839_P_2,
1563   VEX_W_0F383A_P_2,
1564   VEX_W_0F383B_P_2,
1565   VEX_W_0F383C_P_2,
1566   VEX_W_0F383D_P_2,
1567   VEX_W_0F383E_P_2,
1568   VEX_W_0F383F_P_2,
1569   VEX_W_0F3840_P_2,
1570   VEX_W_0F3841_P_2,
1571   VEX_W_0F38DB_P_2,
1572   VEX_W_0F38DC_P_2,
1573   VEX_W_0F38DD_P_2,
1574   VEX_W_0F38DE_P_2,
1575   VEX_W_0F38DF_P_2,
1576   VEX_W_0F3A04_P_2,
1577   VEX_W_0F3A05_P_2,
1578   VEX_W_0F3A06_P_2,
1579   VEX_W_0F3A08_P_2,
1580   VEX_W_0F3A09_P_2,
1581   VEX_W_0F3A0A_P_2,
1582   VEX_W_0F3A0B_P_2,
1583   VEX_W_0F3A0C_P_2,
1584   VEX_W_0F3A0D_P_2,
1585   VEX_W_0F3A0E_P_2,
1586   VEX_W_0F3A0F_P_2,
1587   VEX_W_0F3A14_P_2,
1588   VEX_W_0F3A15_P_2,
1589   VEX_W_0F3A18_P_2,
1590   VEX_W_0F3A19_P_2,
1591   VEX_W_0F3A20_P_2,
1592   VEX_W_0F3A21_P_2,
1593   VEX_W_0F3A40_P_2,
1594   VEX_W_0F3A41_P_2,
1595   VEX_W_0F3A42_P_2,
1596   VEX_W_0F3A44_P_2,
1597   VEX_W_0F3A48_P_2,
1598   VEX_W_0F3A49_P_2,
1599   VEX_W_0F3A4A_P_2,
1600   VEX_W_0F3A4B_P_2,
1601   VEX_W_0F3A4C_P_2,
1602   VEX_W_0F3A60_P_2,
1603   VEX_W_0F3A61_P_2,
1604   VEX_W_0F3A62_P_2,
1605   VEX_W_0F3A63_P_2,
1606   VEX_W_0F3ADF_P_2
1607 };
1608
1609 typedef void (*op_rtn) (int bytemode, int sizeflag);
1610
1611 struct dis386 {
1612   const char *name;
1613   struct
1614     {
1615       op_rtn rtn;
1616       int bytemode;
1617     } op[MAX_OPERANDS];
1618 };
1619
1620 /* Upper case letters in the instruction names here are macros.
1621    'A' => print 'b' if no register operands or suffix_always is true
1622    'B' => print 'b' if suffix_always is true
1623    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1624           size prefix
1625    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1626           suffix_always is true
1627    'E' => print 'e' if 32-bit form of jcxz
1628    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1629    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1630    'H' => print ",pt" or ",pn" branch hint
1631    'I' => honor following macro letter even in Intel mode (implemented only
1632           for some of the macro letters)
1633    'J' => print 'l'
1634    'K' => print 'd' or 'q' if rex prefix is present.
1635    'L' => print 'l' if suffix_always is true
1636    'M' => print 'r' if intel_mnemonic is false.
1637    'N' => print 'n' if instruction has no wait "prefix"
1638    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1639    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1640           or suffix_always is true.  print 'q' if rex prefix is present.
1641    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1642           is true
1643    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1644    'S' => print 'w', 'l' or 'q' if suffix_always is true
1645    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1646    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1647    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1648    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1649    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1650    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1651           suffix_always is true.
1652    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1653    '!' => change condition from true to false or from false to true.
1654    '%' => add 1 upper case letter to the macro.
1655
1656    2 upper case letter macros:
1657    "XY" => print 'x' or 'y' if no register operands or suffix_always
1658            is true.
1659    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1660    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1661            or suffix_always is true
1662    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1663    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1664    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1665
1666    Many of the above letters print nothing in Intel mode.  See "putop"
1667    for the details.
1668
1669    Braces '{' and '}', and vertical bars '|', indicate alternative
1670    mnemonic strings for AT&T and Intel.  */
1671
1672 static const struct dis386 dis386[] = {
1673   /* 00 */
1674   { "addB",             { Eb, Gb } },
1675   { "addS",             { Ev, Gv } },
1676   { "addB",             { Gb, EbS } },
1677   { "addS",             { Gv, EvS } },
1678   { "addB",             { AL, Ib } },
1679   { "addS",             { eAX, Iv } },
1680   { X86_64_TABLE (X86_64_06) },
1681   { X86_64_TABLE (X86_64_07) },
1682   /* 08 */
1683   { "orB",              { Eb, Gb } },
1684   { "orS",              { Ev, Gv } },
1685   { "orB",              { Gb, EbS } },
1686   { "orS",              { Gv, EvS } },
1687   { "orB",              { AL, Ib } },
1688   { "orS",              { eAX, Iv } },
1689   { X86_64_TABLE (X86_64_0D) },
1690   { Bad_Opcode },       /* 0x0f extended opcode escape */
1691   /* 10 */
1692   { "adcB",             { Eb, Gb } },
1693   { "adcS",             { Ev, Gv } },
1694   { "adcB",             { Gb, EbS } },
1695   { "adcS",             { Gv, EvS } },
1696   { "adcB",             { AL, Ib } },
1697   { "adcS",             { eAX, Iv } },
1698   { X86_64_TABLE (X86_64_16) },
1699   { X86_64_TABLE (X86_64_17) },
1700   /* 18 */
1701   { "sbbB",             { Eb, Gb } },
1702   { "sbbS",             { Ev, Gv } },
1703   { "sbbB",             { Gb, EbS } },
1704   { "sbbS",             { Gv, EvS } },
1705   { "sbbB",             { AL, Ib } },
1706   { "sbbS",             { eAX, Iv } },
1707   { X86_64_TABLE (X86_64_1E) },
1708   { X86_64_TABLE (X86_64_1F) },
1709   /* 20 */
1710   { "andB",             { Eb, Gb } },
1711   { "andS",             { Ev, Gv } },
1712   { "andB",             { Gb, EbS } },
1713   { "andS",             { Gv, EvS } },
1714   { "andB",             { AL, Ib } },
1715   { "andS",             { eAX, Iv } },
1716   { Bad_Opcode },       /* SEG ES prefix */
1717   { X86_64_TABLE (X86_64_27) },
1718   /* 28 */
1719   { "subB",             { Eb, Gb } },
1720   { "subS",             { Ev, Gv } },
1721   { "subB",             { Gb, EbS } },
1722   { "subS",             { Gv, EvS } },
1723   { "subB",             { AL, Ib } },
1724   { "subS",             { eAX, Iv } },
1725   { Bad_Opcode },       /* SEG CS prefix */
1726   { X86_64_TABLE (X86_64_2F) },
1727   /* 30 */
1728   { "xorB",             { Eb, Gb } },
1729   { "xorS",             { Ev, Gv } },
1730   { "xorB",             { Gb, EbS } },
1731   { "xorS",             { Gv, EvS } },
1732   { "xorB",             { AL, Ib } },
1733   { "xorS",             { eAX, Iv } },
1734   { Bad_Opcode },       /* SEG SS prefix */
1735   { X86_64_TABLE (X86_64_37) },
1736   /* 38 */
1737   { "cmpB",             { Eb, Gb } },
1738   { "cmpS",             { Ev, Gv } },
1739   { "cmpB",             { Gb, EbS } },
1740   { "cmpS",             { Gv, EvS } },
1741   { "cmpB",             { AL, Ib } },
1742   { "cmpS",             { eAX, Iv } },
1743   { Bad_Opcode },       /* SEG DS prefix */
1744   { X86_64_TABLE (X86_64_3F) },
1745   /* 40 */
1746   { "inc{S|}",          { RMeAX } },
1747   { "inc{S|}",          { RMeCX } },
1748   { "inc{S|}",          { RMeDX } },
1749   { "inc{S|}",          { RMeBX } },
1750   { "inc{S|}",          { RMeSP } },
1751   { "inc{S|}",          { RMeBP } },
1752   { "inc{S|}",          { RMeSI } },
1753   { "inc{S|}",          { RMeDI } },
1754   /* 48 */
1755   { "dec{S|}",          { RMeAX } },
1756   { "dec{S|}",          { RMeCX } },
1757   { "dec{S|}",          { RMeDX } },
1758   { "dec{S|}",          { RMeBX } },
1759   { "dec{S|}",          { RMeSP } },
1760   { "dec{S|}",          { RMeBP } },
1761   { "dec{S|}",          { RMeSI } },
1762   { "dec{S|}",          { RMeDI } },
1763   /* 50 */
1764   { "pushV",            { RMrAX } },
1765   { "pushV",            { RMrCX } },
1766   { "pushV",            { RMrDX } },
1767   { "pushV",            { RMrBX } },
1768   { "pushV",            { RMrSP } },
1769   { "pushV",            { RMrBP } },
1770   { "pushV",            { RMrSI } },
1771   { "pushV",            { RMrDI } },
1772   /* 58 */
1773   { "popV",             { RMrAX } },
1774   { "popV",             { RMrCX } },
1775   { "popV",             { RMrDX } },
1776   { "popV",             { RMrBX } },
1777   { "popV",             { RMrSP } },
1778   { "popV",             { RMrBP } },
1779   { "popV",             { RMrSI } },
1780   { "popV",             { RMrDI } },
1781   /* 60 */
1782   { X86_64_TABLE (X86_64_60) },
1783   { X86_64_TABLE (X86_64_61) },
1784   { X86_64_TABLE (X86_64_62) },
1785   { X86_64_TABLE (X86_64_63) },
1786   { Bad_Opcode },       /* seg fs */
1787   { Bad_Opcode },       /* seg gs */
1788   { Bad_Opcode },       /* op size prefix */
1789   { Bad_Opcode },       /* adr size prefix */
1790   /* 68 */
1791   { "pushT",            { sIv } },
1792   { "imulS",            { Gv, Ev, Iv } },
1793   { "pushT",            { sIb } },
1794   { "imulS",            { Gv, Ev, sIb } },
1795   { "ins{b|}",          { Ybr, indirDX } },
1796   { X86_64_TABLE (X86_64_6D) },
1797   { "outs{b|}",         { indirDXr, Xb } },
1798   { X86_64_TABLE (X86_64_6F) },
1799   /* 70 */
1800   { "joH",              { Jb, XX, cond_jump_flag } },
1801   { "jnoH",             { Jb, XX, cond_jump_flag } },
1802   { "jbH",              { Jb, XX, cond_jump_flag } },
1803   { "jaeH",             { Jb, XX, cond_jump_flag } },
1804   { "jeH",              { Jb, XX, cond_jump_flag } },
1805   { "jneH",             { Jb, XX, cond_jump_flag } },
1806   { "jbeH",             { Jb, XX, cond_jump_flag } },
1807   { "jaH",              { Jb, XX, cond_jump_flag } },
1808   /* 78 */
1809   { "jsH",              { Jb, XX, cond_jump_flag } },
1810   { "jnsH",             { Jb, XX, cond_jump_flag } },
1811   { "jpH",              { Jb, XX, cond_jump_flag } },
1812   { "jnpH",             { Jb, XX, cond_jump_flag } },
1813   { "jlH",              { Jb, XX, cond_jump_flag } },
1814   { "jgeH",             { Jb, XX, cond_jump_flag } },
1815   { "jleH",             { Jb, XX, cond_jump_flag } },
1816   { "jgH",              { Jb, XX, cond_jump_flag } },
1817   /* 80 */
1818   { REG_TABLE (REG_80) },
1819   { REG_TABLE (REG_81) },
1820   { Bad_Opcode },
1821   { REG_TABLE (REG_82) },
1822   { "testB",            { Eb, Gb } },
1823   { "testS",            { Ev, Gv } },
1824   { "xchgB",            { Eb, Gb } },
1825   { "xchgS",            { Ev, Gv } },
1826   /* 88 */
1827   { "movB",             { Eb, Gb } },
1828   { "movS",             { Ev, Gv } },
1829   { "movB",             { Gb, EbS } },
1830   { "movS",             { Gv, EvS } },
1831   { "movD",             { Sv, Sw } },
1832   { MOD_TABLE (MOD_8D) },
1833   { "movD",             { Sw, Sv } },
1834   { REG_TABLE (REG_8F) },
1835   /* 90 */
1836   { PREFIX_TABLE (PREFIX_90) },
1837   { "xchgS",            { RMeCX, eAX } },
1838   { "xchgS",            { RMeDX, eAX } },
1839   { "xchgS",            { RMeBX, eAX } },
1840   { "xchgS",            { RMeSP, eAX } },
1841   { "xchgS",            { RMeBP, eAX } },
1842   { "xchgS",            { RMeSI, eAX } },
1843   { "xchgS",            { RMeDI, eAX } },
1844   /* 98 */
1845   { "cW{t|}R",          { XX } },
1846   { "cR{t|}O",          { XX } },
1847   { X86_64_TABLE (X86_64_9A) },
1848   { Bad_Opcode },       /* fwait */
1849   { "pushfT",           { XX } },
1850   { "popfT",            { XX } },
1851   { "sahf",             { XX } },
1852   { "lahf",             { XX } },
1853   /* a0 */
1854   { "mov%LB",           { AL, Ob } },
1855   { "mov%LS",           { eAX, Ov } },
1856   { "mov%LB",           { Ob, AL } },
1857   { "mov%LS",           { Ov, eAX } },
1858   { "movs{b|}",         { Ybr, Xb } },
1859   { "movs{R|}",         { Yvr, Xv } },
1860   { "cmps{b|}",         { Xb, Yb } },
1861   { "cmps{R|}",         { Xv, Yv } },
1862   /* a8 */
1863   { "testB",            { AL, Ib } },
1864   { "testS",            { eAX, Iv } },
1865   { "stosB",            { Ybr, AL } },
1866   { "stosS",            { Yvr, eAX } },
1867   { "lodsB",            { ALr, Xb } },
1868   { "lodsS",            { eAXr, Xv } },
1869   { "scasB",            { AL, Yb } },
1870   { "scasS",            { eAX, Yv } },
1871   /* b0 */
1872   { "movB",             { RMAL, Ib } },
1873   { "movB",             { RMCL, Ib } },
1874   { "movB",             { RMDL, Ib } },
1875   { "movB",             { RMBL, Ib } },
1876   { "movB",             { RMAH, Ib } },
1877   { "movB",             { RMCH, Ib } },
1878   { "movB",             { RMDH, Ib } },
1879   { "movB",             { RMBH, Ib } },
1880   /* b8 */
1881   { "mov%LV",           { RMeAX, Iv64 } },
1882   { "mov%LV",           { RMeCX, Iv64 } },
1883   { "mov%LV",           { RMeDX, Iv64 } },
1884   { "mov%LV",           { RMeBX, Iv64 } },
1885   { "mov%LV",           { RMeSP, Iv64 } },
1886   { "mov%LV",           { RMeBP, Iv64 } },
1887   { "mov%LV",           { RMeSI, Iv64 } },
1888   { "mov%LV",           { RMeDI, Iv64 } },
1889   /* c0 */
1890   { REG_TABLE (REG_C0) },
1891   { REG_TABLE (REG_C1) },
1892   { "retT",             { Iw } },
1893   { "retT",             { XX } },
1894   { X86_64_TABLE (X86_64_C4) },
1895   { X86_64_TABLE (X86_64_C5) },
1896   { REG_TABLE (REG_C6) },
1897   { REG_TABLE (REG_C7) },
1898   /* c8 */
1899   { "enterT",           { Iw, Ib } },
1900   { "leaveT",           { XX } },
1901   { "Jret{|f}P",        { Iw } },
1902   { "Jret{|f}P",        { XX } },
1903   { "int3",             { XX } },
1904   { "int",              { Ib } },
1905   { X86_64_TABLE (X86_64_CE) },
1906   { "iretP",            { XX } },
1907   /* d0 */
1908   { REG_TABLE (REG_D0) },
1909   { REG_TABLE (REG_D1) },
1910   { REG_TABLE (REG_D2) },
1911   { REG_TABLE (REG_D3) },
1912   { X86_64_TABLE (X86_64_D4) },
1913   { X86_64_TABLE (X86_64_D5) },
1914   { Bad_Opcode },
1915   { "xlat",             { DSBX } },
1916   /* d8 */
1917   { FLOAT },
1918   { FLOAT },
1919   { FLOAT },
1920   { FLOAT },
1921   { FLOAT },
1922   { FLOAT },
1923   { FLOAT },
1924   { FLOAT },
1925   /* e0 */
1926   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1927   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1928   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1929   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1930   { "inB",              { AL, Ib } },
1931   { "inG",              { zAX, Ib } },
1932   { "outB",             { Ib, AL } },
1933   { "outG",             { Ib, zAX } },
1934   /* e8 */
1935   { "callT",            { Jv } },
1936   { "jmpT",             { Jv } },
1937   { X86_64_TABLE (X86_64_EA) },
1938   { "jmp",              { Jb } },
1939   { "inB",              { AL, indirDX } },
1940   { "inG",              { zAX, indirDX } },
1941   { "outB",             { indirDX, AL } },
1942   { "outG",             { indirDX, zAX } },
1943   /* f0 */
1944   { Bad_Opcode },       /* lock prefix */
1945   { "icebp",            { XX } },
1946   { Bad_Opcode },       /* repne */
1947   { Bad_Opcode },       /* repz */
1948   { "hlt",              { XX } },
1949   { "cmc",              { XX } },
1950   { REG_TABLE (REG_F6) },
1951   { REG_TABLE (REG_F7) },
1952   /* f8 */
1953   { "clc",              { XX } },
1954   { "stc",              { XX } },
1955   { "cli",              { XX } },
1956   { "sti",              { XX } },
1957   { "cld",              { XX } },
1958   { "std",              { XX } },
1959   { REG_TABLE (REG_FE) },
1960   { REG_TABLE (REG_FF) },
1961 };
1962
1963 static const struct dis386 dis386_twobyte[] = {
1964   /* 00 */
1965   { REG_TABLE (REG_0F00 ) },
1966   { REG_TABLE (REG_0F01 ) },
1967   { "larS",             { Gv, Ew } },
1968   { "lslS",             { Gv, Ew } },
1969   { Bad_Opcode },
1970   { "syscall",          { XX } },
1971   { "clts",             { XX } },
1972   { "sysretP",          { XX } },
1973   /* 08 */
1974   { "invd",             { XX } },
1975   { "wbinvd",           { XX } },
1976   { Bad_Opcode },
1977   { "ud2",              { XX } },
1978   { Bad_Opcode },
1979   { REG_TABLE (REG_0F0D) },
1980   { "femms",            { XX } },
1981   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1982   /* 10 */
1983   { PREFIX_TABLE (PREFIX_0F10) },
1984   { PREFIX_TABLE (PREFIX_0F11) },
1985   { PREFIX_TABLE (PREFIX_0F12) },
1986   { MOD_TABLE (MOD_0F13) },
1987   { "unpcklpX",         { XM, EXx } },
1988   { "unpckhpX",         { XM, EXx } },
1989   { PREFIX_TABLE (PREFIX_0F16) },
1990   { MOD_TABLE (MOD_0F17) },
1991   /* 18 */
1992   { REG_TABLE (REG_0F18) },
1993   { "nopQ",             { Ev } },
1994   { "nopQ",             { Ev } },
1995   { "nopQ",             { Ev } },
1996   { "nopQ",             { Ev } },
1997   { "nopQ",             { Ev } },
1998   { "nopQ",             { Ev } },
1999   { "nopQ",             { Ev } },
2000   /* 20 */
2001   { MOD_TABLE (MOD_0F20) },
2002   { MOD_TABLE (MOD_0F21) },
2003   { MOD_TABLE (MOD_0F22) },
2004   { MOD_TABLE (MOD_0F23) },
2005   { MOD_TABLE (MOD_0F24) },
2006   { Bad_Opcode },
2007   { MOD_TABLE (MOD_0F26) },
2008   { Bad_Opcode },
2009   /* 28 */
2010   { "movapX",           { XM, EXx } },
2011   { "movapX",           { EXxS, XM } },
2012   { PREFIX_TABLE (PREFIX_0F2A) },
2013   { PREFIX_TABLE (PREFIX_0F2B) },
2014   { PREFIX_TABLE (PREFIX_0F2C) },
2015   { PREFIX_TABLE (PREFIX_0F2D) },
2016   { PREFIX_TABLE (PREFIX_0F2E) },
2017   { PREFIX_TABLE (PREFIX_0F2F) },
2018   /* 30 */
2019   { "wrmsr",            { XX } },
2020   { "rdtsc",            { XX } },
2021   { "rdmsr",            { XX } },
2022   { "rdpmc",            { XX } },
2023   { "sysenter",         { XX } },
2024   { "sysexit",          { XX } },
2025   { Bad_Opcode },
2026   { "getsec",           { XX } },
2027   /* 38 */
2028   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2029   { Bad_Opcode },
2030   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2031   { Bad_Opcode },
2032   { Bad_Opcode },
2033   { Bad_Opcode },
2034   { Bad_Opcode },
2035   { Bad_Opcode },
2036   /* 40 */
2037   { "cmovoS",           { Gv, Ev } },
2038   { "cmovnoS",          { Gv, Ev } },
2039   { "cmovbS",           { Gv, Ev } },
2040   { "cmovaeS",          { Gv, Ev } },
2041   { "cmoveS",           { Gv, Ev } },
2042   { "cmovneS",          { Gv, Ev } },
2043   { "cmovbeS",          { Gv, Ev } },
2044   { "cmovaS",           { Gv, Ev } },
2045   /* 48 */
2046   { "cmovsS",           { Gv, Ev } },
2047   { "cmovnsS",          { Gv, Ev } },
2048   { "cmovpS",           { Gv, Ev } },
2049   { "cmovnpS",          { Gv, Ev } },
2050   { "cmovlS",           { Gv, Ev } },
2051   { "cmovgeS",          { Gv, Ev } },
2052   { "cmovleS",          { Gv, Ev } },
2053   { "cmovgS",           { Gv, Ev } },
2054   /* 50 */
2055   { MOD_TABLE (MOD_0F51) },
2056   { PREFIX_TABLE (PREFIX_0F51) },
2057   { PREFIX_TABLE (PREFIX_0F52) },
2058   { PREFIX_TABLE (PREFIX_0F53) },
2059   { "andpX",            { XM, EXx } },
2060   { "andnpX",           { XM, EXx } },
2061   { "orpX",             { XM, EXx } },
2062   { "xorpX",            { XM, EXx } },
2063   /* 58 */
2064   { PREFIX_TABLE (PREFIX_0F58) },
2065   { PREFIX_TABLE (PREFIX_0F59) },
2066   { PREFIX_TABLE (PREFIX_0F5A) },
2067   { PREFIX_TABLE (PREFIX_0F5B) },
2068   { PREFIX_TABLE (PREFIX_0F5C) },
2069   { PREFIX_TABLE (PREFIX_0F5D) },
2070   { PREFIX_TABLE (PREFIX_0F5E) },
2071   { PREFIX_TABLE (PREFIX_0F5F) },
2072   /* 60 */
2073   { PREFIX_TABLE (PREFIX_0F60) },
2074   { PREFIX_TABLE (PREFIX_0F61) },
2075   { PREFIX_TABLE (PREFIX_0F62) },
2076   { "packsswb",         { MX, EM } },
2077   { "pcmpgtb",          { MX, EM } },
2078   { "pcmpgtw",          { MX, EM } },
2079   { "pcmpgtd",          { MX, EM } },
2080   { "packuswb",         { MX, EM } },
2081   /* 68 */
2082   { "punpckhbw",        { MX, EM } },
2083   { "punpckhwd",        { MX, EM } },
2084   { "punpckhdq",        { MX, EM } },
2085   { "packssdw",         { MX, EM } },
2086   { PREFIX_TABLE (PREFIX_0F6C) },
2087   { PREFIX_TABLE (PREFIX_0F6D) },
2088   { "movK",             { MX, Edq } },
2089   { PREFIX_TABLE (PREFIX_0F6F) },
2090   /* 70 */
2091   { PREFIX_TABLE (PREFIX_0F70) },
2092   { REG_TABLE (REG_0F71) },
2093   { REG_TABLE (REG_0F72) },
2094   { REG_TABLE (REG_0F73) },
2095   { "pcmpeqb",          { MX, EM } },
2096   { "pcmpeqw",          { MX, EM } },
2097   { "pcmpeqd",          { MX, EM } },
2098   { "emms",             { XX } },
2099   /* 78 */
2100   { PREFIX_TABLE (PREFIX_0F78) },
2101   { PREFIX_TABLE (PREFIX_0F79) },
2102   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2103   { Bad_Opcode },
2104   { PREFIX_TABLE (PREFIX_0F7C) },
2105   { PREFIX_TABLE (PREFIX_0F7D) },
2106   { PREFIX_TABLE (PREFIX_0F7E) },
2107   { PREFIX_TABLE (PREFIX_0F7F) },
2108   /* 80 */
2109   { "joH",              { Jv, XX, cond_jump_flag } },
2110   { "jnoH",             { Jv, XX, cond_jump_flag } },
2111   { "jbH",              { Jv, XX, cond_jump_flag } },
2112   { "jaeH",             { Jv, XX, cond_jump_flag } },
2113   { "jeH",              { Jv, XX, cond_jump_flag } },
2114   { "jneH",             { Jv, XX, cond_jump_flag } },
2115   { "jbeH",             { Jv, XX, cond_jump_flag } },
2116   { "jaH",              { Jv, XX, cond_jump_flag } },
2117   /* 88 */
2118   { "jsH",              { Jv, XX, cond_jump_flag } },
2119   { "jnsH",             { Jv, XX, cond_jump_flag } },
2120   { "jpH",              { Jv, XX, cond_jump_flag } },
2121   { "jnpH",             { Jv, XX, cond_jump_flag } },
2122   { "jlH",              { Jv, XX, cond_jump_flag } },
2123   { "jgeH",             { Jv, XX, cond_jump_flag } },
2124   { "jleH",             { Jv, XX, cond_jump_flag } },
2125   { "jgH",              { Jv, XX, cond_jump_flag } },
2126   /* 90 */
2127   { "seto",             { Eb } },
2128   { "setno",            { Eb } },
2129   { "setb",             { Eb } },
2130   { "setae",            { Eb } },
2131   { "sete",             { Eb } },
2132   { "setne",            { Eb } },
2133   { "setbe",            { Eb } },
2134   { "seta",             { Eb } },
2135   /* 98 */
2136   { "sets",             { Eb } },
2137   { "setns",            { Eb } },
2138   { "setp",             { Eb } },
2139   { "setnp",            { Eb } },
2140   { "setl",             { Eb } },
2141   { "setge",            { Eb } },
2142   { "setle",            { Eb } },
2143   { "setg",             { Eb } },
2144   /* a0 */
2145   { "pushT",            { fs } },
2146   { "popT",             { fs } },
2147   { "cpuid",            { XX } },
2148   { "btS",              { Ev, Gv } },
2149   { "shldS",            { Ev, Gv, Ib } },
2150   { "shldS",            { Ev, Gv, CL } },
2151   { REG_TABLE (REG_0FA6) },
2152   { REG_TABLE (REG_0FA7) },
2153   /* a8 */
2154   { "pushT",            { gs } },
2155   { "popT",             { gs } },
2156   { "rsm",              { XX } },
2157   { "btsS",             { Ev, Gv } },
2158   { "shrdS",            { Ev, Gv, Ib } },
2159   { "shrdS",            { Ev, Gv, CL } },
2160   { REG_TABLE (REG_0FAE) },
2161   { "imulS",            { Gv, Ev } },
2162   /* b0 */
2163   { "cmpxchgB",         { Eb, Gb } },
2164   { "cmpxchgS",         { Ev, Gv } },
2165   { MOD_TABLE (MOD_0FB2) },
2166   { "btrS",             { Ev, Gv } },
2167   { MOD_TABLE (MOD_0FB4) },
2168   { MOD_TABLE (MOD_0FB5) },
2169   { "movz{bR|x}",       { Gv, Eb } },
2170   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2171   /* b8 */
2172   { PREFIX_TABLE (PREFIX_0FB8) },
2173   { "ud1",              { XX } },
2174   { REG_TABLE (REG_0FBA) },
2175   { "btcS",             { Ev, Gv } },
2176   { PREFIX_TABLE (PREFIX_0FBC) },
2177   { PREFIX_TABLE (PREFIX_0FBD) },
2178   { "movs{bR|x}",       { Gv, Eb } },
2179   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2180   /* c0 */
2181   { "xaddB",            { Eb, Gb } },
2182   { "xaddS",            { Ev, Gv } },
2183   { PREFIX_TABLE (PREFIX_0FC2) },
2184   { PREFIX_TABLE (PREFIX_0FC3) },
2185   { "pinsrw",           { MX, Edqw, Ib } },
2186   { "pextrw",           { Gdq, MS, Ib } },
2187   { "shufpX",           { XM, EXx, Ib } },
2188   { REG_TABLE (REG_0FC7) },
2189   /* c8 */
2190   { "bswap",            { RMeAX } },
2191   { "bswap",            { RMeCX } },
2192   { "bswap",            { RMeDX } },
2193   { "bswap",            { RMeBX } },
2194   { "bswap",            { RMeSP } },
2195   { "bswap",            { RMeBP } },
2196   { "bswap",            { RMeSI } },
2197   { "bswap",            { RMeDI } },
2198   /* d0 */
2199   { PREFIX_TABLE (PREFIX_0FD0) },
2200   { "psrlw",            { MX, EM } },
2201   { "psrld",            { MX, EM } },
2202   { "psrlq",            { MX, EM } },
2203   { "paddq",            { MX, EM } },
2204   { "pmullw",           { MX, EM } },
2205   { PREFIX_TABLE (PREFIX_0FD6) },
2206   { MOD_TABLE (MOD_0FD7) },
2207   /* d8 */
2208   { "psubusb",          { MX, EM } },
2209   { "psubusw",          { MX, EM } },
2210   { "pminub",           { MX, EM } },
2211   { "pand",             { MX, EM } },
2212   { "paddusb",          { MX, EM } },
2213   { "paddusw",          { MX, EM } },
2214   { "pmaxub",           { MX, EM } },
2215   { "pandn",            { MX, EM } },
2216   /* e0 */
2217   { "pavgb",            { MX, EM } },
2218   { "psraw",            { MX, EM } },
2219   { "psrad",            { MX, EM } },
2220   { "pavgw",            { MX, EM } },
2221   { "pmulhuw",          { MX, EM } },
2222   { "pmulhw",           { MX, EM } },
2223   { PREFIX_TABLE (PREFIX_0FE6) },
2224   { PREFIX_TABLE (PREFIX_0FE7) },
2225   /* e8 */
2226   { "psubsb",           { MX, EM } },
2227   { "psubsw",           { MX, EM } },
2228   { "pminsw",           { MX, EM } },
2229   { "por",              { MX, EM } },
2230   { "paddsb",           { MX, EM } },
2231   { "paddsw",           { MX, EM } },
2232   { "pmaxsw",           { MX, EM } },
2233   { "pxor",             { MX, EM } },
2234   /* f0 */
2235   { PREFIX_TABLE (PREFIX_0FF0) },
2236   { "psllw",            { MX, EM } },
2237   { "pslld",            { MX, EM } },
2238   { "psllq",            { MX, EM } },
2239   { "pmuludq",          { MX, EM } },
2240   { "pmaddwd",          { MX, EM } },
2241   { "psadbw",           { MX, EM } },
2242   { PREFIX_TABLE (PREFIX_0FF7) },
2243   /* f8 */
2244   { "psubb",            { MX, EM } },
2245   { "psubw",            { MX, EM } },
2246   { "psubd",            { MX, EM } },
2247   { "psubq",            { MX, EM } },
2248   { "paddb",            { MX, EM } },
2249   { "paddw",            { MX, EM } },
2250   { "paddd",            { MX, EM } },
2251   { Bad_Opcode },
2252 };
2253
2254 static const unsigned char onebyte_has_modrm[256] = {
2255   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2256   /*       -------------------------------        */
2257   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2258   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2259   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2260   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2261   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2262   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2263   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2264   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2265   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2266   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2267   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2268   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2269   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2270   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2271   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2272   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2273   /*       -------------------------------        */
2274   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2275 };
2276
2277 static const unsigned char twobyte_has_modrm[256] = {
2278   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2279   /*       -------------------------------        */
2280   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2281   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2282   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2283   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2284   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2285   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2286   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2287   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2288   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2289   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2290   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2291   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2292   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2293   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2294   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2295   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2296   /*       -------------------------------        */
2297   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2298 };
2299
2300 static char obuf[100];
2301 static char *obufp;
2302 static char *mnemonicendp;
2303 static char scratchbuf[100];
2304 static unsigned char *start_codep;
2305 static unsigned char *insn_codep;
2306 static unsigned char *codep;
2307 static int last_lock_prefix;
2308 static int last_repz_prefix;
2309 static int last_repnz_prefix;
2310 static int last_data_prefix;
2311 static int last_addr_prefix;
2312 static int last_rex_prefix;
2313 static int last_seg_prefix;
2314 #define MAX_CODE_LENGTH 15
2315 /* We can up to 14 prefixes since the maximum instruction length is
2316    15bytes.  */
2317 static int all_prefixes[MAX_CODE_LENGTH - 1];
2318 static disassemble_info *the_info;
2319 static struct
2320   {
2321     int mod;
2322     int reg;
2323     int rm;
2324   }
2325 modrm;
2326 static unsigned char need_modrm;
2327 static struct
2328   {
2329     int scale;
2330     int index;
2331     int base;
2332   }
2333 sib;
2334 static struct
2335   {
2336     int register_specifier;
2337     int length;
2338     int prefix;
2339     int w;
2340   }
2341 vex;
2342 static unsigned char need_vex;
2343 static unsigned char need_vex_reg;
2344 static unsigned char vex_w_done;
2345
2346 struct op
2347   {
2348     const char *name;
2349     unsigned int len;
2350   };
2351
2352 /* If we are accessing mod/rm/reg without need_modrm set, then the
2353    values are stale.  Hitting this abort likely indicates that you
2354    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2355 #define MODRM_CHECK  if (!need_modrm) abort ()
2356
2357 static const char **names64;
2358 static const char **names32;
2359 static const char **names16;
2360 static const char **names8;
2361 static const char **names8rex;
2362 static const char **names_seg;
2363 static const char *index64;
2364 static const char *index32;
2365 static const char **index16;
2366
2367 static const char *intel_names64[] = {
2368   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2369   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2370 };
2371 static const char *intel_names32[] = {
2372   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2373   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2374 };
2375 static const char *intel_names16[] = {
2376   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2377   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2378 };
2379 static const char *intel_names8[] = {
2380   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2381 };
2382 static const char *intel_names8rex[] = {
2383   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2384   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2385 };
2386 static const char *intel_names_seg[] = {
2387   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2388 };
2389 static const char *intel_index64 = "riz";
2390 static const char *intel_index32 = "eiz";
2391 static const char *intel_index16[] = {
2392   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2393 };
2394
2395 static const char *att_names64[] = {
2396   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2397   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2398 };
2399 static const char *att_names32[] = {
2400   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2401   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2402 };
2403 static const char *att_names16[] = {
2404   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2405   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2406 };
2407 static const char *att_names8[] = {
2408   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2409 };
2410 static const char *att_names8rex[] = {
2411   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2412   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2413 };
2414 static const char *att_names_seg[] = {
2415   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2416 };
2417 static const char *att_index64 = "%riz";
2418 static const char *att_index32 = "%eiz";
2419 static const char *att_index16[] = {
2420   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2421 };
2422
2423 static const char **names_mm;
2424 static const char *intel_names_mm[] = {
2425   "mm0", "mm1", "mm2", "mm3",
2426   "mm4", "mm5", "mm6", "mm7"
2427 };
2428 static const char *att_names_mm[] = {
2429   "%mm0", "%mm1", "%mm2", "%mm3",
2430   "%mm4", "%mm5", "%mm6", "%mm7"
2431 };
2432
2433 static const char **names_xmm;
2434 static const char *intel_names_xmm[] = {
2435   "xmm0", "xmm1", "xmm2", "xmm3",
2436   "xmm4", "xmm5", "xmm6", "xmm7",
2437   "xmm8", "xmm9", "xmm10", "xmm11",
2438   "xmm12", "xmm13", "xmm14", "xmm15"
2439 };
2440 static const char *att_names_xmm[] = {
2441   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2442   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2443   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2444   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2445 };
2446
2447 static const char **names_ymm;
2448 static const char *intel_names_ymm[] = {
2449   "ymm0", "ymm1", "ymm2", "ymm3",
2450   "ymm4", "ymm5", "ymm6", "ymm7",
2451   "ymm8", "ymm9", "ymm10", "ymm11",
2452   "ymm12", "ymm13", "ymm14", "ymm15"
2453 };
2454 static const char *att_names_ymm[] = {
2455   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2456   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2457   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2458   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2459 };
2460
2461 static const struct dis386 reg_table[][8] = {
2462   /* REG_80 */
2463   {
2464     { "addA",   { Eb, Ib } },
2465     { "orA",    { Eb, Ib } },
2466     { "adcA",   { Eb, Ib } },
2467     { "sbbA",   { Eb, Ib } },
2468     { "andA",   { Eb, Ib } },
2469     { "subA",   { Eb, Ib } },
2470     { "xorA",   { Eb, Ib } },
2471     { "cmpA",   { Eb, Ib } },
2472   },
2473   /* REG_81 */
2474   {
2475     { "addQ",   { Ev, Iv } },
2476     { "orQ",    { Ev, Iv } },
2477     { "adcQ",   { Ev, Iv } },
2478     { "sbbQ",   { Ev, Iv } },
2479     { "andQ",   { Ev, Iv } },
2480     { "subQ",   { Ev, Iv } },
2481     { "xorQ",   { Ev, Iv } },
2482     { "cmpQ",   { Ev, Iv } },
2483   },
2484   /* REG_82 */
2485   {
2486     { "addQ",   { Ev, sIb } },
2487     { "orQ",    { Ev, sIb } },
2488     { "adcQ",   { Ev, sIb } },
2489     { "sbbQ",   { Ev, sIb } },
2490     { "andQ",   { Ev, sIb } },
2491     { "subQ",   { Ev, sIb } },
2492     { "xorQ",   { Ev, sIb } },
2493     { "cmpQ",   { Ev, sIb } },
2494   },
2495   /* REG_8F */
2496   {
2497     { "popU",   { stackEv } },
2498     { XOP_8F_TABLE (XOP_09) },
2499     { Bad_Opcode },
2500     { Bad_Opcode },
2501     { Bad_Opcode },
2502     { XOP_8F_TABLE (XOP_09) },
2503   },
2504   /* REG_C0 */
2505   {
2506     { "rolA",   { Eb, Ib } },
2507     { "rorA",   { Eb, Ib } },
2508     { "rclA",   { Eb, Ib } },
2509     { "rcrA",   { Eb, Ib } },
2510     { "shlA",   { Eb, Ib } },
2511     { "shrA",   { Eb, Ib } },
2512     { Bad_Opcode },
2513     { "sarA",   { Eb, Ib } },
2514   },
2515   /* REG_C1 */
2516   {
2517     { "rolQ",   { Ev, Ib } },
2518     { "rorQ",   { Ev, Ib } },
2519     { "rclQ",   { Ev, Ib } },
2520     { "rcrQ",   { Ev, Ib } },
2521     { "shlQ",   { Ev, Ib } },
2522     { "shrQ",   { Ev, Ib } },
2523     { Bad_Opcode },
2524     { "sarQ",   { Ev, Ib } },
2525   },
2526   /* REG_C6 */
2527   {
2528     { "movA",   { Eb, Ib } },
2529   },
2530   /* REG_C7 */
2531   {
2532     { "movQ",   { Ev, Iv } },
2533   },
2534   /* REG_D0 */
2535   {
2536     { "rolA",   { Eb, I1 } },
2537     { "rorA",   { Eb, I1 } },
2538     { "rclA",   { Eb, I1 } },
2539     { "rcrA",   { Eb, I1 } },
2540     { "shlA",   { Eb, I1 } },
2541     { "shrA",   { Eb, I1 } },
2542     { Bad_Opcode },
2543     { "sarA",   { Eb, I1 } },
2544   },
2545   /* REG_D1 */
2546   {
2547     { "rolQ",   { Ev, I1 } },
2548     { "rorQ",   { Ev, I1 } },
2549     { "rclQ",   { Ev, I1 } },
2550     { "rcrQ",   { Ev, I1 } },
2551     { "shlQ",   { Ev, I1 } },
2552     { "shrQ",   { Ev, I1 } },
2553     { Bad_Opcode },
2554     { "sarQ",   { Ev, I1 } },
2555   },
2556   /* REG_D2 */
2557   {
2558     { "rolA",   { Eb, CL } },
2559     { "rorA",   { Eb, CL } },
2560     { "rclA",   { Eb, CL } },
2561     { "rcrA",   { Eb, CL } },
2562     { "shlA",   { Eb, CL } },
2563     { "shrA",   { Eb, CL } },
2564     { Bad_Opcode },
2565     { "sarA",   { Eb, CL } },
2566   },
2567   /* REG_D3 */
2568   {
2569     { "rolQ",   { Ev, CL } },
2570     { "rorQ",   { Ev, CL } },
2571     { "rclQ",   { Ev, CL } },
2572     { "rcrQ",   { Ev, CL } },
2573     { "shlQ",   { Ev, CL } },
2574     { "shrQ",   { Ev, CL } },
2575     { Bad_Opcode },
2576     { "sarQ",   { Ev, CL } },
2577   },
2578   /* REG_F6 */
2579   {
2580     { "testA",  { Eb, Ib } },
2581     { Bad_Opcode },
2582     { "notA",   { Eb } },
2583     { "negA",   { Eb } },
2584     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2585     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2586     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2587     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2588   },
2589   /* REG_F7 */
2590   {
2591     { "testQ",  { Ev, Iv } },
2592     { Bad_Opcode },
2593     { "notQ",   { Ev } },
2594     { "negQ",   { Ev } },
2595     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2596     { "imulQ",  { Ev } },
2597     { "divQ",   { Ev } },
2598     { "idivQ",  { Ev } },
2599   },
2600   /* REG_FE */
2601   {
2602     { "incA",   { Eb } },
2603     { "decA",   { Eb } },
2604   },
2605   /* REG_FF */
2606   {
2607     { "incQ",   { Ev } },
2608     { "decQ",   { Ev } },
2609     { "call{T|}", { indirEv } },
2610     { "Jcall{T|}", { indirEp } },
2611     { "jmp{T|}", { indirEv } },
2612     { "Jjmp{T|}", { indirEp } },
2613     { "pushU",  { stackEv } },
2614     { Bad_Opcode },
2615   },
2616   /* REG_0F00 */
2617   {
2618     { "sldtD",  { Sv } },
2619     { "strD",   { Sv } },
2620     { "lldt",   { Ew } },
2621     { "ltr",    { Ew } },
2622     { "verr",   { Ew } },
2623     { "verw",   { Ew } },
2624     { Bad_Opcode },
2625     { Bad_Opcode },
2626   },
2627   /* REG_0F01 */
2628   {
2629     { MOD_TABLE (MOD_0F01_REG_0) },
2630     { MOD_TABLE (MOD_0F01_REG_1) },
2631     { MOD_TABLE (MOD_0F01_REG_2) },
2632     { MOD_TABLE (MOD_0F01_REG_3) },
2633     { "smswD",  { Sv } },
2634     { Bad_Opcode },
2635     { "lmsw",   { Ew } },
2636     { MOD_TABLE (MOD_0F01_REG_7) },
2637   },
2638   /* REG_0F0D */
2639   {
2640     { "prefetch",       { Mb } },
2641     { "prefetchw",      { Mb } },
2642   },
2643   /* REG_0F18 */
2644   {
2645     { MOD_TABLE (MOD_0F18_REG_0) },
2646     { MOD_TABLE (MOD_0F18_REG_1) },
2647     { MOD_TABLE (MOD_0F18_REG_2) },
2648     { MOD_TABLE (MOD_0F18_REG_3) },
2649   },
2650   /* REG_0F71 */
2651   {
2652     { Bad_Opcode },
2653     { Bad_Opcode },
2654     { MOD_TABLE (MOD_0F71_REG_2) },
2655     { Bad_Opcode },
2656     { MOD_TABLE (MOD_0F71_REG_4) },
2657     { Bad_Opcode },
2658     { MOD_TABLE (MOD_0F71_REG_6) },
2659   },
2660   /* REG_0F72 */
2661   {
2662     { Bad_Opcode },
2663     { Bad_Opcode },
2664     { MOD_TABLE (MOD_0F72_REG_2) },
2665     { Bad_Opcode },
2666     { MOD_TABLE (MOD_0F72_REG_4) },
2667     { Bad_Opcode },
2668     { MOD_TABLE (MOD_0F72_REG_6) },
2669   },
2670   /* REG_0F73 */
2671   {
2672     { Bad_Opcode },
2673     { Bad_Opcode },
2674     { MOD_TABLE (MOD_0F73_REG_2) },
2675     { MOD_TABLE (MOD_0F73_REG_3) },
2676     { Bad_Opcode },
2677     { Bad_Opcode },
2678     { MOD_TABLE (MOD_0F73_REG_6) },
2679     { MOD_TABLE (MOD_0F73_REG_7) },
2680   },
2681   /* REG_0FA6 */
2682   {
2683     { "montmul",        { { OP_0f07, 0 } } },
2684     { "xsha1",          { { OP_0f07, 0 } } },
2685     { "xsha256",        { { OP_0f07, 0 } } },
2686   },
2687   /* REG_0FA7 */
2688   {
2689     { "xstore-rng",     { { OP_0f07, 0 } } },
2690     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2691     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2692     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2693     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2694     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2695   },
2696   /* REG_0FAE */
2697   {
2698     { MOD_TABLE (MOD_0FAE_REG_0) },
2699     { MOD_TABLE (MOD_0FAE_REG_1) },
2700     { MOD_TABLE (MOD_0FAE_REG_2) },
2701     { MOD_TABLE (MOD_0FAE_REG_3) },
2702     { MOD_TABLE (MOD_0FAE_REG_4) },
2703     { MOD_TABLE (MOD_0FAE_REG_5) },
2704     { MOD_TABLE (MOD_0FAE_REG_6) },
2705     { MOD_TABLE (MOD_0FAE_REG_7) },
2706   },
2707   /* REG_0FBA */
2708   {
2709     { Bad_Opcode },
2710     { Bad_Opcode },
2711     { Bad_Opcode },
2712     { Bad_Opcode },
2713     { "btQ",    { Ev, Ib } },
2714     { "btsQ",   { Ev, Ib } },
2715     { "btrQ",   { Ev, Ib } },
2716     { "btcQ",   { Ev, Ib } },
2717   },
2718   /* REG_0FC7 */
2719   {
2720     { Bad_Opcode },
2721     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2722     { Bad_Opcode },
2723     { Bad_Opcode },
2724     { Bad_Opcode },
2725     { Bad_Opcode },
2726     { MOD_TABLE (MOD_0FC7_REG_6) },
2727     { MOD_TABLE (MOD_0FC7_REG_7) },
2728   },
2729   /* REG_VEX_0F71 */
2730   {
2731     { Bad_Opcode },
2732     { Bad_Opcode },
2733     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2734     { Bad_Opcode },
2735     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2736     { Bad_Opcode },
2737     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2738   },
2739   /* REG_VEX_0F72 */
2740   {
2741     { Bad_Opcode },
2742     { Bad_Opcode },
2743     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2744     { Bad_Opcode },
2745     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2746     { Bad_Opcode },
2747     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2748   },
2749   /* REG_VEX_0F73 */
2750   {
2751     { Bad_Opcode },
2752     { Bad_Opcode },
2753     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2754     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
2755     { Bad_Opcode },
2756     { Bad_Opcode },
2757     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
2758     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
2759   },
2760   /* REG_VEX_0FAE */
2761   {
2762     { Bad_Opcode },
2763     { Bad_Opcode },
2764     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2765     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2766   },
2767   /* REG_VEX_0F38F3 */
2768   {
2769     { Bad_Opcode },
2770     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
2771     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
2772     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
2773   },
2774   /* REG_XOP_LWPCB */
2775   {
2776     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2777     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2778   },
2779   /* REG_XOP_LWP */
2780   {
2781     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2782     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2783   },
2784   /* REG_XOP_TBM_01 */
2785   {
2786     { Bad_Opcode },
2787     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
2788     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
2789     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
2790     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
2791     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
2792     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
2793     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
2794   },
2795   /* REG_XOP_TBM_02 */
2796   {
2797     { Bad_Opcode },
2798     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
2799     { Bad_Opcode },
2800     { Bad_Opcode },
2801     { Bad_Opcode },
2802     { Bad_Opcode },
2803     { "blci",   { { OP_LWP_E, 0 }, Ev } },
2804   },
2805 };
2806
2807 static const struct dis386 prefix_table[][4] = {
2808   /* PREFIX_90 */
2809   {
2810     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2811     { "pause", { XX } },
2812     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2813   },
2814
2815   /* PREFIX_0F10 */
2816   {
2817     { "movups", { XM, EXx } },
2818     { "movss",  { XM, EXd } },
2819     { "movupd", { XM, EXx } },
2820     { "movsd",  { XM, EXq } },
2821   },
2822
2823   /* PREFIX_0F11 */
2824   {
2825     { "movups", { EXxS, XM } },
2826     { "movss",  { EXdS, XM } },
2827     { "movupd", { EXxS, XM } },
2828     { "movsd",  { EXqS, XM } },
2829   },
2830
2831   /* PREFIX_0F12 */
2832   {
2833     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2834     { "movsldup", { XM, EXx } },
2835     { "movlpd", { XM, EXq } },
2836     { "movddup", { XM, EXq } },
2837   },
2838
2839   /* PREFIX_0F16 */
2840   {
2841     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2842     { "movshdup", { XM, EXx } },
2843     { "movhpd", { XM, EXq } },
2844   },
2845
2846   /* PREFIX_0F2A */
2847   {
2848     { "cvtpi2ps", { XM, EMCq } },
2849     { "cvtsi2ss%LQ", { XM, Ev } },
2850     { "cvtpi2pd", { XM, EMCq } },
2851     { "cvtsi2sd%LQ", { XM, Ev } },
2852   },
2853
2854   /* PREFIX_0F2B */
2855   {
2856     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2857     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2858     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2859     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2860   },
2861
2862   /* PREFIX_0F2C */
2863   {
2864     { "cvttps2pi", { MXC, EXq } },
2865     { "cvttss2siY", { Gv, EXd } },
2866     { "cvttpd2pi", { MXC, EXx } },
2867     { "cvttsd2siY", { Gv, EXq } },
2868   },
2869
2870   /* PREFIX_0F2D */
2871   {
2872     { "cvtps2pi", { MXC, EXq } },
2873     { "cvtss2siY", { Gv, EXd } },
2874     { "cvtpd2pi", { MXC, EXx } },
2875     { "cvtsd2siY", { Gv, EXq } },
2876   },
2877
2878   /* PREFIX_0F2E */
2879   {
2880     { "ucomiss",{ XM, EXd } },
2881     { Bad_Opcode },
2882     { "ucomisd",{ XM, EXq } },
2883   },
2884
2885   /* PREFIX_0F2F */
2886   {
2887     { "comiss", { XM, EXd } },
2888     { Bad_Opcode },
2889     { "comisd", { XM, EXq } },
2890   },
2891
2892   /* PREFIX_0F51 */
2893   {
2894     { "sqrtps", { XM, EXx } },
2895     { "sqrtss", { XM, EXd } },
2896     { "sqrtpd", { XM, EXx } },
2897     { "sqrtsd", { XM, EXq } },
2898   },
2899
2900   /* PREFIX_0F52 */
2901   {
2902     { "rsqrtps",{ XM, EXx } },
2903     { "rsqrtss",{ XM, EXd } },
2904   },
2905
2906   /* PREFIX_0F53 */
2907   {
2908     { "rcpps",  { XM, EXx } },
2909     { "rcpss",  { XM, EXd } },
2910   },
2911
2912   /* PREFIX_0F58 */
2913   {
2914     { "addps", { XM, EXx } },
2915     { "addss", { XM, EXd } },
2916     { "addpd", { XM, EXx } },
2917     { "addsd", { XM, EXq } },
2918   },
2919
2920   /* PREFIX_0F59 */
2921   {
2922     { "mulps",  { XM, EXx } },
2923     { "mulss",  { XM, EXd } },
2924     { "mulpd",  { XM, EXx } },
2925     { "mulsd",  { XM, EXq } },
2926   },
2927
2928   /* PREFIX_0F5A */
2929   {
2930     { "cvtps2pd", { XM, EXq } },
2931     { "cvtss2sd", { XM, EXd } },
2932     { "cvtpd2ps", { XM, EXx } },
2933     { "cvtsd2ss", { XM, EXq } },
2934   },
2935
2936   /* PREFIX_0F5B */
2937   {
2938     { "cvtdq2ps", { XM, EXx } },
2939     { "cvttps2dq", { XM, EXx } },
2940     { "cvtps2dq", { XM, EXx } },
2941   },
2942
2943   /* PREFIX_0F5C */
2944   {
2945     { "subps",  { XM, EXx } },
2946     { "subss",  { XM, EXd } },
2947     { "subpd",  { XM, EXx } },
2948     { "subsd",  { XM, EXq } },
2949   },
2950
2951   /* PREFIX_0F5D */
2952   {
2953     { "minps",  { XM, EXx } },
2954     { "minss",  { XM, EXd } },
2955     { "minpd",  { XM, EXx } },
2956     { "minsd",  { XM, EXq } },
2957   },
2958
2959   /* PREFIX_0F5E */
2960   {
2961     { "divps",  { XM, EXx } },
2962     { "divss",  { XM, EXd } },
2963     { "divpd",  { XM, EXx } },
2964     { "divsd",  { XM, EXq } },
2965   },
2966
2967   /* PREFIX_0F5F */
2968   {
2969     { "maxps",  { XM, EXx } },
2970     { "maxss",  { XM, EXd } },
2971     { "maxpd",  { XM, EXx } },
2972     { "maxsd",  { XM, EXq } },
2973   },
2974
2975   /* PREFIX_0F60 */
2976   {
2977     { "punpcklbw",{ MX, EMd } },
2978     { Bad_Opcode },
2979     { "punpcklbw",{ MX, EMx } },
2980   },
2981
2982   /* PREFIX_0F61 */
2983   {
2984     { "punpcklwd",{ MX, EMd } },
2985     { Bad_Opcode },
2986     { "punpcklwd",{ MX, EMx } },
2987   },
2988
2989   /* PREFIX_0F62 */
2990   {
2991     { "punpckldq",{ MX, EMd } },
2992     { Bad_Opcode },
2993     { "punpckldq",{ MX, EMx } },
2994   },
2995
2996   /* PREFIX_0F6C */
2997   {
2998     { Bad_Opcode },
2999     { Bad_Opcode },
3000     { "punpcklqdq", { XM, EXx } },
3001   },
3002
3003   /* PREFIX_0F6D */
3004   {
3005     { Bad_Opcode },
3006     { Bad_Opcode },
3007     { "punpckhqdq", { XM, EXx } },
3008   },
3009
3010   /* PREFIX_0F6F */
3011   {
3012     { "movq",   { MX, EM } },
3013     { "movdqu", { XM, EXx } },
3014     { "movdqa", { XM, EXx } },
3015   },
3016
3017   /* PREFIX_0F70 */
3018   {
3019     { "pshufw", { MX, EM, Ib } },
3020     { "pshufhw",{ XM, EXx, Ib } },
3021     { "pshufd", { XM, EXx, Ib } },
3022     { "pshuflw",{ XM, EXx, Ib } },
3023   },
3024
3025   /* PREFIX_0F73_REG_3 */
3026   {
3027     { Bad_Opcode },
3028     { Bad_Opcode },
3029     { "psrldq", { XS, Ib } },
3030   },
3031
3032   /* PREFIX_0F73_REG_7 */
3033   {
3034     { Bad_Opcode },
3035     { Bad_Opcode },
3036     { "pslldq", { XS, Ib } },
3037   },
3038
3039   /* PREFIX_0F78 */
3040   {
3041     {"vmread",  { Em, Gm } },
3042     { Bad_Opcode },
3043     {"extrq",   { XS, Ib, Ib } },
3044     {"insertq", { XM, XS, Ib, Ib } },
3045   },
3046
3047   /* PREFIX_0F79 */
3048   {
3049     {"vmwrite", { Gm, Em } },
3050     { Bad_Opcode },
3051     {"extrq",   { XM, XS } },
3052     {"insertq", { XM, XS } },
3053   },
3054
3055   /* PREFIX_0F7C */
3056   {
3057     { Bad_Opcode },
3058     { Bad_Opcode },
3059     { "haddpd", { XM, EXx } },
3060     { "haddps", { XM, EXx } },
3061   },
3062
3063   /* PREFIX_0F7D */
3064   {
3065     { Bad_Opcode },
3066     { Bad_Opcode },
3067     { "hsubpd", { XM, EXx } },
3068     { "hsubps", { XM, EXx } },
3069   },
3070
3071   /* PREFIX_0F7E */
3072   {
3073     { "movK",   { Edq, MX } },
3074     { "movq",   { XM, EXq } },
3075     { "movK",   { Edq, XM } },
3076   },
3077
3078   /* PREFIX_0F7F */
3079   {
3080     { "movq",   { EMS, MX } },
3081     { "movdqu", { EXxS, XM } },
3082     { "movdqa", { EXxS, XM } },
3083   },
3084
3085   /* PREFIX_0FAE_REG_0 */
3086   {
3087     { Bad_Opcode },
3088     { "rdfsbase", { Ev } },
3089   },
3090
3091   /* PREFIX_0FAE_REG_1 */
3092   {
3093     { Bad_Opcode },
3094     { "rdgsbase", { Ev } },
3095   },
3096
3097   /* PREFIX_0FAE_REG_2 */
3098   {
3099     { Bad_Opcode },
3100     { "wrfsbase", { Ev } },
3101   },
3102
3103   /* PREFIX_0FAE_REG_3 */
3104   {
3105     { Bad_Opcode },
3106     { "wrgsbase", { Ev } },
3107   },
3108
3109   /* PREFIX_0FB8 */
3110   {
3111     { Bad_Opcode },
3112     { "popcntS", { Gv, Ev } },
3113   },
3114
3115   /* PREFIX_0FBC */
3116   {
3117     { "bsfS",   { Gv, Ev } },
3118     { "tzcntS", { Gv, Ev } },
3119     { "bsfS",   { Gv, Ev } },
3120   },
3121
3122   /* PREFIX_0FBD */
3123   {
3124     { "bsrS",   { Gv, Ev } },
3125     { "lzcntS", { Gv, Ev } },
3126     { "bsrS",   { Gv, Ev } },
3127   },
3128
3129   /* PREFIX_0FC2 */
3130   {
3131     { "cmpps",  { XM, EXx, CMP } },
3132     { "cmpss",  { XM, EXd, CMP } },
3133     { "cmppd",  { XM, EXx, CMP } },
3134     { "cmpsd",  { XM, EXq, CMP } },
3135   },
3136
3137   /* PREFIX_0FC3 */
3138   {
3139     { "movntiS", { Ma, Gv } },
3140   },
3141
3142   /* PREFIX_0FC7_REG_6 */
3143   {
3144     { "vmptrld",{ Mq } },
3145     { "vmxon",  { Mq } },
3146     { "vmclear",{ Mq } },
3147   },
3148
3149   /* PREFIX_0FD0 */
3150   {
3151     { Bad_Opcode },
3152     { Bad_Opcode },
3153     { "addsubpd", { XM, EXx } },
3154     { "addsubps", { XM, EXx } },
3155   },
3156
3157   /* PREFIX_0FD6 */
3158   {
3159     { Bad_Opcode },
3160     { "movq2dq",{ XM, MS } },
3161     { "movq",   { EXqS, XM } },
3162     { "movdq2q",{ MX, XS } },
3163   },
3164
3165   /* PREFIX_0FE6 */
3166   {
3167     { Bad_Opcode },
3168     { "cvtdq2pd", { XM, EXq } },
3169     { "cvttpd2dq", { XM, EXx } },
3170     { "cvtpd2dq", { XM, EXx } },
3171   },
3172
3173   /* PREFIX_0FE7 */
3174   {
3175     { "movntq", { Mq, MX } },
3176     { Bad_Opcode },
3177     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3178   },
3179
3180   /* PREFIX_0FF0 */
3181   {
3182     { Bad_Opcode },
3183     { Bad_Opcode },
3184     { Bad_Opcode },
3185     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3186   },
3187
3188   /* PREFIX_0FF7 */
3189   {
3190     { "maskmovq", { MX, MS } },
3191     { Bad_Opcode },
3192     { "maskmovdqu", { XM, XS } },
3193   },
3194
3195   /* PREFIX_0F3810 */
3196   {
3197     { Bad_Opcode },
3198     { Bad_Opcode },
3199     { "pblendvb", { XM, EXx, XMM0 } },
3200   },
3201
3202   /* PREFIX_0F3814 */
3203   {
3204     { Bad_Opcode },
3205     { Bad_Opcode },
3206     { "blendvps", { XM, EXx, XMM0 } },
3207   },
3208
3209   /* PREFIX_0F3815 */
3210   {
3211     { Bad_Opcode },
3212     { Bad_Opcode },
3213     { "blendvpd", { XM, EXx, XMM0 } },
3214   },
3215
3216   /* PREFIX_0F3817 */
3217   {
3218     { Bad_Opcode },
3219     { Bad_Opcode },
3220     { "ptest",  { XM, EXx } },
3221   },
3222
3223   /* PREFIX_0F3820 */
3224   {
3225     { Bad_Opcode },
3226     { Bad_Opcode },
3227     { "pmovsxbw", { XM, EXq } },
3228   },
3229
3230   /* PREFIX_0F3821 */
3231   {
3232     { Bad_Opcode },
3233     { Bad_Opcode },
3234     { "pmovsxbd", { XM, EXd } },
3235   },
3236
3237   /* PREFIX_0F3822 */
3238   {
3239     { Bad_Opcode },
3240     { Bad_Opcode },
3241     { "pmovsxbq", { XM, EXw } },
3242   },
3243
3244   /* PREFIX_0F3823 */
3245   {
3246     { Bad_Opcode },
3247     { Bad_Opcode },
3248     { "pmovsxwd", { XM, EXq } },
3249   },
3250
3251   /* PREFIX_0F3824 */
3252   {
3253     { Bad_Opcode },
3254     { Bad_Opcode },
3255     { "pmovsxwq", { XM, EXd } },
3256   },
3257
3258   /* PREFIX_0F3825 */
3259   {
3260     { Bad_Opcode },
3261     { Bad_Opcode },
3262     { "pmovsxdq", { XM, EXq } },
3263   },
3264
3265   /* PREFIX_0F3828 */
3266   {
3267     { Bad_Opcode },
3268     { Bad_Opcode },
3269     { "pmuldq", { XM, EXx } },
3270   },
3271
3272   /* PREFIX_0F3829 */
3273   {
3274     { Bad_Opcode },
3275     { Bad_Opcode },
3276     { "pcmpeqq", { XM, EXx } },
3277   },
3278
3279   /* PREFIX_0F382A */
3280   {
3281     { Bad_Opcode },
3282     { Bad_Opcode },
3283     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3284   },
3285
3286   /* PREFIX_0F382B */
3287   {
3288     { Bad_Opcode },
3289     { Bad_Opcode },
3290     { "packusdw", { XM, EXx } },
3291   },
3292
3293   /* PREFIX_0F3830 */
3294   {
3295     { Bad_Opcode },
3296     { Bad_Opcode },
3297     { "pmovzxbw", { XM, EXq } },
3298   },
3299
3300   /* PREFIX_0F3831 */
3301   {
3302     { Bad_Opcode },
3303     { Bad_Opcode },
3304     { "pmovzxbd", { XM, EXd } },
3305   },
3306
3307   /* PREFIX_0F3832 */
3308   {
3309     { Bad_Opcode },
3310     { Bad_Opcode },
3311     { "pmovzxbq", { XM, EXw } },
3312   },
3313
3314   /* PREFIX_0F3833 */
3315   {
3316     { Bad_Opcode },
3317     { Bad_Opcode },
3318     { "pmovzxwd", { XM, EXq } },
3319   },
3320
3321   /* PREFIX_0F3834 */
3322   {
3323     { Bad_Opcode },
3324     { Bad_Opcode },
3325     { "pmovzxwq", { XM, EXd } },
3326   },
3327
3328   /* PREFIX_0F3835 */
3329   {
3330     { Bad_Opcode },
3331     { Bad_Opcode },
3332     { "pmovzxdq", { XM, EXq } },
3333   },
3334
3335   /* PREFIX_0F3837 */
3336   {
3337     { Bad_Opcode },
3338     { Bad_Opcode },
3339     { "pcmpgtq", { XM, EXx } },
3340   },
3341
3342   /* PREFIX_0F3838 */
3343   {
3344     { Bad_Opcode },
3345     { Bad_Opcode },
3346     { "pminsb", { XM, EXx } },
3347   },
3348
3349   /* PREFIX_0F3839 */
3350   {
3351     { Bad_Opcode },
3352     { Bad_Opcode },
3353     { "pminsd", { XM, EXx } },
3354   },
3355
3356   /* PREFIX_0F383A */
3357   {
3358     { Bad_Opcode },
3359     { Bad_Opcode },
3360     { "pminuw", { XM, EXx } },
3361   },
3362
3363   /* PREFIX_0F383B */
3364   {
3365     { Bad_Opcode },
3366     { Bad_Opcode },
3367     { "pminud", { XM, EXx } },
3368   },
3369
3370   /* PREFIX_0F383C */
3371   {
3372     { Bad_Opcode },
3373     { Bad_Opcode },
3374     { "pmaxsb", { XM, EXx } },
3375   },
3376
3377   /* PREFIX_0F383D */
3378   {
3379     { Bad_Opcode },
3380     { Bad_Opcode },
3381     { "pmaxsd", { XM, EXx } },
3382   },
3383
3384   /* PREFIX_0F383E */
3385   {
3386     { Bad_Opcode },
3387     { Bad_Opcode },
3388     { "pmaxuw", { XM, EXx } },
3389   },
3390
3391   /* PREFIX_0F383F */
3392   {
3393     { Bad_Opcode },
3394     { Bad_Opcode },
3395     { "pmaxud", { XM, EXx } },
3396   },
3397
3398   /* PREFIX_0F3840 */
3399   {
3400     { Bad_Opcode },
3401     { Bad_Opcode },
3402     { "pmulld", { XM, EXx } },
3403   },
3404
3405   /* PREFIX_0F3841 */
3406   {
3407     { Bad_Opcode },
3408     { Bad_Opcode },
3409     { "phminposuw", { XM, EXx } },
3410   },
3411
3412   /* PREFIX_0F3880 */
3413   {
3414     { Bad_Opcode },
3415     { Bad_Opcode },
3416     { "invept", { Gm, Mo } },
3417   },
3418
3419   /* PREFIX_0F3881 */
3420   {
3421     { Bad_Opcode },
3422     { Bad_Opcode },
3423     { "invvpid", { Gm, Mo } },
3424   },
3425
3426   /* PREFIX_0F38DB */
3427   {
3428     { Bad_Opcode },
3429     { Bad_Opcode },
3430     { "aesimc", { XM, EXx } },
3431   },
3432
3433   /* PREFIX_0F38DC */
3434   {
3435     { Bad_Opcode },
3436     { Bad_Opcode },
3437     { "aesenc", { XM, EXx } },
3438   },
3439
3440   /* PREFIX_0F38DD */
3441   {
3442     { Bad_Opcode },
3443     { Bad_Opcode },
3444     { "aesenclast", { XM, EXx } },
3445   },
3446
3447   /* PREFIX_0F38DE */
3448   {
3449     { Bad_Opcode },
3450     { Bad_Opcode },
3451     { "aesdec", { XM, EXx } },
3452   },
3453
3454   /* PREFIX_0F38DF */
3455   {
3456     { Bad_Opcode },
3457     { Bad_Opcode },
3458     { "aesdeclast", { XM, EXx } },
3459   },
3460
3461   /* PREFIX_0F38F0 */
3462   {
3463     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3464     { Bad_Opcode },
3465     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3466     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3467   },
3468
3469   /* PREFIX_0F38F1 */
3470   {
3471     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3472     { Bad_Opcode },
3473     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3474     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3475   },
3476
3477   /* PREFIX_0F3A08 */
3478   {
3479     { Bad_Opcode },
3480     { Bad_Opcode },
3481     { "roundps", { XM, EXx, Ib } },
3482   },
3483
3484   /* PREFIX_0F3A09 */
3485   {
3486     { Bad_Opcode },
3487     { Bad_Opcode },
3488     { "roundpd", { XM, EXx, Ib } },
3489   },
3490
3491   /* PREFIX_0F3A0A */
3492   {
3493     { Bad_Opcode },
3494     { Bad_Opcode },
3495     { "roundss", { XM, EXd, Ib } },
3496   },
3497
3498   /* PREFIX_0F3A0B */
3499   {
3500     { Bad_Opcode },
3501     { Bad_Opcode },
3502     { "roundsd", { XM, EXq, Ib } },
3503   },
3504
3505   /* PREFIX_0F3A0C */
3506   {
3507     { Bad_Opcode },
3508     { Bad_Opcode },
3509     { "blendps", { XM, EXx, Ib } },
3510   },
3511
3512   /* PREFIX_0F3A0D */
3513   {
3514     { Bad_Opcode },
3515     { Bad_Opcode },
3516     { "blendpd", { XM, EXx, Ib } },
3517   },
3518
3519   /* PREFIX_0F3A0E */
3520   {
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { "pblendw", { XM, EXx, Ib } },
3524   },
3525
3526   /* PREFIX_0F3A14 */
3527   {
3528     { Bad_Opcode },
3529     { Bad_Opcode },
3530     { "pextrb", { Edqb, XM, Ib } },
3531   },
3532
3533   /* PREFIX_0F3A15 */
3534   {
3535     { Bad_Opcode },
3536     { Bad_Opcode },
3537     { "pextrw", { Edqw, XM, Ib } },
3538   },
3539
3540   /* PREFIX_0F3A16 */
3541   {
3542     { Bad_Opcode },
3543     { Bad_Opcode },
3544     { "pextrK", { Edq, XM, Ib } },
3545   },
3546
3547   /* PREFIX_0F3A17 */
3548   {
3549     { Bad_Opcode },
3550     { Bad_Opcode },
3551     { "extractps", { Edqd, XM, Ib } },
3552   },
3553
3554   /* PREFIX_0F3A20 */
3555   {
3556     { Bad_Opcode },
3557     { Bad_Opcode },
3558     { "pinsrb", { XM, Edqb, Ib } },
3559   },
3560
3561   /* PREFIX_0F3A21 */
3562   {
3563     { Bad_Opcode },
3564     { Bad_Opcode },
3565     { "insertps", { XM, EXd, Ib } },
3566   },
3567
3568   /* PREFIX_0F3A22 */
3569   {
3570     { Bad_Opcode },
3571     { Bad_Opcode },
3572     { "pinsrK", { XM, Edq, Ib } },
3573   },
3574
3575   /* PREFIX_0F3A40 */
3576   {
3577     { Bad_Opcode },
3578     { Bad_Opcode },
3579     { "dpps",   { XM, EXx, Ib } },
3580   },
3581
3582   /* PREFIX_0F3A41 */
3583   {
3584     { Bad_Opcode },
3585     { Bad_Opcode },
3586     { "dppd",   { XM, EXx, Ib } },
3587   },
3588
3589   /* PREFIX_0F3A42 */
3590   {
3591     { Bad_Opcode },
3592     { Bad_Opcode },
3593     { "mpsadbw", { XM, EXx, Ib } },
3594   },
3595
3596   /* PREFIX_0F3A44 */
3597   {
3598     { Bad_Opcode },
3599     { Bad_Opcode },
3600     { "pclmulqdq", { XM, EXx, PCLMUL } },
3601   },
3602
3603   /* PREFIX_0F3A60 */
3604   {
3605     { Bad_Opcode },
3606     { Bad_Opcode },
3607     { "pcmpestrm", { XM, EXx, Ib } },
3608   },
3609
3610   /* PREFIX_0F3A61 */
3611   {
3612     { Bad_Opcode },
3613     { Bad_Opcode },
3614     { "pcmpestri", { XM, EXx, Ib } },
3615   },
3616
3617   /* PREFIX_0F3A62 */
3618   {
3619     { Bad_Opcode },
3620     { Bad_Opcode },
3621     { "pcmpistrm", { XM, EXx, Ib } },
3622   },
3623
3624   /* PREFIX_0F3A63 */
3625   {
3626     { Bad_Opcode },
3627     { Bad_Opcode },
3628     { "pcmpistri", { XM, EXx, Ib } },
3629   },
3630
3631   /* PREFIX_0F3ADF */
3632   {
3633     { Bad_Opcode },
3634     { Bad_Opcode },
3635     { "aeskeygenassist", { XM, EXx, Ib } },
3636   },
3637
3638   /* PREFIX_VEX_0F10 */
3639   {
3640     { VEX_W_TABLE (VEX_W_0F10_P_0) },
3641     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
3642     { VEX_W_TABLE (VEX_W_0F10_P_2) },
3643     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
3644   },
3645
3646   /* PREFIX_VEX_0F11 */
3647   {
3648     { VEX_W_TABLE (VEX_W_0F11_P_0) },
3649     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
3650     { VEX_W_TABLE (VEX_W_0F11_P_2) },
3651     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
3652   },
3653
3654   /* PREFIX_VEX_0F12 */
3655   {
3656     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3657     { VEX_W_TABLE (VEX_W_0F12_P_1) },
3658     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3659     { VEX_W_TABLE (VEX_W_0F12_P_3) },
3660   },
3661
3662   /* PREFIX_VEX_0F16 */
3663   {
3664     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3665     { VEX_W_TABLE (VEX_W_0F16_P_1) },
3666     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3667   },
3668
3669   /* PREFIX_VEX_0F2A */
3670   {
3671     { Bad_Opcode },
3672     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
3673     { Bad_Opcode },
3674     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
3675   },
3676
3677   /* PREFIX_VEX_0F2C */
3678   {
3679     { Bad_Opcode },
3680     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
3681     { Bad_Opcode },
3682     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
3683   },
3684
3685   /* PREFIX_VEX_0F2D */
3686   {
3687     { Bad_Opcode },
3688     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
3689     { Bad_Opcode },
3690     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
3691   },
3692
3693   /* PREFIX_VEX_0F2E */
3694   {
3695     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
3696     { Bad_Opcode },
3697     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
3698   },
3699
3700   /* PREFIX_VEX_0F2F */
3701   {
3702     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
3703     { Bad_Opcode },
3704     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
3705   },
3706
3707   /* PREFIX_VEX_0F51 */
3708   {
3709     { VEX_W_TABLE (VEX_W_0F51_P_0) },
3710     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
3711     { VEX_W_TABLE (VEX_W_0F51_P_2) },
3712     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
3713   },
3714
3715   /* PREFIX_VEX_0F52 */
3716   {
3717     { VEX_W_TABLE (VEX_W_0F52_P_0) },
3718     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
3719   },
3720
3721   /* PREFIX_VEX_0F53 */
3722   {
3723     { VEX_W_TABLE (VEX_W_0F53_P_0) },
3724     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
3725   },
3726
3727   /* PREFIX_VEX_0F58 */
3728   {
3729     { VEX_W_TABLE (VEX_W_0F58_P_0) },
3730     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
3731     { VEX_W_TABLE (VEX_W_0F58_P_2) },
3732     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
3733   },
3734
3735   /* PREFIX_VEX_0F59 */
3736   {
3737     { VEX_W_TABLE (VEX_W_0F59_P_0) },
3738     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
3739     { VEX_W_TABLE (VEX_W_0F59_P_2) },
3740     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
3741   },
3742
3743   /* PREFIX_VEX_0F5A */
3744   {
3745     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
3746     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
3747     { "vcvtpd2ps%XY", { XMM, EXx } },
3748     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
3749   },
3750
3751   /* PREFIX_VEX_0F5B */
3752   {
3753     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
3754     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
3755     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
3756   },
3757
3758   /* PREFIX_VEX_0F5C */
3759   {
3760     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
3761     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
3762     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
3763     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
3764   },
3765
3766   /* PREFIX_VEX_0F5D */
3767   {
3768     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
3769     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
3770     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
3771     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
3772   },
3773
3774   /* PREFIX_VEX_0F5E */
3775   {
3776     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
3777     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
3778     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
3779     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
3780   },
3781
3782   /* PREFIX_VEX_0F5F */
3783   {
3784     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
3785     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
3786     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
3787     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
3788   },
3789
3790   /* PREFIX_VEX_0F60 */
3791   {
3792     { Bad_Opcode },
3793     { Bad_Opcode },
3794     { VEX_LEN_TABLE (VEX_LEN_0F60_P_2) },
3795   },
3796
3797   /* PREFIX_VEX_0F61 */
3798   {
3799     { Bad_Opcode },
3800     { Bad_Opcode },
3801     { VEX_LEN_TABLE (VEX_LEN_0F61_P_2) },
3802   },
3803
3804   /* PREFIX_VEX_0F62 */
3805   {
3806     { Bad_Opcode },
3807     { Bad_Opcode },
3808     { VEX_LEN_TABLE (VEX_LEN_0F62_P_2) },
3809   },
3810
3811   /* PREFIX_VEX_0F63 */
3812   {
3813     { Bad_Opcode },
3814     { Bad_Opcode },
3815     { VEX_LEN_TABLE (VEX_LEN_0F63_P_2) },
3816   },
3817
3818   /* PREFIX_VEX_0F64 */
3819   {
3820     { Bad_Opcode },
3821     { Bad_Opcode },
3822     { VEX_LEN_TABLE (VEX_LEN_0F64_P_2) },
3823   },
3824
3825   /* PREFIX_VEX_0F65 */
3826   {
3827     { Bad_Opcode },
3828     { Bad_Opcode },
3829     { VEX_LEN_TABLE (VEX_LEN_0F65_P_2) },
3830   },
3831
3832   /* PREFIX_VEX_0F66 */
3833   {
3834     { Bad_Opcode },
3835     { Bad_Opcode },
3836     { VEX_LEN_TABLE (VEX_LEN_0F66_P_2) },
3837   },
3838
3839   /* PREFIX_VEX_0F67 */
3840   {
3841     { Bad_Opcode },
3842     { Bad_Opcode },
3843     { VEX_LEN_TABLE (VEX_LEN_0F67_P_2) },
3844   },
3845
3846   /* PREFIX_VEX_0F68 */
3847   {
3848     { Bad_Opcode },
3849     { Bad_Opcode },
3850     { VEX_LEN_TABLE (VEX_LEN_0F68_P_2) },
3851   },
3852
3853   /* PREFIX_VEX_0F69 */
3854   {
3855     { Bad_Opcode },
3856     { Bad_Opcode },
3857     { VEX_LEN_TABLE (VEX_LEN_0F69_P_2) },
3858   },
3859
3860   /* PREFIX_VEX_0F6A */
3861   {
3862     { Bad_Opcode },
3863     { Bad_Opcode },
3864     { VEX_LEN_TABLE (VEX_LEN_0F6A_P_2) },
3865   },
3866
3867   /* PREFIX_VEX_0F6B */
3868   {
3869     { Bad_Opcode },
3870     { Bad_Opcode },
3871     { VEX_LEN_TABLE (VEX_LEN_0F6B_P_2) },
3872   },
3873
3874   /* PREFIX_VEX_0F6C */
3875   {
3876     { Bad_Opcode },
3877     { Bad_Opcode },
3878     { VEX_LEN_TABLE (VEX_LEN_0F6C_P_2) },
3879   },
3880
3881   /* PREFIX_VEX_0F6D */
3882   {
3883     { Bad_Opcode },
3884     { Bad_Opcode },
3885     { VEX_LEN_TABLE (VEX_LEN_0F6D_P_2) },
3886   },
3887
3888   /* PREFIX_VEX_0F6E */
3889   {
3890     { Bad_Opcode },
3891     { Bad_Opcode },
3892     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
3893   },
3894
3895   /* PREFIX_VEX_0F6F */
3896   {
3897     { Bad_Opcode },
3898     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
3899     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
3900   },
3901
3902   /* PREFIX_VEX_0F70 */
3903   {
3904     { Bad_Opcode },
3905     { VEX_LEN_TABLE (VEX_LEN_0F70_P_1) },
3906     { VEX_LEN_TABLE (VEX_LEN_0F70_P_2) },
3907     { VEX_LEN_TABLE (VEX_LEN_0F70_P_3) },
3908   },
3909
3910   /* PREFIX_VEX_0F71_REG_2 */
3911   {
3912     { Bad_Opcode },
3913     { Bad_Opcode },
3914     { VEX_LEN_TABLE (VEX_LEN_0F71_R_2_P_2) },
3915   },
3916
3917   /* PREFIX_VEX_0F71_REG_4 */
3918   {
3919     { Bad_Opcode },
3920     { Bad_Opcode },
3921     { VEX_LEN_TABLE (VEX_LEN_0F71_R_4_P_2) },
3922   },
3923
3924   /* PREFIX_VEX_0F71_REG_6 */
3925   {
3926     { Bad_Opcode },
3927     { Bad_Opcode },
3928     { VEX_LEN_TABLE (VEX_LEN_0F71_R_6_P_2) },
3929   },
3930
3931   /* PREFIX_VEX_0F72_REG_2 */
3932   {
3933     { Bad_Opcode },
3934     { Bad_Opcode },
3935     { VEX_LEN_TABLE (VEX_LEN_0F72_R_2_P_2) },
3936   },
3937
3938   /* PREFIX_VEX_0F72_REG_4 */
3939   {
3940     { Bad_Opcode },
3941     { Bad_Opcode },
3942     { VEX_LEN_TABLE (VEX_LEN_0F72_R_4_P_2) },
3943   },
3944
3945   /* PREFIX_VEX_0F72_REG_6 */
3946   {
3947     { Bad_Opcode },
3948     { Bad_Opcode },
3949     { VEX_LEN_TABLE (VEX_LEN_0F72_R_6_P_2) },
3950   },
3951
3952   /* PREFIX_VEX_0F73_REG_2 */
3953   {
3954     { Bad_Opcode },
3955     { Bad_Opcode },
3956     { VEX_LEN_TABLE (VEX_LEN_0F73_R_2_P_2) },
3957   },
3958
3959   /* PREFIX_VEX_0F73_REG_3 */
3960   {
3961     { Bad_Opcode },
3962     { Bad_Opcode },
3963     { VEX_LEN_TABLE (VEX_LEN_0F73_R_3_P_2) },
3964   },
3965
3966   /* PREFIX_VEX_0F73_REG_6 */
3967   {
3968     { Bad_Opcode },
3969     { Bad_Opcode },
3970     { VEX_LEN_TABLE (VEX_LEN_0F73_R_6_P_2) },
3971   },
3972
3973   /* PREFIX_VEX_0F73_REG_7 */
3974   {
3975     { Bad_Opcode },
3976     { Bad_Opcode },
3977     { VEX_LEN_TABLE (VEX_LEN_0F73_R_7_P_2) },
3978   },
3979
3980   /* PREFIX_VEX_0F74 */
3981   {
3982     { Bad_Opcode },
3983     { Bad_Opcode },
3984     { VEX_LEN_TABLE (VEX_LEN_0F74_P_2) },
3985   },
3986
3987   /* PREFIX_VEX_0F75 */
3988   {
3989     { Bad_Opcode },
3990     { Bad_Opcode },
3991     { VEX_LEN_TABLE (VEX_LEN_0F75_P_2) },
3992   },
3993
3994   /* PREFIX_VEX_0F76 */
3995   {
3996     { Bad_Opcode },
3997     { Bad_Opcode },
3998     { VEX_LEN_TABLE (VEX_LEN_0F76_P_2) },
3999   },
4000
4001   /* PREFIX_VEX_0F77 */
4002   {
4003     { VEX_W_TABLE (VEX_W_0F77_P_0) },
4004   },
4005
4006   /* PREFIX_VEX_0F7C */
4007   {
4008     { Bad_Opcode },
4009     { Bad_Opcode },
4010     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4011     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4012   },
4013
4014   /* PREFIX_VEX_0F7D */
4015   {
4016     { Bad_Opcode },
4017     { Bad_Opcode },
4018     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4019     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4020   },
4021
4022   /* PREFIX_VEX_0F7E */
4023   {
4024     { Bad_Opcode },
4025     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4026     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4027   },
4028
4029   /* PREFIX_VEX_0F7F */
4030   {
4031     { Bad_Opcode },
4032     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4033     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4034   },
4035
4036   /* PREFIX_VEX_0FC2 */
4037   {
4038     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4039     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4040     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4041     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4042   },
4043
4044   /* PREFIX_VEX_0FC4 */
4045   {
4046     { Bad_Opcode },
4047     { Bad_Opcode },
4048     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4049   },
4050
4051   /* PREFIX_VEX_0FC5 */
4052   {
4053     { Bad_Opcode },
4054     { Bad_Opcode },
4055     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4056   },
4057
4058   /* PREFIX_VEX_0FD0 */
4059   {
4060     { Bad_Opcode },
4061     { Bad_Opcode },
4062     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4063     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4064   },
4065
4066   /* PREFIX_VEX_0FD1 */
4067   {
4068     { Bad_Opcode },
4069     { Bad_Opcode },
4070     { VEX_LEN_TABLE (VEX_LEN_0FD1_P_2) },
4071   },
4072
4073   /* PREFIX_VEX_0FD2 */
4074   {
4075     { Bad_Opcode },
4076     { Bad_Opcode },
4077     { VEX_LEN_TABLE (VEX_LEN_0FD2_P_2) },
4078   },
4079
4080   /* PREFIX_VEX_0FD3 */
4081   {
4082     { Bad_Opcode },
4083     { Bad_Opcode },
4084     { VEX_LEN_TABLE (VEX_LEN_0FD3_P_2) },
4085   },
4086
4087   /* PREFIX_VEX_0FD4 */
4088   {
4089     { Bad_Opcode },
4090     { Bad_Opcode },
4091     { VEX_LEN_TABLE (VEX_LEN_0FD4_P_2) },
4092   },
4093
4094   /* PREFIX_VEX_0FD5 */
4095   {
4096     { Bad_Opcode },
4097     { Bad_Opcode },
4098     { VEX_LEN_TABLE (VEX_LEN_0FD5_P_2) },
4099   },
4100
4101   /* PREFIX_VEX_0FD6 */
4102   {
4103     { Bad_Opcode },
4104     { Bad_Opcode },
4105     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4106   },
4107
4108   /* PREFIX_VEX_0FD7 */
4109   {
4110     { Bad_Opcode },
4111     { Bad_Opcode },
4112     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4113   },
4114
4115   /* PREFIX_VEX_0FD8 */
4116   {
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { VEX_LEN_TABLE (VEX_LEN_0FD8_P_2) },
4120   },
4121
4122   /* PREFIX_VEX_0FD9 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { VEX_LEN_TABLE (VEX_LEN_0FD9_P_2) },
4127   },
4128
4129   /* PREFIX_VEX_0FDA */
4130   {
4131     { Bad_Opcode },
4132     { Bad_Opcode },
4133     { VEX_LEN_TABLE (VEX_LEN_0FDA_P_2) },
4134   },
4135
4136   /* PREFIX_VEX_0FDB */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { VEX_LEN_TABLE (VEX_LEN_0FDB_P_2) },
4141   },
4142
4143   /* PREFIX_VEX_0FDC */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { VEX_LEN_TABLE (VEX_LEN_0FDC_P_2) },
4148   },
4149
4150   /* PREFIX_VEX_0FDD */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { VEX_LEN_TABLE (VEX_LEN_0FDD_P_2) },
4155   },
4156
4157   /* PREFIX_VEX_0FDE */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { VEX_LEN_TABLE (VEX_LEN_0FDE_P_2) },
4162   },
4163
4164   /* PREFIX_VEX_0FDF */
4165   {
4166     { Bad_Opcode },
4167     { Bad_Opcode },
4168     { VEX_LEN_TABLE (VEX_LEN_0FDF_P_2) },
4169   },
4170
4171   /* PREFIX_VEX_0FE0 */
4172   {
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { VEX_LEN_TABLE (VEX_LEN_0FE0_P_2) },
4176   },
4177
4178   /* PREFIX_VEX_0FE1 */
4179   {
4180     { Bad_Opcode },
4181     { Bad_Opcode },
4182     { VEX_LEN_TABLE (VEX_LEN_0FE1_P_2) },
4183   },
4184
4185   /* PREFIX_VEX_0FE2 */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { VEX_LEN_TABLE (VEX_LEN_0FE2_P_2) },
4190   },
4191
4192   /* PREFIX_VEX_0FE3 */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { VEX_LEN_TABLE (VEX_LEN_0FE3_P_2) },
4197   },
4198
4199   /* PREFIX_VEX_0FE4 */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { VEX_LEN_TABLE (VEX_LEN_0FE4_P_2) },
4204   },
4205
4206   /* PREFIX_VEX_0FE5 */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { VEX_LEN_TABLE (VEX_LEN_0FE5_P_2) },
4211   },
4212
4213   /* PREFIX_VEX_0FE6 */
4214   {
4215     { Bad_Opcode },
4216     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4217     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4218     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4219   },
4220
4221   /* PREFIX_VEX_0FE7 */
4222   {
4223     { Bad_Opcode },
4224     { Bad_Opcode },
4225     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4226   },
4227
4228   /* PREFIX_VEX_0FE8 */
4229   {
4230     { Bad_Opcode },
4231     { Bad_Opcode },
4232     { VEX_LEN_TABLE (VEX_LEN_0FE8_P_2) },
4233   },
4234
4235   /* PREFIX_VEX_0FE9 */
4236   {
4237     { Bad_Opcode },
4238     { Bad_Opcode },
4239     { VEX_LEN_TABLE (VEX_LEN_0FE9_P_2) },
4240   },
4241
4242   /* PREFIX_VEX_0FEA */
4243   {
4244     { Bad_Opcode },
4245     { Bad_Opcode },
4246     { VEX_LEN_TABLE (VEX_LEN_0FEA_P_2) },
4247   },
4248
4249   /* PREFIX_VEX_0FEB */
4250   {
4251     { Bad_Opcode },
4252     { Bad_Opcode },
4253     { VEX_LEN_TABLE (VEX_LEN_0FEB_P_2) },
4254   },
4255
4256   /* PREFIX_VEX_0FEC */
4257   {
4258     { Bad_Opcode },
4259     { Bad_Opcode },
4260     { VEX_LEN_TABLE (VEX_LEN_0FEC_P_2) },
4261   },
4262
4263   /* PREFIX_VEX_0FED */
4264   {
4265     { Bad_Opcode },
4266     { Bad_Opcode },
4267     { VEX_LEN_TABLE (VEX_LEN_0FED_P_2) },
4268   },
4269
4270   /* PREFIX_VEX_0FEE */
4271   {
4272     { Bad_Opcode },
4273     { Bad_Opcode },
4274     { VEX_LEN_TABLE (VEX_LEN_0FEE_P_2) },
4275   },
4276
4277   /* PREFIX_VEX_0FEF */
4278   {
4279     { Bad_Opcode },
4280     { Bad_Opcode },
4281     { VEX_LEN_TABLE (VEX_LEN_0FEF_P_2) },
4282   },
4283
4284   /* PREFIX_VEX_0FF0 */
4285   {
4286     { Bad_Opcode },
4287     { Bad_Opcode },
4288     { Bad_Opcode },
4289     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4290   },
4291
4292   /* PREFIX_VEX_0FF1 */
4293   {
4294     { Bad_Opcode },
4295     { Bad_Opcode },
4296     { VEX_LEN_TABLE (VEX_LEN_0FF1_P_2) },
4297   },
4298
4299   /* PREFIX_VEX_0FF2 */
4300   {
4301     { Bad_Opcode },
4302     { Bad_Opcode },
4303     { VEX_LEN_TABLE (VEX_LEN_0FF2_P_2) },
4304   },
4305
4306   /* PREFIX_VEX_0FF3 */
4307   {
4308     { Bad_Opcode },
4309     { Bad_Opcode },
4310     { VEX_LEN_TABLE (VEX_LEN_0FF3_P_2) },
4311   },
4312
4313   /* PREFIX_VEX_0FF4 */
4314   {
4315     { Bad_Opcode },
4316     { Bad_Opcode },
4317     { VEX_LEN_TABLE (VEX_LEN_0FF4_P_2) },
4318   },
4319
4320   /* PREFIX_VEX_0FF5 */
4321   {
4322     { Bad_Opcode },
4323     { Bad_Opcode },
4324     { VEX_LEN_TABLE (VEX_LEN_0FF5_P_2) },
4325   },
4326
4327   /* PREFIX_VEX_0FF6 */
4328   {
4329     { Bad_Opcode },
4330     { Bad_Opcode },
4331     { VEX_LEN_TABLE (VEX_LEN_0FF6_P_2) },
4332   },
4333
4334   /* PREFIX_VEX_0FF7 */
4335   {
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
4339   },
4340
4341   /* PREFIX_VEX_0FF8 */
4342   {
4343     { Bad_Opcode },
4344     { Bad_Opcode },
4345     { VEX_LEN_TABLE (VEX_LEN_0FF8_P_2) },
4346   },
4347
4348   /* PREFIX_VEX_0FF9 */
4349   {
4350     { Bad_Opcode },
4351     { Bad_Opcode },
4352     { VEX_LEN_TABLE (VEX_LEN_0FF9_P_2) },
4353   },
4354
4355   /* PREFIX_VEX_0FFA */
4356   {
4357     { Bad_Opcode },
4358     { Bad_Opcode },
4359     { VEX_LEN_TABLE (VEX_LEN_0FFA_P_2) },
4360   },
4361
4362   /* PREFIX_VEX_0FFB */
4363   {
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { VEX_LEN_TABLE (VEX_LEN_0FFB_P_2) },
4367   },
4368
4369   /* PREFIX_VEX_0FFC */
4370   {
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { VEX_LEN_TABLE (VEX_LEN_0FFC_P_2) },
4374   },
4375
4376   /* PREFIX_VEX_0FFD */
4377   {
4378     { Bad_Opcode },
4379     { Bad_Opcode },
4380     { VEX_LEN_TABLE (VEX_LEN_0FFD_P_2) },
4381   },
4382
4383   /* PREFIX_VEX_0FFE */
4384   {
4385     { Bad_Opcode },
4386     { Bad_Opcode },
4387     { VEX_LEN_TABLE (VEX_LEN_0FFE_P_2) },
4388   },
4389
4390   /* PREFIX_VEX_0F3800 */
4391   {
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { VEX_LEN_TABLE (VEX_LEN_0F3800_P_2) },
4395   },
4396
4397   /* PREFIX_VEX_0F3801 */
4398   {
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { VEX_LEN_TABLE (VEX_LEN_0F3801_P_2) },
4402   },
4403
4404   /* PREFIX_VEX_0F3802 */
4405   {
4406     { Bad_Opcode },
4407     { Bad_Opcode },
4408     { VEX_LEN_TABLE (VEX_LEN_0F3802_P_2) },
4409   },
4410
4411   /* PREFIX_VEX_0F3803 */
4412   {
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { VEX_LEN_TABLE (VEX_LEN_0F3803_P_2) },
4416   },
4417
4418   /* PREFIX_VEX_0F3804 */
4419   {
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { VEX_LEN_TABLE (VEX_LEN_0F3804_P_2) },
4423   },
4424
4425   /* PREFIX_VEX_0F3805 */
4426   {
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { VEX_LEN_TABLE (VEX_LEN_0F3805_P_2) },
4430   },
4431
4432   /* PREFIX_VEX_0F3806 */
4433   {
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { VEX_LEN_TABLE (VEX_LEN_0F3806_P_2) },
4437   },
4438
4439   /* PREFIX_VEX_0F3807 */
4440   {
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { VEX_LEN_TABLE (VEX_LEN_0F3807_P_2) },
4444   },
4445
4446   /* PREFIX_VEX_0F3808 */
4447   {
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { VEX_LEN_TABLE (VEX_LEN_0F3808_P_2) },
4451   },
4452
4453   /* PREFIX_VEX_0F3809 */
4454   {
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { VEX_LEN_TABLE (VEX_LEN_0F3809_P_2) },
4458   },
4459
4460   /* PREFIX_VEX_0F380A */
4461   {
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { VEX_LEN_TABLE (VEX_LEN_0F380A_P_2) },
4465   },
4466
4467   /* PREFIX_VEX_0F380B */
4468   {
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { VEX_LEN_TABLE (VEX_LEN_0F380B_P_2) },
4472   },
4473
4474   /* PREFIX_VEX_0F380C */
4475   {
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
4479   },
4480
4481   /* PREFIX_VEX_0F380D */
4482   {
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
4486   },
4487
4488   /* PREFIX_VEX_0F380E */
4489   {
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
4493   },
4494
4495   /* PREFIX_VEX_0F380F */
4496   {
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
4500   },
4501
4502   /* PREFIX_VEX_0F3813 */
4503   {
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { "vcvtph2ps", { XM, EXxmmq } },
4507   },
4508
4509   /* PREFIX_VEX_0F3817 */
4510   {
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
4514   },
4515
4516   /* PREFIX_VEX_0F3818 */
4517   {
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { MOD_TABLE (MOD_VEX_0F3818_PREFIX_2) },
4521   },
4522
4523   /* PREFIX_VEX_0F3819 */
4524   {
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { MOD_TABLE (MOD_VEX_0F3819_PREFIX_2) },
4528   },
4529
4530   /* PREFIX_VEX_0F381A */
4531   {
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
4535   },
4536
4537   /* PREFIX_VEX_0F381C */
4538   {
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { VEX_LEN_TABLE (VEX_LEN_0F381C_P_2) },
4542   },
4543
4544   /* PREFIX_VEX_0F381D */
4545   {
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { VEX_LEN_TABLE (VEX_LEN_0F381D_P_2) },
4549   },
4550
4551   /* PREFIX_VEX_0F381E */
4552   {
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { VEX_LEN_TABLE (VEX_LEN_0F381E_P_2) },
4556   },
4557
4558   /* PREFIX_VEX_0F3820 */
4559   {
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { VEX_LEN_TABLE (VEX_LEN_0F3820_P_2) },
4563   },
4564
4565   /* PREFIX_VEX_0F3821 */
4566   {
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { VEX_LEN_TABLE (VEX_LEN_0F3821_P_2) },
4570   },
4571
4572   /* PREFIX_VEX_0F3822 */
4573   {
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { VEX_LEN_TABLE (VEX_LEN_0F3822_P_2) },
4577   },
4578
4579   /* PREFIX_VEX_0F3823 */
4580   {
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { VEX_LEN_TABLE (VEX_LEN_0F3823_P_2) },
4584   },
4585
4586   /* PREFIX_VEX_0F3824 */
4587   {
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { VEX_LEN_TABLE (VEX_LEN_0F3824_P_2) },
4591   },
4592
4593   /* PREFIX_VEX_0F3825 */
4594   {
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { VEX_LEN_TABLE (VEX_LEN_0F3825_P_2) },
4598   },
4599
4600   /* PREFIX_VEX_0F3828 */
4601   {
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { VEX_LEN_TABLE (VEX_LEN_0F3828_P_2) },
4605   },
4606
4607   /* PREFIX_VEX_0F3829 */
4608   {
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { VEX_LEN_TABLE (VEX_LEN_0F3829_P_2) },
4612   },
4613
4614   /* PREFIX_VEX_0F382A */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
4619   },
4620
4621   /* PREFIX_VEX_0F382B */
4622   {
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { VEX_LEN_TABLE (VEX_LEN_0F382B_P_2) },
4626   },
4627
4628   /* PREFIX_VEX_0F382C */
4629   {
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
4633   },
4634
4635   /* PREFIX_VEX_0F382D */
4636   {
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
4640   },
4641
4642   /* PREFIX_VEX_0F382E */
4643   {
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
4647   },
4648
4649   /* PREFIX_VEX_0F382F */
4650   {
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
4654   },
4655
4656   /* PREFIX_VEX_0F3830 */
4657   {
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { VEX_LEN_TABLE (VEX_LEN_0F3830_P_2) },
4661   },
4662
4663   /* PREFIX_VEX_0F3831 */
4664   {
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { VEX_LEN_TABLE (VEX_LEN_0F3831_P_2) },
4668   },
4669
4670   /* PREFIX_VEX_0F3832 */
4671   {
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { VEX_LEN_TABLE (VEX_LEN_0F3832_P_2) },
4675   },
4676
4677   /* PREFIX_VEX_0F3833 */
4678   {
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681     { VEX_LEN_TABLE (VEX_LEN_0F3833_P_2) },
4682   },
4683
4684   /* PREFIX_VEX_0F3834 */
4685   {
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { VEX_LEN_TABLE (VEX_LEN_0F3834_P_2) },
4689   },
4690
4691   /* PREFIX_VEX_0F3835 */
4692   {
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { VEX_LEN_TABLE (VEX_LEN_0F3835_P_2) },
4696   },
4697
4698   /* PREFIX_VEX_0F3837 */
4699   {
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { VEX_LEN_TABLE (VEX_LEN_0F3837_P_2) },
4703   },
4704
4705   /* PREFIX_VEX_0F3838 */
4706   {
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { VEX_LEN_TABLE (VEX_LEN_0F3838_P_2) },
4710   },
4711
4712   /* PREFIX_VEX_0F3839 */
4713   {
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { VEX_LEN_TABLE (VEX_LEN_0F3839_P_2) },
4717   },
4718
4719   /* PREFIX_VEX_0F383A */
4720   {
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { VEX_LEN_TABLE (VEX_LEN_0F383A_P_2) },
4724   },
4725
4726   /* PREFIX_VEX_0F383B */
4727   {
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { VEX_LEN_TABLE (VEX_LEN_0F383B_P_2) },
4731   },
4732
4733   /* PREFIX_VEX_0F383C */
4734   {
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { VEX_LEN_TABLE (VEX_LEN_0F383C_P_2) },
4738   },
4739
4740   /* PREFIX_VEX_0F383D */
4741   {
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { VEX_LEN_TABLE (VEX_LEN_0F383D_P_2) },
4745   },
4746
4747   /* PREFIX_VEX_0F383E */
4748   {
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     { VEX_LEN_TABLE (VEX_LEN_0F383E_P_2) },
4752   },
4753
4754   /* PREFIX_VEX_0F383F */
4755   {
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { VEX_LEN_TABLE (VEX_LEN_0F383F_P_2) },
4759   },
4760
4761   /* PREFIX_VEX_0F3840 */
4762   {
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { VEX_LEN_TABLE (VEX_LEN_0F3840_P_2) },
4766   },
4767
4768   /* PREFIX_VEX_0F3841 */
4769   {
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
4773   },
4774
4775   /* PREFIX_VEX_0F3896 */
4776   {
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4780   },
4781
4782   /* PREFIX_VEX_0F3897 */
4783   {
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4787   },
4788
4789   /* PREFIX_VEX_0F3898 */
4790   {
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { "vfmadd132p%XW", { XM, Vex, EXx } },
4794   },
4795
4796   /* PREFIX_VEX_0F3899 */
4797   {
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4801   },
4802
4803   /* PREFIX_VEX_0F389A */
4804   {
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { "vfmsub132p%XW", { XM, Vex, EXx } },
4808   },
4809
4810   /* PREFIX_VEX_0F389B */
4811   {
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4815   },
4816
4817   /* PREFIX_VEX_0F389C */
4818   {
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4822   },
4823
4824   /* PREFIX_VEX_0F389D */
4825   {
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4829   },
4830
4831   /* PREFIX_VEX_0F389E */
4832   {
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4836   },
4837
4838   /* PREFIX_VEX_0F389F */
4839   {
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4843   },
4844
4845   /* PREFIX_VEX_0F38A6 */
4846   {
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4850     { Bad_Opcode },
4851   },
4852
4853   /* PREFIX_VEX_0F38A7 */
4854   {
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4858   },
4859
4860   /* PREFIX_VEX_0F38A8 */
4861   {
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { "vfmadd213p%XW", { XM, Vex, EXx } },
4865   },
4866
4867   /* PREFIX_VEX_0F38A9 */
4868   {
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4872   },
4873
4874   /* PREFIX_VEX_0F38AA */
4875   {
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { "vfmsub213p%XW", { XM, Vex, EXx } },
4879   },
4880
4881   /* PREFIX_VEX_0F38AB */
4882   {
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4886   },
4887
4888   /* PREFIX_VEX_0F38AC */
4889   {
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4893   },
4894
4895   /* PREFIX_VEX_0F38AD */
4896   {
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4900   },
4901
4902   /* PREFIX_VEX_0F38AE */
4903   {
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4907   },
4908
4909   /* PREFIX_VEX_0F38AF */
4910   {
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4914   },
4915
4916   /* PREFIX_VEX_0F38B6 */
4917   {
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4921   },
4922
4923   /* PREFIX_VEX_0F38B7 */
4924   {
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4928   },
4929
4930   /* PREFIX_VEX_0F38B8 */
4931   {
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { "vfmadd231p%XW", { XM, Vex, EXx } },
4935   },
4936
4937   /* PREFIX_VEX_0F38B9 */
4938   {
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4942   },
4943
4944   /* PREFIX_VEX_0F38BA */
4945   {
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { "vfmsub231p%XW", { XM, Vex, EXx } },
4949   },
4950
4951   /* PREFIX_VEX_0F38BB */
4952   {
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4956   },
4957
4958   /* PREFIX_VEX_0F38BC */
4959   {
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4963   },
4964
4965   /* PREFIX_VEX_0F38BD */
4966   {
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4970   },
4971
4972   /* PREFIX_VEX_0F38BE */
4973   {
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4977   },
4978
4979   /* PREFIX_VEX_0F38BF */
4980   {
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4984   },
4985
4986   /* PREFIX_VEX_0F38DB */
4987   {
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
4991   },
4992
4993   /* PREFIX_VEX_0F38DC */
4994   {
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
4998   },
4999
5000   /* PREFIX_VEX_0F38DD */
5001   {
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5005   },
5006
5007   /* PREFIX_VEX_0F38DE */
5008   {
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5012   },
5013
5014   /* PREFIX_VEX_0F38DF */
5015   {
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5019   },
5020
5021   /* PREFIX_VEX_0F38F2 */
5022   {
5023     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5024   },
5025
5026   /* PREFIX_VEX_0F38F3_REG_1 */
5027   {
5028     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5029   },
5030
5031   /* PREFIX_VEX_0F38F3_REG_2 */
5032   {
5033     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5034   },
5035
5036   /* PREFIX_VEX_0F38F3_REG_3 */
5037   {
5038     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5039   },
5040
5041   /* PREFIX_VEX_0F38F7 */
5042   {
5043     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5044   },
5045
5046   /* PREFIX_VEX_0F3A04 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5051   },
5052
5053   /* PREFIX_VEX_0F3A05 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5058   },
5059
5060   /* PREFIX_VEX_0F3A06 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5065   },
5066
5067   /* PREFIX_VEX_0F3A08 */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5072   },
5073
5074   /* PREFIX_VEX_0F3A09 */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5079   },
5080
5081   /* PREFIX_VEX_0F3A0A */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
5086   },
5087
5088   /* PREFIX_VEX_0F3A0B */
5089   {
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
5093   },
5094
5095   /* PREFIX_VEX_0F3A0C */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
5100   },
5101
5102   /* PREFIX_VEX_0F3A0D */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
5107   },
5108
5109   /* PREFIX_VEX_0F3A0E */
5110   {
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { VEX_LEN_TABLE (VEX_LEN_0F3A0E_P_2) },
5114   },
5115
5116   /* PREFIX_VEX_0F3A0F */
5117   {
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { VEX_LEN_TABLE (VEX_LEN_0F3A0F_P_2) },
5121   },
5122
5123   /* PREFIX_VEX_0F3A14 */
5124   {
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
5128   },
5129
5130   /* PREFIX_VEX_0F3A15 */
5131   {
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
5135   },
5136
5137   /* PREFIX_VEX_0F3A16 */
5138   {
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
5142   },
5143
5144   /* PREFIX_VEX_0F3A17 */
5145   {
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
5149   },
5150
5151   /* PREFIX_VEX_0F3A18 */
5152   {
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
5156   },
5157
5158   /* PREFIX_VEX_0F3A19 */
5159   {
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
5163   },
5164
5165   /* PREFIX_VEX_0F3A1D */
5166   {
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { "vcvtps2ph", { EXxmmq, XM, Ib } },
5170   },
5171
5172   /* PREFIX_VEX_0F3A20 */
5173   {
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
5177   },
5178
5179   /* PREFIX_VEX_0F3A21 */
5180   {
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
5184   },
5185
5186   /* PREFIX_VEX_0F3A22 */
5187   {
5188     { Bad_Opcode },
5189     { Bad_Opcode },
5190     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
5191   },
5192
5193   /* PREFIX_VEX_0F3A40 */
5194   {
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
5198   },
5199
5200   /* PREFIX_VEX_0F3A41 */
5201   {
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
5205   },
5206
5207   /* PREFIX_VEX_0F3A42 */
5208   {
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     { VEX_LEN_TABLE (VEX_LEN_0F3A42_P_2) },
5212   },
5213
5214   /* PREFIX_VEX_0F3A44 */
5215   {
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
5219   },
5220
5221   /* PREFIX_VEX_0F3A48 */
5222   {
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
5226   },
5227
5228   /* PREFIX_VEX_0F3A49 */
5229   {
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
5233   },
5234
5235   /* PREFIX_VEX_0F3A4A */
5236   {
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
5240   },
5241
5242   /* PREFIX_VEX_0F3A4B */
5243   {
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
5247   },
5248
5249   /* PREFIX_VEX_0F3A4C */
5250   {
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { VEX_LEN_TABLE (VEX_LEN_0F3A4C_P_2) },
5254   },
5255
5256   /* PREFIX_VEX_0F3A5C */
5257   {
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5261   },
5262
5263   /* PREFIX_VEX_0F3A5D */
5264   {
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5268   },
5269
5270   /* PREFIX_VEX_0F3A5E */
5271   {
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5275   },
5276
5277   /* PREFIX_VEX_0F3A5F */
5278   {
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5282   },
5283
5284   /* PREFIX_VEX_0F3A60 */
5285   {
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
5289     { Bad_Opcode },
5290   },
5291
5292   /* PREFIX_VEX_0F3A61 */
5293   {
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
5297   },
5298
5299   /* PREFIX_VEX_0F3A62 */
5300   {
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
5304   },
5305
5306   /* PREFIX_VEX_0F3A63 */
5307   {
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
5311   },
5312
5313   /* PREFIX_VEX_0F3A68 */
5314   {
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5318   },
5319
5320   /* PREFIX_VEX_0F3A69 */
5321   {
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5325   },
5326
5327   /* PREFIX_VEX_0F3A6A */
5328   {
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
5332   },
5333
5334   /* PREFIX_VEX_0F3A6B */
5335   {
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
5339   },
5340
5341   /* PREFIX_VEX_0F3A6C */
5342   {
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5346   },
5347
5348   /* PREFIX_VEX_0F3A6D */
5349   {
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5353   },
5354
5355   /* PREFIX_VEX_0F3A6E */
5356   {
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
5360   },
5361
5362   /* PREFIX_VEX_0F3A6F */
5363   {
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
5367   },
5368
5369   /* PREFIX_VEX_0F3A78 */
5370   {
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5374   },
5375
5376   /* PREFIX_VEX_0F3A79 */
5377   {
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5381   },
5382
5383   /* PREFIX_VEX_0F3A7A */
5384   {
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
5388   },
5389
5390   /* PREFIX_VEX_0F3A7B */
5391   {
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
5395   },
5396
5397   /* PREFIX_VEX_0F3A7C */
5398   {
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5402     { Bad_Opcode },
5403   },
5404
5405   /* PREFIX_VEX_0F3A7D */
5406   {
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5410   },
5411
5412   /* PREFIX_VEX_0F3A7E */
5413   {
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
5417   },
5418
5419   /* PREFIX_VEX_0F3A7F */
5420   {
5421     { Bad_Opcode },
5422     { Bad_Opcode },
5423     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
5424   },
5425
5426   /* PREFIX_VEX_0F3ADF */
5427   {
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
5431   },
5432 };
5433
5434 static const struct dis386 x86_64_table[][2] = {
5435   /* X86_64_06 */
5436   {
5437     { "pushP", { es } },
5438   },
5439
5440   /* X86_64_07 */
5441   {
5442     { "popP", { es } },
5443   },
5444
5445   /* X86_64_0D */
5446   {
5447     { "pushP", { cs } },
5448   },
5449
5450   /* X86_64_16 */
5451   {
5452     { "pushP", { ss } },
5453   },
5454
5455   /* X86_64_17 */
5456   {
5457     { "popP", { ss } },
5458   },
5459
5460   /* X86_64_1E */
5461   {
5462     { "pushP", { ds } },
5463   },
5464
5465   /* X86_64_1F */
5466   {
5467     { "popP", { ds } },
5468   },
5469
5470   /* X86_64_27 */
5471   {
5472     { "daa", { XX } },
5473   },
5474
5475   /* X86_64_2F */
5476   {
5477     { "das", { XX } },
5478   },
5479
5480   /* X86_64_37 */
5481   {
5482     { "aaa", { XX } },
5483   },
5484
5485   /* X86_64_3F */
5486   {
5487     { "aas", { XX } },
5488   },
5489
5490   /* X86_64_60 */
5491   {
5492     { "pushaP", { XX } },
5493   },
5494
5495   /* X86_64_61 */
5496   {
5497     { "popaP", { XX } },
5498   },
5499
5500   /* X86_64_62 */
5501   {
5502     { MOD_TABLE (MOD_62_32BIT) },
5503   },
5504
5505   /* X86_64_63 */
5506   {
5507     { "arpl", { Ew, Gw } },
5508     { "movs{lq|xd}", { Gv, Ed } },
5509   },
5510
5511   /* X86_64_6D */
5512   {
5513     { "ins{R|}", { Yzr, indirDX } },
5514     { "ins{G|}", { Yzr, indirDX } },
5515   },
5516
5517   /* X86_64_6F */
5518   {
5519     { "outs{R|}", { indirDXr, Xz } },
5520     { "outs{G|}", { indirDXr, Xz } },
5521   },
5522
5523   /* X86_64_9A */
5524   {
5525     { "Jcall{T|}", { Ap } },
5526   },
5527
5528   /* X86_64_C4 */
5529   {
5530     { MOD_TABLE (MOD_C4_32BIT) },
5531     { VEX_C4_TABLE (VEX_0F) },
5532   },
5533
5534   /* X86_64_C5 */
5535   {
5536     { MOD_TABLE (MOD_C5_32BIT) },
5537     { VEX_C5_TABLE (VEX_0F) },
5538   },
5539
5540   /* X86_64_CE */
5541   {
5542     { "into", { XX } },
5543   },
5544
5545   /* X86_64_D4 */
5546   {
5547     { "aam", { sIb } },
5548   },
5549
5550   /* X86_64_D5 */
5551   {
5552     { "aad", { sIb } },
5553   },
5554
5555   /* X86_64_EA */
5556   {
5557     { "Jjmp{T|}", { Ap } },
5558   },
5559
5560   /* X86_64_0F01_REG_0 */
5561   {
5562     { "sgdt{Q|IQ}", { M } },
5563     { "sgdt", { M } },
5564   },
5565
5566   /* X86_64_0F01_REG_1 */
5567   {
5568     { "sidt{Q|IQ}", { M } },
5569     { "sidt", { M } },
5570   },
5571
5572   /* X86_64_0F01_REG_2 */
5573   {
5574     { "lgdt{Q|Q}", { M } },
5575     { "lgdt", { M } },
5576   },
5577
5578   /* X86_64_0F01_REG_3 */
5579   {
5580     { "lidt{Q|Q}", { M } },
5581     { "lidt", { M } },
5582   },
5583 };
5584
5585 static const struct dis386 three_byte_table[][256] = {
5586
5587   /* THREE_BYTE_0F38 */
5588   {
5589     /* 00 */
5590     { "pshufb",         { MX, EM } },
5591     { "phaddw",         { MX, EM } },
5592     { "phaddd",         { MX, EM } },
5593     { "phaddsw",        { MX, EM } },
5594     { "pmaddubsw",      { MX, EM } },
5595     { "phsubw",         { MX, EM } },
5596     { "phsubd",         { MX, EM } },
5597     { "phsubsw",        { MX, EM } },
5598     /* 08 */
5599     { "psignb",         { MX, EM } },
5600     { "psignw",         { MX, EM } },
5601     { "psignd",         { MX, EM } },
5602     { "pmulhrsw",       { MX, EM } },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     /* 10 */
5608     { PREFIX_TABLE (PREFIX_0F3810) },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { PREFIX_TABLE (PREFIX_0F3814) },
5613     { PREFIX_TABLE (PREFIX_0F3815) },
5614     { Bad_Opcode },
5615     { PREFIX_TABLE (PREFIX_0F3817) },
5616     /* 18 */
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { "pabsb",          { MX, EM } },
5622     { "pabsw",          { MX, EM } },
5623     { "pabsd",          { MX, EM } },
5624     { Bad_Opcode },
5625     /* 20 */
5626     { PREFIX_TABLE (PREFIX_0F3820) },
5627     { PREFIX_TABLE (PREFIX_0F3821) },
5628     { PREFIX_TABLE (PREFIX_0F3822) },
5629     { PREFIX_TABLE (PREFIX_0F3823) },
5630     { PREFIX_TABLE (PREFIX_0F3824) },
5631     { PREFIX_TABLE (PREFIX_0F3825) },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     /* 28 */
5635     { PREFIX_TABLE (PREFIX_0F3828) },
5636     { PREFIX_TABLE (PREFIX_0F3829) },
5637     { PREFIX_TABLE (PREFIX_0F382A) },
5638     { PREFIX_TABLE (PREFIX_0F382B) },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     /* 30 */
5644     { PREFIX_TABLE (PREFIX_0F3830) },
5645     { PREFIX_TABLE (PREFIX_0F3831) },
5646     { PREFIX_TABLE (PREFIX_0F3832) },
5647     { PREFIX_TABLE (PREFIX_0F3833) },
5648     { PREFIX_TABLE (PREFIX_0F3834) },
5649     { PREFIX_TABLE (PREFIX_0F3835) },
5650     { Bad_Opcode },
5651     { PREFIX_TABLE (PREFIX_0F3837) },
5652     /* 38 */
5653     { PREFIX_TABLE (PREFIX_0F3838) },
5654     { PREFIX_TABLE (PREFIX_0F3839) },
5655     { PREFIX_TABLE (PREFIX_0F383A) },
5656     { PREFIX_TABLE (PREFIX_0F383B) },
5657     { PREFIX_TABLE (PREFIX_0F383C) },
5658     { PREFIX_TABLE (PREFIX_0F383D) },
5659     { PREFIX_TABLE (PREFIX_0F383E) },
5660     { PREFIX_TABLE (PREFIX_0F383F) },
5661     /* 40 */
5662     { PREFIX_TABLE (PREFIX_0F3840) },
5663     { PREFIX_TABLE (PREFIX_0F3841) },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     /* 48 */
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     /* 50 */
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     /* 58 */
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     /* 60 */
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     /* 68 */
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     /* 70 */
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     /* 78 */
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     /* 80 */
5734     { PREFIX_TABLE (PREFIX_0F3880) },
5735     { PREFIX_TABLE (PREFIX_0F3881) },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     /* 88 */
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     /* 90 */
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     /* 98 */
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     /* a0 */
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     /* a8 */
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     /* b0 */
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     /* b8 */
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     /* c0 */
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     /* c8 */
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     /* d0 */
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     /* d8 */
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { PREFIX_TABLE (PREFIX_0F38DB) },
5837     { PREFIX_TABLE (PREFIX_0F38DC) },
5838     { PREFIX_TABLE (PREFIX_0F38DD) },
5839     { PREFIX_TABLE (PREFIX_0F38DE) },
5840     { PREFIX_TABLE (PREFIX_0F38DF) },
5841     /* e0 */
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     /* e8 */
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     /* f0 */
5860     { PREFIX_TABLE (PREFIX_0F38F0) },
5861     { PREFIX_TABLE (PREFIX_0F38F1) },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     /* f8 */
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877   },
5878   /* THREE_BYTE_0F3A */
5879   {
5880     /* 00 */
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     /* 08 */
5890     { PREFIX_TABLE (PREFIX_0F3A08) },
5891     { PREFIX_TABLE (PREFIX_0F3A09) },
5892     { PREFIX_TABLE (PREFIX_0F3A0A) },
5893     { PREFIX_TABLE (PREFIX_0F3A0B) },
5894     { PREFIX_TABLE (PREFIX_0F3A0C) },
5895     { PREFIX_TABLE (PREFIX_0F3A0D) },
5896     { PREFIX_TABLE (PREFIX_0F3A0E) },
5897     { "palignr",        { MX, EM, Ib } },
5898     /* 10 */
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { PREFIX_TABLE (PREFIX_0F3A14) },
5904     { PREFIX_TABLE (PREFIX_0F3A15) },
5905     { PREFIX_TABLE (PREFIX_0F3A16) },
5906     { PREFIX_TABLE (PREFIX_0F3A17) },
5907     /* 18 */
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     /* 20 */
5917     { PREFIX_TABLE (PREFIX_0F3A20) },
5918     { PREFIX_TABLE (PREFIX_0F3A21) },
5919     { PREFIX_TABLE (PREFIX_0F3A22) },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     /* 28 */
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     /* 30 */
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     /* 38 */
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     /* 40 */
5953     { PREFIX_TABLE (PREFIX_0F3A40) },
5954     { PREFIX_TABLE (PREFIX_0F3A41) },
5955     { PREFIX_TABLE (PREFIX_0F3A42) },
5956     { Bad_Opcode },
5957     { PREFIX_TABLE (PREFIX_0F3A44) },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     /* 48 */
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     /* 50 */
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     /* 58 */
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     /* 60 */
5989     { PREFIX_TABLE (PREFIX_0F3A60) },
5990     { PREFIX_TABLE (PREFIX_0F3A61) },
5991     { PREFIX_TABLE (PREFIX_0F3A62) },
5992     { PREFIX_TABLE (PREFIX_0F3A63) },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     /* 68 */
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     /* 70 */
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     /* 78 */
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     /* 80 */
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     /* 88 */
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     /* 90 */
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     /* 98 */
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     /* a0 */
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     /* a8 */
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     /* b0 */
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     /* b8 */
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     /* c0 */
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     /* c8 */
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     /* d0 */
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     /* d8 */
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { PREFIX_TABLE (PREFIX_0F3ADF) },
6132     /* e0 */
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { Bad_Opcode },
6141     /* e8 */
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     /* f0 */
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { Bad_Opcode },
6159     /* f8 */
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168   },
6169
6170   /* THREE_BYTE_0F7A */
6171   {
6172     /* 00 */
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     /* 08 */
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     /* 10 */
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     /* 18 */
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     /* 20 */
6209     { "ptest",          { XX } },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     /* 28 */
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     /* 30 */
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     /* 38 */
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     /* 40 */
6245     { Bad_Opcode },
6246     { "phaddbw",        { XM, EXq } },
6247     { "phaddbd",        { XM, EXq } },
6248     { "phaddbq",        { XM, EXq } },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { "phaddwd",        { XM, EXq } },
6252     { "phaddwq",        { XM, EXq } },
6253     /* 48 */
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { "phadddq",        { XM, EXq } },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     /* 50 */
6263     { Bad_Opcode },
6264     { "phaddubw",       { XM, EXq } },
6265     { "phaddubd",       { XM, EXq } },
6266     { "phaddubq",       { XM, EXq } },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { "phadduwd",       { XM, EXq } },
6270     { "phadduwq",       { XM, EXq } },
6271     /* 58 */
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { "phaddudq",       { XM, EXq } },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     /* 60 */
6281     { Bad_Opcode },
6282     { "phsubbw",        { XM, EXq } },
6283     { "phsubbd",        { XM, EXq } },
6284     { "phsubbq",        { XM, EXq } },
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     /* 68 */
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     /* 70 */
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     /* 78 */
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     /* 80 */
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     /* 88 */
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     /* 90 */
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     /* 98 */
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     /* a0 */
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     /* a8 */
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     /* b0 */
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     /* b8 */
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     /* c0 */
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     /* c8 */
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     /* d0 */
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     /* d8 */
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     /* e0 */
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     /* e8 */
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     /* f0 */
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     /* f8 */
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460   },
6461 };
6462
6463 static const struct dis386 xop_table[][256] = {
6464   /* XOP_08 */
6465   {
6466     /* 00 */
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     /* 08 */
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     /* 10 */
6485     { "bextr",  { Gv, Ev, Iq } },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     /* 18 */
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     /* 20 */
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     /* 28 */
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     /* 30 */
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     /* 38 */
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     /* 40 */
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     /* 48 */
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     /* 50 */
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     /* 58 */
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     /* 60 */
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     /* 68 */
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     /* 70 */
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     /* 78 */
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     /* 80 */
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6617     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6618     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6619     /* 88 */
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6627     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6628     /* 90 */
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6635     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6636     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6637     /* 98 */
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6645     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6646     /* a0 */
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6650     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6654     { Bad_Opcode },
6655     /* a8 */
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     /* b0 */
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6672     { Bad_Opcode },
6673     /* b8 */
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     /* c0 */
6683     { "vprotb",         { XM, Vex_2src_1, Ib } },
6684     { "vprotw",         { XM, Vex_2src_1, Ib } },
6685     { "vprotd",         { XM, Vex_2src_1, Ib } },
6686     { "vprotq",         { XM, Vex_2src_1, Ib } },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     /* c8 */
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { "vpcomb",         { XM, Vex128, EXx, Ib } },
6697     { "vpcomw",         { XM, Vex128, EXx, Ib } },
6698     { "vpcomd",         { XM, Vex128, EXx, Ib } },
6699     { "vpcomq",         { XM, Vex128, EXx, Ib } },
6700     /* d0 */
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     /* d8 */
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     /* e0 */
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     /* e8 */
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { "vpcomub",        { XM, Vex128, EXx, Ib } },
6733     { "vpcomuw",        { XM, Vex128, EXx, Ib } },
6734     { "vpcomud",        { XM, Vex128, EXx, Ib } },
6735     { "vpcomuq",        { XM, Vex128, EXx, Ib } },
6736     /* f0 */
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     /* f8 */
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754   },
6755   /* XOP_09 */
6756   {
6757     /* 00 */
6758     { Bad_Opcode },
6759     { REG_TABLE (REG_XOP_TBM_01) },
6760     { REG_TABLE (REG_XOP_TBM_02) },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     /* 08 */
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     /* 10 */
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { REG_TABLE (REG_XOP_LWPCB) },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     /* 18 */
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     /* 20 */
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     /* 28 */
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     /* 30 */
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     /* 38 */
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     /* 40 */
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     /* 48 */
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     /* 50 */
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     /* 58 */
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     /* 60 */
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     /* 68 */
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     /* 70 */
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     /* 78 */
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     /* 80 */
6902     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
6903     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
6904     { "vfrczss",        { XM, EXd } },
6905     { "vfrczsd",        { XM, EXq } },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     /* 88 */
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     /* 90 */
6920     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
6921     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
6922     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
6923     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
6924     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
6925     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
6926     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
6927     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
6928     /* 98 */
6929     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
6930     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
6931     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
6932     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     /* a0 */
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     /* a8 */
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     /* b0 */
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     /* b8 */
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     /* c0 */
6974     { Bad_Opcode },
6975     { "vphaddbw",       { XM, EXxmm } },
6976     { "vphaddbd",       { XM, EXxmm } },
6977     { "vphaddbq",       { XM, EXxmm } },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { "vphaddwd",       { XM, EXxmm } },
6981     { "vphaddwq",       { XM, EXxmm } },
6982     /* c8 */
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { "vphadddq",       { XM, EXxmm } },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     /* d0 */
6992     { Bad_Opcode },
6993     { "vphaddubw",      { XM, EXxmm } },
6994     { "vphaddubd",      { XM, EXxmm } },
6995     { "vphaddubq",      { XM, EXxmm } },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { "vphadduwd",      { XM, EXxmm } },
6999     { "vphadduwq",      { XM, EXxmm } },
7000     /* d8 */
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { "vphaddudq",      { XM, EXxmm } },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     /* e0 */
7010     { Bad_Opcode },
7011     { "vphsubbw",       { XM, EXxmm } },
7012     { "vphsubwd",       { XM, EXxmm } },
7013     { "vphsubdq",       { XM, EXxmm } },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     /* e8 */
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     /* f0 */
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     /* f8 */
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045   },
7046   /* XOP_0A */
7047   {
7048     /* 00 */
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     /* 08 */
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     /* 10 */
7067     { "bextr",  { Gv, Ev, Iq } },
7068     { Bad_Opcode },
7069     { REG_TABLE (REG_XOP_LWP) },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     /* 18 */
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     /* 20 */
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     /* 28 */
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     /* 30 */
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     /* 38 */
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     /* 40 */
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     /* 48 */
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     /* 50 */
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     /* 58 */
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     /* 60 */
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     /* 68 */
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     /* 70 */
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     /* 78 */
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     /* 80 */
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     /* 88 */
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     /* 90 */
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     /* 98 */
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     /* a0 */
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     /* a8 */
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     /* b0 */
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     /* b8 */
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     /* c0 */
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     /* c8 */
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     /* d0 */
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     /* d8 */
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     /* e0 */
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     /* e8 */
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     /* f0 */
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     /* f8 */
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336   },
7337 };
7338
7339 static const struct dis386 vex_table[][256] = {
7340   /* VEX_0F */
7341   {
7342     /* 00 */
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     /* 08 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     /* 10 */
7361     { PREFIX_TABLE (PREFIX_VEX_0F10) },
7362     { PREFIX_TABLE (PREFIX_VEX_0F11) },
7363     { PREFIX_TABLE (PREFIX_VEX_0F12) },
7364     { MOD_TABLE (MOD_VEX_0F13) },
7365     { VEX_W_TABLE (VEX_W_0F14) },
7366     { VEX_W_TABLE (VEX_W_0F15) },
7367     { PREFIX_TABLE (PREFIX_VEX_0F16) },
7368     { MOD_TABLE (MOD_VEX_0F17) },
7369     /* 18 */
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     /* 20 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     /* 28 */
7388     { VEX_W_TABLE (VEX_W_0F28) },
7389     { VEX_W_TABLE (VEX_W_0F29) },
7390     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
7391     { MOD_TABLE (MOD_VEX_0F2B) },
7392     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
7393     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
7394     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
7395     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
7396     /* 30 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     /* 38 */
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     /* 40 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     /* 48 */
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     /* 50 */
7433     { MOD_TABLE (MOD_VEX_0F50) },
7434     { PREFIX_TABLE (PREFIX_VEX_0F51) },
7435     { PREFIX_TABLE (PREFIX_VEX_0F52) },
7436     { PREFIX_TABLE (PREFIX_VEX_0F53) },
7437     { "vandpX",         { XM, Vex, EXx } },
7438     { "vandnpX",        { XM, Vex, EXx } },
7439     { "vorpX",          { XM, Vex, EXx } },
7440     { "vxorpX",         { XM, Vex, EXx } },
7441     /* 58 */
7442     { PREFIX_TABLE (PREFIX_VEX_0F58) },
7443     { PREFIX_TABLE (PREFIX_VEX_0F59) },
7444     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
7445     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
7446     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
7447     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
7448     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
7449     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
7450     /* 60 */
7451     { PREFIX_TABLE (PREFIX_VEX_0F60) },
7452     { PREFIX_TABLE (PREFIX_VEX_0F61) },
7453     { PREFIX_TABLE (PREFIX_VEX_0F62) },
7454     { PREFIX_TABLE (PREFIX_VEX_0F63) },
7455     { PREFIX_TABLE (PREFIX_VEX_0F64) },
7456     { PREFIX_TABLE (PREFIX_VEX_0F65) },
7457     { PREFIX_TABLE (PREFIX_VEX_0F66) },
7458     { PREFIX_TABLE (PREFIX_VEX_0F67) },
7459     /* 68 */
7460     { PREFIX_TABLE (PREFIX_VEX_0F68) },
7461     { PREFIX_TABLE (PREFIX_VEX_0F69) },
7462     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
7463     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
7464     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
7465     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
7466     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
7467     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
7468     /* 70 */
7469     { PREFIX_TABLE (PREFIX_VEX_0F70) },
7470     { REG_TABLE (REG_VEX_0F71) },
7471     { REG_TABLE (REG_VEX_0F72) },
7472     { REG_TABLE (REG_VEX_0F73) },
7473     { PREFIX_TABLE (PREFIX_VEX_0F74) },
7474     { PREFIX_TABLE (PREFIX_VEX_0F75) },
7475     { PREFIX_TABLE (PREFIX_VEX_0F76) },
7476     { PREFIX_TABLE (PREFIX_VEX_0F77) },
7477     /* 78 */
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
7483     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
7484     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
7485     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
7486     /* 80 */
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     /* 88 */
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     /* 90 */
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     /* 98 */
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     /* a0 */
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     /* a8 */
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { REG_TABLE (REG_VEX_0FAE) },
7539     { Bad_Opcode },
7540     /* b0 */
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     /* b8 */
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     /* c0 */
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
7562     { Bad_Opcode },
7563     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
7564     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
7565     { "vshufpX",        { XM, Vex, EXx, Ib } },
7566     { Bad_Opcode },
7567     /* c8 */
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     /* d0 */
7577     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
7578     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
7579     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
7580     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
7581     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
7582     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
7583     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
7584     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
7585     /* d8 */
7586     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
7587     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
7588     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
7589     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
7590     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
7591     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
7592     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
7593     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
7594     /* e0 */
7595     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
7596     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
7597     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
7598     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
7599     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
7600     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
7601     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
7602     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
7603     /* e8 */
7604     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
7605     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
7606     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
7607     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
7608     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
7609     { PREFIX_TABLE (PREFIX_VEX_0FED) },
7610     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
7611     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
7612     /* f0 */
7613     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
7614     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
7615     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
7616     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
7617     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
7618     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
7619     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
7620     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
7621     /* f8 */
7622     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
7623     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
7624     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
7625     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
7626     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
7627     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
7628     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
7629     { Bad_Opcode },
7630   },
7631   /* VEX_0F38 */
7632   {
7633     /* 00 */
7634     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
7635     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
7636     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
7637     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
7638     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
7639     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
7640     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
7641     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
7642     /* 08 */
7643     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
7644     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
7645     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
7646     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
7647     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
7648     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
7649     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
7650     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
7651     /* 10 */
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
7660     /* 18 */
7661     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
7662     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
7663     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
7664     { Bad_Opcode },
7665     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
7666     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
7667     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
7668     { Bad_Opcode },
7669     /* 20 */
7670     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
7671     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
7672     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
7673     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
7674     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
7675     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     /* 28 */
7679     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
7680     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
7681     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
7682     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
7683     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
7684     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
7685     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
7686     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
7687     /* 30 */
7688     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
7689     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
7690     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
7691     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
7692     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
7693     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
7694     { Bad_Opcode },
7695     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
7696     /* 38 */
7697     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
7698     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
7699     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
7700     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
7701     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
7702     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
7703     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
7704     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
7705     /* 40 */
7706     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
7707     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     /* 48 */
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     /* 50 */
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     /* 58 */
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     /* 60 */
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     /* 68 */
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     /* 70 */
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     /* 78 */
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     /* 80 */
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     /* 88 */
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     /* 90 */
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
7803     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
7804     /* 98 */
7805     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
7806     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
7807     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
7808     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
7809     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
7810     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
7811     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
7812     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
7813     /* a0 */
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
7821     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
7822     /* a8 */
7823     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
7824     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
7825     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
7826     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
7827     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
7828     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
7829     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
7830     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
7831     /* b0 */
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
7839     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
7840     /* b8 */
7841     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
7842     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
7843     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
7844     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
7845     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
7846     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
7847     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
7848     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
7849     /* c0 */
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     /* c8 */
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     /* d0 */
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     /* d8 */
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
7881     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
7882     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
7883     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
7884     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
7885     /* e0 */
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     /* e8 */
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     /* f0 */
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
7907     { REG_TABLE (REG_VEX_0F38F3) },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
7912     /* f8 */
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921   },
7922   /* VEX_0F3A */
7923   {
7924     /* 00 */
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
7930     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
7931     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
7932     { Bad_Opcode },
7933     /* 08 */
7934     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
7935     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
7936     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
7937     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
7938     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
7939     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
7940     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
7941     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
7942     /* 10 */
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
7948     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
7949     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
7950     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
7951     /* 18 */
7952     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
7953     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     /* 20 */
7961     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
7962     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
7963     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     /* 28 */
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     /* 30 */
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     /* 38 */
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     /* 40 */
7997     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
7998     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
7999     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8000     { Bad_Opcode },
8001     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     /* 48 */
8006     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8007     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8008     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8009     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8010     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     /* 50 */
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     /* 58 */
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8029     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8030     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8031     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8032     /* 60 */
8033     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8034     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8035     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8036     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     /* 68 */
8042     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
8043     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
8044     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
8045     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
8046     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
8047     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
8048     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
8049     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
8050     /* 70 */
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     /* 78 */
8060     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
8061     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
8062     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
8063     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
8064     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
8065     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
8066     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
8067     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
8068     /* 80 */
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     /* 88 */
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     /* 90 */
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     /* 98 */
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     /* a0 */
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     /* a8 */
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     /* b0 */
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     /* b8 */
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     /* c0 */
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     /* c8 */
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     /* d0 */
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     /* d8 */
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
8176     /* e0 */
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     /* e8 */
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     /* f0 */
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     /* f8 */
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212   },
8213 };
8214
8215 static const struct dis386 vex_len_table[][2] = {
8216   /* VEX_LEN_0F10_P_1 */
8217   {
8218     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8219     { VEX_W_TABLE (VEX_W_0F10_P_1) },
8220   },
8221
8222   /* VEX_LEN_0F10_P_3 */
8223   {
8224     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8225     { VEX_W_TABLE (VEX_W_0F10_P_3) },
8226   },
8227
8228   /* VEX_LEN_0F11_P_1 */
8229   {
8230     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8231     { VEX_W_TABLE (VEX_W_0F11_P_1) },
8232   },
8233
8234   /* VEX_LEN_0F11_P_3 */
8235   {
8236     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8237     { VEX_W_TABLE (VEX_W_0F11_P_3) },
8238   },
8239
8240   /* VEX_LEN_0F12_P_0_M_0 */
8241   {
8242     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
8243   },
8244
8245   /* VEX_LEN_0F12_P_0_M_1 */
8246   {
8247     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
8248   },
8249
8250   /* VEX_LEN_0F12_P_2 */
8251   {
8252     { VEX_W_TABLE (VEX_W_0F12_P_2) },
8253   },
8254
8255   /* VEX_LEN_0F13_M_0 */
8256   {
8257     { VEX_W_TABLE (VEX_W_0F13_M_0) },
8258   },
8259
8260   /* VEX_LEN_0F16_P_0_M_0 */
8261   {
8262     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
8263   },
8264
8265   /* VEX_LEN_0F16_P_0_M_1 */
8266   {
8267     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
8268   },
8269
8270   /* VEX_LEN_0F16_P_2 */
8271   {
8272     { VEX_W_TABLE (VEX_W_0F16_P_2) },
8273   },
8274
8275   /* VEX_LEN_0F17_M_0 */
8276   {
8277     { VEX_W_TABLE (VEX_W_0F17_M_0) },
8278   },
8279
8280   /* VEX_LEN_0F2A_P_1 */
8281   {
8282     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8283     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8284   },
8285
8286   /* VEX_LEN_0F2A_P_3 */
8287   {
8288     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8289     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8290   },
8291
8292   /* VEX_LEN_0F2C_P_1 */
8293   {
8294     { "vcvttss2siY",    { Gv, EXdScalar } },
8295     { "vcvttss2siY",    { Gv, EXdScalar } },
8296   },
8297
8298   /* VEX_LEN_0F2C_P_3 */
8299   {
8300     { "vcvttsd2siY",    { Gv, EXqScalar } },
8301     { "vcvttsd2siY",    { Gv, EXqScalar } },
8302   },
8303
8304   /* VEX_LEN_0F2D_P_1 */
8305   {
8306     { "vcvtss2siY",     { Gv, EXdScalar } },
8307     { "vcvtss2siY",     { Gv, EXdScalar } },
8308   },
8309
8310   /* VEX_LEN_0F2D_P_3 */
8311   {
8312     { "vcvtsd2siY",     { Gv, EXqScalar } },
8313     { "vcvtsd2siY",     { Gv, EXqScalar } },
8314   },
8315
8316   /* VEX_LEN_0F2E_P_0 */
8317   {
8318     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8319     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8320   },
8321
8322   /* VEX_LEN_0F2E_P_2 */
8323   {
8324     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8325     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8326   },
8327
8328   /* VEX_LEN_0F2F_P_0 */
8329   {
8330     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8331     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8332   },
8333
8334   /* VEX_LEN_0F2F_P_2 */
8335   {
8336     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8337     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8338   },
8339
8340   /* VEX_LEN_0F51_P_1 */
8341   {
8342     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8343     { VEX_W_TABLE (VEX_W_0F51_P_1) },
8344   },
8345
8346   /* VEX_LEN_0F51_P_3 */
8347   {
8348     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8349     { VEX_W_TABLE (VEX_W_0F51_P_3) },
8350   },
8351
8352   /* VEX_LEN_0F52_P_1 */
8353   {
8354     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8355     { VEX_W_TABLE (VEX_W_0F52_P_1) },
8356   },
8357
8358   /* VEX_LEN_0F53_P_1 */
8359   {
8360     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8361     { VEX_W_TABLE (VEX_W_0F53_P_1) },
8362   },
8363
8364   /* VEX_LEN_0F58_P_1 */
8365   {
8366     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8367     { VEX_W_TABLE (VEX_W_0F58_P_1) },
8368   },
8369
8370   /* VEX_LEN_0F58_P_3 */
8371   {
8372     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8373     { VEX_W_TABLE (VEX_W_0F58_P_3) },
8374   },
8375
8376   /* VEX_LEN_0F59_P_1 */
8377   {
8378     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8379     { VEX_W_TABLE (VEX_W_0F59_P_1) },
8380   },
8381
8382   /* VEX_LEN_0F59_P_3 */
8383   {
8384     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8385     { VEX_W_TABLE (VEX_W_0F59_P_3) },
8386   },
8387
8388   /* VEX_LEN_0F5A_P_1 */
8389   {
8390     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8391     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8392   },
8393
8394   /* VEX_LEN_0F5A_P_3 */
8395   {
8396     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8397     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8398   },
8399
8400   /* VEX_LEN_0F5C_P_1 */
8401   {
8402     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8403     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8404   },
8405
8406   /* VEX_LEN_0F5C_P_3 */
8407   {
8408     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8409     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8410   },
8411
8412   /* VEX_LEN_0F5D_P_1 */
8413   {
8414     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8415     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8416   },
8417
8418   /* VEX_LEN_0F5D_P_3 */
8419   {
8420     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8421     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8422   },
8423
8424   /* VEX_LEN_0F5E_P_1 */
8425   {
8426     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8427     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8428   },
8429
8430   /* VEX_LEN_0F5E_P_3 */
8431   {
8432     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8433     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8434   },
8435
8436   /* VEX_LEN_0F5F_P_1 */
8437   {
8438     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8439     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8440   },
8441
8442   /* VEX_LEN_0F5F_P_3 */
8443   {
8444     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8445     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8446   },
8447
8448   /* VEX_LEN_0F60_P_2 */
8449   {
8450     { VEX_W_TABLE (VEX_W_0F60_P_2) },
8451   },
8452
8453   /* VEX_LEN_0F61_P_2 */
8454   {
8455     { VEX_W_TABLE (VEX_W_0F61_P_2) },
8456   },
8457
8458   /* VEX_LEN_0F62_P_2 */
8459   {
8460     { VEX_W_TABLE (VEX_W_0F62_P_2) },
8461   },
8462
8463   /* VEX_LEN_0F63_P_2 */
8464   {
8465     { VEX_W_TABLE (VEX_W_0F63_P_2) },
8466   },
8467
8468   /* VEX_LEN_0F64_P_2 */
8469   {
8470     { VEX_W_TABLE (VEX_W_0F64_P_2) },
8471   },
8472
8473   /* VEX_LEN_0F65_P_2 */
8474   {
8475     { VEX_W_TABLE (VEX_W_0F65_P_2) },
8476   },
8477
8478   /* VEX_LEN_0F66_P_2 */
8479   {
8480     { VEX_W_TABLE (VEX_W_0F66_P_2) },
8481   },
8482
8483   /* VEX_LEN_0F67_P_2 */
8484   {
8485     { VEX_W_TABLE (VEX_W_0F67_P_2) },
8486   },
8487
8488   /* VEX_LEN_0F68_P_2 */
8489   {
8490     { VEX_W_TABLE (VEX_W_0F68_P_2) },
8491   },
8492
8493   /* VEX_LEN_0F69_P_2 */
8494   {
8495     { VEX_W_TABLE (VEX_W_0F69_P_2) },
8496   },
8497
8498   /* VEX_LEN_0F6A_P_2 */
8499   {
8500     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
8501   },
8502
8503   /* VEX_LEN_0F6B_P_2 */
8504   {
8505     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
8506   },
8507
8508   /* VEX_LEN_0F6C_P_2 */
8509   {
8510     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
8511   },
8512
8513   /* VEX_LEN_0F6D_P_2 */
8514   {
8515     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
8516   },
8517
8518   /* VEX_LEN_0F6E_P_2 */
8519   {
8520     { "vmovK",          { XMScalar, Edq } },
8521     { "vmovK",          { XMScalar, Edq } },
8522   },
8523
8524   /* VEX_LEN_0F70_P_1 */
8525   {
8526     { VEX_W_TABLE (VEX_W_0F70_P_1) },
8527   },
8528
8529   /* VEX_LEN_0F70_P_2 */
8530   {
8531     { VEX_W_TABLE (VEX_W_0F70_P_2) },
8532   },
8533
8534   /* VEX_LEN_0F70_P_3 */
8535   {
8536     { VEX_W_TABLE (VEX_W_0F70_P_3) },
8537   },
8538
8539   /* VEX_LEN_0F71_R_2_P_2 */
8540   {
8541     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
8542   },
8543
8544   /* VEX_LEN_0F71_R_4_P_2 */
8545   {
8546     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
8547   },
8548
8549   /* VEX_LEN_0F71_R_6_P_2 */
8550   {
8551     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
8552   },
8553
8554   /* VEX_LEN_0F72_R_2_P_2 */
8555   {
8556     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
8557   },
8558
8559   /* VEX_LEN_0F72_R_4_P_2 */
8560   {
8561     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
8562   },
8563
8564   /* VEX_LEN_0F72_R_6_P_2 */
8565   {
8566     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
8567   },
8568
8569   /* VEX_LEN_0F73_R_2_P_2 */
8570   {
8571     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
8572   },
8573
8574   /* VEX_LEN_0F73_R_3_P_2 */
8575   {
8576     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
8577   },
8578
8579   /* VEX_LEN_0F73_R_6_P_2 */
8580   {
8581     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
8582   },
8583
8584   /* VEX_LEN_0F73_R_7_P_2 */
8585   {
8586     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
8587   },
8588
8589   /* VEX_LEN_0F74_P_2 */
8590   {
8591     { VEX_W_TABLE (VEX_W_0F74_P_2) },
8592   },
8593
8594   /* VEX_LEN_0F75_P_2 */
8595   {
8596     { VEX_W_TABLE (VEX_W_0F75_P_2) },
8597   },
8598
8599   /* VEX_LEN_0F76_P_2 */
8600   {
8601     { VEX_W_TABLE (VEX_W_0F76_P_2) },
8602   },
8603
8604   /* VEX_LEN_0F7E_P_1 */
8605   {
8606     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8607     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8608   },
8609
8610   /* VEX_LEN_0F7E_P_2 */
8611   {
8612     { "vmovK",          { Edq, XMScalar } },
8613     { "vmovK",          { Edq, XMScalar } },
8614   },
8615
8616   /* VEX_LEN_0FAE_R_2_M_0 */
8617   {
8618     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
8619   },
8620
8621   /* VEX_LEN_0FAE_R_3_M_0 */
8622   {
8623     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
8624   },
8625
8626   /* VEX_LEN_0FC2_P_1 */
8627   {
8628     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8629     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8630   },
8631
8632   /* VEX_LEN_0FC2_P_3 */
8633   {
8634     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8635     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8636   },
8637
8638   /* VEX_LEN_0FC4_P_2 */
8639   {
8640     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
8641   },
8642
8643   /* VEX_LEN_0FC5_P_2 */
8644   {
8645     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
8646   },
8647
8648   /* VEX_LEN_0FD1_P_2 */
8649   {
8650     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
8651   },
8652
8653   /* VEX_LEN_0FD2_P_2 */
8654   {
8655     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
8656   },
8657
8658   /* VEX_LEN_0FD3_P_2 */
8659   {
8660     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
8661   },
8662
8663   /* VEX_LEN_0FD4_P_2 */
8664   {
8665     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
8666   },
8667
8668   /* VEX_LEN_0FD5_P_2 */
8669   {
8670     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
8671   },
8672
8673   /* VEX_LEN_0FD6_P_2 */
8674   {
8675     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8676     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8677   },
8678
8679   /* VEX_LEN_0FD7_P_2_M_1 */
8680   {
8681     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
8682   },
8683
8684   /* VEX_LEN_0FD8_P_2 */
8685   {
8686     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
8687   },
8688
8689   /* VEX_LEN_0FD9_P_2 */
8690   {
8691     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
8692   },
8693
8694   /* VEX_LEN_0FDA_P_2 */
8695   {
8696     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
8697   },
8698
8699   /* VEX_LEN_0FDB_P_2 */
8700   {
8701     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
8702   },
8703
8704   /* VEX_LEN_0FDC_P_2 */
8705   {
8706     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
8707   },
8708
8709   /* VEX_LEN_0FDD_P_2 */
8710   {
8711     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
8712   },
8713
8714   /* VEX_LEN_0FDE_P_2 */
8715   {
8716     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
8717   },
8718
8719   /* VEX_LEN_0FDF_P_2 */
8720   {
8721     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
8722   },
8723
8724   /* VEX_LEN_0FE0_P_2 */
8725   {
8726     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
8727   },
8728
8729   /* VEX_LEN_0FE1_P_2 */
8730   {
8731     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
8732   },
8733
8734   /* VEX_LEN_0FE2_P_2 */
8735   {
8736     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
8737   },
8738
8739   /* VEX_LEN_0FE3_P_2 */
8740   {
8741     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
8742   },
8743
8744   /* VEX_LEN_0FE4_P_2 */
8745   {
8746     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
8747   },
8748
8749   /* VEX_LEN_0FE5_P_2 */
8750   {
8751     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
8752   },
8753
8754   /* VEX_LEN_0FE8_P_2 */
8755   {
8756     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
8757   },
8758
8759   /* VEX_LEN_0FE9_P_2 */
8760   {
8761     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
8762   },
8763
8764   /* VEX_LEN_0FEA_P_2 */
8765   {
8766     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
8767   },
8768
8769   /* VEX_LEN_0FEB_P_2 */
8770   {
8771     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
8772   },
8773
8774   /* VEX_LEN_0FEC_P_2 */
8775   {
8776     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
8777   },
8778
8779   /* VEX_LEN_0FED_P_2 */
8780   {
8781     { VEX_W_TABLE (VEX_W_0FED_P_2) },
8782   },
8783
8784   /* VEX_LEN_0FEE_P_2 */
8785   {
8786     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
8787   },
8788
8789   /* VEX_LEN_0FEF_P_2 */
8790   {
8791     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
8792   },
8793
8794   /* VEX_LEN_0FF1_P_2 */
8795   {
8796     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
8797   },
8798
8799   /* VEX_LEN_0FF2_P_2 */
8800   {
8801     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
8802   },
8803
8804   /* VEX_LEN_0FF3_P_2 */
8805   {
8806     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
8807   },
8808
8809   /* VEX_LEN_0FF4_P_2 */
8810   {
8811     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
8812   },
8813
8814   /* VEX_LEN_0FF5_P_2 */
8815   {
8816     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
8817   },
8818
8819   /* VEX_LEN_0FF6_P_2 */
8820   {
8821     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
8822   },
8823
8824   /* VEX_LEN_0FF7_P_2 */
8825   {
8826     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
8827   },
8828
8829   /* VEX_LEN_0FF8_P_2 */
8830   {
8831     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
8832   },
8833
8834   /* VEX_LEN_0FF9_P_2 */
8835   {
8836     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
8837   },
8838
8839   /* VEX_LEN_0FFA_P_2 */
8840   {
8841     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
8842   },
8843
8844   /* VEX_LEN_0FFB_P_2 */
8845   {
8846     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
8847   },
8848
8849   /* VEX_LEN_0FFC_P_2 */
8850   {
8851     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
8852   },
8853
8854   /* VEX_LEN_0FFD_P_2 */
8855   {
8856     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
8857   },
8858
8859   /* VEX_LEN_0FFE_P_2 */
8860   {
8861     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
8862   },
8863
8864   /* VEX_LEN_0F3800_P_2 */
8865   {
8866     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
8867   },
8868
8869   /* VEX_LEN_0F3801_P_2 */
8870   {
8871     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
8872   },
8873
8874   /* VEX_LEN_0F3802_P_2 */
8875   {
8876     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
8877   },
8878
8879   /* VEX_LEN_0F3803_P_2 */
8880   {
8881     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
8882   },
8883
8884   /* VEX_LEN_0F3804_P_2 */
8885   {
8886     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
8887   },
8888
8889   /* VEX_LEN_0F3805_P_2 */
8890   {
8891     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
8892   },
8893
8894   /* VEX_LEN_0F3806_P_2 */
8895   {
8896     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
8897   },
8898
8899   /* VEX_LEN_0F3807_P_2 */
8900   {
8901     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
8902   },
8903
8904   /* VEX_LEN_0F3808_P_2 */
8905   {
8906     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
8907   },
8908
8909   /* VEX_LEN_0F3809_P_2 */
8910   {
8911     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
8912   },
8913
8914   /* VEX_LEN_0F380A_P_2 */
8915   {
8916     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
8917   },
8918
8919   /* VEX_LEN_0F380B_P_2 */
8920   {
8921     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
8922   },
8923
8924   /* VEX_LEN_0F3819_P_2_M_0 */
8925   {
8926     { Bad_Opcode },
8927     { VEX_W_TABLE (VEX_W_0F3819_P_2_M_0) },
8928   },
8929
8930   /* VEX_LEN_0F381A_P_2_M_0 */
8931   {
8932     { Bad_Opcode },
8933     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
8934   },
8935
8936   /* VEX_LEN_0F381C_P_2 */
8937   {
8938     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
8939   },
8940
8941   /* VEX_LEN_0F381D_P_2 */
8942   {
8943     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
8944   },
8945
8946   /* VEX_LEN_0F381E_P_2 */
8947   {
8948     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
8949   },
8950
8951   /* VEX_LEN_0F3820_P_2 */
8952   {
8953     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
8954   },
8955
8956   /* VEX_LEN_0F3821_P_2 */
8957   {
8958     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
8959   },
8960
8961   /* VEX_LEN_0F3822_P_2 */
8962   {
8963     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
8964   },
8965
8966   /* VEX_LEN_0F3823_P_2 */
8967   {
8968     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
8969   },
8970
8971   /* VEX_LEN_0F3824_P_2 */
8972   {
8973     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
8974   },
8975
8976   /* VEX_LEN_0F3825_P_2 */
8977   {
8978     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
8979   },
8980
8981   /* VEX_LEN_0F3828_P_2 */
8982   {
8983     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
8984   },
8985
8986   /* VEX_LEN_0F3829_P_2 */
8987   {
8988     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
8989   },
8990
8991   /* VEX_LEN_0F382A_P_2_M_0 */
8992   {
8993     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
8994   },
8995
8996   /* VEX_LEN_0F382B_P_2 */
8997   {
8998     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
8999   },
9000
9001   /* VEX_LEN_0F3830_P_2 */
9002   {
9003     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
9004   },
9005
9006   /* VEX_LEN_0F3831_P_2 */
9007   {
9008     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
9009   },
9010
9011   /* VEX_LEN_0F3832_P_2 */
9012   {
9013     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
9014   },
9015
9016   /* VEX_LEN_0F3833_P_2 */
9017   {
9018     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
9019   },
9020
9021   /* VEX_LEN_0F3834_P_2 */
9022   {
9023     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
9024   },
9025
9026   /* VEX_LEN_0F3835_P_2 */
9027   {
9028     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
9029   },
9030
9031   /* VEX_LEN_0F3837_P_2 */
9032   {
9033     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
9034   },
9035
9036   /* VEX_LEN_0F3838_P_2 */
9037   {
9038     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
9039   },
9040
9041   /* VEX_LEN_0F3839_P_2 */
9042   {
9043     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
9044   },
9045
9046   /* VEX_LEN_0F383A_P_2 */
9047   {
9048     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
9049   },
9050
9051   /* VEX_LEN_0F383B_P_2 */
9052   {
9053     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
9054   },
9055
9056   /* VEX_LEN_0F383C_P_2 */
9057   {
9058     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
9059   },
9060
9061   /* VEX_LEN_0F383D_P_2 */
9062   {
9063     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
9064   },
9065
9066   /* VEX_LEN_0F383E_P_2 */
9067   {
9068     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
9069   },
9070
9071   /* VEX_LEN_0F383F_P_2 */
9072   {
9073     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
9074   },
9075
9076   /* VEX_LEN_0F3840_P_2 */
9077   {
9078     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
9079   },
9080
9081   /* VEX_LEN_0F3841_P_2 */
9082   {
9083     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9084   },
9085
9086   /* VEX_LEN_0F38DB_P_2 */
9087   {
9088     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9089   },
9090
9091   /* VEX_LEN_0F38DC_P_2 */
9092   {
9093     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9094   },
9095
9096   /* VEX_LEN_0F38DD_P_2 */
9097   {
9098     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9099   },
9100
9101   /* VEX_LEN_0F38DE_P_2 */
9102   {
9103     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9104   },
9105
9106   /* VEX_LEN_0F38DF_P_2 */
9107   {
9108     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9109   },
9110
9111   /* VEX_LEN_0F38F2_P_0 */
9112   {
9113     { "andnS",          { Gdq, VexGdq, Edq } },
9114   },
9115
9116   /* VEX_LEN_0F38F3_R_1_P_0 */
9117   {
9118     { "blsrS",          { VexGdq, Edq } },
9119   },
9120
9121   /* VEX_LEN_0F38F3_R_2_P_0 */
9122   {
9123     { "blsmskS",        { VexGdq, Edq } },
9124   },
9125
9126   /* VEX_LEN_0F38F3_R_3_P_0 */
9127   {
9128     { "blsiS",          { VexGdq, Edq } },
9129   },
9130
9131   /* VEX_LEN_0F38F7_P_0 */
9132   {
9133     { "bextrS",         { Gdq, Edq, VexGdq } },
9134   },
9135
9136   /* VEX_LEN_0F3A06_P_2 */
9137   {
9138     { Bad_Opcode },
9139     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9140   },
9141
9142   /* VEX_LEN_0F3A0A_P_2 */
9143   {
9144     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9145     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9146   },
9147
9148   /* VEX_LEN_0F3A0B_P_2 */
9149   {
9150     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9151     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9152   },
9153
9154   /* VEX_LEN_0F3A0E_P_2 */
9155   {
9156     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
9157   },
9158
9159   /* VEX_LEN_0F3A0F_P_2 */
9160   {
9161     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
9162   },
9163
9164   /* VEX_LEN_0F3A14_P_2 */
9165   {
9166     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9167   },
9168
9169   /* VEX_LEN_0F3A15_P_2 */
9170   {
9171     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9172   },
9173
9174   /* VEX_LEN_0F3A16_P_2  */
9175   {
9176     { "vpextrK",        { Edq, XM, Ib } },
9177   },
9178
9179   /* VEX_LEN_0F3A17_P_2 */
9180   {
9181     { "vextractps",     { Edqd, XM, Ib } },
9182   },
9183
9184   /* VEX_LEN_0F3A18_P_2 */
9185   {
9186     { Bad_Opcode },
9187     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9188   },
9189
9190   /* VEX_LEN_0F3A19_P_2 */
9191   {
9192     { Bad_Opcode },
9193     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9194   },
9195
9196   /* VEX_LEN_0F3A20_P_2 */
9197   {
9198     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9199   },
9200
9201   /* VEX_LEN_0F3A21_P_2 */
9202   {
9203     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9204   },
9205
9206   /* VEX_LEN_0F3A22_P_2 */
9207   {
9208     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9209   },
9210
9211   /* VEX_LEN_0F3A41_P_2 */
9212   {
9213     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9214   },
9215
9216   /* VEX_LEN_0F3A42_P_2 */
9217   {
9218     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
9219   },
9220
9221   /* VEX_LEN_0F3A44_P_2 */
9222   {
9223     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9224   },
9225
9226   /* VEX_LEN_0F3A4C_P_2 */
9227   {
9228     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
9229   },
9230
9231   /* VEX_LEN_0F3A60_P_2 */
9232   {
9233     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
9234   },
9235
9236   /* VEX_LEN_0F3A61_P_2 */
9237   {
9238     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
9239   },
9240
9241   /* VEX_LEN_0F3A62_P_2 */
9242   {
9243     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
9244   },
9245
9246   /* VEX_LEN_0F3A63_P_2 */
9247   {
9248     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
9249   },
9250
9251   /* VEX_LEN_0F3A6A_P_2 */
9252   {
9253     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9254   },
9255
9256   /* VEX_LEN_0F3A6B_P_2 */
9257   {
9258     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9259   },
9260
9261   /* VEX_LEN_0F3A6E_P_2 */
9262   {
9263     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9264   },
9265
9266   /* VEX_LEN_0F3A6F_P_2 */
9267   {
9268     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9269   },
9270
9271   /* VEX_LEN_0F3A7A_P_2 */
9272   {
9273     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9274   },
9275
9276   /* VEX_LEN_0F3A7B_P_2 */
9277   {
9278     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9279   },
9280
9281   /* VEX_LEN_0F3A7E_P_2 */
9282   {
9283     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9284   },
9285
9286   /* VEX_LEN_0F3A7F_P_2 */
9287   {
9288     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9289   },
9290
9291   /* VEX_LEN_0F3ADF_P_2 */
9292   {
9293     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9294   },
9295
9296   /* VEX_LEN_0FXOP_09_80 */
9297   {
9298     { "vfrczps",        { XM, EXxmm } },
9299     { "vfrczps",        { XM, EXymmq } },
9300   },
9301
9302   /* VEX_LEN_0FXOP_09_81 */
9303   {
9304     { "vfrczpd",        { XM, EXxmm } },
9305     { "vfrczpd",        { XM, EXymmq } },
9306   },
9307 };
9308
9309 static const struct dis386 vex_w_table[][2] = {
9310   {
9311     /* VEX_W_0F10_P_0 */
9312     { "vmovups",        { XM, EXx } },
9313   },
9314   {
9315     /* VEX_W_0F10_P_1 */
9316     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9317   },
9318   {
9319     /* VEX_W_0F10_P_2 */
9320     { "vmovupd",        { XM, EXx } },
9321   },
9322   {
9323     /* VEX_W_0F10_P_3 */
9324     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9325   },
9326   {
9327     /* VEX_W_0F11_P_0 */
9328     { "vmovups",        { EXxS, XM } },
9329   },
9330   {
9331     /* VEX_W_0F11_P_1 */
9332     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9333   },
9334   {
9335     /* VEX_W_0F11_P_2 */
9336     { "vmovupd",        { EXxS, XM } },
9337   },
9338   {
9339     /* VEX_W_0F11_P_3 */
9340     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9341   },
9342   {
9343     /* VEX_W_0F12_P_0_M_0 */
9344     { "vmovlps",        { XM, Vex128, EXq } },
9345   },
9346   {
9347     /* VEX_W_0F12_P_0_M_1 */
9348     { "vmovhlps",       { XM, Vex128, EXq } },
9349   },
9350   {
9351     /* VEX_W_0F12_P_1 */
9352     { "vmovsldup",      { XM, EXx } },
9353   },
9354   {
9355     /* VEX_W_0F12_P_2 */
9356     { "vmovlpd",        { XM, Vex128, EXq } },
9357   },
9358   {
9359     /* VEX_W_0F12_P_3 */
9360     { "vmovddup",       { XM, EXymmq } },
9361   },
9362   {
9363     /* VEX_W_0F13_M_0 */
9364     { "vmovlpX",        { EXq, XM } },
9365   },
9366   {
9367     /* VEX_W_0F14 */
9368     { "vunpcklpX",      { XM, Vex, EXx } },
9369   },
9370   {
9371     /* VEX_W_0F15 */
9372     { "vunpckhpX",      { XM, Vex, EXx } },
9373   },
9374   {
9375     /* VEX_W_0F16_P_0_M_0 */
9376     { "vmovhps",        { XM, Vex128, EXq } },
9377   },
9378   {
9379     /* VEX_W_0F16_P_0_M_1 */
9380     { "vmovlhps",       { XM, Vex128, EXq } },
9381   },
9382   {
9383     /* VEX_W_0F16_P_1 */
9384     { "vmovshdup",      { XM, EXx } },
9385   },
9386   {
9387     /* VEX_W_0F16_P_2 */
9388     { "vmovhpd",        { XM, Vex128, EXq } },
9389   },
9390   {
9391     /* VEX_W_0F17_M_0 */
9392     { "vmovhpX",        { EXq, XM } },
9393   },
9394   {
9395     /* VEX_W_0F28 */
9396     { "vmovapX",        { XM, EXx } },
9397   },
9398   {
9399     /* VEX_W_0F29 */
9400     { "vmovapX",        { EXxS, XM } },
9401   },
9402   {
9403     /* VEX_W_0F2B_M_0 */
9404     { "vmovntpX",       { Mx, XM } },
9405   },
9406   {
9407     /* VEX_W_0F2E_P_0 */
9408     { "vucomiss",       { XMScalar, EXdScalar } },
9409   },
9410   {
9411     /* VEX_W_0F2E_P_2 */
9412     { "vucomisd",       { XMScalar, EXqScalar } },
9413   },
9414   {
9415     /* VEX_W_0F2F_P_0 */
9416     { "vcomiss",        { XMScalar, EXdScalar } },
9417   },
9418   {
9419     /* VEX_W_0F2F_P_2 */
9420     { "vcomisd",        { XMScalar, EXqScalar } },
9421   },
9422   {
9423     /* VEX_W_0F50_M_0 */
9424     { "vmovmskpX",      { Gdq, XS } },
9425   },
9426   {
9427     /* VEX_W_0F51_P_0 */
9428     { "vsqrtps",        { XM, EXx } },
9429   },
9430   {
9431     /* VEX_W_0F51_P_1 */
9432     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
9433   },
9434   {
9435     /* VEX_W_0F51_P_2  */
9436     { "vsqrtpd",        { XM, EXx } },
9437   },
9438   {
9439     /* VEX_W_0F51_P_3 */
9440     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
9441   },
9442   {
9443     /* VEX_W_0F52_P_0 */
9444     { "vrsqrtps",       { XM, EXx } },
9445   },
9446   {
9447     /* VEX_W_0F52_P_1 */
9448     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
9449   },
9450   {
9451     /* VEX_W_0F53_P_0  */
9452     { "vrcpps",         { XM, EXx } },
9453   },
9454   {
9455     /* VEX_W_0F53_P_1  */
9456     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
9457   },
9458   {
9459     /* VEX_W_0F58_P_0  */
9460     { "vaddps",         { XM, Vex, EXx } },
9461   },
9462   {
9463     /* VEX_W_0F58_P_1  */
9464     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
9465   },
9466   {
9467     /* VEX_W_0F58_P_2  */
9468     { "vaddpd",         { XM, Vex, EXx } },
9469   },
9470   {
9471     /* VEX_W_0F58_P_3  */
9472     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
9473   },
9474   {
9475     /* VEX_W_0F59_P_0  */
9476     { "vmulps",         { XM, Vex, EXx } },
9477   },
9478   {
9479     /* VEX_W_0F59_P_1  */
9480     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
9481   },
9482   {
9483     /* VEX_W_0F59_P_2  */
9484     { "vmulpd",         { XM, Vex, EXx } },
9485   },
9486   {
9487     /* VEX_W_0F59_P_3  */
9488     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
9489   },
9490   {
9491     /* VEX_W_0F5A_P_0  */
9492     { "vcvtps2pd",      { XM, EXxmmq } },
9493   },
9494   {
9495     /* VEX_W_0F5A_P_1  */
9496     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
9497   },
9498   {
9499     /* VEX_W_0F5A_P_3  */
9500     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
9501   },
9502   {
9503     /* VEX_W_0F5B_P_0  */
9504     { "vcvtdq2ps",      { XM, EXx } },
9505   },
9506   {
9507     /* VEX_W_0F5B_P_1  */
9508     { "vcvttps2dq",     { XM, EXx } },
9509   },
9510   {
9511     /* VEX_W_0F5B_P_2  */
9512     { "vcvtps2dq",      { XM, EXx } },
9513   },
9514   {
9515     /* VEX_W_0F5C_P_0  */
9516     { "vsubps",         { XM, Vex, EXx } },
9517   },
9518   {
9519     /* VEX_W_0F5C_P_1  */
9520     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
9521   },
9522   {
9523     /* VEX_W_0F5C_P_2  */
9524     { "vsubpd",         { XM, Vex, EXx } },
9525   },
9526   {
9527     /* VEX_W_0F5C_P_3  */
9528     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
9529   },
9530   {
9531     /* VEX_W_0F5D_P_0  */
9532     { "vminps",         { XM, Vex, EXx } },
9533   },
9534   {
9535     /* VEX_W_0F5D_P_1  */
9536     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
9537   },
9538   {
9539     /* VEX_W_0F5D_P_2  */
9540     { "vminpd",         { XM, Vex, EXx } },
9541   },
9542   {
9543     /* VEX_W_0F5D_P_3  */
9544     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
9545   },
9546   {
9547     /* VEX_W_0F5E_P_0  */
9548     { "vdivps",         { XM, Vex, EXx } },
9549   },
9550   {
9551     /* VEX_W_0F5E_P_1  */
9552     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
9553   },
9554   {
9555     /* VEX_W_0F5E_P_2  */
9556     { "vdivpd",         { XM, Vex, EXx } },
9557   },
9558   {
9559     /* VEX_W_0F5E_P_3  */
9560     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
9561   },
9562   {
9563     /* VEX_W_0F5F_P_0  */
9564     { "vmaxps",         { XM, Vex, EXx } },
9565   },
9566   {
9567     /* VEX_W_0F5F_P_1  */
9568     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
9569   },
9570   {
9571     /* VEX_W_0F5F_P_2  */
9572     { "vmaxpd",         { XM, Vex, EXx } },
9573   },
9574   {
9575     /* VEX_W_0F5F_P_3  */
9576     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
9577   },
9578   {
9579     /* VEX_W_0F60_P_2  */
9580     { "vpunpcklbw",     { XM, Vex128, EXx } },
9581   },
9582   {
9583     /* VEX_W_0F61_P_2  */
9584     { "vpunpcklwd",     { XM, Vex128, EXx } },
9585   },
9586   {
9587     /* VEX_W_0F62_P_2  */
9588     { "vpunpckldq",     { XM, Vex128, EXx } },
9589   },
9590   {
9591     /* VEX_W_0F63_P_2  */
9592     { "vpacksswb",      { XM, Vex128, EXx } },
9593   },
9594   {
9595     /* VEX_W_0F64_P_2  */
9596     { "vpcmpgtb",       { XM, Vex128, EXx } },
9597   },
9598   {
9599     /* VEX_W_0F65_P_2  */
9600     { "vpcmpgtw",       { XM, Vex128, EXx } },
9601   },
9602   {
9603     /* VEX_W_0F66_P_2  */
9604     { "vpcmpgtd",       { XM, Vex128, EXx } },
9605   },
9606   {
9607     /* VEX_W_0F67_P_2  */
9608     { "vpackuswb",      { XM, Vex128, EXx } },
9609   },
9610   {
9611     /* VEX_W_0F68_P_2  */
9612     { "vpunpckhbw",     { XM, Vex128, EXx } },
9613   },
9614   {
9615     /* VEX_W_0F69_P_2  */
9616     { "vpunpckhwd",     { XM, Vex128, EXx } },
9617   },
9618   {
9619     /* VEX_W_0F6A_P_2  */
9620     { "vpunpckhdq",     { XM, Vex128, EXx } },
9621   },
9622   {
9623     /* VEX_W_0F6B_P_2  */
9624     { "vpackssdw",      { XM, Vex128, EXx } },
9625   },
9626   {
9627     /* VEX_W_0F6C_P_2  */
9628     { "vpunpcklqdq",    { XM, Vex128, EXx } },
9629   },
9630   {
9631     /* VEX_W_0F6D_P_2  */
9632     { "vpunpckhqdq",    { XM, Vex128, EXx } },
9633   },
9634   {
9635     /* VEX_W_0F6F_P_1  */
9636     { "vmovdqu",        { XM, EXx } },
9637   },
9638   {
9639     /* VEX_W_0F6F_P_2  */
9640     { "vmovdqa",        { XM, EXx } },
9641   },
9642   {
9643     /* VEX_W_0F70_P_1 */
9644     { "vpshufhw",       { XM, EXx, Ib } },
9645   },
9646   {
9647     /* VEX_W_0F70_P_2 */
9648     { "vpshufd",        { XM, EXx, Ib } },
9649   },
9650   {
9651     /* VEX_W_0F70_P_3 */
9652     { "vpshuflw",       { XM, EXx, Ib } },
9653   },
9654   {
9655     /* VEX_W_0F71_R_2_P_2  */
9656     { "vpsrlw",         { Vex128, XS, Ib } },
9657   },
9658   {
9659     /* VEX_W_0F71_R_4_P_2  */
9660     { "vpsraw",         { Vex128, XS, Ib } },
9661   },
9662   {
9663     /* VEX_W_0F71_R_6_P_2  */
9664     { "vpsllw",         { Vex128, XS, Ib } },
9665   },
9666   {
9667     /* VEX_W_0F72_R_2_P_2  */
9668     { "vpsrld",         { Vex128, XS, Ib } },
9669   },
9670   {
9671     /* VEX_W_0F72_R_4_P_2  */
9672     { "vpsrad",         { Vex128, XS, Ib } },
9673   },
9674   {
9675     /* VEX_W_0F72_R_6_P_2  */
9676     { "vpslld",         { Vex128, XS, Ib } },
9677   },
9678   {
9679     /* VEX_W_0F73_R_2_P_2  */
9680     { "vpsrlq",         { Vex128, XS, Ib } },
9681   },
9682   {
9683     /* VEX_W_0F73_R_3_P_2  */
9684     { "vpsrldq",        { Vex128, XS, Ib } },
9685   },
9686   {
9687     /* VEX_W_0F73_R_6_P_2  */
9688     { "vpsllq",         { Vex128, XS, Ib } },
9689   },
9690   {
9691     /* VEX_W_0F73_R_7_P_2  */
9692     { "vpslldq",        { Vex128, XS, Ib } },
9693   },
9694   {
9695     /* VEX_W_0F74_P_2 */
9696     { "vpcmpeqb",       { XM, Vex128, EXx } },
9697   },
9698   {
9699     /* VEX_W_0F75_P_2 */
9700     { "vpcmpeqw",       { XM, Vex128, EXx } },
9701   },
9702   {
9703     /* VEX_W_0F76_P_2 */
9704     { "vpcmpeqd",       { XM, Vex128, EXx } },
9705   },
9706   {
9707     /* VEX_W_0F77_P_0 */
9708     { "",               { VZERO } },
9709   },
9710   {
9711     /* VEX_W_0F7C_P_2 */
9712     { "vhaddpd",        { XM, Vex, EXx } },
9713   },
9714   {
9715     /* VEX_W_0F7C_P_3 */
9716     { "vhaddps",        { XM, Vex, EXx } },
9717   },
9718   {
9719     /* VEX_W_0F7D_P_2 */
9720     { "vhsubpd",        { XM, Vex, EXx } },
9721   },
9722   {
9723     /* VEX_W_0F7D_P_3 */
9724     { "vhsubps",        { XM, Vex, EXx } },
9725   },
9726   {
9727     /* VEX_W_0F7E_P_1 */
9728     { "vmovq",          { XMScalar, EXqScalar } },
9729   },
9730   {
9731     /* VEX_W_0F7F_P_1 */
9732     { "vmovdqu",        { EXxS, XM } },
9733   },
9734   {
9735     /* VEX_W_0F7F_P_2 */
9736     { "vmovdqa",        { EXxS, XM } },
9737   },
9738   {
9739     /* VEX_W_0FAE_R_2_M_0 */
9740     { "vldmxcsr",       { Md } },
9741   },
9742   {
9743     /* VEX_W_0FAE_R_3_M_0 */
9744     { "vstmxcsr",       { Md } },
9745   },
9746   {
9747     /* VEX_W_0FC2_P_0 */
9748     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9749   },
9750   {
9751     /* VEX_W_0FC2_P_1 */
9752     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
9753   },
9754   {
9755     /* VEX_W_0FC2_P_2 */
9756     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9757   },
9758   {
9759     /* VEX_W_0FC2_P_3 */
9760     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
9761   },
9762   {
9763     /* VEX_W_0FC4_P_2 */
9764     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9765   },
9766   {
9767     /* VEX_W_0FC5_P_2 */
9768     { "vpextrw",        { Gdq, XS, Ib } },
9769   },
9770   {
9771     /* VEX_W_0FD0_P_2 */
9772     { "vaddsubpd",      { XM, Vex, EXx } },
9773   },
9774   {
9775     /* VEX_W_0FD0_P_3 */
9776     { "vaddsubps",      { XM, Vex, EXx } },
9777   },
9778   {
9779     /* VEX_W_0FD1_P_2 */
9780     { "vpsrlw",         { XM, Vex128, EXx } },
9781   },
9782   {
9783     /* VEX_W_0FD2_P_2 */
9784     { "vpsrld",         { XM, Vex128, EXx } },
9785   },
9786   {
9787     /* VEX_W_0FD3_P_2 */
9788     { "vpsrlq",         { XM, Vex128, EXx } },
9789   },
9790   {
9791     /* VEX_W_0FD4_P_2 */
9792     { "vpaddq",         { XM, Vex128, EXx } },
9793   },
9794   {
9795     /* VEX_W_0FD5_P_2 */
9796     { "vpmullw",        { XM, Vex128, EXx } },
9797   },
9798   {
9799     /* VEX_W_0FD6_P_2 */
9800     { "vmovq",          { EXqScalarS, XMScalar } },
9801   },
9802   {
9803     /* VEX_W_0FD7_P_2_M_1 */
9804     { "vpmovmskb",      { Gdq, XS } },
9805   },
9806   {
9807     /* VEX_W_0FD8_P_2 */
9808     { "vpsubusb",       { XM, Vex128, EXx } },
9809   },
9810   {
9811     /* VEX_W_0FD9_P_2 */
9812     { "vpsubusw",       { XM, Vex128, EXx } },
9813   },
9814   {
9815     /* VEX_W_0FDA_P_2 */
9816     { "vpminub",        { XM, Vex128, EXx } },
9817   },
9818   {
9819     /* VEX_W_0FDB_P_2 */
9820     { "vpand",          { XM, Vex128, EXx } },
9821   },
9822   {
9823     /* VEX_W_0FDC_P_2 */
9824     { "vpaddusb",       { XM, Vex128, EXx } },
9825   },
9826   {
9827     /* VEX_W_0FDD_P_2 */
9828     { "vpaddusw",       { XM, Vex128, EXx } },
9829   },
9830   {
9831     /* VEX_W_0FDE_P_2 */
9832     { "vpmaxub",        { XM, Vex128, EXx } },
9833   },
9834   {
9835     /* VEX_W_0FDF_P_2 */
9836     { "vpandn",         { XM, Vex128, EXx } },
9837   },
9838   {
9839     /* VEX_W_0FE0_P_2  */
9840     { "vpavgb",         { XM, Vex128, EXx } },
9841   },
9842   {
9843     /* VEX_W_0FE1_P_2  */
9844     { "vpsraw",         { XM, Vex128, EXx } },
9845   },
9846   {
9847     /* VEX_W_0FE2_P_2  */
9848     { "vpsrad",         { XM, Vex128, EXx } },
9849   },
9850   {
9851     /* VEX_W_0FE3_P_2  */
9852     { "vpavgw",         { XM, Vex128, EXx } },
9853   },
9854   {
9855     /* VEX_W_0FE4_P_2  */
9856     { "vpmulhuw",       { XM, Vex128, EXx } },
9857   },
9858   {
9859     /* VEX_W_0FE5_P_2  */
9860     { "vpmulhw",        { XM, Vex128, EXx } },
9861   },
9862   {
9863     /* VEX_W_0FE6_P_1  */
9864     { "vcvtdq2pd",      { XM, EXxmmq } },
9865   },
9866   {
9867     /* VEX_W_0FE6_P_2  */
9868     { "vcvttpd2dq%XY",  { XMM, EXx } },
9869   },
9870   {
9871     /* VEX_W_0FE6_P_3  */
9872     { "vcvtpd2dq%XY",   { XMM, EXx } },
9873   },
9874   {
9875     /* VEX_W_0FE7_P_2_M_0 */
9876     { "vmovntdq",       { Mx, XM } },
9877   },
9878   {
9879     /* VEX_W_0FE8_P_2  */
9880     { "vpsubsb",        { XM, Vex128, EXx } },
9881   },
9882   {
9883     /* VEX_W_0FE9_P_2  */
9884     { "vpsubsw",        { XM, Vex128, EXx } },
9885   },
9886   {
9887     /* VEX_W_0FEA_P_2  */
9888     { "vpminsw",        { XM, Vex128, EXx } },
9889   },
9890   {
9891     /* VEX_W_0FEB_P_2  */
9892     { "vpor",           { XM, Vex128, EXx } },
9893   },
9894   {
9895     /* VEX_W_0FEC_P_2  */
9896     { "vpaddsb",        { XM, Vex128, EXx } },
9897   },
9898   {
9899     /* VEX_W_0FED_P_2  */
9900     { "vpaddsw",        { XM, Vex128, EXx } },
9901   },
9902   {
9903     /* VEX_W_0FEE_P_2  */
9904     { "vpmaxsw",        { XM, Vex128, EXx } },
9905   },
9906   {
9907     /* VEX_W_0FEF_P_2  */
9908     { "vpxor",          { XM, Vex128, EXx } },
9909   },
9910   {
9911     /* VEX_W_0FF0_P_3_M_0 */
9912     { "vlddqu",         { XM, M } },
9913   },
9914   {
9915     /* VEX_W_0FF1_P_2 */
9916     { "vpsllw",         { XM, Vex128, EXx } },
9917   },
9918   {
9919     /* VEX_W_0FF2_P_2 */
9920     { "vpslld",         { XM, Vex128, EXx } },
9921   },
9922   {
9923     /* VEX_W_0FF3_P_2 */
9924     { "vpsllq",         { XM, Vex128, EXx } },
9925   },
9926   {
9927     /* VEX_W_0FF4_P_2 */
9928     { "vpmuludq",       { XM, Vex128, EXx } },
9929   },
9930   {
9931     /* VEX_W_0FF5_P_2 */
9932     { "vpmaddwd",       { XM, Vex128, EXx } },
9933   },
9934   {
9935     /* VEX_W_0FF6_P_2 */
9936     { "vpsadbw",        { XM, Vex128, EXx } },
9937   },
9938   {
9939     /* VEX_W_0FF7_P_2 */
9940     { "vmaskmovdqu",    { XM, XS } },
9941   },
9942   {
9943     /* VEX_W_0FF8_P_2 */
9944     { "vpsubb",         { XM, Vex128, EXx } },
9945   },
9946   {
9947     /* VEX_W_0FF9_P_2 */
9948     { "vpsubw",         { XM, Vex128, EXx } },
9949   },
9950   {
9951     /* VEX_W_0FFA_P_2 */
9952     { "vpsubd",         { XM, Vex128, EXx } },
9953   },
9954   {
9955     /* VEX_W_0FFB_P_2 */
9956     { "vpsubq",         { XM, Vex128, EXx } },
9957   },
9958   {
9959     /* VEX_W_0FFC_P_2 */
9960     { "vpaddb",         { XM, Vex128, EXx } },
9961   },
9962   {
9963     /* VEX_W_0FFD_P_2 */
9964     { "vpaddw",         { XM, Vex128, EXx } },
9965   },
9966   {
9967     /* VEX_W_0FFE_P_2 */
9968     { "vpaddd",         { XM, Vex128, EXx } },
9969   },
9970   {
9971     /* VEX_W_0F3800_P_2  */
9972     { "vpshufb",        { XM, Vex128, EXx } },
9973   },
9974   {
9975     /* VEX_W_0F3801_P_2  */
9976     { "vphaddw",        { XM, Vex128, EXx } },
9977   },
9978   {
9979     /* VEX_W_0F3802_P_2  */
9980     { "vphaddd",        { XM, Vex128, EXx } },
9981   },
9982   {
9983     /* VEX_W_0F3803_P_2  */
9984     { "vphaddsw",       { XM, Vex128, EXx } },
9985   },
9986   {
9987     /* VEX_W_0F3804_P_2  */
9988     { "vpmaddubsw",     { XM, Vex128, EXx } },
9989   },
9990   {
9991     /* VEX_W_0F3805_P_2  */
9992     { "vphsubw",        { XM, Vex128, EXx } },
9993   },
9994   {
9995     /* VEX_W_0F3806_P_2  */
9996     { "vphsubd",        { XM, Vex128, EXx } },
9997   },
9998   {
9999     /* VEX_W_0F3807_P_2  */
10000     { "vphsubsw",       { XM, Vex128, EXx } },
10001   },
10002   {
10003     /* VEX_W_0F3808_P_2  */
10004     { "vpsignb",        { XM, Vex128, EXx } },
10005   },
10006   {
10007     /* VEX_W_0F3809_P_2  */
10008     { "vpsignw",        { XM, Vex128, EXx } },
10009   },
10010   {
10011     /* VEX_W_0F380A_P_2  */
10012     { "vpsignd",        { XM, Vex128, EXx } },
10013   },
10014   {
10015     /* VEX_W_0F380B_P_2  */
10016     { "vpmulhrsw",      { XM, Vex128, EXx } },
10017   },
10018   {
10019     /* VEX_W_0F380C_P_2  */
10020     { "vpermilps",      { XM, Vex, EXx } },
10021   },
10022   {
10023     /* VEX_W_0F380D_P_2  */
10024     { "vpermilpd",      { XM, Vex, EXx } },
10025   },
10026   {
10027     /* VEX_W_0F380E_P_2  */
10028     { "vtestps",        { XM, EXx } },
10029   },
10030   {
10031     /* VEX_W_0F380F_P_2  */
10032     { "vtestpd",        { XM, EXx } },
10033   },
10034   {
10035     /* VEX_W_0F3817_P_2 */
10036     { "vptest",         { XM, EXx } },
10037   },
10038   {
10039     /* VEX_W_0F3818_P_2_M_0 */
10040     { "vbroadcastss",   { XM, Md } },
10041   },
10042   {
10043     /* VEX_W_0F3819_P_2_M_0 */
10044     { "vbroadcastsd",   { XM, Mq } },
10045   },
10046   {
10047     /* VEX_W_0F381A_P_2_M_0 */
10048     { "vbroadcastf128", { XM, Mxmm } },
10049   },
10050   {
10051     /* VEX_W_0F381C_P_2 */
10052     { "vpabsb",         { XM, EXx } },
10053   },
10054   {
10055     /* VEX_W_0F381D_P_2 */
10056     { "vpabsw",         { XM, EXx } },
10057   },
10058   {
10059     /* VEX_W_0F381E_P_2 */
10060     { "vpabsd",         { XM, EXx } },
10061   },
10062   {
10063     /* VEX_W_0F3820_P_2 */
10064     { "vpmovsxbw",      { XM, EXq } },
10065   },
10066   {
10067     /* VEX_W_0F3821_P_2 */
10068     { "vpmovsxbd",      { XM, EXd } },
10069   },
10070   {
10071     /* VEX_W_0F3822_P_2 */
10072     { "vpmovsxbq",      { XM, EXw } },
10073   },
10074   {
10075     /* VEX_W_0F3823_P_2 */
10076     { "vpmovsxwd",      { XM, EXq } },
10077   },
10078   {
10079     /* VEX_W_0F3824_P_2 */
10080     { "vpmovsxwq",      { XM, EXd } },
10081   },
10082   {
10083     /* VEX_W_0F3825_P_2 */
10084     { "vpmovsxdq",      { XM, EXq } },
10085   },
10086   {
10087     /* VEX_W_0F3828_P_2 */
10088     { "vpmuldq",        { XM, Vex128, EXx } },
10089   },
10090   {
10091     /* VEX_W_0F3829_P_2 */
10092     { "vpcmpeqq",       { XM, Vex128, EXx } },
10093   },
10094   {
10095     /* VEX_W_0F382A_P_2_M_0 */
10096     { "vmovntdqa",      { XM, Mx } },
10097   },
10098   {
10099     /* VEX_W_0F382B_P_2 */
10100     { "vpackusdw",      { XM, Vex128, EXx } },
10101   },
10102   {
10103     /* VEX_W_0F382C_P_2_M_0 */
10104     { "vmaskmovps",     { XM, Vex, Mx } },
10105   },
10106   {
10107     /* VEX_W_0F382D_P_2_M_0 */
10108     { "vmaskmovpd",     { XM, Vex, Mx } },
10109   },
10110   {
10111     /* VEX_W_0F382E_P_2_M_0 */
10112     { "vmaskmovps",     { Mx, Vex, XM } },
10113   },
10114   {
10115     /* VEX_W_0F382F_P_2_M_0 */
10116     { "vmaskmovpd",     { Mx, Vex, XM } },
10117   },
10118   {
10119     /* VEX_W_0F3830_P_2 */
10120     { "vpmovzxbw",      { XM, EXq } },
10121   },
10122   {
10123     /* VEX_W_0F3831_P_2 */
10124     { "vpmovzxbd",      { XM, EXd } },
10125   },
10126   {
10127     /* VEX_W_0F3832_P_2 */
10128     { "vpmovzxbq",      { XM, EXw } },
10129   },
10130   {
10131     /* VEX_W_0F3833_P_2 */
10132     { "vpmovzxwd",      { XM, EXq } },
10133   },
10134   {
10135     /* VEX_W_0F3834_P_2 */
10136     { "vpmovzxwq",      { XM, EXd } },
10137   },
10138   {
10139     /* VEX_W_0F3835_P_2 */
10140     { "vpmovzxdq",      { XM, EXq } },
10141   },
10142   {
10143     /* VEX_W_0F3837_P_2 */
10144     { "vpcmpgtq",       { XM, Vex128, EXx } },
10145   },
10146   {
10147     /* VEX_W_0F3838_P_2 */
10148     { "vpminsb",        { XM, Vex128, EXx } },
10149   },
10150   {
10151     /* VEX_W_0F3839_P_2 */
10152     { "vpminsd",        { XM, Vex128, EXx } },
10153   },
10154   {
10155     /* VEX_W_0F383A_P_2 */
10156     { "vpminuw",        { XM, Vex128, EXx } },
10157   },
10158   {
10159     /* VEX_W_0F383B_P_2 */
10160     { "vpminud",        { XM, Vex128, EXx } },
10161   },
10162   {
10163     /* VEX_W_0F383C_P_2 */
10164     { "vpmaxsb",        { XM, Vex128, EXx } },
10165   },
10166   {
10167     /* VEX_W_0F383D_P_2 */
10168     { "vpmaxsd",        { XM, Vex128, EXx } },
10169   },
10170   {
10171     /* VEX_W_0F383E_P_2 */
10172     { "vpmaxuw",        { XM, Vex128, EXx } },
10173   },
10174   {
10175     /* VEX_W_0F383F_P_2 */
10176     { "vpmaxud",        { XM, Vex128, EXx } },
10177   },
10178   {
10179     /* VEX_W_0F3840_P_2 */
10180     { "vpmulld",        { XM, Vex128, EXx } },
10181   },
10182   {
10183     /* VEX_W_0F3841_P_2 */
10184     { "vphminposuw",    { XM, EXx } },
10185   },
10186   {
10187     /* VEX_W_0F38DB_P_2 */
10188     { "vaesimc",        { XM, EXx } },
10189   },
10190   {
10191     /* VEX_W_0F38DC_P_2 */
10192     { "vaesenc",        { XM, Vex128, EXx } },
10193   },
10194   {
10195     /* VEX_W_0F38DD_P_2 */
10196     { "vaesenclast",    { XM, Vex128, EXx } },
10197   },
10198   {
10199     /* VEX_W_0F38DE_P_2 */
10200     { "vaesdec",        { XM, Vex128, EXx } },
10201   },
10202   {
10203     /* VEX_W_0F38DF_P_2 */
10204     { "vaesdeclast",    { XM, Vex128, EXx } },
10205   },
10206   {
10207     /* VEX_W_0F3A04_P_2 */
10208     { "vpermilps",      { XM, EXx, Ib } },
10209   },
10210   {
10211     /* VEX_W_0F3A05_P_2 */
10212     { "vpermilpd",      { XM, EXx, Ib } },
10213   },
10214   {
10215     /* VEX_W_0F3A06_P_2 */
10216     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10217   },
10218   {
10219     /* VEX_W_0F3A08_P_2 */
10220     { "vroundps",       { XM, EXx, Ib } },
10221   },
10222   {
10223     /* VEX_W_0F3A09_P_2 */
10224     { "vroundpd",       { XM, EXx, Ib } },
10225   },
10226   {
10227     /* VEX_W_0F3A0A_P_2 */
10228     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10229   },
10230   {
10231     /* VEX_W_0F3A0B_P_2 */
10232     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10233   },
10234   {
10235     /* VEX_W_0F3A0C_P_2 */
10236     { "vblendps",       { XM, Vex, EXx, Ib } },
10237   },
10238   {
10239     /* VEX_W_0F3A0D_P_2 */
10240     { "vblendpd",       { XM, Vex, EXx, Ib } },
10241   },
10242   {
10243     /* VEX_W_0F3A0E_P_2 */
10244     { "vpblendw",       { XM, Vex128, EXx, Ib } },
10245   },
10246   {
10247     /* VEX_W_0F3A0F_P_2 */
10248     { "vpalignr",       { XM, Vex128, EXx, Ib } },
10249   },
10250   {
10251     /* VEX_W_0F3A14_P_2 */
10252     { "vpextrb",        { Edqb, XM, Ib } },
10253   },
10254   {
10255     /* VEX_W_0F3A15_P_2 */
10256     { "vpextrw",        { Edqw, XM, Ib } },
10257   },
10258   {
10259     /* VEX_W_0F3A18_P_2 */
10260     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10261   },
10262   {
10263     /* VEX_W_0F3A19_P_2 */
10264     { "vextractf128",   { EXxmm, XM, Ib } },
10265   },
10266   {
10267     /* VEX_W_0F3A20_P_2 */
10268     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10269   },
10270   {
10271     /* VEX_W_0F3A21_P_2 */
10272     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10273   },
10274   {
10275     /* VEX_W_0F3A40_P_2 */
10276     { "vdpps",          { XM, Vex, EXx, Ib } },
10277   },
10278   {
10279     /* VEX_W_0F3A41_P_2 */
10280     { "vdppd",          { XM, Vex128, EXx, Ib } },
10281   },
10282   {
10283     /* VEX_W_0F3A42_P_2 */
10284     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
10285   },
10286   {
10287     /* VEX_W_0F3A44_P_2 */
10288     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10289   },
10290   {
10291     /* VEX_W_0F3A48_P_2 */
10292     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10293     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10294   },
10295   {
10296     /* VEX_W_0F3A49_P_2 */
10297     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10298     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10299   },
10300   {
10301     /* VEX_W_0F3A4A_P_2 */
10302     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10303   },
10304   {
10305     /* VEX_W_0F3A4B_P_2 */
10306     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10307   },
10308   {
10309     /* VEX_W_0F3A4C_P_2 */
10310     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
10311   },
10312   {
10313     /* VEX_W_0F3A60_P_2 */
10314     { "vpcmpestrm",     { XM, EXx, Ib } },
10315   },
10316   {
10317     /* VEX_W_0F3A61_P_2 */
10318     { "vpcmpestri",     { XM, EXx, Ib } },
10319   },
10320   {
10321     /* VEX_W_0F3A62_P_2 */
10322     { "vpcmpistrm",     { XM, EXx, Ib } },
10323   },
10324   {
10325     /* VEX_W_0F3A63_P_2 */
10326     { "vpcmpistri",     { XM, EXx, Ib } },
10327   },
10328   {
10329     /* VEX_W_0F3ADF_P_2 */
10330     { "vaeskeygenassist", { XM, EXx, Ib } },
10331   },
10332 };
10333
10334 static const struct dis386 mod_table[][2] = {
10335   {
10336     /* MOD_8D */
10337     { "leaS",           { Gv, M } },
10338   },
10339   {
10340     /* MOD_0F01_REG_0 */
10341     { X86_64_TABLE (X86_64_0F01_REG_0) },
10342     { RM_TABLE (RM_0F01_REG_0) },
10343   },
10344   {
10345     /* MOD_0F01_REG_1 */
10346     { X86_64_TABLE (X86_64_0F01_REG_1) },
10347     { RM_TABLE (RM_0F01_REG_1) },
10348   },
10349   {
10350     /* MOD_0F01_REG_2 */
10351     { X86_64_TABLE (X86_64_0F01_REG_2) },
10352     { RM_TABLE (RM_0F01_REG_2) },
10353   },
10354   {
10355     /* MOD_0F01_REG_3 */
10356     { X86_64_TABLE (X86_64_0F01_REG_3) },
10357     { RM_TABLE (RM_0F01_REG_3) },
10358   },
10359   {
10360     /* MOD_0F01_REG_7 */
10361     { "invlpg",         { Mb } },
10362     { RM_TABLE (RM_0F01_REG_7) },
10363   },
10364   {
10365     /* MOD_0F12_PREFIX_0 */
10366     { "movlps",         { XM, EXq } },
10367     { "movhlps",        { XM, EXq } },
10368   },
10369   {
10370     /* MOD_0F13 */
10371     { "movlpX",         { EXq, XM } },
10372   },
10373   {
10374     /* MOD_0F16_PREFIX_0 */
10375     { "movhps",         { XM, EXq } },
10376     { "movlhps",        { XM, EXq } },
10377   },
10378   {
10379     /* MOD_0F17 */
10380     { "movhpX",         { EXq, XM } },
10381   },
10382   {
10383     /* MOD_0F18_REG_0 */
10384     { "prefetchnta",    { Mb } },
10385   },
10386   {
10387     /* MOD_0F18_REG_1 */
10388     { "prefetcht0",     { Mb } },
10389   },
10390   {
10391     /* MOD_0F18_REG_2 */
10392     { "prefetcht1",     { Mb } },
10393   },
10394   {
10395     /* MOD_0F18_REG_3 */
10396     { "prefetcht2",     { Mb } },
10397   },
10398   {
10399     /* MOD_0F20 */
10400     { Bad_Opcode },
10401     { "movZ",           { Rm, Cm } },
10402   },
10403   {
10404     /* MOD_0F21 */
10405     { Bad_Opcode },
10406     { "movZ",           { Rm, Dm } },
10407   },
10408   {
10409     /* MOD_0F22 */
10410     { Bad_Opcode },
10411     { "movZ",           { Cm, Rm } },
10412   },
10413   {
10414     /* MOD_0F23 */
10415     { Bad_Opcode },
10416     { "movZ",           { Dm, Rm } },
10417   },
10418   {
10419     /* MOD_0F24 */
10420     { Bad_Opcode },
10421     { "movL",           { Rd, Td } },
10422   },
10423   {
10424     /* MOD_0F26 */
10425     { Bad_Opcode },
10426     { "movL",           { Td, Rd } },
10427   },
10428   {
10429     /* MOD_0F2B_PREFIX_0 */
10430     {"movntps",         { Mx, XM } },
10431   },
10432   {
10433     /* MOD_0F2B_PREFIX_1 */
10434     {"movntss",         { Md, XM } },
10435   },
10436   {
10437     /* MOD_0F2B_PREFIX_2 */
10438     {"movntpd",         { Mx, XM } },
10439   },
10440   {
10441     /* MOD_0F2B_PREFIX_3 */
10442     {"movntsd",         { Mq, XM } },
10443   },
10444   {
10445     /* MOD_0F51 */
10446     { Bad_Opcode },
10447     { "movmskpX",       { Gdq, XS } },
10448   },
10449   {
10450     /* MOD_0F71_REG_2 */
10451     { Bad_Opcode },
10452     { "psrlw",          { MS, Ib } },
10453   },
10454   {
10455     /* MOD_0F71_REG_4 */
10456     { Bad_Opcode },
10457     { "psraw",          { MS, Ib } },
10458   },
10459   {
10460     /* MOD_0F71_REG_6 */
10461     { Bad_Opcode },
10462     { "psllw",          { MS, Ib } },
10463   },
10464   {
10465     /* MOD_0F72_REG_2 */
10466     { Bad_Opcode },
10467     { "psrld",          { MS, Ib } },
10468   },
10469   {
10470     /* MOD_0F72_REG_4 */
10471     { Bad_Opcode },
10472     { "psrad",          { MS, Ib } },
10473   },
10474   {
10475     /* MOD_0F72_REG_6 */
10476     { Bad_Opcode },
10477     { "pslld",          { MS, Ib } },
10478   },
10479   {
10480     /* MOD_0F73_REG_2 */
10481     { Bad_Opcode },
10482     { "psrlq",          { MS, Ib } },
10483   },
10484   {
10485     /* MOD_0F73_REG_3 */
10486     { Bad_Opcode },
10487     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10488   },
10489   {
10490     /* MOD_0F73_REG_6 */
10491     { Bad_Opcode },
10492     { "psllq",          { MS, Ib } },
10493   },
10494   {
10495     /* MOD_0F73_REG_7 */
10496     { Bad_Opcode },
10497     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10498   },
10499   {
10500     /* MOD_0FAE_REG_0 */
10501     { "fxsave",         { FXSAVE } },
10502     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10503   },
10504   {
10505     /* MOD_0FAE_REG_1 */
10506     { "fxrstor",        { FXSAVE } },
10507     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10508   },
10509   {
10510     /* MOD_0FAE_REG_2 */
10511     { "ldmxcsr",        { Md } },
10512     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10513   },
10514   {
10515     /* MOD_0FAE_REG_3 */
10516     { "stmxcsr",        { Md } },
10517     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10518   },
10519   {
10520     /* MOD_0FAE_REG_4 */
10521     { "xsave",          { FXSAVE } },
10522   },
10523   {
10524     /* MOD_0FAE_REG_5 */
10525     { "xrstor",         { FXSAVE } },
10526     { RM_TABLE (RM_0FAE_REG_5) },
10527   },
10528   {
10529     /* MOD_0FAE_REG_6 */
10530     { "xsaveopt",       { FXSAVE } },
10531     { RM_TABLE (RM_0FAE_REG_6) },
10532   },
10533   {
10534     /* MOD_0FAE_REG_7 */
10535     { "clflush",        { Mb } },
10536     { RM_TABLE (RM_0FAE_REG_7) },
10537   },
10538   {
10539     /* MOD_0FB2 */
10540     { "lssS",           { Gv, Mp } },
10541   },
10542   {
10543     /* MOD_0FB4 */
10544     { "lfsS",           { Gv, Mp } },
10545   },
10546   {
10547     /* MOD_0FB5 */
10548     { "lgsS",           { Gv, Mp } },
10549   },
10550   {
10551     /* MOD_0FC7_REG_6 */
10552     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10553     { "rdrand",         { Ev } },
10554   },
10555   {
10556     /* MOD_0FC7_REG_7 */
10557     { "vmptrst",        { Mq } },
10558   },
10559   {
10560     /* MOD_0FD7 */
10561     { Bad_Opcode },
10562     { "pmovmskb",       { Gdq, MS } },
10563   },
10564   {
10565     /* MOD_0FE7_PREFIX_2 */
10566     { "movntdq",        { Mx, XM } },
10567   },
10568   {
10569     /* MOD_0FF0_PREFIX_3 */
10570     { "lddqu",          { XM, M } },
10571   },
10572   {
10573     /* MOD_0F382A_PREFIX_2 */
10574     { "movntdqa",       { XM, Mx } },
10575   },
10576   {
10577     /* MOD_62_32BIT */
10578     { "bound{S|}",      { Gv, Ma } },
10579   },
10580   {
10581     /* MOD_C4_32BIT */
10582     { "lesS",           { Gv, Mp } },
10583     { VEX_C4_TABLE (VEX_0F) },
10584   },
10585   {
10586     /* MOD_C5_32BIT */
10587     { "ldsS",           { Gv, Mp } },
10588     { VEX_C5_TABLE (VEX_0F) },
10589   },
10590   {
10591     /* MOD_VEX_0F12_PREFIX_0 */
10592     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10593     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10594   },
10595   {
10596     /* MOD_VEX_0F13 */
10597     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10598   },
10599   {
10600     /* MOD_VEX_0F16_PREFIX_0 */
10601     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10602     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10603   },
10604   {
10605     /* MOD_VEX_0F17 */
10606     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10607   },
10608   {
10609     /* MOD_VEX_0F2B */
10610     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
10611   },
10612   {
10613     /* MOD_VEX_0F50 */
10614     { Bad_Opcode },
10615     { VEX_W_TABLE (VEX_W_0F50_M_0) },
10616   },
10617   {
10618     /* MOD_VEX_0F71_REG_2 */
10619     { Bad_Opcode },
10620     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10621   },
10622   {
10623     /* MOD_VEX_0F71_REG_4 */
10624     { Bad_Opcode },
10625     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10626   },
10627   {
10628     /* MOD_VEX_0F71_REG_6 */
10629     { Bad_Opcode },
10630     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10631   },
10632   {
10633     /* MOD_VEX_0F72_REG_2 */
10634     { Bad_Opcode },
10635     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10636   },
10637   {
10638     /* MOD_VEX_0F72_REG_4 */
10639     { Bad_Opcode },
10640     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10641   },
10642   {
10643     /* MOD_VEX_0F72_REG_6 */
10644     { Bad_Opcode },
10645     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10646   },
10647   {
10648     /* MOD_VEX_0F73_REG_2 */
10649     { Bad_Opcode },
10650     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10651   },
10652   {
10653     /* MOD_VEX_0F73_REG_3 */
10654     { Bad_Opcode },
10655     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10656   },
10657   {
10658     /* MOD_VEX_0F73_REG_6 */
10659     { Bad_Opcode },
10660     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10661   },
10662   {
10663     /* MOD_VEX_0F73_REG_7 */
10664     { Bad_Opcode },
10665     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10666   },
10667   {
10668     /* MOD_VEX_0FAE_REG_2 */
10669     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10670   },
10671   {
10672     /* MOD_VEX_0FAE_REG_3 */
10673     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10674   },
10675   {
10676     /* MOD_VEX_0FD7_PREFIX_2 */
10677     { Bad_Opcode },
10678     { VEX_LEN_TABLE (VEX_LEN_0FD7_P_2_M_1) },
10679   },
10680   {
10681     /* MOD_VEX_0FE7_PREFIX_2 */
10682     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
10683   },
10684   {
10685     /* MOD_VEX_0FF0_PREFIX_3 */
10686     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
10687   },
10688   {
10689     /* MOD_VEX_0F3818_PREFIX_2 */
10690     { VEX_W_TABLE (VEX_W_0F3818_P_2_M_0) },
10691   },
10692   {
10693     /* MOD_VEX_0F3819_PREFIX_2 */
10694     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2_M_0) },
10695   },
10696   {
10697     /* MOD_VEX_0F381A_PREFIX_2 */
10698     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10699   },
10700   {
10701     /* MOD_VEX_0F382A_PREFIX_2 */
10702     { VEX_LEN_TABLE (VEX_LEN_0F382A_P_2_M_0) },
10703   },
10704   {
10705     /* MOD_VEX_0F382C_PREFIX_2 */
10706     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10707   },
10708   {
10709     /* MOD_VEX_0F382D_PREFIX_2 */
10710     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10711   },
10712   {
10713     /* MOD_VEX_0F382E_PREFIX_2 */
10714     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10715   },
10716   {
10717     /* MOD_VEX_0F382F_PREFIX_2 */
10718     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10719   },
10720 };
10721
10722 static const struct dis386 rm_table[][8] = {
10723   {
10724     /* RM_0F01_REG_0 */
10725     { Bad_Opcode },
10726     { "vmcall",         { Skip_MODRM } },
10727     { "vmlaunch",       { Skip_MODRM } },
10728     { "vmresume",       { Skip_MODRM } },
10729     { "vmxoff",         { Skip_MODRM } },
10730   },
10731   {
10732     /* RM_0F01_REG_1 */
10733     { "monitor",        { { OP_Monitor, 0 } } },
10734     { "mwait",          { { OP_Mwait, 0 } } },
10735   },
10736   {
10737     /* RM_0F01_REG_2 */
10738     { "xgetbv",         { Skip_MODRM } },
10739     { "xsetbv",         { Skip_MODRM } },
10740   },
10741   {
10742     /* RM_0F01_REG_3 */
10743     { "vmrun",          { Skip_MODRM } },
10744     { "vmmcall",        { Skip_MODRM } },
10745     { "vmload",         { Skip_MODRM } },
10746     { "vmsave",         { Skip_MODRM } },
10747     { "stgi",           { Skip_MODRM } },
10748     { "clgi",           { Skip_MODRM } },
10749     { "skinit",         { Skip_MODRM } },
10750     { "invlpga",        { Skip_MODRM } },
10751   },
10752   {
10753     /* RM_0F01_REG_7 */
10754     { "swapgs",         { Skip_MODRM } },
10755     { "rdtscp",         { Skip_MODRM } },
10756   },
10757   {
10758     /* RM_0FAE_REG_5 */
10759     { "lfence",         { Skip_MODRM } },
10760   },
10761   {
10762     /* RM_0FAE_REG_6 */
10763     { "mfence",         { Skip_MODRM } },
10764   },
10765   {
10766     /* RM_0FAE_REG_7 */
10767     { "sfence",         { Skip_MODRM } },
10768   },
10769 };
10770
10771 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10772
10773 /* We use the high bit to indicate different name for the same
10774    prefix.  */
10775 #define ADDR16_PREFIX   (0x67 | 0x100)
10776 #define ADDR32_PREFIX   (0x67 | 0x200)
10777 #define DATA16_PREFIX   (0x66 | 0x100)
10778 #define DATA32_PREFIX   (0x66 | 0x200)
10779 #define REP_PREFIX      (0xf3 | 0x100)
10780
10781 static int
10782 ckprefix (void)
10783 {
10784   int newrex, i, length;
10785   rex = 0;
10786   rex_ignored = 0;
10787   prefixes = 0;
10788   used_prefixes = 0;
10789   rex_used = 0;
10790   last_lock_prefix = -1;
10791   last_repz_prefix = -1;
10792   last_repnz_prefix = -1;
10793   last_data_prefix = -1;
10794   last_addr_prefix = -1;
10795   last_rex_prefix = -1;
10796   last_seg_prefix = -1;
10797   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10798     all_prefixes[i] = 0;
10799   i = 0;
10800   length = 0;
10801   /* The maximum instruction length is 15bytes.  */
10802   while (length < MAX_CODE_LENGTH - 1)
10803     {
10804       FETCH_DATA (the_info, codep + 1);
10805       newrex = 0;
10806       switch (*codep)
10807         {
10808         /* REX prefixes family.  */
10809         case 0x40:
10810         case 0x41:
10811         case 0x42:
10812         case 0x43:
10813         case 0x44:
10814         case 0x45:
10815         case 0x46:
10816         case 0x47:
10817         case 0x48:
10818         case 0x49:
10819         case 0x4a:
10820         case 0x4b:
10821         case 0x4c:
10822         case 0x4d:
10823         case 0x4e:
10824         case 0x4f:
10825           if (address_mode == mode_64bit)
10826             newrex = *codep;
10827           else
10828             return 1;
10829           last_rex_prefix = i;
10830           break;
10831         case 0xf3:
10832           prefixes |= PREFIX_REPZ;
10833           last_repz_prefix = i;
10834           break;
10835         case 0xf2:
10836           prefixes |= PREFIX_REPNZ;
10837           last_repnz_prefix = i;
10838           break;
10839         case 0xf0:
10840           prefixes |= PREFIX_LOCK;
10841           last_lock_prefix = i;
10842           break;
10843         case 0x2e:
10844           prefixes |= PREFIX_CS;
10845           last_seg_prefix = i;
10846           break;
10847         case 0x36:
10848           prefixes |= PREFIX_SS;
10849           last_seg_prefix = i;
10850           break;
10851         case 0x3e:
10852           prefixes |= PREFIX_DS;
10853           last_seg_prefix = i;
10854           break;
10855         case 0x26:
10856           prefixes |= PREFIX_ES;
10857           last_seg_prefix = i;
10858           break;
10859         case 0x64:
10860           prefixes |= PREFIX_FS;
10861           last_seg_prefix = i;
10862           break;
10863         case 0x65:
10864           prefixes |= PREFIX_GS;
10865           last_seg_prefix = i;
10866           break;
10867         case 0x66:
10868           prefixes |= PREFIX_DATA;
10869           last_data_prefix = i;
10870           break;
10871         case 0x67:
10872           prefixes |= PREFIX_ADDR;
10873           last_addr_prefix = i;
10874           break;
10875         case FWAIT_OPCODE:
10876           /* fwait is really an instruction.  If there are prefixes
10877              before the fwait, they belong to the fwait, *not* to the
10878              following instruction.  */
10879           if (prefixes || rex)
10880             {
10881               prefixes |= PREFIX_FWAIT;
10882               codep++;
10883               return 1;
10884             }
10885           prefixes = PREFIX_FWAIT;
10886           break;
10887         default:
10888           return 1;
10889         }
10890       /* Rex is ignored when followed by another prefix.  */
10891       if (rex)
10892         {
10893           rex_used = rex;
10894           return 1;
10895         }
10896       if (*codep != FWAIT_OPCODE)
10897         all_prefixes[i++] = *codep;
10898       rex = newrex;
10899       codep++;
10900       length++;
10901     }
10902   return 0;
10903 }
10904
10905 static int
10906 seg_prefix (int pref)
10907 {
10908   switch (pref)
10909     {
10910     case 0x2e:
10911       return PREFIX_CS;
10912     case 0x36:
10913       return PREFIX_SS;
10914     case 0x3e:
10915       return PREFIX_DS;
10916     case 0x26:
10917       return PREFIX_ES;
10918     case 0x64:
10919       return PREFIX_FS;
10920     case 0x65:
10921       return PREFIX_GS;
10922     default:
10923       return 0;
10924     }
10925 }
10926
10927 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10928    prefix byte.  */
10929
10930 static const char *
10931 prefix_name (int pref, int sizeflag)
10932 {
10933   static const char *rexes [16] =
10934     {
10935       "rex",            /* 0x40 */
10936       "rex.B",          /* 0x41 */
10937       "rex.X",          /* 0x42 */
10938       "rex.XB",         /* 0x43 */
10939       "rex.R",          /* 0x44 */
10940       "rex.RB",         /* 0x45 */
10941       "rex.RX",         /* 0x46 */
10942       "rex.RXB",        /* 0x47 */
10943       "rex.W",          /* 0x48 */
10944       "rex.WB",         /* 0x49 */
10945       "rex.WX",         /* 0x4a */
10946       "rex.WXB",        /* 0x4b */
10947       "rex.WR",         /* 0x4c */
10948       "rex.WRB",        /* 0x4d */
10949       "rex.WRX",        /* 0x4e */
10950       "rex.WRXB",       /* 0x4f */
10951     };
10952
10953   switch (pref)
10954     {
10955     /* REX prefixes family.  */
10956     case 0x40:
10957     case 0x41:
10958     case 0x42:
10959     case 0x43:
10960     case 0x44:
10961     case 0x45:
10962     case 0x46:
10963     case 0x47:
10964     case 0x48:
10965     case 0x49:
10966     case 0x4a:
10967     case 0x4b:
10968     case 0x4c:
10969     case 0x4d:
10970     case 0x4e:
10971     case 0x4f:
10972       return rexes [pref - 0x40];
10973     case 0xf3:
10974       return "repz";
10975     case 0xf2:
10976       return "repnz";
10977     case 0xf0:
10978       return "lock";
10979     case 0x2e:
10980       return "cs";
10981     case 0x36:
10982       return "ss";
10983     case 0x3e:
10984       return "ds";
10985     case 0x26:
10986       return "es";
10987     case 0x64:
10988       return "fs";
10989     case 0x65:
10990       return "gs";
10991     case 0x66:
10992       return (sizeflag & DFLAG) ? "data16" : "data32";
10993     case 0x67:
10994       if (address_mode == mode_64bit)
10995         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10996       else
10997         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10998     case FWAIT_OPCODE:
10999       return "fwait";
11000     case ADDR16_PREFIX:
11001       return "addr16";
11002     case ADDR32_PREFIX:
11003       return "addr32";
11004     case DATA16_PREFIX:
11005       return "data16";
11006     case DATA32_PREFIX:
11007       return "data32";
11008     case REP_PREFIX:
11009       return "rep";
11010     default:
11011       return NULL;
11012     }
11013 }
11014
11015 static char op_out[MAX_OPERANDS][100];
11016 static int op_ad, op_index[MAX_OPERANDS];
11017 static int two_source_ops;
11018 static bfd_vma op_address[MAX_OPERANDS];
11019 static bfd_vma op_riprel[MAX_OPERANDS];
11020 static bfd_vma start_pc;
11021
11022 /*
11023  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11024  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11025  *   section of the "Virtual 8086 Mode" chapter.)
11026  * 'pc' should be the address of this instruction, it will
11027  *   be used to print the target address if this is a relative jump or call
11028  * The function returns the length of this instruction in bytes.
11029  */
11030
11031 static char intel_syntax;
11032 static char intel_mnemonic = !SYSV386_COMPAT;
11033 static char open_char;
11034 static char close_char;
11035 static char separator_char;
11036 static char scale_char;
11037
11038 /* Here for backwards compatibility.  When gdb stops using
11039    print_insn_i386_att and print_insn_i386_intel these functions can
11040    disappear, and print_insn_i386 be merged into print_insn.  */
11041 int
11042 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11043 {
11044   intel_syntax = 0;
11045
11046   return print_insn (pc, info);
11047 }
11048
11049 int
11050 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11051 {
11052   intel_syntax = 1;
11053
11054   return print_insn (pc, info);
11055 }
11056
11057 int
11058 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11059 {
11060   intel_syntax = -1;
11061
11062   return print_insn (pc, info);
11063 }
11064
11065 void
11066 print_i386_disassembler_options (FILE *stream)
11067 {
11068   fprintf (stream, _("\n\
11069 The following i386/x86-64 specific disassembler options are supported for use\n\
11070 with the -M switch (multiple options should be separated by commas):\n"));
11071
11072   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11073   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11074   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11075   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11076   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11077   fprintf (stream, _("  att-mnemonic\n"
11078                      "              Display instruction in AT&T mnemonic\n"));
11079   fprintf (stream, _("  intel-mnemonic\n"
11080                      "              Display instruction in Intel mnemonic\n"));
11081   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11082   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11083   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11084   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11085   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11086   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11087 }
11088
11089 /* Bad opcode.  */
11090 static const struct dis386 bad_opcode = { "(bad)", { XX } };
11091
11092 /* Get a pointer to struct dis386 with a valid name.  */
11093
11094 static const struct dis386 *
11095 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11096 {
11097   int vindex, vex_table_index;
11098
11099   if (dp->name != NULL)
11100     return dp;
11101
11102   switch (dp->op[0].bytemode)
11103     {
11104     case USE_REG_TABLE:
11105       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11106       break;
11107
11108     case USE_MOD_TABLE:
11109       vindex = modrm.mod == 0x3 ? 1 : 0;
11110       dp = &mod_table[dp->op[1].bytemode][vindex];
11111       break;
11112
11113     case USE_RM_TABLE:
11114       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11115       break;
11116
11117     case USE_PREFIX_TABLE:
11118       if (need_vex)
11119         {
11120           /* The prefix in VEX is implicit.  */
11121           switch (vex.prefix)
11122             {
11123             case 0:
11124               vindex = 0;
11125               break;
11126             case REPE_PREFIX_OPCODE:
11127               vindex = 1;
11128               break;
11129             case DATA_PREFIX_OPCODE:
11130               vindex = 2;
11131               break;
11132             case REPNE_PREFIX_OPCODE:
11133               vindex = 3;
11134               break;
11135             default:
11136               abort ();
11137               break;
11138             }
11139         }
11140       else
11141         {
11142           vindex = 0;
11143           used_prefixes |= (prefixes & PREFIX_REPZ);
11144           if (prefixes & PREFIX_REPZ)
11145             {
11146               vindex = 1;
11147               all_prefixes[last_repz_prefix] = 0;
11148             }
11149           else
11150             {
11151               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11152                  PREFIX_DATA.  */
11153               used_prefixes |= (prefixes & PREFIX_REPNZ);
11154               if (prefixes & PREFIX_REPNZ)
11155                 {
11156                   vindex = 3;
11157                   all_prefixes[last_repnz_prefix] = 0;
11158                 }
11159               else
11160                 {
11161                   used_prefixes |= (prefixes & PREFIX_DATA);
11162                   if (prefixes & PREFIX_DATA)
11163                     {
11164                       vindex = 2;
11165                       all_prefixes[last_data_prefix] = 0;
11166                     }
11167                 }
11168             }
11169         }
11170       dp = &prefix_table[dp->op[1].bytemode][vindex];
11171       break;
11172
11173     case USE_X86_64_TABLE:
11174       vindex = address_mode == mode_64bit ? 1 : 0;
11175       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11176       break;
11177
11178     case USE_3BYTE_TABLE:
11179       FETCH_DATA (info, codep + 2);
11180       vindex = *codep++;
11181       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11182       modrm.mod = (*codep >> 6) & 3;
11183       modrm.reg = (*codep >> 3) & 7;
11184       modrm.rm = *codep & 7;
11185       break;
11186
11187     case USE_VEX_LEN_TABLE:
11188       if (!need_vex)
11189         abort ();
11190
11191       switch (vex.length)
11192         {
11193         case 128:
11194           vindex = 0;
11195           break;
11196         case 256:
11197           vindex = 1;
11198           break;
11199         default:
11200           abort ();
11201           break;
11202         }
11203
11204       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11205       break;
11206
11207     case USE_XOP_8F_TABLE:
11208       FETCH_DATA (info, codep + 3);
11209       /* All bits in the REX prefix are ignored.  */
11210       rex_ignored = rex;
11211       rex = ~(*codep >> 5) & 0x7;
11212
11213       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11214       switch ((*codep & 0x1f))
11215         {
11216         default:
11217           dp = &bad_opcode;
11218           return dp;
11219         case 0x8:
11220           vex_table_index = XOP_08;
11221           break;
11222         case 0x9:
11223           vex_table_index = XOP_09;
11224           break;
11225         case 0xa:
11226           vex_table_index = XOP_0A;
11227           break;
11228         }
11229       codep++;
11230       vex.w = *codep & 0x80;
11231       if (vex.w && address_mode == mode_64bit)
11232         rex |= REX_W;
11233
11234       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11235       if (address_mode != mode_64bit
11236           && vex.register_specifier > 0x7)
11237         {
11238           dp = &bad_opcode;
11239           return dp;
11240         }
11241
11242       vex.length = (*codep & 0x4) ? 256 : 128;
11243       switch ((*codep & 0x3))
11244         {
11245         case 0:
11246           vex.prefix = 0;
11247           break;
11248         case 1:
11249           vex.prefix = DATA_PREFIX_OPCODE;
11250           break;
11251         case 2:
11252           vex.prefix = REPE_PREFIX_OPCODE;
11253           break;
11254         case 3:
11255           vex.prefix = REPNE_PREFIX_OPCODE;
11256           break;
11257         }
11258       need_vex = 1;
11259       need_vex_reg = 1;
11260       codep++;
11261       vindex = *codep++;
11262       dp = &xop_table[vex_table_index][vindex];
11263
11264       FETCH_DATA (info, codep + 1);
11265       modrm.mod = (*codep >> 6) & 3;
11266       modrm.reg = (*codep >> 3) & 7;
11267       modrm.rm = *codep & 7;
11268       break;
11269
11270     case USE_VEX_C4_TABLE:
11271       FETCH_DATA (info, codep + 3);
11272       /* All bits in the REX prefix are ignored.  */
11273       rex_ignored = rex;
11274       rex = ~(*codep >> 5) & 0x7;
11275       switch ((*codep & 0x1f))
11276         {
11277         default:
11278           dp = &bad_opcode;
11279           return dp;
11280         case 0x1:
11281           vex_table_index = VEX_0F;
11282           break;
11283         case 0x2:
11284           vex_table_index = VEX_0F38;
11285           break;
11286         case 0x3:
11287           vex_table_index = VEX_0F3A;
11288           break;
11289         }
11290       codep++;
11291       vex.w = *codep & 0x80;
11292       if (vex.w && address_mode == mode_64bit)
11293         rex |= REX_W;
11294
11295       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11296       if (address_mode != mode_64bit
11297           && vex.register_specifier > 0x7)
11298         {
11299           dp = &bad_opcode;
11300           return dp;
11301         }
11302
11303       vex.length = (*codep & 0x4) ? 256 : 128;
11304       switch ((*codep & 0x3))
11305         {
11306         case 0:
11307           vex.prefix = 0;
11308           break;
11309         case 1:
11310           vex.prefix = DATA_PREFIX_OPCODE;
11311           break;
11312         case 2:
11313           vex.prefix = REPE_PREFIX_OPCODE;
11314           break;
11315         case 3:
11316           vex.prefix = REPNE_PREFIX_OPCODE;
11317           break;
11318         }
11319       need_vex = 1;
11320       need_vex_reg = 1;
11321       codep++;
11322       vindex = *codep++;
11323       dp = &vex_table[vex_table_index][vindex];
11324       /* There is no MODRM byte for VEX [82|77].  */
11325       if (vindex != 0x77 && vindex != 0x82)
11326         {
11327           FETCH_DATA (info, codep + 1);
11328           modrm.mod = (*codep >> 6) & 3;
11329           modrm.reg = (*codep >> 3) & 7;
11330           modrm.rm = *codep & 7;
11331         }
11332       break;
11333
11334     case USE_VEX_C5_TABLE:
11335       FETCH_DATA (info, codep + 2);
11336       /* All bits in the REX prefix are ignored.  */
11337       rex_ignored = rex;
11338       rex = (*codep & 0x80) ? 0 : REX_R;
11339
11340       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11341       if (address_mode != mode_64bit
11342           && vex.register_specifier > 0x7)
11343         {
11344           dp = &bad_opcode;
11345           return dp;
11346         }
11347
11348       vex.w = 0;
11349
11350       vex.length = (*codep & 0x4) ? 256 : 128;
11351       switch ((*codep & 0x3))
11352         {
11353         case 0:
11354           vex.prefix = 0;
11355           break;
11356         case 1:
11357           vex.prefix = DATA_PREFIX_OPCODE;
11358           break;
11359         case 2:
11360           vex.prefix = REPE_PREFIX_OPCODE;
11361           break;
11362         case 3:
11363           vex.prefix = REPNE_PREFIX_OPCODE;
11364           break;
11365         }
11366       need_vex = 1;
11367       need_vex_reg = 1;
11368       codep++;
11369       vindex = *codep++;
11370       dp = &vex_table[dp->op[1].bytemode][vindex];
11371       /* There is no MODRM byte for VEX [82|77].  */
11372       if (vindex != 0x77 && vindex != 0x82)
11373         {
11374           FETCH_DATA (info, codep + 1);
11375           modrm.mod = (*codep >> 6) & 3;
11376           modrm.reg = (*codep >> 3) & 7;
11377           modrm.rm = *codep & 7;
11378         }
11379       break;
11380
11381     case USE_VEX_W_TABLE:
11382       if (!need_vex)
11383         abort ();
11384
11385       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11386       break;
11387
11388     case 0:
11389       dp = &bad_opcode;
11390       break;
11391
11392     default:
11393       abort ();
11394     }
11395
11396   if (dp->name != NULL)
11397     return dp;
11398   else
11399     return get_valid_dis386 (dp, info);
11400 }
11401
11402 static void
11403 get_sib (disassemble_info *info)
11404 {
11405   /* If modrm.mod == 3, operand must be register.  */
11406   if (need_modrm
11407       && address_mode != mode_16bit
11408       && modrm.mod != 3
11409       && modrm.rm == 4)
11410     {
11411       FETCH_DATA (info, codep + 2);
11412       sib.index = (codep [1] >> 3) & 7;
11413       sib.scale = (codep [1] >> 6) & 3;
11414       sib.base = codep [1] & 7;
11415     }
11416 }
11417
11418 static int
11419 print_insn (bfd_vma pc, disassemble_info *info)
11420 {
11421   const struct dis386 *dp;
11422   int i;
11423   char *op_txt[MAX_OPERANDS];
11424   int needcomma;
11425   int sizeflag;
11426   const char *p;
11427   struct dis_private priv;
11428   int prefix_length;
11429   int default_prefixes;
11430
11431   if (info->mach == bfd_mach_x86_64_intel_syntax
11432       || info->mach == bfd_mach_x86_64
11433       || info->mach == bfd_mach_x64_32_intel_syntax
11434       || info->mach == bfd_mach_x64_32
11435       || info->mach == bfd_mach_l1om
11436       || info->mach == bfd_mach_l1om_intel_syntax)
11437     address_mode = mode_64bit;
11438   else
11439     address_mode = mode_32bit;
11440
11441   if (intel_syntax == (char) -1)
11442     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11443                     || info->mach == bfd_mach_x86_64_intel_syntax
11444                     || info->mach == bfd_mach_x64_32_intel_syntax
11445                     || info->mach == bfd_mach_l1om_intel_syntax);
11446
11447   if (info->mach == bfd_mach_i386_i386
11448       || info->mach == bfd_mach_x86_64
11449       || info->mach == bfd_mach_x64_32
11450       || info->mach == bfd_mach_l1om
11451       || info->mach == bfd_mach_i386_i386_intel_syntax
11452       || info->mach == bfd_mach_x86_64_intel_syntax
11453       || info->mach == bfd_mach_x64_32_intel_syntax
11454       || info->mach == bfd_mach_l1om_intel_syntax)
11455     priv.orig_sizeflag = AFLAG | DFLAG;
11456   else if (info->mach == bfd_mach_i386_i8086)
11457     priv.orig_sizeflag = 0;
11458   else
11459     abort ();
11460
11461   for (p = info->disassembler_options; p != NULL; )
11462     {
11463       if (CONST_STRNEQ (p, "x86-64"))
11464         {
11465           address_mode = mode_64bit;
11466           priv.orig_sizeflag = AFLAG | DFLAG;
11467         }
11468       else if (CONST_STRNEQ (p, "i386"))
11469         {
11470           address_mode = mode_32bit;
11471           priv.orig_sizeflag = AFLAG | DFLAG;
11472         }
11473       else if (CONST_STRNEQ (p, "i8086"))
11474         {
11475           address_mode = mode_16bit;
11476           priv.orig_sizeflag = 0;
11477         }
11478       else if (CONST_STRNEQ (p, "intel"))
11479         {
11480           intel_syntax = 1;
11481           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11482             intel_mnemonic = 1;
11483         }
11484       else if (CONST_STRNEQ (p, "att"))
11485         {
11486           intel_syntax = 0;
11487           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11488             intel_mnemonic = 0;
11489         }
11490       else if (CONST_STRNEQ (p, "addr"))
11491         {
11492           if (address_mode == mode_64bit)
11493             {
11494               if (p[4] == '3' && p[5] == '2')
11495                 priv.orig_sizeflag &= ~AFLAG;
11496               else if (p[4] == '6' && p[5] == '4')
11497                 priv.orig_sizeflag |= AFLAG;
11498             }
11499           else
11500             {
11501               if (p[4] == '1' && p[5] == '6')
11502                 priv.orig_sizeflag &= ~AFLAG;
11503               else if (p[4] == '3' && p[5] == '2')
11504                 priv.orig_sizeflag |= AFLAG;
11505             }
11506         }
11507       else if (CONST_STRNEQ (p, "data"))
11508         {
11509           if (p[4] == '1' && p[5] == '6')
11510             priv.orig_sizeflag &= ~DFLAG;
11511           else if (p[4] == '3' && p[5] == '2')
11512             priv.orig_sizeflag |= DFLAG;
11513         }
11514       else if (CONST_STRNEQ (p, "suffix"))
11515         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11516
11517       p = strchr (p, ',');
11518       if (p != NULL)
11519         p++;
11520     }
11521
11522   if (intel_syntax)
11523     {
11524       names64 = intel_names64;
11525       names32 = intel_names32;
11526       names16 = intel_names16;
11527       names8 = intel_names8;
11528       names8rex = intel_names8rex;
11529       names_seg = intel_names_seg;
11530       names_mm = intel_names_mm;
11531       names_xmm = intel_names_xmm;
11532       names_ymm = intel_names_ymm;
11533       index64 = intel_index64;
11534       index32 = intel_index32;
11535       index16 = intel_index16;
11536       open_char = '[';
11537       close_char = ']';
11538       separator_char = '+';
11539       scale_char = '*';
11540     }
11541   else
11542     {
11543       names64 = att_names64;
11544       names32 = att_names32;
11545       names16 = att_names16;
11546       names8 = att_names8;
11547       names8rex = att_names8rex;
11548       names_seg = att_names_seg;
11549       names_mm = att_names_mm;
11550       names_xmm = att_names_xmm;
11551       names_ymm = att_names_ymm;
11552       index64 = att_index64;
11553       index32 = att_index32;
11554       index16 = att_index16;
11555       open_char = '(';
11556       close_char =  ')';
11557       separator_char = ',';
11558       scale_char = ',';
11559     }
11560
11561   /* The output looks better if we put 7 bytes on a line, since that
11562      puts most long word instructions on a single line.  Use 8 bytes
11563      for Intel L1OM.  */
11564   if (info->mach == bfd_mach_l1om
11565       || info->mach == bfd_mach_l1om_intel_syntax)
11566     info->bytes_per_line = 8;
11567   else
11568     info->bytes_per_line = 7;
11569
11570   info->private_data = &priv;
11571   priv.max_fetched = priv.the_buffer;
11572   priv.insn_start = pc;
11573
11574   obuf[0] = 0;
11575   for (i = 0; i < MAX_OPERANDS; ++i)
11576     {
11577       op_out[i][0] = 0;
11578       op_index[i] = -1;
11579     }
11580
11581   the_info = info;
11582   start_pc = pc;
11583   start_codep = priv.the_buffer;
11584   codep = priv.the_buffer;
11585
11586   if (setjmp (priv.bailout) != 0)
11587     {
11588       const char *name;
11589
11590       /* Getting here means we tried for data but didn't get it.  That
11591          means we have an incomplete instruction of some sort.  Just
11592          print the first byte as a prefix or a .byte pseudo-op.  */
11593       if (codep > priv.the_buffer)
11594         {
11595           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11596           if (name != NULL)
11597             (*info->fprintf_func) (info->stream, "%s", name);
11598           else
11599             {
11600               /* Just print the first byte as a .byte instruction.  */
11601               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11602                                      (unsigned int) priv.the_buffer[0]);
11603             }
11604
11605           return 1;
11606         }
11607
11608       return -1;
11609     }
11610
11611   obufp = obuf;
11612   sizeflag = priv.orig_sizeflag;
11613
11614   if (!ckprefix () || rex_used)
11615     {
11616       /* Too many prefixes or unused REX prefixes.  */
11617       for (i = 0;
11618            all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11619            i++)
11620         (*info->fprintf_func) (info->stream, "%s",
11621                                prefix_name (all_prefixes[i], sizeflag));
11622       return 1;
11623     }
11624
11625   insn_codep = codep;
11626
11627   FETCH_DATA (info, codep + 1);
11628   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11629
11630   if (((prefixes & PREFIX_FWAIT)
11631        && ((*codep < 0xd8) || (*codep > 0xdf))))
11632     {
11633       (*info->fprintf_func) (info->stream, "fwait");
11634       return 1;
11635     }
11636
11637   if (*codep == 0x0f)
11638     {
11639       unsigned char threebyte;
11640       FETCH_DATA (info, codep + 2);
11641       threebyte = *++codep;
11642       dp = &dis386_twobyte[threebyte];
11643       need_modrm = twobyte_has_modrm[*codep];
11644       codep++;
11645     }
11646   else
11647     {
11648       dp = &dis386[*codep];
11649       need_modrm = onebyte_has_modrm[*codep];
11650       codep++;
11651     }
11652
11653   if ((prefixes & PREFIX_REPZ))
11654     used_prefixes |= PREFIX_REPZ;
11655   if ((prefixes & PREFIX_REPNZ))
11656     used_prefixes |= PREFIX_REPNZ;
11657   if ((prefixes & PREFIX_LOCK))
11658     used_prefixes |= PREFIX_LOCK;
11659
11660   default_prefixes = 0;
11661   if (prefixes & PREFIX_ADDR)
11662     {
11663       sizeflag ^= AFLAG;
11664       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11665         {
11666           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11667             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11668           else
11669             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11670           default_prefixes |= PREFIX_ADDR;
11671         }
11672     }
11673
11674   if ((prefixes & PREFIX_DATA))
11675     {
11676       sizeflag ^= DFLAG;
11677       if (dp->op[2].bytemode == cond_jump_mode
11678           && dp->op[0].bytemode == v_mode
11679           && !intel_syntax)
11680         {
11681           if (sizeflag & DFLAG)
11682             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11683           else
11684             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11685           default_prefixes |= PREFIX_DATA;
11686         }
11687       else if (rex & REX_W)
11688         {
11689           /* REX_W will override PREFIX_DATA.  */
11690           default_prefixes |= PREFIX_DATA;
11691         }
11692     }
11693
11694   if (need_modrm)
11695     {
11696       FETCH_DATA (info, codep + 1);
11697       modrm.mod = (*codep >> 6) & 3;
11698       modrm.reg = (*codep >> 3) & 7;
11699       modrm.rm = *codep & 7;
11700     }
11701
11702    need_vex = 0;
11703    need_vex_reg = 0;
11704    vex_w_done = 0;
11705
11706   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11707     {
11708       get_sib (info);
11709       dofloat (sizeflag);
11710     }
11711   else
11712     {
11713       dp = get_valid_dis386 (dp, info);
11714       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11715         {
11716           get_sib (info);
11717           for (i = 0; i < MAX_OPERANDS; ++i)
11718             {
11719               obufp = op_out[i];
11720               op_ad = MAX_OPERANDS - 1 - i;
11721               if (dp->op[i].rtn)
11722                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11723             }
11724         }
11725     }
11726
11727   /* See if any prefixes were not used.  If so, print the first one
11728      separately.  If we don't do this, we'll wind up printing an
11729      instruction stream which does not precisely correspond to the
11730      bytes we are disassembling.  */
11731   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11732     {
11733       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11734         if (all_prefixes[i])
11735           {
11736             const char *name;
11737             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11738             if (name == NULL)
11739               name = INTERNAL_DISASSEMBLER_ERROR;
11740             (*info->fprintf_func) (info->stream, "%s", name);
11741             return 1;
11742           }
11743     }
11744
11745   /* Check if the REX prefix is used.  */
11746   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11747     all_prefixes[last_rex_prefix] = 0;
11748
11749   /* Check if the SEG prefix is used.  */
11750   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11751                    | PREFIX_FS | PREFIX_GS)) != 0
11752       && (used_prefixes
11753           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11754     all_prefixes[last_seg_prefix] = 0;
11755
11756   /* Check if the ADDR prefix is used.  */
11757   if ((prefixes & PREFIX_ADDR) != 0
11758       && (used_prefixes & PREFIX_ADDR) != 0)
11759     all_prefixes[last_addr_prefix] = 0;
11760
11761   /* Check if the DATA prefix is used.  */
11762   if ((prefixes & PREFIX_DATA) != 0
11763       && (used_prefixes & PREFIX_DATA) != 0)
11764     all_prefixes[last_data_prefix] = 0;
11765
11766   prefix_length = 0;
11767   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11768     if (all_prefixes[i])
11769       {
11770         const char *name;
11771         name = prefix_name (all_prefixes[i], sizeflag);
11772         if (name == NULL)
11773           abort ();
11774         prefix_length += strlen (name) + 1;
11775         (*info->fprintf_func) (info->stream, "%s ", name);
11776       }
11777
11778   /* Check maximum code length.  */
11779   if ((codep - start_codep) > MAX_CODE_LENGTH)
11780     {
11781       (*info->fprintf_func) (info->stream, "(bad)");
11782       return MAX_CODE_LENGTH;
11783     }
11784
11785   obufp = mnemonicendp;
11786   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11787     oappend (" ");
11788   oappend (" ");
11789   (*info->fprintf_func) (info->stream, "%s", obuf);
11790
11791   /* The enter and bound instructions are printed with operands in the same
11792      order as the intel book; everything else is printed in reverse order.  */
11793   if (intel_syntax || two_source_ops)
11794     {
11795       bfd_vma riprel;
11796
11797       for (i = 0; i < MAX_OPERANDS; ++i)
11798         op_txt[i] = op_out[i];
11799
11800       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11801         {
11802           op_ad = op_index[i];
11803           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11804           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11805           riprel = op_riprel[i];
11806           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11807           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11808         }
11809     }
11810   else
11811     {
11812       for (i = 0; i < MAX_OPERANDS; ++i)
11813         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11814     }
11815
11816   needcomma = 0;
11817   for (i = 0; i < MAX_OPERANDS; ++i)
11818     if (*op_txt[i])
11819       {
11820         if (needcomma)
11821           (*info->fprintf_func) (info->stream, ",");
11822         if (op_index[i] != -1 && !op_riprel[i])
11823           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11824         else
11825           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11826         needcomma = 1;
11827       }
11828
11829   for (i = 0; i < MAX_OPERANDS; i++)
11830     if (op_index[i] != -1 && op_riprel[i])
11831       {
11832         (*info->fprintf_func) (info->stream, "        # ");
11833         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11834                                                 + op_address[op_index[i]]), info);
11835         break;
11836       }
11837   return codep - priv.the_buffer;
11838 }
11839
11840 static const char *float_mem[] = {
11841   /* d8 */
11842   "fadd{s|}",
11843   "fmul{s|}",
11844   "fcom{s|}",
11845   "fcomp{s|}",
11846   "fsub{s|}",
11847   "fsubr{s|}",
11848   "fdiv{s|}",
11849   "fdivr{s|}",
11850   /* d9 */
11851   "fld{s|}",
11852   "(bad)",
11853   "fst{s|}",
11854   "fstp{s|}",
11855   "fldenvIC",
11856   "fldcw",
11857   "fNstenvIC",
11858   "fNstcw",
11859   /* da */
11860   "fiadd{l|}",
11861   "fimul{l|}",
11862   "ficom{l|}",
11863   "ficomp{l|}",
11864   "fisub{l|}",
11865   "fisubr{l|}",
11866   "fidiv{l|}",
11867   "fidivr{l|}",
11868   /* db */
11869   "fild{l|}",
11870   "fisttp{l|}",
11871   "fist{l|}",
11872   "fistp{l|}",
11873   "(bad)",
11874   "fld{t||t|}",
11875   "(bad)",
11876   "fstp{t||t|}",
11877   /* dc */
11878   "fadd{l|}",
11879   "fmul{l|}",
11880   "fcom{l|}",
11881   "fcomp{l|}",
11882   "fsub{l|}",
11883   "fsubr{l|}",
11884   "fdiv{l|}",
11885   "fdivr{l|}",
11886   /* dd */
11887   "fld{l|}",
11888   "fisttp{ll|}",
11889   "fst{l||}",
11890   "fstp{l|}",
11891   "frstorIC",
11892   "(bad)",
11893   "fNsaveIC",
11894   "fNstsw",
11895   /* de */
11896   "fiadd",
11897   "fimul",
11898   "ficom",
11899   "ficomp",
11900   "fisub",
11901   "fisubr",
11902   "fidiv",
11903   "fidivr",
11904   /* df */
11905   "fild",
11906   "fisttp",
11907   "fist",
11908   "fistp",
11909   "fbld",
11910   "fild{ll|}",
11911   "fbstp",
11912   "fistp{ll|}",
11913 };
11914
11915 static const unsigned char float_mem_mode[] = {
11916   /* d8 */
11917   d_mode,
11918   d_mode,
11919   d_mode,
11920   d_mode,
11921   d_mode,
11922   d_mode,
11923   d_mode,
11924   d_mode,
11925   /* d9 */
11926   d_mode,
11927   0,
11928   d_mode,
11929   d_mode,
11930   0,
11931   w_mode,
11932   0,
11933   w_mode,
11934   /* da */
11935   d_mode,
11936   d_mode,
11937   d_mode,
11938   d_mode,
11939   d_mode,
11940   d_mode,
11941   d_mode,
11942   d_mode,
11943   /* db */
11944   d_mode,
11945   d_mode,
11946   d_mode,
11947   d_mode,
11948   0,
11949   t_mode,
11950   0,
11951   t_mode,
11952   /* dc */
11953   q_mode,
11954   q_mode,
11955   q_mode,
11956   q_mode,
11957   q_mode,
11958   q_mode,
11959   q_mode,
11960   q_mode,
11961   /* dd */
11962   q_mode,
11963   q_mode,
11964   q_mode,
11965   q_mode,
11966   0,
11967   0,
11968   0,
11969   w_mode,
11970   /* de */
11971   w_mode,
11972   w_mode,
11973   w_mode,
11974   w_mode,
11975   w_mode,
11976   w_mode,
11977   w_mode,
11978   w_mode,
11979   /* df */
11980   w_mode,
11981   w_mode,
11982   w_mode,
11983   w_mode,
11984   t_mode,
11985   q_mode,
11986   t_mode,
11987   q_mode
11988 };
11989
11990 #define ST { OP_ST, 0 }
11991 #define STi { OP_STi, 0 }
11992
11993 #define FGRPd9_2 NULL, { { NULL, 0 } }
11994 #define FGRPd9_4 NULL, { { NULL, 1 } }
11995 #define FGRPd9_5 NULL, { { NULL, 2 } }
11996 #define FGRPd9_6 NULL, { { NULL, 3 } }
11997 #define FGRPd9_7 NULL, { { NULL, 4 } }
11998 #define FGRPda_5 NULL, { { NULL, 5 } }
11999 #define FGRPdb_4 NULL, { { NULL, 6 } }
12000 #define FGRPde_3 NULL, { { NULL, 7 } }
12001 #define FGRPdf_4 NULL, { { NULL, 8 } }
12002
12003 static const struct dis386 float_reg[][8] = {
12004   /* d8 */
12005   {
12006     { "fadd",   { ST, STi } },
12007     { "fmul",   { ST, STi } },
12008     { "fcom",   { STi } },
12009     { "fcomp",  { STi } },
12010     { "fsub",   { ST, STi } },
12011     { "fsubr",  { ST, STi } },
12012     { "fdiv",   { ST, STi } },
12013     { "fdivr",  { ST, STi } },
12014   },
12015   /* d9 */
12016   {
12017     { "fld",    { STi } },
12018     { "fxch",   { STi } },
12019     { FGRPd9_2 },
12020     { Bad_Opcode },
12021     { FGRPd9_4 },
12022     { FGRPd9_5 },
12023     { FGRPd9_6 },
12024     { FGRPd9_7 },
12025   },
12026   /* da */
12027   {
12028     { "fcmovb", { ST, STi } },
12029     { "fcmove", { ST, STi } },
12030     { "fcmovbe",{ ST, STi } },
12031     { "fcmovu", { ST, STi } },
12032     { Bad_Opcode },
12033     { FGRPda_5 },
12034     { Bad_Opcode },
12035     { Bad_Opcode },
12036   },
12037   /* db */
12038   {
12039     { "fcmovnb",{ ST, STi } },
12040     { "fcmovne",{ ST, STi } },
12041     { "fcmovnbe",{ ST, STi } },
12042     { "fcmovnu",{ ST, STi } },
12043     { FGRPdb_4 },
12044     { "fucomi", { ST, STi } },
12045     { "fcomi",  { ST, STi } },
12046     { Bad_Opcode },
12047   },
12048   /* dc */
12049   {
12050     { "fadd",   { STi, ST } },
12051     { "fmul",   { STi, ST } },
12052     { Bad_Opcode },
12053     { Bad_Opcode },
12054     { "fsub!M", { STi, ST } },
12055     { "fsubM",  { STi, ST } },
12056     { "fdiv!M", { STi, ST } },
12057     { "fdivM",  { STi, ST } },
12058   },
12059   /* dd */
12060   {
12061     { "ffree",  { STi } },
12062     { Bad_Opcode },
12063     { "fst",    { STi } },
12064     { "fstp",   { STi } },
12065     { "fucom",  { STi } },
12066     { "fucomp", { STi } },
12067     { Bad_Opcode },
12068     { Bad_Opcode },
12069   },
12070   /* de */
12071   {
12072     { "faddp",  { STi, ST } },
12073     { "fmulp",  { STi, ST } },
12074     { Bad_Opcode },
12075     { FGRPde_3 },
12076     { "fsub!Mp", { STi, ST } },
12077     { "fsubMp", { STi, ST } },
12078     { "fdiv!Mp", { STi, ST } },
12079     { "fdivMp", { STi, ST } },
12080   },
12081   /* df */
12082   {
12083     { "ffreep", { STi } },
12084     { Bad_Opcode },
12085     { Bad_Opcode },
12086     { Bad_Opcode },
12087     { FGRPdf_4 },
12088     { "fucomip", { ST, STi } },
12089     { "fcomip", { ST, STi } },
12090     { Bad_Opcode },
12091   },
12092 };
12093
12094 static char *fgrps[][8] = {
12095   /* d9_2  0 */
12096   {
12097     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12098   },
12099
12100   /* d9_4  1 */
12101   {
12102     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12103   },
12104
12105   /* d9_5  2 */
12106   {
12107     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12108   },
12109
12110   /* d9_6  3 */
12111   {
12112     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12113   },
12114
12115   /* d9_7  4 */
12116   {
12117     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12118   },
12119
12120   /* da_5  5 */
12121   {
12122     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12123   },
12124
12125   /* db_4  6 */
12126   {
12127     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12128     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12129   },
12130
12131   /* de_3  7 */
12132   {
12133     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12134   },
12135
12136   /* df_4  8 */
12137   {
12138     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12139   },
12140 };
12141
12142 static void
12143 swap_operand (void)
12144 {
12145   mnemonicendp[0] = '.';
12146   mnemonicendp[1] = 's';
12147   mnemonicendp += 2;
12148 }
12149
12150 static void
12151 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12152                int sizeflag ATTRIBUTE_UNUSED)
12153 {
12154   /* Skip mod/rm byte.  */
12155   MODRM_CHECK;
12156   codep++;
12157 }
12158
12159 static void
12160 dofloat (int sizeflag)
12161 {
12162   const struct dis386 *dp;
12163   unsigned char floatop;
12164
12165   floatop = codep[-1];
12166
12167   if (modrm.mod != 3)
12168     {
12169       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12170
12171       putop (float_mem[fp_indx], sizeflag);
12172       obufp = op_out[0];
12173       op_ad = 2;
12174       OP_E (float_mem_mode[fp_indx], sizeflag);
12175       return;
12176     }
12177   /* Skip mod/rm byte.  */
12178   MODRM_CHECK;
12179   codep++;
12180
12181   dp = &float_reg[floatop - 0xd8][modrm.reg];
12182   if (dp->name == NULL)
12183     {
12184       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12185
12186       /* Instruction fnstsw is only one with strange arg.  */
12187       if (floatop == 0xdf && codep[-1] == 0xe0)
12188         strcpy (op_out[0], names16[0]);
12189     }
12190   else
12191     {
12192       putop (dp->name, sizeflag);
12193
12194       obufp = op_out[0];
12195       op_ad = 2;
12196       if (dp->op[0].rtn)
12197         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12198
12199       obufp = op_out[1];
12200       op_ad = 1;
12201       if (dp->op[1].rtn)
12202         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12203     }
12204 }
12205
12206 static void
12207 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12208 {
12209   oappend ("%st" + intel_syntax);
12210 }
12211
12212 static void
12213 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12214 {
12215   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12216   oappend (scratchbuf + intel_syntax);
12217 }
12218
12219 /* Capital letters in template are macros.  */
12220 static int
12221 putop (const char *in_template, int sizeflag)
12222 {
12223   const char *p;
12224   int alt = 0;
12225   int cond = 1;
12226   unsigned int l = 0, len = 1;
12227   char last[4];
12228
12229 #define SAVE_LAST(c)                    \
12230   if (l < len && l < sizeof (last))     \
12231     last[l++] = c;                      \
12232   else                                  \
12233     abort ();
12234
12235   for (p = in_template; *p; p++)
12236     {
12237       switch (*p)
12238         {
12239         default:
12240           *obufp++ = *p;
12241           break;
12242         case '%':
12243           len++;
12244           break;
12245         case '!':
12246           cond = 0;
12247           break;
12248         case '{':
12249           alt = 0;
12250           if (intel_syntax)
12251             {
12252               while (*++p != '|')
12253                 if (*p == '}' || *p == '\0')
12254                   abort ();
12255             }
12256           /* Fall through.  */
12257         case 'I':
12258           alt = 1;
12259           continue;
12260         case '|':
12261           while (*++p != '}')
12262             {
12263               if (*p == '\0')
12264                 abort ();
12265             }
12266           break;
12267         case '}':
12268           break;
12269         case 'A':
12270           if (intel_syntax)
12271             break;
12272           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12273             *obufp++ = 'b';
12274           break;
12275         case 'B':
12276           if (l == 0 && len == 1)
12277             {
12278 case_B:
12279               if (intel_syntax)
12280                 break;
12281               if (sizeflag & SUFFIX_ALWAYS)
12282                 *obufp++ = 'b';
12283             }
12284           else
12285             {
12286               if (l != 1
12287                   || len != 2
12288                   || last[0] != 'L')
12289                 {
12290                   SAVE_LAST (*p);
12291                   break;
12292                 }
12293
12294               if (address_mode == mode_64bit
12295                   && !(prefixes & PREFIX_ADDR))
12296                 {
12297                   *obufp++ = 'a';
12298                   *obufp++ = 'b';
12299                   *obufp++ = 's';
12300                 }
12301
12302               goto case_B;
12303             }
12304           break;
12305         case 'C':
12306           if (intel_syntax && !alt)
12307             break;
12308           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12309             {
12310               if (sizeflag & DFLAG)
12311                 *obufp++ = intel_syntax ? 'd' : 'l';
12312               else
12313                 *obufp++ = intel_syntax ? 'w' : 's';
12314               used_prefixes |= (prefixes & PREFIX_DATA);
12315             }
12316           break;
12317         case 'D':
12318           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12319             break;
12320           USED_REX (REX_W);
12321           if (modrm.mod == 3)
12322             {
12323               if (rex & REX_W)
12324                 *obufp++ = 'q';
12325               else
12326                 {
12327                   if (sizeflag & DFLAG)
12328                     *obufp++ = intel_syntax ? 'd' : 'l';
12329                   else
12330                     *obufp++ = 'w';
12331                   used_prefixes |= (prefixes & PREFIX_DATA);
12332                 }
12333             }
12334           else
12335             *obufp++ = 'w';
12336           break;
12337         case 'E':               /* For jcxz/jecxz */
12338           if (address_mode == mode_64bit)
12339             {
12340               if (sizeflag & AFLAG)
12341                 *obufp++ = 'r';
12342               else
12343                 *obufp++ = 'e';
12344             }
12345           else
12346             if (sizeflag & AFLAG)
12347               *obufp++ = 'e';
12348           used_prefixes |= (prefixes & PREFIX_ADDR);
12349           break;
12350         case 'F':
12351           if (intel_syntax)
12352             break;
12353           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12354             {
12355               if (sizeflag & AFLAG)
12356                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12357               else
12358                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12359               used_prefixes |= (prefixes & PREFIX_ADDR);
12360             }
12361           break;
12362         case 'G':
12363           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12364             break;
12365           if ((rex & REX_W) || (sizeflag & DFLAG))
12366             *obufp++ = 'l';
12367           else
12368             *obufp++ = 'w';
12369           if (!(rex & REX_W))
12370             used_prefixes |= (prefixes & PREFIX_DATA);
12371           break;
12372         case 'H':
12373           if (intel_syntax)
12374             break;
12375           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12376               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12377             {
12378               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12379               *obufp++ = ',';
12380               *obufp++ = 'p';
12381               if (prefixes & PREFIX_DS)
12382                 *obufp++ = 't';
12383               else
12384                 *obufp++ = 'n';
12385             }
12386           break;
12387         case 'J':
12388           if (intel_syntax)
12389             break;
12390           *obufp++ = 'l';
12391           break;
12392         case 'K':
12393           USED_REX (REX_W);
12394           if (rex & REX_W)
12395             *obufp++ = 'q';
12396           else
12397             *obufp++ = 'd';
12398           break;
12399         case 'Z':
12400           if (intel_syntax)
12401             break;
12402           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12403             {
12404               *obufp++ = 'q';
12405               break;
12406             }
12407           /* Fall through.  */
12408           goto case_L;
12409         case 'L':
12410           if (l != 0 || len != 1)
12411             {
12412               SAVE_LAST (*p);
12413               break;
12414             }
12415 case_L:
12416           if (intel_syntax)
12417             break;
12418           if (sizeflag & SUFFIX_ALWAYS)
12419             *obufp++ = 'l';
12420           break;
12421         case 'M':
12422           if (intel_mnemonic != cond)
12423             *obufp++ = 'r';
12424           break;
12425         case 'N':
12426           if ((prefixes & PREFIX_FWAIT) == 0)
12427             *obufp++ = 'n';
12428           else
12429             used_prefixes |= PREFIX_FWAIT;
12430           break;
12431         case 'O':
12432           USED_REX (REX_W);
12433           if (rex & REX_W)
12434             *obufp++ = 'o';
12435           else if (intel_syntax && (sizeflag & DFLAG))
12436             *obufp++ = 'q';
12437           else
12438             *obufp++ = 'd';
12439           if (!(rex & REX_W))
12440             used_prefixes |= (prefixes & PREFIX_DATA);
12441           break;
12442         case 'T':
12443           if (!intel_syntax
12444               && address_mode == mode_64bit
12445               && (sizeflag & DFLAG))
12446             {
12447               *obufp++ = 'q';
12448               break;
12449             }
12450           /* Fall through.  */
12451         case 'P':
12452           if (intel_syntax)
12453             {
12454               if ((rex & REX_W) == 0
12455                   && (prefixes & PREFIX_DATA))
12456                 {
12457                   if ((sizeflag & DFLAG) == 0)
12458                     *obufp++ = 'w';
12459                    used_prefixes |= (prefixes & PREFIX_DATA);
12460                 }
12461               break;
12462             }
12463           if ((prefixes & PREFIX_DATA)
12464               || (rex & REX_W)
12465               || (sizeflag & SUFFIX_ALWAYS))
12466             {
12467               USED_REX (REX_W);
12468               if (rex & REX_W)
12469                 *obufp++ = 'q';
12470               else
12471                 {
12472                    if (sizeflag & DFLAG)
12473                       *obufp++ = 'l';
12474                    else
12475                      *obufp++ = 'w';
12476                    used_prefixes |= (prefixes & PREFIX_DATA);
12477                 }
12478             }
12479           break;
12480         case 'U':
12481           if (intel_syntax)
12482             break;
12483           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12484             {
12485               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12486                 *obufp++ = 'q';
12487               break;
12488             }
12489           /* Fall through.  */
12490           goto case_Q;
12491         case 'Q':
12492           if (l == 0 && len == 1)
12493             {
12494 case_Q:
12495               if (intel_syntax && !alt)
12496                 break;
12497               USED_REX (REX_W);
12498               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12499                 {
12500                   if (rex & REX_W)
12501                     *obufp++ = 'q';
12502                   else
12503                     {
12504                       if (sizeflag & DFLAG)
12505                         *obufp++ = intel_syntax ? 'd' : 'l';
12506                       else
12507                         *obufp++ = 'w';
12508                       used_prefixes |= (prefixes & PREFIX_DATA);
12509                     }
12510                 }
12511             }
12512           else
12513             {
12514               if (l != 1 || len != 2 || last[0] != 'L')
12515                 {
12516                   SAVE_LAST (*p);
12517                   break;
12518                 }
12519               if (intel_syntax
12520                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12521                 break;
12522               if ((rex & REX_W))
12523                 {
12524                   USED_REX (REX_W);
12525                   *obufp++ = 'q';
12526                 }
12527               else
12528                 *obufp++ = 'l';
12529             }
12530           break;
12531         case 'R':
12532           USED_REX (REX_W);
12533           if (rex & REX_W)
12534             *obufp++ = 'q';
12535           else if (sizeflag & DFLAG)
12536             {
12537               if (intel_syntax)
12538                   *obufp++ = 'd';
12539               else
12540                   *obufp++ = 'l';
12541             }
12542           else
12543             *obufp++ = 'w';
12544           if (intel_syntax && !p[1]
12545               && ((rex & REX_W) || (sizeflag & DFLAG)))
12546             *obufp++ = 'e';
12547           if (!(rex & REX_W))
12548             used_prefixes |= (prefixes & PREFIX_DATA);
12549           break;
12550         case 'V':
12551           if (l == 0 && len == 1)
12552             {
12553               if (intel_syntax)
12554                 break;
12555               if (address_mode == mode_64bit && (sizeflag & DFLAG))
12556                 {
12557                   if (sizeflag & SUFFIX_ALWAYS)
12558                     *obufp++ = 'q';
12559                   break;
12560                 }
12561             }
12562           else
12563             {
12564               if (l != 1
12565                   || len != 2
12566                   || last[0] != 'L')
12567                 {
12568                   SAVE_LAST (*p);
12569                   break;
12570                 }
12571
12572               if (rex & REX_W)
12573                 {
12574                   *obufp++ = 'a';
12575                   *obufp++ = 'b';
12576                   *obufp++ = 's';
12577                 }
12578             }
12579           /* Fall through.  */
12580           goto case_S;
12581         case 'S':
12582           if (l == 0 && len == 1)
12583             {
12584 case_S:
12585               if (intel_syntax)
12586                 break;
12587               if (sizeflag & SUFFIX_ALWAYS)
12588                 {
12589                   if (rex & REX_W)
12590                     *obufp++ = 'q';
12591                   else
12592                     {
12593                       if (sizeflag & DFLAG)
12594                         *obufp++ = 'l';
12595                       else
12596                         *obufp++ = 'w';
12597                       used_prefixes |= (prefixes & PREFIX_DATA);
12598                     }
12599                 }
12600             }
12601           else
12602             {
12603               if (l != 1
12604                   || len != 2
12605                   || last[0] != 'L')
12606                 {
12607                   SAVE_LAST (*p);
12608                   break;
12609                 }
12610
12611               if (address_mode == mode_64bit
12612                   && !(prefixes & PREFIX_ADDR))
12613                 {
12614                   *obufp++ = 'a';
12615                   *obufp++ = 'b';
12616                   *obufp++ = 's';
12617                 }
12618
12619               goto case_S;
12620             }
12621           break;
12622         case 'X':
12623           if (l != 0 || len != 1)
12624             {
12625               SAVE_LAST (*p);
12626               break;
12627             }
12628           if (need_vex && vex.prefix)
12629             {
12630               if (vex.prefix == DATA_PREFIX_OPCODE)
12631                 *obufp++ = 'd';
12632               else
12633                 *obufp++ = 's';
12634             }
12635           else
12636             {
12637               if (prefixes & PREFIX_DATA)
12638                 *obufp++ = 'd';
12639               else
12640                 *obufp++ = 's';
12641               used_prefixes |= (prefixes & PREFIX_DATA);
12642             }
12643           break;
12644         case 'Y':
12645           if (l == 0 && len == 1)
12646             {
12647               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12648                 break;
12649               if (rex & REX_W)
12650                 {
12651                   USED_REX (REX_W);
12652                   *obufp++ = 'q';
12653                 }
12654               break;
12655             }
12656           else
12657             {
12658               if (l != 1 || len != 2 || last[0] != 'X')
12659                 {
12660                   SAVE_LAST (*p);
12661                   break;
12662                 }
12663               if (!need_vex)
12664                 abort ();
12665               if (intel_syntax
12666                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12667                 break;
12668               switch (vex.length)
12669                 {
12670                 case 128:
12671                   *obufp++ = 'x';
12672                   break;
12673                 case 256:
12674                   *obufp++ = 'y';
12675                   break;
12676                 default:
12677                   abort ();
12678                 }
12679             }
12680           break;
12681         case 'W':
12682           if (l == 0 && len == 1)
12683             {
12684               /* operand size flag for cwtl, cbtw */
12685               USED_REX (REX_W);
12686               if (rex & REX_W)
12687                 {
12688                   if (intel_syntax)
12689                     *obufp++ = 'd';
12690                   else
12691                     *obufp++ = 'l';
12692                 }
12693               else if (sizeflag & DFLAG)
12694                 *obufp++ = 'w';
12695               else
12696                 *obufp++ = 'b';
12697               if (!(rex & REX_W))
12698                 used_prefixes |= (prefixes & PREFIX_DATA);
12699             }
12700           else
12701             {
12702               if (l != 1 || len != 2 || last[0] != 'X')
12703                 {
12704                   SAVE_LAST (*p);
12705                   break;
12706                 }
12707               if (!need_vex)
12708                 abort ();
12709               *obufp++ = vex.w ? 'd': 's';
12710             }
12711           break;
12712         }
12713       alt = 0;
12714     }
12715   *obufp = 0;
12716   mnemonicendp = obufp;
12717   return 0;
12718 }
12719
12720 static void
12721 oappend (const char *s)
12722 {
12723   obufp = stpcpy (obufp, s);
12724 }
12725
12726 static void
12727 append_seg (void)
12728 {
12729   if (prefixes & PREFIX_CS)
12730     {
12731       used_prefixes |= PREFIX_CS;
12732       oappend ("%cs:" + intel_syntax);
12733     }
12734   if (prefixes & PREFIX_DS)
12735     {
12736       used_prefixes |= PREFIX_DS;
12737       oappend ("%ds:" + intel_syntax);
12738     }
12739   if (prefixes & PREFIX_SS)
12740     {
12741       used_prefixes |= PREFIX_SS;
12742       oappend ("%ss:" + intel_syntax);
12743     }
12744   if (prefixes & PREFIX_ES)
12745     {
12746       used_prefixes |= PREFIX_ES;
12747       oappend ("%es:" + intel_syntax);
12748     }
12749   if (prefixes & PREFIX_FS)
12750     {
12751       used_prefixes |= PREFIX_FS;
12752       oappend ("%fs:" + intel_syntax);
12753     }
12754   if (prefixes & PREFIX_GS)
12755     {
12756       used_prefixes |= PREFIX_GS;
12757       oappend ("%gs:" + intel_syntax);
12758     }
12759 }
12760
12761 static void
12762 OP_indirE (int bytemode, int sizeflag)
12763 {
12764   if (!intel_syntax)
12765     oappend ("*");
12766   OP_E (bytemode, sizeflag);
12767 }
12768
12769 static void
12770 print_operand_value (char *buf, int hex, bfd_vma disp)
12771 {
12772   if (address_mode == mode_64bit)
12773     {
12774       if (hex)
12775         {
12776           char tmp[30];
12777           int i;
12778           buf[0] = '0';
12779           buf[1] = 'x';
12780           sprintf_vma (tmp, disp);
12781           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12782           strcpy (buf + 2, tmp + i);
12783         }
12784       else
12785         {
12786           bfd_signed_vma v = disp;
12787           char tmp[30];
12788           int i;
12789           if (v < 0)
12790             {
12791               *(buf++) = '-';
12792               v = -disp;
12793               /* Check for possible overflow on 0x8000000000000000.  */
12794               if (v < 0)
12795                 {
12796                   strcpy (buf, "9223372036854775808");
12797                   return;
12798                 }
12799             }
12800           if (!v)
12801             {
12802               strcpy (buf, "0");
12803               return;
12804             }
12805
12806           i = 0;
12807           tmp[29] = 0;
12808           while (v)
12809             {
12810               tmp[28 - i] = (v % 10) + '0';
12811               v /= 10;
12812               i++;
12813             }
12814           strcpy (buf, tmp + 29 - i);
12815         }
12816     }
12817   else
12818     {
12819       if (hex)
12820         sprintf (buf, "0x%x", (unsigned int) disp);
12821       else
12822         sprintf (buf, "%d", (int) disp);
12823     }
12824 }
12825
12826 /* Put DISP in BUF as signed hex number.  */
12827
12828 static void
12829 print_displacement (char *buf, bfd_vma disp)
12830 {
12831   bfd_signed_vma val = disp;
12832   char tmp[30];
12833   int i, j = 0;
12834
12835   if (val < 0)
12836     {
12837       buf[j++] = '-';
12838       val = -disp;
12839
12840       /* Check for possible overflow.  */
12841       if (val < 0)
12842         {
12843           switch (address_mode)
12844             {
12845             case mode_64bit:
12846               strcpy (buf + j, "0x8000000000000000");
12847               break;
12848             case mode_32bit:
12849               strcpy (buf + j, "0x80000000");
12850               break;
12851             case mode_16bit:
12852               strcpy (buf + j, "0x8000");
12853               break;
12854             }
12855           return;
12856         }
12857     }
12858
12859   buf[j++] = '0';
12860   buf[j++] = 'x';
12861
12862   sprintf_vma (tmp, (bfd_vma) val);
12863   for (i = 0; tmp[i] == '0'; i++)
12864     continue;
12865   if (tmp[i] == '\0')
12866     i--;
12867   strcpy (buf + j, tmp + i);
12868 }
12869
12870 static void
12871 intel_operand_size (int bytemode, int sizeflag)
12872 {
12873   switch (bytemode)
12874     {
12875     case b_mode:
12876     case b_swap_mode:
12877     case dqb_mode:
12878       oappend ("BYTE PTR ");
12879       break;
12880     case w_mode:
12881     case dqw_mode:
12882       oappend ("WORD PTR ");
12883       break;
12884     case stack_v_mode:
12885       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12886         {
12887           oappend ("QWORD PTR ");
12888           break;
12889         }
12890       /* FALLTHRU */
12891     case v_mode:
12892     case v_swap_mode:
12893     case dq_mode:
12894       USED_REX (REX_W);
12895       if (rex & REX_W)
12896         oappend ("QWORD PTR ");
12897       else
12898         {
12899           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12900             oappend ("DWORD PTR ");
12901           else
12902             oappend ("WORD PTR ");
12903           used_prefixes |= (prefixes & PREFIX_DATA);
12904         }
12905       break;
12906     case z_mode:
12907       if ((rex & REX_W) || (sizeflag & DFLAG))
12908         *obufp++ = 'D';
12909       oappend ("WORD PTR ");
12910       if (!(rex & REX_W))
12911         used_prefixes |= (prefixes & PREFIX_DATA);
12912       break;
12913     case a_mode:
12914       if (sizeflag & DFLAG)
12915         oappend ("QWORD PTR ");
12916       else
12917         oappend ("DWORD PTR ");
12918       used_prefixes |= (prefixes & PREFIX_DATA);
12919       break;
12920     case d_mode:
12921     case d_scalar_mode:
12922     case d_scalar_swap_mode:
12923     case d_swap_mode:
12924     case dqd_mode:
12925       oappend ("DWORD PTR ");
12926       break;
12927     case q_mode:
12928     case q_scalar_mode:
12929     case q_scalar_swap_mode:
12930     case q_swap_mode:
12931       oappend ("QWORD PTR ");
12932       break;
12933     case m_mode:
12934       if (address_mode == mode_64bit)
12935         oappend ("QWORD PTR ");
12936       else
12937         oappend ("DWORD PTR ");
12938       break;
12939     case f_mode:
12940       if (sizeflag & DFLAG)
12941         oappend ("FWORD PTR ");
12942       else
12943         oappend ("DWORD PTR ");
12944       used_prefixes |= (prefixes & PREFIX_DATA);
12945       break;
12946     case t_mode:
12947       oappend ("TBYTE PTR ");
12948       break;
12949     case x_mode:
12950     case x_swap_mode:
12951       if (need_vex)
12952         {
12953           switch (vex.length)
12954             {
12955             case 128:
12956               oappend ("XMMWORD PTR ");
12957               break;
12958             case 256:
12959               oappend ("YMMWORD PTR ");
12960               break;
12961             default:
12962               abort ();
12963             }
12964         }
12965       else
12966         oappend ("XMMWORD PTR ");
12967       break;
12968     case xmm_mode:
12969       oappend ("XMMWORD PTR ");
12970       break;
12971     case xmmq_mode:
12972       if (!need_vex)
12973         abort ();
12974
12975       switch (vex.length)
12976         {
12977         case 128:
12978           oappend ("QWORD PTR ");
12979           break;
12980         case 256:
12981           oappend ("XMMWORD PTR ");
12982           break;
12983         default:
12984           abort ();
12985         }
12986       break;
12987     case ymmq_mode:
12988       if (!need_vex)
12989         abort ();
12990
12991       switch (vex.length)
12992         {
12993         case 128:
12994           oappend ("QWORD PTR ");
12995           break;
12996         case 256:
12997           oappend ("YMMWORD PTR ");
12998           break;
12999         default:
13000           abort ();
13001         }
13002       break;
13003     case o_mode:
13004       oappend ("OWORD PTR ");
13005       break;
13006     case vex_w_dq_mode:
13007     case vex_scalar_w_dq_mode:
13008       if (!need_vex)
13009         abort ();
13010
13011       if (vex.w)
13012         oappend ("QWORD PTR ");
13013       else
13014         oappend ("DWORD PTR ");
13015       break;
13016     default:
13017       break;
13018     }
13019 }
13020
13021 static void
13022 OP_E_register (int bytemode, int sizeflag)
13023 {
13024   int reg = modrm.rm;
13025   const char **names;
13026
13027   USED_REX (REX_B);
13028   if ((rex & REX_B))
13029     reg += 8;
13030
13031   if ((sizeflag & SUFFIX_ALWAYS)
13032       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
13033     swap_operand ();
13034
13035   switch (bytemode)
13036     {
13037     case b_mode:
13038     case b_swap_mode:
13039       USED_REX (0);
13040       if (rex)
13041         names = names8rex;
13042       else
13043         names = names8;
13044       break;
13045     case w_mode:
13046       names = names16;
13047       break;
13048     case d_mode:
13049       names = names32;
13050       break;
13051     case q_mode:
13052       names = names64;
13053       break;
13054     case m_mode:
13055       names = address_mode == mode_64bit ? names64 : names32;
13056       break;
13057     case stack_v_mode:
13058       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13059         {
13060           names = names64;
13061           break;
13062         }
13063       bytemode = v_mode;
13064       /* FALLTHRU */
13065     case v_mode:
13066     case v_swap_mode:
13067     case dq_mode:
13068     case dqb_mode:
13069     case dqd_mode:
13070     case dqw_mode:
13071       USED_REX (REX_W);
13072       if (rex & REX_W)
13073         names = names64;
13074       else
13075         {
13076           if ((sizeflag & DFLAG)
13077               || (bytemode != v_mode
13078                   && bytemode != v_swap_mode))
13079             names = names32;
13080           else
13081             names = names16;
13082           used_prefixes |= (prefixes & PREFIX_DATA);
13083         }
13084       break;
13085     case 0:
13086       return;
13087     default:
13088       oappend (INTERNAL_DISASSEMBLER_ERROR);
13089       return;
13090     }
13091   oappend (names[reg]);
13092 }
13093
13094 static void
13095 OP_E_memory (int bytemode, int sizeflag)
13096 {
13097   bfd_vma disp = 0;
13098   int add = (rex & REX_B) ? 8 : 0;
13099   int riprel = 0;
13100
13101   USED_REX (REX_B);
13102   if (intel_syntax)
13103     intel_operand_size (bytemode, sizeflag);
13104   append_seg ();
13105
13106   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13107     {
13108       /* 32/64 bit address mode */
13109       int havedisp;
13110       int havesib;
13111       int havebase;
13112       int haveindex;
13113       int needindex;
13114       int base, rbase;
13115       int vindex = 0;
13116       int scale = 0;
13117
13118       havesib = 0;
13119       havebase = 1;
13120       haveindex = 0;
13121       base = modrm.rm;
13122
13123       if (base == 4)
13124         {
13125           havesib = 1;
13126           vindex = sib.index;
13127           scale = sib.scale;
13128           base = sib.base;
13129           USED_REX (REX_X);
13130           if (rex & REX_X)
13131             vindex += 8;
13132           haveindex = vindex != 4;
13133           codep++;
13134         }
13135       rbase = base + add;
13136
13137       switch (modrm.mod)
13138         {
13139         case 0:
13140           if (base == 5)
13141             {
13142               havebase = 0;
13143               if (address_mode == mode_64bit && !havesib)
13144                 riprel = 1;
13145               disp = get32s ();
13146             }
13147           break;
13148         case 1:
13149           FETCH_DATA (the_info, codep + 1);
13150           disp = *codep++;
13151           if ((disp & 0x80) != 0)
13152             disp -= 0x100;
13153           break;
13154         case 2:
13155           disp = get32s ();
13156           break;
13157         }
13158
13159       /* In 32bit mode, we need index register to tell [offset] from
13160          [eiz*1 + offset].  */
13161       needindex = (havesib
13162                    && !havebase
13163                    && !haveindex
13164                    && address_mode == mode_32bit);
13165       havedisp = (havebase
13166                   || needindex
13167                   || (havesib && (haveindex || scale != 0)));
13168
13169       if (!intel_syntax)
13170         if (modrm.mod != 0 || base == 5)
13171           {
13172             if (havedisp || riprel)
13173               print_displacement (scratchbuf, disp);
13174             else
13175               print_operand_value (scratchbuf, 1, disp);
13176             oappend (scratchbuf);
13177             if (riprel)
13178               {
13179                 set_op (disp, 1);
13180                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
13181               }
13182           }
13183
13184       if (havebase || haveindex || riprel)
13185         used_prefixes |= PREFIX_ADDR;
13186
13187       if (havedisp || (intel_syntax && riprel))
13188         {
13189           *obufp++ = open_char;
13190           if (intel_syntax && riprel)
13191             {
13192               set_op (disp, 1);
13193               oappend (sizeflag & AFLAG ? "rip" : "eip");
13194             }
13195           *obufp = '\0';
13196           if (havebase)
13197             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13198                      ? names64[rbase] : names32[rbase]);
13199           if (havesib)
13200             {
13201               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
13202                  print index to tell base + index from base.  */
13203               if (scale != 0
13204                   || needindex
13205                   || haveindex
13206                   || (havebase && base != ESP_REG_NUM))
13207                 {
13208                   if (!intel_syntax || havebase)
13209                     {
13210                       *obufp++ = separator_char;
13211                       *obufp = '\0';
13212                     }
13213                   if (haveindex)
13214                     oappend (address_mode == mode_64bit
13215                              && (sizeflag & AFLAG)
13216                              ? names64[vindex] : names32[vindex]);
13217                   else
13218                     oappend (address_mode == mode_64bit
13219                              && (sizeflag & AFLAG)
13220                              ? index64 : index32);
13221
13222                   *obufp++ = scale_char;
13223                   *obufp = '\0';
13224                   sprintf (scratchbuf, "%d", 1 << scale);
13225                   oappend (scratchbuf);
13226                 }
13227             }
13228           if (intel_syntax
13229               && (disp || modrm.mod != 0 || base == 5))
13230             {
13231               if (!havedisp || (bfd_signed_vma) disp >= 0)
13232                 {
13233                   *obufp++ = '+';
13234                   *obufp = '\0';
13235                 }
13236               else if (modrm.mod != 1 && disp != -disp)
13237                 {
13238                   *obufp++ = '-';
13239                   *obufp = '\0';
13240                   disp = - (bfd_signed_vma) disp;
13241                 }
13242
13243               if (havedisp)
13244                 print_displacement (scratchbuf, disp);
13245               else
13246                 print_operand_value (scratchbuf, 1, disp);
13247               oappend (scratchbuf);
13248             }
13249
13250           *obufp++ = close_char;
13251           *obufp = '\0';
13252         }
13253       else if (intel_syntax)
13254         {
13255           if (modrm.mod != 0 || base == 5)
13256             {
13257               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13258                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13259                 ;
13260               else
13261                 {
13262                   oappend (names_seg[ds_reg - es_reg]);
13263                   oappend (":");
13264                 }
13265               print_operand_value (scratchbuf, 1, disp);
13266               oappend (scratchbuf);
13267             }
13268         }
13269     }
13270   else
13271     {
13272       /* 16 bit address mode */
13273       used_prefixes |= prefixes & PREFIX_ADDR;
13274       switch (modrm.mod)
13275         {
13276         case 0:
13277           if (modrm.rm == 6)
13278             {
13279               disp = get16 ();
13280               if ((disp & 0x8000) != 0)
13281                 disp -= 0x10000;
13282             }
13283           break;
13284         case 1:
13285           FETCH_DATA (the_info, codep + 1);
13286           disp = *codep++;
13287           if ((disp & 0x80) != 0)
13288             disp -= 0x100;
13289           break;
13290         case 2:
13291           disp = get16 ();
13292           if ((disp & 0x8000) != 0)
13293             disp -= 0x10000;
13294           break;
13295         }
13296
13297       if (!intel_syntax)
13298         if (modrm.mod != 0 || modrm.rm == 6)
13299           {
13300             print_displacement (scratchbuf, disp);
13301             oappend (scratchbuf);
13302           }
13303
13304       if (modrm.mod != 0 || modrm.rm != 6)
13305         {
13306           *obufp++ = open_char;
13307           *obufp = '\0';
13308           oappend (index16[modrm.rm]);
13309           if (intel_syntax
13310               && (disp || modrm.mod != 0 || modrm.rm == 6))
13311             {
13312               if ((bfd_signed_vma) disp >= 0)
13313                 {
13314                   *obufp++ = '+';
13315                   *obufp = '\0';
13316                 }
13317               else if (modrm.mod != 1)
13318                 {
13319                   *obufp++ = '-';
13320                   *obufp = '\0';
13321                   disp = - (bfd_signed_vma) disp;
13322                 }
13323
13324               print_displacement (scratchbuf, disp);
13325               oappend (scratchbuf);
13326             }
13327
13328           *obufp++ = close_char;
13329           *obufp = '\0';
13330         }
13331       else if (intel_syntax)
13332         {
13333           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13334                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13335             ;
13336           else
13337             {
13338               oappend (names_seg[ds_reg - es_reg]);
13339               oappend (":");
13340             }
13341           print_operand_value (scratchbuf, 1, disp & 0xffff);
13342           oappend (scratchbuf);
13343         }
13344     }
13345 }
13346
13347 static void
13348 OP_E (int bytemode, int sizeflag)
13349 {
13350   /* Skip mod/rm byte.  */
13351   MODRM_CHECK;
13352   codep++;
13353
13354   if (modrm.mod == 3)
13355     OP_E_register (bytemode, sizeflag);
13356   else
13357     OP_E_memory (bytemode, sizeflag);
13358 }
13359
13360 static void
13361 OP_G (int bytemode, int sizeflag)
13362 {
13363   int add = 0;
13364   USED_REX (REX_R);
13365   if (rex & REX_R)
13366     add += 8;
13367   switch (bytemode)
13368     {
13369     case b_mode:
13370       USED_REX (0);
13371       if (rex)
13372         oappend (names8rex[modrm.reg + add]);
13373       else
13374         oappend (names8[modrm.reg + add]);
13375       break;
13376     case w_mode:
13377       oappend (names16[modrm.reg + add]);
13378       break;
13379     case d_mode:
13380       oappend (names32[modrm.reg + add]);
13381       break;
13382     case q_mode:
13383       oappend (names64[modrm.reg + add]);
13384       break;
13385     case v_mode:
13386     case dq_mode:
13387     case dqb_mode:
13388     case dqd_mode:
13389     case dqw_mode:
13390       USED_REX (REX_W);
13391       if (rex & REX_W)
13392         oappend (names64[modrm.reg + add]);
13393       else
13394         {
13395           if ((sizeflag & DFLAG) || bytemode != v_mode)
13396             oappend (names32[modrm.reg + add]);
13397           else
13398             oappend (names16[modrm.reg + add]);
13399           used_prefixes |= (prefixes & PREFIX_DATA);
13400         }
13401       break;
13402     case m_mode:
13403       if (address_mode == mode_64bit)
13404         oappend (names64[modrm.reg + add]);
13405       else
13406         oappend (names32[modrm.reg + add]);
13407       break;
13408     default:
13409       oappend (INTERNAL_DISASSEMBLER_ERROR);
13410       break;
13411     }
13412 }
13413
13414 static bfd_vma
13415 get64 (void)
13416 {
13417   bfd_vma x;
13418 #ifdef BFD64
13419   unsigned int a;
13420   unsigned int b;
13421
13422   FETCH_DATA (the_info, codep + 8);
13423   a = *codep++ & 0xff;
13424   a |= (*codep++ & 0xff) << 8;
13425   a |= (*codep++ & 0xff) << 16;
13426   a |= (*codep++ & 0xff) << 24;
13427   b = *codep++ & 0xff;
13428   b |= (*codep++ & 0xff) << 8;
13429   b |= (*codep++ & 0xff) << 16;
13430   b |= (*codep++ & 0xff) << 24;
13431   x = a + ((bfd_vma) b << 32);
13432 #else
13433   abort ();
13434   x = 0;
13435 #endif
13436   return x;
13437 }
13438
13439 static bfd_signed_vma
13440 get32 (void)
13441 {
13442   bfd_signed_vma x = 0;
13443
13444   FETCH_DATA (the_info, codep + 4);
13445   x = *codep++ & (bfd_signed_vma) 0xff;
13446   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13447   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13448   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13449   return x;
13450 }
13451
13452 static bfd_signed_vma
13453 get32s (void)
13454 {
13455   bfd_signed_vma x = 0;
13456
13457   FETCH_DATA (the_info, codep + 4);
13458   x = *codep++ & (bfd_signed_vma) 0xff;
13459   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13460   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13461   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13462
13463   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13464
13465   return x;
13466 }
13467
13468 static int
13469 get16 (void)
13470 {
13471   int x = 0;
13472
13473   FETCH_DATA (the_info, codep + 2);
13474   x = *codep++ & 0xff;
13475   x |= (*codep++ & 0xff) << 8;
13476   return x;
13477 }
13478
13479 static void
13480 set_op (bfd_vma op, int riprel)
13481 {
13482   op_index[op_ad] = op_ad;
13483   if (address_mode == mode_64bit)
13484     {
13485       op_address[op_ad] = op;
13486       op_riprel[op_ad] = riprel;
13487     }
13488   else
13489     {
13490       /* Mask to get a 32-bit address.  */
13491       op_address[op_ad] = op & 0xffffffff;
13492       op_riprel[op_ad] = riprel & 0xffffffff;
13493     }
13494 }
13495
13496 static void
13497 OP_REG (int code, int sizeflag)
13498 {
13499   const char *s;
13500   int add;
13501   USED_REX (REX_B);
13502   if (rex & REX_B)
13503     add = 8;
13504   else
13505     add = 0;
13506
13507   switch (code)
13508     {
13509     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13510     case sp_reg: case bp_reg: case si_reg: case di_reg:
13511       s = names16[code - ax_reg + add];
13512       break;
13513     case es_reg: case ss_reg: case cs_reg:
13514     case ds_reg: case fs_reg: case gs_reg:
13515       s = names_seg[code - es_reg + add];
13516       break;
13517     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13518     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13519       USED_REX (0);
13520       if (rex)
13521         s = names8rex[code - al_reg + add];
13522       else
13523         s = names8[code - al_reg];
13524       break;
13525     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13526     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13527       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13528         {
13529           s = names64[code - rAX_reg + add];
13530           break;
13531         }
13532       code += eAX_reg - rAX_reg;
13533       /* Fall through.  */
13534     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13535     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13536       USED_REX (REX_W);
13537       if (rex & REX_W)
13538         s = names64[code - eAX_reg + add];
13539       else
13540         {
13541           if (sizeflag & DFLAG)
13542             s = names32[code - eAX_reg + add];
13543           else
13544             s = names16[code - eAX_reg + add];
13545           used_prefixes |= (prefixes & PREFIX_DATA);
13546         }
13547       break;
13548     default:
13549       s = INTERNAL_DISASSEMBLER_ERROR;
13550       break;
13551     }
13552   oappend (s);
13553 }
13554
13555 static void
13556 OP_IMREG (int code, int sizeflag)
13557 {
13558   const char *s;
13559
13560   switch (code)
13561     {
13562     case indir_dx_reg:
13563       if (intel_syntax)
13564         s = "dx";
13565       else
13566         s = "(%dx)";
13567       break;
13568     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13569     case sp_reg: case bp_reg: case si_reg: case di_reg:
13570       s = names16[code - ax_reg];
13571       break;
13572     case es_reg: case ss_reg: case cs_reg:
13573     case ds_reg: case fs_reg: case gs_reg:
13574       s = names_seg[code - es_reg];
13575       break;
13576     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13577     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13578       USED_REX (0);
13579       if (rex)
13580         s = names8rex[code - al_reg];
13581       else
13582         s = names8[code - al_reg];
13583       break;
13584     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13585     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13586       USED_REX (REX_W);
13587       if (rex & REX_W)
13588         s = names64[code - eAX_reg];
13589       else
13590         {
13591           if (sizeflag & DFLAG)
13592             s = names32[code - eAX_reg];
13593           else
13594             s = names16[code - eAX_reg];
13595           used_prefixes |= (prefixes & PREFIX_DATA);
13596         }
13597       break;
13598     case z_mode_ax_reg:
13599       if ((rex & REX_W) || (sizeflag & DFLAG))
13600         s = *names32;
13601       else
13602         s = *names16;
13603       if (!(rex & REX_W))
13604         used_prefixes |= (prefixes & PREFIX_DATA);
13605       break;
13606     default:
13607       s = INTERNAL_DISASSEMBLER_ERROR;
13608       break;
13609     }
13610   oappend (s);
13611 }
13612
13613 static void
13614 OP_I (int bytemode, int sizeflag)
13615 {
13616   bfd_signed_vma op;
13617   bfd_signed_vma mask = -1;
13618
13619   switch (bytemode)
13620     {
13621     case b_mode:
13622       FETCH_DATA (the_info, codep + 1);
13623       op = *codep++;
13624       mask = 0xff;
13625       break;
13626     case q_mode:
13627       if (address_mode == mode_64bit)
13628         {
13629           op = get32s ();
13630           break;
13631         }
13632       /* Fall through.  */
13633     case v_mode:
13634       USED_REX (REX_W);
13635       if (rex & REX_W)
13636         op = get32s ();
13637       else
13638         {
13639           if (sizeflag & DFLAG)
13640             {
13641               op = get32 ();
13642               mask = 0xffffffff;
13643             }
13644           else
13645             {
13646               op = get16 ();
13647               mask = 0xfffff;
13648             }
13649           used_prefixes |= (prefixes & PREFIX_DATA);
13650         }
13651       break;
13652     case w_mode:
13653       mask = 0xfffff;
13654       op = get16 ();
13655       break;
13656     case const_1_mode:
13657       if (intel_syntax)
13658         oappend ("1");
13659       return;
13660     default:
13661       oappend (INTERNAL_DISASSEMBLER_ERROR);
13662       return;
13663     }
13664
13665   op &= mask;
13666   scratchbuf[0] = '$';
13667   print_operand_value (scratchbuf + 1, 1, op);
13668   oappend (scratchbuf + intel_syntax);
13669   scratchbuf[0] = '\0';
13670 }
13671
13672 static void
13673 OP_I64 (int bytemode, int sizeflag)
13674 {
13675   bfd_signed_vma op;
13676   bfd_signed_vma mask = -1;
13677
13678   if (address_mode != mode_64bit)
13679     {
13680       OP_I (bytemode, sizeflag);
13681       return;
13682     }
13683
13684   switch (bytemode)
13685     {
13686     case b_mode:
13687       FETCH_DATA (the_info, codep + 1);
13688       op = *codep++;
13689       mask = 0xff;
13690       break;
13691     case v_mode:
13692       USED_REX (REX_W);
13693       if (rex & REX_W)
13694         op = get64 ();
13695       else
13696         {
13697           if (sizeflag & DFLAG)
13698             {
13699               op = get32 ();
13700               mask = 0xffffffff;
13701             }
13702           else
13703             {
13704               op = get16 ();
13705               mask = 0xfffff;
13706             }
13707           used_prefixes |= (prefixes & PREFIX_DATA);
13708         }
13709       break;
13710     case w_mode:
13711       mask = 0xfffff;
13712       op = get16 ();
13713       break;
13714     default:
13715       oappend (INTERNAL_DISASSEMBLER_ERROR);
13716       return;
13717     }
13718
13719   op &= mask;
13720   scratchbuf[0] = '$';
13721   print_operand_value (scratchbuf + 1, 1, op);
13722   oappend (scratchbuf + intel_syntax);
13723   scratchbuf[0] = '\0';
13724 }
13725
13726 static void
13727 OP_sI (int bytemode, int sizeflag)
13728 {
13729   bfd_signed_vma op;
13730
13731   switch (bytemode)
13732     {
13733     case b_mode:
13734       FETCH_DATA (the_info, codep + 1);
13735       op = *codep++;
13736       if ((op & 0x80) != 0)
13737         op -= 0x100;
13738       break;
13739     case v_mode:
13740       if (sizeflag & DFLAG)
13741         op = get32s ();
13742       else
13743         op = get16 ();
13744       break;
13745     default:
13746       oappend (INTERNAL_DISASSEMBLER_ERROR);
13747       return;
13748     }
13749
13750   scratchbuf[0] = '$';
13751   print_operand_value (scratchbuf + 1, 1, op);
13752   oappend (scratchbuf + intel_syntax);
13753 }
13754
13755 static void
13756 OP_J (int bytemode, int sizeflag)
13757 {
13758   bfd_vma disp;
13759   bfd_vma mask = -1;
13760   bfd_vma segment = 0;
13761
13762   switch (bytemode)
13763     {
13764     case b_mode:
13765       FETCH_DATA (the_info, codep + 1);
13766       disp = *codep++;
13767       if ((disp & 0x80) != 0)
13768         disp -= 0x100;
13769       break;
13770     case v_mode:
13771       USED_REX (REX_W);
13772       if ((sizeflag & DFLAG) || (rex & REX_W))
13773         disp = get32s ();
13774       else
13775         {
13776           disp = get16 ();
13777           if ((disp & 0x8000) != 0)
13778             disp -= 0x10000;
13779           /* In 16bit mode, address is wrapped around at 64k within
13780              the same segment.  Otherwise, a data16 prefix on a jump
13781              instruction means that the pc is masked to 16 bits after
13782              the displacement is added!  */
13783           mask = 0xffff;
13784           if ((prefixes & PREFIX_DATA) == 0)
13785             segment = ((start_pc + codep - start_codep)
13786                        & ~((bfd_vma) 0xffff));
13787         }
13788       if (!(rex & REX_W))
13789         used_prefixes |= (prefixes & PREFIX_DATA);
13790       break;
13791     default:
13792       oappend (INTERNAL_DISASSEMBLER_ERROR);
13793       return;
13794     }
13795   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
13796   set_op (disp, 0);
13797   print_operand_value (scratchbuf, 1, disp);
13798   oappend (scratchbuf);
13799 }
13800
13801 static void
13802 OP_SEG (int bytemode, int sizeflag)
13803 {
13804   if (bytemode == w_mode)
13805     oappend (names_seg[modrm.reg]);
13806   else
13807     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13808 }
13809
13810 static void
13811 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13812 {
13813   int seg, offset;
13814
13815   if (sizeflag & DFLAG)
13816     {
13817       offset = get32 ();
13818       seg = get16 ();
13819     }
13820   else
13821     {
13822       offset = get16 ();
13823       seg = get16 ();
13824     }
13825   used_prefixes |= (prefixes & PREFIX_DATA);
13826   if (intel_syntax)
13827     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13828   else
13829     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13830   oappend (scratchbuf);
13831 }
13832
13833 static void
13834 OP_OFF (int bytemode, int sizeflag)
13835 {
13836   bfd_vma off;
13837
13838   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13839     intel_operand_size (bytemode, sizeflag);
13840   append_seg ();
13841
13842   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13843     off = get32 ();
13844   else
13845     off = get16 ();
13846
13847   if (intel_syntax)
13848     {
13849       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13850                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13851         {
13852           oappend (names_seg[ds_reg - es_reg]);
13853           oappend (":");
13854         }
13855     }
13856   print_operand_value (scratchbuf, 1, off);
13857   oappend (scratchbuf);
13858 }
13859
13860 static void
13861 OP_OFF64 (int bytemode, int sizeflag)
13862 {
13863   bfd_vma off;
13864
13865   if (address_mode != mode_64bit
13866       || (prefixes & PREFIX_ADDR))
13867     {
13868       OP_OFF (bytemode, sizeflag);
13869       return;
13870     }
13871
13872   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13873     intel_operand_size (bytemode, sizeflag);
13874   append_seg ();
13875
13876   off = get64 ();
13877
13878   if (intel_syntax)
13879     {
13880       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13881                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13882         {
13883           oappend (names_seg[ds_reg - es_reg]);
13884           oappend (":");
13885         }
13886     }
13887   print_operand_value (scratchbuf, 1, off);
13888   oappend (scratchbuf);
13889 }
13890
13891 static void
13892 ptr_reg (int code, int sizeflag)
13893 {
13894   const char *s;
13895
13896   *obufp++ = open_char;
13897   used_prefixes |= (prefixes & PREFIX_ADDR);
13898   if (address_mode == mode_64bit)
13899     {
13900       if (!(sizeflag & AFLAG))
13901         s = names32[code - eAX_reg];
13902       else
13903         s = names64[code - eAX_reg];
13904     }
13905   else if (sizeflag & AFLAG)
13906     s = names32[code - eAX_reg];
13907   else
13908     s = names16[code - eAX_reg];
13909   oappend (s);
13910   *obufp++ = close_char;
13911   *obufp = 0;
13912 }
13913
13914 static void
13915 OP_ESreg (int code, int sizeflag)
13916 {
13917   if (intel_syntax)
13918     {
13919       switch (codep[-1])
13920         {
13921         case 0x6d:      /* insw/insl */
13922           intel_operand_size (z_mode, sizeflag);
13923           break;
13924         case 0xa5:      /* movsw/movsl/movsq */
13925         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13926         case 0xab:      /* stosw/stosl */
13927         case 0xaf:      /* scasw/scasl */
13928           intel_operand_size (v_mode, sizeflag);
13929           break;
13930         default:
13931           intel_operand_size (b_mode, sizeflag);
13932         }
13933     }
13934   oappend ("%es:" + intel_syntax);
13935   ptr_reg (code, sizeflag);
13936 }
13937
13938 static void
13939 OP_DSreg (int code, int sizeflag)
13940 {
13941   if (intel_syntax)
13942     {
13943       switch (codep[-1])
13944         {
13945         case 0x6f:      /* outsw/outsl */
13946           intel_operand_size (z_mode, sizeflag);
13947           break;
13948         case 0xa5:      /* movsw/movsl/movsq */
13949         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13950         case 0xad:      /* lodsw/lodsl/lodsq */
13951           intel_operand_size (v_mode, sizeflag);
13952           break;
13953         default:
13954           intel_operand_size (b_mode, sizeflag);
13955         }
13956     }
13957   if ((prefixes
13958        & (PREFIX_CS
13959           | PREFIX_DS
13960           | PREFIX_SS
13961           | PREFIX_ES
13962           | PREFIX_FS
13963           | PREFIX_GS)) == 0)
13964     prefixes |= PREFIX_DS;
13965   append_seg ();
13966   ptr_reg (code, sizeflag);
13967 }
13968
13969 static void
13970 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13971 {
13972   int add;
13973   if (rex & REX_R)
13974     {
13975       USED_REX (REX_R);
13976       add = 8;
13977     }
13978   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13979     {
13980       all_prefixes[last_lock_prefix] = 0;
13981       used_prefixes |= PREFIX_LOCK;
13982       add = 8;
13983     }
13984   else
13985     add = 0;
13986   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13987   oappend (scratchbuf + intel_syntax);
13988 }
13989
13990 static void
13991 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13992 {
13993   int add;
13994   USED_REX (REX_R);
13995   if (rex & REX_R)
13996     add = 8;
13997   else
13998     add = 0;
13999   if (intel_syntax)
14000     sprintf (scratchbuf, "db%d", modrm.reg + add);
14001   else
14002     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
14003   oappend (scratchbuf);
14004 }
14005
14006 static void
14007 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14008 {
14009   sprintf (scratchbuf, "%%tr%d", modrm.reg);
14010   oappend (scratchbuf + intel_syntax);
14011 }
14012
14013 static void
14014 OP_R (int bytemode, int sizeflag)
14015 {
14016   if (modrm.mod == 3)
14017     OP_E (bytemode, sizeflag);
14018   else
14019     BadOp ();
14020 }
14021
14022 static void
14023 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14024 {
14025   int reg = modrm.reg;
14026   const char **names;
14027
14028   used_prefixes |= (prefixes & PREFIX_DATA);
14029   if (prefixes & PREFIX_DATA)
14030     {
14031       names = names_xmm;
14032       USED_REX (REX_R);
14033       if (rex & REX_R)
14034         reg += 8;
14035     }
14036   else
14037     names = names_mm;
14038   oappend (names[reg]);
14039 }
14040
14041 static void
14042 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14043 {
14044   int reg = modrm.reg;
14045   const char **names;
14046
14047   USED_REX (REX_R);
14048   if (rex & REX_R)
14049     reg += 8;
14050   if (need_vex
14051       && bytemode != xmm_mode
14052       && bytemode != scalar_mode)
14053     {
14054       switch (vex.length)
14055         {
14056         case 128:
14057           names = names_xmm;
14058           break;
14059         case 256:
14060           names = names_ymm;
14061           break;
14062         default:
14063           abort ();
14064         }
14065     }
14066   else
14067     names = names_xmm;
14068   oappend (names[reg]);
14069 }
14070
14071 static void
14072 OP_EM (int bytemode, int sizeflag)
14073 {
14074   int reg;
14075   const char **names;
14076
14077   if (modrm.mod != 3)
14078     {
14079       if (intel_syntax
14080           && (bytemode == v_mode || bytemode == v_swap_mode))
14081         {
14082           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14083           used_prefixes |= (prefixes & PREFIX_DATA);
14084         }
14085       OP_E (bytemode, sizeflag);
14086       return;
14087     }
14088
14089   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
14090     swap_operand ();
14091
14092   /* Skip mod/rm byte.  */
14093   MODRM_CHECK;
14094   codep++;
14095   used_prefixes |= (prefixes & PREFIX_DATA);
14096   reg = modrm.rm;
14097   if (prefixes & PREFIX_DATA)
14098     {
14099       names = names_xmm;
14100       USED_REX (REX_B);
14101       if (rex & REX_B)
14102         reg += 8;
14103     }
14104   else
14105     names = names_mm;
14106   oappend (names[reg]);
14107 }
14108
14109 /* cvt* are the only instructions in sse2 which have
14110    both SSE and MMX operands and also have 0x66 prefix
14111    in their opcode. 0x66 was originally used to differentiate
14112    between SSE and MMX instruction(operands). So we have to handle the
14113    cvt* separately using OP_EMC and OP_MXC */
14114 static void
14115 OP_EMC (int bytemode, int sizeflag)
14116 {
14117   if (modrm.mod != 3)
14118     {
14119       if (intel_syntax && bytemode == v_mode)
14120         {
14121           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14122           used_prefixes |= (prefixes & PREFIX_DATA);
14123         }
14124       OP_E (bytemode, sizeflag);
14125       return;
14126     }
14127
14128   /* Skip mod/rm byte.  */
14129   MODRM_CHECK;
14130   codep++;
14131   used_prefixes |= (prefixes & PREFIX_DATA);
14132   oappend (names_mm[modrm.rm]);
14133 }
14134
14135 static void
14136 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14137 {
14138   used_prefixes |= (prefixes & PREFIX_DATA);
14139   oappend (names_mm[modrm.reg]);
14140 }
14141
14142 static void
14143 OP_EX (int bytemode, int sizeflag)
14144 {
14145   int reg;
14146   const char **names;
14147
14148   /* Skip mod/rm byte.  */
14149   MODRM_CHECK;
14150   codep++;
14151
14152   if (modrm.mod != 3)
14153     {
14154       OP_E_memory (bytemode, sizeflag);
14155       return;
14156     }
14157
14158   reg = modrm.rm;
14159   USED_REX (REX_B);
14160   if (rex & REX_B)
14161     reg += 8;
14162
14163   if ((sizeflag & SUFFIX_ALWAYS)
14164       && (bytemode == x_swap_mode
14165           || bytemode == d_swap_mode
14166           || bytemode == d_scalar_swap_mode
14167           || bytemode == q_swap_mode
14168           || bytemode == q_scalar_swap_mode))
14169     swap_operand ();
14170
14171   if (need_vex
14172       && bytemode != xmm_mode
14173       && bytemode != xmmq_mode
14174       && bytemode != d_scalar_mode
14175       && bytemode != d_scalar_swap_mode
14176       && bytemode != q_scalar_mode
14177       && bytemode != q_scalar_swap_mode
14178       && bytemode != vex_scalar_w_dq_mode)
14179     {
14180       switch (vex.length)
14181         {
14182         case 128:
14183           names = names_xmm;
14184           break;
14185         case 256:
14186           names = names_ymm;
14187           break;
14188         default:
14189           abort ();
14190         }
14191     }
14192   else
14193     names = names_xmm;
14194   oappend (names[reg]);
14195 }
14196
14197 static void
14198 OP_MS (int bytemode, int sizeflag)
14199 {
14200   if (modrm.mod == 3)
14201     OP_EM (bytemode, sizeflag);
14202   else
14203     BadOp ();
14204 }
14205
14206 static void
14207 OP_XS (int bytemode, int sizeflag)
14208 {
14209   if (modrm.mod == 3)
14210     OP_EX (bytemode, sizeflag);
14211   else
14212     BadOp ();
14213 }
14214
14215 static void
14216 OP_M (int bytemode, int sizeflag)
14217 {
14218   if (modrm.mod == 3)
14219     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14220     BadOp ();
14221   else
14222     OP_E (bytemode, sizeflag);
14223 }
14224
14225 static void
14226 OP_0f07 (int bytemode, int sizeflag)
14227 {
14228   if (modrm.mod != 3 || modrm.rm != 0)
14229     BadOp ();
14230   else
14231     OP_E (bytemode, sizeflag);
14232 }
14233
14234 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14235    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
14236
14237 static void
14238 NOP_Fixup1 (int bytemode, int sizeflag)
14239 {
14240   if ((prefixes & PREFIX_DATA) != 0
14241       || (rex != 0
14242           && rex != 0x48
14243           && address_mode == mode_64bit))
14244     OP_REG (bytemode, sizeflag);
14245   else
14246     strcpy (obuf, "nop");
14247 }
14248
14249 static void
14250 NOP_Fixup2 (int bytemode, int sizeflag)
14251 {
14252   if ((prefixes & PREFIX_DATA) != 0
14253       || (rex != 0
14254           && rex != 0x48
14255           && address_mode == mode_64bit))
14256     OP_IMREG (bytemode, sizeflag);
14257 }
14258
14259 static const char *const Suffix3DNow[] = {
14260 /* 00 */        NULL,           NULL,           NULL,           NULL,
14261 /* 04 */        NULL,           NULL,           NULL,           NULL,
14262 /* 08 */        NULL,           NULL,           NULL,           NULL,
14263 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
14264 /* 10 */        NULL,           NULL,           NULL,           NULL,
14265 /* 14 */        NULL,           NULL,           NULL,           NULL,
14266 /* 18 */        NULL,           NULL,           NULL,           NULL,
14267 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
14268 /* 20 */        NULL,           NULL,           NULL,           NULL,
14269 /* 24 */        NULL,           NULL,           NULL,           NULL,
14270 /* 28 */        NULL,           NULL,           NULL,           NULL,
14271 /* 2C */        NULL,           NULL,           NULL,           NULL,
14272 /* 30 */        NULL,           NULL,           NULL,           NULL,
14273 /* 34 */        NULL,           NULL,           NULL,           NULL,
14274 /* 38 */        NULL,           NULL,           NULL,           NULL,
14275 /* 3C */        NULL,           NULL,           NULL,           NULL,
14276 /* 40 */        NULL,           NULL,           NULL,           NULL,
14277 /* 44 */        NULL,           NULL,           NULL,           NULL,
14278 /* 48 */        NULL,           NULL,           NULL,           NULL,
14279 /* 4C */        NULL,           NULL,           NULL,           NULL,
14280 /* 50 */        NULL,           NULL,           NULL,           NULL,
14281 /* 54 */        NULL,           NULL,           NULL,           NULL,
14282 /* 58 */        NULL,           NULL,           NULL,           NULL,
14283 /* 5C */        NULL,           NULL,           NULL,           NULL,
14284 /* 60 */        NULL,           NULL,           NULL,           NULL,
14285 /* 64 */        NULL,           NULL,           NULL,           NULL,
14286 /* 68 */        NULL,           NULL,           NULL,           NULL,
14287 /* 6C */        NULL,           NULL,           NULL,           NULL,
14288 /* 70 */        NULL,           NULL,           NULL,           NULL,
14289 /* 74 */        NULL,           NULL,           NULL,           NULL,
14290 /* 78 */        NULL,           NULL,           NULL,           NULL,
14291 /* 7C */        NULL,           NULL,           NULL,           NULL,
14292 /* 80 */        NULL,           NULL,           NULL,           NULL,
14293 /* 84 */        NULL,           NULL,           NULL,           NULL,
14294 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14295 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14296 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14297 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14298 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14299 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14300 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14301 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14302 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14303 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14304 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14305 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14306 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14307 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14308 /* C0 */        NULL,           NULL,           NULL,           NULL,
14309 /* C4 */        NULL,           NULL,           NULL,           NULL,
14310 /* C8 */        NULL,           NULL,           NULL,           NULL,
14311 /* CC */        NULL,           NULL,           NULL,           NULL,
14312 /* D0 */        NULL,           NULL,           NULL,           NULL,
14313 /* D4 */        NULL,           NULL,           NULL,           NULL,
14314 /* D8 */        NULL,           NULL,           NULL,           NULL,
14315 /* DC */        NULL,           NULL,           NULL,           NULL,
14316 /* E0 */        NULL,           NULL,           NULL,           NULL,
14317 /* E4 */        NULL,           NULL,           NULL,           NULL,
14318 /* E8 */        NULL,           NULL,           NULL,           NULL,
14319 /* EC */        NULL,           NULL,           NULL,           NULL,
14320 /* F0 */        NULL,           NULL,           NULL,           NULL,
14321 /* F4 */        NULL,           NULL,           NULL,           NULL,
14322 /* F8 */        NULL,           NULL,           NULL,           NULL,
14323 /* FC */        NULL,           NULL,           NULL,           NULL,
14324 };
14325
14326 static void
14327 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14328 {
14329   const char *mnemonic;
14330
14331   FETCH_DATA (the_info, codep + 1);
14332   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14333      place where an 8-bit immediate would normally go.  ie. the last
14334      byte of the instruction.  */
14335   obufp = mnemonicendp;
14336   mnemonic = Suffix3DNow[*codep++ & 0xff];
14337   if (mnemonic)
14338     oappend (mnemonic);
14339   else
14340     {
14341       /* Since a variable sized modrm/sib chunk is between the start
14342          of the opcode (0x0f0f) and the opcode suffix, we need to do
14343          all the modrm processing first, and don't know until now that
14344          we have a bad opcode.  This necessitates some cleaning up.  */
14345       op_out[0][0] = '\0';
14346       op_out[1][0] = '\0';
14347       BadOp ();
14348     }
14349   mnemonicendp = obufp;
14350 }
14351
14352 static struct op simd_cmp_op[] =
14353 {
14354   { STRING_COMMA_LEN ("eq") },
14355   { STRING_COMMA_LEN ("lt") },
14356   { STRING_COMMA_LEN ("le") },
14357   { STRING_COMMA_LEN ("unord") },
14358   { STRING_COMMA_LEN ("neq") },
14359   { STRING_COMMA_LEN ("nlt") },
14360   { STRING_COMMA_LEN ("nle") },
14361   { STRING_COMMA_LEN ("ord") }
14362 };
14363
14364 static void
14365 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14366 {
14367   unsigned int cmp_type;
14368
14369   FETCH_DATA (the_info, codep + 1);
14370   cmp_type = *codep++ & 0xff;
14371   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14372     {
14373       char suffix [3];
14374       char *p = mnemonicendp - 2;
14375       suffix[0] = p[0];
14376       suffix[1] = p[1];
14377       suffix[2] = '\0';
14378       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14379       mnemonicendp += simd_cmp_op[cmp_type].len;
14380     }
14381   else
14382     {
14383       /* We have a reserved extension byte.  Output it directly.  */
14384       scratchbuf[0] = '$';
14385       print_operand_value (scratchbuf + 1, 1, cmp_type);
14386       oappend (scratchbuf + intel_syntax);
14387       scratchbuf[0] = '\0';
14388     }
14389 }
14390
14391 static void
14392 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14393           int sizeflag ATTRIBUTE_UNUSED)
14394 {
14395   /* mwait %eax,%ecx  */
14396   if (!intel_syntax)
14397     {
14398       const char **names = (address_mode == mode_64bit
14399                             ? names64 : names32);
14400       strcpy (op_out[0], names[0]);
14401       strcpy (op_out[1], names[1]);
14402       two_source_ops = 1;
14403     }
14404   /* Skip mod/rm byte.  */
14405   MODRM_CHECK;
14406   codep++;
14407 }
14408
14409 static void
14410 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14411             int sizeflag ATTRIBUTE_UNUSED)
14412 {
14413   /* monitor %eax,%ecx,%edx"  */
14414   if (!intel_syntax)
14415     {
14416       const char **op1_names;
14417       const char **names = (address_mode == mode_64bit
14418                             ? names64 : names32);
14419
14420       if (!(prefixes & PREFIX_ADDR))
14421         op1_names = (address_mode == mode_16bit
14422                      ? names16 : names);
14423       else
14424         {
14425           /* Remove "addr16/addr32".  */
14426           all_prefixes[last_addr_prefix] = 0;
14427           op1_names = (address_mode != mode_32bit
14428                        ? names32 : names16);
14429           used_prefixes |= PREFIX_ADDR;
14430         }
14431       strcpy (op_out[0], op1_names[0]);
14432       strcpy (op_out[1], names[1]);
14433       strcpy (op_out[2], names[2]);
14434       two_source_ops = 1;
14435     }
14436   /* Skip mod/rm byte.  */
14437   MODRM_CHECK;
14438   codep++;
14439 }
14440
14441 static void
14442 BadOp (void)
14443 {
14444   /* Throw away prefixes and 1st. opcode byte.  */
14445   codep = insn_codep + 1;
14446   oappend ("(bad)");
14447 }
14448
14449 static void
14450 REP_Fixup (int bytemode, int sizeflag)
14451 {
14452   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14453      lods and stos.  */
14454   if (prefixes & PREFIX_REPZ)
14455     all_prefixes[last_repz_prefix] = REP_PREFIX;
14456
14457   switch (bytemode)
14458     {
14459     case al_reg:
14460     case eAX_reg:
14461     case indir_dx_reg:
14462       OP_IMREG (bytemode, sizeflag);
14463       break;
14464     case eDI_reg:
14465       OP_ESreg (bytemode, sizeflag);
14466       break;
14467     case eSI_reg:
14468       OP_DSreg (bytemode, sizeflag);
14469       break;
14470     default:
14471       abort ();
14472       break;
14473     }
14474 }
14475
14476 static void
14477 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14478 {
14479   USED_REX (REX_W);
14480   if (rex & REX_W)
14481     {
14482       /* Change cmpxchg8b to cmpxchg16b.  */
14483       char *p = mnemonicendp - 2;
14484       mnemonicendp = stpcpy (p, "16b");
14485       bytemode = o_mode;
14486     }
14487   OP_M (bytemode, sizeflag);
14488 }
14489
14490 static void
14491 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14492 {
14493   const char **names;
14494
14495   if (need_vex)
14496     {
14497       switch (vex.length)
14498         {
14499         case 128:
14500           names = names_xmm;
14501           break;
14502         case 256:
14503           names = names_ymm;
14504           break;
14505         default:
14506           abort ();
14507         }
14508     }
14509   else
14510     names = names_xmm;
14511   oappend (names[reg]);
14512 }
14513
14514 static void
14515 CRC32_Fixup (int bytemode, int sizeflag)
14516 {
14517   /* Add proper suffix to "crc32".  */
14518   char *p = mnemonicendp;
14519
14520   switch (bytemode)
14521     {
14522     case b_mode:
14523       if (intel_syntax)
14524         goto skip;
14525
14526       *p++ = 'b';
14527       break;
14528     case v_mode:
14529       if (intel_syntax)
14530         goto skip;
14531
14532       USED_REX (REX_W);
14533       if (rex & REX_W)
14534         *p++ = 'q';
14535       else
14536         {
14537           if (sizeflag & DFLAG)
14538             *p++ = 'l';
14539           else
14540             *p++ = 'w';
14541           used_prefixes |= (prefixes & PREFIX_DATA);
14542         }
14543       break;
14544     default:
14545       oappend (INTERNAL_DISASSEMBLER_ERROR);
14546       break;
14547     }
14548   mnemonicendp = p;
14549   *p = '\0';
14550
14551 skip:
14552   if (modrm.mod == 3)
14553     {
14554       int add;
14555
14556       /* Skip mod/rm byte.  */
14557       MODRM_CHECK;
14558       codep++;
14559
14560       USED_REX (REX_B);
14561       add = (rex & REX_B) ? 8 : 0;
14562       if (bytemode == b_mode)
14563         {
14564           USED_REX (0);
14565           if (rex)
14566             oappend (names8rex[modrm.rm + add]);
14567           else
14568             oappend (names8[modrm.rm + add]);
14569         }
14570       else
14571         {
14572           USED_REX (REX_W);
14573           if (rex & REX_W)
14574             oappend (names64[modrm.rm + add]);
14575           else if ((prefixes & PREFIX_DATA))
14576             oappend (names16[modrm.rm + add]);
14577           else
14578             oappend (names32[modrm.rm + add]);
14579         }
14580     }
14581   else
14582     OP_E (bytemode, sizeflag);
14583 }
14584
14585 static void
14586 FXSAVE_Fixup (int bytemode, int sizeflag)
14587 {
14588   /* Add proper suffix to "fxsave" and "fxrstor".  */
14589   USED_REX (REX_W);
14590   if (rex & REX_W)
14591     {
14592       char *p = mnemonicendp;
14593       *p++ = '6';
14594       *p++ = '4';
14595       *p = '\0';
14596       mnemonicendp = p;
14597     }
14598   OP_M (bytemode, sizeflag);
14599 }
14600
14601 /* Display the destination register operand for instructions with
14602    VEX. */
14603
14604 static void
14605 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14606 {
14607   int reg;
14608   const char **names;
14609
14610   if (!need_vex)
14611     abort ();
14612
14613   if (!need_vex_reg)
14614     return;
14615
14616   reg = vex.register_specifier;
14617   if (bytemode == vex_scalar_mode)
14618     {
14619       oappend (names_xmm[reg]);
14620       return;
14621     }
14622
14623   switch (vex.length)
14624     {
14625     case 128:
14626       switch (bytemode)
14627         {
14628         case vex_mode:
14629         case vex128_mode:
14630           names = names_xmm;
14631           break;
14632         case dq_mode:
14633           if (vex.w)
14634             names = names64;
14635           else
14636             names = names32;
14637           break;
14638         default:
14639           abort ();
14640           return;
14641         }
14642       break;
14643     case 256:
14644       switch (bytemode)
14645         {
14646         case vex_mode:
14647         case vex256_mode:
14648           break;
14649         default:
14650           abort ();
14651           return;
14652         }
14653
14654       names = names_ymm;
14655       break;
14656     default:
14657       abort ();
14658       break;
14659     }
14660   oappend (names[reg]);
14661 }
14662
14663 /* Get the VEX immediate byte without moving codep.  */
14664
14665 static unsigned char
14666 get_vex_imm8 (int sizeflag, int opnum)
14667 {
14668   int bytes_before_imm = 0;
14669
14670   if (modrm.mod != 3)
14671     {
14672       /* There are SIB/displacement bytes.  */
14673       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14674         {
14675           /* 32/64 bit address mode */
14676           int base = modrm.rm;
14677
14678           /* Check SIB byte.  */
14679           if (base == 4)
14680             {
14681               FETCH_DATA (the_info, codep + 1);
14682               base = *codep & 7;
14683               /* When decoding the third source, don't increase
14684                  bytes_before_imm as this has already been incremented
14685                  by one in OP_E_memory while decoding the second
14686                  source operand.  */
14687               if (opnum == 0)
14688                 bytes_before_imm++;
14689             }
14690
14691           /* Don't increase bytes_before_imm when decoding the third source,
14692              it has already been incremented by OP_E_memory while decoding
14693              the second source operand.  */
14694           if (opnum == 0)
14695             {
14696               switch (modrm.mod)
14697                 {
14698                   case 0:
14699                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14700                        SIB == 5, there is a 4 byte displacement.  */
14701                     if (base != 5)
14702                       /* No displacement. */
14703                       break;
14704                   case 2:
14705                     /* 4 byte displacement.  */
14706                     bytes_before_imm += 4;
14707                     break;
14708                   case 1:
14709                     /* 1 byte displacement.  */
14710                     bytes_before_imm++;
14711                     break;
14712                 }
14713             }
14714         }
14715       else
14716         {
14717           /* 16 bit address mode */
14718           /* Don't increase bytes_before_imm when decoding the third source,
14719              it has already been incremented by OP_E_memory while decoding
14720              the second source operand.  */
14721           if (opnum == 0)
14722             {
14723               switch (modrm.mod)
14724                 {
14725                 case 0:
14726                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14727                   if (modrm.rm != 6)
14728                     /* No displacement. */
14729                     break;
14730                 case 2:
14731                   /* 2 byte displacement.  */
14732                   bytes_before_imm += 2;
14733                   break;
14734                 case 1:
14735                   /* 1 byte displacement: when decoding the third source,
14736                      don't increase bytes_before_imm as this has already
14737                      been incremented by one in OP_E_memory while decoding
14738                      the second source operand.  */
14739                   if (opnum == 0)
14740                     bytes_before_imm++;
14741
14742                   break;
14743                 }
14744             }
14745         }
14746     }
14747
14748   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14749   return codep [bytes_before_imm];
14750 }
14751
14752 static void
14753 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14754 {
14755   const char **names;
14756
14757   if (reg == -1 && modrm.mod != 3)
14758     {
14759       OP_E_memory (bytemode, sizeflag);
14760       return;
14761     }
14762   else
14763     {
14764       if (reg == -1)
14765         {
14766           reg = modrm.rm;
14767           USED_REX (REX_B);
14768           if (rex & REX_B)
14769             reg += 8;
14770         }
14771       else if (reg > 7 && address_mode != mode_64bit)
14772         BadOp ();
14773     }
14774
14775   switch (vex.length)
14776     {
14777     case 128:
14778       names = names_xmm;
14779       break;
14780     case 256:
14781       names = names_ymm;
14782       break;
14783     default:
14784       abort ();
14785     }
14786   oappend (names[reg]);
14787 }
14788
14789 static void
14790 OP_EX_VexImmW (int bytemode, int sizeflag)
14791 {
14792   int reg = -1;
14793   static unsigned char vex_imm8;
14794
14795   if (vex_w_done == 0)
14796     {
14797       vex_w_done = 1;
14798
14799       /* Skip mod/rm byte.  */
14800       MODRM_CHECK;
14801       codep++;
14802
14803       vex_imm8 = get_vex_imm8 (sizeflag, 0);
14804
14805       if (vex.w)
14806           reg = vex_imm8 >> 4;
14807
14808       OP_EX_VexReg (bytemode, sizeflag, reg);
14809     }
14810   else if (vex_w_done == 1)
14811     {
14812       vex_w_done = 2;
14813
14814       if (!vex.w)
14815           reg = vex_imm8 >> 4;
14816
14817       OP_EX_VexReg (bytemode, sizeflag, reg);
14818     }
14819   else
14820     {
14821       /* Output the imm8 directly.  */
14822       scratchbuf[0] = '$';
14823       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14824       oappend (scratchbuf + intel_syntax);
14825       scratchbuf[0] = '\0';
14826       codep++;
14827     }
14828 }
14829
14830 static void
14831 OP_Vex_2src (int bytemode, int sizeflag)
14832 {
14833   if (modrm.mod == 3)
14834     {
14835       int reg = modrm.rm;
14836       USED_REX (REX_B);
14837       if (rex & REX_B)
14838         reg += 8;
14839       oappend (names_xmm[reg]);
14840     }
14841   else
14842     {
14843       if (intel_syntax
14844           && (bytemode == v_mode || bytemode == v_swap_mode))
14845         {
14846           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14847           used_prefixes |= (prefixes & PREFIX_DATA);
14848         }
14849       OP_E (bytemode, sizeflag);
14850     }
14851 }
14852
14853 static void
14854 OP_Vex_2src_1 (int bytemode, int sizeflag)
14855 {
14856   if (modrm.mod == 3)
14857     {
14858       /* Skip mod/rm byte.   */
14859       MODRM_CHECK;
14860       codep++;
14861     }
14862
14863   if (vex.w)
14864     oappend (names_xmm[vex.register_specifier]);
14865   else
14866     OP_Vex_2src (bytemode, sizeflag);
14867 }
14868
14869 static void
14870 OP_Vex_2src_2 (int bytemode, int sizeflag)
14871 {
14872   if (vex.w)
14873     OP_Vex_2src (bytemode, sizeflag);
14874   else
14875     oappend (names_xmm[vex.register_specifier]);
14876 }
14877
14878 static void
14879 OP_EX_VexW (int bytemode, int sizeflag)
14880 {
14881   int reg = -1;
14882
14883   if (!vex_w_done)
14884     {
14885       vex_w_done = 1;
14886
14887       /* Skip mod/rm byte.  */
14888       MODRM_CHECK;
14889       codep++;
14890
14891       if (vex.w)
14892         reg = get_vex_imm8 (sizeflag, 0) >> 4;
14893     }
14894   else
14895     {
14896       if (!vex.w)
14897         reg = get_vex_imm8 (sizeflag, 1) >> 4;
14898     }
14899
14900   OP_EX_VexReg (bytemode, sizeflag, reg);
14901 }
14902
14903 static void
14904 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14905              int sizeflag ATTRIBUTE_UNUSED)
14906 {
14907   /* Skip the immediate byte and check for invalid bits.  */
14908   FETCH_DATA (the_info, codep + 1);
14909   if (*codep++ & 0xf)
14910     BadOp ();
14911 }
14912
14913 static void
14914 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14915 {
14916   int reg;
14917   const char **names;
14918
14919   FETCH_DATA (the_info, codep + 1);
14920   reg = *codep++;
14921
14922   if (bytemode != x_mode)
14923     abort ();
14924
14925   if (reg & 0xf)
14926       BadOp ();
14927
14928   reg >>= 4;
14929   if (reg > 7 && address_mode != mode_64bit)
14930     BadOp ();
14931
14932   switch (vex.length)
14933     {
14934     case 128:
14935       names = names_xmm;
14936       break;
14937     case 256:
14938       names = names_ymm;
14939       break;
14940     default:
14941       abort ();
14942     }
14943   oappend (names[reg]);
14944 }
14945
14946 static void
14947 OP_XMM_VexW (int bytemode, int sizeflag)
14948 {
14949   /* Turn off the REX.W bit since it is used for swapping operands
14950      now.  */
14951   rex &= ~REX_W;
14952   OP_XMM (bytemode, sizeflag);
14953 }
14954
14955 static void
14956 OP_EX_Vex (int bytemode, int sizeflag)
14957 {
14958   if (modrm.mod != 3)
14959     {
14960       if (vex.register_specifier != 0)
14961         BadOp ();
14962       need_vex_reg = 0;
14963     }
14964   OP_EX (bytemode, sizeflag);
14965 }
14966
14967 static void
14968 OP_XMM_Vex (int bytemode, int sizeflag)
14969 {
14970   if (modrm.mod != 3)
14971     {
14972       if (vex.register_specifier != 0)
14973         BadOp ();
14974       need_vex_reg = 0;
14975     }
14976   OP_XMM (bytemode, sizeflag);
14977 }
14978
14979 static void
14980 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14981 {
14982   switch (vex.length)
14983     {
14984     case 128:
14985       mnemonicendp = stpcpy (obuf, "vzeroupper");
14986       break;
14987     case 256:
14988       mnemonicendp = stpcpy (obuf, "vzeroall");
14989       break;
14990     default:
14991       abort ();
14992     }
14993 }
14994
14995 static struct op vex_cmp_op[] =
14996 {
14997   { STRING_COMMA_LEN ("eq") },
14998   { STRING_COMMA_LEN ("lt") },
14999   { STRING_COMMA_LEN ("le") },
15000   { STRING_COMMA_LEN ("unord") },
15001   { STRING_COMMA_LEN ("neq") },
15002   { STRING_COMMA_LEN ("nlt") },
15003   { STRING_COMMA_LEN ("nle") },
15004   { STRING_COMMA_LEN ("ord") },
15005   { STRING_COMMA_LEN ("eq_uq") },
15006   { STRING_COMMA_LEN ("nge") },
15007   { STRING_COMMA_LEN ("ngt") },
15008   { STRING_COMMA_LEN ("false") },
15009   { STRING_COMMA_LEN ("neq_oq") },
15010   { STRING_COMMA_LEN ("ge") },
15011   { STRING_COMMA_LEN ("gt") },
15012   { STRING_COMMA_LEN ("true") },
15013   { STRING_COMMA_LEN ("eq_os") },
15014   { STRING_COMMA_LEN ("lt_oq") },
15015   { STRING_COMMA_LEN ("le_oq") },
15016   { STRING_COMMA_LEN ("unord_s") },
15017   { STRING_COMMA_LEN ("neq_us") },
15018   { STRING_COMMA_LEN ("nlt_uq") },
15019   { STRING_COMMA_LEN ("nle_uq") },
15020   { STRING_COMMA_LEN ("ord_s") },
15021   { STRING_COMMA_LEN ("eq_us") },
15022   { STRING_COMMA_LEN ("nge_uq") },
15023   { STRING_COMMA_LEN ("ngt_uq") },
15024   { STRING_COMMA_LEN ("false_os") },
15025   { STRING_COMMA_LEN ("neq_os") },
15026   { STRING_COMMA_LEN ("ge_oq") },
15027   { STRING_COMMA_LEN ("gt_oq") },
15028   { STRING_COMMA_LEN ("true_us") },
15029 };
15030
15031 static void
15032 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15033 {
15034   unsigned int cmp_type;
15035
15036   FETCH_DATA (the_info, codep + 1);
15037   cmp_type = *codep++ & 0xff;
15038   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
15039     {
15040       char suffix [3];
15041       char *p = mnemonicendp - 2;
15042       suffix[0] = p[0];
15043       suffix[1] = p[1];
15044       suffix[2] = '\0';
15045       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
15046       mnemonicendp += vex_cmp_op[cmp_type].len;
15047     }
15048   else
15049     {
15050       /* We have a reserved extension byte.  Output it directly.  */
15051       scratchbuf[0] = '$';
15052       print_operand_value (scratchbuf + 1, 1, cmp_type);
15053       oappend (scratchbuf + intel_syntax);
15054       scratchbuf[0] = '\0';
15055     }
15056 }
15057
15058 static const struct op pclmul_op[] =
15059 {
15060   { STRING_COMMA_LEN ("lql") },
15061   { STRING_COMMA_LEN ("hql") },
15062   { STRING_COMMA_LEN ("lqh") },
15063   { STRING_COMMA_LEN ("hqh") }
15064 };
15065
15066 static void
15067 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
15068               int sizeflag ATTRIBUTE_UNUSED)
15069 {
15070   unsigned int pclmul_type;
15071
15072   FETCH_DATA (the_info, codep + 1);
15073   pclmul_type = *codep++ & 0xff;
15074   switch (pclmul_type)
15075     {
15076     case 0x10:
15077       pclmul_type = 2;
15078       break;
15079     case 0x11:
15080       pclmul_type = 3;
15081       break;
15082     default:
15083       break;
15084     }
15085   if (pclmul_type < ARRAY_SIZE (pclmul_op))
15086     {
15087       char suffix [4];
15088       char *p = mnemonicendp - 3;
15089       suffix[0] = p[0];
15090       suffix[1] = p[1];
15091       suffix[2] = p[2];
15092       suffix[3] = '\0';
15093       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
15094       mnemonicendp += pclmul_op[pclmul_type].len;
15095     }
15096   else
15097     {
15098       /* We have a reserved extension byte.  Output it directly.  */
15099       scratchbuf[0] = '$';
15100       print_operand_value (scratchbuf + 1, 1, pclmul_type);
15101       oappend (scratchbuf + intel_syntax);
15102       scratchbuf[0] = '\0';
15103     }
15104 }
15105
15106 static void
15107 MOVBE_Fixup (int bytemode, int sizeflag)
15108 {
15109   /* Add proper suffix to "movbe".  */
15110   char *p = mnemonicendp;
15111
15112   switch (bytemode)
15113     {
15114     case v_mode:
15115       if (intel_syntax)
15116         goto skip;
15117
15118       USED_REX (REX_W);
15119       if (sizeflag & SUFFIX_ALWAYS)
15120         {
15121           if (rex & REX_W)
15122             *p++ = 'q';
15123           else
15124             {
15125               if (sizeflag & DFLAG)
15126                 *p++ = 'l';
15127               else
15128                 *p++ = 'w';
15129               used_prefixes |= (prefixes & PREFIX_DATA);
15130             }
15131         }
15132       break;
15133     default:
15134       oappend (INTERNAL_DISASSEMBLER_ERROR);
15135       break;
15136     }
15137   mnemonicendp = p;
15138   *p = '\0';
15139
15140 skip:
15141   OP_M (bytemode, sizeflag);
15142 }
15143
15144 static void
15145 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15146 {
15147   int reg;
15148   const char **names;
15149
15150   /* Skip mod/rm byte.  */
15151   MODRM_CHECK;
15152   codep++;
15153
15154   if (vex.w)
15155     names = names64;
15156   else
15157     names = names32;
15158
15159   reg = modrm.rm;
15160   USED_REX (REX_B);
15161   if (rex & REX_B)
15162     reg += 8;
15163
15164   oappend (names[reg]);
15165 }
15166
15167 static void
15168 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15169 {
15170   const char **names;
15171
15172   if (vex.w)
15173     names = names64;
15174   else
15175     names = names32;
15176
15177   oappend (names[vex.register_specifier]);
15178 }
15179