opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 /* i186 or better required */
  34 #define Cpu186          0
  35 /* i286 or better required */
  36 #define Cpu286          (Cpu186 + 1)
  37 /* i386 or better required */
  38 #define Cpu386          (Cpu286 + 1)
  39 /* i486 or better required */
  40 #define Cpu486          (Cpu386 + 1)
  41 /* i585 or better required */
  42 #define Cpu586          (Cpu486 + 1)
  43 /* i686 or better required */
  44 #define Cpu686          (Cpu586 + 1)
  45 /* Pentium4 or better required */
  46 #define CpuP4           (Cpu686 + 1)
  47 /* AMD K6 or better required*/
  48 #define CpuK6           (CpuP4 + 1)
  49 /* AMD K8 or better required */
  50 #define CpuK8           (CpuK6 + 1)
  51 /* MMX support required */
  52 #define CpuMMX          (CpuK8 + 1)
  53 /* extended MMX support (with SSE or 3DNow!Ext) required */
  54 #define CpuMMX2         (CpuMMX + 1)
  55 /* SSE support required */
  56 #define CpuSSE          (CpuMMX2 + 1)
  57 /* SSE2 support required */
  58 #define CpuSSE2         (CpuSSE + 1)
  59 /* 3dnow! support required */
  60 #define Cpu3dnow        (CpuSSE2 + 1)
  61 /* 3dnow! Extensions support required */
  62 #define Cpu3dnowA       (Cpu3dnow + 1)
  63 /* SSE3 support required */
  64 #define CpuSSE3         (Cpu3dnowA + 1)
  65 /* VIA PadLock required */
  66 #define CpuPadLock      (CpuSSE3 + 1)
  67 /* AMD Secure Virtual Machine Ext-s required */
  68 #define CpuSVME         (CpuPadLock + 1)
  69 /* VMX Instructions required */
  70 #define CpuVMX          (CpuSVME + 1)
  71 /* SSSE3 support required */
  72 #define CpuSSSE3        (CpuVMX + 1)
  73 /* SSE4a support required */
  74 #define CpuSSE4a        (CpuSSSE3 + 1)
  75 /* ABM New Instructions required */
  76 #define CpuABM          (CpuSSE4a + 1)
  77 /* SSE4.1 support required */
  78 #define CpuSSE4_1       (CpuABM + 1)
  79 /* SSE4.2 support required */
  80 #define CpuSSE4_2       (CpuSSE4_1 + 1)
  81 /* 64bit support available, used by -march= in assembler.  */
  82 #define CpuLM           (CpuSSE4_2 + 1)
  83 /* 64bit support required  */
  84 #define Cpu64           (CpuLM + 1)
  85 /* Not supported in the 64bit mode  */
  86 #define CpuNo64         (Cpu64 + 1)
  87 /* The last bitfield in i386_cpu_flags.  */
  88 #define CpuMax          CpuNo64
  89
  90 #define CpuNumOfUints \
  91   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
  92 #define CpuNumOfBits \
  93   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
  94
  95 /* If you get a compiler error for zero width of the unused field,
  96    comment it out.  */
  97 #define CpuUnused       (CpuNo64 + 1)
  98
  99 /* We can check if an instruction is available with array instead
 100    of bitfield. */
 101 typedef union i386_cpu_flags
 102 {
 103   struct
 104     {
 105       unsigned int cpui186:1;
 106       unsigned int cpui286:1;
 107       unsigned int cpui386:1;
 108       unsigned int cpui486:1;
 109       unsigned int cpui586:1;
 110       unsigned int cpui686:1;
 111       unsigned int cpup4:1;
 112       unsigned int cpuk6:1;
 113       unsigned int cpuk8:1;
 114       unsigned int cpummx:1;
 115       unsigned int cpummx2:1;
 116       unsigned int cpusse:1;
 117       unsigned int cpusse2:1;
 118       unsigned int cpua3dnow:1;
 119       unsigned int cpua3dnowa:1;
 120       unsigned int cpusse3:1;
 121       unsigned int cpupadlock:1;
 122       unsigned int cpusvme:1;
 123       unsigned int cpuvmx:1;
 124       unsigned int cpussse3:1;
 125       unsigned int cpusse4a:1;
 126       unsigned int cpuabm:1;
 127       unsigned int cpusse4_1:1;
 128       unsigned int cpusse4_2:1;
 129       unsigned int cpulm:1;
 130       unsigned int cpu64:1;
 131       unsigned int cpuno64:1;
 132 #ifdef CpuUnused
 133       unsigned int unused:(CpuNumOfBits - CpuUnused);
 134 #endif
 135     } bitfield;
 136   unsigned int array[CpuNumOfUints];
 137 } i386_cpu_flags;
 138
 139 /* Position of opcode_modifier bits.  */
 140
 141 /* has direction bit. */
 142 #define D                       0
 143 /* set if operands can be words or dwords encoded the canonical way */
 144 #define W                       (D + 1)
 145 /* insn has a modrm byte. */
 146 #define Modrm                   (W + 1)
 147 /* register is in low 3 bits of opcode */
 148 #define ShortForm               (Modrm + 1)
 149 /* special case for jump insns.  */
 150 #define Jump                    (ShortForm + 1)
 151 /* call and jump */
 152 #define JumpDword               (Jump + 1)
 153 /* loop and jecxz */
 154 #define JumpByte                (JumpDword + 1)
 155 /* special case for intersegment leaps/calls */
 156 #define JumpInterSegment        (JumpByte + 1)
 157 /* FP insn memory format bit, sized by 0x4 */
 158 #define FloatMF                 (JumpInterSegment + 1)
 159 /* src/dest swap for floats. */
 160 #define FloatR                  (FloatMF + 1)
 161 /* has float insn direction bit. */
 162 #define FloatD                  (FloatR + 1)
 163 /* needs size prefix if in 32-bit mode */
 164 #define Size16                  (FloatD + 1)
 165 /* needs size prefix if in 16-bit mode */
 166 #define Size32                  (Size16 + 1)
 167 /* needs size prefix if in 64-bit mode */
 168 #define Size64                  (Size32 + 1)
 169 /* instruction ignores operand size prefix */
 170 #define IgnoreSize              (Size64 + 1)
 171 /* default insn size depends on mode */
 172 #define DefaultSize             (IgnoreSize + 1)
 173 /* b suffix on instruction illegal */
 174 #define No_bSuf                 (DefaultSize + 1)
 175 /* w suffix on instruction illegal */
 176 #define No_wSuf                 (No_bSuf + 1)
 177 /* l suffix on instruction illegal */
 178 #define No_lSuf                 (No_wSuf + 1)
 179 /* s suffix on instruction illegal */
 180 #define No_sSuf                 (No_lSuf + 1)
 181 /* q suffix on instruction illegal */
 182 #define No_qSuf                 (No_sSuf + 1)
 183 /* x suffix on instruction illegal */
 184 #define No_xSuf                 (No_qSuf + 1)
 185 /* instruction needs FWAIT */
 186 #define FWait                   (No_xSuf + 1)
 187 /* quick test for string instructions */
 188 #define IsString                (FWait + 1)
 189 /* fake an extra reg operand for clr, imul and special register
 190    processing for some instructions.  */
 191 #define RegKludge               (IsString + 1)
 192 /* opcode is a prefix */
 193 #define IsPrefix                (RegKludge + 1)
 194 /* instruction has extension in 8 bit imm */
 195 #define ImmExt                  (IsPrefix + 1)
 196 /* instruction don't need Rex64 prefix.  */
 197 #define NoRex64                 (ImmExt + 1)
 198 /* instruction require Rex64 prefix.  */
 199 #define Rex64                   (NoRex64 + 1)
 200 /* deprecated fp insn, gets a warning */
 201 #define Ugh                     (Rex64 + 1)
 202 /* The last bitfield in i386_opcode_modifier.  */
 203 #define Opcode_Modifier_Max     Ugh
 204
 205 typedef struct i386_opcode_modifier
 206 {
 207   unsigned int d:1;
 208   unsigned int w:1;
 209   unsigned int modrm:1;
 210   unsigned int shortform:1;
 211   unsigned int jump:1;
 212   unsigned int jumpdword:1;
 213   unsigned int jumpbyte:1;
 214   unsigned int jumpintersegment:1;
 215   unsigned int floatmf:1;
 216   unsigned int floatr:1;
 217   unsigned int floatd:1;
 218   unsigned int size16:1;
 219   unsigned int size32:1;
 220   unsigned int size64:1;
 221   unsigned int ignoresize:1;
 222   unsigned int defaultsize:1;
 223   unsigned int no_bsuf:1;
 224   unsigned int no_wsuf:1;
 225   unsigned int no_lsuf:1;
 226   unsigned int no_ssuf:1;
 227   unsigned int no_qsuf:1;
 228   unsigned int no_xsuf:1;
 229   unsigned int fwait:1;
 230   unsigned int isstring:1;
 231   unsigned int regkludge:1;
 232   unsigned int isprefix:1;
 233   unsigned int immext:1;
 234   unsigned int norex64:1;
 235   unsigned int rex64:1;
 236   unsigned int ugh:1;
 237 } i386_opcode_modifier;
 238
 239 /* Position of operand_type bits.  */
 240
 241 /* Registers  */
 242
 243 /* 8 bit reg */
 244 #define Reg8                    0
 245 /* 16 bit reg */
 246 #define Reg16                   (Reg8 + 1)
 247 /* 32 bit reg */
 248 #define Reg32                   (Reg16 + 1)
 249 /* 64 bit reg */
 250 #define Reg64                   (Reg32 + 1)
 251
 252 /* immediate */
 253
 254 /* 8 bit immediate */
 255 #define Imm8                    (Reg64 + 1)
 256 /* 8 bit immediate sign extended */
 257 #define Imm8S                   (Imm8 + 1)
 258 /* 16 bit immediate */
 259 #define Imm16                   (Imm8S + 1)
 260 /* 32 bit immediate */
 261 #define Imm32                   (Imm16 + 1)
 262 /* 32 bit immediate sign extended */
 263 #define Imm32S                  (Imm32 + 1)
 264 /* 64 bit immediate */
 265 #define Imm64                   (Imm32S + 1)
 266 /* 1 bit immediate */
 267 #define Imm1                    (Imm64 + 1)
 268
 269 /* memory */
 270
 271 #define BaseIndex               (Imm1 + 1)
 272 /* Disp8,16,32 are used in different ways, depending on the
 273    instruction.  For jumps, they specify the size of the PC relative
 274    displacement, for baseindex type instructions, they specify the
 275    size of the offset relative to the base register, and for memory
 276    offset instructions such as `mov 1234,%al' they specify the size of
 277    the offset relative to the segment base.  */
 278 /* 8 bit displacement */
 279 #define Disp8                   (BaseIndex + 1)
 280 /* 16 bit displacement */
 281 #define Disp16                  (Disp8 + 1)
 282 /* 32 bit displacement */
 283 #define Disp32                  (Disp16 + 1)
 284 /* 32 bit signed displacement */
 285 #define Disp32S                 (Disp32 + 1)
 286 /* 64 bit displacement */
 287 #define Disp64                  (Disp32S + 1)
 288
 289 /* specials */
 290
 291 /* register to hold in/out port addr = dx */
 292 #define InOutPortReg            (Disp64 + 1)
 293 /* register to hold shift count = cl */
 294 #define ShiftCount              (InOutPortReg + 1)
 295 /* Control register */
 296 #define Control                 (ShiftCount + 1)
 297 /* Debug register */
 298 #define Debug                   (Control + 1)
 299 /* Test register */
 300 #define Test                    (Debug + 1)
 301 /* Float register */
 302 #define FloatReg                (Test + 1)
 303 /* Float stack top %st(0) */
 304 #define FloatAcc                (FloatReg + 1)
 305 /* 2 bit segment register */
 306 #define SReg2                   (FloatAcc + 1)
 307 /* 3 bit segment register */
 308 #define SReg3                   (SReg2 + 1)
 309 /* Accumulator %al or %ax or %eax */
 310 #define Acc                     (SReg3 + 1)
 311 #define JumpAbsolute            (Acc + 1)
 312 /* MMX register */
 313 #define RegMMX                  (JumpAbsolute + 1)
 314 /* XMM registers in PIII */
 315 #define RegXMM                  (RegMMX + 1)
 316 /* String insn operand with fixed es segment */
 317 #define EsSeg                   (RegXMM + 1)
 318
 319 /* RegMem is for instructions with a modrm byte where the register
 320    destination operand should be encoded in the mod and regmem fields.
 321    Normally, it will be encoded in the reg field. We add a RegMem
 322    flag to the destination register operand to indicate that it should
 323    be encoded in the regmem field.  */
 324 #define RegMem                  (EsSeg + 1)
 325
 326 /* The last bitfield in i386_operand_type.  */
 327 #define OTMax                   RegMem
 328
 329 #define OTNumOfUints \
 330   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 331 #define OTNumOfBits \
 332   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 333
 334 /* If you get a compiler error for zero width of the unused field,
 335    comment it out.  */
 336 #if 0
 337 #define OTUnused                (RegMem + 1)
 338 #endif
 339
 340 typedef union i386_operand_type
 341 {
 342   struct
 343     {
 344       unsigned int reg8:1;
 345       unsigned int reg16:1;
 346       unsigned int reg32:1;
 347       unsigned int reg64:1;
 348       unsigned int imm8:1;
 349       unsigned int imm8s:1;
 350       unsigned int imm16:1;
 351       unsigned int imm32:1;
 352       unsigned int imm32s:1;
 353       unsigned int imm64:1;
 354       unsigned int imm1:1;
 355       unsigned int baseindex:1;
 356       unsigned int disp8:1;
 357       unsigned int disp16:1;
 358       unsigned int disp32:1;
 359       unsigned int disp32s:1;
 360       unsigned int disp64:1;
 361       unsigned int inoutportreg:1;
 362       unsigned int shiftcount:1;
 363       unsigned int control:1;
 364       unsigned int debug:1;
 365       unsigned int test:1;
 366       unsigned int floatreg:1;
 367       unsigned int floatacc:1;
 368       unsigned int sreg2:1;
 369       unsigned int sreg3:1;
 370       unsigned int acc:1;
 371       unsigned int jumpabsolute:1;
 372       unsigned int regmmx:1;
 373       unsigned int regxmm:1;
 374       unsigned int esseg:1;
 375       unsigned int regmem:1;
 376 #ifdef OTUnused
 377       unsigned int unused:(OTNumOfBits - OTUnused);
 378 #endif
 379     } bitfield;
 380   unsigned int array[OTNumOfUints];
 381 } i386_operand_type;
 382
 383 typedef struct template
 384 {
 385   /* instruction name sans width suffix ("mov" for movl insns) */
 386   char *name;
 387
 388   /* how many operands */
 389   unsigned int operands;
 390
 391   /* base_opcode is the fundamental opcode byte without optional
 392      prefix(es).  */
 393   unsigned int base_opcode;
 394 #define Opcode_D        0x2 /* Direction bit:
 395                                set if Reg --> Regmem;
 396                                unset if Regmem --> Reg. */
 397 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 398 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 399
 400   /* extension_opcode is the 3 bit extension for group <n> insns.
 401      This field is also used to store the 8-bit opcode suffix for the
 402      AMD 3DNow! instructions.
 403      If this template has no extension opcode (the usual case) use None */
 404   unsigned int extension_opcode;
 405 #define None 0xffff             /* If no extension_opcode is possible.  */
 406
 407   /* cpu feature flags */
 408   i386_cpu_flags cpu_flags;
 409
 410   /* the bits in opcode_modifier are used to generate the final opcode from
 411      the base_opcode.  These bits also are used to detect alternate forms of
 412      the same instruction */
 413   i386_opcode_modifier opcode_modifier;
 414
 415   /* operand_types[i] describes the type of operand i.  This is made
 416      by OR'ing together all of the possible type masks.  (e.g.
 417      'operand_types[i] = Reg|Imm' specifies that operand i can be
 418      either a register or an immediate operand.  */
 419   i386_operand_type operand_types[MAX_OPERANDS];
 420 }
 421 template;
 422
 423 extern const template i386_optab[];
 424
 425 /* these are for register name --> number & type hash lookup */
 426 typedef struct
 427 {
 428   char *reg_name;
 429   i386_operand_type reg_type;
 430   unsigned int reg_flags;
 431 #define RegRex      0x1  /* Extended register.  */
 432 #define RegRex64    0x2  /* Extended 8 bit register.  */
 433   unsigned int reg_num;
 434 }
 435 reg_entry;
 436
 437 /* Entries in i386_regtab.  */
 438 #define REGNAM_AL 1
 439 #define REGNAM_AX 25
 440 #define REGNAM_EAX 41
 441
 442 extern const reg_entry i386_regtab[];
 443 extern const unsigned int i386_regtab_size;
 444
 445 typedef struct
 446 {
 447   char *seg_name;
 448   unsigned int seg_prefix;
 449 }
 450 seg_entry;
 451
 452 extern const seg_entry cs;
 453 extern const seg_entry ds;
 454 extern const seg_entry ss;
 455 extern const seg_entry es;
 456 extern const seg_entry fs;
 457 extern const seg_entry gs;