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gas/
[binutils.git] / gas / config / tc-m68k.c
blobd4e21ceb46e80058b2095e78c0726f086dd484f2
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
177 0
178 };
179 static const enum m68k_register mcf51qe_ctrl[] = {
180 VBR,
181 0
182 };
183 static const enum m68k_register mcf5206_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
185 0
186 };
187 static const enum m68k_register mcf5208_ctrl[] = {
188 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
189 0
190 };
191 static const enum m68k_register mcf5210a_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
193 0
194 };
195 static const enum m68k_register mcf5213_ctrl[] = {
196 VBR, RAMBAR, RAMBAR1, FLASHBAR,
197 0
198 };
199 static const enum m68k_register mcf5216_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
201 0
202 };
203 static const enum m68k_register mcf52223_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
205 0
206 };
207 static const enum m68k_register mcf52235_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
209 0
210 };
211 static const enum m68k_register mcf5225_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
213 0
214 };
215 static const enum m68k_register mcf5235_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
217 0
218 };
219 static const enum m68k_register mcf5249_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
221 0
222 };
223 static const enum m68k_register mcf5250_ctrl[] = {
224 VBR,
225 0
226 };
227 static const enum m68k_register mcf5253_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
229 0
230 };
231 static const enum m68k_register mcf5271_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
233 0
234 };
235 static const enum m68k_register mcf5272_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
237 0
238 };
239 static const enum m68k_register mcf5275_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
241 0
242 };
243 static const enum m68k_register mcf5282_ctrl[] = {
244 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
245 0
246 };
247 static const enum m68k_register mcf5307_ctrl[] = {
248 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
249 0
250 };
251 static const enum m68k_register mcf5329_ctrl[] = {
252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
253 0
254 };
255 static const enum m68k_register mcf5373_ctrl[] = {
256 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
257 0
258 };
259 static const enum m68k_register mcfv4e_ctrl[] = {
260 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
261 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
262 MBAR, SECMBAR,
263 MPCR /* Multiprocessor Control register */,
264 EDRAMBAR /* Embedded DRAM Base Address Register */,
265 /* Permutation control registers. */
266 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
267 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
268 /* Legacy names */
269 TC /* ASID */, BUSCR /* MMUBAR */,
270 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
271 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
272 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
273 0
274 };
275 static const enum m68k_register mcf5407_ctrl[] = {
276 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
277 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
278 /* Legacy names */
279 TC /* ASID */,
280 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
281 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
282 0
283 };
284 static const enum m68k_register mcf54455_ctrl[] = {
285 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
286 VBR, PC, RAMBAR1, MBAR,
287 /* Legacy names */
288 TC /* ASID */, BUSCR /* MMUBAR */,
289 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
290 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
291 0
292 };
293 static const enum m68k_register mcf5475_ctrl[] = {
294 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
295 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
296 /* Legacy names */
297 TC /* ASID */, BUSCR /* MMUBAR */,
298 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
299 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
300 0
301 };
302 static const enum m68k_register mcf5485_ctrl[] = {
303 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
304 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
305 /* Legacy names */
306 TC /* ASID */, BUSCR /* MMUBAR */,
307 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
308 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
309 0
310 };
311 static const enum m68k_register fido_ctrl[] = {
312 SFC, DFC, USP, VBR, CAC, MBB,
313 0
314 };
315 #define cpu32_ctrl m68010_ctrl
316
317 static const enum m68k_register *control_regs;
318
319 /* Internal form of a 68020 instruction. */
320 struct m68k_it
321 {
322 const char *error;
323 const char *args; /* List of opcode info. */
324 int numargs;
325
326 int numo; /* Number of shorts in opcode. */
327 short opcode[11];
328
329 struct m68k_op operands[6];
330
331 int nexp; /* Number of exprs in use. */
332 struct m68k_exp exprs[4];
333
334 int nfrag; /* Number of frags we have to produce. */
335 struct
336 {
337 int fragoff; /* Where in the current opcode the frag ends. */
338 symbolS *fadd;
339 offsetT foff;
340 int fragty;
341 }
342 fragb[4];
343
344 int nrel; /* Num of reloc strucs in use. */
345 struct
346 {
347 int n;
348 expressionS exp;
349 char wid;
350 char pcrel;
351 /* In a pc relative address the difference between the address
352 of the offset and the address that the offset is relative
353 to. This depends on the addressing mode. Basically this
354 is the value to put in the offset field to address the
355 first byte of the offset, without regarding the special
356 significance of some values (in the branch instruction, for
357 example). */
358 int pcrel_fix;
359 #ifdef OBJ_ELF
360 /* Whether this expression needs special pic relocation, and if
361 so, which. */
362 enum pic_relocation pic_reloc;
363 #endif
364 }
365 reloc[5]; /* Five is enough??? */
366 };
367
368 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
369 #define float_of_arch(x) ((x) & mfloat)
370 #define mmu_of_arch(x) ((x) & mmmu)
371 #define arch_coldfire_p(x) ((x) & mcfisa_a)
372 #define arch_coldfire_fpu(x) ((x) & cfloat)
373
374 /* Macros for determining if cpu supports a specific addressing mode. */
375 #define HAVE_LONG_DISP(x) \
376 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
377 #define HAVE_LONG_CALL(x) \
378 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
379 #define HAVE_LONG_COND(x) \
380 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
381 #define HAVE_LONG_BRANCH(x) \
382 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
383
384 static struct m68k_it the_ins; /* The instruction being assembled. */
385
386 #define op(ex) ((ex)->exp.X_op)
387 #define adds(ex) ((ex)->exp.X_add_symbol)
388 #define subs(ex) ((ex)->exp.X_op_symbol)
389 #define offs(ex) ((ex)->exp.X_add_number)
390
391 /* Macros for adding things to the m68k_it struct. */
392 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
393
394 /* Like addword, but goes BEFORE general operands. */
395
396 static void
397 insop (int w, const struct m68k_incant *opcode)
398 {
399 int z;
400 for (z = the_ins.numo; z > opcode->m_codenum; --z)
401 the_ins.opcode[z] = the_ins.opcode[z - 1];
402 for (z = 0; z < the_ins.nrel; z++)
403 the_ins.reloc[z].n += 2;
404 for (z = 0; z < the_ins.nfrag; z++)
405 the_ins.fragb[z].fragoff++;
406 the_ins.opcode[opcode->m_codenum] = w;
407 the_ins.numo++;
408 }
409
410 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
411 Blecch. */
412 static void
413 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
414 {
415 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
416 ? the_ins.numo * 2 - 1
417 : (width == 'b'
418 ? the_ins.numo * 2 + 1
419 : the_ins.numo * 2));
420 the_ins.reloc[the_ins.nrel].exp = exp->exp;
421 the_ins.reloc[the_ins.nrel].wid = width;
422 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
423 #ifdef OBJ_ELF
424 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
425 #endif
426 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
427 }
428
429 /* Cause an extra frag to be generated here, inserting up to 10 bytes
430 (that value is chosen in the frag_var call in md_assemble). TYPE
431 is the subtype of the frag to be generated; its primary type is
432 rs_machine_dependent.
433
434 The TYPE parameter is also used by md_convert_frag_1 and
435 md_estimate_size_before_relax. The appropriate type of fixup will
436 be emitted by md_convert_frag_1.
437
438 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
439 static void
440 add_frag (symbolS *add, offsetT off, int type)
441 {
442 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
443 the_ins.fragb[the_ins.nfrag].fadd = add;
444 the_ins.fragb[the_ins.nfrag].foff = off;
445 the_ins.fragb[the_ins.nfrag++].fragty = type;
446 }
447
448 #define isvar(ex) \
449 (op (ex) != O_constant && op (ex) != O_big)
450
451 static char *crack_operand (char *str, struct m68k_op *opP);
452 static int get_num (struct m68k_exp *exp, int ok);
453 static int reverse_16_bits (int in);
454 static int reverse_8_bits (int in);
455 static void install_gen_operand (int mode, int val);
456 static void install_operand (int mode, int val);
457 static void s_bss (int);
458 static void s_data1 (int);
459 static void s_data2 (int);
460 static void s_even (int);
461 static void s_proc (int);
462 static void s_chip (int);
463 static void s_fopt (int);
464 static void s_opt (int);
465 static void s_reg (int);
466 static void s_restore (int);
467 static void s_save (int);
468 static void s_mri_if (int);
469 static void s_mri_else (int);
470 static void s_mri_endi (int);
471 static void s_mri_break (int);
472 static void s_mri_next (int);
473 static void s_mri_for (int);
474 static void s_mri_endf (int);
475 static void s_mri_repeat (int);
476 static void s_mri_until (int);
477 static void s_mri_while (int);
478 static void s_mri_endw (int);
479 static void s_m68k_cpu (int);
480 static void s_m68k_arch (int);
481
482 struct m68k_cpu
483 {
484 unsigned long arch; /* Architecture features. */
485 const enum m68k_register *control_regs; /* Control regs on chip */
486 const char *name; /* Name */
487 int alias; /* Alias for a cannonical name. If 1, then
488 succeeds canonical name, if -1 then
489 succeeds canonical name, if <-1 ||>1 this is a
490 deprecated name, and the next/previous name
491 should be used. */
492 };
493
494 /* We hold flags for features explicitly enabled and explicitly
495 disabled. */
496 static int current_architecture;
497 static int not_current_architecture;
498 static const struct m68k_cpu *selected_arch;
499 static const struct m68k_cpu *selected_cpu;
500 static int initialized;
501
502 /* Architecture models. */
503 static const struct m68k_cpu m68k_archs[] =
504 {
505 {m68000, m68000_ctrl, "68000", 0},
506 {m68010, m68010_ctrl, "68010", 0},
507 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
508 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
509 {m68040, m68040_ctrl, "68040", 0},
510 {m68060, m68060_ctrl, "68060", 0},
511 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
512 {fido_a, fido_ctrl, "fidoa", 0},
513 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
514 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
515 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
516 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
517 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
518 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
519 {0,0,NULL, 0}
520 };
521
522 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
523 for either. */
524 static const struct m68k_cpu m68k_extensions[] =
525 {
526 {m68851, NULL, "68851", -1},
527 {m68881, NULL, "68881", -1},
528 {m68881, NULL, "68882", -1},
529
530 {cfloat|m68881, NULL, "float", 0},
531
532 {mcfhwdiv, NULL, "div", 1},
533 {mcfusp, NULL, "usp", 1},
534 {mcfmac, NULL, "mac", 1},
535 {mcfemac, NULL, "emac", 1},
536
537 {0,NULL,NULL, 0}
538 };
539
540 /* Processor list */
541 static const struct m68k_cpu m68k_cpus[] =
542 {
543 {m68000, m68000_ctrl, "68000", 0},
544 {m68000, m68000_ctrl, "68ec000", 1},
545 {m68000, m68000_ctrl, "68hc000", 1},
546 {m68000, m68000_ctrl, "68hc001", 1},
547 {m68000, m68000_ctrl, "68008", 1},
548 {m68000, m68000_ctrl, "68302", 1},
549 {m68000, m68000_ctrl, "68306", 1},
550 {m68000, m68000_ctrl, "68307", 1},
551 {m68000, m68000_ctrl, "68322", 1},
552 {m68000, m68000_ctrl, "68356", 1},
553 {m68010, m68010_ctrl, "68010", 0},
554 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
555 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
556 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
557 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
558 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
559 {m68040, m68040_ctrl, "68040", 0},
560 {m68040, m68040_ctrl, "68ec040", 1},
561 {m68060, m68060_ctrl, "68060", 0},
562 {m68060, m68060_ctrl, "68ec060", 1},
563
564 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
565 {cpu32|m68881, cpu32_ctrl, "68330", 1},
566 {cpu32|m68881, cpu32_ctrl, "68331", 1},
567 {cpu32|m68881, cpu32_ctrl, "68332", 1},
568 {cpu32|m68881, cpu32_ctrl, "68333", 1},
569 {cpu32|m68881, cpu32_ctrl, "68334", 1},
570 {cpu32|m68881, cpu32_ctrl, "68336", 1},
571 {cpu32|m68881, cpu32_ctrl, "68340", 1},
572 {cpu32|m68881, cpu32_ctrl, "68341", 1},
573 {cpu32|m68881, cpu32_ctrl, "68349", 1},
574 {cpu32|m68881, cpu32_ctrl, "68360", 1},
575
576 {mcfisa_a|mcfisa_c|mcfusp, mcf51qe_ctrl, "51qe", 0},
577
578 {mcfisa_a, mcf_ctrl, "5200", 0},
579 {mcfisa_a, mcf_ctrl, "5202", 1},
580 {mcfisa_a, mcf_ctrl, "5204", 1},
581 {mcfisa_a, mcf5206_ctrl, "5206", 1},
582
583 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
584
585 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
586 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
587
588 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
590
591 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
592 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
594
595 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
598
599 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
600 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
601
602 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
603 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
604 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
606
607 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
608 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
609
610 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
612 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
613 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
615
616 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
617 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
618 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
619
620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
622
623 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
624
625 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
627
628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
632
633 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
634
635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
639
640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
643
644 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
645
646 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
647 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
648 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
649 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
650 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
651 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
652
653 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
654 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
655 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
656 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
657 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
658 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
659 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
660
661 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
662 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
663 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
664 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
665 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
666 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
667 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
668
669 {fido_a, fido_ctrl, "fidoa", 0},
670 {fido_a, fido_ctrl, "fido", 1},
671
672 {0,NULL,NULL, 0}
673 };
674
675 static const struct m68k_cpu *m68k_lookup_cpu
676 (const char *, const struct m68k_cpu *, int, int *);
677 static int m68k_set_arch (const char *, int, int);
678 static int m68k_set_cpu (const char *, int, int);
679 static int m68k_set_extension (const char *, int, int);
680 static void m68k_init_arch (void);
681
682 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
683 architecture and we have a lot of relaxation modes. */
684
685 /* Macros used in the relaxation code. */
686 #define TAB(x,y) (((x) << 2) + (y))
687 #define TABTYPE(x) ((x) >> 2)
688
689 /* Relaxation states. */
690 #define BYTE 0
691 #define SHORT 1
692 #define LONG 2
693 #define SZ_UNDEF 3
694
695 /* Here are all the relaxation modes we support. First we can relax ordinary
696 branches. On 68020 and higher and on CPU32 all branch instructions take
697 three forms, so on these CPUs all branches always remain as such. When we
698 have to expand to the LONG form on a 68000, though, we substitute an
699 absolute jump instead. This is a direct replacement for unconditional
700 branches and a branch over a jump for conditional branches. However, if the
701 user requires PIC and disables this with --pcrel, we can only relax between
702 BYTE and SHORT forms, punting if that isn't enough. This gives us four
703 different relaxation modes for branches: */
704
705 #define BRANCHBWL 0 /* Branch byte, word, or long. */
706 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
707 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
708 #define BRANCHBW 3 /* Branch byte or word. */
709
710 /* We also relax coprocessor branches and DBcc's. All CPUs that support
711 coprocessor branches support them in word and long forms, so we have only
712 one relaxation mode for them. DBcc's are word only on all CPUs. We can
713 relax them to the LONG form with a branch-around sequence. This sequence
714 can use a long branch (if available) or an absolute jump (if acceptable).
715 This gives us two relaxation modes. If long branches are not available and
716 absolute jumps are not acceptable, we don't relax DBcc's. */
717
718 #define FBRANCH 4 /* Coprocessor branch. */
719 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
720 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
721
722 /* That's all for instruction relaxation. However, we also relax PC-relative
723 operands. Specifically, we have three operand relaxation modes. On the
724 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
725 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
726 two. Also PC+displacement+index operands in their simple form (with a non-
727 suppressed index without memory indirection) are supported on all CPUs, but
728 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
729 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
730 form of the PC+displacement+index operand. Finally, some absolute operands
731 can be relaxed down to 16-bit PC-relative. */
732
733 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
734 #define PCINDEX 8 /* PC + displacement + index. */
735 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
736
737 /* Note that calls to frag_var need to specify the maximum expansion
738 needed; this is currently 10 bytes for DBCC. */
739
740 /* The fields are:
741 How far Forward this mode will reach:
742 How far Backward this mode will reach:
743 How many bytes this mode will add to the size of the frag
744 Which mode to go to if the offset won't fit in this one
745
746 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
747 relax_typeS md_relax_table[] =
748 {
749 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
750 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
751 { 0, 0, 4, 0 },
752 { 1, 1, 0, 0 },
753
754 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
755 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
756 { 0, 0, 4, 0 },
757 { 1, 1, 0, 0 },
758
759 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
760 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
761 { 0, 0, 6, 0 },
762 { 1, 1, 0, 0 },
763
764 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
765 { 0, 0, 2, 0 },
766 { 1, 1, 0, 0 },
767 { 1, 1, 0, 0 },
768
769 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
770 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
771 { 0, 0, 4, 0 },
772 { 1, 1, 0, 0 },
773
774 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
775 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
776 { 0, 0, 10, 0 },
777 { 1, 1, 0, 0 },
778
779 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
780 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
781 { 0, 0, 10, 0 },
782 { 1, 1, 0, 0 },
783
784 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
785 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
786 { 0, 0, 6, 0 },
787 { 1, 1, 0, 0 },
788
789 { 125, -130, 0, TAB (PCINDEX, SHORT) },
790 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
791 { 0, 0, 4, 0 },
792 { 1, 1, 0, 0 },
793
794 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
795 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
796 { 0, 0, 4, 0 },
797 { 1, 1, 0, 0 },
798 };
799
800 /* These are the machine dependent pseudo-ops. These are included so
801 the assembler can work on the output from the SUN C compiler, which
802 generates these. */
803
804 /* This table describes all the machine specific pseudo-ops the assembler
805 has to support. The fields are:
806 pseudo-op name without dot
807 function to call to execute this pseudo-op
808 Integer arg to pass to the function. */
809 const pseudo_typeS md_pseudo_table[] =
810 {
811 {"data1", s_data1, 0},
812 {"data2", s_data2, 0},
813 {"bss", s_bss, 0},
814 {"even", s_even, 0},
815 {"skip", s_space, 0},
816 {"proc", s_proc, 0},
817 #if defined (TE_SUN3) || defined (OBJ_ELF)
818 {"align", s_align_bytes, 0},
819 #endif
820 #ifdef OBJ_ELF
821 {"swbeg", s_ignore, 0},
822 #endif
823 {"extend", float_cons, 'x'},
824 {"ldouble", float_cons, 'x'},
825
826 {"arch", s_m68k_arch, 0},
827 {"cpu", s_m68k_cpu, 0},
828
829 /* The following pseudo-ops are supported for MRI compatibility. */
830 {"chip", s_chip, 0},
831 {"comline", s_space, 1},
832 {"fopt", s_fopt, 0},
833 {"mask2", s_ignore, 0},
834 {"opt", s_opt, 0},
835 {"reg", s_reg, 0},
836 {"restore", s_restore, 0},
837 {"save", s_save, 0},
838
839 {"if", s_mri_if, 0},
840 {"if.b", s_mri_if, 'b'},
841 {"if.w", s_mri_if, 'w'},
842 {"if.l", s_mri_if, 'l'},
843 {"else", s_mri_else, 0},
844 {"else.s", s_mri_else, 's'},
845 {"else.l", s_mri_else, 'l'},
846 {"endi", s_mri_endi, 0},
847 {"break", s_mri_break, 0},
848 {"break.s", s_mri_break, 's'},
849 {"break.l", s_mri_break, 'l'},
850 {"next", s_mri_next, 0},
851 {"next.s", s_mri_next, 's'},
852 {"next.l", s_mri_next, 'l'},
853 {"for", s_mri_for, 0},
854 {"for.b", s_mri_for, 'b'},
855 {"for.w", s_mri_for, 'w'},
856 {"for.l", s_mri_for, 'l'},
857 {"endf", s_mri_endf, 0},
858 {"repeat", s_mri_repeat, 0},
859 {"until", s_mri_until, 0},
860 {"until.b", s_mri_until, 'b'},
861 {"until.w", s_mri_until, 'w'},
862 {"until.l", s_mri_until, 'l'},
863 {"while", s_mri_while, 0},
864 {"while.b", s_mri_while, 'b'},
865 {"while.w", s_mri_while, 'w'},
866 {"while.l", s_mri_while, 'l'},
867 {"endw", s_mri_endw, 0},
868
869 {0, 0, 0}
870 };
871
872 /* The mote pseudo ops are put into the opcode table, since they
873 don't start with a . they look like opcodes to gas. */
874
875 const pseudo_typeS mote_pseudo_table[] =
876 {
877
878 {"dcl", cons, 4},
879 {"dc", cons, 2},
880 {"dcw", cons, 2},
881 {"dcb", cons, 1},
882
883 {"dsl", s_space, 4},
884 {"ds", s_space, 2},
885 {"dsw", s_space, 2},
886 {"dsb", s_space, 1},
887
888 {"xdef", s_globl, 0},
889 #ifdef OBJ_ELF
890 {"align", s_align_bytes, 0},
891 #else
892 {"align", s_align_ptwo, 0},
893 #endif
894 #ifdef M68KCOFF
895 {"sect", obj_coff_section, 0},
896 {"section", obj_coff_section, 0},
897 #endif
898 {0, 0, 0}
899 };
900
901 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
902 gives identical results to a 32-bit host. */
903 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
904 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
905
906 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
907 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
908 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
909 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
910
911 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
912 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
913 #define islong(x) (1)
914
915 static char notend_table[256];
916 static char alt_notend_table[256];
917 #define notend(s) \
918 (! (notend_table[(unsigned char) *s] \
919 || (*s == ':' \
920 && alt_notend_table[(unsigned char) s[1]])))
921
922 #ifdef OBJ_ELF
923
924 /* Return zero if the reference to SYMBOL from within the same segment may
925 be relaxed. */
926
927 /* On an ELF system, we can't relax an externally visible symbol,
928 because it may be overridden by a shared library. However, if
929 TARGET_OS is "elf", then we presume that we are assembling for an
930 embedded system, in which case we don't have to worry about shared
931 libraries, and we can relax any external sym. */
932
933 #define relaxable_symbol(symbol) \
934 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
935 || S_IS_WEAK (symbol)))
936
937 /* Compute the relocation code for a fixup of SIZE bytes, using pc
938 relative relocation if PCREL is non-zero. PIC says whether a special
939 pic relocation was requested. */
940
941 static bfd_reloc_code_real_type
942 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
943 {
944 switch (pic)
945 {
946 case pic_got_pcrel:
947 switch (size)
948 {
949 case 1:
950 return BFD_RELOC_8_GOT_PCREL;
951 case 2:
952 return BFD_RELOC_16_GOT_PCREL;
953 case 4:
954 return BFD_RELOC_32_GOT_PCREL;
955 }
956 break;
957
958 case pic_got_off:
959 switch (size)
960 {
961 case 1:
962 return BFD_RELOC_8_GOTOFF;
963 case 2:
964 return BFD_RELOC_16_GOTOFF;
965 case 4:
966 return BFD_RELOC_32_GOTOFF;
967 }
968 break;
969
970 case pic_plt_pcrel:
971 switch (size)
972 {
973 case 1:
974 return BFD_RELOC_8_PLT_PCREL;
975 case 2:
976 return BFD_RELOC_16_PLT_PCREL;
977 case 4:
978 return BFD_RELOC_32_PLT_PCREL;
979 }
980 break;
981
982 case pic_plt_off:
983 switch (size)
984 {
985 case 1:
986 return BFD_RELOC_8_PLTOFF;
987 case 2:
988 return BFD_RELOC_16_PLTOFF;
989 case 4:
990 return BFD_RELOC_32_PLTOFF;
991 }
992 break;
993
994 case pic_none:
995 if (pcrel)
996 {
997 switch (size)
998 {
999 case 1:
1000 return BFD_RELOC_8_PCREL;
1001 case 2:
1002 return BFD_RELOC_16_PCREL;
1003 case 4:
1004 return BFD_RELOC_32_PCREL;
1005 }
1006 }
1007 else
1008 {
1009 switch (size)
1010 {
1011 case 1:
1012 return BFD_RELOC_8;
1013 case 2:
1014 return BFD_RELOC_16;
1015 case 4:
1016 return BFD_RELOC_32;
1017 }
1018 }
1019 }
1020
1021 if (pcrel)
1022 {
1023 if (pic == pic_none)
1024 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1025 else
1026 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1027 }
1028 else
1029 {
1030 if (pic == pic_none)
1031 as_bad (_("Can not do %d byte relocation"), size);
1032 else
1033 as_bad (_("Can not do %d byte pic relocation"), size);
1034 }
1035
1036 return BFD_RELOC_NONE;
1037 }
1038
1039 /* Here we decide which fixups can be adjusted to make them relative
1040 to the beginning of the section instead of the symbol. Basically
1041 we need to make sure that the dynamic relocations are done
1042 correctly, so in some cases we force the original symbol to be
1043 used. */
1044 int
1045 tc_m68k_fix_adjustable (fixS *fixP)
1046 {
1047 /* Adjust_reloc_syms doesn't know about the GOT. */
1048 switch (fixP->fx_r_type)
1049 {
1050 case BFD_RELOC_8_GOT_PCREL:
1051 case BFD_RELOC_16_GOT_PCREL:
1052 case BFD_RELOC_32_GOT_PCREL:
1053 case BFD_RELOC_8_GOTOFF:
1054 case BFD_RELOC_16_GOTOFF:
1055 case BFD_RELOC_32_GOTOFF:
1056 case BFD_RELOC_8_PLT_PCREL:
1057 case BFD_RELOC_16_PLT_PCREL:
1058 case BFD_RELOC_32_PLT_PCREL:
1059 case BFD_RELOC_8_PLTOFF:
1060 case BFD_RELOC_16_PLTOFF:
1061 case BFD_RELOC_32_PLTOFF:
1062 return 0;
1063
1064 case BFD_RELOC_VTABLE_INHERIT:
1065 case BFD_RELOC_VTABLE_ENTRY:
1066 return 0;
1067
1068 default:
1069 return 1;
1070 }
1071 }
1072
1073 #else /* !OBJ_ELF */
1074
1075 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1076
1077 /* PR gas/3041 Weak symbols are not relaxable
1078 because they must be treated as extern. */
1079 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1080
1081 #endif /* OBJ_ELF */
1082
1083 arelent *
1084 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1085 {
1086 arelent *reloc;
1087 bfd_reloc_code_real_type code;
1088
1089 /* If the tcbit is set, then this was a fixup of a negative value
1090 that was never resolved. We do not have a reloc to handle this,
1091 so just return. We assume that other code will have detected this
1092 situation and produced a helpful error message, so we just tell the
1093 user that the reloc cannot be produced. */
1094 if (fixp->fx_tcbit)
1095 {
1096 if (fixp->fx_addsy)
1097 as_bad_where (fixp->fx_file, fixp->fx_line,
1098 _("Unable to produce reloc against symbol '%s'"),
1099 S_GET_NAME (fixp->fx_addsy));
1100 return NULL;
1101 }
1102
1103 if (fixp->fx_r_type != BFD_RELOC_NONE)
1104 {
1105 code = fixp->fx_r_type;
1106
1107 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1108 that fixup_segment converted a non-PC relative reloc into a
1109 PC relative reloc. In such a case, we need to convert the
1110 reloc code. */
1111 if (fixp->fx_pcrel)
1112 {
1113 switch (code)
1114 {
1115 case BFD_RELOC_8:
1116 code = BFD_RELOC_8_PCREL;
1117 break;
1118 case BFD_RELOC_16:
1119 code = BFD_RELOC_16_PCREL;
1120 break;
1121 case BFD_RELOC_32:
1122 code = BFD_RELOC_32_PCREL;
1123 break;
1124 case BFD_RELOC_8_PCREL:
1125 case BFD_RELOC_16_PCREL:
1126 case BFD_RELOC_32_PCREL:
1127 case BFD_RELOC_8_GOT_PCREL:
1128 case BFD_RELOC_16_GOT_PCREL:
1129 case BFD_RELOC_32_GOT_PCREL:
1130 case BFD_RELOC_8_GOTOFF:
1131 case BFD_RELOC_16_GOTOFF:
1132 case BFD_RELOC_32_GOTOFF:
1133 case BFD_RELOC_8_PLT_PCREL:
1134 case BFD_RELOC_16_PLT_PCREL:
1135 case BFD_RELOC_32_PLT_PCREL:
1136 case BFD_RELOC_8_PLTOFF:
1137 case BFD_RELOC_16_PLTOFF:
1138 case BFD_RELOC_32_PLTOFF:
1139 break;
1140 default:
1141 as_bad_where (fixp->fx_file, fixp->fx_line,
1142 _("Cannot make %s relocation PC relative"),
1143 bfd_get_reloc_code_name (code));
1144 }
1145 }
1146 }
1147 else
1148 {
1149 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1150 switch (F (fixp->fx_size, fixp->fx_pcrel))
1151 {
1152 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1153 MAP (1, 0, BFD_RELOC_8);
1154 MAP (2, 0, BFD_RELOC_16);
1155 MAP (4, 0, BFD_RELOC_32);
1156 MAP (1, 1, BFD_RELOC_8_PCREL);
1157 MAP (2, 1, BFD_RELOC_16_PCREL);
1158 MAP (4, 1, BFD_RELOC_32_PCREL);
1159 default:
1160 abort ();
1161 }
1162 }
1163 #undef F
1164 #undef MAP
1165
1166 reloc = (arelent *) xmalloc (sizeof (arelent));
1167 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1168 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1169 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1170 #ifndef OBJ_ELF
1171 if (fixp->fx_pcrel)
1172 reloc->addend = fixp->fx_addnumber;
1173 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1174 && fixp->fx_addsy
1175 && S_IS_WEAK (fixp->fx_addsy)
1176 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1177 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1178 to put the symbol offset into frags referencing a weak symbol. */
1179 reloc->addend = fixp->fx_addnumber
1180 - (S_GET_VALUE (fixp->fx_addsy) * 2);
1181 else
1182 reloc->addend = 0;
1183 #else
1184 if (!fixp->fx_pcrel)
1185 reloc->addend = fixp->fx_addnumber;
1186 else
1187 reloc->addend = (section->vma
1188 /* Explicit sign extension in case char is
1189 unsigned. */
1190 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1191 + fixp->fx_addnumber
1192 + md_pcrel_from (fixp));
1193 #endif
1194
1195 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1196 assert (reloc->howto != 0);
1197
1198 return reloc;
1199 }
1200
1201 /* Handle of the OPCODE hash table. NULL means any use before
1202 m68k_ip_begin() will crash. */
1203 static struct hash_control *op_hash;
1204 \f
1205 /* Assemble an m68k instruction. */
1206
1207 static void
1208 m68k_ip (char *instring)
1209 {
1210 register char *p;
1211 register struct m68k_op *opP;
1212 register const struct m68k_incant *opcode;
1213 register const char *s;
1214 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1215 char *pdot, *pdotmove;
1216 enum m68k_size siz1, siz2;
1217 char c;
1218 int losing;
1219 int opsfound;
1220 struct m68k_op operands_backup[6];
1221 LITTLENUM_TYPE words[6];
1222 LITTLENUM_TYPE *wordp;
1223 unsigned long ok_arch = 0;
1224
1225 if (*instring == ' ')
1226 instring++; /* Skip leading whitespace. */
1227
1228 /* Scan up to end of operation-code, which MUST end in end-of-string
1229 or exactly 1 space. */
1230 pdot = 0;
1231 for (p = instring; *p != '\0'; p++)
1232 {
1233 if (*p == ' ')
1234 break;
1235 if (*p == '.')
1236 pdot = p;
1237 }
1238
1239 if (p == instring)
1240 {
1241 the_ins.error = _("No operator");
1242 return;
1243 }
1244
1245 /* p now points to the end of the opcode name, probably whitespace.
1246 Make sure the name is null terminated by clobbering the
1247 whitespace, look it up in the hash table, then fix it back.
1248 Remove a dot, first, since the opcode tables have none. */
1249 if (pdot != NULL)
1250 {
1251 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1252 *pdotmove = pdotmove[1];
1253 p--;
1254 }
1255
1256 c = *p;
1257 *p = '\0';
1258 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1259 *p = c;
1260
1261 if (pdot != NULL)
1262 {
1263 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1264 *pdotmove = pdotmove[-1];
1265 *pdot = '.';
1266 ++p;
1267 }
1268
1269 if (opcode == NULL)
1270 {
1271 the_ins.error = _("Unknown operator");
1272 return;
1273 }
1274
1275 /* Found a legitimate opcode, start matching operands. */
1276 while (*p == ' ')
1277 ++p;
1278
1279 if (opcode->m_operands == 0)
1280 {
1281 char *old = input_line_pointer;
1282 *old = '\n';
1283 input_line_pointer = p;
1284 /* Ahh - it's a motorola style psuedo op. */
1285 mote_pseudo_table[opcode->m_opnum].poc_handler
1286 (mote_pseudo_table[opcode->m_opnum].poc_val);
1287 input_line_pointer = old;
1288 *old = 0;
1289
1290 return;
1291 }
1292
1293 if (flag_mri && opcode->m_opnum == 0)
1294 {
1295 /* In MRI mode, random garbage is allowed after an instruction
1296 which accepts no operands. */
1297 the_ins.args = opcode->m_operands;
1298 the_ins.numargs = opcode->m_opnum;
1299 the_ins.numo = opcode->m_codenum;
1300 the_ins.opcode[0] = getone (opcode);
1301 the_ins.opcode[1] = gettwo (opcode);
1302 return;
1303 }
1304
1305 for (opP = &the_ins.operands[0]; *p; opP++)
1306 {
1307 p = crack_operand (p, opP);
1308
1309 if (opP->error)
1310 {
1311 the_ins.error = opP->error;
1312 return;
1313 }
1314 }
1315
1316 opsfound = opP - &the_ins.operands[0];
1317
1318 /* This ugly hack is to support the floating pt opcodes in their
1319 standard form. Essentially, we fake a first enty of type COP#1 */
1320 if (opcode->m_operands[0] == 'I')
1321 {
1322 int n;
1323
1324 for (n = opsfound; n > 0; --n)
1325 the_ins.operands[n] = the_ins.operands[n - 1];
1326
1327 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1328 the_ins.operands[0].mode = CONTROL;
1329 the_ins.operands[0].reg = m68k_float_copnum;
1330 opsfound++;
1331 }
1332
1333 /* We've got the operands. Find an opcode that'll accept them. */
1334 for (losing = 0;;)
1335 {
1336 /* If we didn't get the right number of ops, or we have no
1337 common model with this pattern then reject this pattern. */
1338
1339 ok_arch |= opcode->m_arch;
1340 if (opsfound != opcode->m_opnum
1341 || ((opcode->m_arch & current_architecture) == 0))
1342 ++losing;
1343 else
1344 {
1345 int i;
1346
1347 /* Make a copy of the operands of this insn so that
1348 we can modify them safely, should we want to. */
1349 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1350 for (i = 0; i < opsfound; i++)
1351 operands_backup[i] = the_ins.operands[i];
1352
1353 for (s = opcode->m_operands, opP = &operands_backup[0];
1354 *s && !losing;
1355 s += 2, opP++)
1356 {
1357 /* Warning: this switch is huge! */
1358 /* I've tried to organize the cases into this order:
1359 non-alpha first, then alpha by letter. Lower-case
1360 goes directly before uppercase counterpart. */
1361 /* Code with multiple case ...: gets sorted by the lowest
1362 case ... it belongs to. I hope this makes sense. */
1363 switch (*s)
1364 {
1365 case '!':
1366 switch (opP->mode)
1367 {
1368 case IMMED:
1369 case DREG:
1370 case AREG:
1371 case FPREG:
1372 case CONTROL:
1373 case AINC:
1374 case ADEC:
1375 case REGLST:
1376 losing++;
1377 break;
1378 default:
1379 break;
1380 }
1381 break;
1382
1383 case '<':
1384 switch (opP->mode)
1385 {
1386 case DREG:
1387 case AREG:
1388 case FPREG:
1389 case CONTROL:
1390 case IMMED:
1391 case ADEC:
1392 case REGLST:
1393 losing++;
1394 break;
1395 default:
1396 break;
1397 }
1398 break;
1399
1400 case '>':
1401 switch (opP->mode)
1402 {
1403 case DREG:
1404 case AREG:
1405 case FPREG:
1406 case CONTROL:
1407 case IMMED:
1408 case AINC:
1409 case REGLST:
1410 losing++;
1411 break;
1412 case ABSL:
1413 break;
1414 default:
1415 if (opP->reg == PC
1416 || opP->reg == ZPC)
1417 losing++;
1418 break;
1419 }
1420 break;
1421
1422 case 'm':
1423 switch (opP->mode)
1424 {
1425 case DREG:
1426 case AREG:
1427 case AINDR:
1428 case AINC:
1429 case ADEC:
1430 break;
1431 default:
1432 losing++;
1433 }
1434 break;
1435
1436 case 'n':
1437 switch (opP->mode)
1438 {
1439 case DISP:
1440 break;
1441 default:
1442 losing++;
1443 }
1444 break;
1445
1446 case 'o':
1447 switch (opP->mode)
1448 {
1449 case BASE:
1450 case ABSL:
1451 case IMMED:
1452 break;
1453 default:
1454 losing++;
1455 }
1456 break;
1457
1458 case 'p':
1459 switch (opP->mode)
1460 {
1461 case DREG:
1462 case AREG:
1463 case AINDR:
1464 case AINC:
1465 case ADEC:
1466 break;
1467 case DISP:
1468 if (opP->reg == PC || opP->reg == ZPC)
1469 losing++;
1470 break;
1471 default:
1472 losing++;
1473 }
1474 break;
1475
1476 case 'q':
1477 switch (opP->mode)
1478 {
1479 case DREG:
1480 case AINDR:
1481 case AINC:
1482 case ADEC:
1483 break;
1484 case DISP:
1485 if (opP->reg == PC || opP->reg == ZPC)
1486 losing++;
1487 break;
1488 default:
1489 losing++;
1490 break;
1491 }
1492 break;
1493
1494 case 'v':
1495 switch (opP->mode)
1496 {
1497 case DREG:
1498 case AINDR:
1499 case AINC:
1500 case ADEC:
1501 case ABSL:
1502 break;
1503 case DISP:
1504 if (opP->reg == PC || opP->reg == ZPC)
1505 losing++;
1506 break;
1507 default:
1508 losing++;
1509 break;
1510 }
1511 break;
1512
1513 case '#':
1514 if (opP->mode != IMMED)
1515 losing++;
1516 else if (s[1] == 'b'
1517 && ! isvar (&opP->disp)
1518 && (opP->disp.exp.X_op != O_constant
1519 || ! isbyte (opP->disp.exp.X_add_number)))
1520 losing++;
1521 else if (s[1] == 'B'
1522 && ! isvar (&opP->disp)
1523 && (opP->disp.exp.X_op != O_constant
1524 || ! issbyte (opP->disp.exp.X_add_number)))
1525 losing++;
1526 else if (s[1] == 'w'
1527 && ! isvar (&opP->disp)
1528 && (opP->disp.exp.X_op != O_constant
1529 || ! isword (opP->disp.exp.X_add_number)))
1530 losing++;
1531 else if (s[1] == 'W'
1532 && ! isvar (&opP->disp)
1533 && (opP->disp.exp.X_op != O_constant
1534 || ! issword (opP->disp.exp.X_add_number)))
1535 losing++;
1536 break;
1537
1538 case '^':
1539 case 'T':
1540 if (opP->mode != IMMED)
1541 losing++;
1542 break;
1543
1544 case '$':
1545 if (opP->mode == AREG
1546 || opP->mode == CONTROL
1547 || opP->mode == FPREG
1548 || opP->mode == IMMED
1549 || opP->mode == REGLST
1550 || (opP->mode != ABSL
1551 && (opP->reg == PC
1552 || opP->reg == ZPC)))
1553 losing++;
1554 break;
1555
1556 case '%':
1557 if (opP->mode == CONTROL
1558 || opP->mode == FPREG
1559 || opP->mode == REGLST
1560 || opP->mode == IMMED
1561 || (opP->mode != ABSL
1562 && (opP->reg == PC
1563 || opP->reg == ZPC)))
1564 losing++;
1565 break;
1566
1567 case '&':
1568 switch (opP->mode)
1569 {
1570 case DREG:
1571 case AREG:
1572 case FPREG:
1573 case CONTROL:
1574 case IMMED:
1575 case AINC:
1576 case ADEC:
1577 case REGLST:
1578 losing++;
1579 break;
1580 case ABSL:
1581 break;
1582 default:
1583 if (opP->reg == PC
1584 || opP->reg == ZPC)
1585 losing++;
1586 break;
1587 }
1588 break;
1589
1590 case '*':
1591 if (opP->mode == CONTROL
1592 || opP->mode == FPREG
1593 || opP->mode == REGLST)
1594 losing++;
1595 break;
1596
1597 case '+':
1598 if (opP->mode != AINC)
1599 losing++;
1600 break;
1601
1602 case '-':
1603 if (opP->mode != ADEC)
1604 losing++;
1605 break;
1606
1607 case '/':
1608 switch (opP->mode)
1609 {
1610 case AREG:
1611 case CONTROL:
1612 case FPREG:
1613 case AINC:
1614 case ADEC:
1615 case IMMED:
1616 case REGLST:
1617 losing++;
1618 break;
1619 default:
1620 break;
1621 }
1622 break;
1623
1624 case ';':
1625 switch (opP->mode)
1626 {
1627 case AREG:
1628 case CONTROL:
1629 case FPREG:
1630 case REGLST:
1631 losing++;
1632 break;
1633 default:
1634 break;
1635 }
1636 break;
1637
1638 case '?':
1639 switch (opP->mode)
1640 {
1641 case AREG:
1642 case CONTROL:
1643 case FPREG:
1644 case AINC:
1645 case ADEC:
1646 case IMMED:
1647 case REGLST:
1648 losing++;
1649 break;
1650 case ABSL:
1651 break;
1652 default:
1653 if (opP->reg == PC || opP->reg == ZPC)
1654 losing++;
1655 break;
1656 }
1657 break;
1658
1659 case '@':
1660 switch (opP->mode)
1661 {
1662 case AREG:
1663 case CONTROL:
1664 case FPREG:
1665 case IMMED:
1666 case REGLST:
1667 losing++;
1668 break;
1669 default:
1670 break;
1671 }
1672 break;
1673
1674 case '~': /* For now! (JF FOO is this right?) */
1675 switch (opP->mode)
1676 {
1677 case DREG:
1678 case AREG:
1679 case CONTROL:
1680 case FPREG:
1681 case IMMED:
1682 case REGLST:
1683 losing++;
1684 break;
1685 case ABSL:
1686 break;
1687 default:
1688 if (opP->reg == PC
1689 || opP->reg == ZPC)
1690 losing++;
1691 break;
1692 }
1693 break;
1694
1695 case '3':
1696 if (opP->mode != CONTROL
1697 || (opP->reg != TT0 && opP->reg != TT1))
1698 losing++;
1699 break;
1700
1701 case 'A':
1702 if (opP->mode != AREG)
1703 losing++;
1704 break;
1705
1706 case 'a':
1707 if (opP->mode != AINDR)
1708 ++losing;
1709 break;
1710
1711 case '4':
1712 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1713 && (opP->mode != DISP
1714 || opP->reg < ADDR0
1715 || opP->reg > ADDR7))
1716 ++losing;
1717 break;
1718
1719 case 'B': /* FOO */
1720 if (opP->mode != ABSL
1721 || (flag_long_jumps
1722 && strncmp (instring, "jbsr", 4) == 0))
1723 losing++;
1724 break;
1725
1726 case 'b':
1727 switch (opP->mode)
1728 {
1729 case IMMED:
1730 case ABSL:
1731 case AREG:
1732 case FPREG:
1733 case CONTROL:
1734 case POST:
1735 case PRE:
1736 case REGLST:
1737 losing++;
1738 break;
1739 default:
1740 break;
1741 }
1742 break;
1743
1744 case 'C':
1745 if (opP->mode != CONTROL || opP->reg != CCR)
1746 losing++;
1747 break;
1748
1749 case 'd':
1750 if (opP->mode != DISP
1751 || opP->reg < ADDR0
1752 || opP->reg > ADDR7)
1753 losing++;
1754 break;
1755
1756 case 'D':
1757 if (opP->mode != DREG)
1758 losing++;
1759 break;
1760
1761 case 'E':
1762 if (opP->reg != ACC)
1763 losing++;
1764 break;
1765
1766 case 'e':
1767 if (opP->reg != ACC && opP->reg != ACC1
1768 && opP->reg != ACC2 && opP->reg != ACC3)
1769 losing++;
1770 break;
1771
1772 case 'F':
1773 if (opP->mode != FPREG)
1774 losing++;
1775 break;
1776
1777 case 'G':
1778 if (opP->reg != MACSR)
1779 losing++;
1780 break;
1781
1782 case 'g':
1783 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1784 losing++;
1785 break;
1786
1787 case 'H':
1788 if (opP->reg != MASK)
1789 losing++;
1790 break;
1791
1792 case 'I':
1793 if (opP->mode != CONTROL
1794 || opP->reg < COP0
1795 || opP->reg > COP7)
1796 losing++;
1797 break;
1798
1799 case 'i':
1800 if (opP->mode != LSH && opP->mode != RSH)
1801 losing++;
1802 break;
1803
1804 case 'J':
1805 if (opP->mode != CONTROL
1806 || opP->reg < USP
1807 || opP->reg > last_movec_reg
1808 || !control_regs)
1809 losing++;
1810 else
1811 {
1812 const enum m68k_register *rp;
1813
1814 for (rp = control_regs; *rp; rp++)
1815 {
1816 if (*rp == opP->reg)
1817 break;
1818 /* In most CPUs RAMBAR refers to control reg
1819 c05 (RAMBAR1), but a few CPUs have it
1820 refer to c04 (RAMBAR0). */
1821 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1822 {
1823 opP->reg = RAMBAR_ALT;
1824 break;
1825 }
1826 }
1827 if (*rp == 0)
1828 losing++;
1829 }
1830 break;
1831
1832 case 'k':
1833 if (opP->mode != IMMED)
1834 losing++;
1835 break;
1836
1837 case 'l':
1838 case 'L':
1839 if (opP->mode == DREG
1840 || opP->mode == AREG
1841 || opP->mode == FPREG)
1842 {
1843 if (s[1] == '8')
1844 losing++;
1845 else
1846 {
1847 switch (opP->mode)
1848 {
1849 case DREG:
1850 opP->mask = 1 << (opP->reg - DATA0);
1851 break;
1852 case AREG:
1853 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1854 break;
1855 case FPREG:
1856 opP->mask = 1 << (opP->reg - FP0 + 16);
1857 break;
1858 default:
1859 abort ();
1860 }
1861 opP->mode = REGLST;
1862 }
1863 }
1864 else if (opP->mode == CONTROL)
1865 {
1866 if (s[1] != '8')
1867 losing++;
1868 else
1869 {
1870 switch (opP->reg)
1871 {
1872 case FPI:
1873 opP->mask = 1 << 24;
1874 break;
1875 case FPS:
1876 opP->mask = 1 << 25;
1877 break;
1878 case FPC:
1879 opP->mask = 1 << 26;
1880 break;
1881 default:
1882 losing++;
1883 break;
1884 }
1885 opP->mode = REGLST;
1886 }
1887 }
1888 else if (opP->mode != REGLST)
1889 losing++;
1890 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1891 losing++;
1892 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1893 losing++;
1894 break;
1895
1896 case 'M':
1897 if (opP->mode != IMMED)
1898 losing++;
1899 else if (opP->disp.exp.X_op != O_constant
1900 || ! issbyte (opP->disp.exp.X_add_number))
1901 losing++;
1902 else if (! m68k_quick
1903 && instring[3] != 'q'
1904 && instring[4] != 'q')
1905 losing++;
1906 break;
1907
1908 case 'O':
1909 if (opP->mode != DREG
1910 && opP->mode != IMMED
1911 && opP->mode != ABSL)
1912 losing++;
1913 break;
1914
1915 case 'Q':
1916 if (opP->mode != IMMED)
1917 losing++;
1918 else if (opP->disp.exp.X_op != O_constant
1919 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1920 losing++;
1921 else if (! m68k_quick
1922 && (strncmp (instring, "add", 3) == 0
1923 || strncmp (instring, "sub", 3) == 0)
1924 && instring[3] != 'q')
1925 losing++;
1926 break;
1927
1928 case 'R':
1929 if (opP->mode != DREG && opP->mode != AREG)
1930 losing++;
1931 break;
1932
1933 case 'r':
1934 if (opP->mode != AINDR
1935 && (opP->mode != BASE
1936 || (opP->reg != 0
1937 && opP->reg != ZADDR0)
1938 || opP->disp.exp.X_op != O_absent
1939 || ((opP->index.reg < DATA0
1940 || opP->index.reg > DATA7)
1941 && (opP->index.reg < ADDR0
1942 || opP->index.reg > ADDR7))
1943 || opP->index.size != SIZE_UNSPEC
1944 || opP->index.scale != 1))
1945 losing++;
1946 break;
1947
1948 case 's':
1949 if (opP->mode != CONTROL
1950 || ! (opP->reg == FPI
1951 || opP->reg == FPS
1952 || opP->reg == FPC))
1953 losing++;
1954 break;
1955
1956 case 'S':
1957 if (opP->mode != CONTROL || opP->reg != SR)
1958 losing++;
1959 break;
1960
1961 case 't':
1962 if (opP->mode != IMMED)
1963 losing++;
1964 else if (opP->disp.exp.X_op != O_constant
1965 || TRUNC (opP->disp.exp.X_add_number) > 7)
1966 losing++;
1967 break;
1968
1969 case 'U':
1970 if (opP->mode != CONTROL || opP->reg != USP)
1971 losing++;
1972 break;
1973
1974 case 'x':
1975 if (opP->mode != IMMED)
1976 losing++;
1977 else if (opP->disp.exp.X_op != O_constant
1978 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1979 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1980 losing++;
1981 break;
1982
1983 case 'j':
1984 if (opP->mode != IMMED)
1985 losing++;
1986 else if (opP->disp.exp.X_op != O_constant
1987 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1988 losing++;
1989 break;
1990
1991 case 'K':
1992 if (opP->mode != IMMED)
1993 losing++;
1994 else if (opP->disp.exp.X_op != O_constant
1995 || TRUNC (opP->disp.exp.X_add_number) > 511)
1996 losing++;
1997 break;
1998
1999 /* JF these are out of order. We could put them
2000 in order if we were willing to put up with
2001 bunches of #ifdef m68851s in the code.
2002
2003 Don't forget that you need these operands
2004 to use 68030 MMU instructions. */
2005 #ifndef NO_68851
2006 /* Memory addressing mode used by pflushr. */
2007 case '|':
2008 if (opP->mode == CONTROL
2009 || opP->mode == FPREG
2010 || opP->mode == DREG
2011 || opP->mode == AREG
2012 || opP->mode == REGLST)
2013 losing++;
2014 /* We should accept immediate operands, but they
2015 supposedly have to be quad word, and we don't
2016 handle that. I would like to see what a Motorola
2017 assembler does before doing something here. */
2018 if (opP->mode == IMMED)
2019 losing++;
2020 break;
2021
2022 case 'f':
2023 if (opP->mode != CONTROL
2024 || (opP->reg != SFC && opP->reg != DFC))
2025 losing++;
2026 break;
2027
2028 case '0':
2029 if (opP->mode != CONTROL || opP->reg != TC)
2030 losing++;
2031 break;
2032
2033 case '1':
2034 if (opP->mode != CONTROL || opP->reg != AC)
2035 losing++;
2036 break;
2037
2038 case '2':
2039 if (opP->mode != CONTROL
2040 || (opP->reg != CAL
2041 && opP->reg != VAL
2042 && opP->reg != SCC))
2043 losing++;
2044 break;
2045
2046 case 'V':
2047 if (opP->mode != CONTROL
2048 || opP->reg != VAL)
2049 losing++;
2050 break;
2051
2052 case 'W':
2053 if (opP->mode != CONTROL
2054 || (opP->reg != DRP
2055 && opP->reg != SRP
2056 && opP->reg != CRP))
2057 losing++;
2058 break;
2059
2060 case 'w':
2061 switch (opP->mode)
2062 {
2063 case IMMED:
2064 case ABSL:
2065 case AREG:
2066 case DREG:
2067 case FPREG:
2068 case CONTROL:
2069 case POST:
2070 case PRE:
2071 case REGLST:
2072 losing++;
2073 break;
2074 default:
2075 break;
2076 }
2077 break;
2078
2079 case 'X':
2080 if (opP->mode != CONTROL
2081 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2082 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2083 losing++;
2084 break;
2085
2086 case 'Y':
2087 if (opP->mode != CONTROL || opP->reg != PSR)
2088 losing++;
2089 break;
2090
2091 case 'Z':
2092 if (opP->mode != CONTROL || opP->reg != PCSR)
2093 losing++;
2094 break;
2095 #endif
2096 case 'c':
2097 if (opP->mode != CONTROL
2098 || (opP->reg != NC
2099 && opP->reg != IC
2100 && opP->reg != DC
2101 && opP->reg != BC))
2102 losing++;
2103 break;
2104
2105 case '_':
2106 if (opP->mode != ABSL)
2107 ++losing;
2108 break;
2109
2110 case 'u':
2111 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2112 losing++;
2113 /* FIXME: kludge instead of fixing parser:
2114 upper/lower registers are *not* CONTROL
2115 registers, but ordinary ones. */
2116 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2117 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2118 opP->mode = DREG;
2119 else
2120 opP->mode = AREG;
2121 break;
2122
2123 case 'y':
2124 if (!(opP->mode == AINDR
2125 || (opP->mode == DISP
2126 && !(opP->reg == PC || opP->reg == ZPC))))
2127 losing++;
2128 break;
2129
2130 case 'z':
2131 if (!(opP->mode == AINDR || opP->mode == DISP))
2132 losing++;
2133 break;
2134
2135 default:
2136 abort ();
2137 }
2138
2139 if (losing)
2140 break;
2141 }
2142
2143 /* Since we have found the correct instruction, copy
2144 in the modifications that we may have made. */
2145 if (!losing)
2146 for (i = 0; i < opsfound; i++)
2147 the_ins.operands[i] = operands_backup[i];
2148 }
2149
2150 if (!losing)
2151 break;
2152
2153 opcode = opcode->m_next;
2154
2155 if (!opcode)
2156 {
2157 if (ok_arch
2158 && !(ok_arch & current_architecture))
2159 {
2160 const struct m68k_cpu *cpu;
2161 int any = 0;
2162 size_t space = 400;
2163 char *buf = xmalloc (space + 1);
2164 size_t len;
2165 int paren = 1;
2166
2167 the_ins.error = buf;
2168 /* Make sure there's a NUL at the end of the buffer -- strncpy
2169 won't write one when it runs out of buffer */
2170 buf[space] = 0;
2171 #define APPEND(STRING) \
2172 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2173
2174 APPEND (_("invalid instruction for this architecture; needs "));
2175 switch (ok_arch)
2176 {
2177 case mcfisa_a:
2178 APPEND (_("ColdFire ISA_A"));
2179 break;
2180 case mcfhwdiv:
2181 APPEND (_("ColdFire hardware divide"));
2182 break;
2183 case mcfisa_aa:
2184 APPEND (_("ColdFire ISA_A+"));
2185 break;
2186 case mcfisa_b:
2187 APPEND (_("ColdFire ISA_B"));
2188 break;
2189 case cfloat:
2190 APPEND (_("ColdFire fpu"));
2191 break;
2192 case mfloat:
2193 APPEND (_("M68K fpu"));
2194 break;
2195 case mmmu:
2196 APPEND (_("M68K mmu"));
2197 break;
2198 case m68020up:
2199 APPEND (_("68020 or higher"));
2200 break;
2201 case m68000up:
2202 APPEND (_("68000 or higher"));
2203 break;
2204 case m68010up:
2205 APPEND (_("68010 or higher"));
2206 break;
2207 default:
2208 paren = 0;
2209 }
2210 if (paren)
2211 APPEND (" (");
2212
2213 for (cpu = m68k_cpus; cpu->name; cpu++)
2214 if (!cpu->alias && (cpu->arch & ok_arch))
2215 {
2216 const struct m68k_cpu *alias;
2217 int seen_master = 0;
2218
2219 if (any)
2220 APPEND (", ");
2221 any = 0;
2222 APPEND (cpu->name);
2223 for (alias = cpu; alias != m68k_cpus; alias--)
2224 if (alias[-1].alias >= 0)
2225 break;
2226 for (; !seen_master || alias->alias > 0; alias++)
2227 {
2228 if (!alias->alias)
2229 seen_master = 1;
2230 else
2231 {
2232 if (any)
2233 APPEND (", ");
2234 else
2235 APPEND (" [");
2236 APPEND (alias->name);
2237 any = 1;
2238 }
2239 }
2240 if (any)
2241 APPEND ("]");
2242 any = 1;
2243 }
2244 if (paren)
2245 APPEND (")");
2246 #undef APPEND
2247 if (!space)
2248 {
2249 /* we ran out of space, so replace the end of the list
2250 with ellipsis. */
2251 buf -= 4;
2252 while (*buf != ' ')
2253 buf--;
2254 strcpy (buf, " ...");
2255 }
2256 }
2257 else
2258 the_ins.error = _("operands mismatch");
2259 return;
2260 }
2261
2262 losing = 0;
2263 }
2264
2265 /* Now assemble it. */
2266 the_ins.args = opcode->m_operands;
2267 the_ins.numargs = opcode->m_opnum;
2268 the_ins.numo = opcode->m_codenum;
2269 the_ins.opcode[0] = getone (opcode);
2270 the_ins.opcode[1] = gettwo (opcode);
2271
2272 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2273 {
2274 int have_disp = 0;
2275
2276 /* This switch is a doozy.
2277 Watch the first step; its a big one! */
2278 switch (s[0])
2279 {
2280
2281 case '*':
2282 case '~':
2283 case '%':
2284 case ';':
2285 case '@':
2286 case '!':
2287 case '&':
2288 case '$':
2289 case '?':
2290 case '/':
2291 case '<':
2292 case '>':
2293 case 'b':
2294 case 'm':
2295 case 'n':
2296 case 'o':
2297 case 'p':
2298 case 'q':
2299 case 'v':
2300 case 'w':
2301 case 'y':
2302 case 'z':
2303 case '4':
2304 #ifndef NO_68851
2305 case '|':
2306 #endif
2307 switch (opP->mode)
2308 {
2309 case IMMED:
2310 tmpreg = 0x3c; /* 7.4 */
2311 if (strchr ("bwl", s[1]))
2312 nextword = get_num (&opP->disp, 90);
2313 else
2314 nextword = get_num (&opP->disp, 0);
2315 if (isvar (&opP->disp))
2316 add_fix (s[1], &opP->disp, 0, 0);
2317 switch (s[1])
2318 {
2319 case 'b':
2320 if (!isbyte (nextword))
2321 opP->error = _("operand out of range");
2322 addword (nextword);
2323 baseo = 0;
2324 break;
2325 case 'w':
2326 if (!isword (nextword))
2327 opP->error = _("operand out of range");
2328 addword (nextword);
2329 baseo = 0;
2330 break;
2331 case 'W':
2332 if (!issword (nextword))
2333 opP->error = _("operand out of range");
2334 addword (nextword);
2335 baseo = 0;
2336 break;
2337 case 'l':
2338 addword (nextword >> 16);
2339 addword (nextword);
2340 baseo = 0;
2341 break;
2342
2343 case 'f':
2344 baseo = 2;
2345 outro = 8;
2346 break;
2347 case 'F':
2348 baseo = 4;
2349 outro = 11;
2350 break;
2351 case 'x':
2352 baseo = 6;
2353 outro = 15;
2354 break;
2355 case 'p':
2356 baseo = 6;
2357 outro = -1;
2358 break;
2359 default:
2360 abort ();
2361 }
2362 if (!baseo)
2363 break;
2364
2365 /* We gotta put out some float. */
2366 if (op (&opP->disp) != O_big)
2367 {
2368 valueT val;
2369 int gencnt;
2370
2371 /* Can other cases happen here? */
2372 if (op (&opP->disp) != O_constant)
2373 abort ();
2374
2375 val = (valueT) offs (&opP->disp);
2376 gencnt = 0;
2377 do
2378 {
2379 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2380 val >>= LITTLENUM_NUMBER_OF_BITS;
2381 ++gencnt;
2382 }
2383 while (val != 0);
2384 offs (&opP->disp) = gencnt;
2385 }
2386 if (offs (&opP->disp) > 0)
2387 {
2388 if (offs (&opP->disp) > baseo)
2389 {
2390 as_warn (_("Bignum too big for %c format; truncated"),
2391 s[1]);
2392 offs (&opP->disp) = baseo;
2393 }
2394 baseo -= offs (&opP->disp);
2395 while (baseo--)
2396 addword (0);
2397 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2398 offs (&opP->disp)--;
2399 --wordp)
2400 addword (*wordp);
2401 break;
2402 }
2403 gen_to_words (words, baseo, (long) outro);
2404 for (wordp = words; baseo--; wordp++)
2405 addword (*wordp);
2406 break;
2407 case DREG:
2408 tmpreg = opP->reg - DATA; /* 0.dreg */
2409 break;
2410 case AREG:
2411 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2412 break;
2413 case AINDR:
2414 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2415 break;
2416 case ADEC:
2417 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2418 break;
2419 case AINC:
2420 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2421 break;
2422 case DISP:
2423
2424 nextword = get_num (&opP->disp, 90);
2425
2426 /* Convert mode 5 addressing with a zero offset into
2427 mode 2 addressing to reduce the instruction size by a
2428 word. */
2429 if (! isvar (&opP->disp)
2430 && (nextword == 0)
2431 && (opP->disp.size == SIZE_UNSPEC)
2432 && (opP->reg >= ADDR0)
2433 && (opP->reg <= ADDR7))
2434 {
2435 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2436 break;
2437 }
2438
2439 if (opP->reg == PC
2440 && ! isvar (&opP->disp)
2441 && m68k_abspcadd)
2442 {
2443 opP->disp.exp.X_op = O_symbol;
2444 opP->disp.exp.X_add_symbol =
2445 section_symbol (absolute_section);
2446 }
2447
2448 /* Force into index mode. Hope this works. */
2449
2450 /* We do the first bit for 32-bit displacements, and the
2451 second bit for 16 bit ones. It is possible that we
2452 should make the default be WORD instead of LONG, but
2453 I think that'd break GCC, so we put up with a little
2454 inefficiency for the sake of working output. */
2455
2456 if (!issword (nextword)
2457 || (isvar (&opP->disp)
2458 && ((opP->disp.size == SIZE_UNSPEC
2459 && flag_short_refs == 0
2460 && cpu_of_arch (current_architecture) >= m68020
2461 && ! arch_coldfire_p (current_architecture))
2462 || opP->disp.size == SIZE_LONG)))
2463 {
2464 if (cpu_of_arch (current_architecture) < m68020
2465 || arch_coldfire_p (current_architecture))
2466 opP->error =
2467 _("displacement too large for this architecture; needs 68020 or higher");
2468 if (opP->reg == PC)
2469 tmpreg = 0x3B; /* 7.3 */
2470 else
2471 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2472 if (isvar (&opP->disp))
2473 {
2474 if (opP->reg == PC)
2475 {
2476 if (opP->disp.size == SIZE_LONG
2477 #ifdef OBJ_ELF
2478 /* If the displacement needs pic
2479 relocation it cannot be relaxed. */
2480 || opP->disp.pic_reloc != pic_none
2481 #endif
2482 )
2483 {
2484 addword (0x0170);
2485 add_fix ('l', &opP->disp, 1, 2);
2486 }
2487 else
2488 {
2489 add_frag (adds (&opP->disp),
2490 SEXT (offs (&opP->disp)),
2491 TAB (PCREL1632, SZ_UNDEF));
2492 break;
2493 }
2494 }
2495 else
2496 {
2497 addword (0x0170);
2498 add_fix ('l', &opP->disp, 0, 0);
2499 }
2500 }
2501 else
2502 addword (0x0170);
2503 addword (nextword >> 16);
2504 }
2505 else
2506 {
2507 if (opP->reg == PC)
2508 tmpreg = 0x3A; /* 7.2 */
2509 else
2510 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2511
2512 if (isvar (&opP->disp))
2513 {
2514 if (opP->reg == PC)
2515 {
2516 add_fix ('w', &opP->disp, 1, 0);
2517 }
2518 else
2519 add_fix ('w', &opP->disp, 0, 0);
2520 }
2521 }
2522 addword (nextword);
2523 break;
2524
2525 case POST:
2526 case PRE:
2527 case BASE:
2528 nextword = 0;
2529 baseo = get_num (&opP->disp, 90);
2530 if (opP->mode == POST || opP->mode == PRE)
2531 outro = get_num (&opP->odisp, 90);
2532 /* Figure out the `addressing mode'.
2533 Also turn on the BASE_DISABLE bit, if needed. */
2534 if (opP->reg == PC || opP->reg == ZPC)
2535 {
2536 tmpreg = 0x3b; /* 7.3 */
2537 if (opP->reg == ZPC)
2538 nextword |= 0x80;
2539 }
2540 else if (opP->reg == 0)
2541 {
2542 nextword |= 0x80;
2543 tmpreg = 0x30; /* 6.garbage */
2544 }
2545 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2546 {
2547 nextword |= 0x80;
2548 tmpreg = 0x30 + opP->reg - ZADDR0;
2549 }
2550 else
2551 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2552
2553 siz1 = opP->disp.size;
2554 if (opP->mode == POST || opP->mode == PRE)
2555 siz2 = opP->odisp.size;
2556 else
2557 siz2 = SIZE_UNSPEC;
2558
2559 /* Index register stuff. */
2560 if (opP->index.reg != 0
2561 && opP->index.reg >= DATA
2562 && opP->index.reg <= ADDR7)
2563 {
2564 nextword |= (opP->index.reg - DATA) << 12;
2565
2566 if (opP->index.size == SIZE_LONG
2567 || (opP->index.size == SIZE_UNSPEC
2568 && m68k_index_width_default == SIZE_LONG))
2569 nextword |= 0x800;
2570
2571 if ((opP->index.scale != 1
2572 && cpu_of_arch (current_architecture) < m68020)
2573 || (opP->index.scale == 8
2574 && (arch_coldfire_p (current_architecture)
2575 && !arch_coldfire_fpu (current_architecture))))
2576 {
2577 opP->error =
2578 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2579 }
2580
2581 if (arch_coldfire_p (current_architecture)
2582 && opP->index.size == SIZE_WORD)
2583 opP->error = _("invalid index size for coldfire");
2584
2585 switch (opP->index.scale)
2586 {
2587 case 1:
2588 break;
2589 case 2:
2590 nextword |= 0x200;
2591 break;
2592 case 4:
2593 nextword |= 0x400;
2594 break;
2595 case 8:
2596 nextword |= 0x600;
2597 break;
2598 default:
2599 abort ();
2600 }
2601 /* IF its simple,
2602 GET US OUT OF HERE! */
2603
2604 /* Must be INDEX, with an index register. Address
2605 register cannot be ZERO-PC, and either :b was
2606 forced, or we know it will fit. For a 68000 or
2607 68010, force this mode anyways, because the
2608 larger modes aren't supported. */
2609 if (opP->mode == BASE
2610 && ((opP->reg >= ADDR0
2611 && opP->reg <= ADDR7)
2612 || opP->reg == PC))
2613 {
2614 if (siz1 == SIZE_BYTE
2615 || cpu_of_arch (current_architecture) < m68020
2616 || arch_coldfire_p (current_architecture)
2617 || (siz1 == SIZE_UNSPEC
2618 && ! isvar (&opP->disp)
2619 && issbyte (baseo)))
2620 {
2621 nextword += baseo & 0xff;
2622 addword (nextword);
2623 if (isvar (&opP->disp))
2624 {
2625 /* Do a byte relocation. If it doesn't
2626 fit (possible on m68000) let the
2627 fixup processing complain later. */
2628 if (opP->reg == PC)
2629 add_fix ('B', &opP->disp, 1, 1);
2630 else
2631 add_fix ('B', &opP->disp, 0, 0);
2632 }
2633 else if (siz1 != SIZE_BYTE)
2634 {
2635 if (siz1 != SIZE_UNSPEC)
2636 as_warn (_("Forcing byte displacement"));
2637 if (! issbyte (baseo))
2638 opP->error = _("byte displacement out of range");
2639 }
2640
2641 break;
2642 }
2643 else if (siz1 == SIZE_UNSPEC
2644 && opP->reg == PC
2645 && isvar (&opP->disp)
2646 && subs (&opP->disp) == NULL
2647 #ifdef OBJ_ELF
2648 /* If the displacement needs pic
2649 relocation it cannot be relaxed. */
2650 && opP->disp.pic_reloc == pic_none
2651 #endif
2652 )
2653 {
2654 /* The code in md_convert_frag_1 needs to be
2655 able to adjust nextword. Call frag_grow
2656 to ensure that we have enough space in
2657 the frag obstack to make all the bytes
2658 contiguous. */
2659 frag_grow (14);
2660 nextword += baseo & 0xff;
2661 addword (nextword);
2662 add_frag (adds (&opP->disp),
2663 SEXT (offs (&opP->disp)),
2664 TAB (PCINDEX, SZ_UNDEF));
2665
2666 break;
2667 }
2668 }
2669 }
2670 else
2671 {
2672 nextword |= 0x40; /* No index reg. */
2673 if (opP->index.reg >= ZDATA0
2674 && opP->index.reg <= ZDATA7)
2675 nextword |= (opP->index.reg - ZDATA0) << 12;
2676 else if (opP->index.reg >= ZADDR0
2677 || opP->index.reg <= ZADDR7)
2678 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2679 }
2680
2681 /* It isn't simple. */
2682
2683 if (cpu_of_arch (current_architecture) < m68020
2684 || arch_coldfire_p (current_architecture))
2685 opP->error =
2686 _("invalid operand mode for this architecture; needs 68020 or higher");
2687
2688 nextword |= 0x100;
2689 /* If the guy specified a width, we assume that it is
2690 wide enough. Maybe it isn't. If so, we lose. */
2691 switch (siz1)
2692 {
2693 case SIZE_UNSPEC:
2694 if (isvar (&opP->disp)
2695 ? m68k_rel32
2696 : ! issword (baseo))
2697 {
2698 siz1 = SIZE_LONG;
2699 nextword |= 0x30;
2700 }
2701 else if (! isvar (&opP->disp) && baseo == 0)
2702 nextword |= 0x10;
2703 else
2704 {
2705 nextword |= 0x20;
2706 siz1 = SIZE_WORD;
2707 }
2708 break;
2709 case SIZE_BYTE:
2710 as_warn (_(":b not permitted; defaulting to :w"));
2711 /* Fall through. */
2712 case SIZE_WORD:
2713 nextword |= 0x20;
2714 break;
2715 case SIZE_LONG:
2716 nextword |= 0x30;
2717 break;
2718 }
2719
2720 /* Figure out inner displacement stuff. */
2721 if (opP->mode == POST || opP->mode == PRE)
2722 {
2723 if (cpu_of_arch (current_architecture) & cpu32)
2724 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2725 switch (siz2)
2726 {
2727 case SIZE_UNSPEC:
2728 if (isvar (&opP->odisp)
2729 ? m68k_rel32
2730 : ! issword (outro))
2731 {
2732 siz2 = SIZE_LONG;
2733 nextword |= 0x3;
2734 }
2735 else if (! isvar (&opP->odisp) && outro == 0)
2736 nextword |= 0x1;
2737 else
2738 {
2739 nextword |= 0x2;
2740 siz2 = SIZE_WORD;
2741 }
2742 break;
2743 case 1:
2744 as_warn (_(":b not permitted; defaulting to :w"));
2745 /* Fall through. */
2746 case 2:
2747 nextword |= 0x2;
2748 break;
2749 case 3:
2750 nextword |= 0x3;
2751 break;
2752 }
2753 if (opP->mode == POST
2754 && (nextword & 0x40) == 0)
2755 nextword |= 0x04;
2756 }
2757 addword (nextword);
2758
2759 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2760 {
2761 if (opP->reg == PC || opP->reg == ZPC)
2762 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2763 else
2764 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2765 }
2766 if (siz1 == SIZE_LONG)
2767 addword (baseo >> 16);
2768 if (siz1 != SIZE_UNSPEC)
2769 addword (baseo);
2770
2771 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2772 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2773 if (siz2 == SIZE_LONG)
2774 addword (outro >> 16);
2775 if (siz2 != SIZE_UNSPEC)
2776 addword (outro);
2777
2778 break;
2779
2780 case ABSL:
2781 nextword = get_num (&opP->disp, 90);
2782 switch (opP->disp.size)
2783 {
2784 default:
2785 abort ();
2786 case SIZE_UNSPEC:
2787 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2788 {
2789 tmpreg = 0x38; /* 7.0 */
2790 addword (nextword);
2791 break;
2792 }
2793 if (isvar (&opP->disp)
2794 && !subs (&opP->disp)
2795 && adds (&opP->disp)
2796 #ifdef OBJ_ELF
2797 /* If the displacement needs pic relocation it
2798 cannot be relaxed. */
2799 && opP->disp.pic_reloc == pic_none
2800 #endif
2801 && !flag_long_jumps
2802 && !strchr ("~%&$?", s[0]))
2803 {
2804 tmpreg = 0x3A; /* 7.2 */
2805 add_frag (adds (&opP->disp),
2806 SEXT (offs (&opP->disp)),
2807 TAB (ABSTOPCREL, SZ_UNDEF));
2808 break;
2809 }
2810 /* Fall through into long. */
2811 case SIZE_LONG:
2812 if (isvar (&opP->disp))
2813 add_fix ('l', &opP->disp, 0, 0);
2814
2815 tmpreg = 0x39;/* 7.1 mode */
2816 addword (nextword >> 16);
2817 addword (nextword);
2818 break;
2819
2820 case SIZE_BYTE:
2821 as_bad (_("unsupported byte value; use a different suffix"));
2822 /* Fall through. */
2823
2824 case SIZE_WORD:
2825 if (isvar (&opP->disp))
2826 add_fix ('w', &opP->disp, 0, 0);
2827
2828 tmpreg = 0x38;/* 7.0 mode */
2829 addword (nextword);
2830 break;
2831 }
2832 break;
2833 case CONTROL:
2834 case FPREG:
2835 default:
2836 as_bad (_("unknown/incorrect operand"));
2837 /* abort (); */
2838 }
2839
2840 /* If s[0] is '4', then this is for the mac instructions
2841 that can have a trailing_ampersand set. If so, set 0x100
2842 bit on tmpreg so install_gen_operand can check for it and
2843 set the appropriate bit (word2, bit 5). */
2844 if (s[0] == '4')
2845 {
2846 if (opP->trailing_ampersand)
2847 tmpreg |= 0x100;
2848 }
2849 install_gen_operand (s[1], tmpreg);
2850 break;
2851
2852 case '#':
2853 case '^':
2854 switch (s[1])
2855 { /* JF: I hate floating point! */
2856 case 'j':
2857 tmpreg = 70;
2858 break;
2859 case '8':
2860 tmpreg = 20;
2861 break;
2862 case 'C':
2863 tmpreg = 50;
2864 break;
2865 case '3':
2866 default:
2867 tmpreg = 90;
2868 break;
2869 }
2870 tmpreg = get_num (&opP->disp, tmpreg);
2871 if (isvar (&opP->disp))
2872 add_fix (s[1], &opP->disp, 0, 0);
2873 switch (s[1])
2874 {
2875 case 'b': /* Danger: These do no check for
2876 certain types of overflow.
2877 user beware! */
2878 if (!isbyte (tmpreg))
2879 opP->error = _("out of range");
2880 insop (tmpreg, opcode);
2881 if (isvar (&opP->disp))
2882 the_ins.reloc[the_ins.nrel - 1].n =
2883 (opcode->m_codenum) * 2 + 1;
2884 break;
2885 case 'B':
2886 if (!issbyte (tmpreg))
2887 opP->error = _("out of range");
2888 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2889 if (isvar (&opP->disp))
2890 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2891 break;
2892 case 'w':
2893 if (!isword (tmpreg))
2894 opP->error = _("out of range");
2895 insop (tmpreg, opcode);
2896 if (isvar (&opP->disp))
2897 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2898 break;
2899 case 'W':
2900 if (!issword (tmpreg))
2901 opP->error = _("out of range");
2902 insop (tmpreg, opcode);
2903 if (isvar (&opP->disp))
2904 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2905 break;
2906 case 'l':
2907 /* Because of the way insop works, we put these two out
2908 backwards. */
2909 insop (tmpreg, opcode);
2910 insop (tmpreg >> 16, opcode);
2911 if (isvar (&opP->disp))
2912 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2913 break;
2914 case '3':
2915 tmpreg &= 0xFF;
2916 case '8':
2917 case 'C':
2918 case 'j':
2919 install_operand (s[1], tmpreg);
2920 break;
2921 default:
2922 abort ();
2923 }
2924 break;
2925
2926 case '+':
2927 case '-':
2928 case 'A':
2929 case 'a':
2930 install_operand (s[1], opP->reg - ADDR);
2931 break;
2932
2933 case 'B':
2934 tmpreg = get_num (&opP->disp, 90);
2935
2936 switch (s[1])
2937 {
2938 case 'B':
2939 add_fix ('B', &opP->disp, 1, -1);
2940 break;
2941 case 'W':
2942 add_fix ('w', &opP->disp, 1, 0);
2943 addword (0);
2944 break;
2945 case 'L':
2946 long_branch:
2947 the_ins.opcode[0] |= 0xff;
2948 add_fix ('l', &opP->disp, 1, 0);
2949 addword (0);
2950 addword (0);
2951 break;
2952 case 'g': /* Conditional branch */
2953 have_disp = HAVE_LONG_CALL (current_architecture);
2954 goto var_branch;
2955
2956 case 'b': /* Unconditional branch */
2957 have_disp = HAVE_LONG_BRANCH (current_architecture);
2958 goto var_branch;
2959
2960 case 's': /* Unconditional subroutine */
2961 have_disp = HAVE_LONG_CALL (current_architecture);
2962
2963 var_branch:
2964 if (subs (&opP->disp) /* We can't relax it. */
2965 #ifdef OBJ_ELF
2966 /* If the displacement needs pic relocation it cannot be
2967 relaxed. */
2968 || opP->disp.pic_reloc != pic_none
2969 #endif
2970 || 0)
2971 {
2972 if (!have_disp)
2973 as_warn (_("Can't use long branches on this architecture"));
2974 goto long_branch;
2975 }
2976
2977 /* This could either be a symbol, or an absolute
2978 address. If it's an absolute address, turn it into
2979 an absolute jump right here and keep it out of the
2980 relaxer. */
2981 if (adds (&opP->disp) == 0)
2982 {
2983 if (the_ins.opcode[0] == 0x6000) /* jbra */
2984 the_ins.opcode[0] = 0x4EF9;
2985 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2986 the_ins.opcode[0] = 0x4EB9;
2987 else /* jCC */
2988 {
2989 the_ins.opcode[0] ^= 0x0100;
2990 the_ins.opcode[0] |= 0x0006;
2991 addword (0x4EF9);
2992 }
2993 add_fix ('l', &opP->disp, 0, 0);
2994 addword (0);
2995 addword (0);
2996 break;
2997 }
2998
2999 /* Now we know it's going into the relaxer. Now figure
3000 out which mode. We try in this order of preference:
3001 long branch, absolute jump, byte/word branches only. */
3002 if (have_disp)
3003 add_frag (adds (&opP->disp),
3004 SEXT (offs (&opP->disp)),
3005 TAB (BRANCHBWL, SZ_UNDEF));
3006 else if (! flag_keep_pcrel)
3007 {
3008 if ((the_ins.opcode[0] == 0x6000)
3009 || (the_ins.opcode[0] == 0x6100))
3010 add_frag (adds (&opP->disp),
3011 SEXT (offs (&opP->disp)),
3012 TAB (BRABSJUNC, SZ_UNDEF));
3013 else
3014 add_frag (adds (&opP->disp),
3015 SEXT (offs (&opP->disp)),
3016 TAB (BRABSJCOND, SZ_UNDEF));
3017 }
3018 else
3019 add_frag (adds (&opP->disp),
3020 SEXT (offs (&opP->disp)),
3021 TAB (BRANCHBW, SZ_UNDEF));
3022 break;
3023 case 'w':
3024 if (isvar (&opP->disp))
3025 {
3026 /* Check for DBcc instructions. We can relax them,
3027 but only if we have long branches and/or absolute
3028 jumps. */
3029 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3030 && (HAVE_LONG_BRANCH (current_architecture)
3031 || ! flag_keep_pcrel))
3032 {
3033 if (HAVE_LONG_BRANCH (current_architecture))
3034 add_frag (adds (&opP->disp),
3035 SEXT (offs (&opP->disp)),
3036 TAB (DBCCLBR, SZ_UNDEF));
3037 else
3038 add_frag (adds (&opP->disp),
3039 SEXT (offs (&opP->disp)),
3040 TAB (DBCCABSJ, SZ_UNDEF));
3041 break;
3042 }
3043 add_fix ('w', &opP->disp, 1, 0);
3044 }
3045 addword (0);
3046 break;
3047 case 'C': /* Fixed size LONG coproc branches. */
3048 add_fix ('l', &opP->disp, 1, 0);
3049 addword (0);
3050 addword (0);
3051 break;
3052 case 'c': /* Var size Coprocesssor branches. */
3053 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3054 {
3055 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3056 add_fix ('l', &opP->disp, 1, 0);
3057 addword (0);
3058 addword (0);
3059 }
3060 else
3061 add_frag (adds (&opP->disp),
3062 SEXT (offs (&opP->disp)),
3063 TAB (FBRANCH, SZ_UNDEF));
3064 break;
3065 default:
3066 abort ();
3067 }
3068 break;
3069
3070 case 'C': /* Ignore it. */
3071 break;
3072
3073 case 'd': /* JF this is a kludge. */
3074 install_operand ('s', opP->reg - ADDR);
3075 tmpreg = get_num (&opP->disp, 90);
3076 if (!issword (tmpreg))
3077 {
3078 as_warn (_("Expression out of range, using 0"));
3079 tmpreg = 0;
3080 }
3081 addword (tmpreg);
3082 break;
3083
3084 case 'D':
3085 install_operand (s[1], opP->reg - DATA);
3086 break;
3087
3088 case 'e': /* EMAC ACCx, reg/reg. */
3089 install_operand (s[1], opP->reg - ACC);
3090 break;
3091
3092 case 'E': /* Ignore it. */
3093 break;
3094
3095 case 'F':
3096 install_operand (s[1], opP->reg - FP0);
3097 break;
3098
3099 case 'g': /* EMAC ACCEXTx. */
3100 install_operand (s[1], opP->reg - ACCEXT01);
3101 break;
3102
3103 case 'G': /* Ignore it. */
3104 case 'H':
3105 break;
3106
3107 case 'I':
3108 tmpreg = opP->reg - COP0;
3109 install_operand (s[1], tmpreg);
3110 break;
3111
3112 case 'i': /* MAC/EMAC scale factor. */
3113 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3114 break;
3115
3116 case 'J': /* JF foo. */
3117 switch (opP->reg)
3118 {
3119 case SFC:
3120 tmpreg = 0x000;
3121 break;
3122 case DFC:
3123 tmpreg = 0x001;
3124 break;
3125 case CACR:
3126 tmpreg = 0x002;
3127 break;
3128 case TC:
3129 case ASID:
3130 tmpreg = 0x003;
3131 break;
3132 case ACR0:
3133 case ITT0:
3134 tmpreg = 0x004;
3135 break;
3136 case ACR1:
3137 case ITT1:
3138 tmpreg = 0x005;
3139 break;
3140 case ACR2:
3141 case DTT0:
3142 tmpreg = 0x006;
3143 break;
3144 case ACR3:
3145 case DTT1:
3146 tmpreg = 0x007;
3147 break;
3148 case BUSCR:
3149 case MMUBAR:
3150 tmpreg = 0x008;
3151 break;
3152
3153 case USP:
3154 tmpreg = 0x800;
3155 break;
3156 case VBR:
3157 tmpreg = 0x801;
3158 break;
3159 case CAAR:
3160 tmpreg = 0x802;
3161 break;
3162 case MSP:
3163 tmpreg = 0x803;
3164 break;
3165 case ISP:
3166 tmpreg = 0x804;
3167 break;
3168 case MMUSR:
3169 tmpreg = 0x805;
3170 break;
3171 case URP:
3172 tmpreg = 0x806;
3173 break;
3174 case SRP:
3175 tmpreg = 0x807;
3176 break;
3177 case PCR:
3178 tmpreg = 0x808;
3179 break;
3180 case ROMBAR:
3181 case ROMBAR0:
3182 tmpreg = 0xC00;
3183 break;
3184 case ROMBAR1:
3185 tmpreg = 0xC01;
3186 break;
3187 case FLASHBAR:
3188 case RAMBAR0:
3189 case RAMBAR_ALT:
3190 tmpreg = 0xC04;
3191 break;
3192 case RAMBAR:
3193 case RAMBAR1:
3194 tmpreg = 0xC05;
3195 break;
3196 case MPCR:
3197 tmpreg = 0xC0C;
3198 break;
3199 case EDRAMBAR:
3200 tmpreg = 0xC0D;
3201 break;
3202 case MBAR0:
3203 case MBAR2:
3204 case SECMBAR:
3205 tmpreg = 0xC0E;
3206 break;
3207 case MBAR1:
3208 case MBAR:
3209 tmpreg = 0xC0F;
3210 break;
3211 case PCR1U0:
3212 tmpreg = 0xD02;
3213 break;
3214 case PCR1L0:
3215 tmpreg = 0xD03;
3216 break;
3217 case PCR2U0:
3218 tmpreg = 0xD04;
3219 break;
3220 case PCR2L0:
3221 tmpreg = 0xD05;
3222 break;
3223 case PCR3U0:
3224 tmpreg = 0xD06;
3225 break;
3226 case PCR3L0:
3227 tmpreg = 0xD07;
3228 break;
3229 case PCR1L1:
3230 tmpreg = 0xD0A;
3231 break;
3232 case PCR1U1:
3233 tmpreg = 0xD0B;
3234 break;
3235 case PCR2L1:
3236 tmpreg = 0xD0C;
3237 break;
3238 case PCR2U1:
3239 tmpreg = 0xD0D;
3240 break;
3241 case PCR3L1:
3242 tmpreg = 0xD0E;
3243 break;
3244 case PCR3U1:
3245 tmpreg = 0xD0F;
3246 break;
3247 case CAC:
3248 tmpreg = 0xFFE;
3249 break;
3250 case MBB:
3251 tmpreg = 0xFFF;
3252 break;
3253 default:
3254 abort ();
3255 }
3256 install_operand (s[1], tmpreg);
3257 break;
3258
3259 case 'k':
3260 tmpreg = get_num (&opP->disp, 55);
3261 install_operand (s[1], tmpreg & 0x7f);
3262 break;
3263
3264 case 'l':
3265 tmpreg = opP->mask;
3266 if (s[1] == 'w')
3267 {
3268 if (tmpreg & 0x7FF0000)
3269 as_bad (_("Floating point register in register list"));
3270 insop (reverse_16_bits (tmpreg), opcode);
3271 }
3272 else
3273 {
3274 if (tmpreg & 0x700FFFF)
3275 as_bad (_("Wrong register in floating-point reglist"));
3276 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3277 }
3278 break;
3279
3280 case 'L':
3281 tmpreg = opP->mask;
3282 if (s[1] == 'w')
3283 {
3284 if (tmpreg & 0x7FF0000)
3285 as_bad (_("Floating point register in register list"));
3286 insop (tmpreg, opcode);
3287 }
3288 else if (s[1] == '8')
3289 {
3290 if (tmpreg & 0x0FFFFFF)
3291 as_bad (_("incorrect register in reglist"));
3292 install_operand (s[1], tmpreg >> 24);
3293 }
3294 else
3295 {
3296 if (tmpreg & 0x700FFFF)
3297 as_bad (_("wrong register in floating-point reglist"));
3298 else
3299 install_operand (s[1], tmpreg >> 16);
3300 }
3301 break;
3302
3303 case 'M':
3304 install_operand (s[1], get_num (&opP->disp, 60));
3305 break;
3306
3307 case 'O':
3308 tmpreg = ((opP->mode == DREG)
3309 ? 0x20 + (int) (opP->reg - DATA)
3310 : (get_num (&opP->disp, 40) & 0x1F));
3311 install_operand (s[1], tmpreg);
3312 break;
3313
3314 case 'Q':
3315 tmpreg = get_num (&opP->disp, 10);
3316 if (tmpreg == 8)
3317 tmpreg = 0;
3318 install_operand (s[1], tmpreg);
3319 break;
3320
3321 case 'R':
3322 /* This depends on the fact that ADDR registers are eight
3323 more than their corresponding DATA regs, so the result
3324 will have the ADDR_REG bit set. */
3325 install_operand (s[1], opP->reg - DATA);
3326 break;
3327
3328 case 'r':
3329 if (opP->mode == AINDR)
3330 install_operand (s[1], opP->reg - DATA);
3331 else
3332 install_operand (s[1], opP->index.reg - DATA);
3333 break;
3334
3335 case 's':
3336 if (opP->reg == FPI)
3337 tmpreg = 0x1;
3338 else if (opP->reg == FPS)
3339 tmpreg = 0x2;
3340 else if (opP->reg == FPC)
3341 tmpreg = 0x4;
3342 else
3343 abort ();
3344 install_operand (s[1], tmpreg);
3345 break;
3346
3347 case 'S': /* Ignore it. */
3348 break;
3349
3350 case 'T':
3351 install_operand (s[1], get_num (&opP->disp, 30));
3352 break;
3353
3354 case 'U': /* Ignore it. */
3355 break;
3356
3357 case 'c':
3358 switch (opP->reg)
3359 {
3360 case NC:
3361 tmpreg = 0;
3362 break;
3363 case DC:
3364 tmpreg = 1;
3365 break;
3366 case IC:
3367 tmpreg = 2;
3368 break;
3369 case BC:
3370 tmpreg = 3;
3371 break;
3372 default:
3373 as_fatal (_("failed sanity check"));
3374 } /* switch on cache token. */
3375 install_operand (s[1], tmpreg);
3376 break;
3377 #ifndef NO_68851
3378 /* JF: These are out of order, I fear. */
3379 case 'f':
3380 switch (opP->reg)
3381 {
3382 case SFC:
3383 tmpreg = 0;
3384 break;
3385 case DFC:
3386 tmpreg = 1;
3387 break;
3388 default:
3389 abort ();
3390 }
3391 install_operand (s[1], tmpreg);
3392 break;
3393
3394 case '0':
3395 case '1':
3396 case '2':
3397 switch (opP->reg)
3398 {
3399 case TC:
3400 tmpreg = 0;
3401 break;
3402 case CAL:
3403 tmpreg = 4;
3404 break;
3405 case VAL:
3406 tmpreg = 5;
3407 break;
3408 case SCC:
3409 tmpreg = 6;
3410 break;
3411 case AC:
3412 tmpreg = 7;
3413 break;
3414 default:
3415 abort ();
3416 }
3417 install_operand (s[1], tmpreg);
3418 break;
3419
3420 case 'V':
3421 if (opP->reg == VAL)
3422 break;
3423 abort ();
3424
3425 case 'W':
3426 switch (opP->reg)
3427 {
3428 case DRP:
3429 tmpreg = 1;
3430 break;
3431 case SRP:
3432 tmpreg = 2;
3433 break;
3434 case CRP:
3435 tmpreg = 3;
3436 break;
3437 default:
3438 abort ();
3439 }
3440 install_operand (s[1], tmpreg);
3441 break;
3442
3443 case 'X':
3444 switch (opP->reg)
3445 {
3446 case BAD:
3447 case BAD + 1:
3448 case BAD + 2:
3449 case BAD + 3:
3450 case BAD + 4:
3451 case BAD + 5:
3452 case BAD + 6:
3453 case BAD + 7:
3454 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3455 break;
3456
3457 case BAC:
3458 case BAC + 1:
3459 case BAC + 2:
3460 case BAC + 3:
3461 case BAC + 4:
3462 case BAC + 5:
3463 case BAC + 6:
3464 case BAC + 7:
3465 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3466 break;
3467
3468 default:
3469 abort ();
3470 }
3471 install_operand (s[1], tmpreg);
3472 break;
3473 case 'Y':
3474 know (opP->reg == PSR);
3475 break;
3476 case 'Z':
3477 know (opP->reg == PCSR);
3478 break;
3479 #endif /* m68851 */
3480 case '3':
3481 switch (opP->reg)
3482 {
3483 case TT0:
3484 tmpreg = 2;
3485 break;
3486 case TT1:
3487 tmpreg = 3;
3488 break;
3489 default:
3490 abort ();
3491 }
3492 install_operand (s[1], tmpreg);
3493 break;
3494 case 't':
3495 tmpreg = get_num (&opP->disp, 20);
3496 install_operand (s[1], tmpreg);
3497 break;
3498 case '_': /* used only for move16 absolute 32-bit address. */
3499 if (isvar (&opP->disp))
3500 add_fix ('l', &opP->disp, 0, 0);
3501 tmpreg = get_num (&opP->disp, 90);
3502 addword (tmpreg >> 16);
3503 addword (tmpreg & 0xFFFF);
3504 break;
3505 case 'u':
3506 install_operand (s[1], opP->reg - DATA0L);
3507 opP->reg -= (DATA0L);
3508 opP->reg &= 0x0F; /* remove upper/lower bit. */
3509 break;
3510 case 'x':
3511 tmpreg = get_num (&opP->disp, 80);
3512 if (tmpreg == -1)
3513 tmpreg = 0;
3514 install_operand (s[1], tmpreg);
3515 break;
3516 case 'j':
3517 tmpreg = get_num (&opP->disp, 10);
3518 install_operand (s[1], tmpreg - 1);
3519 break;
3520 case 'K':
3521 tmpreg = get_num (&opP->disp, 65);
3522 install_operand (s[1], tmpreg);
3523 break;
3524 default:
3525 abort ();
3526 }
3527 }
3528
3529 /* By the time whe get here (FINALLY) the_ins contains the complete
3530 instruction, ready to be emitted. . . */
3531 }
3532
3533 static int
3534 reverse_16_bits (int in)
3535 {
3536 int out = 0;
3537 int n;
3538
3539 static int mask[16] =
3540 {
3541 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3542 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3543 };
3544 for (n = 0; n < 16; n++)
3545 {
3546 if (in & mask[n])
3547 out |= mask[15 - n];
3548 }
3549 return out;
3550 } /* reverse_16_bits() */
3551
3552 static int
3553 reverse_8_bits (int in)
3554 {
3555 int out = 0;
3556 int n;
3557
3558 static int mask[8] =
3559 {
3560 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3561 };
3562
3563 for (n = 0; n < 8; n++)
3564 {
3565 if (in & mask[n])
3566 out |= mask[7 - n];
3567 }
3568 return out;
3569 } /* reverse_8_bits() */
3570
3571 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3572 (that value is chosen in the frag_var call in md_assemble). TYPE
3573 is the subtype of the frag to be generated; its primary type is
3574 rs_machine_dependent.
3575
3576 The TYPE parameter is also used by md_convert_frag_1 and
3577 md_estimate_size_before_relax. The appropriate type of fixup will
3578 be emitted by md_convert_frag_1.
3579
3580 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3581 static void
3582 install_operand (int mode, int val)
3583 {
3584 switch (mode)
3585 {
3586 case 's':
3587 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3588 break;
3589 case 'd':
3590 the_ins.opcode[0] |= val << 9;
3591 break;
3592 case 'E':
3593 the_ins.opcode[1] |= val << 9;
3594 break;
3595 case '1':
3596 the_ins.opcode[1] |= val << 12;
3597 break;
3598 case '2':
3599 the_ins.opcode[1] |= val << 6;
3600 break;
3601 case '3':
3602 the_ins.opcode[1] |= val;
3603 break;
3604 case '4':
3605 the_ins.opcode[2] |= val << 12;
3606 break;
3607 case '5':
3608 the_ins.opcode[2] |= val << 6;
3609 break;
3610 case '6':
3611 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3612 three words long! */
3613 the_ins.numo++;
3614 the_ins.opcode[2] |= val;
3615 break;
3616 case '7':
3617 the_ins.opcode[1] |= val << 7;
3618 break;
3619 case '8':
3620 the_ins.opcode[1] |= val << 10;
3621 break;
3622 #ifndef NO_68851
3623 case '9':
3624 the_ins.opcode[1] |= val << 5;
3625 break;
3626 #endif
3627
3628 case 't':
3629 the_ins.opcode[1] |= (val << 10) | (val << 7);
3630 break;
3631 case 'D':
3632 the_ins.opcode[1] |= (val << 12) | val;
3633 break;
3634 case 'g':
3635 the_ins.opcode[0] |= val = 0xff;
3636 break;
3637 case 'i':
3638 the_ins.opcode[0] |= val << 9;
3639 break;
3640 case 'C':
3641 the_ins.opcode[1] |= val;
3642 break;
3643 case 'j':
3644 the_ins.opcode[1] |= val;
3645 the_ins.numo++; /* What a hack. */
3646 break;
3647 case 'k':
3648 the_ins.opcode[1] |= val << 4;
3649 break;
3650 case 'b':
3651 case 'w':
3652 case 'W':
3653 case 'l':
3654 break;
3655 case 'e':
3656 the_ins.opcode[0] |= (val << 6);
3657 break;
3658 case 'L':
3659 the_ins.opcode[1] = (val >> 16);
3660 the_ins.opcode[2] = val & 0xffff;
3661 break;
3662 case 'm':
3663 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3664 the_ins.opcode[0] |= ((val & 0x7) << 9);
3665 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3666 break;
3667 case 'n': /* MAC/EMAC Rx on !load. */
3668 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3669 the_ins.opcode[0] |= ((val & 0x7) << 9);
3670 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3671 break;
3672 case 'o': /* MAC/EMAC Rx on load. */
3673 the_ins.opcode[1] |= val << 12;
3674 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3675 break;
3676 case 'M': /* MAC/EMAC Ry on !load. */
3677 the_ins.opcode[0] |= (val & 0xF);
3678 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3679 break;
3680 case 'N': /* MAC/EMAC Ry on load. */
3681 the_ins.opcode[1] |= (val & 0xF);
3682 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3683 break;
3684 case 'h':
3685 the_ins.opcode[1] |= ((val != 1) << 10);
3686 break;
3687 case 'F':
3688 the_ins.opcode[0] |= ((val & 0x3) << 9);
3689 break;
3690 case 'f':
3691 the_ins.opcode[0] |= ((val & 0x3) << 0);
3692 break;
3693 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3694 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3695 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3696 break;
3697 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3698 the_ins.opcode[0] |= ((val & 0x1) << 7);
3699 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3700 break;
3701 case 'I':
3702 the_ins.opcode[1] |= ((val & 0x3) << 9);
3703 break;
3704 case ']':
3705 the_ins.opcode[0] |= (val & 0x1) <<10;
3706 break;
3707 case 'c':
3708 default:
3709 as_fatal (_("failed sanity check."));
3710 }
3711 }
3712
3713 static void
3714 install_gen_operand (int mode, int val)
3715 {
3716 switch (mode)
3717 {
3718 case '/': /* Special for mask loads for mac/msac insns with
3719 possible mask; trailing_ampersend set in bit 8. */
3720 the_ins.opcode[0] |= (val & 0x3f);
3721 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3722 break;
3723 case 's':
3724 the_ins.opcode[0] |= val;
3725 break;
3726 case 'd':
3727 /* This is a kludge!!! */
3728 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3729 break;
3730 case 'b':
3731 case 'w':
3732 case 'l':
3733 case 'f':
3734 case 'F':
3735 case 'x':
3736 case 'p':
3737 the_ins.opcode[0] |= val;
3738 break;
3739 /* more stuff goes here. */
3740 default:
3741 as_fatal (_("failed sanity check."));
3742 }
3743 }
3744
3745 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3746 then deal with the bitfield hack. */
3747
3748 static char *
3749 crack_operand (char *str, struct m68k_op *opP)
3750 {
3751 register int parens;
3752 register int c;
3753 register char *beg_str;
3754 int inquote = 0;
3755
3756 if (!str)
3757 {
3758 return str;
3759 }
3760 beg_str = str;
3761 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3762 {
3763 if (! inquote)
3764 {
3765 if (*str == '(')
3766 parens++;
3767 else if (*str == ')')
3768 {
3769 if (!parens)
3770 { /* ERROR. */
3771 opP->error = _("Extra )");
3772 return str;
3773 }
3774 --parens;
3775 }
3776 }
3777 if (flag_mri && *str == '\'')
3778 inquote = ! inquote;
3779 }
3780 if (!*str && parens)
3781 { /* ERROR. */
3782 opP->error = _("Missing )");
3783 return str;
3784 }
3785 c = *str;
3786 *str = '\0';
3787 if (m68k_ip_op (beg_str, opP) != 0)
3788 {
3789 *str = c;
3790 return str;
3791 }
3792 *str = c;
3793 if (c == '}')
3794 c = *++str; /* JF bitfield hack. */
3795 if (c)
3796 {
3797 c = *++str;
3798 if (!c)
3799 as_bad (_("Missing operand"));
3800 }
3801
3802 /* Detect MRI REG symbols and convert them to REGLSTs. */
3803 if (opP->mode == CONTROL && (int)opP->reg < 0)
3804 {
3805 opP->mode = REGLST;
3806 opP->mask = ~(int)opP->reg;
3807 opP->reg = 0;
3808 }
3809
3810 return str;
3811 }
3812
3813 /* This is the guts of the machine-dependent assembler. STR points to a
3814 machine dependent instruction. This function is supposed to emit
3815 the frags/bytes it assembles to.
3816 */
3817
3818 static void
3819 insert_reg (const char *regname, int regnum)
3820 {
3821 char buf[100];
3822 int i;
3823
3824 #ifdef REGISTER_PREFIX
3825 if (!flag_reg_prefix_optional)
3826 {
3827 buf[0] = REGISTER_PREFIX;
3828 strcpy (buf + 1, regname);
3829 regname = buf;
3830 }
3831 #endif
3832
3833 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3834 &zero_address_frag));
3835
3836 for (i = 0; regname[i]; i++)
3837 buf[i] = TOUPPER (regname[i]);
3838 buf[i] = '\0';
3839
3840 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3841 &zero_address_frag));
3842 }
3843
3844 struct init_entry
3845 {
3846 const char *name;
3847 int number;
3848 };
3849
3850 static const struct init_entry init_table[] =
3851 {
3852 { "d0", DATA0 },
3853 { "d1", DATA1 },
3854 { "d2", DATA2 },
3855 { "d3", DATA3 },
3856 { "d4", DATA4 },
3857 { "d5", DATA5 },
3858 { "d6", DATA6 },
3859 { "d7", DATA7 },
3860 { "a0", ADDR0 },
3861 { "a1", ADDR1 },
3862 { "a2", ADDR2 },
3863 { "a3", ADDR3 },
3864 { "a4", ADDR4 },
3865 { "a5", ADDR5 },
3866 { "a6", ADDR6 },
3867 { "fp", ADDR6 },
3868 { "a7", ADDR7 },
3869 { "sp", ADDR7 },
3870 { "ssp", ADDR7 },
3871 { "fp0", FP0 },
3872 { "fp1", FP1 },
3873 { "fp2", FP2 },
3874 { "fp3", FP3 },
3875 { "fp4", FP4 },
3876 { "fp5", FP5 },
3877 { "fp6", FP6 },
3878 { "fp7", FP7 },
3879 { "fpi", FPI },
3880 { "fpiar", FPI },
3881 { "fpc", FPI },
3882 { "fps", FPS },
3883 { "fpsr", FPS },
3884 { "fpc", FPC },
3885 { "fpcr", FPC },
3886 { "control", FPC },
3887 { "status", FPS },
3888 { "iaddr", FPI },
3889
3890 { "cop0", COP0 },
3891 { "cop1", COP1 },
3892 { "cop2", COP2 },
3893 { "cop3", COP3 },
3894 { "cop4", COP4 },
3895 { "cop5", COP5 },
3896 { "cop6", COP6 },
3897 { "cop7", COP7 },
3898 { "pc", PC },
3899 { "zpc", ZPC },
3900 { "sr", SR },
3901
3902 { "ccr", CCR },
3903 { "cc", CCR },
3904
3905 { "acc", ACC },
3906 { "acc0", ACC },
3907 { "acc1", ACC1 },
3908 { "acc2", ACC2 },
3909 { "acc3", ACC3 },
3910 { "accext01", ACCEXT01 },
3911 { "accext23", ACCEXT23 },
3912 { "macsr", MACSR },
3913 { "mask", MASK },
3914
3915 /* Control registers. */
3916 { "sfc", SFC }, /* Source Function Code. */
3917 { "sfcr", SFC },
3918 { "dfc", DFC }, /* Destination Function Code. */
3919 { "dfcr", DFC },
3920 { "cacr", CACR }, /* Cache Control Register. */
3921 { "caar", CAAR }, /* Cache Address Register. */
3922
3923 { "usp", USP }, /* User Stack Pointer. */
3924 { "vbr", VBR }, /* Vector Base Register. */
3925 { "msp", MSP }, /* Master Stack Pointer. */
3926 { "isp", ISP }, /* Interrupt Stack Pointer. */
3927
3928 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3929 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3930 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3931 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3932
3933 /* 68ec040 versions of same */
3934 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3935 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3936 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3937 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3938
3939 /* Coldfire versions of same. The ColdFire programmer's reference
3940 manual indicated that the order is 2,3,0,1, but Ken Rose
3941 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3942 { "acr0", ACR0 }, /* Access Control Unit 0. */
3943 { "acr1", ACR1 }, /* Access Control Unit 1. */
3944 { "acr2", ACR2 }, /* Access Control Unit 2. */
3945 { "acr3", ACR3 }, /* Access Control Unit 3. */
3946
3947 { "tc", TC }, /* MMU Translation Control Register. */
3948 { "tcr", TC },
3949 { "asid", ASID },
3950
3951 { "mmusr", MMUSR }, /* MMU Status Register. */
3952 { "srp", SRP }, /* User Root Pointer. */
3953 { "urp", URP }, /* Supervisor Root Pointer. */
3954
3955 { "buscr", BUSCR },
3956 { "mmubar", MMUBAR },
3957 { "pcr", PCR },
3958
3959 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3960 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3961 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3962 { "mbar", MBAR }, /* Module Base Address Register. */
3963
3964 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3965 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3966 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3967 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3968 { "mpcr", MPCR }, /* mcfv4e registers. */
3969 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3970 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3971 { "asid", TC }, /* mcfv4e registers. */
3972 { "mmubar", BUSCR }, /* mcfv4e registers. */
3973 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3974 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3975 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3976 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3977 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3978 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3979 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3980 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3981 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3982 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3983 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3984 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3985
3986 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3987 { "rambar", RAMBAR }, /* mcf528x registers. */
3988
3989 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3990
3991 { "cac", CAC }, /* fido registers. */
3992 { "mbb", MBB }, /* fido registers. */
3993 /* End of control registers. */
3994
3995 { "ac", AC },
3996 { "bc", BC },
3997 { "cal", CAL },
3998 { "crp", CRP },
3999 { "drp", DRP },
4000 { "pcsr", PCSR },
4001 { "psr", PSR },
4002 { "scc", SCC },
4003 { "val", VAL },
4004 { "bad0", BAD0 },
4005 { "bad1", BAD1 },
4006 { "bad2", BAD2 },
4007 { "bad3", BAD3 },
4008 { "bad4", BAD4 },
4009 { "bad5", BAD5 },
4010 { "bad6", BAD6 },
4011 { "bad7", BAD7 },
4012 { "bac0", BAC0 },
4013 { "bac1", BAC1 },
4014 { "bac2", BAC2 },
4015 { "bac3", BAC3 },
4016 { "bac4", BAC4 },
4017 { "bac5", BAC5 },
4018 { "bac6", BAC6 },
4019 { "bac7", BAC7 },
4020
4021 { "ic", IC },
4022 { "dc", DC },
4023 { "nc", NC },
4024
4025 { "tt0", TT0 },
4026 { "tt1", TT1 },
4027 /* 68ec030 versions of same. */
4028 { "ac0", TT0 },
4029 { "ac1", TT1 },
4030 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4031 { "acusr", PSR },
4032
4033 /* Suppressed data and address registers. */
4034 { "zd0", ZDATA0 },
4035 { "zd1", ZDATA1 },
4036 { "zd2", ZDATA2 },
4037 { "zd3", ZDATA3 },
4038 { "zd4", ZDATA4 },
4039 { "zd5", ZDATA5 },
4040 { "zd6", ZDATA6 },
4041 { "zd7", ZDATA7 },
4042 { "za0", ZADDR0 },
4043 { "za1", ZADDR1 },
4044 { "za2", ZADDR2 },
4045 { "za3", ZADDR3 },
4046 { "za4", ZADDR4 },
4047 { "za5", ZADDR5 },
4048 { "za6", ZADDR6 },
4049 { "za7", ZADDR7 },
4050
4051 /* Upper and lower data and address registers, used by macw and msacw. */
4052 { "d0l", DATA0L },
4053 { "d1l", DATA1L },
4054 { "d2l", DATA2L },
4055 { "d3l", DATA3L },
4056 { "d4l", DATA4L },
4057 { "d5l", DATA5L },
4058 { "d6l", DATA6L },
4059 { "d7l", DATA7L },
4060
4061 { "a0l", ADDR0L },
4062 { "a1l", ADDR1L },
4063 { "a2l", ADDR2L },
4064 { "a3l", ADDR3L },
4065 { "a4l", ADDR4L },
4066 { "a5l", ADDR5L },
4067 { "a6l", ADDR6L },
4068 { "a7l", ADDR7L },
4069
4070 { "d0u", DATA0U },
4071 { "d1u", DATA1U },
4072 { "d2u", DATA2U },
4073 { "d3u", DATA3U },
4074 { "d4u", DATA4U },
4075 { "d5u", DATA5U },
4076 { "d6u", DATA6U },
4077 { "d7u", DATA7U },
4078
4079 { "a0u", ADDR0U },
4080 { "a1u", ADDR1U },
4081 { "a2u", ADDR2U },
4082 { "a3u", ADDR3U },
4083 { "a4u", ADDR4U },
4084 { "a5u", ADDR5U },
4085 { "a6u", ADDR6U },
4086 { "a7u", ADDR7U },
4087
4088 { 0, 0 }
4089 };
4090
4091 static void
4092 init_regtable (void)
4093 {
4094 int i;
4095 for (i = 0; init_table[i].name; i++)
4096 insert_reg (init_table[i].name, init_table[i].number);
4097 }
4098
4099 void
4100 md_assemble (char *str)
4101 {
4102 const char *er;
4103 short *fromP;
4104 char *toP = NULL;
4105 int m, n = 0;
4106 char *to_beg_P;
4107 int shorts_this_frag;
4108 fixS *fixP;
4109
4110 if (!selected_cpu && !selected_arch)
4111 {
4112 /* We've not selected an architecture yet. Set the default
4113 now. We do this lazily so that an initial .cpu or .arch directive
4114 can specify. */
4115 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4116 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4117 }
4118 if (!initialized)
4119 m68k_init_arch ();
4120
4121 /* In MRI mode, the instruction and operands are separated by a
4122 space. Anything following the operands is a comment. The label
4123 has already been removed. */
4124 if (flag_mri)
4125 {
4126 char *s;
4127 int fields = 0;
4128 int infield = 0;
4129 int inquote = 0;
4130
4131 for (s = str; *s != '\0'; s++)
4132 {
4133 if ((*s == ' ' || *s == '\t') && ! inquote)
4134 {
4135 if (infield)
4136 {
4137 ++fields;
4138 if (fields >= 2)
4139 {
4140 *s = '\0';
4141 break;
4142 }
4143 infield = 0;
4144 }
4145 }
4146 else
4147 {
4148 if (! infield)
4149 infield = 1;
4150 if (*s == '\'')
4151 inquote = ! inquote;
4152 }
4153 }
4154 }
4155
4156 memset (&the_ins, '\0', sizeof (the_ins));
4157 m68k_ip (str);
4158 er = the_ins.error;
4159 if (!er)
4160 {
4161 for (n = 0; n < the_ins.numargs; n++)
4162 if (the_ins.operands[n].error)
4163 {
4164 er = the_ins.operands[n].error;
4165 break;
4166 }
4167 }
4168 if (er)
4169 {
4170 as_bad (_("%s -- statement `%s' ignored"), er, str);
4171 return;
4172 }
4173
4174 /* If there is a current label, record that it marks an instruction. */
4175 if (current_label != NULL)
4176 {
4177 current_label->text = 1;
4178 current_label = NULL;
4179 }
4180
4181 #ifdef OBJ_ELF
4182 /* Tie dwarf2 debug info to the address at the start of the insn. */
4183 dwarf2_emit_insn (0);
4184 #endif
4185
4186 if (the_ins.nfrag == 0)
4187 {
4188 /* No frag hacking involved; just put it out. */
4189 toP = frag_more (2 * the_ins.numo);
4190 fromP = &the_ins.opcode[0];
4191 for (m = the_ins.numo; m; --m)
4192 {
4193 md_number_to_chars (toP, (long) (*fromP), 2);
4194 toP += 2;
4195 fromP++;
4196 }
4197 /* Put out symbol-dependent info. */
4198 for (m = 0; m < the_ins.nrel; m++)
4199 {
4200 switch (the_ins.reloc[m].wid)
4201 {
4202 case 'B':
4203 n = 1;
4204 break;
4205 case 'b':
4206 n = 1;
4207 break;
4208 case '3':
4209 n = 1;
4210 break;
4211 case 'w':
4212 case 'W':
4213 n = 2;
4214 break;
4215 case 'l':
4216 n = 4;
4217 break;
4218 default:
4219 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4220 the_ins.reloc[m].wid);
4221 }
4222
4223 fixP = fix_new_exp (frag_now,
4224 ((toP - frag_now->fr_literal)
4225 - the_ins.numo * 2 + the_ins.reloc[m].n),
4226 n,
4227 &the_ins.reloc[m].exp,
4228 the_ins.reloc[m].pcrel,
4229 get_reloc_code (n, the_ins.reloc[m].pcrel,
4230 the_ins.reloc[m].pic_reloc));
4231 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4232 if (the_ins.reloc[m].wid == 'B')
4233 fixP->fx_signed = 1;
4234 }
4235 return;
4236 }
4237
4238 /* There's some frag hacking. */
4239 {
4240 /* Calculate the max frag size. */
4241 int wid;
4242
4243 wid = 2 * the_ins.fragb[0].fragoff;
4244 for (n = 1; n < the_ins.nfrag; n++)
4245 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4246 /* frag_var part. */
4247 wid += 10;
4248 /* Make sure the whole insn fits in one chunk, in particular that
4249 the var part is attached, as we access one byte before the
4250 variable frag for byte branches. */
4251 frag_grow (wid);
4252 }
4253
4254 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4255 {
4256 int wid;
4257
4258 if (n == 0)
4259 wid = 2 * the_ins.fragb[n].fragoff;
4260 else
4261 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4262 toP = frag_more (wid);
4263 to_beg_P = toP;
4264 shorts_this_frag = 0;
4265 for (m = wid / 2; m; --m)
4266 {
4267 md_number_to_chars (toP, (long) (*fromP), 2);
4268 toP += 2;
4269 fromP++;
4270 shorts_this_frag++;
4271 }
4272 for (m = 0; m < the_ins.nrel; m++)
4273 {
4274 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4275 {
4276 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4277 break;
4278 }
4279 wid = the_ins.reloc[m].wid;
4280 if (wid == 0)
4281 continue;
4282 the_ins.reloc[m].wid = 0;
4283 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4284
4285 fixP = fix_new_exp (frag_now,
4286 ((toP - frag_now->fr_literal)
4287 - the_ins.numo * 2 + the_ins.reloc[m].n),
4288 wid,
4289 &the_ins.reloc[m].exp,
4290 the_ins.reloc[m].pcrel,
4291 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4292 the_ins.reloc[m].pic_reloc));
4293 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4294 }
4295 (void) frag_var (rs_machine_dependent, 10, 0,
4296 (relax_substateT) (the_ins.fragb[n].fragty),
4297 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4298 }
4299 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4300 shorts_this_frag = 0;
4301 if (n)
4302 {
4303 toP = frag_more (n * 2);
4304 while (n--)
4305 {
4306 md_number_to_chars (toP, (long) (*fromP), 2);
4307 toP += 2;
4308 fromP++;
4309 shorts_this_frag++;
4310 }
4311 }
4312 for (m = 0; m < the_ins.nrel; m++)
4313 {
4314 int wid;
4315
4316 wid = the_ins.reloc[m].wid;
4317 if (wid == 0)
4318 continue;
4319 the_ins.reloc[m].wid = 0;
4320 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4321
4322 fixP = fix_new_exp (frag_now,
4323 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4324 - shorts_this_frag * 2),
4325 wid,
4326 &the_ins.reloc[m].exp,
4327 the_ins.reloc[m].pcrel,
4328 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4329 the_ins.reloc[m].pic_reloc));
4330 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4331 }
4332 }
4333
4334 /* Comparison function used by qsort to rank the opcode entries by name. */
4335
4336 static int
4337 m68k_compare_opcode (const void * v1, const void * v2)
4338 {
4339 struct m68k_opcode * op1, * op2;
4340 int ret;
4341
4342 if (v1 == v2)
4343 return 0;
4344
4345 op1 = *(struct m68k_opcode **) v1;
4346 op2 = *(struct m68k_opcode **) v2;
4347
4348 /* Compare the two names. If different, return the comparison.
4349 If the same, return the order they are in the opcode table. */
4350 ret = strcmp (op1->name, op2->name);
4351 if (ret)
4352 return ret;
4353 if (op1 < op2)
4354 return -1;
4355 return 1;
4356 }
4357
4358 void
4359 md_begin (void)
4360 {
4361 const struct m68k_opcode *ins;
4362 struct m68k_incant *hack, *slak;
4363 const char *retval = 0; /* Empty string, or error msg text. */
4364 int i;
4365
4366 /* Set up hash tables with 68000 instructions.
4367 similar to what the vax assembler does. */
4368 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4369 a copy of it at runtime, adding in the information we want but isn't
4370 there. I think it'd be better to have an awk script hack the table
4371 at compile time. Or even just xstr the table and use it as-is. But
4372 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4373 names. */
4374
4375 if (flag_mri)
4376 {
4377 flag_reg_prefix_optional = 1;
4378 m68k_abspcadd = 1;
4379 if (! m68k_rel32_from_cmdline)
4380 m68k_rel32 = 0;
4381 }
4382
4383 /* First sort the opcode table into alphabetical order to seperate
4384 the order that the assembler wants to see the opcodes from the
4385 order that the disassembler wants to see them. */
4386 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4387 if (!m68k_sorted_opcodes)
4388 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4389 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4390
4391 for (i = m68k_numopcodes; i--;)
4392 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4393
4394 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4395 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4396
4397 op_hash = hash_new ();
4398
4399 obstack_begin (&robyn, 4000);
4400 for (i = 0; i < m68k_numopcodes; i++)
4401 {
4402 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4403 do
4404 {
4405 ins = m68k_sorted_opcodes[i];
4406
4407 /* We must enter all insns into the table, because .arch and
4408 .cpu directives can change things. */
4409 slak->m_operands = ins->args;
4410 slak->m_arch = ins->arch;
4411 slak->m_opcode = ins->opcode;
4412
4413 /* In most cases we can determine the number of opcode words
4414 by checking the second word of the mask. Unfortunately
4415 some instructions have 2 opcode words, but no fixed bits
4416 in the second word. A leading dot in the operands
4417 string also indicates 2 opcodes. */
4418 if (*slak->m_operands == '.')
4419 {
4420 slak->m_operands++;
4421 slak->m_codenum = 2;
4422 }
4423 else if (ins->match & 0xffffL)
4424 slak->m_codenum = 2;
4425 else
4426 slak->m_codenum = 1;
4427 slak->m_opnum = strlen (slak->m_operands) / 2;
4428
4429 if (i + 1 != m68k_numopcodes
4430 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4431 {
4432 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4433 i++;
4434 }
4435 else
4436 slak->m_next = 0;
4437 slak = slak->m_next;
4438 }
4439 while (slak);
4440
4441 retval = hash_insert (op_hash, ins->name, (char *) hack);
4442 if (retval)
4443 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4444 }
4445
4446 for (i = 0; i < m68k_numaliases; i++)
4447 {
4448 const char *name = m68k_opcode_aliases[i].primary;
4449 const char *alias = m68k_opcode_aliases[i].alias;
4450 PTR val = hash_find (op_hash, name);
4451
4452 if (!val)
4453 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4454 retval = hash_insert (op_hash, alias, val);
4455 if (retval)
4456 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4457 }
4458
4459 /* In MRI mode, all unsized branches are variable sized. Normally,
4460 they are word sized. */
4461 if (flag_mri)
4462 {
4463 static struct m68k_opcode_alias mri_aliases[] =
4464 {
4465 { "bhi", "jhi", },
4466 { "bls", "jls", },
4467 { "bcc", "jcc", },
4468 { "bcs", "jcs", },
4469 { "bne", "jne", },
4470 { "beq", "jeq", },
4471 { "bvc", "jvc", },
4472 { "bvs", "jvs", },
4473 { "bpl", "jpl", },
4474 { "bmi", "jmi", },
4475 { "bge", "jge", },
4476 { "blt", "jlt", },
4477 { "bgt", "jgt", },
4478 { "ble", "jle", },
4479 { "bra", "jra", },
4480 { "bsr", "jbsr", },
4481 };
4482
4483 for (i = 0;
4484 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4485 i++)
4486 {
4487 const char *name = mri_aliases[i].primary;
4488 const char *alias = mri_aliases[i].alias;
4489 PTR val = hash_find (op_hash, name);
4490
4491 if (!val)
4492 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4493 retval = hash_jam (op_hash, alias, val);
4494 if (retval)
4495 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4496 }
4497 }
4498
4499 for (i = 0; i < (int) sizeof (notend_table); i++)
4500 {
4501 notend_table[i] = 0;
4502 alt_notend_table[i] = 0;
4503 }
4504
4505 notend_table[','] = 1;
4506 notend_table['{'] = 1;
4507 notend_table['}'] = 1;
4508 alt_notend_table['a'] = 1;
4509 alt_notend_table['A'] = 1;
4510 alt_notend_table['d'] = 1;
4511 alt_notend_table['D'] = 1;
4512 alt_notend_table['#'] = 1;
4513 alt_notend_table['&'] = 1;
4514 alt_notend_table['f'] = 1;
4515 alt_notend_table['F'] = 1;
4516 #ifdef REGISTER_PREFIX
4517 alt_notend_table[REGISTER_PREFIX] = 1;
4518 #endif
4519
4520 /* We need to put '(' in alt_notend_table to handle
4521 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4522 alt_notend_table['('] = 1;
4523
4524 /* We need to put '@' in alt_notend_table to handle
4525 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4526 alt_notend_table['@'] = 1;
4527
4528 /* We need to put digits in alt_notend_table to handle
4529 bfextu %d0{24:1},%d0 */
4530 alt_notend_table['0'] = 1;
4531 alt_notend_table['1'] = 1;
4532 alt_notend_table['2'] = 1;
4533 alt_notend_table['3'] = 1;
4534 alt_notend_table['4'] = 1;
4535 alt_notend_table['5'] = 1;
4536 alt_notend_table['6'] = 1;
4537 alt_notend_table['7'] = 1;
4538 alt_notend_table['8'] = 1;
4539 alt_notend_table['9'] = 1;
4540
4541 #ifndef MIT_SYNTAX_ONLY
4542 /* Insert pseudo ops, these have to go into the opcode table since
4543 gas expects pseudo ops to start with a dot. */
4544 {
4545 int n = 0;
4546
4547 while (mote_pseudo_table[n].poc_name)
4548 {
4549 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4550 hash_insert (op_hash,
4551 mote_pseudo_table[n].poc_name, (char *) hack);
4552 hack->m_operands = 0;
4553 hack->m_opnum = n;
4554 n++;
4555 }
4556 }
4557 #endif
4558
4559 init_regtable ();
4560
4561 #ifdef OBJ_ELF
4562 record_alignment (text_section, 2);
4563 record_alignment (data_section, 2);
4564 record_alignment (bss_section, 2);
4565 #endif
4566 }
4567
4568 \f
4569 /* This is called when a label is defined. */
4570
4571 void
4572 m68k_frob_label (symbolS *sym)
4573 {
4574 struct label_line *n;
4575
4576 n = (struct label_line *) xmalloc (sizeof *n);
4577 n->next = labels;
4578 n->label = sym;
4579 as_where (&n->file, &n->line);
4580 n->text = 0;
4581 labels = n;
4582 current_label = n;
4583
4584 #ifdef OBJ_ELF
4585 dwarf2_emit_label (sym);
4586 #endif
4587 }
4588
4589 /* This is called when a value that is not an instruction is emitted. */
4590
4591 void
4592 m68k_flush_pending_output (void)
4593 {
4594 current_label = NULL;
4595 }
4596
4597 /* This is called at the end of the assembly, when the final value of
4598 the label is known. We warn if this is a text symbol aligned at an
4599 odd location. */
4600
4601 void
4602 m68k_frob_symbol (symbolS *sym)
4603 {
4604 if (S_GET_SEGMENT (sym) == reg_section
4605 && (int) S_GET_VALUE (sym) < 0)
4606 {
4607 S_SET_SEGMENT (sym, absolute_section);
4608 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4609 }
4610 else if ((S_GET_VALUE (sym) & 1) != 0)
4611 {
4612 struct label_line *l;
4613
4614 for (l = labels; l != NULL; l = l->next)
4615 {
4616 if (l->label == sym)
4617 {
4618 if (l->text)
4619 as_warn_where (l->file, l->line,
4620 _("text label `%s' aligned to odd boundary"),
4621 S_GET_NAME (sym));
4622 break;
4623 }
4624 }
4625 }
4626 }
4627 \f
4628 /* This is called if we go in or out of MRI mode because of the .mri
4629 pseudo-op. */
4630
4631 void
4632 m68k_mri_mode_change (int on)
4633 {
4634 if (on)
4635 {
4636 if (! flag_reg_prefix_optional)
4637 {
4638 flag_reg_prefix_optional = 1;
4639 #ifdef REGISTER_PREFIX
4640 init_regtable ();
4641 #endif
4642 }
4643 m68k_abspcadd = 1;
4644 if (! m68k_rel32_from_cmdline)
4645 m68k_rel32 = 0;
4646 }
4647 else
4648 {
4649 if (! reg_prefix_optional_seen)
4650 {
4651 #ifdef REGISTER_PREFIX_OPTIONAL
4652 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4653 #else
4654 flag_reg_prefix_optional = 0;
4655 #endif
4656 #ifdef REGISTER_PREFIX
4657 init_regtable ();
4658 #endif
4659 }
4660 m68k_abspcadd = 0;
4661 if (! m68k_rel32_from_cmdline)
4662 m68k_rel32 = 1;
4663 }
4664 }
4665
4666 /* Equal to MAX_PRECISION in atof-ieee.c. */
4667 #define MAX_LITTLENUMS 6
4668
4669 /* Turn a string in input_line_pointer into a floating point constant
4670 of type TYPE, and store the appropriate bytes in *LITP. The number
4671 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4672 returned, or NULL on OK. */
4673
4674 char *
4675 md_atof (int type, char *litP, int *sizeP)
4676 {
4677 int prec;
4678 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4679 LITTLENUM_TYPE *wordP;
4680 char *t;
4681
4682 switch (type)
4683 {
4684 case 'f':
4685 case 'F':
4686 case 's':
4687 case 'S':
4688 prec = 2;
4689 break;
4690
4691 case 'd':
4692 case 'D':
4693 case 'r':
4694 case 'R':
4695 prec = 4;
4696 break;
4697
4698 case 'x':
4699 case 'X':
4700 prec = 6;
4701 break;
4702
4703 case 'p':
4704 case 'P':
4705 prec = 6;
4706 break;
4707
4708 default:
4709 *sizeP = 0;
4710 return _("Bad call to MD_ATOF()");
4711 }
4712 t = atof_ieee (input_line_pointer, type, words);
4713 if (t)
4714 input_line_pointer = t;
4715
4716 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4717 for (wordP = words; prec--;)
4718 {
4719 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4720 litP += sizeof (LITTLENUM_TYPE);
4721 }
4722 return 0;
4723 }
4724
4725 void
4726 md_number_to_chars (char *buf, valueT val, int n)
4727 {
4728 number_to_chars_bigendian (buf, val, n);
4729 }
4730
4731 void
4732 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4733 {
4734 offsetT val = *valP;
4735 addressT upper_limit;
4736 offsetT lower_limit;
4737
4738 /* This is unnecessary but it convinces the native rs6000 compiler
4739 to generate the code we want. */
4740 char *buf = fixP->fx_frag->fr_literal;
4741 buf += fixP->fx_where;
4742 /* End ibm compiler workaround. */
4743
4744 val = SEXT (val);
4745
4746 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4747 fixP->fx_done = 1;
4748
4749 #ifdef OBJ_ELF
4750 if (fixP->fx_addsy)
4751 {
4752 memset (buf, 0, fixP->fx_size);
4753 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4754
4755 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4756 && !S_IS_DEFINED (fixP->fx_addsy)
4757 && !S_IS_WEAK (fixP->fx_addsy))
4758 S_SET_WEAK (fixP->fx_addsy);
4759 return;
4760 }
4761 #elif defined(OBJ_AOUT)
4762 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4763 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4764 {
4765 memset (buf, 0, fixP->fx_size);
4766 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4767 return;
4768 }
4769 #endif
4770
4771 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4772 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4773 return;
4774
4775 switch (fixP->fx_size)
4776 {
4777 /* The cast to offsetT below are necessary to make code
4778 correct for machines where ints are smaller than offsetT. */
4779 case 1:
4780 *buf++ = val;
4781 upper_limit = 0x7f;
4782 lower_limit = - (offsetT) 0x80;
4783 break;
4784 case 2:
4785 *buf++ = (val >> 8);
4786 *buf++ = val;
4787 upper_limit = 0x7fff;
4788 lower_limit = - (offsetT) 0x8000;
4789 break;
4790 case 4:
4791 *buf++ = (val >> 24);
4792 *buf++ = (val >> 16);
4793 *buf++ = (val >> 8);
4794 *buf++ = val;
4795 upper_limit = 0x7fffffff;
4796 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4797 break;
4798 default:
4799 BAD_CASE (fixP->fx_size);
4800 }
4801
4802 /* Fix up a negative reloc. */
4803 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4804 {
4805 fixP->fx_addsy = fixP->fx_subsy;
4806 fixP->fx_subsy = NULL;
4807 fixP->fx_tcbit = 1;
4808 }
4809
4810 /* For non-pc-relative values, it's conceivable we might get something
4811 like "0xff" for a byte field. So extend the upper part of the range
4812 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4813 so that we can do any range checking at all. */
4814 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4815 upper_limit = upper_limit * 2 + 1;
4816
4817 if ((addressT) val > upper_limit
4818 && (val > 0 || val < lower_limit))
4819 as_bad_where (fixP->fx_file, fixP->fx_line,
4820 _("value %ld out of range"), (long)val);
4821
4822 /* A one byte PC-relative reloc means a short branch. We can't use
4823 a short branch with a value of 0 or -1, because those indicate
4824 different opcodes (branches with longer offsets). fixup_segment
4825 in write.c may have clobbered fx_pcrel, so we need to examine the
4826 reloc type. */
4827 if ((fixP->fx_pcrel
4828 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4829 && fixP->fx_size == 1
4830 && (fixP->fx_addsy == NULL
4831 || S_IS_DEFINED (fixP->fx_addsy))
4832 && (val == 0 || val == -1))
4833 as_bad_where (fixP->fx_file, fixP->fx_line,
4834 _("invalid byte branch offset"));
4835 }
4836
4837 /* *fragP has been relaxed to its final size, and now needs to have
4838 the bytes inside it modified to conform to the new size There is UGLY
4839 MAGIC here. ..
4840 */
4841 static void
4842 md_convert_frag_1 (fragS *fragP)
4843 {
4844 long disp;
4845 fixS *fixP = NULL;
4846
4847 /* Address in object code of the displacement. */
4848 register int object_address = fragP->fr_fix + fragP->fr_address;
4849
4850 /* Address in gas core of the place to store the displacement. */
4851 /* This convinces the native rs6000 compiler to generate the code we
4852 want. */
4853 register char *buffer_address = fragP->fr_literal;
4854 buffer_address += fragP->fr_fix;
4855 /* End ibm compiler workaround. */
4856
4857 /* The displacement of the address, from current location. */
4858 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4859 disp = (disp + fragP->fr_offset) - object_address;
4860
4861 switch (fragP->fr_subtype)
4862 {
4863 case TAB (BRANCHBWL, BYTE):
4864 case TAB (BRABSJUNC, BYTE):
4865 case TAB (BRABSJCOND, BYTE):
4866 case TAB (BRANCHBW, BYTE):
4867 know (issbyte (disp));
4868 if (disp == 0)
4869 as_bad_where (fragP->fr_file, fragP->fr_line,
4870 _("short branch with zero offset: use :w"));
4871 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4872 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4873 fixP->fx_pcrel_adjust = -1;
4874 break;
4875 case TAB (BRANCHBWL, SHORT):
4876 case TAB (BRABSJUNC, SHORT):
4877 case TAB (BRABSJCOND, SHORT):
4878 case TAB (BRANCHBW, SHORT):
4879 fragP->fr_opcode[1] = 0x00;
4880 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4881 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4882 fragP->fr_fix += 2;
4883 break;
4884 case TAB (BRANCHBWL, LONG):
4885 fragP->fr_opcode[1] = (char) 0xFF;
4886 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4887 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4888 fragP->fr_fix += 4;
4889 break;
4890 case TAB (BRABSJUNC, LONG):
4891 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4892 {
4893 if (flag_keep_pcrel)
4894 as_bad_where (fragP->fr_file, fragP->fr_line,
4895 _("Conversion of PC relative BSR to absolute JSR"));
4896 fragP->fr_opcode[0] = 0x4E;
4897 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4898 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4899 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4900 fragP->fr_fix += 4;
4901 }
4902 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4903 {
4904 if (flag_keep_pcrel)
4905 as_bad_where (fragP->fr_file, fragP->fr_line,
4906 _("Conversion of PC relative branch to absolute jump"));
4907 fragP->fr_opcode[0] = 0x4E;
4908 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4909 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4910 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4911 fragP->fr_fix += 4;
4912 }
4913 else
4914 {
4915 /* This cannot happen, because jbsr and jbra are the only two
4916 unconditional branches. */
4917 abort ();
4918 }
4919 break;
4920 case TAB (BRABSJCOND, LONG):
4921 if (flag_keep_pcrel)
4922 as_bad_where (fragP->fr_file, fragP->fr_line,
4923 _("Conversion of PC relative conditional branch to absolute jump"));
4924
4925 /* Only Bcc 68000 instructions can come here
4926 Change bcc into b!cc/jmp absl long. */
4927 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4928 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4929
4930 /* JF: these used to be fr_opcode[2,3], but they may be in a
4931 different frag, in which case referring to them is a no-no.
4932 Only fr_opcode[0,1] are guaranteed to work. */
4933 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4934 *buffer_address++ = (char) 0xf9;
4935 fragP->fr_fix += 2; /* Account for jmp instruction. */
4936 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4937 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4938 fragP->fr_fix += 4;
4939 break;
4940 case TAB (FBRANCH, SHORT):
4941 know ((fragP->fr_opcode[1] & 0x40) == 0);
4942 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4943 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4944 fragP->fr_fix += 2;
4945 break;
4946 case TAB (FBRANCH, LONG):
4947 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4948 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4949 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4950 fragP->fr_fix += 4;
4951 break;
4952 case TAB (DBCCLBR, SHORT):
4953 case TAB (DBCCABSJ, SHORT):
4954 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4955 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4956 fragP->fr_fix += 2;
4957 break;
4958 case TAB (DBCCLBR, LONG):
4959 /* Only DBcc instructions can come here.
4960 Change dbcc into dbcc/bral.
4961 JF: these used to be fr_opcode[2-7], but that's wrong. */
4962 if (flag_keep_pcrel)
4963 as_bad_where (fragP->fr_file, fragP->fr_line,
4964 _("Conversion of DBcc to absolute jump"));
4965
4966 *buffer_address++ = 0x00; /* Branch offset = 4. */
4967 *buffer_address++ = 0x04;
4968 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4969 *buffer_address++ = 0x06;
4970 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4971 *buffer_address++ = (char) 0xff;
4972
4973 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4974 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4975 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4976 fragP->fr_fix += 4;
4977 break;
4978 case TAB (DBCCABSJ, LONG):
4979 /* Only DBcc instructions can come here.
4980 Change dbcc into dbcc/jmp.
4981 JF: these used to be fr_opcode[2-7], but that's wrong. */
4982 if (flag_keep_pcrel)
4983 as_bad_where (fragP->fr_file, fragP->fr_line,
4984 _("Conversion of PC relative conditional branch to absolute jump"));
4985
4986 *buffer_address++ = 0x00; /* Branch offset = 4. */
4987 *buffer_address++ = 0x04;
4988 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4989 *buffer_address++ = 0x06;
4990 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4991 *buffer_address++ = (char) 0xf9;
4992
4993 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4994 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4995 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4996 fragP->fr_fix += 4;
4997 break;
4998 case TAB (PCREL1632, SHORT):
4999 fragP->fr_opcode[1] &= ~0x3F;
5000 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
5001 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5002 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5003 fragP->fr_fix += 2;
5004 break;
5005 case TAB (PCREL1632, LONG):
5006 /* Already set to mode 7.3; this indicates: PC indirect with
5007 suppressed index, 32-bit displacement. */
5008 *buffer_address++ = 0x01;
5009 *buffer_address++ = 0x70;
5010 fragP->fr_fix += 2;
5011 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5012 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5013 fixP->fx_pcrel_adjust = 2;
5014 fragP->fr_fix += 4;
5015 break;
5016 case TAB (PCINDEX, BYTE):
5017 assert (fragP->fr_fix >= 2);
5018 buffer_address[-2] &= ~1;
5019 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5020 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5021 fixP->fx_pcrel_adjust = 1;
5022 break;
5023 case TAB (PCINDEX, SHORT):
5024 assert (fragP->fr_fix >= 2);
5025 buffer_address[-2] |= 0x1;
5026 buffer_address[-1] = 0x20;
5027 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5028 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5029 fixP->fx_pcrel_adjust = 2;
5030 fragP->fr_fix += 2;
5031 break;
5032 case TAB (PCINDEX, LONG):
5033 assert (fragP->fr_fix >= 2);
5034 buffer_address[-2] |= 0x1;
5035 buffer_address[-1] = 0x30;
5036 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5037 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5038 fixP->fx_pcrel_adjust = 2;
5039 fragP->fr_fix += 4;
5040 break;
5041 case TAB (ABSTOPCREL, SHORT):
5042 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5043 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5044 fragP->fr_fix += 2;
5045 break;
5046 case TAB (ABSTOPCREL, LONG):
5047 if (flag_keep_pcrel)
5048 as_fatal (_("Conversion of PC relative displacement to absolute"));
5049 /* The thing to do here is force it to ABSOLUTE LONG, since
5050 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5051 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5052 abort ();
5053 fragP->fr_opcode[1] &= ~0x3F;
5054 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
5055 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5056 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5057 fragP->fr_fix += 4;
5058 break;
5059 }
5060 if (fixP)
5061 {
5062 fixP->fx_file = fragP->fr_file;
5063 fixP->fx_line = fragP->fr_line;
5064 }
5065 }
5066
5067 void
5068 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5069 segT sec ATTRIBUTE_UNUSED,
5070 fragS *fragP)
5071 {
5072 md_convert_frag_1 (fragP);
5073 }
5074
5075 /* Force truly undefined symbols to their maximum size, and generally set up
5076 the frag list to be relaxed
5077 */
5078 int
5079 md_estimate_size_before_relax (fragS *fragP, segT segment)
5080 {
5081 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5082 switch (fragP->fr_subtype)
5083 {
5084 case TAB (BRANCHBWL, SZ_UNDEF):
5085 case TAB (BRABSJUNC, SZ_UNDEF):
5086 case TAB (BRABSJCOND, SZ_UNDEF):
5087 {
5088 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5089 && relaxable_symbol (fragP->fr_symbol))
5090 {
5091 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5092 }
5093 else if (flag_short_refs)
5094 {
5095 /* Symbol is undefined and we want short ref. */
5096 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5097 }
5098 else
5099 {
5100 /* Symbol is still undefined. Make it LONG. */
5101 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5102 }
5103 break;
5104 }
5105
5106 case TAB (BRANCHBW, SZ_UNDEF):
5107 {
5108 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5109 && relaxable_symbol (fragP->fr_symbol))
5110 {
5111 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5112 }
5113 else
5114 {
5115 /* Symbol is undefined and we don't have long branches. */
5116 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5117 }
5118 break;
5119 }
5120
5121 case TAB (FBRANCH, SZ_UNDEF):
5122 case TAB (DBCCLBR, SZ_UNDEF):
5123 case TAB (DBCCABSJ, SZ_UNDEF):
5124 case TAB (PCREL1632, SZ_UNDEF):
5125 {
5126 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5127 && relaxable_symbol (fragP->fr_symbol))
5128 || flag_short_refs)
5129 {
5130 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5131 }
5132 else
5133 {
5134 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5135 }
5136 break;
5137 }
5138
5139 case TAB (PCINDEX, SZ_UNDEF):
5140 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5141 && relaxable_symbol (fragP->fr_symbol)))
5142 {
5143 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5144 }
5145 else
5146 {
5147 fragP->fr_subtype = TAB (PCINDEX, LONG);
5148 }
5149 break;
5150
5151 case TAB (ABSTOPCREL, SZ_UNDEF):
5152 {
5153 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5154 && relaxable_symbol (fragP->fr_symbol)))
5155 {
5156 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5157 }
5158 else
5159 {
5160 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5161 }
5162 break;
5163 }
5164
5165 default:
5166 break;
5167 }
5168
5169 /* Now that SZ_UNDEF are taken care of, check others. */
5170 switch (fragP->fr_subtype)
5171 {
5172 case TAB (BRANCHBWL, BYTE):
5173 case TAB (BRABSJUNC, BYTE):
5174 case TAB (BRABSJCOND, BYTE):
5175 case TAB (BRANCHBW, BYTE):
5176 /* We can't do a short jump to the next instruction, so in that
5177 case we force word mode. If the symbol is at the start of a
5178 frag, and it is the next frag with any data in it (usually
5179 this is just the next frag, but assembler listings may
5180 introduce empty frags), we must use word mode. */
5181 if (fragP->fr_symbol)
5182 {
5183 fragS *sym_frag;
5184
5185 sym_frag = symbol_get_frag (fragP->fr_symbol);
5186 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5187 {
5188 fragS *l;
5189
5190 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5191 if (l->fr_fix != 0)
5192 break;
5193 if (l == sym_frag)
5194 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5195 }
5196 }
5197 break;
5198 default:
5199 break;
5200 }
5201 return md_relax_table[fragP->fr_subtype].rlx_length;
5202 }
5203
5204 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5205 /* the bit-field entries in the relocation_info struct plays hell
5206 with the byte-order problems of cross-assembly. So as a hack,
5207 I added this mach. dependent ri twiddler. Ugly, but it gets
5208 you there. -KWK */
5209 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5210 are symbolnum, most sig. byte first. Last byte is broken up with
5211 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5212 nibble as nuthin. (on Sun 3 at least) */
5213 /* Translate the internal relocation information into target-specific
5214 format. */
5215 #ifdef comment
5216 void
5217 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5218 {
5219 /* This is easy. */
5220 md_number_to_chars (the_bytes, ri->r_address, 4);
5221 /* Now the fun stuff. */
5222 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5223 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5224 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5225 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5226 | ((ri->r_length << 5) & 0x60)
5227 | ((ri->r_extern << 4) & 0x10));
5228 }
5229
5230 #endif
5231
5232 #endif /* OBJ_AOUT or OBJ_BOUT */
5233
5234 #ifndef WORKING_DOT_WORD
5235 int md_short_jump_size = 4;
5236 int md_long_jump_size = 6;
5237
5238 void
5239 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5240 fragS *frag ATTRIBUTE_UNUSED,
5241 symbolS *to_symbol ATTRIBUTE_UNUSED)
5242 {
5243 valueT offset;
5244
5245 offset = to_addr - (from_addr + 2);
5246
5247 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5248 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5249 }
5250
5251 void
5252 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5253 fragS *frag, symbolS *to_symbol)
5254 {
5255 valueT offset;
5256
5257 if (!HAVE_LONG_BRANCH (current_architecture))
5258 {
5259 if (flag_keep_pcrel)
5260 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5261 offset = to_addr - S_GET_VALUE (to_symbol);
5262 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5263 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5264 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5265 0, NO_RELOC);
5266 }
5267 else
5268 {
5269 offset = to_addr - (from_addr + 2);
5270 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5271 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5272 }
5273 }
5274
5275 #endif
5276
5277 /* Different values of OK tell what its OK to return. Things that
5278 aren't OK are an error (what a shock, no?)
5279
5280 0: Everything is OK
5281 10: Absolute 1:8 only
5282 20: Absolute 0:7 only
5283 30: absolute 0:15 only
5284 40: Absolute 0:31 only
5285 50: absolute 0:127 only
5286 55: absolute -64:63 only
5287 60: absolute -128:127 only
5288 65: absolute 0:511 only
5289 70: absolute 0:4095 only
5290 80: absolute -1, 1:7 only
5291 90: No bignums. */
5292
5293 static int
5294 get_num (struct m68k_exp *exp, int ok)
5295 {
5296 if (exp->exp.X_op == O_absent)
5297 {
5298 /* Do the same thing the VAX asm does. */
5299 op (exp) = O_constant;
5300 adds (exp) = 0;
5301 subs (exp) = 0;
5302 offs (exp) = 0;
5303 if (ok == 10)
5304 {
5305 as_warn (_("expression out of range: defaulting to 1"));
5306 offs (exp) = 1;
5307 }
5308 }
5309 else if (exp->exp.X_op == O_constant)
5310 {
5311 switch (ok)
5312 {
5313 case 10:
5314 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5315 {
5316 as_warn (_("expression out of range: defaulting to 1"));
5317 offs (exp) = 1;
5318 }
5319 break;
5320 case 20:
5321 if ((valueT) TRUNC (offs (exp)) > 7)
5322 goto outrange;
5323 break;
5324 case 30:
5325 if ((valueT) TRUNC (offs (exp)) > 15)
5326 goto outrange;
5327 break;
5328 case 40:
5329 if ((valueT) TRUNC (offs (exp)) > 32)
5330 goto outrange;
5331 break;
5332 case 50:
5333 if ((valueT) TRUNC (offs (exp)) > 127)
5334 goto outrange;
5335 break;
5336 case 55:
5337 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5338 goto outrange;
5339 break;
5340 case 60:
5341 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5342 goto outrange;
5343 break;
5344 case 65:
5345 if ((valueT) TRUNC (offs (exp)) > 511)
5346 goto outrange;
5347 break;
5348 case 70:
5349 if ((valueT) TRUNC (offs (exp)) > 4095)
5350 {
5351 outrange:
5352 as_warn (_("expression out of range: defaulting to 0"));
5353 offs (exp) = 0;
5354 }
5355 break;
5356 case 80:
5357 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5358 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5359 {
5360 as_warn (_("expression out of range: defaulting to 1"));
5361 offs (exp) = 1;
5362 }
5363 break;
5364 default:
5365 break;
5366 }
5367 }
5368 else if (exp->exp.X_op == O_big)
5369 {
5370 if (offs (exp) <= 0 /* flonum. */
5371 && (ok == 90 /* no bignums */
5372 || (ok > 10 /* Small-int ranges including 0 ok. */
5373 /* If we have a flonum zero, a zero integer should
5374 do as well (e.g., in moveq). */
5375 && generic_floating_point_number.exponent == 0
5376 && generic_floating_point_number.low[0] == 0)))
5377 {
5378 /* HACK! Turn it into a long. */
5379 LITTLENUM_TYPE words[6];
5380
5381 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5382 op (exp) = O_constant;
5383 adds (exp) = 0;
5384 subs (exp) = 0;
5385 offs (exp) = words[1] | (words[0] << 16);
5386 }
5387 else if (ok != 0)
5388 {
5389 op (exp) = O_constant;
5390 adds (exp) = 0;
5391 subs (exp) = 0;
5392 offs (exp) = (ok == 10) ? 1 : 0;
5393 as_warn (_("Can't deal with expression; defaulting to %ld"),
5394 (long) offs (exp));
5395 }
5396 }
5397 else
5398 {
5399 if (ok >= 10 && ok <= 80)
5400 {
5401 op (exp) = O_constant;
5402 adds (exp) = 0;
5403 subs (exp) = 0;
5404 offs (exp) = (ok == 10) ? 1 : 0;
5405 as_warn (_("Can't deal with expression; defaulting to %ld"),
5406 (long) offs (exp));
5407 }
5408 }
5409
5410 if (exp->size != SIZE_UNSPEC)
5411 {
5412 switch (exp->size)
5413 {
5414 case SIZE_UNSPEC:
5415 case SIZE_LONG:
5416 break;
5417 case SIZE_BYTE:
5418 if (!isbyte (offs (exp)))
5419 as_warn (_("expression doesn't fit in BYTE"));
5420 break;
5421 case SIZE_WORD:
5422 if (!isword (offs (exp)))
5423 as_warn (_("expression doesn't fit in WORD"));
5424 break;
5425 }
5426 }
5427
5428 return offs (exp);
5429 }
5430
5431 /* These are the back-ends for the various machine dependent pseudo-ops. */
5432
5433 static void
5434 s_data1 (int ignore ATTRIBUTE_UNUSED)
5435 {
5436 subseg_set (data_section, 1);
5437 demand_empty_rest_of_line ();
5438 }
5439
5440 static void
5441 s_data2 (int ignore ATTRIBUTE_UNUSED)
5442 {
5443 subseg_set (data_section, 2);
5444 demand_empty_rest_of_line ();
5445 }
5446
5447 static void
5448 s_bss (int ignore ATTRIBUTE_UNUSED)
5449 {
5450 /* We don't support putting frags in the BSS segment, we fake it
5451 by marking in_bss, then looking at s_skip for clues. */
5452
5453 subseg_set (bss_section, 0);
5454 demand_empty_rest_of_line ();
5455 }
5456
5457 static void
5458 s_even (int ignore ATTRIBUTE_UNUSED)
5459 {
5460 register int temp;
5461 register long temp_fill;
5462
5463 temp = 1; /* JF should be 2? */
5464 temp_fill = get_absolute_expression ();
5465 if (!need_pass_2) /* Never make frag if expect extra pass. */
5466 frag_align (temp, (int) temp_fill, 0);
5467 demand_empty_rest_of_line ();
5468 record_alignment (now_seg, temp);
5469 }
5470
5471 static void
5472 s_proc (int ignore ATTRIBUTE_UNUSED)
5473 {
5474 demand_empty_rest_of_line ();
5475 }
5476 \f
5477 /* Pseudo-ops handled for MRI compatibility. */
5478
5479 /* This function returns non-zero if the argument is a conditional
5480 pseudo-op. This is called when checking whether a pending
5481 alignment is needed. */
5482
5483 int
5484 m68k_conditional_pseudoop (pseudo_typeS *pop)
5485 {
5486 return (pop->poc_handler == s_mri_if
5487 || pop->poc_handler == s_mri_else);
5488 }
5489
5490 /* Handle an MRI style chip specification. */
5491
5492 static void
5493 mri_chip (void)
5494 {
5495 char *s;
5496 char c;
5497 int i;
5498
5499 s = input_line_pointer;
5500 /* We can't use get_symbol_end since the processor names are not proper
5501 symbols. */
5502 while (is_part_of_name (c = *input_line_pointer++))
5503 ;
5504 *--input_line_pointer = 0;
5505 for (i = 0; m68k_cpus[i].name; i++)
5506 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5507 break;
5508 if (!m68k_cpus[i].name)
5509 {
5510 as_bad (_("%s: unrecognized processor name"), s);
5511 *input_line_pointer = c;
5512 ignore_rest_of_line ();
5513 return;
5514 }
5515 *input_line_pointer = c;
5516
5517 if (*input_line_pointer == '/')
5518 current_architecture = 0;
5519 else
5520 current_architecture &= m68881 | m68851;
5521 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5522 control_regs = m68k_cpus[i].control_regs;
5523
5524 while (*input_line_pointer == '/')
5525 {
5526 ++input_line_pointer;
5527 s = input_line_pointer;
5528 /* We can't use get_symbol_end since the processor names are not
5529 proper symbols. */
5530 while (is_part_of_name (c = *input_line_pointer++))
5531 ;
5532 *--input_line_pointer = 0;
5533 if (strcmp (s, "68881") == 0)
5534 current_architecture |= m68881;
5535 else if (strcmp (s, "68851") == 0)
5536 current_architecture |= m68851;
5537 *input_line_pointer = c;
5538 }
5539 }
5540
5541 /* The MRI CHIP pseudo-op. */
5542
5543 static void
5544 s_chip (int ignore ATTRIBUTE_UNUSED)
5545 {
5546 char *stop = NULL;
5547 char stopc;
5548
5549 if (flag_mri)
5550 stop = mri_comment_field (&stopc);
5551 mri_chip ();
5552 if (flag_mri)
5553 mri_comment_end (stop, stopc);
5554 demand_empty_rest_of_line ();
5555 }
5556
5557 /* The MRI FOPT pseudo-op. */
5558
5559 static void
5560 s_fopt (int ignore ATTRIBUTE_UNUSED)
5561 {
5562 SKIP_WHITESPACE ();
5563
5564 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5565 {
5566 int temp;
5567
5568 input_line_pointer += 3;
5569 temp = get_absolute_expression ();
5570 if (temp < 0 || temp > 7)
5571 as_bad (_("bad coprocessor id"));
5572 else
5573 m68k_float_copnum = COP0 + temp;
5574 }
5575 else
5576 {
5577 as_bad (_("unrecognized fopt option"));
5578 ignore_rest_of_line ();
5579 return;
5580 }
5581
5582 demand_empty_rest_of_line ();
5583 }
5584
5585 /* The structure used to handle the MRI OPT pseudo-op. */
5586
5587 struct opt_action
5588 {
5589 /* The name of the option. */
5590 const char *name;
5591
5592 /* If this is not NULL, just call this function. The first argument
5593 is the ARG field of this structure, the second argument is
5594 whether the option was negated. */
5595 void (*pfn) (int arg, int on);
5596
5597 /* If this is not NULL, and the PFN field is NULL, set the variable
5598 this points to. Set it to the ARG field if the option was not
5599 negated, and the NOTARG field otherwise. */
5600 int *pvar;
5601
5602 /* The value to pass to PFN or to assign to *PVAR. */
5603 int arg;
5604
5605 /* The value to assign to *PVAR if the option is negated. If PFN is
5606 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5607 the option may not be negated. */
5608 int notarg;
5609 };
5610
5611 /* The table used to handle the MRI OPT pseudo-op. */
5612
5613 static void skip_to_comma (int, int);
5614 static void opt_nest (int, int);
5615 static void opt_chip (int, int);
5616 static void opt_list (int, int);
5617 static void opt_list_symbols (int, int);
5618
5619 static const struct opt_action opt_table[] =
5620 {
5621 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5622
5623 /* We do relaxing, so there is little use for these options. */
5624 { "b", 0, 0, 0, 0 },
5625 { "brs", 0, 0, 0, 0 },
5626 { "brb", 0, 0, 0, 0 },
5627 { "brl", 0, 0, 0, 0 },
5628 { "brw", 0, 0, 0, 0 },
5629
5630 { "c", 0, 0, 0, 0 },
5631 { "cex", 0, 0, 0, 0 },
5632 { "case", 0, &symbols_case_sensitive, 1, 0 },
5633 { "cl", 0, 0, 0, 0 },
5634 { "cre", 0, 0, 0, 0 },
5635 { "d", 0, &flag_keep_locals, 1, 0 },
5636 { "e", 0, 0, 0, 0 },
5637 { "f", 0, &flag_short_refs, 1, 0 },
5638 { "frs", 0, &flag_short_refs, 1, 0 },
5639 { "frl", 0, &flag_short_refs, 0, 1 },
5640 { "g", 0, 0, 0, 0 },
5641 { "i", 0, 0, 0, 0 },
5642 { "m", 0, 0, 0, 0 },
5643 { "mex", 0, 0, 0, 0 },
5644 { "mc", 0, 0, 0, 0 },
5645 { "md", 0, 0, 0, 0 },
5646 { "nest", opt_nest, 0, 0, 0 },
5647 { "next", skip_to_comma, 0, 0, 0 },
5648 { "o", 0, 0, 0, 0 },
5649 { "old", 0, 0, 0, 0 },
5650 { "op", skip_to_comma, 0, 0, 0 },
5651 { "pco", 0, 0, 0, 0 },
5652 { "p", opt_chip, 0, 0, 0 },
5653 { "pcr", 0, 0, 0, 0 },
5654 { "pcs", 0, 0, 0, 0 },
5655 { "r", 0, 0, 0, 0 },
5656 { "quick", 0, &m68k_quick, 1, 0 },
5657 { "rel32", 0, &m68k_rel32, 1, 0 },
5658 { "s", opt_list, 0, 0, 0 },
5659 { "t", opt_list_symbols, 0, 0, 0 },
5660 { "w", 0, &flag_no_warnings, 0, 1 },
5661 { "x", 0, 0, 0, 0 }
5662 };
5663
5664 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5665
5666 /* The MRI OPT pseudo-op. */
5667
5668 static void
5669 s_opt (int ignore ATTRIBUTE_UNUSED)
5670 {
5671 do
5672 {
5673 int t;
5674 char *s;
5675 char c;
5676 int i;
5677 const struct opt_action *o;
5678
5679 SKIP_WHITESPACE ();
5680
5681 t = 1;
5682 if (*input_line_pointer == '-')
5683 {
5684 ++input_line_pointer;
5685 t = 0;
5686 }
5687 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5688 {
5689 input_line_pointer += 2;
5690 t = 0;
5691 }
5692
5693 s = input_line_pointer;
5694 c = get_symbol_end ();
5695
5696 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5697 {
5698 if (strcasecmp (s, o->name) == 0)
5699 {
5700 if (o->pfn)
5701 {
5702 /* Restore input_line_pointer now in case the option
5703 takes arguments. */
5704 *input_line_pointer = c;
5705 (*o->pfn) (o->arg, t);
5706 }
5707 else if (o->pvar != NULL)
5708 {
5709 if (! t && o->arg == o->notarg)
5710 as_bad (_("option `%s' may not be negated"), s);
5711 *input_line_pointer = c;
5712 *o->pvar = t ? o->arg : o->notarg;
5713 }
5714 else
5715 *input_line_pointer = c;
5716 break;
5717 }
5718 }
5719 if (i >= OPTCOUNT)
5720 {
5721 as_bad (_("option `%s' not recognized"), s);
5722 *input_line_pointer = c;
5723 }
5724 }
5725 while (*input_line_pointer++ == ',');
5726
5727 /* Move back to terminating character. */
5728 --input_line_pointer;
5729 demand_empty_rest_of_line ();
5730 }
5731
5732 /* Skip ahead to a comma. This is used for OPT options which we do
5733 not support and which take arguments. */
5734
5735 static void
5736 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5737 {
5738 while (*input_line_pointer != ','
5739 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5740 ++input_line_pointer;
5741 }
5742
5743 /* Handle the OPT NEST=depth option. */
5744
5745 static void
5746 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5747 {
5748 if (*input_line_pointer != '=')
5749 {
5750 as_bad (_("bad format of OPT NEST=depth"));
5751 return;
5752 }
5753
5754 ++input_line_pointer;
5755 max_macro_nest = get_absolute_expression ();
5756 }
5757
5758 /* Handle the OPT P=chip option. */
5759
5760 static void
5761 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5762 {
5763 if (*input_line_pointer != '=')
5764 {
5765 /* This is just OPT P, which we do not support. */
5766 return;
5767 }
5768
5769 ++input_line_pointer;
5770 mri_chip ();
5771 }
5772
5773 /* Handle the OPT S option. */
5774
5775 static void
5776 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5777 {
5778 listing_list (on);
5779 }
5780
5781 /* Handle the OPT T option. */
5782
5783 static void
5784 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5785 {
5786 if (on)
5787 listing |= LISTING_SYMBOLS;
5788 else
5789 listing &= ~LISTING_SYMBOLS;
5790 }
5791
5792 /* Handle the MRI REG pseudo-op. */
5793
5794 static void
5795 s_reg (int ignore ATTRIBUTE_UNUSED)
5796 {
5797 char *s;
5798 int c;
5799 struct m68k_op rop;
5800 int mask;
5801 char *stop = NULL;
5802 char stopc;
5803
5804 if (line_label == NULL)
5805 {
5806 as_bad (_("missing label"));
5807 ignore_rest_of_line ();
5808 return;
5809 }
5810
5811 if (flag_mri)
5812 stop = mri_comment_field (&stopc);
5813
5814 SKIP_WHITESPACE ();
5815
5816 s = input_line_pointer;
5817 while (ISALNUM (*input_line_pointer)
5818 #ifdef REGISTER_PREFIX
5819 || *input_line_pointer == REGISTER_PREFIX
5820 #endif
5821 || *input_line_pointer == '/'
5822 || *input_line_pointer == '-')
5823 ++input_line_pointer;
5824 c = *input_line_pointer;
5825 *input_line_pointer = '\0';
5826
5827 if (m68k_ip_op (s, &rop) != 0)
5828 {
5829 if (rop.error == NULL)
5830 as_bad (_("bad register list"));
5831 else
5832 as_bad (_("bad register list: %s"), rop.error);
5833 *input_line_pointer = c;
5834 ignore_rest_of_line ();
5835 return;
5836 }
5837
5838 *input_line_pointer = c;
5839
5840 if (rop.mode == REGLST)
5841 mask = rop.mask;
5842 else if (rop.mode == DREG)
5843 mask = 1 << (rop.reg - DATA0);
5844 else if (rop.mode == AREG)
5845 mask = 1 << (rop.reg - ADDR0 + 8);
5846 else if (rop.mode == FPREG)
5847 mask = 1 << (rop.reg - FP0 + 16);
5848 else if (rop.mode == CONTROL
5849 && rop.reg == FPI)
5850 mask = 1 << 24;
5851 else if (rop.mode == CONTROL
5852 && rop.reg == FPS)
5853 mask = 1 << 25;
5854 else if (rop.mode == CONTROL
5855 && rop.reg == FPC)
5856 mask = 1 << 26;
5857 else
5858 {
5859 as_bad (_("bad register list"));
5860 ignore_rest_of_line ();
5861 return;
5862 }
5863
5864 S_SET_SEGMENT (line_label, reg_section);
5865 S_SET_VALUE (line_label, ~mask);
5866 symbol_set_frag (line_label, &zero_address_frag);
5867
5868 if (flag_mri)
5869 mri_comment_end (stop, stopc);
5870
5871 demand_empty_rest_of_line ();
5872 }
5873
5874 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5875
5876 struct save_opts
5877 {
5878 struct save_opts *next;
5879 int abspcadd;
5880 int symbols_case_sensitive;
5881 int keep_locals;
5882 int short_refs;
5883 int architecture;
5884 const enum m68k_register *control_regs;
5885 int quick;
5886 int rel32;
5887 int listing;
5888 int no_warnings;
5889 /* FIXME: We don't save OPT S. */
5890 };
5891
5892 /* This variable holds the stack of saved options. */
5893
5894 static struct save_opts *save_stack;
5895
5896 /* The MRI SAVE pseudo-op. */
5897
5898 static void
5899 s_save (int ignore ATTRIBUTE_UNUSED)
5900 {
5901 struct save_opts *s;
5902
5903 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5904 s->abspcadd = m68k_abspcadd;
5905 s->symbols_case_sensitive = symbols_case_sensitive;
5906 s->keep_locals = flag_keep_locals;
5907 s->short_refs = flag_short_refs;
5908 s->architecture = current_architecture;
5909 s->control_regs = control_regs;
5910 s->quick = m68k_quick;
5911 s->rel32 = m68k_rel32;
5912 s->listing = listing;
5913 s->no_warnings = flag_no_warnings;
5914
5915 s->next = save_stack;
5916 save_stack = s;
5917
5918 demand_empty_rest_of_line ();
5919 }
5920
5921 /* The MRI RESTORE pseudo-op. */
5922
5923 static void
5924 s_restore (int ignore ATTRIBUTE_UNUSED)
5925 {
5926 struct save_opts *s;
5927
5928 if (save_stack == NULL)
5929 {
5930 as_bad (_("restore without save"));
5931 ignore_rest_of_line ();
5932 return;
5933 }
5934
5935 s = save_stack;
5936 save_stack = s->next;
5937
5938 m68k_abspcadd = s->abspcadd;
5939 symbols_case_sensitive = s->symbols_case_sensitive;
5940 flag_keep_locals = s->keep_locals;
5941 flag_short_refs = s->short_refs;
5942 current_architecture = s->architecture;
5943 control_regs = s->control_regs;
5944 m68k_quick = s->quick;
5945 m68k_rel32 = s->rel32;
5946 listing = s->listing;
5947 flag_no_warnings = s->no_warnings;
5948
5949 free (s);
5950
5951 demand_empty_rest_of_line ();
5952 }
5953
5954 /* Types of MRI structured control directives. */
5955
5956 enum mri_control_type
5957 {
5958 mri_for,
5959 mri_if,
5960 mri_repeat,
5961 mri_while
5962 };
5963
5964 /* This structure is used to stack the MRI structured control
5965 directives. */
5966
5967 struct mri_control_info
5968 {
5969 /* The directive within which this one is enclosed. */
5970 struct mri_control_info *outer;
5971
5972 /* The type of directive. */
5973 enum mri_control_type type;
5974
5975 /* Whether an ELSE has been in an IF. */
5976 int else_seen;
5977
5978 /* The add or sub statement at the end of a FOR. */
5979 char *incr;
5980
5981 /* The label of the top of a FOR or REPEAT loop. */
5982 char *top;
5983
5984 /* The label to jump to for the next iteration, or the else
5985 expression of a conditional. */
5986 char *next;
5987
5988 /* The label to jump to to break out of the loop, or the label past
5989 the end of a conditional. */
5990 char *bottom;
5991 };
5992
5993 /* The stack of MRI structured control directives. */
5994
5995 static struct mri_control_info *mri_control_stack;
5996
5997 /* The current MRI structured control directive index number, used to
5998 generate label names. */
5999
6000 static int mri_control_index;
6001
6002 /* Assemble an instruction for an MRI structured control directive. */
6003
6004 static void
6005 mri_assemble (char *str)
6006 {
6007 char *s;
6008
6009 /* md_assemble expects the opcode to be in lower case. */
6010 for (s = str; *s != ' ' && *s != '\0'; s++)
6011 *s = TOLOWER (*s);
6012
6013 md_assemble (str);
6014 }
6015
6016 /* Generate a new MRI label structured control directive label name. */
6017
6018 static char *
6019 mri_control_label (void)
6020 {
6021 char *n;
6022
6023 n = (char *) xmalloc (20);
6024 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6025 ++mri_control_index;
6026 return n;
6027 }
6028
6029 /* Create a new MRI structured control directive. */
6030
6031 static struct mri_control_info *
6032 push_mri_control (enum mri_control_type type)
6033 {
6034 struct mri_control_info *n;
6035
6036 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6037
6038 n->type = type;
6039 n->else_seen = 0;
6040 if (type == mri_if || type == mri_while)
6041 n->top = NULL;
6042 else
6043 n->top = mri_control_label ();
6044 n->next = mri_control_label ();
6045 n->bottom = mri_control_label ();
6046
6047 n->outer = mri_control_stack;
6048 mri_control_stack = n;
6049
6050 return n;
6051 }
6052
6053 /* Pop off the stack of MRI structured control directives. */
6054
6055 static void
6056 pop_mri_control (void)
6057 {
6058 struct mri_control_info *n;
6059
6060 n = mri_control_stack;
6061 mri_control_stack = n->outer;
6062 if (n->top != NULL)
6063 free (n->top);
6064 free (n->next);
6065 free (n->bottom);
6066 free (n);
6067 }
6068
6069 /* Recognize a condition code in an MRI structured control expression. */
6070
6071 static int
6072 parse_mri_condition (int *pcc)
6073 {
6074 char c1, c2;
6075
6076 know (*input_line_pointer == '<');
6077
6078 ++input_line_pointer;
6079 c1 = *input_line_pointer++;
6080 c2 = *input_line_pointer++;
6081
6082 if (*input_line_pointer != '>')
6083 {
6084 as_bad (_("syntax error in structured control directive"));
6085 return 0;
6086 }
6087
6088 ++input_line_pointer;
6089 SKIP_WHITESPACE ();
6090
6091 c1 = TOLOWER (c1);
6092 c2 = TOLOWER (c2);
6093
6094 *pcc = (c1 << 8) | c2;
6095
6096 return 1;
6097 }
6098
6099 /* Parse a single operand in an MRI structured control expression. */
6100
6101 static int
6102 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6103 char **rightstart, char **rightstop)
6104 {
6105 char *s;
6106
6107 SKIP_WHITESPACE ();
6108
6109 *pcc = -1;
6110 *leftstart = NULL;
6111 *leftstop = NULL;
6112 *rightstart = NULL;
6113 *rightstop = NULL;
6114
6115 if (*input_line_pointer == '<')
6116 {
6117 /* It's just a condition code. */
6118 return parse_mri_condition (pcc);
6119 }
6120
6121 /* Look ahead for the condition code. */
6122 for (s = input_line_pointer; *s != '\0'; ++s)
6123 {
6124 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6125 break;
6126 }
6127 if (*s == '\0')
6128 {
6129 as_bad (_("missing condition code in structured control directive"));
6130 return 0;
6131 }
6132
6133 *leftstart = input_line_pointer;
6134 *leftstop = s;
6135 if (*leftstop > *leftstart
6136 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6137 --*leftstop;
6138
6139 input_line_pointer = s;
6140 if (! parse_mri_condition (pcc))
6141 return 0;
6142
6143 /* Look ahead for AND or OR or end of line. */
6144 for (s = input_line_pointer; *s != '\0'; ++s)
6145 {
6146 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6147 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6148 ^^^ ^^ */
6149 if ((s == input_line_pointer
6150 || *(s-1) == ' '
6151 || *(s-1) == '\t')
6152 && ((strncasecmp (s, "AND", 3) == 0
6153 && (s[3] == '.' || ! is_part_of_name (s[3])))
6154 || (strncasecmp (s, "OR", 2) == 0
6155 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6156 break;
6157 }
6158
6159 *rightstart = input_line_pointer;
6160 *rightstop = s;
6161 if (*rightstop > *rightstart
6162 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6163 --*rightstop;
6164
6165 input_line_pointer = s;
6166
6167 return 1;
6168 }
6169
6170 #define MCC(b1, b2) (((b1) << 8) | (b2))
6171
6172 /* Swap the sense of a condition. This changes the condition so that
6173 it generates the same result when the operands are swapped. */
6174
6175 static int
6176 swap_mri_condition (int cc)
6177 {
6178 switch (cc)
6179 {
6180 case MCC ('h', 'i'): return MCC ('c', 's');
6181 case MCC ('l', 's'): return MCC ('c', 'c');
6182 /* <HS> is an alias for <CC>. */
6183 case MCC ('h', 's'):
6184 case MCC ('c', 'c'): return MCC ('l', 's');
6185 /* <LO> is an alias for <CS>. */
6186 case MCC ('l', 'o'):
6187 case MCC ('c', 's'): return MCC ('h', 'i');
6188 case MCC ('p', 'l'): return MCC ('m', 'i');
6189 case MCC ('m', 'i'): return MCC ('p', 'l');
6190 case MCC ('g', 'e'): return MCC ('l', 'e');
6191 case MCC ('l', 't'): return MCC ('g', 't');
6192 case MCC ('g', 't'): return MCC ('l', 't');
6193 case MCC ('l', 'e'): return MCC ('g', 'e');
6194 /* Issue a warning for conditions we can not swap. */
6195 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6196 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6197 case MCC ('v', 'c'):
6198 case MCC ('v', 's'):
6199 default :
6200 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6201 (char) (cc >> 8), (char) (cc));
6202 break;
6203 }
6204 return cc;
6205 }
6206
6207 /* Reverse the sense of a condition. */
6208
6209 static int
6210 reverse_mri_condition (int cc)
6211 {
6212 switch (cc)
6213 {
6214 case MCC ('h', 'i'): return MCC ('l', 's');
6215 case MCC ('l', 's'): return MCC ('h', 'i');
6216 /* <HS> is an alias for <CC> */
6217 case MCC ('h', 's'): return MCC ('l', 'o');
6218 case MCC ('c', 'c'): return MCC ('c', 's');
6219 /* <LO> is an alias for <CS> */
6220 case MCC ('l', 'o'): return MCC ('h', 's');
6221 case MCC ('c', 's'): return MCC ('c', 'c');
6222 case MCC ('n', 'e'): return MCC ('e', 'q');
6223 case MCC ('e', 'q'): return MCC ('n', 'e');
6224 case MCC ('v', 'c'): return MCC ('v', 's');
6225 case MCC ('v', 's'): return MCC ('v', 'c');
6226 case MCC ('p', 'l'): return MCC ('m', 'i');
6227 case MCC ('m', 'i'): return MCC ('p', 'l');
6228 case MCC ('g', 'e'): return MCC ('l', 't');
6229 case MCC ('l', 't'): return MCC ('g', 'e');
6230 case MCC ('g', 't'): return MCC ('l', 'e');
6231 case MCC ('l', 'e'): return MCC ('g', 't');
6232 }
6233 return cc;
6234 }
6235
6236 /* Build an MRI structured control expression. This generates test
6237 and branch instructions. It goes to TRUELAB if the condition is
6238 true, and to FALSELAB if the condition is false. Exactly one of
6239 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6240 is the size qualifier for the expression. EXTENT is the size to
6241 use for the branch. */
6242
6243 static void
6244 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6245 char *rightstart, char *rightstop,
6246 const char *truelab, const char *falselab,
6247 int extent)
6248 {
6249 char *buf;
6250 char *s;
6251
6252 if (leftstart != NULL)
6253 {
6254 struct m68k_op leftop, rightop;
6255 char c;
6256
6257 /* Swap the compare operands, if necessary, to produce a legal
6258 m68k compare instruction. Comparing a register operand with
6259 a non-register operand requires the register to be on the
6260 right (cmp, cmpa). Comparing an immediate value with
6261 anything requires the immediate value to be on the left
6262 (cmpi). */
6263
6264 c = *leftstop;
6265 *leftstop = '\0';
6266 (void) m68k_ip_op (leftstart, &leftop);
6267 *leftstop = c;
6268
6269 c = *rightstop;
6270 *rightstop = '\0';
6271 (void) m68k_ip_op (rightstart, &rightop);
6272 *rightstop = c;
6273
6274 if (rightop.mode == IMMED
6275 || ((leftop.mode == DREG || leftop.mode == AREG)
6276 && (rightop.mode != DREG && rightop.mode != AREG)))
6277 {
6278 char *temp;
6279
6280 /* Correct conditional handling:
6281 if #1 <lt> d0 then ;means if (1 < d0)
6282 ...
6283 endi
6284
6285 should assemble to:
6286
6287 cmp #1,d0 if we do *not* swap the operands
6288 bgt true we need the swapped condition!
6289 ble false
6290 true:
6291 ...
6292 false:
6293 */
6294 temp = leftstart;
6295 leftstart = rightstart;
6296 rightstart = temp;
6297 temp = leftstop;
6298 leftstop = rightstop;
6299 rightstop = temp;
6300 }
6301 else
6302 {
6303 cc = swap_mri_condition (cc);
6304 }
6305 }
6306
6307 if (truelab == NULL)
6308 {
6309 cc = reverse_mri_condition (cc);
6310 truelab = falselab;
6311 }
6312
6313 if (leftstart != NULL)
6314 {
6315 buf = (char *) xmalloc (20
6316 + (leftstop - leftstart)
6317 + (rightstop - rightstart));
6318 s = buf;
6319 *s++ = 'c';
6320 *s++ = 'm';
6321 *s++ = 'p';
6322 if (qual != '\0')
6323 *s++ = TOLOWER (qual);
6324 *s++ = ' ';
6325 memcpy (s, leftstart, leftstop - leftstart);
6326 s += leftstop - leftstart;
6327 *s++ = ',';
6328 memcpy (s, rightstart, rightstop - rightstart);
6329 s += rightstop - rightstart;
6330 *s = '\0';
6331 mri_assemble (buf);
6332 free (buf);
6333 }
6334
6335 buf = (char *) xmalloc (20 + strlen (truelab));
6336 s = buf;
6337 *s++ = 'b';
6338 *s++ = cc >> 8;
6339 *s++ = cc & 0xff;
6340 if (extent != '\0')
6341 *s++ = TOLOWER (extent);
6342 *s++ = ' ';
6343 strcpy (s, truelab);
6344 mri_assemble (buf);
6345 free (buf);
6346 }
6347
6348 /* Parse an MRI structured control expression. This generates test
6349 and branch instructions. STOP is where the expression ends. It
6350 goes to TRUELAB if the condition is true, and to FALSELAB if the
6351 condition is false. Exactly one of TRUELAB and FALSELAB will be
6352 NULL, meaning to fall through. QUAL is the size qualifier for the
6353 expression. EXTENT is the size to use for the branch. */
6354
6355 static void
6356 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6357 const char *falselab, int extent)
6358 {
6359 int c;
6360 int cc;
6361 char *leftstart;
6362 char *leftstop;
6363 char *rightstart;
6364 char *rightstop;
6365
6366 c = *stop;
6367 *stop = '\0';
6368
6369 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6370 &rightstart, &rightstop))
6371 {
6372 *stop = c;
6373 return;
6374 }
6375
6376 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6377 {
6378 const char *flab;
6379
6380 if (falselab != NULL)
6381 flab = falselab;
6382 else
6383 flab = mri_control_label ();
6384
6385 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6386 rightstop, (const char *) NULL, flab, extent);
6387
6388 input_line_pointer += 3;
6389 if (*input_line_pointer != '.'
6390 || input_line_pointer[1] == '\0')
6391 qual = '\0';
6392 else
6393 {
6394 qual = input_line_pointer[1];
6395 input_line_pointer += 2;
6396 }
6397
6398 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6399 &rightstart, &rightstop))
6400 {
6401 *stop = c;
6402 return;
6403 }
6404
6405 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6406 rightstop, truelab, falselab, extent);
6407
6408 if (falselab == NULL)
6409 colon (flab);
6410 }
6411 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6412 {
6413 const char *tlab;
6414
6415 if (truelab != NULL)
6416 tlab = truelab;
6417 else
6418 tlab = mri_control_label ();
6419
6420 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6421 rightstop, tlab, (const char *) NULL, extent);
6422
6423 input_line_pointer += 2;
6424 if (*input_line_pointer != '.'
6425 || input_line_pointer[1] == '\0')
6426 qual = '\0';
6427 else
6428 {
6429 qual = input_line_pointer[1];
6430 input_line_pointer += 2;
6431 }
6432
6433 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6434 &rightstart, &rightstop))
6435 {
6436 *stop = c;
6437 return;
6438 }
6439
6440 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6441 rightstop, truelab, falselab, extent);
6442
6443 if (truelab == NULL)
6444 colon (tlab);
6445 }
6446 else
6447 {
6448 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6449 rightstop, truelab, falselab, extent);
6450 }
6451
6452 *stop = c;
6453 if (input_line_pointer != stop)
6454 as_bad (_("syntax error in structured control directive"));
6455 }
6456
6457 /* Handle the MRI IF pseudo-op. This may be a structured control
6458 directive, or it may be a regular assembler conditional, depending
6459 on its operands. */
6460
6461 static void
6462 s_mri_if (int qual)
6463 {
6464 char *s;
6465 int c;
6466 struct mri_control_info *n;
6467
6468 /* A structured control directive must end with THEN with an
6469 optional qualifier. */
6470 s = input_line_pointer;
6471 /* We only accept '*' as introduction of comments if preceded by white space
6472 or at first column of a line (I think this can't actually happen here?)
6473 This is important when assembling:
6474 if d0 <ne> 12(a0,d0*2) then
6475 if d0 <ne> #CONST*20 then. */
6476 while (! (is_end_of_line[(unsigned char) *s]
6477 || (flag_mri
6478 && *s == '*'
6479 && (s == input_line_pointer
6480 || *(s-1) == ' '
6481 || *(s-1) == '\t'))))
6482 ++s;
6483 --s;
6484 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6485 --s;
6486
6487 if (s - input_line_pointer > 1
6488 && s[-1] == '.')
6489 s -= 2;
6490
6491 if (s - input_line_pointer < 3
6492 || strncasecmp (s - 3, "THEN", 4) != 0)
6493 {
6494 if (qual != '\0')
6495 {
6496 as_bad (_("missing then"));
6497 ignore_rest_of_line ();
6498 return;
6499 }
6500
6501 /* It's a conditional. */
6502 s_if (O_ne);
6503 return;
6504 }
6505
6506 /* Since this might be a conditional if, this pseudo-op will be
6507 called even if we are supported to be ignoring input. Double
6508 check now. Clobber *input_line_pointer so that ignore_input
6509 thinks that this is not a special pseudo-op. */
6510 c = *input_line_pointer;
6511 *input_line_pointer = 0;
6512 if (ignore_input ())
6513 {
6514 *input_line_pointer = c;
6515 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6516 ++input_line_pointer;
6517 demand_empty_rest_of_line ();
6518 return;
6519 }
6520 *input_line_pointer = c;
6521
6522 n = push_mri_control (mri_if);
6523
6524 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6525 n->next, s[1] == '.' ? s[2] : '\0');
6526
6527 if (s[1] == '.')
6528 input_line_pointer = s + 3;
6529 else
6530 input_line_pointer = s + 1;
6531
6532 if (flag_mri)
6533 {
6534 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6535 ++input_line_pointer;
6536 }
6537
6538 demand_empty_rest_of_line ();
6539 }
6540
6541 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6542 structured IF, associate the ELSE with the IF. Otherwise, assume
6543 it is a conditional else. */
6544
6545 static void
6546 s_mri_else (int qual)
6547 {
6548 int c;
6549 char *buf;
6550 char q[2];
6551
6552 if (qual == '\0'
6553 && (mri_control_stack == NULL
6554 || mri_control_stack->type != mri_if
6555 || mri_control_stack->else_seen))
6556 {
6557 s_else (0);
6558 return;
6559 }
6560
6561 c = *input_line_pointer;
6562 *input_line_pointer = 0;
6563 if (ignore_input ())
6564 {
6565 *input_line_pointer = c;
6566 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6567 ++input_line_pointer;
6568 demand_empty_rest_of_line ();
6569 return;
6570 }
6571 *input_line_pointer = c;
6572
6573 if (mri_control_stack == NULL
6574 || mri_control_stack->type != mri_if
6575 || mri_control_stack->else_seen)
6576 {
6577 as_bad (_("else without matching if"));
6578 ignore_rest_of_line ();
6579 return;
6580 }
6581
6582 mri_control_stack->else_seen = 1;
6583
6584 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6585 q[0] = TOLOWER (qual);
6586 q[1] = '\0';
6587 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6588 mri_assemble (buf);
6589 free (buf);
6590
6591 colon (mri_control_stack->next);
6592
6593 if (flag_mri)
6594 {
6595 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6596 ++input_line_pointer;
6597 }
6598
6599 demand_empty_rest_of_line ();
6600 }
6601
6602 /* Handle the MRI ENDI pseudo-op. */
6603
6604 static void
6605 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6606 {
6607 if (mri_control_stack == NULL
6608 || mri_control_stack->type != mri_if)
6609 {
6610 as_bad (_("endi without matching if"));
6611 ignore_rest_of_line ();
6612 return;
6613 }
6614
6615 /* ignore_input will not return true for ENDI, so we don't need to
6616 worry about checking it again here. */
6617
6618 if (! mri_control_stack->else_seen)
6619 colon (mri_control_stack->next);
6620 colon (mri_control_stack->bottom);
6621
6622 pop_mri_control ();
6623
6624 if (flag_mri)
6625 {
6626 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6627 ++input_line_pointer;
6628 }
6629
6630 demand_empty_rest_of_line ();
6631 }
6632
6633 /* Handle the MRI BREAK pseudo-op. */
6634
6635 static void
6636 s_mri_break (int extent)
6637 {
6638 struct mri_control_info *n;
6639 char *buf;
6640 char ex[2];
6641
6642 n = mri_control_stack;
6643 while (n != NULL
6644 && n->type != mri_for
6645 && n->type != mri_repeat
6646 && n->type != mri_while)
6647 n = n->outer;
6648 if (n == NULL)
6649 {
6650 as_bad (_("break outside of structured loop"));
6651 ignore_rest_of_line ();
6652 return;
6653 }
6654
6655 buf = (char *) xmalloc (20 + strlen (n->bottom));
6656 ex[0] = TOLOWER (extent);
6657 ex[1] = '\0';
6658 sprintf (buf, "bra%s %s", ex, n->bottom);
6659 mri_assemble (buf);
6660 free (buf);
6661
6662 if (flag_mri)
6663 {
6664 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6665 ++input_line_pointer;
6666 }
6667
6668 demand_empty_rest_of_line ();
6669 }
6670
6671 /* Handle the MRI NEXT pseudo-op. */
6672
6673 static void
6674 s_mri_next (int extent)
6675 {
6676 struct mri_control_info *n;
6677 char *buf;
6678 char ex[2];
6679
6680 n = mri_control_stack;
6681 while (n != NULL
6682 && n->type != mri_for
6683 && n->type != mri_repeat
6684 && n->type != mri_while)
6685 n = n->outer;
6686 if (n == NULL)
6687 {
6688 as_bad (_("next outside of structured loop"));
6689 ignore_rest_of_line ();
6690 return;
6691 }
6692
6693 buf = (char *) xmalloc (20 + strlen (n->next));
6694 ex[0] = TOLOWER (extent);
6695 ex[1] = '\0';
6696 sprintf (buf, "bra%s %s", ex, n->next);
6697 mri_assemble (buf);
6698 free (buf);
6699
6700 if (flag_mri)
6701 {
6702 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6703 ++input_line_pointer;
6704 }
6705
6706 demand_empty_rest_of_line ();
6707 }
6708
6709 /* Handle the MRI FOR pseudo-op. */
6710
6711 static void
6712 s_mri_for (int qual)
6713 {
6714 const char *varstart, *varstop;
6715 const char *initstart, *initstop;
6716 const char *endstart, *endstop;
6717 const char *bystart, *bystop;
6718 int up;
6719 int by;
6720 int extent;
6721 struct mri_control_info *n;
6722 char *buf;
6723 char *s;
6724 char ex[2];
6725
6726 /* The syntax is
6727 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6728 */
6729
6730 SKIP_WHITESPACE ();
6731 varstart = input_line_pointer;
6732
6733 /* Look for the '='. */
6734 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6735 && *input_line_pointer != '=')
6736 ++input_line_pointer;
6737 if (*input_line_pointer != '=')
6738 {
6739 as_bad (_("missing ="));
6740 ignore_rest_of_line ();
6741 return;
6742 }
6743
6744 varstop = input_line_pointer;
6745 if (varstop > varstart
6746 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6747 --varstop;
6748
6749 ++input_line_pointer;
6750
6751 initstart = input_line_pointer;
6752
6753 /* Look for TO or DOWNTO. */
6754 up = 1;
6755 initstop = NULL;
6756 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6757 {
6758 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6759 && ! is_part_of_name (input_line_pointer[2]))
6760 {
6761 initstop = input_line_pointer;
6762 input_line_pointer += 2;
6763 break;
6764 }
6765 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6766 && ! is_part_of_name (input_line_pointer[6]))
6767 {
6768 initstop = input_line_pointer;
6769 up = 0;
6770 input_line_pointer += 6;
6771 break;
6772 }
6773 ++input_line_pointer;
6774 }
6775 if (initstop == NULL)
6776 {
6777 as_bad (_("missing to or downto"));
6778 ignore_rest_of_line ();
6779 return;
6780 }
6781 if (initstop > initstart
6782 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6783 --initstop;
6784
6785 SKIP_WHITESPACE ();
6786 endstart = input_line_pointer;
6787
6788 /* Look for BY or DO. */
6789 by = 0;
6790 endstop = NULL;
6791 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6792 {
6793 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6794 && ! is_part_of_name (input_line_pointer[2]))
6795 {
6796 endstop = input_line_pointer;
6797 by = 1;
6798 input_line_pointer += 2;
6799 break;
6800 }
6801 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6802 && (input_line_pointer[2] == '.'
6803 || ! is_part_of_name (input_line_pointer[2])))
6804 {
6805 endstop = input_line_pointer;
6806 input_line_pointer += 2;
6807 break;
6808 }
6809 ++input_line_pointer;
6810 }
6811 if (endstop == NULL)
6812 {
6813 as_bad (_("missing do"));
6814 ignore_rest_of_line ();
6815 return;
6816 }
6817 if (endstop > endstart
6818 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6819 --endstop;
6820
6821 if (! by)
6822 {
6823 bystart = "#1";
6824 bystop = bystart + 2;
6825 }
6826 else
6827 {
6828 SKIP_WHITESPACE ();
6829 bystart = input_line_pointer;
6830
6831 /* Look for DO. */
6832 bystop = NULL;
6833 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6834 {
6835 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6836 && (input_line_pointer[2] == '.'
6837 || ! is_part_of_name (input_line_pointer[2])))
6838 {
6839 bystop = input_line_pointer;
6840 input_line_pointer += 2;
6841 break;
6842 }
6843 ++input_line_pointer;
6844 }
6845 if (bystop == NULL)
6846 {
6847 as_bad (_("missing do"));
6848 ignore_rest_of_line ();
6849 return;
6850 }
6851 if (bystop > bystart
6852 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6853 --bystop;
6854 }
6855
6856 if (*input_line_pointer != '.')
6857 extent = '\0';
6858 else
6859 {
6860 extent = input_line_pointer[1];
6861 input_line_pointer += 2;
6862 }
6863
6864 /* We have fully parsed the FOR operands. Now build the loop. */
6865 n = push_mri_control (mri_for);
6866
6867 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6868
6869 /* Move init,var. */
6870 s = buf;
6871 *s++ = 'm';
6872 *s++ = 'o';
6873 *s++ = 'v';
6874 *s++ = 'e';
6875 if (qual != '\0')
6876 *s++ = TOLOWER (qual);
6877 *s++ = ' ';
6878 memcpy (s, initstart, initstop - initstart);
6879 s += initstop - initstart;
6880 *s++ = ',';
6881 memcpy (s, varstart, varstop - varstart);
6882 s += varstop - varstart;
6883 *s = '\0';
6884 mri_assemble (buf);
6885
6886 colon (n->top);
6887
6888 /* cmp end,var. */
6889 s = buf;
6890 *s++ = 'c';
6891 *s++ = 'm';
6892 *s++ = 'p';
6893 if (qual != '\0')
6894 *s++ = TOLOWER (qual);
6895 *s++ = ' ';
6896 memcpy (s, endstart, endstop - endstart);
6897 s += endstop - endstart;
6898 *s++ = ',';
6899 memcpy (s, varstart, varstop - varstart);
6900 s += varstop - varstart;
6901 *s = '\0';
6902 mri_assemble (buf);
6903
6904 /* bcc bottom. */
6905 ex[0] = TOLOWER (extent);
6906 ex[1] = '\0';
6907 if (up)
6908 sprintf (buf, "blt%s %s", ex, n->bottom);
6909 else
6910 sprintf (buf, "bgt%s %s", ex, n->bottom);
6911 mri_assemble (buf);
6912
6913 /* Put together the add or sub instruction used by ENDF. */
6914 s = buf;
6915 if (up)
6916 strcpy (s, "add");
6917 else
6918 strcpy (s, "sub");
6919 s += 3;
6920 if (qual != '\0')
6921 *s++ = TOLOWER (qual);
6922 *s++ = ' ';
6923 memcpy (s, bystart, bystop - bystart);
6924 s += bystop - bystart;
6925 *s++ = ',';
6926 memcpy (s, varstart, varstop - varstart);
6927 s += varstop - varstart;
6928 *s = '\0';
6929 n->incr = buf;
6930
6931 if (flag_mri)
6932 {
6933 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6934 ++input_line_pointer;
6935 }
6936
6937 demand_empty_rest_of_line ();
6938 }
6939
6940 /* Handle the MRI ENDF pseudo-op. */
6941
6942 static void
6943 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6944 {
6945 if (mri_control_stack == NULL
6946 || mri_control_stack->type != mri_for)
6947 {
6948 as_bad (_("endf without for"));
6949 ignore_rest_of_line ();
6950 return;
6951 }
6952
6953 colon (mri_control_stack->next);
6954
6955 mri_assemble (mri_control_stack->incr);
6956
6957 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6958 mri_assemble (mri_control_stack->incr);
6959
6960 free (mri_control_stack->incr);
6961
6962 colon (mri_control_stack->bottom);
6963
6964 pop_mri_control ();
6965
6966 if (flag_mri)
6967 {
6968 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6969 ++input_line_pointer;
6970 }
6971
6972 demand_empty_rest_of_line ();
6973 }
6974
6975 /* Handle the MRI REPEAT pseudo-op. */
6976
6977 static void
6978 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6979 {
6980 struct mri_control_info *n;
6981
6982 n = push_mri_control (mri_repeat);
6983 colon (n->top);
6984 if (flag_mri)
6985 {
6986 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6987 ++input_line_pointer;
6988 }
6989 demand_empty_rest_of_line ();
6990 }
6991
6992 /* Handle the MRI UNTIL pseudo-op. */
6993
6994 static void
6995 s_mri_until (int qual)
6996 {
6997 char *s;
6998
6999 if (mri_control_stack == NULL
7000 || mri_control_stack->type != mri_repeat)
7001 {
7002 as_bad (_("until without repeat"));
7003 ignore_rest_of_line ();
7004 return;
7005 }
7006
7007 colon (mri_control_stack->next);
7008
7009 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7010 ;
7011
7012 parse_mri_control_expression (s, qual, (const char *) NULL,
7013 mri_control_stack->top, '\0');
7014
7015 colon (mri_control_stack->bottom);
7016
7017 input_line_pointer = s;
7018
7019 pop_mri_control ();
7020
7021 if (flag_mri)
7022 {
7023 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7024 ++input_line_pointer;
7025 }
7026
7027 demand_empty_rest_of_line ();
7028 }
7029
7030 /* Handle the MRI WHILE pseudo-op. */
7031
7032 static void
7033 s_mri_while (int qual)
7034 {
7035 char *s;
7036
7037 struct mri_control_info *n;
7038
7039 s = input_line_pointer;
7040 /* We only accept '*' as introduction of comments if preceded by white space
7041 or at first column of a line (I think this can't actually happen here?)
7042 This is important when assembling:
7043 while d0 <ne> 12(a0,d0*2) do
7044 while d0 <ne> #CONST*20 do. */
7045 while (! (is_end_of_line[(unsigned char) *s]
7046 || (flag_mri
7047 && *s == '*'
7048 && (s == input_line_pointer
7049 || *(s-1) == ' '
7050 || *(s-1) == '\t'))))
7051 s++;
7052 --s;
7053 while (*s == ' ' || *s == '\t')
7054 --s;
7055 if (s - input_line_pointer > 1
7056 && s[-1] == '.')
7057 s -= 2;
7058 if (s - input_line_pointer < 2
7059 || strncasecmp (s - 1, "DO", 2) != 0)
7060 {
7061 as_bad (_("missing do"));
7062 ignore_rest_of_line ();
7063 return;
7064 }
7065
7066 n = push_mri_control (mri_while);
7067
7068 colon (n->next);
7069
7070 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7071 s[1] == '.' ? s[2] : '\0');
7072
7073 input_line_pointer = s + 1;
7074 if (*input_line_pointer == '.')
7075 input_line_pointer += 2;
7076
7077 if (flag_mri)
7078 {
7079 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7080 ++input_line_pointer;
7081 }
7082
7083 demand_empty_rest_of_line ();
7084 }
7085
7086 /* Handle the MRI ENDW pseudo-op. */
7087
7088 static void
7089 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7090 {
7091 char *buf;
7092
7093 if (mri_control_stack == NULL
7094 || mri_control_stack->type != mri_while)
7095 {
7096 as_bad (_("endw without while"));
7097 ignore_rest_of_line ();
7098 return;
7099 }
7100
7101 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7102 sprintf (buf, "bra %s", mri_control_stack->next);
7103 mri_assemble (buf);
7104 free (buf);
7105
7106 colon (mri_control_stack->bottom);
7107
7108 pop_mri_control ();
7109
7110 if (flag_mri)
7111 {
7112 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7113 ++input_line_pointer;
7114 }
7115
7116 demand_empty_rest_of_line ();
7117 }
7118 \f
7119 /* Parse a .cpu directive. */
7120
7121 static void
7122 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7123 {
7124 char saved_char;
7125 char *name;
7126
7127 if (initialized)
7128 {
7129 as_bad (_("already assembled instructions"));
7130 ignore_rest_of_line ();
7131 return;
7132 }
7133
7134 name = input_line_pointer;
7135 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7136 input_line_pointer++;
7137 saved_char = *input_line_pointer;
7138 *input_line_pointer = 0;
7139
7140 m68k_set_cpu (name, 1, 0);
7141
7142 *input_line_pointer = saved_char;
7143 demand_empty_rest_of_line ();
7144 return;
7145 }
7146
7147 /* Parse a .arch directive. */
7148
7149 static void
7150 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7151 {
7152 char saved_char;
7153 char *name;
7154
7155 if (initialized)
7156 {
7157 as_bad (_("already assembled instructions"));
7158 ignore_rest_of_line ();
7159 return;
7160 }
7161
7162 name = input_line_pointer;
7163 while (*input_line_pointer && *input_line_pointer != ','
7164 && !ISSPACE (*input_line_pointer))
7165 input_line_pointer++;
7166 saved_char = *input_line_pointer;
7167 *input_line_pointer = 0;
7168
7169 if (m68k_set_arch (name, 1, 0))
7170 {
7171 /* Scan extensions. */
7172 do
7173 {
7174 *input_line_pointer++ = saved_char;
7175 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7176 break;
7177 name = input_line_pointer;
7178 while (*input_line_pointer && *input_line_pointer != ','
7179 && !ISSPACE (*input_line_pointer))
7180 input_line_pointer++;
7181 saved_char = *input_line_pointer;
7182 *input_line_pointer = 0;
7183 }
7184 while (m68k_set_extension (name, 1, 0));
7185 }
7186
7187 *input_line_pointer = saved_char;
7188 demand_empty_rest_of_line ();
7189 return;
7190 }
7191 \f
7192 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7193 if none is found, the caller is responsible for emitting an error
7194 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7195 cpu name, if it begins with a '6' (possibly skipping an intervening
7196 'c'. We also allow a 'c' in the same place. if NEGATED is
7197 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7198 the option is indeed negated. */
7199
7200 static const struct m68k_cpu *
7201 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7202 int allow_m, int *negated)
7203 {
7204 /* allow negated value? */
7205 if (negated)
7206 {
7207 *negated = 0;
7208
7209 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7210 {
7211 arg += 3;
7212 *negated = 1;
7213 }
7214 }
7215
7216 /* Remove 'm' or 'mc' prefix from 68k variants. */
7217 if (allow_m)
7218 {
7219 if (arg[0] == 'm')
7220 {
7221 if (arg[1] == '6')
7222 arg += 1;
7223 else if (arg[1] == 'c' && arg[2] == '6')
7224 arg += 2;
7225 }
7226 }
7227 else if (arg[0] == 'c' && arg[1] == '6')
7228 arg += 1;
7229
7230 for (; table->name; table++)
7231 if (!strcmp (arg, table->name))
7232 {
7233 if (table->alias < -1 || table->alias > 1)
7234 as_bad (_("`%s' is deprecated, use `%s'"),
7235 table->name, table[table->alias < 0 ? 1 : -1].name);
7236 return table;
7237 }
7238 return 0;
7239 }
7240
7241 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7242
7243 static int
7244 m68k_set_cpu (char const *name, int allow_m, int silent)
7245 {
7246 const struct m68k_cpu *cpu;
7247
7248 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7249
7250 if (!cpu)
7251 {
7252 if (!silent)
7253 as_bad (_("cpu `%s' unrecognized"), name);
7254 return 0;
7255 }
7256
7257 if (selected_cpu && selected_cpu != cpu)
7258 {
7259 as_bad (_("already selected `%s' processor"),
7260 selected_cpu->name);
7261 return 0;
7262 }
7263 selected_cpu = cpu;
7264 return 1;
7265 }
7266
7267 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7268
7269 static int
7270 m68k_set_arch (char const *name, int allow_m, int silent)
7271 {
7272 const struct m68k_cpu *arch;
7273
7274 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7275
7276 if (!arch)
7277 {
7278 if (!silent)
7279 as_bad (_("architecture `%s' unrecognized"), name);
7280 return 0;
7281 }
7282
7283 if (selected_arch && selected_arch != arch)
7284 {
7285 as_bad (_("already selected `%s' architecture"),
7286 selected_arch->name);
7287 return 0;
7288 }
7289
7290 selected_arch = arch;
7291 return 1;
7292 }
7293
7294 /* Set the architecture extension, issuing errors if it is
7295 unrecognized, or invalid */
7296
7297 static int
7298 m68k_set_extension (char const *name, int allow_m, int silent)
7299 {
7300 int negated;
7301 const struct m68k_cpu *ext;
7302
7303 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7304
7305 if (!ext)
7306 {
7307 if (!silent)
7308 as_bad (_("extension `%s' unrecognized"), name);
7309 return 0;
7310 }
7311
7312 if (negated)
7313 not_current_architecture |= ext->arch;
7314 else
7315 current_architecture |= ext->arch;
7316 return 1;
7317 }
7318
7319 /* md_parse_option
7320 Invocation line includes a switch not recognized by the base assembler.
7321 */
7322
7323 #ifdef OBJ_ELF
7324 const char *md_shortopts = "lSA:m:kQ:V";
7325 #else
7326 const char *md_shortopts = "lSA:m:k";
7327 #endif
7328
7329 struct option md_longopts[] = {
7330 #define OPTION_PIC (OPTION_MD_BASE)
7331 {"pic", no_argument, NULL, OPTION_PIC},
7332 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7333 {"register-prefix-optional", no_argument, NULL,
7334 OPTION_REGISTER_PREFIX_OPTIONAL},
7335 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7336 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7337 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7338 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7339 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7340 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7341 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7342 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7343 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7344 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7345 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7346 {"pcrel", no_argument, NULL, OPTION_PCREL},
7347 {NULL, no_argument, NULL, 0}
7348 };
7349 size_t md_longopts_size = sizeof (md_longopts);
7350
7351 int
7352 md_parse_option (int c, char *arg)
7353 {
7354 switch (c)
7355 {
7356 case 'l': /* -l means keep external to 2 bit offset
7357 rather than 16 bit one. */
7358 flag_short_refs = 1;
7359 break;
7360
7361 case 'S': /* -S means that jbsr's always turn into
7362 jsr's. */
7363 flag_long_jumps = 1;
7364 break;
7365
7366 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7367 branches into absolute jumps. */
7368 flag_keep_pcrel = 1;
7369 break;
7370
7371 case OPTION_PIC:
7372 case 'k':
7373 flag_want_pic = 1;
7374 break; /* -pic, Position Independent Code. */
7375
7376 case OPTION_REGISTER_PREFIX_OPTIONAL:
7377 flag_reg_prefix_optional = 1;
7378 reg_prefix_optional_seen = 1;
7379 break;
7380
7381 /* -V: SVR4 argument to print version ID. */
7382 case 'V':
7383 print_version_id ();
7384 break;
7385
7386 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7387 should be emitted or not. FIXME: Not implemented. */
7388 case 'Q':
7389 break;
7390
7391 case OPTION_BITWISE_OR:
7392 {
7393 char *n, *t;
7394 const char *s;
7395
7396 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7397 t = n;
7398 for (s = m68k_comment_chars; *s != '\0'; s++)
7399 if (*s != '|')
7400 *t++ = *s;
7401 *t = '\0';
7402 m68k_comment_chars = n;
7403 }
7404 break;
7405
7406 case OPTION_BASE_SIZE_DEFAULT_16:
7407 m68k_index_width_default = SIZE_WORD;
7408 break;
7409
7410 case OPTION_BASE_SIZE_DEFAULT_32:
7411 m68k_index_width_default = SIZE_LONG;
7412 break;
7413
7414 case OPTION_DISP_SIZE_DEFAULT_16:
7415 m68k_rel32 = 0;
7416 m68k_rel32_from_cmdline = 1;
7417 break;
7418
7419 case OPTION_DISP_SIZE_DEFAULT_32:
7420 m68k_rel32 = 1;
7421 m68k_rel32_from_cmdline = 1;
7422 break;
7423
7424 case 'A':
7425 #if WARN_DEPRECATED
7426 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7427 arg, arg));
7428 #endif
7429 /* Intentional fall-through. */
7430 case 'm':
7431 if (!strncmp (arg, "arch=", 5))
7432 m68k_set_arch (arg + 5, 1, 0);
7433 else if (!strncmp (arg, "cpu=", 4))
7434 m68k_set_cpu (arg + 4, 1, 0);
7435 else if (m68k_set_extension (arg, 0, 1))
7436 ;
7437 else if (m68k_set_arch (arg, 0, 1))
7438 ;
7439 else if (m68k_set_cpu (arg, 0, 1))
7440 ;
7441 else
7442 return 0;
7443 break;
7444
7445 default:
7446 return 0;
7447 }
7448
7449 return 1;
7450 }
7451
7452 /* Setup tables from the selected arch and/or cpu */
7453
7454 static void
7455 m68k_init_arch (void)
7456 {
7457 if (not_current_architecture & current_architecture)
7458 {
7459 as_bad (_("architecture features both enabled and disabled"));
7460 not_current_architecture &= ~current_architecture;
7461 }
7462 if (selected_arch)
7463 {
7464 current_architecture |= selected_arch->arch;
7465 control_regs = selected_arch->control_regs;
7466 }
7467 else
7468 current_architecture |= selected_cpu->arch;
7469
7470 current_architecture &= ~not_current_architecture;
7471
7472 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7473 {
7474 /* Determine which float is really meant. */
7475 if (current_architecture & (m68k_mask & ~m68881))
7476 current_architecture ^= cfloat;
7477 else
7478 current_architecture ^= m68881;
7479 }
7480
7481 if (selected_cpu)
7482 {
7483 control_regs = selected_cpu->control_regs;
7484 if (current_architecture & ~selected_cpu->arch)
7485 {
7486 as_bad (_("selected processor does not have all features of selected architecture"));
7487 current_architecture
7488 = selected_cpu->arch & ~not_current_architecture;
7489 }
7490 }
7491
7492 if ((current_architecture & m68k_mask)
7493 && (current_architecture & ~m68k_mask))
7494 {
7495 as_bad (_ ("m68k and cf features both selected"));
7496 if (current_architecture & m68k_mask)
7497 current_architecture &= m68k_mask;
7498 else
7499 current_architecture &= ~m68k_mask;
7500 }
7501
7502 /* Permit m68881 specification with all cpus; those that can't work
7503 with a coprocessor could be doing emulation. */
7504 if (current_architecture & m68851)
7505 {
7506 if (current_architecture & m68040)
7507 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7508 }
7509 /* What other incompatibilities could we check for? */
7510
7511 if (cpu_of_arch (current_architecture) < m68020
7512 || arch_coldfire_p (current_architecture))
7513 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7514
7515 initialized = 1;
7516 }
7517
7518 void
7519 md_show_usage (FILE *stream)
7520 {
7521 const char *default_cpu = TARGET_CPU;
7522 int i;
7523 unsigned int default_arch;
7524
7525 /* Get the canonical name for the default target CPU. */
7526 if (*default_cpu == 'm')
7527 default_cpu++;
7528 for (i = 0; m68k_cpus[i].name; i++)
7529 {
7530 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7531 {
7532 default_arch = m68k_cpus[i].arch;
7533 while (m68k_cpus[i].alias > 0)
7534 i--;
7535 while (m68k_cpus[i].alias < 0)
7536 i++;
7537 default_cpu = m68k_cpus[i].name;
7538 }
7539 }
7540
7541 fprintf (stream, _("\
7542 -march=<arch> set architecture\n\
7543 -mcpu=<cpu> set cpu [default %s]\n\
7544 "), default_cpu);
7545 for (i = 0; m68k_extensions[i].name; i++)
7546 fprintf (stream, _("\
7547 -m[no-]%-16s enable/disable%s architecture extension\n\
7548 "), m68k_extensions[i].name,
7549 m68k_extensions[i].alias > 0 ? " ColdFire"
7550 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7551
7552 fprintf (stream, _("\
7553 -l use 1 word for refs to undefined symbols [default 2]\n\
7554 -pic, -k generate position independent code\n\
7555 -S turn jbsr into jsr\n\
7556 --pcrel never turn PC-relative branches into absolute jumps\n\
7557 --register-prefix-optional\n\
7558 recognize register names without prefix character\n\
7559 --bitwise-or do not treat `|' as a comment character\n\
7560 --base-size-default-16 base reg without size is 16 bits\n\
7561 --base-size-default-32 base reg without size is 32 bits (default)\n\
7562 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7563 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7564 "));
7565
7566 fprintf (stream, _("Architecture variants are: "));
7567 for (i = 0; m68k_archs[i].name; i++)
7568 {
7569 if (i)
7570 fprintf (stream, " | ");
7571 fprintf (stream, m68k_archs[i].name);
7572 }
7573 fprintf (stream, "\n");
7574
7575 fprintf (stream, _("Processor variants are: "));
7576 for (i = 0; m68k_cpus[i].name; i++)
7577 {
7578 if (i)
7579 fprintf (stream, " | ");
7580 fprintf (stream, m68k_cpus[i].name);
7581 }
7582 fprintf (stream, _("\n"));
7583 }
7584 \f
7585 #ifdef TEST2
7586
7587 /* TEST2: Test md_assemble() */
7588 /* Warning, this routine probably doesn't work anymore. */
7589 int
7590 main (void)
7591 {
7592 struct m68k_it the_ins;
7593 char buf[120];
7594 char *cp;
7595 int n;
7596
7597 m68k_ip_begin ();
7598 for (;;)
7599 {
7600 if (!gets (buf) || !*buf)
7601 break;
7602 if (buf[0] == '|' || buf[1] == '.')
7603 continue;
7604 for (cp = buf; *cp; cp++)
7605 if (*cp == '\t')
7606 *cp = ' ';
7607 if (is_label (buf))
7608 continue;
7609 memset (&the_ins, '\0', sizeof (the_ins));
7610 m68k_ip (&the_ins, buf);
7611 if (the_ins.error)
7612 {
7613 printf (_("Error %s in %s\n"), the_ins.error, buf);
7614 }
7615 else
7616 {
7617 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7618 for (n = 0; n < the_ins.numo; n++)
7619 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7620 printf (" ");
7621 print_the_insn (&the_ins.opcode[0], stdout);
7622 (void) putchar ('\n');
7623 }
7624 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7625 {
7626 if (the_ins.operands[n].error)
7627 {
7628 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7629 continue;
7630 }
7631 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7632 the_ins.operands[n].reg);
7633 if (the_ins.operands[n].b_const)
7634 printf ("Constant: '%.*s', ",
7635 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7636 the_ins.operands[n].b_const);
7637 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7638 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7639 if (the_ins.operands[n].b_iadd)
7640 printf ("Iadd: '%.*s',",
7641 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7642 the_ins.operands[n].b_iadd);
7643 putchar ('\n');
7644 }
7645 }
7646 m68k_ip_end ();
7647 return 0;
7648 }
7649
7650 int
7651 is_label (char *str)
7652 {
7653 while (*str == ' ')
7654 str++;
7655 while (*str && *str != ' ')
7656 str++;
7657 if (str[-1] == ':' || str[1] == '=')
7658 return 1;
7659 return 0;
7660 }
7661
7662 #endif
7663
7664 /* Possible states for relaxation:
7665
7666 0 0 branch offset byte (bra, etc)
7667 0 1 word
7668 0 2 long
7669
7670 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7671 1 1 word
7672 1 2 long
7673
7674 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7675 2 1 word-long
7676 2 2 long-word
7677 2 3 long-long
7678
7679 */
7680
7681 /* We have no need to default values of symbols. */
7682
7683 symbolS *
7684 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7685 {
7686 return 0;
7687 }
7688
7689 /* Round up a section size to the appropriate boundary. */
7690 valueT
7691 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7692 {
7693 #ifdef OBJ_AOUT
7694 /* For a.out, force the section size to be aligned. If we don't do
7695 this, BFD will align it for us, but it will not write out the
7696 final bytes of the section. This may be a bug in BFD, but it is
7697 easier to fix it here since that is how the other a.out targets
7698 work. */
7699 int align;
7700
7701 align = bfd_get_section_alignment (stdoutput, segment);
7702 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7703 #endif
7704
7705 return size;
7706 }
7707
7708 /* Exactly what point is a PC-relative offset relative TO?
7709 On the 68k, it is relative to the address of the first extension
7710 word. The difference between the addresses of the offset and the
7711 first extension word is stored in fx_pcrel_adjust. */
7712 long
7713 md_pcrel_from (fixS *fixP)
7714 {
7715 int adjust;
7716
7717 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7718 sign extend the value here. */
7719 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7720 if (adjust == 64)
7721 adjust = -1;
7722 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7723 }
7724
7725 #ifdef OBJ_ELF
7726 void
7727 m68k_elf_final_processing (void)
7728 {
7729 unsigned flags = 0;
7730
7731 if (arch_coldfire_fpu (current_architecture))
7732 flags |= EF_M68K_CFV4E;
7733 /* Set file-specific flags if this is a cpu32 processor. */
7734 if (cpu_of_arch (current_architecture) & cpu32)
7735 flags |= EF_M68K_CPU32;
7736 else if (cpu_of_arch (current_architecture) & fido_a)
7737 flags |= EF_M68K_FIDO;
7738 else if ((cpu_of_arch (current_architecture) & m68000up)
7739 && !(cpu_of_arch (current_architecture) & m68020up))
7740 flags |= EF_M68K_M68000;
7741
7742 if (current_architecture & mcfisa_a)
7743 {
7744 static const unsigned isa_features[][2] =
7745 {
7746 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7747 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7748 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7749 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7750 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7751 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7752 {0,0},
7753 };
7754 static const unsigned mac_features[][2] =
7755 {
7756 {EF_M68K_CF_MAC, mcfmac},
7757 {EF_M68K_CF_EMAC, mcfemac},
7758 {0,0},
7759 };
7760 unsigned ix;
7761 unsigned pattern;
7762
7763 pattern = (current_architecture
7764 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7765 for (ix = 0; isa_features[ix][1]; ix++)
7766 {
7767 if (pattern == isa_features[ix][1])
7768 {
7769 flags |= isa_features[ix][0];
7770 break;
7771 }
7772 }
7773 if (!isa_features[ix][1])
7774 {
7775 cf_bad:
7776 as_warn (_("Not a defined coldfire architecture"));
7777 }
7778 else
7779 {
7780 if (current_architecture & cfloat)
7781 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7782
7783 pattern = current_architecture & (mcfmac|mcfemac);
7784 if (pattern)
7785 {
7786 for (ix = 0; mac_features[ix][1]; ix++)
7787 {
7788 if (pattern == mac_features[ix][1])
7789 {
7790 flags |= mac_features[ix][0];
7791 break;
7792 }
7793 }
7794 if (!mac_features[ix][1])
7795 goto cf_bad;
7796 }
7797 }
7798 }
7799 elf_elfheader (stdoutput)->e_flags |= flags;
7800 }
7801 #endif
7802
7803 int
7804 tc_m68k_regname_to_dw2regnum (char *regname)
7805 {
7806 unsigned int regnum;
7807 static const char *const regnames[] =
7808 {
7809 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7810 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7811 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7812 "pc"
7813 };
7814
7815 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7816 if (strcmp (regname, regnames[regnum]) == 0)
7817 return regnum;
7818
7819 return -1;
7820 }
7821
7822 void
7823 tc_m68k_frame_initial_instructions (void)
7824 {
7825 static int sp_regno = -1;
7826
7827 if (sp_regno < 0)
7828 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7829
7830 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7831 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7832 }
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