gas/
[binutils.git] / gas / config / tc-d10v.c
blob336d9a845363c6ffff0008c1d4f791f4a162cc1f
1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "subsegs.h"
25 #include "opcode/d10v.h"
26 #include "elf/ppc.h"
28 const char comment_chars[] = ";";
29 const char line_comment_chars[] = "#";
30 const char line_separator_chars[] = "";
31 const char *md_shortopts = "O";
32 const char EXP_CHARS[] = "eE";
33 const char FLT_CHARS[] = "dD";
35 int Optimizing = 0;
37 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
38 && (X)->X_op_symbol != NULL \
39 && symbol_constant_p ((X)->X_op_symbol) \
40 && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
41 #define AT_WORD_RIGHT_SHIFT 2
43 /* Fixups. */
44 #define MAX_INSN_FIXUPS 5
46 struct d10v_fixup
48 expressionS exp;
49 int operand;
50 int pcrel;
51 int size;
52 bfd_reloc_code_real_type reloc;
55 typedef struct _fixups
57 int fc;
58 struct d10v_fixup fix[MAX_INSN_FIXUPS];
59 struct _fixups *next;
60 } Fixups;
62 static Fixups FixUps[2];
63 static Fixups *fixups;
65 static int do_not_ignore_hash = 0;
67 typedef int packing_type;
68 #define PACK_UNSPEC (0) /* Packing order not specified. */
69 #define PACK_PARALLEL (1) /* "||" */
70 #define PACK_LEFT_RIGHT (2) /* "->" */
71 #define PACK_RIGHT_LEFT (3) /* "<-" */
72 static packing_type etype = PACK_UNSPEC; /* Used by d10v_cleanup. */
74 /* TRUE if instruction swapping warnings should be inhibited.
75 --nowarnswap. */
76 static bfd_boolean flag_warn_suppress_instructionswap;
78 /* TRUE if instruction packing should be performed when --gstabs is specified.
79 --gstabs-packing, --no-gstabs-packing. */
80 static bfd_boolean flag_allow_gstabs_packing = 1;
82 /* Local functions. */
84 enum options
86 OPTION_NOWARNSWAP = OPTION_MD_BASE,
87 OPTION_GSTABSPACKING,
88 OPTION_NOGSTABSPACKING
91 struct option md_longopts[] =
93 {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP},
94 {"gstabspacking", no_argument, NULL, OPTION_GSTABSPACKING},
95 {"gstabs-packing", no_argument, NULL, OPTION_GSTABSPACKING},
96 {"nogstabspacking", no_argument, NULL, OPTION_NOGSTABSPACKING},
97 {"no-gstabs-packing", no_argument, NULL, OPTION_NOGSTABSPACKING},
98 {NULL, no_argument, NULL, 0}
101 size_t md_longopts_size = sizeof (md_longopts);
103 /* Opcode hash table. */
104 static struct hash_control *d10v_hash;
106 /* Do a binary search of the d10v_predefined_registers array to see if
107 NAME is a valid regiter name. Return the register number from the
108 array on success, or -1 on failure. */
110 static int
111 reg_name_search (char *name)
113 int middle, low, high;
114 int cmp;
116 low = 0;
117 high = d10v_reg_name_cnt () - 1;
121 middle = (low + high) / 2;
122 cmp = strcasecmp (name, d10v_predefined_registers[middle].name);
123 if (cmp < 0)
124 high = middle - 1;
125 else if (cmp > 0)
126 low = middle + 1;
127 else
128 return d10v_predefined_registers[middle].value;
130 while (low <= high);
131 return -1;
134 /* Check the string at input_line_pointer
135 to see if it is a valid register name. */
137 static int
138 register_name (expressionS *expressionP)
140 int reg_number;
141 char c, *p = input_line_pointer;
143 while (*p
144 && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')')
145 p++;
147 c = *p;
148 if (c)
149 *p++ = 0;
151 /* Look to see if it's in the register table. */
152 reg_number = reg_name_search (input_line_pointer);
153 if (reg_number >= 0)
155 expressionP->X_op = O_register;
156 /* Temporarily store a pointer to the string here. */
157 expressionP->X_op_symbol = (symbolS *) input_line_pointer;
158 expressionP->X_add_number = reg_number;
159 input_line_pointer = p;
160 return 1;
162 if (c)
163 *(p - 1) = c;
164 return 0;
167 static int
168 check_range (unsigned long num, int bits, int flags)
170 long min, max;
171 int retval = 0;
173 /* Don't bother checking 16-bit values. */
174 if (bits == 16)
175 return 0;
177 if (flags & OPERAND_SHIFT)
179 /* All special shift operands are unsigned and <= 16.
180 We allow 0 for now. */
181 if (num > 16)
182 return 1;
183 else
184 return 0;
187 if (flags & OPERAND_SIGNED)
189 /* Signed 3-bit integers are restricted to the (-2, 3) range. */
190 if (flags & RESTRICTED_NUM3)
192 if ((long) num < -2 || (long) num > 3)
193 retval = 1;
195 else
197 max = (1 << (bits - 1)) - 1;
198 min = - (1 << (bits - 1));
199 if (((long) num > max) || ((long) num < min))
200 retval = 1;
203 else
205 max = (1 << bits) - 1;
206 min = 0;
207 if (((long) num > max) || ((long) num < min))
208 retval = 1;
210 return retval;
213 void
214 md_show_usage (FILE *stream)
216 fprintf (stream, _("D10V options:\n\
217 -O Optimize. Will do some operations in parallel.\n\
218 --gstabs-packing Pack adjacent short instructions together even\n\
219 when --gstabs is specified. On by default.\n\
220 --no-gstabs-packing If --gstabs is specified, do not pack adjacent\n\
221 instructions together.\n"));
225 md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
227 switch (c)
229 case 'O':
230 /* Optimize. Will attempt to parallelize operations. */
231 Optimizing = 1;
232 break;
233 case OPTION_NOWARNSWAP:
234 flag_warn_suppress_instructionswap = 1;
235 break;
236 case OPTION_GSTABSPACKING:
237 flag_allow_gstabs_packing = 1;
238 break;
239 case OPTION_NOGSTABSPACKING:
240 flag_allow_gstabs_packing = 0;
241 break;
242 default:
243 return 0;
245 return 1;
248 symbolS *
249 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
251 return 0;
254 /* Turn a string in input_line_pointer into a floating point constant
255 of type TYPE, and store the appropriate bytes in *LITP. The number
256 of LITTLENUMS emitted is stored in *SIZEP. An error message is
257 returned, or NULL on OK. */
259 char *
260 md_atof (int type, char *litP, int *sizeP)
262 int prec;
263 LITTLENUM_TYPE words[4];
264 char *t;
265 int i;
267 switch (type)
269 case 'f':
270 prec = 2;
271 break;
272 case 'd':
273 prec = 4;
274 break;
275 default:
276 *sizeP = 0;
277 return _("bad call to md_atof");
280 t = atof_ieee (input_line_pointer, type, words);
281 if (t)
282 input_line_pointer = t;
284 *sizeP = prec * 2;
286 for (i = 0; i < prec; i++)
288 md_number_to_chars (litP, (valueT) words[i], 2);
289 litP += 2;
291 return NULL;
294 void
295 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
296 asection *sec ATTRIBUTE_UNUSED,
297 fragS *fragP ATTRIBUTE_UNUSED)
299 abort ();
302 valueT
303 md_section_align (asection *seg, valueT addr)
305 int align = bfd_get_section_alignment (stdoutput, seg);
306 return ((addr + (1 << align) - 1) & (-1 << align));
309 void
310 md_begin (void)
312 char *prev_name = "";
313 struct d10v_opcode *opcode;
314 d10v_hash = hash_new ();
316 /* Insert unique names into hash table. The D10v instruction set
317 has many identical opcode names that have different opcodes based
318 on the operands. This hash table then provides a quick index to
319 the first opcode with a particular name in the opcode table. */
321 for (opcode = (struct d10v_opcode *) d10v_opcodes; opcode->name; opcode++)
323 if (strcmp (prev_name, opcode->name))
325 prev_name = (char *) opcode->name;
326 hash_insert (d10v_hash, opcode->name, (char *) opcode);
330 fixups = &FixUps[0];
331 FixUps[0].next = &FixUps[1];
332 FixUps[1].next = &FixUps[0];
335 /* Remove the postincrement or postdecrement operator ( '+' or '-' )
336 from an expression. */
338 static int
339 postfix (char *p)
341 while (*p != '-' && *p != '+')
343 if (*p == 0 || *p == '\n' || *p == '\r')
344 break;
345 p++;
348 if (*p == '-')
350 *p = ' ';
351 return -1;
353 if (*p == '+')
355 *p = ' ';
356 return 1;
359 return 0;
362 static bfd_reloc_code_real_type
363 get_reloc (struct d10v_operand *op)
365 int bits = op->bits;
367 if (bits <= 4)
368 return 0;
370 if (op->flags & OPERAND_ADDR)
372 if (bits == 8)
373 return BFD_RELOC_D10V_10_PCREL_R;
374 else
375 return BFD_RELOC_D10V_18_PCREL;
378 return BFD_RELOC_16;
381 /* Parse a string of operands. Return an array of expressions. */
383 static int
384 get_operands (expressionS exp[])
386 char *p = input_line_pointer;
387 int numops = 0;
388 int post = 0;
389 int uses_at = 0;
391 while (*p)
393 while (*p == ' ' || *p == '\t' || *p == ',')
394 p++;
395 if (*p == 0 || *p == '\n' || *p == '\r')
396 break;
398 if (*p == '@')
400 uses_at = 1;
402 p++;
403 exp[numops].X_op = O_absent;
404 if (*p == '(')
406 p++;
407 exp[numops].X_add_number = OPERAND_ATPAR;
409 else if (*p == '-')
411 p++;
412 exp[numops].X_add_number = OPERAND_ATMINUS;
414 else
416 exp[numops].X_add_number = OPERAND_ATSIGN;
417 if (*p == '+')
419 numops++;
420 exp[numops].X_op = O_absent;
421 exp[numops].X_add_number = OPERAND_PLUS;
422 p++;
424 post = postfix (p);
426 numops++;
427 continue;
430 if (*p == ')')
432 /* Just skip the trailing paren. */
433 p++;
434 continue;
437 input_line_pointer = p;
439 /* Check to see if it might be a register name. */
440 if (!register_name (&exp[numops]))
442 /* Parse as an expression. */
443 if (uses_at)
445 /* Any expression that involves the indirect addressing
446 cannot also involve immediate addressing. Therefore
447 the use of the hash character is illegal. */
448 int save = do_not_ignore_hash;
449 do_not_ignore_hash = 1;
451 expression (&exp[numops]);
453 do_not_ignore_hash = save;
455 else
456 expression (&exp[numops]);
459 if (strncasecmp (input_line_pointer, "@word", 5) == 0)
461 input_line_pointer += 5;
462 if (exp[numops].X_op == O_register)
464 /* If it looked like a register name but was followed by
465 "@word" then it was really a symbol, so change it to
466 one. */
467 exp[numops].X_op = O_symbol;
468 exp[numops].X_add_symbol =
469 symbol_find_or_make ((char *) exp[numops].X_op_symbol);
472 /* Check for identifier@word+constant. */
473 if (*input_line_pointer == '-' || *input_line_pointer == '+')
475 expressionS new_exp;
476 expression (&new_exp);
477 exp[numops].X_add_number = new_exp.X_add_number;
480 /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */
482 expressionS new_exp;
483 memset (&new_exp, 0, sizeof new_exp);
484 new_exp.X_add_number = AT_WORD_RIGHT_SHIFT;
485 new_exp.X_op = O_constant;
486 new_exp.X_unsigned = 1;
487 exp[numops].X_op_symbol = make_expr_symbol (&new_exp);
488 exp[numops].X_op = O_right_shift;
491 know (AT_WORD_P (&exp[numops]));
494 if (exp[numops].X_op == O_illegal)
495 as_bad (_("illegal operand"));
496 else if (exp[numops].X_op == O_absent)
497 as_bad (_("missing operand"));
499 numops++;
500 p = input_line_pointer;
503 switch (post)
505 case -1: /* Postdecrement mode. */
506 exp[numops].X_op = O_absent;
507 exp[numops++].X_add_number = OPERAND_MINUS;
508 break;
509 case 1: /* Postincrement mode. */
510 exp[numops].X_op = O_absent;
511 exp[numops++].X_add_number = OPERAND_PLUS;
512 break;
515 exp[numops].X_op = 0;
516 return numops;
519 static unsigned long
520 d10v_insert_operand (unsigned long insn,
521 int op_type,
522 offsetT value,
523 int left,
524 fixS *fix)
526 int shift, bits;
528 shift = d10v_operands[op_type].shift;
529 if (left)
530 shift += 15;
532 bits = d10v_operands[op_type].bits;
534 /* Truncate to the proper number of bits. */
535 if (check_range (value, bits, d10v_operands[op_type].flags))
536 as_bad_where (fix->fx_file, fix->fx_line,
537 _("operand out of range: %ld"), (long) value);
539 value &= 0x7FFFFFFF >> (31 - bits);
540 insn |= (value << shift);
542 return insn;
545 /* Take a pointer to the opcode entry in the opcode table and the
546 array of operand expressions. Return the instruction. */
548 static unsigned long
549 build_insn (struct d10v_opcode *opcode,
550 expressionS *opers,
551 unsigned long insn)
553 int i, bits, shift, flags, format;
554 unsigned long number;
556 /* The insn argument is only used for the DIVS kludge. */
557 if (insn)
558 format = LONG_R;
559 else
561 insn = opcode->opcode;
562 format = opcode->format;
565 for (i = 0; opcode->operands[i]; i++)
567 flags = d10v_operands[opcode->operands[i]].flags;
568 bits = d10v_operands[opcode->operands[i]].bits;
569 shift = d10v_operands[opcode->operands[i]].shift;
570 number = opers[i].X_add_number;
572 if (flags & OPERAND_REG)
574 number &= REGISTER_MASK;
575 if (format == LONG_L)
576 shift += 15;
579 if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
581 /* Now create a fixup. */
583 if (fixups->fc >= MAX_INSN_FIXUPS)
584 as_fatal (_("too many fixups"));
586 if (AT_WORD_P (&opers[i]))
588 /* Recognize XXX>>1+N aka XXX@word+N as special (AT_WORD). */
589 fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18;
590 opers[i].X_op = O_symbol;
591 opers[i].X_op_symbol = NULL; /* Should free it. */
592 /* number is left shifted by AT_WORD_RIGHT_SHIFT so
593 that, it is aligned with the symbol's value. Later,
594 BFD_RELOC_D10V_18 will right shift (symbol_value +
595 X_add_number). */
596 number <<= AT_WORD_RIGHT_SHIFT;
597 opers[i].X_add_number = number;
599 else
601 fixups->fix[fixups->fc].reloc =
602 get_reloc ((struct d10v_operand *) &d10v_operands[opcode->operands[i]]);
604 /* Check that an immediate was passed to ops that expect one. */
605 if ((flags & OPERAND_NUM)
606 && (fixups->fix[fixups->fc].reloc == 0))
607 as_bad (_("operand is not an immediate"));
610 if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 ||
611 fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18)
612 fixups->fix[fixups->fc].size = 2;
613 else
614 fixups->fix[fixups->fc].size = 4;
616 fixups->fix[fixups->fc].exp = opers[i];
617 fixups->fix[fixups->fc].operand = opcode->operands[i];
618 fixups->fix[fixups->fc].pcrel =
619 (flags & OPERAND_ADDR) ? TRUE : FALSE;
620 (fixups->fc)++;
623 /* Truncate to the proper number of bits. */
624 if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
625 as_bad (_("operand out of range: %lu"), number);
626 number &= 0x7FFFFFFF >> (31 - bits);
627 insn = insn | (number << shift);
630 /* kludge: for DIVS, we need to put the operands in twice on the second
631 pass, format is changed to LONG_R to force the second set of operands
632 to not be shifted over 15. */
633 if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L))
634 insn = build_insn (opcode, opers, insn);
636 return insn;
639 /* Write out a long form instruction. */
641 static void
642 write_long (unsigned long insn, Fixups *fx)
644 int i, where;
645 char *f = frag_more (4);
647 insn |= FM11;
648 number_to_chars_bigendian (f, insn, 4);
650 for (i = 0; i < fx->fc; i++)
652 if (fx->fix[i].reloc)
654 where = f - frag_now->fr_literal;
655 if (fx->fix[i].size == 2)
656 where += 2;
658 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
659 fx->fix[i].operand |= 4096;
661 fix_new_exp (frag_now,
662 where,
663 fx->fix[i].size,
664 &(fx->fix[i].exp),
665 fx->fix[i].pcrel,
666 fx->fix[i].operand|2048);
669 fx->fc = 0;
672 /* Write out a short form instruction by itself. */
674 static void
675 write_1_short (struct d10v_opcode *opcode,
676 unsigned long insn,
677 Fixups *fx)
679 char *f = frag_more (4);
680 int i, where;
682 if (opcode->exec_type & PARONLY)
683 as_fatal (_("Instruction must be executed in parallel with another instruction."));
685 /* The other container needs to be NOP.
686 According to 4.3.1: for FM=00, sub-instructions performed only by IU
687 cannot be encoded in L-container. */
688 if (opcode->unit == IU)
689 insn |= FM00 | (NOP << 15); /* Right container. */
690 else
691 insn = FM00 | (insn << 15) | NOP; /* Left container. */
693 number_to_chars_bigendian (f, insn, 4);
694 for (i = 0; i < fx->fc; i++)
696 if (fx->fix[i].reloc)
698 where = f - frag_now->fr_literal;
699 if (fx->fix[i].size == 2)
700 where += 2;
702 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
703 fx->fix[i].operand |= 4096;
705 /* If it's an R reloc, we may have to switch it to L. */
706 if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R)
707 && (opcode->unit != IU))
708 fx->fix[i].operand |= 1024;
710 fix_new_exp (frag_now,
711 where,
712 fx->fix[i].size,
713 &(fx->fix[i].exp),
714 fx->fix[i].pcrel,
715 fx->fix[i].operand|2048);
718 fx->fc = 0;
721 /* Determine if there are any resource conflicts among two manually
722 parallelized instructions. Some of this was lifted from parallel_ok. */
724 static void
725 check_resource_conflict (struct d10v_opcode *op1,
726 unsigned long insn1,
727 struct d10v_opcode *op2,
728 unsigned long insn2)
730 int i, j, flags, mask, shift, regno;
731 unsigned long ins, mod[2];
732 struct d10v_opcode *op;
734 if ((op1->exec_type & SEQ)
735 || ! ((op1->exec_type & PAR) || (op1->exec_type & PARONLY)))
737 as_warn (_("packing conflict: %s must dispatch sequentially"),
738 op1->name);
739 return;
742 if ((op2->exec_type & SEQ)
743 || ! ((op2->exec_type & PAR) || (op2->exec_type & PARONLY)))
745 as_warn (_("packing conflict: %s must dispatch sequentially"),
746 op2->name);
747 return;
750 /* See if both instructions write to the same resource.
752 The idea here is to create two sets of bitmasks (mod and used) which
753 indicate which registers are modified or used by each instruction.
754 The operation can only be done in parallel if neither instruction
755 modifies the same register. Accesses to control registers and memory
756 are treated as accesses to a single register. So if both instructions
757 write memory or if the first instruction writes memory and the second
758 reads, then they cannot be done in parallel. We treat reads to the PSW
759 (which includes C, F0, and F1) in isolation. So simultaneously writing
760 C and F0 in two different sub-instructions is permitted. */
762 /* The bitmasks (mod and used) look like this (bit 31 = MSB).
763 r0-r15 0-15
764 a0-a1 16-17
765 cr (not psw) 18
766 psw(other) 19
767 mem 20
768 psw(C flag) 21
769 psw(F0 flag) 22 */
771 for (j = 0; j < 2; j++)
773 if (j == 0)
775 op = op1;
776 ins = insn1;
778 else
780 op = op2;
781 ins = insn2;
783 mod[j] = 0;
784 if (op->exec_type & BRANCH_LINK)
785 mod[j] |= 1 << 13;
787 for (i = 0; op->operands[i]; i++)
789 flags = d10v_operands[op->operands[i]].flags;
790 shift = d10v_operands[op->operands[i]].shift;
791 mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
792 if (flags & OPERAND_REG)
794 regno = (ins >> shift) & mask;
795 if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
796 regno += 16;
797 else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */
799 if (regno == 0)
800 regno = 19;
801 else
802 regno = 18;
804 else if (flags & OPERAND_FFLAG)
805 regno = 22;
806 else if (flags & OPERAND_CFLAG)
807 regno = 21;
809 if (flags & OPERAND_DEST
810 /* Auto inc/dec also modifies the register. */
811 || (op->operands[i + 1] != 0
812 && (d10v_operands[op->operands[i + 1]].flags
813 & (OPERAND_PLUS | OPERAND_MINUS)) != 0))
815 mod[j] |= 1 << regno;
816 if (flags & OPERAND_EVEN)
817 mod[j] |= 1 << (regno + 1);
820 else if (flags & OPERAND_ATMINUS)
822 /* SP implicitly used/modified. */
823 mod[j] |= 1 << 15;
827 if (op->exec_type & WMEM)
828 mod[j] |= 1 << 20;
829 else if (op->exec_type & WF0)
830 mod[j] |= 1 << 22;
831 else if (op->exec_type & WCAR)
832 mod[j] |= 1 << 21;
835 if ((mod[0] & mod[1]) == 0)
836 return;
837 else
839 unsigned long x;
840 x = mod[0] & mod[1];
842 for (j = 0; j <= 15; j++)
843 if (x & (1 << j))
844 as_warn (_("resource conflict (R%d)"), j);
845 for (j = 16; j <= 17; j++)
846 if (x & (1 << j))
847 as_warn (_("resource conflict (A%d)"), j - 16);
848 if (x & (1 << 19))
849 as_warn (_("resource conflict (PSW)"));
850 if (x & (1 << 21))
851 as_warn (_("resource conflict (C flag)"));
852 if (x & (1 << 22))
853 as_warn (_("resource conflict (F flag)"));
857 /* Check 2 instructions and determine if they can be safely
858 executed in parallel. Return 1 if they can be. */
860 static int
861 parallel_ok (struct d10v_opcode *op1,
862 unsigned long insn1,
863 struct d10v_opcode *op2,
864 unsigned long insn2,
865 packing_type exec_type)
867 int i, j, flags, mask, shift, regno;
868 unsigned long ins, mod[2], used[2];
869 struct d10v_opcode *op;
871 if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0
872 || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0
873 || (op1->unit == BOTH) || (op2->unit == BOTH)
874 || (op1->unit == IU && op2->unit == IU)
875 || (op1->unit == MU && op2->unit == MU))
876 return 0;
878 /* If this is auto parallelization, and the first instruction is a
879 branch or should not be packed, then don't parallelize. */
880 if (exec_type == PACK_UNSPEC
881 && (op1->exec_type & (ALONE | BRANCH)))
882 return 0;
884 /* The idea here is to create two sets of bitmasks (mod and used)
885 which indicate which registers are modified or used by each
886 instruction. The operation can only be done in parallel if
887 instruction 1 and instruction 2 modify different registers, and
888 the first instruction does not modify registers that the second
889 is using (The second instruction can modify registers that the
890 first is using as they are only written back after the first
891 instruction has completed). Accesses to control registers, PSW,
892 and memory are treated as accesses to a single register. So if
893 both instructions write memory or if the first instruction writes
894 memory and the second reads, then they cannot be done in
895 parallel. Likewise, if the first instruction mucks with the psw
896 and the second reads the PSW (which includes C, F0, and F1), then
897 they cannot operate safely in parallel. */
899 /* The bitmasks (mod and used) look like this (bit 31 = MSB).
900 r0-r15 0-15
901 a0-a1 16-17
902 cr (not psw) 18
903 psw 19
904 mem 20 */
906 for (j = 0; j < 2; j++)
908 if (j == 0)
910 op = op1;
911 ins = insn1;
913 else
915 op = op2;
916 ins = insn2;
918 mod[j] = used[j] = 0;
919 if (op->exec_type & BRANCH_LINK)
920 mod[j] |= 1 << 13;
922 for (i = 0; op->operands[i]; i++)
924 flags = d10v_operands[op->operands[i]].flags;
925 shift = d10v_operands[op->operands[i]].shift;
926 mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
927 if (flags & OPERAND_REG)
929 regno = (ins >> shift) & mask;
930 if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
931 regno += 16;
932 else if (flags & OPERAND_CONTROL) /* mvtc or mvfc. */
934 if (regno == 0)
935 regno = 19;
936 else
937 regno = 18;
939 else if (flags & (OPERAND_FFLAG | OPERAND_CFLAG))
940 regno = 19;
942 if (flags & OPERAND_DEST)
944 mod[j] |= 1 << regno;
945 if (flags & OPERAND_EVEN)
946 mod[j] |= 1 << (regno + 1);
948 else
950 used[j] |= 1 << regno;
951 if (flags & OPERAND_EVEN)
952 used[j] |= 1 << (regno + 1);
954 /* Auto inc/dec also modifies the register. */
955 if (op->operands[i + 1] != 0
956 && (d10v_operands[op->operands[i + 1]].flags
957 & (OPERAND_PLUS | OPERAND_MINUS)) != 0)
958 mod[j] |= 1 << regno;
961 else if (flags & OPERAND_ATMINUS)
963 /* SP implicitly used/modified. */
964 mod[j] |= 1 << 15;
965 used[j] |= 1 << 15;
968 if (op->exec_type & RMEM)
969 used[j] |= 1 << 20;
970 else if (op->exec_type & WMEM)
971 mod[j] |= 1 << 20;
972 else if (op->exec_type & RF0)
973 used[j] |= 1 << 19;
974 else if (op->exec_type & WF0)
975 mod[j] |= 1 << 19;
976 else if (op->exec_type & WCAR)
977 mod[j] |= 1 << 19;
979 if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0)
980 return 1;
981 return 0;
984 /* Expects two short instructions.
985 If possible, writes out both as a single packed instruction.
986 Otherwise, writes out the first one, packed with a NOP.
987 Returns number of instructions not written out. */
989 static int
990 write_2_short (struct d10v_opcode *opcode1,
991 unsigned long insn1,
992 struct d10v_opcode *opcode2,
993 unsigned long insn2,
994 packing_type exec_type,
995 Fixups *fx)
997 unsigned long insn;
998 char *f;
999 int i, j, where;
1001 if ((exec_type != PACK_PARALLEL)
1002 && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY)))
1003 as_fatal (_("Instruction must be executed in parallel"));
1005 if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
1006 as_fatal (_("Long instructions may not be combined."));
1008 switch (exec_type)
1010 case PACK_UNSPEC: /* Order not specified. */
1011 if (opcode1->exec_type & ALONE)
1013 /* Case of a short branch on a separate GAS line. Pack with NOP. */
1014 write_1_short (opcode1, insn1, fx->next);
1015 return 1;
1017 if (Optimizing
1018 && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
1020 /* Parallel. */
1021 if (opcode1->unit == IU)
1022 insn = FM00 | (insn2 << 15) | insn1;
1023 else if (opcode2->unit == MU)
1024 insn = FM00 | (insn2 << 15) | insn1;
1025 else
1026 insn = FM00 | (insn1 << 15) | insn2;
1028 else if (opcode1->unit == IU)
1029 /* Reverse sequential with IU opcode1 on right and done first. */
1030 insn = FM10 | (insn2 << 15) | insn1;
1031 else
1032 /* Sequential with non-IU opcode1 on left and done first. */
1033 insn = FM01 | (insn1 << 15) | insn2;
1034 break;
1036 case PACK_PARALLEL:
1037 if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ)
1038 as_fatal
1039 (_("One of these instructions may not be executed in parallel."));
1040 if (opcode1->unit == IU)
1042 if (opcode2->unit == IU)
1043 as_fatal (_("Two IU instructions may not be executed in parallel"));
1044 if (!flag_warn_suppress_instructionswap)
1045 as_warn (_("Swapping instruction order"));
1046 insn = FM00 | (insn2 << 15) | insn1;
1048 else if (opcode2->unit == MU)
1050 if (opcode1->unit == MU)
1051 as_fatal (_("Two MU instructions may not be executed in parallel"));
1052 if (!flag_warn_suppress_instructionswap)
1053 as_warn (_("Swapping instruction order"));
1054 insn = FM00 | (insn2 << 15) | insn1;
1056 else
1057 insn = FM00 | (insn1 << 15) | insn2;
1058 check_resource_conflict (opcode1, insn1, opcode2, insn2);
1059 break;
1061 case PACK_LEFT_RIGHT:
1062 if (opcode1->unit != IU)
1063 insn = FM01 | (insn1 << 15) | insn2;
1064 else if (opcode2->unit == MU || opcode2->unit == EITHER)
1066 if (!flag_warn_suppress_instructionswap)
1067 as_warn (_("Swapping instruction order"));
1068 insn = FM10 | (insn2 << 15) | insn1;
1070 else
1071 as_fatal (_("IU instruction may not be in the left container"));
1072 if (opcode1->exec_type & ALONE)
1073 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
1074 break;
1076 case PACK_RIGHT_LEFT:
1077 if (opcode2->unit != MU)
1078 insn = FM10 | (insn1 << 15) | insn2;
1079 else if (opcode1->unit == IU || opcode1->unit == EITHER)
1081 if (!flag_warn_suppress_instructionswap)
1082 as_warn (_("Swapping instruction order"));
1083 insn = FM01 | (insn2 << 15) | insn1;
1085 else
1086 as_fatal (_("MU instruction may not be in the right container"));
1087 if (opcode2->exec_type & ALONE)
1088 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
1089 break;
1091 default:
1092 as_fatal (_("unknown execution type passed to write_2_short()"));
1095 f = frag_more (4);
1096 number_to_chars_bigendian (f, insn, 4);
1098 /* Process fixup chains. fx refers to insn2 when j == 0, and to
1099 insn1 when j == 1. Yes, it's reversed. */
1101 for (j = 0; j < 2; j++)
1103 for (i = 0; i < fx->fc; i++)
1105 if (fx->fix[i].reloc)
1107 where = f - frag_now->fr_literal;
1108 if (fx->fix[i].size == 2)
1109 where += 2;
1111 if (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R
1112 /* A BFD_RELOC_D10V_10_PCREL_R relocation applied to
1113 the instruction in the L container has to be
1114 adjusted to BDF_RELOC_D10V_10_PCREL_L. When
1115 j==0, we're processing insn2's operands, so we
1116 want to mark the operand if insn2 is *not* in the
1117 R container. When j==1, we're processing insn1's
1118 operands, so we want to mark the operand if insn2
1119 *is* in the R container. Note that, if two
1120 instructions are identical, we're never going to
1121 swap them, so the test is safe. */
1122 && j == ((insn & 0x7fff) == insn2))
1123 fx->fix[i].operand |= 1024;
1125 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
1126 fx->fix[i].operand |= 4096;
1128 fix_new_exp (frag_now,
1129 where,
1130 fx->fix[i].size,
1131 &(fx->fix[i].exp),
1132 fx->fix[i].pcrel,
1133 fx->fix[i].operand|2048);
1136 fx->fc = 0;
1137 fx = fx->next;
1139 return 0;
1142 /* This is the main entry point for the machine-dependent assembler.
1143 str points to a machine-dependent instruction. This function is
1144 supposed to emit the frags/bytes it assembles to. For the D10V, it
1145 mostly handles the special VLIW parsing and packing and leaves the
1146 difficult stuff to do_assemble(). */
1148 static unsigned long prev_insn;
1149 static struct d10v_opcode *prev_opcode = 0;
1150 static subsegT prev_subseg;
1151 static segT prev_seg = 0;;
1153 /* Find the symbol which has the same name as the register in exp. */
1155 static symbolS *
1156 find_symbol_matching_register (expressionS *exp)
1158 int i;
1160 if (exp->X_op != O_register)
1161 return NULL;
1163 /* Find the name of the register. */
1164 for (i = d10v_reg_name_cnt (); i--;)
1165 if (d10v_predefined_registers[i].value == exp->X_add_number)
1166 break;
1168 if (i < 0)
1169 abort ();
1171 /* Now see if a symbol has been defined with the same name. */
1172 return symbol_find (d10v_predefined_registers[i].name);
1175 /* Get a pointer to an entry in the opcode table.
1176 The function must look at all opcodes with the same name and use
1177 the operands to choose the correct opcode. */
1179 static struct d10v_opcode *
1180 find_opcode (struct d10v_opcode *opcode, expressionS myops[])
1182 int i, match;
1183 struct d10v_opcode *next_opcode;
1185 /* Get all the operands and save them as expressions. */
1186 get_operands (myops);
1188 /* Now see if the operand is a fake. If so, find the correct size
1189 instruction, if possible. */
1190 if (opcode->format == OPCODE_FAKE)
1192 int opnum = opcode->operands[0];
1193 int flags;
1195 if (myops[opnum].X_op == O_register)
1197 myops[opnum].X_op = O_symbol;
1198 myops[opnum].X_add_symbol =
1199 symbol_find_or_make ((char *) myops[opnum].X_op_symbol);
1200 myops[opnum].X_add_number = 0;
1201 myops[opnum].X_op_symbol = NULL;
1204 next_opcode = opcode + 1;
1206 /* If the first operand is supposed to be a register, make sure
1207 we got a valid one. */
1208 flags = d10v_operands[next_opcode->operands[0]].flags;
1209 if (flags & OPERAND_REG)
1211 int X_op = myops[0].X_op;
1212 int num = myops[0].X_add_number;
1214 if (X_op != O_register
1215 || (num & ~flags
1216 & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1
1217 | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL))
1218 || ((flags & OPERAND_SP) && ! (num & OPERAND_SP)))
1220 as_bad (_("bad opcode or operands"));
1221 return 0;
1225 if (myops[opnum].X_op == O_constant
1226 || (myops[opnum].X_op == O_symbol
1227 && S_IS_DEFINED (myops[opnum].X_add_symbol)
1228 && (S_GET_SEGMENT (myops[opnum].X_add_symbol) == now_seg)))
1230 for (i = 0; opcode->operands[i + 1]; i++)
1232 int bits = d10v_operands[next_opcode->operands[opnum]].bits;
1233 int flags = d10v_operands[next_opcode->operands[opnum]].flags;
1234 if (flags & OPERAND_ADDR)
1235 bits += 2;
1237 if (myops[opnum].X_op == O_constant)
1239 if (!check_range (myops[opnum].X_add_number, bits, flags))
1240 break;
1242 else
1244 fragS *sym_frag;
1245 fragS *f;
1246 unsigned long current_position;
1247 unsigned long symbol_position;
1248 unsigned long value;
1249 bfd_boolean found_symbol;
1251 /* Calculate the address of the current instruction
1252 and the address of the symbol. Do this by summing
1253 the offsets of previous frags until we reach the
1254 frag containing the symbol, and the current frag. */
1255 sym_frag = symbol_get_frag (myops[opnum].X_add_symbol);
1256 found_symbol = FALSE;
1258 current_position =
1259 obstack_next_free (&frchain_now->frch_obstack)
1260 - frag_now->fr_literal;
1261 symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol);
1263 for (f = frchain_now->frch_root; f; f = f->fr_next)
1265 current_position += f->fr_fix + f->fr_offset;
1267 if (f == sym_frag)
1268 found_symbol = TRUE;
1270 if (! found_symbol)
1271 symbol_position += f->fr_fix + f->fr_offset;
1274 value = symbol_position;
1276 if (flags & OPERAND_ADDR)
1277 value -= current_position;
1279 if (AT_WORD_P (&myops[opnum]))
1281 if (bits > 4)
1283 bits += 2;
1284 if (!check_range (value, bits, flags))
1285 break;
1288 else if (!check_range (value, bits, flags))
1289 break;
1291 next_opcode++;
1294 if (opcode->operands [i + 1] == 0)
1295 as_fatal (_("value out of range"));
1296 else
1297 opcode = next_opcode;
1299 else
1300 /* Not a constant, so use a long instruction. */
1301 opcode += 2;
1304 match = 0;
1306 /* Now search the opcode table table for one with operands
1307 that matches what we've got. */
1308 while (!match)
1310 match = 1;
1311 for (i = 0; opcode->operands[i]; i++)
1313 int flags = d10v_operands[opcode->operands[i]].flags;
1314 int X_op = myops[i].X_op;
1315 int num = myops[i].X_add_number;
1317 if (X_op == 0)
1319 match = 0;
1320 break;
1323 if (flags & OPERAND_REG)
1325 if ((X_op != O_register)
1326 || (num & ~flags
1327 & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1
1328 | OPERAND_FFLAG | OPERAND_CFLAG
1329 | OPERAND_CONTROL))
1330 || ((flags & OPERAND_SP) && ! (num & OPERAND_SP)))
1332 match = 0;
1333 break;
1337 if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) ||
1338 ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) ||
1339 ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) ||
1340 ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) ||
1341 ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || ((num != OPERAND_ATSIGN) && (num != OPERAND_ATPAR)))))
1343 match = 0;
1344 break;
1347 /* Unfortunately, for the indirect operand in instructions such
1348 as ``ldb r1, @(c,r14)'' this function can be passed
1349 X_op == O_register (because 'c' is a valid register name).
1350 However we cannot just ignore the case when X_op == O_register
1351 but flags & OPERAND_REG is null, so we check to see if a symbol
1352 of the same name as the register exists. If the symbol does
1353 exist, then the parser was unable to distinguish the two cases
1354 and we fix things here. (Ref: PR14826) */
1356 if (!(flags & OPERAND_REG) && (X_op == O_register))
1358 symbolS * sym;
1360 sym = find_symbol_matching_register (& myops[i]);
1362 if (sym != NULL)
1364 myops[i].X_op = X_op = O_symbol;
1365 myops[i].X_add_symbol = sym;
1367 else
1368 as_bad
1369 (_("illegal operand - register name found where none expected"));
1373 /* We're only done if the operands matched so far AND there
1374 are no more to check. */
1375 if (match && myops[i].X_op == 0)
1376 break;
1377 else
1378 match = 0;
1380 next_opcode = opcode + 1;
1382 if (next_opcode->opcode == 0)
1383 break;
1385 if (strcmp (next_opcode->name, opcode->name))
1386 break;
1388 opcode = next_opcode;
1391 if (!match)
1393 as_bad (_("bad opcode or operands"));
1394 return 0;
1397 /* Check that all registers that are required to be even are.
1398 Also, if any operands were marked as registers, but were really symbols,
1399 fix that here. */
1400 for (i = 0; opcode->operands[i]; i++)
1402 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) &&
1403 (myops[i].X_add_number & 1))
1404 as_fatal (_("Register number must be EVEN"));
1405 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_NOSP)
1406 && (myops[i].X_add_number & OPERAND_SP))
1407 as_bad (_("Unsupported use of sp"));
1408 if (myops[i].X_op == O_register)
1410 if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
1412 myops[i].X_op = O_symbol;
1413 myops[i].X_add_symbol =
1414 symbol_find_or_make ((char *) myops[i].X_op_symbol);
1415 myops[i].X_add_number = 0;
1416 myops[i].X_op_symbol = NULL;
1419 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_CONTROL)
1420 && (myops[i].X_add_number == OPERAND_CONTROL + 4
1421 || myops[i].X_add_number == OPERAND_CONTROL + 5
1422 || myops[i].X_add_number == OPERAND_CONTROL + 6
1423 || myops[i].X_add_number == OPERAND_CONTROL + 12
1424 || myops[i].X_add_number == OPERAND_CONTROL + 13
1425 || myops[i].X_add_number == OPERAND_CONTROL + 15))
1426 as_warn (_("cr%ld is a reserved control register"),
1427 myops[i].X_add_number - OPERAND_CONTROL);
1429 return opcode;
1432 /* Assemble a single instruction.
1433 Return an opcode, or -1 (an invalid opcode) on error. */
1435 static unsigned long
1436 do_assemble (char *str, struct d10v_opcode **opcode)
1438 unsigned char *op_start, *op_end;
1439 char *save;
1440 char name[20];
1441 int nlen = 0;
1442 expressionS myops[6];
1444 /* Drop leading whitespace. */
1445 while (*str == ' ')
1446 str++;
1448 /* Find the opcode end. */
1449 for (op_start = op_end = (unsigned char *) str;
1450 *op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' ';
1451 op_end++)
1453 name[nlen] = TOLOWER (op_start[nlen]);
1454 nlen++;
1456 name[nlen] = 0;
1458 if (nlen == 0)
1459 return -1;
1461 /* Find the first opcode with the proper name. */
1462 *opcode = (struct d10v_opcode *) hash_find (d10v_hash, name);
1463 if (*opcode == NULL)
1464 return -1;
1466 save = input_line_pointer;
1467 input_line_pointer = (char *) op_end;
1468 *opcode = find_opcode (*opcode, myops);
1469 if (*opcode == 0)
1470 return -1;
1471 input_line_pointer = save;
1473 return build_insn ((*opcode), myops, 0);
1476 /* If while processing a fixup, a reloc really needs to be created.
1477 Then it is done here. */
1479 arelent *
1480 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
1482 arelent *reloc;
1483 reloc = xmalloc (sizeof (arelent));
1484 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
1485 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1486 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1487 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1488 if (reloc->howto == (reloc_howto_type *) NULL)
1490 as_bad_where (fixp->fx_file, fixp->fx_line,
1491 _("reloc %d not supported by object file format"),
1492 (int) fixp->fx_r_type);
1493 return NULL;
1496 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1497 reloc->address = fixp->fx_offset;
1499 reloc->addend = 0;
1501 return reloc;
1505 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
1506 asection *seg ATTRIBUTE_UNUSED)
1508 abort ();
1509 return 0;
1512 long
1513 md_pcrel_from_section (fixS *fixp, segT sec)
1515 if (fixp->fx_addsy != (symbolS *) NULL
1516 && (!S_IS_DEFINED (fixp->fx_addsy)
1517 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1518 return 0;
1519 return fixp->fx_frag->fr_address + fixp->fx_where;
1522 void
1523 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
1525 char *where;
1526 unsigned long insn;
1527 long value = *valP;
1528 int op_type;
1529 int left = 0;
1531 if (fixP->fx_addsy == (symbolS *) NULL)
1532 fixP->fx_done = 1;
1534 /* We don't actually support subtracting a symbol. */
1535 if (fixP->fx_subsy != (symbolS *) NULL)
1536 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1538 op_type = fixP->fx_r_type;
1539 if (op_type & 2048)
1541 op_type -= 2048;
1542 if (op_type & 1024)
1544 op_type -= 1024;
1545 fixP->fx_r_type = BFD_RELOC_D10V_10_PCREL_L;
1546 left = 1;
1548 else if (op_type & 4096)
1550 op_type -= 4096;
1551 fixP->fx_r_type = BFD_RELOC_D10V_18;
1553 else
1554 fixP->fx_r_type =
1555 get_reloc ((struct d10v_operand *) &d10v_operands[op_type]);
1558 /* Fetch the instruction, insert the fully resolved operand
1559 value, and stuff the instruction back again. */
1560 where = fixP->fx_frag->fr_literal + fixP->fx_where;
1561 insn = bfd_getb32 ((unsigned char *) where);
1563 switch (fixP->fx_r_type)
1565 case BFD_RELOC_D10V_10_PCREL_L:
1566 case BFD_RELOC_D10V_10_PCREL_R:
1567 case BFD_RELOC_D10V_18_PCREL:
1568 /* If the fix is relative to a global symbol, not a section
1569 symbol, then ignore the offset.
1570 XXX - Do we have to worry about branches to a symbol + offset ? */
1571 if (fixP->fx_addsy != NULL
1572 && S_IS_EXTERNAL (fixP->fx_addsy) )
1574 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
1575 segment_info_type *segf = seg_info(fseg);
1577 if ( segf && segf->sym != fixP->fx_addsy)
1578 value = 0;
1580 /* Drop through. */
1581 case BFD_RELOC_D10V_18:
1582 /* Instruction addresses are always right-shifted by 2. */
1583 value >>= AT_WORD_RIGHT_SHIFT;
1584 if (fixP->fx_size == 2)
1585 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1586 else
1588 struct d10v_opcode *rep, *repi;
1590 rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep");
1591 repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi");
1592 if ((insn & FM11) == FM11
1593 && ((repi != NULL
1594 && (insn & repi->mask) == (unsigned) repi->opcode)
1595 || (rep != NULL
1596 && (insn & rep->mask) == (unsigned) rep->opcode))
1597 && value < 4)
1598 as_fatal
1599 (_("line %d: rep or repi must include at least 4 instructions"),
1600 fixP->fx_line);
1601 insn =
1602 d10v_insert_operand (insn, op_type, (offsetT) value, left, fixP);
1603 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1605 break;
1606 case BFD_RELOC_32:
1607 bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
1608 break;
1609 case BFD_RELOC_16:
1610 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1611 break;
1613 case BFD_RELOC_VTABLE_INHERIT:
1614 case BFD_RELOC_VTABLE_ENTRY:
1615 fixP->fx_done = 0;
1616 return;
1618 default:
1619 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1620 fixP->fx_line, fixP->fx_r_type);
1624 /* d10v_cleanup() is called after the assembler has finished parsing
1625 the input file, when a label is read from the input file, or when a
1626 stab directive is output. Because the D10V assembler sometimes
1627 saves short instructions to see if it can package them with the
1628 next instruction, there may be a short instruction that still needs
1629 to be written.
1631 NOTE: accesses a global, etype.
1632 NOTE: invoked by various macros such as md_cleanup: see. */
1635 d10v_cleanup (void)
1637 segT seg;
1638 subsegT subseg;
1640 /* If cleanup was invoked because the assembler encountered, e.g., a
1641 user label, we write out the pending instruction, if any. If it
1642 was invoked because the assembler is outputting a piece of line
1643 debugging information, though, we write out the pending
1644 instruction only if the --no-gstabs-packing command line switch
1645 has been specified. */
1646 if (prev_opcode
1647 && etype == PACK_UNSPEC
1648 && (! outputting_stabs_line_debug || ! flag_allow_gstabs_packing))
1650 seg = now_seg;
1651 subseg = now_subseg;
1653 if (prev_seg)
1654 subseg_set (prev_seg, prev_subseg);
1656 write_1_short (prev_opcode, prev_insn, fixups->next);
1657 subseg_set (seg, subseg);
1658 prev_opcode = NULL;
1660 return 1;
1663 /* Like normal .word, except support @word.
1664 Clobbers input_line_pointer, checks end-of-line. */
1666 static void
1667 d10v_dot_word (int dummy ATTRIBUTE_UNUSED)
1669 expressionS exp;
1670 char *p;
1672 if (is_it_end_of_statement ())
1674 demand_empty_rest_of_line ();
1675 return;
1680 expression (&exp);
1681 if (!strncasecmp (input_line_pointer, "@word", 5))
1683 exp.X_add_number = 0;
1684 input_line_pointer += 5;
1686 p = frag_more (2);
1687 fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
1688 &exp, 0, BFD_RELOC_D10V_18);
1690 else
1691 emit_expr (&exp, 2);
1693 while (*input_line_pointer++ == ',');
1695 input_line_pointer--; /* Put terminator back into stream. */
1696 demand_empty_rest_of_line ();
1699 /* Mitsubishi asked that we support some old syntax that apparently
1700 had immediate operands starting with '#'. This is in some of their
1701 sample code but is not documented (although it appears in some
1702 examples in their assembler manual). For now, we'll solve this
1703 compatibility problem by simply ignoring any '#' at the beginning
1704 of an operand. */
1706 /* Operands that begin with '#' should fall through to here.
1707 From expr.c. */
1709 void
1710 md_operand (expressionS *expressionP)
1712 if (*input_line_pointer == '#' && ! do_not_ignore_hash)
1714 input_line_pointer++;
1715 expression (expressionP);
1719 bfd_boolean
1720 d10v_fix_adjustable (fixS *fixP)
1722 /* We need the symbol name for the VTABLE entries. */
1723 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1724 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1725 return 0;
1727 return 1;
1730 /* The target specific pseudo-ops which we support. */
1731 const pseudo_typeS md_pseudo_table[] =
1733 { "word", d10v_dot_word, 2 },
1734 { NULL, NULL, 0 }
1737 void
1738 md_assemble (char *str)
1740 /* etype is saved extype. For multi-line instructions. */
1741 packing_type extype = PACK_UNSPEC; /* Parallel, etc. */
1742 struct d10v_opcode *opcode;
1743 unsigned long insn;
1744 char *str2;
1746 if (etype == PACK_UNSPEC)
1748 /* Look for the special multiple instruction separators. */
1749 str2 = strstr (str, "||");
1750 if (str2)
1751 extype = PACK_PARALLEL;
1752 else
1754 str2 = strstr (str, "->");
1755 if (str2)
1756 extype = PACK_LEFT_RIGHT;
1757 else
1759 str2 = strstr (str, "<-");
1760 if (str2)
1761 extype = PACK_RIGHT_LEFT;
1765 /* str2 points to the separator, if there is one. */
1766 if (str2)
1768 *str2 = 0;
1770 /* If two instructions are present and we already have one saved,
1771 then first write out the saved one. */
1772 d10v_cleanup ();
1774 /* Assemble first instruction and save it. */
1775 prev_insn = do_assemble (str, &prev_opcode);
1776 prev_seg = now_seg;
1777 prev_subseg = now_subseg;
1778 if (prev_insn == (unsigned long) -1)
1779 as_fatal (_("can't find previous opcode "));
1780 fixups = fixups->next;
1781 str = str2 + 2;
1785 insn = do_assemble (str, &opcode);
1786 if (insn == (unsigned long) -1)
1788 if (extype != PACK_UNSPEC)
1789 etype = extype;
1790 else
1791 as_bad (_("could not assemble: %s"), str);
1792 return;
1795 if (etype != PACK_UNSPEC)
1797 extype = etype;
1798 etype = PACK_UNSPEC;
1801 /* If this is a long instruction, write it and any previous short
1802 instruction. */
1803 if (opcode->format & LONG_OPCODE)
1805 if (extype != PACK_UNSPEC)
1806 as_fatal (_("Unable to mix instructions as specified"));
1807 d10v_cleanup ();
1808 write_long (insn, fixups);
1809 prev_opcode = NULL;
1810 return;
1813 if (prev_opcode
1814 && prev_seg
1815 && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
1816 d10v_cleanup ();
1818 if (prev_opcode
1819 && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype,
1820 fixups)))
1822 /* No instructions saved. */
1823 prev_opcode = NULL;
1825 else
1827 if (extype != PACK_UNSPEC)
1828 as_fatal (_("Unable to mix instructions as specified"));
1829 /* Save last instruction so it may be packed on next pass. */
1830 prev_opcode = opcode;
1831 prev_insn = insn;
1832 prev_seg = now_seg;
1833 prev_subseg = now_subseg;
1834 fixups = fixups->next;