opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009, 2010
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* ABM New Instructions required */
  88   CpuABM,
  89   /* SSE4.1 support required */
  90   CpuSSE4_1,
  91   /* SSE4.2 support required */
  92   CpuSSE4_2,
  93   /* AVX support required */
  94   CpuAVX,
  95   /* Intel L1OM support required */
  96   CpuL1OM,
  97   /* Xsave/xrstor New Instructions support required */
  98   CpuXsave,
  99   /* Xsaveopt New Instructions support required */
 100   CpuXsaveopt,
 101   /* AES support required */
 102   CpuAES,
 103   /* PCLMUL support required */
 104   CpuPCLMUL,
 105   /* FMA support required */
 106   CpuFMA,
 107   /* FMA4 support required */
 108   CpuFMA4,
 109   /* XOP support required */
 110   CpuXOP,
 111   /* LWP support required */
 112   CpuLWP,
 113   /* MOVBE Instruction support required */
 114   CpuMovbe,
 115   /* EPT Instructions required */
 116   CpuEPT,
 117   /* RDTSCP Instruction support required */
 118   CpuRdtscp,
 119   /* FSGSBASE Instructions required */
 120   CpuFSGSBase,
 121   /* RDRND Instructions required */
 122   CpuRdRnd,
 123   /* F16C Instructions required */
 124   CpuF16C,
 125   /* 64bit support available, used by -march= in assembler.  */
 126   CpuLM,
 127   /* 64bit support required  */
 128   Cpu64,
 129   /* Not supported in the 64bit mode  */
 130   CpuNo64,
 131   /* The last bitfield in i386_cpu_flags.  */
 132   CpuMax = CpuNo64
 133 };
 134
 135 #define CpuNumOfUints \
 136   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 137 #define CpuNumOfBits \
 138   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 139
 140 /* If you get a compiler error for zero width of the unused field,
 141    comment it out.  */
 142 #define CpuUnused       (CpuMax + 1)
 143
 144 /* We can check if an instruction is available with array instead
 145    of bitfield. */
 146 typedef union i386_cpu_flags
 147 {
 148   struct
 149     {
 150       unsigned int cpui186:1;
 151       unsigned int cpui286:1;
 152       unsigned int cpui386:1;
 153       unsigned int cpui486:1;
 154       unsigned int cpui586:1;
 155       unsigned int cpui686:1;
 156       unsigned int cpuclflush:1;
 157       unsigned int cpunop:1;
 158       unsigned int cpusyscall:1;
 159       unsigned int cpu8087:1;
 160       unsigned int cpu287:1;
 161       unsigned int cpu387:1;
 162       unsigned int cpu687:1;
 163       unsigned int cpufisttp:1;
 164       unsigned int cpummx:1;
 165       unsigned int cpusse:1;
 166       unsigned int cpusse2:1;
 167       unsigned int cpua3dnow:1;
 168       unsigned int cpua3dnowa:1;
 169       unsigned int cpusse3:1;
 170       unsigned int cpupadlock:1;
 171       unsigned int cpusvme:1;
 172       unsigned int cpuvmx:1;
 173       unsigned int cpusmx:1;
 174       unsigned int cpussse3:1;
 175       unsigned int cpusse4a:1;
 176       unsigned int cpuabm:1;
 177       unsigned int cpusse4_1:1;
 178       unsigned int cpusse4_2:1;
 179       unsigned int cpuavx:1;
 180       unsigned int cpul1om:1;
 181       unsigned int cpuxsave:1;
 182       unsigned int cpuxsaveopt:1;
 183       unsigned int cpuaes:1;
 184       unsigned int cpupclmul:1;
 185       unsigned int cpufma:1;
 186       unsigned int cpufma4:1;
 187       unsigned int cpuxop:1;
 188       unsigned int cpulwp:1;
 189       unsigned int cpumovbe:1;
 190       unsigned int cpuept:1;
 191       unsigned int cpurdtscp:1;
 192       unsigned int cpufsgsbase:1;
 193       unsigned int cpurdrnd:1;
 194       unsigned int cpuf16c:1;
 195       unsigned int cpulm:1;
 196       unsigned int cpu64:1;
 197       unsigned int cpuno64:1;
 198 #ifdef CpuUnused
 199       unsigned int unused:(CpuNumOfBits - CpuUnused);
 200 #endif
 201     } bitfield;
 202   unsigned int array[CpuNumOfUints];
 203 } i386_cpu_flags;
 204
 205 /* Position of opcode_modifier bits.  */
 206
 207 enum
 208 {
 209   /* has direction bit. */
 210   D = 0,
 211   /* set if operands can be words or dwords encoded the canonical way */
 212   W,
 213   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 214      operand in encoding.  */
 215   S,
 216   /* insn has a modrm byte. */
 217   Modrm,
 218   /* register is in low 3 bits of opcode */
 219   ShortForm,
 220   /* special case for jump insns.  */
 221   Jump,
 222   /* call and jump */
 223   JumpDword,
 224   /* loop and jecxz */
 225   JumpByte,
 226   /* special case for intersegment leaps/calls */
 227   JumpInterSegment,
 228   /* FP insn memory format bit, sized by 0x4 */
 229   FloatMF,
 230   /* src/dest swap for floats. */
 231   FloatR,
 232   /* has float insn direction bit. */
 233   FloatD,
 234   /* needs size prefix if in 32-bit mode */
 235   Size16,
 236   /* needs size prefix if in 16-bit mode */
 237   Size32,
 238   /* needs size prefix if in 64-bit mode */
 239   Size64,
 240   /* check register size.  */
 241   CheckRegSize,
 242   /* instruction ignores operand size prefix and in Intel mode ignores
 243      mnemonic size suffix check.  */
 244   IgnoreSize,
 245   /* default insn size depends on mode */
 246   DefaultSize,
 247   /* b suffix on instruction illegal */
 248   No_bSuf,
 249   /* w suffix on instruction illegal */
 250   No_wSuf,
 251   /* l suffix on instruction illegal */
 252   No_lSuf,
 253   /* s suffix on instruction illegal */
 254   No_sSuf,
 255   /* q suffix on instruction illegal */
 256   No_qSuf,
 257   /* long double suffix on instruction illegal */
 258   No_ldSuf,
 259   /* instruction needs FWAIT */
 260   FWait,
 261   /* quick test for string instructions */
 262   IsString,
 263   /* quick test for lockable instructions */
 264   IsLockable,
 265   /* fake an extra reg operand for clr, imul and special register
 266      processing for some instructions.  */
 267   RegKludge,
 268   /* The first operand must be xmm0 */
 269   FirstXmm0,
 270   /* An implicit xmm0 as the first operand */
 271   Implicit1stXmm0,
 272   /* Convert to DWORD */
 273   ToDword,
 274   /* Convert to QWORD */
 275   ToQword,
 276   /* Address prefix changes operand 0 */
 277   AddrPrefixOp0,
 278   /* opcode is a prefix */
 279   IsPrefix,
 280   /* instruction has extension in 8 bit imm */
 281   ImmExt,
 282   /* instruction don't need Rex64 prefix.  */
 283   NoRex64,
 284   /* instruction require Rex64 prefix.  */
 285   Rex64,
 286   /* deprecated fp insn, gets a warning */
 287   Ugh,
 288   /* insn has VEX prefix:
 289         1: 128bit VEX prefix.
 290         2: 256bit VEX prefix.
 291         3: Scalar VEX prefix.
 292    */
 293 #define VEX128          1
 294 #define VEX256          2
 295 #define VEXScalar       3
 296   Vex,
 297   /* How to encode VEX.vvvv:
 298      0: VEX.vvvv must be 1111b.
 299      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 300         the content of source registers will be preserved.
 301         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 302         where the content of first source register will be overwritten
 303         by the result.
 304         For assembler, there are no difference between VEX.NDS and
 305         VEX.DDS.
 306      2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
 307      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 308         of the operands can access a memory location.
 309    */
 310 #define VEXXDS  1
 311 #define VEXNDD  2
 312 #define VEXLWP  3
 313   VexVVVV,
 314   /* How the VEX.W bit is used:
 315      0: Set by the REX.W bit.
 316      1: VEX.W0.  Should always be 0.
 317      2: VEX.W1.  Should always be 1.
 318    */
 319 #define VEXW0   1
 320 #define VEXW1   2
 321   VexW,
 322   /* VEX opcode prefix:
 323      0: VEX 0x0F opcode prefix.
 324      1: VEX 0x0F38 opcode prefix.
 325      2: VEX 0x0F3A opcode prefix
 326      3: XOP 0x08 opcode prefix.
 327      4: XOP 0x09 opcode prefix
 328      5: XOP 0x0A opcode prefix.
 329    */
 330 #define VEX0F           0
 331 #define VEX0F38         1
 332 #define VEX0F3A         2
 333 #define XOP08           3
 334 #define XOP09           4
 335 #define XOP0A           5
 336   VexOpcode,
 337   /* number of VEX source operands:
 338      0: <= 2 source operands.
 339      1: 2 XOP source operands.
 340      2: 3 source operands.
 341    */
 342 #define XOP2SOURCES     1
 343 #define VEX3SOURCES     2
 344   VexSources,
 345   /* instruction has VEX 8 bit imm */
 346   VexImmExt,
 347   /* SSE to AVX support required */
 348   SSE2AVX,
 349   /* No AVX equivalent */
 350   NoAVX,
 351   /* Compatible with old (<= 2.8.1) versions of gcc  */
 352   OldGcc,
 353   /* AT&T mnemonic.  */
 354   ATTMnemonic,
 355   /* AT&T syntax.  */
 356   ATTSyntax,
 357   /* Intel syntax.  */
 358   IntelSyntax,
 359   /* The last bitfield in i386_opcode_modifier.  */
 360   Opcode_Modifier_Max
 361 };
 362
 363 typedef struct i386_opcode_modifier
 364 {
 365   unsigned int d:1;
 366   unsigned int w:1;
 367   unsigned int s:1;
 368   unsigned int modrm:1;
 369   unsigned int shortform:1;
 370   unsigned int jump:1;
 371   unsigned int jumpdword:1;
 372   unsigned int jumpbyte:1;
 373   unsigned int jumpintersegment:1;
 374   unsigned int floatmf:1;
 375   unsigned int floatr:1;
 376   unsigned int floatd:1;
 377   unsigned int size16:1;
 378   unsigned int size32:1;
 379   unsigned int size64:1;
 380   unsigned int checkregsize:1;
 381   unsigned int ignoresize:1;
 382   unsigned int defaultsize:1;
 383   unsigned int no_bsuf:1;
 384   unsigned int no_wsuf:1;
 385   unsigned int no_lsuf:1;
 386   unsigned int no_ssuf:1;
 387   unsigned int no_qsuf:1;
 388   unsigned int no_ldsuf:1;
 389   unsigned int fwait:1;
 390   unsigned int isstring:1;
 391   unsigned int islockable:1;
 392   unsigned int regkludge:1;
 393   unsigned int firstxmm0:1;
 394   unsigned int implicit1stxmm0:1;
 395   unsigned int todword:1;
 396   unsigned int toqword:1;
 397   unsigned int addrprefixop0:1;
 398   unsigned int isprefix:1;
 399   unsigned int immext:1;
 400   unsigned int norex64:1;
 401   unsigned int rex64:1;
 402   unsigned int ugh:1;
 403   unsigned int vex:2;
 404   unsigned int vexvvvv:2;
 405   unsigned int vexw:2;
 406   unsigned int vexopcode:3;
 407   unsigned int vexsources:2;
 408   unsigned int veximmext:1;
 409   unsigned int sse2avx:1;
 410   unsigned int noavx:1;
 411   unsigned int oldgcc:1;
 412   unsigned int attmnemonic:1;
 413   unsigned int attsyntax:1;
 414   unsigned int intelsyntax:1;
 415 } i386_opcode_modifier;
 416
 417 /* Position of operand_type bits.  */
 418
 419 enum
 420 {
 421   /* 8bit register */
 422   Reg8 = 0,
 423   /* 16bit register */
 424   Reg16,
 425   /* 32bit register */
 426   Reg32,
 427   /* 64bit register */
 428   Reg64,
 429   /* Floating pointer stack register */
 430   FloatReg,
 431   /* MMX register */
 432   RegMMX,
 433   /* SSE register */
 434   RegXMM,
 435   /* AVX registers */
 436   RegYMM,
 437   /* Control register */
 438   Control,
 439   /* Debug register */
 440   Debug,
 441   /* Test register */
 442   Test,
 443   /* 2 bit segment register */
 444   SReg2,
 445   /* 3 bit segment register */
 446   SReg3,
 447   /* 1 bit immediate */
 448   Imm1,
 449   /* 8 bit immediate */
 450   Imm8,
 451   /* 8 bit immediate sign extended */
 452   Imm8S,
 453   /* 16 bit immediate */
 454   Imm16,
 455   /* 32 bit immediate */
 456   Imm32,
 457   /* 32 bit immediate sign extended */
 458   Imm32S,
 459   /* 64 bit immediate */
 460   Imm64,
 461   /* 8bit/16bit/32bit displacements are used in different ways,
 462      depending on the instruction.  For jumps, they specify the
 463      size of the PC relative displacement, for instructions with
 464      memory operand, they specify the size of the offset relative
 465      to the base register, and for instructions with memory offset
 466      such as `mov 1234,%al' they specify the size of the offset
 467      relative to the segment base.  */
 468   /* 8 bit displacement */
 469   Disp8,
 470   /* 16 bit displacement */
 471   Disp16,
 472   /* 32 bit displacement */
 473   Disp32,
 474   /* 32 bit signed displacement */
 475   Disp32S,
 476   /* 64 bit displacement */
 477   Disp64,
 478   /* Accumulator %al/%ax/%eax/%rax */
 479   Acc,
 480   /* Floating pointer top stack register %st(0) */
 481   FloatAcc,
 482   /* Register which can be used for base or index in memory operand.  */
 483   BaseIndex,
 484   /* Register to hold in/out port addr = dx */
 485   InOutPortReg,
 486   /* Register to hold shift count = cl */
 487   ShiftCount,
 488   /* Absolute address for jump.  */
 489   JumpAbsolute,
 490   /* String insn operand with fixed es segment */
 491   EsSeg,
 492   /* RegMem is for instructions with a modrm byte where the register
 493      destination operand should be encoded in the mod and regmem fields.
 494      Normally, it will be encoded in the reg field. We add a RegMem
 495      flag to the destination register operand to indicate that it should
 496      be encoded in the regmem field.  */
 497   RegMem,
 498   /* Memory.  */
 499   Mem,
 500   /* BYTE memory. */
 501   Byte,
 502   /* WORD memory. 2 byte */
 503   Word,
 504   /* DWORD memory. 4 byte */
 505   Dword,
 506   /* FWORD memory. 6 byte */
 507   Fword,
 508   /* QWORD memory. 8 byte */
 509   Qword,
 510   /* TBYTE memory. 10 byte */
 511   Tbyte,
 512   /* XMMWORD memory. */
 513   Xmmword,
 514   /* YMMWORD memory. */
 515   Ymmword,
 516   /* Unspecified memory size.  */
 517   Unspecified,
 518   /* Any memory size.  */
 519   Anysize,
 520
 521   /* Vector 4 bit immediate.  */
 522   Vec_Imm4,
 523
 524   /* The last bitfield in i386_operand_type.  */
 525   OTMax
 526 };
 527
 528 #define OTNumOfUints \
 529   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 530 #define OTNumOfBits \
 531   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 532
 533 /* If you get a compiler error for zero width of the unused field,
 534    comment it out.  */
 535 #define OTUnused                (OTMax + 1)
 536
 537 typedef union i386_operand_type
 538 {
 539   struct
 540     {
 541       unsigned int reg8:1;
 542       unsigned int reg16:1;
 543       unsigned int reg32:1;
 544       unsigned int reg64:1;
 545       unsigned int floatreg:1;
 546       unsigned int regmmx:1;
 547       unsigned int regxmm:1;
 548       unsigned int regymm:1;
 549       unsigned int control:1;
 550       unsigned int debug:1;
 551       unsigned int test:1;
 552       unsigned int sreg2:1;
 553       unsigned int sreg3:1;
 554       unsigned int imm1:1;
 555       unsigned int imm8:1;
 556       unsigned int imm8s:1;
 557       unsigned int imm16:1;
 558       unsigned int imm32:1;
 559       unsigned int imm32s:1;
 560       unsigned int imm64:1;
 561       unsigned int disp8:1;
 562       unsigned int disp16:1;
 563       unsigned int disp32:1;
 564       unsigned int disp32s:1;
 565       unsigned int disp64:1;
 566       unsigned int acc:1;
 567       unsigned int floatacc:1;
 568       unsigned int baseindex:1;
 569       unsigned int inoutportreg:1;
 570       unsigned int shiftcount:1;
 571       unsigned int jumpabsolute:1;
 572       unsigned int esseg:1;
 573       unsigned int regmem:1;
 574       unsigned int mem:1;
 575       unsigned int byte:1;
 576       unsigned int word:1;
 577       unsigned int dword:1;
 578       unsigned int fword:1;
 579       unsigned int qword:1;
 580       unsigned int tbyte:1;
 581       unsigned int xmmword:1;
 582       unsigned int ymmword:1;
 583       unsigned int unspecified:1;
 584       unsigned int anysize:1;
 585       unsigned int vec_imm4:1;
 586 #ifdef OTUnused
 587       unsigned int unused:(OTNumOfBits - OTUnused);
 588 #endif
 589     } bitfield;
 590   unsigned int array[OTNumOfUints];
 591 } i386_operand_type;
 592
 593 typedef struct insn_template
 594 {
 595   /* instruction name sans width suffix ("mov" for movl insns) */
 596   char *name;
 597
 598   /* how many operands */
 599   unsigned int operands;
 600
 601   /* base_opcode is the fundamental opcode byte without optional
 602      prefix(es).  */
 603   unsigned int base_opcode;
 604 #define Opcode_D        0x2 /* Direction bit:
 605                                set if Reg --> Regmem;
 606                                unset if Regmem --> Reg. */
 607 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 608 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 609
 610   /* extension_opcode is the 3 bit extension for group <n> insns.
 611      This field is also used to store the 8-bit opcode suffix for the
 612      AMD 3DNow! instructions.
 613      If this template has no extension opcode (the usual case) use None
 614      Instructions */
 615   unsigned int extension_opcode;
 616 #define None 0xffff             /* If no extension_opcode is possible.  */
 617
 618   /* Opcode length.  */
 619   unsigned char opcode_length;
 620
 621   /* cpu feature flags */
 622   i386_cpu_flags cpu_flags;
 623
 624   /* the bits in opcode_modifier are used to generate the final opcode from
 625      the base_opcode.  These bits also are used to detect alternate forms of
 626      the same instruction */
 627   i386_opcode_modifier opcode_modifier;
 628
 629   /* operand_types[i] describes the type of operand i.  This is made
 630      by OR'ing together all of the possible type masks.  (e.g.
 631      'operand_types[i] = Reg|Imm' specifies that operand i can be
 632      either a register or an immediate operand.  */
 633   i386_operand_type operand_types[MAX_OPERANDS];
 634 }
 635 insn_template;
 636
 637 extern const insn_template i386_optab[];
 638
 639 /* these are for register name --> number & type hash lookup */
 640 typedef struct
 641 {
 642   char *reg_name;
 643   i386_operand_type reg_type;
 644   unsigned char reg_flags;
 645 #define RegRex      0x1  /* Extended register.  */
 646 #define RegRex64    0x2  /* Extended 8 bit register.  */
 647   unsigned char reg_num;
 648 #define RegRip  ((unsigned char ) ~0)
 649 #define RegEip  (RegRip - 1)
 650 /* EIZ and RIZ are fake index registers.  */
 651 #define RegEiz  (RegEip - 1)
 652 #define RegRiz  (RegEiz - 1)
 653 /* FLAT is a fake segment register (Intel mode).  */
 654 #define RegFlat     ((unsigned char) ~0)
 655   signed char dw2_regnum[2];
 656 #define Dw2Inval (-1)
 657 }
 658 reg_entry;
 659
 660 /* Entries in i386_regtab.  */
 661 #define REGNAM_AL 1
 662 #define REGNAM_AX 25
 663 #define REGNAM_EAX 41
 664
 665 extern const reg_entry i386_regtab[];
 666 extern const unsigned int i386_regtab_size;
 667
 668 typedef struct
 669 {
 670   char *seg_name;
 671   unsigned int seg_prefix;
 672 }
 673 seg_entry;
 674
 675 extern const seg_entry cs;
 676 extern const seg_entry ds;
 677 extern const seg_entry ss;
 678 extern const seg_entry es;
 679 extern const seg_entry fs;
 680 extern const seg_entry gs;