?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Cosmetic changes to tc-i386.[ch] + extend x86 gas testsuite jmp and
[binutils.git] / include / opcode / i386.h
blob7bddbed4e6d5d3e51f8124407df8b29cbe21d9b5
1 /* opcode/i386.h -- Intel 80386 opcode table
2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation.
3
4 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19
20 /* The UnixWare assembler, and probably other AT&T derived ix86 Unix
21 assemblers, generate floating point instructions with reversed
22 source and destination registers in certain cases. Unfortunately,
23 gcc and possibly many other programs use this reversed syntax, so
24 we're stuck with it.
25
26 eg. `fsub %st(3),%st' results in st <- st - st(3) as expected, but
27 `fsub %st,%st(3)' results in st(3) <- st - st(3), rather than
28 the expected st(3) <- st(3) - st !
29
30 This happens with all the non-commutative arithmetic floating point
31 operations with two register operands, where the source register is
32 %st, and destination register is %st(i). Look for FloatDR below. */
33
34 #ifndef UNIXWARE_COMPAT
35 /* Set non-zero for broken, compatible instructions. Set to zero for
36 non-broken opcodes at your peril. gcc generates UnixWare
37 compatible instructions. */
38 #define UNIXWARE_COMPAT 1
39 #endif
40
41
42 static const template i386_optab[] = {
43
44 #define X None
45 #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
46 #define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
47 #define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
48 #define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_dSuf|No_xSuf)
49 #define d_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf)
50 #define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_dSuf)
51 #define bw_Suf (No_lSuf|No_sSuf|No_dSuf|No_xSuf)
52 #define bl_Suf (No_wSuf|No_sSuf|No_dSuf|No_xSuf)
53 #define wl_Suf (No_bSuf|No_sSuf|No_dSuf|No_xSuf)
54 #define sl_Suf (No_bSuf|No_wSuf|No_dSuf|No_xSuf)
55 #define sld_Suf (No_bSuf|No_wSuf|No_xSuf)
56 #define sldx_Suf (No_bSuf|No_wSuf)
57 #define bwl_Suf (No_sSuf|No_dSuf|No_xSuf)
58 #define bwld_Suf (No_sSuf|No_xSuf)
59 #define FP (NoSuf|IgnoreSize)
60 #define l_FP (l_Suf|IgnoreSize)
61 #define d_FP (d_Suf|IgnoreSize)
62 #define x_FP (x_Suf|IgnoreSize)
63 #define sl_FP (sl_Suf|IgnoreSize)
64 #define sld_FP (sld_Suf|IgnoreSize)
65 #define sldx_FP (sldx_Suf|IgnoreSize)
66 #if UNIXWARE_COMPAT
67 #define FloatDR FloatD
68 #else
69 #define FloatDR (FloatD|FloatR)
70 #endif
71
72 /* move instructions */
73 #define MOV_AX_DISP32 0xa0
74 { "mov", 2, 0xa0, X, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
75 { "mov", 2, 0x88, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } },
76 { "mov", 2, 0xb0, X, bwl_Suf|W|ShortForm, { Imm, Reg, 0 } },
77 { "mov", 2, 0xc6, X, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0 } },
78 /* The next two instructions accept WordReg so that a segment register
79 can be copied to a 32 bit register, and vice versa, without using a
80 size prefix. When moving to a 32 bit register, the upper 16 bits
81 are set to an implementation defined value (on the Pentium Pro,
82 the implementation defined value is zero). */
83 { "mov", 2, 0x8c, X, wl_Suf|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } },
84 { "mov", 2, 0x8e, X, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3|SReg2, 0 } },
85 /* move to/from control debug registers */
86 { "mov", 2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32|InvMem, 0} },
87 { "mov", 2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32|InvMem, 0} },
88 { "mov", 2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} },
89
90 /* move with sign extend */
91 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
92 conflict with the "movs" string move instruction. */
93 {"movsbl", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} },
94 {"movsbw", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} },
95 {"movswl", 2, 0x0fbf, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} },
96 /* Intel Syntax */
97 {"movsx", 2, 0x0fbf, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} },
98 {"movsx", 2, 0x0fbe, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
99
100 /* move with zero extend */
101 {"movzb", 2, 0x0fb6, X, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
102 {"movzwl", 2, 0x0fb7, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} },
103 /* Intel Syntax */
104 {"movzx", 2, 0x0fb7, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} },
105 {"movzx", 2, 0x0fb6, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
106
107 /* push instructions */
108 {"push", 1, 0x50, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
109 {"push", 1, 0xff, 6, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
110 {"push", 1, 0x6a, X, wl_Suf|DefaultSize, { Imm8S, 0, 0} },
111 {"push", 1, 0x68, X, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} },
112 {"push", 1, 0x06, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
113 {"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
114 /* push all */
115 {"pusha", 0, 0x60, X, wl_Suf|DefaultSize, { 0, 0, 0 } },
116
117 /* pop instructions */
118 {"pop", 1, 0x58, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
119 {"pop", 1, 0x8f, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
120 #define POP_SEG_SHORT 0x07
121 {"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
122 {"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
123 /* pop all */
124 {"popa", 0, 0x61, X, wl_Suf|DefaultSize, { 0, 0, 0 } },
125
126 /* xchg exchange instructions
127 xchg commutes: we allow both operand orders */
128 {"xchg", 2, 0x90, X, wl_Suf|ShortForm, { WordReg, Acc, 0 } },
129 {"xchg", 2, 0x90, X, wl_Suf|ShortForm, { Acc, WordReg, 0 } },
130 {"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
131 {"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } },
132
133 /* in/out from ports */
134 {"in", 2, 0xe4, X, bwl_Suf|W, { Imm8, Acc, 0 } },
135 {"in", 2, 0xec, X, bwl_Suf|W, { InOutPortReg, Acc, 0 } },
136 {"in", 1, 0xe4, X, bwl_Suf|W, { Imm8, 0, 0 } },
137 {"in", 1, 0xec, X, bwl_Suf|W, { InOutPortReg, 0, 0 } },
138 {"out", 2, 0xe6, X, bwl_Suf|W, { Acc, Imm8, 0 } },
139 {"out", 2, 0xee, X, bwl_Suf|W, { Acc, InOutPortReg, 0 } },
140 {"out", 1, 0xe6, X, bwl_Suf|W, { Imm8, 0, 0 } },
141 {"out", 1, 0xee, X, bwl_Suf|W, { InOutPortReg, 0, 0 } },
142
143 /* load effective address */
144 {"lea", 2, 0x8d, X, wl_Suf|Modrm, { WordMem, WordReg, 0 } },
145
146 /* load segment registers from memory */
147 {"lds", 2, 0xc5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
148 {"les", 2, 0xc4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
149 {"lfs", 2, 0x0fb4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
150 {"lgs", 2, 0x0fb5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
151 {"lss", 2, 0x0fb2, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
152
153 /* flags register instructions */
154 {"clc", 0, 0xf8, X, NoSuf, { 0, 0, 0} },
155 {"cld", 0, 0xfc, X, NoSuf, { 0, 0, 0} },
156 {"cli", 0, 0xfa, X, NoSuf, { 0, 0, 0} },
157 {"clts", 0, 0x0f06, X, NoSuf, { 0, 0, 0} },
158 {"cmc", 0, 0xf5, X, NoSuf, { 0, 0, 0} },
159 {"lahf", 0, 0x9f, X, NoSuf, { 0, 0, 0} },
160 {"sahf", 0, 0x9e, X, NoSuf, { 0, 0, 0} },
161 {"pushf", 0, 0x9c, X, wl_Suf|DefaultSize, { 0, 0, 0} },
162 {"popf", 0, 0x9d, X, wl_Suf|DefaultSize, { 0, 0, 0} },
163 {"stc", 0, 0xf9, X, NoSuf, { 0, 0, 0} },
164 {"std", 0, 0xfd, X, NoSuf, { 0, 0, 0} },
165 {"sti", 0, 0xfb, X, NoSuf, { 0, 0, 0} },
166
167 /* arithmetic */
168 {"add", 2, 0x00, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
169 {"add", 2, 0x83, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
170 {"add", 2, 0x04, X, bwl_Suf|W, { Imm, Acc, 0} },
171 {"add", 2, 0x80, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
172
173 {"inc", 1, 0x40, X, wl_Suf|ShortForm, { WordReg, 0, 0} },
174 {"inc", 1, 0xfe, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
175
176 {"sub", 2, 0x28, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
177 {"sub", 2, 0x83, 5, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
178 {"sub", 2, 0x2c, X, bwl_Suf|W, { Imm, Acc, 0} },
179 {"sub", 2, 0x80, 5, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
180
181 {"dec", 1, 0x48, X, wl_Suf|ShortForm, { WordReg, 0, 0} },
182 {"dec", 1, 0xfe, 1, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
183
184 {"sbb", 2, 0x18, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
185 {"sbb", 2, 0x83, 3, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
186 {"sbb", 2, 0x1c, X, bwl_Suf|W, { Imm, Acc, 0} },
187 {"sbb", 2, 0x80, 3, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
188
189 {"cmp", 2, 0x38, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
190 {"cmp", 2, 0x83, 7, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
191 {"cmp", 2, 0x3c, X, bwl_Suf|W, { Imm, Acc, 0} },
192 {"cmp", 2, 0x80, 7, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
193
194 {"test", 2, 0x84, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} },
195 {"test", 2, 0x84, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} },
196 {"test", 2, 0xa8, X, bwl_Suf|W, { Imm, Acc, 0} },
197 {"test", 2, 0xf6, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
198
199 {"and", 2, 0x20, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
200 {"and", 2, 0x83, 4, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
201 {"and", 2, 0x24, X, bwl_Suf|W, { Imm, Acc, 0} },
202 {"and", 2, 0x80, 4, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
203
204 {"or", 2, 0x08, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
205 {"or", 2, 0x83, 1, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
206 {"or", 2, 0x0c, X, bwl_Suf|W, { Imm, Acc, 0} },
207 {"or", 2, 0x80, 1, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
208
209 {"xor", 2, 0x30, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
210 {"xor", 2, 0x83, 6, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
211 {"xor", 2, 0x34, X, bwl_Suf|W, { Imm, Acc, 0} },
212 {"xor", 2, 0x80, 6, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
213
214 /* iclr with 1 operand is really xor with 2 operands. */
215 {"clr", 1, 0x30, X, bwl_Suf|W|Modrm|regKludge, { Reg, 0, 0 } },
216
217 {"adc", 2, 0x10, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
218 {"adc", 2, 0x83, 2, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
219 {"adc", 2, 0x14, X, bwl_Suf|W, { Imm, Acc, 0} },
220 {"adc", 2, 0x80, 2, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
221
222 {"neg", 1, 0xf6, 3, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
223 {"not", 1, 0xf6, 2, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
224
225 {"aaa", 0, 0x37, X, NoSuf, { 0, 0, 0} },
226 {"aas", 0, 0x3f, X, NoSuf, { 0, 0, 0} },
227 {"daa", 0, 0x27, X, NoSuf, { 0, 0, 0} },
228 {"das", 0, 0x2f, X, NoSuf, { 0, 0, 0} },
229 {"aad", 0, 0xd50a, X, NoSuf, { 0, 0, 0} },
230 {"aad", 1, 0xd5, X, NoSuf, { Imm8S, 0, 0} },
231 {"aam", 0, 0xd40a, X, NoSuf, { 0, 0, 0} },
232 {"aam", 1, 0xd4, X, NoSuf, { Imm8S, 0, 0} },
233
234 /* conversion insns */
235 /* conversion: intel naming */
236 {"cbw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} },
237 {"cwde", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} },
238 {"cwd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} },
239 {"cdq", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} },
240 /* att naming */
241 {"cbtw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} },
242 {"cwtl", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} },
243 {"cwtd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} },
244 {"cltd", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} },
245
246 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
247 expanding 64-bit multiplies, and *cannot* be selected to accomplish
248 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
249 These multiplies can only be selected with single operand forms. */
250 {"mul", 1, 0xf6, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
251 {"imul", 1, 0xf6, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
252 {"imul", 2, 0x0faf, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
253 {"imul", 3, 0x6b, X, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} },
254 {"imul", 3, 0x69, X, wl_Suf|Modrm, { Imm16|Imm32, WordReg|WordMem, WordReg} },
255 /* imul with 2 operands mimics imul with 3 by putting the register in
256 both i.rm.reg & i.rm.regmem fields. regKludge enables this
257 transformation. */
258 {"imul", 2, 0x6b, X, wl_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
259 {"imul", 2, 0x69, X, wl_Suf|Modrm|regKludge,{ Imm16|Imm32, WordReg, 0} },
260
261 {"div", 1, 0xf6, 6, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
262 {"div", 2, 0xf6, 6, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
263 {"idiv", 1, 0xf6, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
264 {"idiv", 2, 0xf6, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
265
266 {"rol", 2, 0xd0, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
267 {"rol", 2, 0xc0, 0, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
268 {"rol", 2, 0xd2, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
269 {"rol", 1, 0xd0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
270
271 {"ror", 2, 0xd0, 1, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
272 {"ror", 2, 0xc0, 1, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
273 {"ror", 2, 0xd2, 1, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
274 {"ror", 1, 0xd0, 1, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
275
276 {"rcl", 2, 0xd0, 2, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
277 {"rcl", 2, 0xc0, 2, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
278 {"rcl", 2, 0xd2, 2, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
279 {"rcl", 1, 0xd0, 2, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
280
281 {"rcr", 2, 0xd0, 3, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
282 {"rcr", 2, 0xc0, 3, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
283 {"rcr", 2, 0xd2, 3, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
284 {"rcr", 1, 0xd0, 3, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
285
286 {"sal", 2, 0xd0, 4, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
287 {"sal", 2, 0xc0, 4, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
288 {"sal", 2, 0xd2, 4, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
289 {"sal", 1, 0xd0, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
290 {"shl", 2, 0xd0, 4, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
291 {"shl", 2, 0xc0, 4, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
292 {"shl", 2, 0xd2, 4, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
293 {"shl", 1, 0xd0, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
294
295 {"shld", 3, 0x0fa4, X, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
296 {"shld", 3, 0x0fa5, X, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
297 {"shld", 2, 0x0fa5, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
298
299 {"shr", 2, 0xd0, 5, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
300 {"shr", 2, 0xc0, 5, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
301 {"shr", 2, 0xd2, 5, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
302 {"shr", 1, 0xd0, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
303
304 {"shrd", 3, 0x0fac, X, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
305 {"shrd", 3, 0x0fad, X, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
306 {"shrd", 2, 0x0fad, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
307
308 {"sar", 2, 0xd0, 7, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
309 {"sar", 2, 0xc0, 7, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
310 {"sar", 2, 0xd2, 7, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
311 {"sar", 1, 0xd0, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
312
313 /* control transfer instructions */
314 {"call", 1, 0xe8, X, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },
315 {"call", 1, 0xff, 2, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} },
316 /* Intel Syntax */
317 {"call", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
318 /* Intel Syntax */
319 {"call", 1, 0xff, 3, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} },
320 {"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
321 {"lcall", 1, 0xff, 3, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} },
322
323 #define JUMP_PC_RELATIVE 0xeb
324 {"jmp", 1, 0xeb, X, NoSuf|Jump, { Disp, 0, 0} },
325 {"jmp", 1, 0xff, 4, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
326 /* Intel Syntax */
327 {"jmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
328 /* Intel Syntax */
329 {"jmp", 1, 0xff, 5, x_Suf|Modrm, { WordMem, 0, 0} },
330 {"ljmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
331 {"ljmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} },
332
333 {"ret", 0, 0xc3, X, wl_Suf|DefaultSize, { 0, 0, 0} },
334 {"ret", 1, 0xc2, X, wl_Suf|DefaultSize, { Imm16, 0, 0} },
335 {"lret", 0, 0xcb, X, wl_Suf|DefaultSize, { 0, 0, 0} },
336 {"lret", 1, 0xca, X, wl_Suf|DefaultSize, { Imm16, 0, 0} },
337 {"enter", 2, 0xc8, X, wl_Suf|DefaultSize, { Imm16, Imm8, 0} },
338 {"leave", 0, 0xc9, X, wl_Suf|DefaultSize, { 0, 0, 0} },
339
340 /* conditional jumps */
341 {"jo", 1, 0x70, X, NoSuf|Jump, { Disp, 0, 0} },
342 {"jno", 1, 0x71, X, NoSuf|Jump, { Disp, 0, 0} },
343 {"jb", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} },
344 {"jc", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} },
345 {"jnae", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} },
346 {"jnb", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} },
347 {"jnc", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} },
348 {"jae", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} },
349 {"je", 1, 0x74, X, NoSuf|Jump, { Disp, 0, 0} },
350 {"jz", 1, 0x74, X, NoSuf|Jump, { Disp, 0, 0} },
351 {"jne", 1, 0x75, X, NoSuf|Jump, { Disp, 0, 0} },
352 {"jnz", 1, 0x75, X, NoSuf|Jump, { Disp, 0, 0} },
353 {"jbe", 1, 0x76, X, NoSuf|Jump, { Disp, 0, 0} },
354 {"jna", 1, 0x76, X, NoSuf|Jump, { Disp, 0, 0} },
355 {"jnbe", 1, 0x77, X, NoSuf|Jump, { Disp, 0, 0} },
356 {"ja", 1, 0x77, X, NoSuf|Jump, { Disp, 0, 0} },
357 {"js", 1, 0x78, X, NoSuf|Jump, { Disp, 0, 0} },
358 {"jns", 1, 0x79, X, NoSuf|Jump, { Disp, 0, 0} },
359 {"jp", 1, 0x7a, X, NoSuf|Jump, { Disp, 0, 0} },
360 {"jpe", 1, 0x7a, X, NoSuf|Jump, { Disp, 0, 0} },
361 {"jnp", 1, 0x7b, X, NoSuf|Jump, { Disp, 0, 0} },
362 {"jpo", 1, 0x7b, X, NoSuf|Jump, { Disp, 0, 0} },
363 {"jl", 1, 0x7c, X, NoSuf|Jump, { Disp, 0, 0} },
364 {"jnge", 1, 0x7c, X, NoSuf|Jump, { Disp, 0, 0} },
365 {"jnl", 1, 0x7d, X, NoSuf|Jump, { Disp, 0, 0} },
366 {"jge", 1, 0x7d, X, NoSuf|Jump, { Disp, 0, 0} },
367 {"jle", 1, 0x7e, X, NoSuf|Jump, { Disp, 0, 0} },
368 {"jng", 1, 0x7e, X, NoSuf|Jump, { Disp, 0, 0} },
369 {"jnle", 1, 0x7f, X, NoSuf|Jump, { Disp, 0, 0} },
370 {"jg", 1, 0x7f, X, NoSuf|Jump, { Disp, 0, 0} },
371
372 /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
373 {"jcxz", 1, 0xe3, X, NoSuf|JumpByte|Size16, { Disp, 0, 0} },
374 {"jecxz", 1, 0xe3, X, NoSuf|JumpByte|Size32, { Disp, 0, 0} },
375
376 /* The loop instructions also use the address size prefix to select
377 %cx rather than %ecx for the loop count, so the `w' form of these
378 instructions emit an address size prefix rather than a data size
379 prefix. */
380 {"loop", 1, 0xe2, X, wl_Suf|JumpByte, { Disp, 0, 0} },
381 {"loopz", 1, 0xe1, X, wl_Suf|JumpByte, { Disp, 0, 0} },
382 {"loope", 1, 0xe1, X, wl_Suf|JumpByte, { Disp, 0, 0} },
383 {"loopnz", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} },
384 {"loopne", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} },
385
386 /* set byte on flag instructions */
387 {"seto", 1, 0x0f90, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
388 {"setno", 1, 0x0f91, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
389 {"setb", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
390 {"setc", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
391 {"setnae", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
392 {"setnb", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
393 {"setnc", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
394 {"setae", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
395 {"sete", 1, 0x0f94, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
396 {"setz", 1, 0x0f94, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
397 {"setne", 1, 0x0f95, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
398 {"setnz", 1, 0x0f95, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
399 {"setbe", 1, 0x0f96, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
400 {"setna", 1, 0x0f96, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
401 {"setnbe", 1, 0x0f97, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
402 {"seta", 1, 0x0f97, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
403 {"sets", 1, 0x0f98, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
404 {"setns", 1, 0x0f99, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
405 {"setp", 1, 0x0f9a, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
406 {"setpe", 1, 0x0f9a, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
407 {"setnp", 1, 0x0f9b, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
408 {"setpo", 1, 0x0f9b, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
409 {"setl", 1, 0x0f9c, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
410 {"setnge", 1, 0x0f9c, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
411 {"setnl", 1, 0x0f9d, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
412 {"setge", 1, 0x0f9d, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
413 {"setle", 1, 0x0f9e, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
414 {"setng", 1, 0x0f9e, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
415 {"setnle", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
416 {"setg", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
417
418 /* string manipulation */
419 {"cmps", 0, 0xa6, X, bwld_Suf|W|IsString, { 0, 0, 0} },
420 {"cmps", 2, 0xa6, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
421 {"scmp", 0, 0xa6, X, bwld_Suf|W|IsString, { 0, 0, 0} },
422 {"scmp", 2, 0xa6, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
423 {"ins", 0, 0x6c, X, bwld_Suf|W|IsString, { 0, 0, 0} },
424 {"ins", 2, 0x6c, X, bwld_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} },
425 {"outs", 0, 0x6e, X, bwld_Suf|W|IsString, { 0, 0, 0} },
426 {"outs", 2, 0x6e, X, bwld_Suf|W|IsString, { AnyMem, InOutPortReg, 0} },
427 {"lods", 0, 0xac, X, bwld_Suf|W|IsString, { 0, 0, 0} },
428 {"lods", 1, 0xac, X, bwld_Suf|W|IsString, { AnyMem, 0, 0} },
429 {"lods", 2, 0xac, X, bwld_Suf|W|IsString, { AnyMem, Acc, 0} },
430 {"slod", 0, 0xac, X, bwld_Suf|W|IsString, { 0, 0, 0} },
431 {"slod", 1, 0xac, X, bwld_Suf|W|IsString, { AnyMem, 0, 0} },
432 {"slod", 2, 0xac, X, bwld_Suf|W|IsString, { AnyMem, Acc, 0} },
433 {"movs", 0, 0xa4, X, bwld_Suf|W|IsString, { 0, 0, 0} },
434 {"movs", 2, 0xa4, X, bwld_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
435 {"smov", 0, 0xa4, X, bwld_Suf|W|IsString, { 0, 0, 0} },
436 {"smov", 2, 0xa4, X, bwld_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
437 {"scas", 0, 0xae, X, bwld_Suf|W|IsString, { 0, 0, 0} },
438 {"scas", 1, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
439 {"scas", 2, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
440 {"ssca", 0, 0xae, X, bwld_Suf|W|IsString, { 0, 0, 0} },
441 {"ssca", 1, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
442 {"ssca", 2, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
443 {"stos", 0, 0xaa, X, bwld_Suf|W|IsString, { 0, 0, 0} },
444 {"stos", 1, 0xaa, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
445 {"stos", 2, 0xaa, X, bwld_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
446 {"ssto", 0, 0xaa, X, bwld_Suf|W|IsString, { 0, 0, 0} },
447 {"ssto", 1, 0xaa, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
448 {"ssto", 2, 0xaa, X, bwld_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
449 {"xlat", 0, 0xd7, X, b_Suf|IsString, { 0, 0, 0} },
450 {"xlat", 1, 0xd7, X, b_Suf|IsString, { AnyMem, 0, 0} },
451
452 /* bit manipulation */
453 {"bsf", 2, 0x0fbc, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
454 {"bsr", 2, 0x0fbd, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
455 {"bt", 2, 0x0fa3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
456 {"bt", 2, 0x0fba, 4, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
457 {"btc", 2, 0x0fbb, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
458 {"btc", 2, 0x0fba, 7, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
459 {"btr", 2, 0x0fb3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
460 {"btr", 2, 0x0fba, 6, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
461 {"bts", 2, 0x0fab, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
462 {"bts", 2, 0x0fba, 5, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
463
464 /* interrupts & op. sys insns */
465 /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
466 int 3 insn. */
467 #define INT_OPCODE 0xcd
468 #define INT3_OPCODE 0xcc
469 {"int", 1, 0xcd, X, NoSuf, { Imm8, 0, 0} },
470 {"int3", 0, 0xcc, X, NoSuf, { 0, 0, 0} },
471 {"into", 0, 0xce, X, NoSuf, { 0, 0, 0} },
472 {"iret", 0, 0xcf, X, wl_Suf, { 0, 0, 0} },
473 /* i386sl, i486sl, later 486, and Pentium */
474 {"rsm", 0, 0x0faa, X, NoSuf, { 0, 0, 0} },
475
476 {"bound", 2, 0x62, X, wl_Suf|Modrm, { WordReg, WordMem, 0} },
477
478 {"hlt", 0, 0xf4, X, NoSuf, { 0, 0, 0} },
479 /* nop is actually 'xchgl %eax, %eax' */
480 {"nop", 0, 0x90, X, NoSuf, { 0, 0, 0} },
481
482 /* protection control */
483 {"arpl", 2, 0x63, X, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
484 {"lar", 2, 0x0f02, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
485 {"lgdt", 1, 0x0f01, 2, wl_Suf|Modrm, { WordMem, 0, 0} },
486 {"lidt", 1, 0x0f01, 3, wl_Suf|Modrm, { WordMem, 0, 0} },
487 {"lldt", 1, 0x0f00, 2, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
488 {"lmsw", 1, 0x0f01, 6, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
489 {"lsl", 2, 0x0f03, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
490 {"ltr", 1, 0x0f00, 3, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
491
492 {"sgdt", 1, 0x0f01, 0, wl_Suf|Modrm, { WordMem, 0, 0} },
493 {"sidt", 1, 0x0f01, 1, wl_Suf|Modrm, { WordMem, 0, 0} },
494 {"sldt", 1, 0x0f00, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} },
495 {"smsw", 1, 0x0f01, 4, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} },
496 {"str", 1, 0x0f00, 1, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
497
498 {"verr", 1, 0x0f00, 4, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
499 {"verw", 1, 0x0f00, 5, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
500
501 /* floating point instructions */
502
503 /* load */
504 {"fld", 1, 0xd9c0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */
505 {"fld", 1, 0xd9, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 <-- mem float/double */
506 {"fld", 1, 0xd9c0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
507 /* Intel Syntax */
508 {"fld", 1, 0xdb, 5, x_FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem efloat */
509 {"fild", 1, 0xdf, 0, sl_Suf|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 <-- mem word(16)/dword(32) */
510 /* Intel Syntax */
511 {"fild", 1, 0xdf, 5, d_Suf|IgnoreSize|Modrm,{ LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */
512 {"fildq", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */
513 {"fildll", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */
514 {"fldt", 1, 0xdb, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem efloat */
515 {"fbld", 1, 0xdf, 4, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem bcd */
516
517 /* store (no pop) */
518 {"fst", 1, 0xddd0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */
519 {"fst", 1, 0xd9, 2, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 --> mem float/double */
520 {"fst", 1, 0xddd0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
521 {"fist", 1, 0xdf, 2, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */
522
523 /* store (with pop) */
524 {"fstp", 1, 0xddd8, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */
525 {"fstp", 1, 0xd9, 3, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 --> mem float/double */
526 {"fstp", 1, 0xddd8, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
527 /* Intel Syntax */
528 {"fstp", 1, 0xdb, 7, x_FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem efloat */
529 {"fistp", 1, 0xdf, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */
530 /* Intel Syntax */
531 {"fistp", 1, 0xdf, 7, d_FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */
532 {"fistpq", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */
533 {"fistpll",1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */
534 {"fstpt", 1, 0xdb, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem efloat */
535 {"fbstp", 1, 0xdf, 6, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem bcd */
536
537 /* exchange %st<n> with %st0 */
538 {"fxch", 1, 0xd9c8, X, FP|ShortForm, { FloatReg, 0, 0} },
539 {"fxch", 0, 0xd9c9, X, FP, { 0, 0, 0} }, /* alias for fxch %st(1) */
540
541 /* comparison (without pop) */
542 {"fcom", 1, 0xd8d0, X, FP|ShortForm, { FloatReg, 0, 0} },
543 {"fcom", 0, 0xd8d1, X, FP, { 0, 0, 0} }, /* alias for fcom %st(1) */
544 {"fcom", 1, 0xd8, 2, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* compare %st0, mem float/double */
545 {"fcom", 1, 0xd8d0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
546 {"ficom", 1, 0xde, 2, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* compare %st0, mem word/dword */
547
548 /* comparison (with pop) */
549 {"fcomp", 1, 0xd8d8, X, FP|ShortForm, { FloatReg, 0, 0} },
550 {"fcomp", 0, 0xd8d9, X, FP, { 0, 0, 0} }, /* alias for fcomp %st(1) */
551 {"fcomp", 1, 0xd8, 3, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* compare %st0, mem float/double */
552 {"fcomp", 1, 0xd8d8, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
553 {"ficomp", 1, 0xde, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* compare %st0, mem word/dword */
554 {"fcompp", 0, 0xded9, X, FP, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */
555
556 /* unordered comparison (with pop) */
557 {"fucom", 1, 0xdde0, X, FP|ShortForm, { FloatReg, 0, 0} },
558 {"fucom", 0, 0xdde1, X, FP, { 0, 0, 0} }, /* alias for fucom %st(1) */
559 {"fucomp", 1, 0xdde8, X, FP|ShortForm, { FloatReg, 0, 0} },
560 {"fucomp", 0, 0xdde9, X, FP, { 0, 0, 0} }, /* alias for fucomp %st(1) */
561 {"fucompp",0, 0xdae9, X, FP, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
562
563 {"ftst", 0, 0xd9e4, X, FP, { 0, 0, 0} }, /* test %st0 */
564 {"fxam", 0, 0xd9e5, X, FP, { 0, 0, 0} }, /* examine %st0 */
565
566 /* load constants into %st0 */
567 {"fld1", 0, 0xd9e8, X, FP, { 0, 0, 0} }, /* %st0 <-- 1.0 */
568 {"fldl2t", 0, 0xd9e9, X, FP, { 0, 0, 0} }, /* %st0 <-- log2(10) */
569 {"fldl2e", 0, 0xd9ea, X, FP, { 0, 0, 0} }, /* %st0 <-- log2(e) */
570 {"fldpi", 0, 0xd9eb, X, FP, { 0, 0, 0} }, /* %st0 <-- pi */
571 {"fldlg2", 0, 0xd9ec, X, FP, { 0, 0, 0} }, /* %st0 <-- log10(2) */
572 {"fldln2", 0, 0xd9ed, X, FP, { 0, 0, 0} }, /* %st0 <-- ln(2) */
573 {"fldz", 0, 0xd9ee, X, FP, { 0, 0, 0} }, /* %st0 <-- 0.0 */
574
575 /* arithmetic */
576
577 /* add */
578 {"fadd", 2, 0xd8c0, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
579 {"fadd", 1, 0xd8c0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for fadd %st(i), %st */
580 #if UNIXWARE_COMPAT
581 {"fadd", 0, 0xdec1, X, FP|Ugh, { 0, 0, 0} }, /* alias for faddp */
582 #endif
583 {"fadd", 1, 0xd8, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
584 {"fiadd", 1, 0xde, 0, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
585
586 {"faddp", 2, 0xdec0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
587 {"faddp", 1, 0xdec0, X, FP|ShortForm, { FloatReg, 0, 0} },
588 {"faddp", 0, 0xdec1, X, FP, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
589 {"faddp", 2, 0xdec0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
590
591 /* subtract */
592 {"fsub", 2, 0xd8e0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
593 {"fsub", 1, 0xd8e0, X, FP|ShortForm, { FloatReg, 0, 0} },
594 #if UNIXWARE_COMPAT
595 {"fsub", 0, 0xdee1, X, FP|Ugh, { 0, 0, 0} }, /* alias for fsubp */
596 #endif
597 {"fsub", 1, 0xd8, 4, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
598 {"fisub", 1, 0xde, 4, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
599
600 #if UNIXWARE_COMPAT
601 {"fsubp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
602 {"fsubp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} },
603 {"fsubp", 0, 0xdee1, X, FP, { 0, 0, 0} },
604 {"fsubp", 2, 0xdee0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
605 #else
606 {"fsubp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
607 {"fsubp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} },
608 {"fsubp", 0, 0xdee9, X, FP, { 0, 0, 0} },
609 #endif
610
611 /* subtract reverse */
612 {"fsubr", 2, 0xd8e8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
613 {"fsubr", 1, 0xd8e8, X, FP|ShortForm, { FloatReg, 0, 0} },
614 #if UNIXWARE_COMPAT
615 {"fsubr", 0, 0xdee9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fsubrp */
616 #endif
617 {"fsubr", 1, 0xd8, 5, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
618 {"fisubr", 1, 0xde, 5, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
619
620 #if UNIXWARE_COMPAT
621 {"fsubrp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
622 {"fsubrp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} },
623 {"fsubrp", 0, 0xdee9, X, FP, { 0, 0, 0} },
624 {"fsubrp", 2, 0xdee8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
625 #else
626 {"fsubrp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
627 {"fsubrp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} },
628 {"fsubrp", 0, 0xdee1, X, FP, { 0, 0, 0} },
629 #endif
630
631 /* multiply */
632 {"fmul", 2, 0xd8c8, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
633 {"fmul", 1, 0xd8c8, X, FP|ShortForm, { FloatReg, 0, 0} },
634 #if UNIXWARE_COMPAT
635 {"fmul", 0, 0xdec9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fmulp */
636 #endif
637 {"fmul", 1, 0xd8, 1, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
638 {"fimul", 1, 0xde, 1, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
639
640 {"fmulp", 2, 0xdec8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
641 {"fmulp", 1, 0xdec8, X, FP|ShortForm, { FloatReg, 0, 0} },
642 {"fmulp", 0, 0xdec9, X, FP, { 0, 0, 0} },
643 {"fmulp", 2, 0xdec8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
644
645 /* divide */
646 {"fdiv", 2, 0xd8f0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
647 {"fdiv", 1, 0xd8f0, X, FP|ShortForm, { FloatReg, 0, 0} },
648 #if UNIXWARE_COMPAT
649 {"fdiv", 0, 0xdef1, X, FP|Ugh, { 0, 0, 0} }, /* alias for fdivp */
650 #endif
651 {"fdiv", 1, 0xd8, 6, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
652 {"fidiv", 1, 0xde, 6, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
653
654 #if UNIXWARE_COMPAT
655 {"fdivp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
656 {"fdivp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} },
657 {"fdivp", 0, 0xdef1, X, FP, { 0, 0, 0} },
658 {"fdivp", 2, 0xdef0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
659 #else
660 {"fdivp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
661 {"fdivp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} },
662 {"fdivp", 0, 0xdef9, X, FP, { 0, 0, 0} },
663 #endif
664
665 /* divide reverse */
666 {"fdivr", 2, 0xd8f8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
667 {"fdivr", 1, 0xd8f8, X, FP|ShortForm, { FloatReg, 0, 0} },
668 #if UNIXWARE_COMPAT
669 {"fdivr", 0, 0xdef9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fdivrp */
670 #endif
671 {"fdivr", 1, 0xd8, 7, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
672 {"fidivr", 1, 0xde, 7, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
673
674 #if UNIXWARE_COMPAT
675 {"fdivrp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
676 {"fdivrp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} },
677 {"fdivrp", 0, 0xdef9, X, FP, { 0, 0, 0} },
678 {"fdivrp", 2, 0xdef8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
679 #else
680 {"fdivrp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
681 {"fdivrp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} },
682 {"fdivrp", 0, 0xdef1, X, FP, { 0, 0, 0} },
683 #endif
684
685 {"f2xm1", 0, 0xd9f0, X, FP, { 0, 0, 0} },
686 {"fyl2x", 0, 0xd9f1, X, FP, { 0, 0, 0} },
687 {"fptan", 0, 0xd9f2, X, FP, { 0, 0, 0} },
688 {"fpatan", 0, 0xd9f3, X, FP, { 0, 0, 0} },
689 {"fxtract",0, 0xd9f4, X, FP, { 0, 0, 0} },
690 {"fprem1", 0, 0xd9f5, X, FP, { 0, 0, 0} },
691 {"fdecstp",0, 0xd9f6, X, FP, { 0, 0, 0} },
692 {"fincstp",0, 0xd9f7, X, FP, { 0, 0, 0} },
693 {"fprem", 0, 0xd9f8, X, FP, { 0, 0, 0} },
694 {"fyl2xp1",0, 0xd9f9, X, FP, { 0, 0, 0} },
695 {"fsqrt", 0, 0xd9fa, X, FP, { 0, 0, 0} },
696 {"fsincos",0, 0xd9fb, X, FP, { 0, 0, 0} },
697 {"frndint",0, 0xd9fc, X, FP, { 0, 0, 0} },
698 {"fscale", 0, 0xd9fd, X, FP, { 0, 0, 0} },
699 {"fsin", 0, 0xd9fe, X, FP, { 0, 0, 0} },
700 {"fcos", 0, 0xd9ff, X, FP, { 0, 0, 0} },
701 {"fchs", 0, 0xd9e0, X, FP, { 0, 0, 0} },
702 {"fabs", 0, 0xd9e1, X, FP, { 0, 0, 0} },
703
704 /* processor control */
705 {"fninit", 0, 0xdbe3, X, FP, { 0, 0, 0} },
706 {"finit", 0, 0xdbe3, X, FP|FWait, { 0, 0, 0} },
707 {"fldcw", 1, 0xd9, 5, FP|Modrm, { ShortMem, 0, 0} },
708 {"fnstcw", 1, 0xd9, 7, FP|Modrm, { ShortMem, 0, 0} },
709 {"fstcw", 1, 0xd9, 7, FP|FWait|Modrm, { ShortMem, 0, 0} },
710 {"fnstsw", 1, 0xdfe0, X, FP, { Acc, 0, 0} },
711 {"fnstsw", 1, 0xdd, 7, FP|Modrm, { ShortMem, 0, 0} },
712 {"fnstsw", 0, 0xdfe0, X, FP, { 0, 0, 0} },
713 {"fstsw", 1, 0xdfe0, X, FP|FWait, { Acc, 0, 0} },
714 {"fstsw", 1, 0xdd, 7, FP|FWait|Modrm, { ShortMem, 0, 0} },
715 {"fstsw", 0, 0xdfe0, X, FP|FWait, { 0, 0, 0} },
716 {"fnclex", 0, 0xdbe2, X, FP, { 0, 0, 0} },
717 {"fclex", 0, 0xdbe2, X, FP|FWait, { 0, 0, 0} },
718 /* Short forms of fldenv, fstenv use data size prefix.
719 FIXME: Are these the right suffixes? */
720 {"fnstenv",1, 0xd9, 6, sl_Suf|Modrm, { LLongMem, 0, 0} },
721 {"fstenv", 1, 0xd9, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
722 {"fldenv", 1, 0xd9, 4, sl_Suf|Modrm, { LLongMem, 0, 0} },
723 {"fnsave", 1, 0xdd, 6, sl_Suf|Modrm, { LLongMem, 0, 0} },
724 {"fsave", 1, 0xdd, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
725 {"frstor", 1, 0xdd, 4, sl_Suf|Modrm, { LLongMem, 0, 0} },
726
727 {"ffree", 1, 0xddc0, X, FP|ShortForm, { FloatReg, 0, 0} },
728 /* P6:free st(i), pop st */
729 {"ffreep", 1, 0xdfc0, X, FP|ShortForm, { FloatReg, 0, 0} },
730 {"fnop", 0, 0xd9d0, X, FP, { 0, 0, 0} },
731 #define FWAIT_OPCODE 0x9b
732 {"fwait", 0, 0x9b, X, FP, { 0, 0, 0} },
733
734 /*
735 opcode prefixes; we allow them as seperate insns too
736 */
737 #define ADDR_PREFIX_OPCODE 0x67
738 {"addr16", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
739 {"addr32", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
740 {"aword", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
741 {"adword", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
742 #define DATA_PREFIX_OPCODE 0x66
743 {"data16", 0, 0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
744 {"data32", 0, 0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
745 {"word", 0, 0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
746 {"dword", 0, 0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
747 #define LOCK_PREFIX_OPCODE 0xf0
748 {"lock", 0, 0xf0, X, NoSuf|IsPrefix, { 0, 0, 0} },
749 {"wait", 0, 0x9b, X, NoSuf|IsPrefix, { 0, 0, 0} },
750 #define CS_PREFIX_OPCODE 0x2e
751 {"cs", 0, 0x2e, X, NoSuf|IsPrefix, { 0, 0, 0} },
752 #define DS_PREFIX_OPCODE 0x3e
753 {"ds", 0, 0x3e, X, NoSuf|IsPrefix, { 0, 0, 0} },
754 #define ES_PREFIX_OPCODE 0x26
755 {"es", 0, 0x26, X, NoSuf|IsPrefix, { 0, 0, 0} },
756 #define FS_PREFIX_OPCODE 0x64
757 {"fs", 0, 0x64, X, NoSuf|IsPrefix, { 0, 0, 0} },
758 #define GS_PREFIX_OPCODE 0x65
759 {"gs", 0, 0x65, X, NoSuf|IsPrefix, { 0, 0, 0} },
760 #define SS_PREFIX_OPCODE 0x36
761 {"ss", 0, 0x36, X, NoSuf|IsPrefix, { 0, 0, 0} },
762 #define REPNE_PREFIX_OPCODE 0xf2
763 #define REPE_PREFIX_OPCODE 0xf3
764 {"rep", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
765 {"repe", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
766 {"repz", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
767 {"repne", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} },
768 {"repnz", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} },
769
770 /* 486 extensions */
771
772 {"bswap", 1, 0x0fc8, X, l_Suf|ShortForm, { Reg32, 0, 0 } },
773 {"xadd", 2, 0x0fc0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
774 {"cmpxchg", 2, 0x0fb0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
775 {"invd", 0, 0x0f08, X, NoSuf, { 0, 0, 0} },
776 {"wbinvd", 0, 0x0f09, X, NoSuf, { 0, 0, 0} },
777 {"invlpg", 1, 0x0f01, 7, NoSuf|Modrm, { AnyMem, 0, 0} },
778
779 /* 586 and late 486 extensions */
780 {"cpuid", 0, 0x0fa2, X, NoSuf, { 0, 0, 0} },
781
782 /* Pentium extensions */
783 {"wrmsr", 0, 0x0f30, X, NoSuf, { 0, 0, 0} },
784 {"rdtsc", 0, 0x0f31, X, NoSuf, { 0, 0, 0} },
785 {"rdmsr", 0, 0x0f32, X, NoSuf, { 0, 0, 0} },
786 {"cmpxchg8b",1,0x0fc7, 1, NoSuf|Modrm, { LLongMem, 0, 0} },
787 {"sysenter",0, 0x0f34, X, NoSuf, { 0, 0, 0} },
788 {"sysexit", 0, 0x0f35, X, NoSuf, { 0, 0, 0} },
789 {"fxsave", 1, 0x0fae, 0, FP|Modrm, { LLongMem, 0, 0} },
790 {"fxrstor", 1, 0x0fae, 1, FP|Modrm, { LLongMem, 0, 0} },
791
792 /* Pentium Pro extensions */
793 {"rdpmc", 0, 0x0f33, X, NoSuf, { 0, 0, 0} },
794
795 {"ud2", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, /* official undefined instr. */
796 {"ud2a", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, /* alias for ud2 */
797 {"ud2b", 0, 0x0fb9, X, NoSuf, { 0, 0, 0} }, /* 2nd. official undefined instr. */
798
799 {"cmovo", 2, 0x0f40, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
800 {"cmovno", 2, 0x0f41, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
801 {"cmovb", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
802 {"cmovc", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
803 {"cmovnae", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
804 {"cmovae", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
805 {"cmovnc", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
806 {"cmovnb", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
807 {"cmove", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
808 {"cmovz", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
809 {"cmovne", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
810 {"cmovnz", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
811 {"cmovbe", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
812 {"cmovna", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
813 {"cmova", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
814 {"cmovnbe", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
815 {"cmovs", 2, 0x0f48, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
816 {"cmovns", 2, 0x0f49, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
817 {"cmovp", 2, 0x0f4a, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
818 {"cmovnp", 2, 0x0f4b, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
819 {"cmovl", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
820 {"cmovnge", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
821 {"cmovge", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
822 {"cmovnl", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
823 {"cmovle", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
824 {"cmovng", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
825 {"cmovg", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
826 {"cmovnle", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
827
828 {"fcmovb", 2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
829 {"fcmovnae",2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
830 {"fcmove", 2, 0xdac8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
831 {"fcmovbe", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
832 {"fcmovna", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
833 {"fcmovu", 2, 0xdad8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
834 {"fcmovae", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
835 {"fcmovnb", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
836 {"fcmovne", 2, 0xdbc8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
837 {"fcmova", 2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
838 {"fcmovnbe",2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
839 {"fcmovnu", 2, 0xdbd8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
840
841 {"fcomi", 2, 0xdbf0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
842 {"fcomi", 0, 0xdbf1, X, FP|ShortForm, { 0, 0, 0} },
843 {"fcomi", 1, 0xdbf0, X, FP|ShortForm, { FloatReg, 0, 0} },
844 {"fucomi", 2, 0xdbe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
845 {"fucomi", 0, 0xdbe9, X, FP|ShortForm, { 0, 0, 0} },
846 {"fucomi", 1, 0xdbe8, X, FP|ShortForm, { FloatReg, 0, 0} },
847 {"fcomip", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
848 {"fcompi", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
849 {"fcompi", 0, 0xdff1, X, FP|ShortForm, { 0, 0, 0} },
850 {"fcompi", 1, 0xdff0, X, FP|ShortForm, { FloatReg, 0, 0} },
851 {"fucomip", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
852 {"fucompi", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
853 {"fucompi", 0, 0xdfe9, X, FP|ShortForm, { 0, 0, 0} },
854 {"fucompi", 1, 0xdfe8, X, FP|ShortForm, { FloatReg, 0, 0} },
855
856 /* MMX instructions. */
857
858 {"emms", 0, 0x0f77, X, FP, { 0, 0, 0 } },
859 {"movd", 2, 0x0f6e, X, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } },
860 {"movd", 2, 0x0f7e, X, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } },
861 {"movq", 2, 0x0f6f, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
862 {"movq", 2, 0x0f7f, X, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } },
863 {"packssdw", 2, 0x0f6b, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
864 {"packsswb", 2, 0x0f63, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
865 {"packuswb", 2, 0x0f67, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
866 {"paddb", 2, 0x0ffc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
867 {"paddw", 2, 0x0ffd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
868 {"paddd", 2, 0x0ffe, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
869 {"paddsb", 2, 0x0fec, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
870 {"paddsw", 2, 0x0fed, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
871 {"paddusb", 2, 0x0fdc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
872 {"paddusw", 2, 0x0fdd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
873 {"pand", 2, 0x0fdb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
874 {"pandn", 2, 0x0fdf, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
875 {"pcmpeqb", 2, 0x0f74, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
876 {"pcmpeqw", 2, 0x0f75, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
877 {"pcmpeqd", 2, 0x0f76, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
878 {"pcmpgtb", 2, 0x0f64, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
879 {"pcmpgtw", 2, 0x0f65, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
880 {"pcmpgtd", 2, 0x0f66, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
881 {"pmaddwd", 2, 0x0ff5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
882 {"pmulhw", 2, 0x0fe5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
883 {"pmullw", 2, 0x0fd5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
884 {"por", 2, 0x0feb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
885 {"psllw", 2, 0x0ff1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
886 {"psllw", 2, 0x0f71, 6, FP|Modrm, { Imm8, RegMMX, 0 } },
887 {"pslld", 2, 0x0ff2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
888 {"pslld", 2, 0x0f72, 6, FP|Modrm, { Imm8, RegMMX, 0 } },
889 {"psllq", 2, 0x0ff3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
890 {"psllq", 2, 0x0f73, 6, FP|Modrm, { Imm8, RegMMX, 0 } },
891 {"psraw", 2, 0x0fe1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
892 {"psraw", 2, 0x0f71, 4, FP|Modrm, { Imm8, RegMMX, 0 } },
893 {"psrad", 2, 0x0fe2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
894 {"psrad", 2, 0x0f72, 4, FP|Modrm, { Imm8, RegMMX, 0 } },
895 {"psrlw", 2, 0x0fd1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
896 {"psrlw", 2, 0x0f71, 2, FP|Modrm, { Imm8, RegMMX, 0 } },
897 {"psrld", 2, 0x0fd2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
898 {"psrld", 2, 0x0f72, 2, FP|Modrm, { Imm8, RegMMX, 0 } },
899 {"psrlq", 2, 0x0fd3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
900 {"psrlq", 2, 0x0f73, 2, FP|Modrm, { Imm8, RegMMX, 0 } },
901 {"psubb", 2, 0x0ff8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
902 {"psubw", 2, 0x0ff9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
903 {"psubd", 2, 0x0ffa, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
904 {"psubsb", 2, 0x0fe8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
905 {"psubsw", 2, 0x0fe9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
906 {"psubusb", 2, 0x0fd8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
907 {"psubusw", 2, 0x0fd9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
908 {"punpckhbw",2, 0x0f68, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
909 {"punpckhwd",2, 0x0f69, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
910 {"punpckhdq",2, 0x0f6a, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
911 {"punpcklbw",2, 0x0f60, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
912 {"punpcklwd",2, 0x0f61, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
913 {"punpckldq",2, 0x0f62, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
914 {"pxor", 2, 0x0fef, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
915
916
917 /* PIII Katmai New Instructions / SIMD instructions */
918
919 {"addps", 2, 0x0f58, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
920 {"addss", 2, 0xf30f58, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
921 {"andnps", 2, 0x0f55, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
922 {"andps", 2, 0x0f54, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
923 {"cmpeqps", 2, 0x0fc2, 0, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
924 {"cmpeqss", 2, 0xf30fc2, 0, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
925 {"cmpleps", 2, 0x0fc2, 2, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
926 {"cmpless", 2, 0xf30fc2, 2, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
927 {"cmpltps", 2, 0x0fc2, 1, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
928 {"cmpltss", 2, 0xf30fc2, 1, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
929 {"cmpneqps", 2, 0x0fc2, 4, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
930 {"cmpneqss", 2, 0xf30fc2, 4, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
931 {"cmpnleps", 2, 0x0fc2, 6, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
932 {"cmpnless", 2, 0xf30fc2, 6, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
933 {"cmpnltps", 2, 0x0fc2, 5, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
934 {"cmpnltss", 2, 0xf30fc2, 5, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
935 {"cmpordps", 2, 0x0fc2, 7, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
936 {"cmpordss", 2, 0xf30fc2, 7, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
937 {"cmpunordps",2, 0x0fc2, 3, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
938 {"cmpunordss",2, 0xf30fc2, 3, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
939 {"cmpps", 3, 0x0fc2, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
940 {"cmpss", 3, 0xf30fc2, X, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } },
941 {"comiss", 2, 0x0f2f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
942 {"cvtpi2ps", 2, 0x0f2a, X, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
943 {"cvtps2pi", 2, 0x0f2d, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
944 {"cvtsi2ss", 2, 0xf30f2a, X, FP|Modrm, { Reg32|WordMem, RegXMM, 0 } },
945 {"cvtss2si", 2, 0xf30f2d, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } },
946 {"cvttps2pi", 2, 0x0f2c, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
947 {"cvttss2si", 2, 0xf30f2c, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } },
948 {"divps", 2, 0x0f5e, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
949 {"divss", 2, 0xf30f5e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
950 {"ldmxcsr", 1, 0x0fae, 2, FP|Modrm, { WordMem, 0, 0 } },
951 {"maskmovq", 2, 0x0ff7, X, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } },
952 {"maxps", 2, 0x0f5f, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
953 {"maxss", 2, 0xf30f5f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
954 {"minps", 2, 0x0f5d, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
955 {"minss", 2, 0xf30f5d, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
956 {"movaps", 2, 0x0f28, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
957 {"movaps", 2, 0x0f29, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
958 {"movhlps", 2, 0x0f12, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
959 {"movhps", 2, 0x0f16, X, FP|Modrm, { LLongMem, RegXMM, 0 } },
960 {"movhps", 2, 0x0f17, X, FP|Modrm, { RegXMM, LLongMem, 0 } },
961 {"movlhps", 2, 0x0f16, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
962 {"movlps", 2, 0x0f12, X, FP|Modrm, { LLongMem, RegXMM, 0 } },
963 {"movlps", 2, 0x0f13, X, FP|Modrm, { RegXMM, LLongMem, 0 } },
964 {"movmskps", 2, 0x0f50, X, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } },
965 {"movntps", 2, 0x0f2b, X, FP|Modrm, { RegXMM, LLongMem, 0 } },
966 {"movntq", 2, 0x0fe7, X, FP|Modrm, { RegMMX, LLongMem, 0 } },
967 {"movss", 2, 0xf30f10, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
968 {"movss", 2, 0xf30f11, X, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } },
969 {"movups", 2, 0x0f10, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
970 {"movups", 2, 0x0f11, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
971 {"mulps", 2, 0x0f59, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
972 {"mulss", 2, 0xf30f59, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
973 {"orps", 2, 0x0f56, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
974 {"pavgb", 2, 0x0fe0, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
975 {"pavgw", 2, 0x0fe3, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
976 {"pextrw", 3, 0x0fc5, X, FP|Modrm, { Imm8, RegMMX, Reg32|InvMem } },
977 {"pinsrw", 3, 0x0fc4, X, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } },
978 {"pmaxsw", 2, 0x0fee, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
979 {"pmaxub", 2, 0x0fde, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
980 {"pminsw", 2, 0x0fea, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
981 {"pminub", 2, 0x0fda, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
982 {"pmovmskb", 2, 0x0fd7, X, FP|Modrm, { RegMMX, Reg32|InvMem, 0 } },
983 {"pmulhuw", 2, 0x0fe4, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
984 {"prefetchnta", 1, 0x0f18, 0, FP|Modrm, { LLongMem, 0, 0 } },
985 {"prefetcht0", 1, 0x0f18, 1, FP|Modrm, { LLongMem, 0, 0 } },
986 {"prefetcht1", 1, 0x0f18, 2, FP|Modrm, { LLongMem, 0, 0 } },
987 {"prefetcht2", 1, 0x0f18, 3, FP|Modrm, { LLongMem, 0, 0 } },
988 {"psadbw", 2, 0x0ff6, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
989 {"pshufw", 3, 0x0f70, X, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } },
990 {"rcpps", 2, 0x0f53, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
991 {"rcpss", 2, 0xf30f53, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
992 {"rsqrtps", 2, 0x0f52, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
993 {"rsqrtss", 2, 0xf30f52, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
994 {"sfence", 0, 0x0faef8, X, FP, { 0, 0, 0 } },
995 {"shufps", 3, 0x0fc6, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
996 {"sqrtps", 2, 0x0f51, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
997 {"sqrtss", 2, 0xf30f51, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
998 {"stmxcsr", 1, 0x0fae, 3, FP|Modrm, { WordMem, 0, 0 } },
999 {"subps", 2, 0x0f5c, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1000 {"subss", 2, 0xf30f5c, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1001 {"ucomiss", 2, 0x0f2e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1002 {"unpckhps", 2, 0x0f15, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1003 {"unpcklps", 2, 0x0f14, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1004 {"xorps", 2, 0x0f57, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1005
1006 /* AMD 3DNow! instructions */
1007
1008 {"prefetch", 1, 0x0f0d, 0, FP|Modrm, { ByteMem, 0, 0 } },
1009 {"prefetchw",1, 0x0f0d, 1, FP|Modrm, { ByteMem, 0, 0 } },
1010 {"femms", 0, 0x0f0e, X, FP, { 0, 0, 0 } },
1011 {"pavgusb", 2, 0x0f0f, 0xbf, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1012 {"pf2id", 2, 0x0f0f, 0x1d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1013 {"pf2iw", 2, 0x0f0f, 0x1c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
1014 {"pfacc", 2, 0x0f0f, 0xae, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1015 {"pfadd", 2, 0x0f0f, 0x9e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1016 {"pfcmpeq", 2, 0x0f0f, 0xb0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1017 {"pfcmpge", 2, 0x0f0f, 0x90, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1018 {"pfcmpgt", 2, 0x0f0f, 0xa0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1019 {"pfmax", 2, 0x0f0f, 0xa4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1020 {"pfmin", 2, 0x0f0f, 0x94, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1021 {"pfmul", 2, 0x0f0f, 0xb4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1022 {"pfnacc", 2, 0x0f0f, 0x8a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
1023 {"pfpnacc", 2, 0x0f0f, 0x8e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
1024 {"pfrcp", 2, 0x0f0f, 0x96, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1025 {"pfrcpit1", 2, 0x0f0f, 0xa6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1026 {"pfrcpit2", 2, 0x0f0f, 0xb6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1027 {"pfrsqit1", 2, 0x0f0f, 0xa7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1028 {"pfrsqrt", 2, 0x0f0f, 0x97, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1029 {"pfsub", 2, 0x0f0f, 0x9a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1030 {"pfsubr", 2, 0x0f0f, 0xaa, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1031 {"pi2fd", 2, 0x0f0f, 0x0d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1032 {"pi2fw", 2, 0x0f0f, 0x0c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
1033 {"pmulhrw", 2, 0x0f0f, 0xb7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1034 {"pswapd", 2, 0x0f0f, 0xbb, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */
1035
1036 {NULL, 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
1037 };
1038 #undef X
1039 #undef NoSuf
1040 #undef b_Suf
1041 #undef w_Suf
1042 #undef l_Suf
1043 #undef d_Suf
1044 #undef x_Suf
1045 #undef bw_Suf
1046 #undef bl_Suf
1047 #undef wl_Suf
1048 #undef sl_Suf
1049 #undef sld_Suf
1050 #undef sldx_Suf
1051 #undef bwl_Suf
1052 #undef bwld_Suf
1053 #undef FP
1054 #undef l_FP
1055 #undef d_FP
1056 #undef x_FP
1057 #undef sl_FP
1058 #undef sld_FP
1059 #undef sldx_FP
1060
1061 #define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */
1062
1063
1064 /* 386 register table */
1065
1066 static const reg_entry i386_regtab[] = {
1067 /* make %st first as we test for it */
1068 {"st", FloatReg|FloatAcc, 0},
1069 /* 8 bit regs */
1070 {"al", Reg8|Acc, 0},
1071 {"cl", Reg8|ShiftCount, 1},
1072 {"dl", Reg8, 2},
1073 {"bl", Reg8, 3},
1074 {"ah", Reg8, 4},
1075 {"ch", Reg8, 5},
1076 {"dh", Reg8, 6},
1077 {"bh", Reg8, 7},
1078 /* 16 bit regs */
1079 {"ax", Reg16|Acc, 0},
1080 {"cx", Reg16, 1},
1081 {"dx", Reg16|InOutPortReg, 2},
1082 {"bx", Reg16|BaseIndex, 3},
1083 {"sp", Reg16, 4},
1084 {"bp", Reg16|BaseIndex, 5},
1085 {"si", Reg16|BaseIndex, 6},
1086 {"di", Reg16|BaseIndex, 7},
1087 /* 32 bit regs */
1088 {"eax", Reg32|BaseIndex|Acc, 0},
1089 {"ecx", Reg32|BaseIndex, 1},
1090 {"edx", Reg32|BaseIndex, 2},
1091 {"ebx", Reg32|BaseIndex, 3},
1092 {"esp", Reg32, 4},
1093 {"ebp", Reg32|BaseIndex, 5},
1094 {"esi", Reg32|BaseIndex, 6},
1095 {"edi", Reg32|BaseIndex, 7},
1096 /* segment registers */
1097 {"es", SReg2, 0},
1098 {"cs", SReg2, 1},
1099 {"ss", SReg2, 2},
1100 {"ds", SReg2, 3},
1101 {"fs", SReg3, 4},
1102 {"gs", SReg3, 5},
1103 /* control registers */
1104 {"cr0", Control, 0},
1105 {"cr1", Control, 1},
1106 {"cr2", Control, 2},
1107 {"cr3", Control, 3},
1108 {"cr4", Control, 4},
1109 {"cr5", Control, 5},
1110 {"cr6", Control, 6},
1111 {"cr7", Control, 7},
1112 /* debug registers */
1113 {"db0", Debug, 0},
1114 {"db1", Debug, 1},
1115 {"db2", Debug, 2},
1116 {"db3", Debug, 3},
1117 {"db4", Debug, 4},
1118 {"db5", Debug, 5},
1119 {"db6", Debug, 6},
1120 {"db7", Debug, 7},
1121 {"dr0", Debug, 0},
1122 {"dr1", Debug, 1},
1123 {"dr2", Debug, 2},
1124 {"dr3", Debug, 3},
1125 {"dr4", Debug, 4},
1126 {"dr5", Debug, 5},
1127 {"dr6", Debug, 6},
1128 {"dr7", Debug, 7},
1129 /* test registers */
1130 {"tr0", Test, 0},
1131 {"tr1", Test, 1},
1132 {"tr2", Test, 2},
1133 {"tr3", Test, 3},
1134 {"tr4", Test, 4},
1135 {"tr5", Test, 5},
1136 {"tr6", Test, 6},
1137 {"tr7", Test, 7},
1138 /* mmx and simd registers */
1139 {"mm0", RegMMX, 0},
1140 {"mm1", RegMMX, 1},
1141 {"mm2", RegMMX, 2},
1142 {"mm3", RegMMX, 3},
1143 {"mm4", RegMMX, 4},
1144 {"mm5", RegMMX, 5},
1145 {"mm6", RegMMX, 6},
1146 {"mm7", RegMMX, 7},
1147 {"xmm0", RegXMM, 0},
1148 {"xmm1", RegXMM, 1},
1149 {"xmm2", RegXMM, 2},
1150 {"xmm3", RegXMM, 3},
1151 {"xmm4", RegXMM, 4},
1152 {"xmm5", RegXMM, 5},
1153 {"xmm6", RegXMM, 6},
1154 {"xmm7", RegXMM, 7}
1155 };
1156
1157 static const reg_entry i386_float_regtab[] = {
1158 {"st(0)", FloatReg|FloatAcc, 0},
1159 {"st(1)", FloatReg, 1},
1160 {"st(2)", FloatReg, 2},
1161 {"st(3)", FloatReg, 3},
1162 {"st(4)", FloatReg, 4},
1163 {"st(5)", FloatReg, 5},
1164 {"st(6)", FloatReg, 6},
1165 {"st(7)", FloatReg, 7}
1166 };
1167
1168 #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
1169
1170 /* segment stuff */
1171 static const seg_entry cs = { "cs", 0x2e };
1172 static const seg_entry ds = { "ds", 0x3e };
1173 static const seg_entry ss = { "ss", 0x36 };
1174 static const seg_entry es = { "es", 0x26 };
1175 static const seg_entry fs = { "fs", 0x64 };
1176 static const seg_entry gs = { "gs", 0x65 };
1177
1178 /* end of opcode/i386.h */
git-cvsimport of binutils cvsroot