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opcodes: blackfin: fix decoding of all register move insns
[binutils.git] / opcodes / bfin-dis.c
blobb17e0552b943b0199a00207d550027fe3bcbdc94
1 /* Disassemble ADI Blackfin Instructions.
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
3
4 This file is part of libopcodes.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include <stdio.h>
22 #include <stdlib.h>
23 #include <string.h>
24
25 #include "opcode/bfin.h"
26
27 #define M_S2RND 1
28 #define M_T 2
29 #define M_W32 3
30 #define M_FU 4
31 #define M_TFU 6
32 #define M_IS 8
33 #define M_ISS2 9
34 #define M_IH 11
35 #define M_IU 12
36
37 #ifndef PRINTF
38 #define PRINTF printf
39 #endif
40
41 #ifndef EXIT
42 #define EXIT exit
43 #endif
44
45 typedef long TIword;
46
47 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
48 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
49 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
50 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
51
52 #include "dis-asm.h"
53
54 typedef unsigned int bu32;
55
56 static char comment = 0;
57 static char parallel = 0;
58
59 typedef enum
60 {
61 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
62 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
63 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
64 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
65 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
66 } const_forms_t;
67
68 static const struct
69 {
70 const char *name;
71 const int nbits;
72 const char reloc;
73 const char issigned;
74 const char pcrel;
75 const char scale;
76 const char offset;
77 const char negative;
78 const char positive;
79 const char decimal;
80 const char leading;
81 const char exact;
82 } constant_formats[] =
83 {
84 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
85 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
86 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
88 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
89 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
91 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
92 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
94 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
95 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
97 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
98 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
99 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
100 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
101 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
102 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
103 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
104 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
107 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
108 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
109 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
110 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
111 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
112 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
113 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
114 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
118 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
119 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
120 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
121 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
122 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
123 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
124 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
125 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
126 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
127 };
128
129 static const char *
130 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
131 {
132 static char buf[60];
133
134 if (constant_formats[cf].reloc)
135 {
136 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
137 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
138 if (constant_formats[cf].pcrel)
139 ea += pc;
140
141 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
142 {
143 outf->print_address_func (ea, outf);
144 return "";
145 }
146 else
147 {
148 sprintf (buf, "%lx", (unsigned long) x);
149 return buf;
150 }
151 }
152
153 /* Negative constants have an implied sign bit. */
154 if (constant_formats[cf].negative)
155 {
156 int nb = constant_formats[cf].nbits + 1;
157
158 x = x | (1 << constant_formats[cf].nbits);
159 x = SIGNEXTEND (x, nb);
160 }
161 else
162 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
163
164 if (constant_formats[cf].offset)
165 x += constant_formats[cf].offset;
166
167 if (constant_formats[cf].scale)
168 x <<= constant_formats[cf].scale;
169
170 if (constant_formats[cf].decimal)
171 {
172 if (constant_formats[cf].leading)
173 {
174 char ps[10];
175 sprintf (ps, "%%%ii", constant_formats[cf].leading);
176 sprintf (buf, ps, x);
177 }
178 else
179 sprintf (buf, "%li", x);
180 }
181 else
182 {
183 if (constant_formats[cf].issigned && x < 0)
184 sprintf (buf, "-0x%x", abs (x));
185 else
186 sprintf (buf, "0x%lx", (unsigned long) x);
187 }
188
189 return buf;
190 }
191
192 static bu32
193 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
194 {
195 if (0 && constant_formats[cf].reloc)
196 {
197 bu32 ea = (((constant_formats[cf].pcrel
198 ? SIGNEXTEND (x, constant_formats[cf].nbits)
199 : x) + constant_formats[cf].offset)
200 << constant_formats[cf].scale);
201 if (constant_formats[cf].pcrel)
202 ea += pc;
203
204 return ea;
205 }
206
207 /* Negative constants have an implied sign bit. */
208 if (constant_formats[cf].negative)
209 {
210 int nb = constant_formats[cf].nbits + 1;
211 x = x | (1 << constant_formats[cf].nbits);
212 x = SIGNEXTEND (x, nb);
213 }
214 else if (constant_formats[cf].issigned)
215 x = SIGNEXTEND (x, constant_formats[cf].nbits);
216
217 x += constant_formats[cf].offset;
218 x <<= constant_formats[cf].scale;
219
220 return x;
221 }
222
223 enum machine_registers
224 {
225 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
226 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
227 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
228 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
229 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
230 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
231 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
232 REG_L2, REG_L3,
233 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
234 REG_AQ, REG_V, REG_VS,
235 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
236 REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
237 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
238 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
239 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
240 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
241 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
242 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
243 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
244 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
245 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
246 REG_LASTREG,
247 };
248
249 enum reg_class
250 {
251 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
252 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
253 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
254 rc_sysregs3, rc_allregs,
255 LIM_REG_CLASSES
256 };
257
258 static const char *reg_names[] =
259 {
260 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
261 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
262 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
263 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
264 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
265 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
266 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
267 "L2", "L3",
268 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
269 "AQ", "V", "VS",
270 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
271 "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
272 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
273 "RETE", "EMUDAT",
274 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
275 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
276 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
277 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
278 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
279 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
280 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
281 "AC0_COPY", "V_COPY", "RND_MOD",
282 "LASTREG",
283 0
284 };
285
286 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
287
288 /* RL(0..7). */
289 static enum machine_registers decode_dregs_lo[] =
290 {
291 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
292 };
293
294 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
295
296 /* RH(0..7). */
297 static enum machine_registers decode_dregs_hi[] =
298 {
299 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
300 };
301
302 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
303
304 /* R(0..7). */
305 static enum machine_registers decode_dregs[] =
306 {
307 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
308 };
309
310 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
311
312 /* R BYTE(0..7). */
313 static enum machine_registers decode_dregs_byte[] =
314 {
315 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
316 };
317
318 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
319
320 /* P(0..5) SP FP. */
321 static enum machine_registers decode_pregs[] =
322 {
323 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
324 };
325
326 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
327 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
328 #define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
329 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
330 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
331 #define accum(x) REGNAME (decode_accum[(x) & 1])
332
333 /* I(0..3). */
334 static enum machine_registers decode_iregs[] =
335 {
336 REG_I0, REG_I1, REG_I2, REG_I3,
337 };
338
339 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
340
341 /* M(0..3). */
342 static enum machine_registers decode_mregs[] =
343 {
344 REG_M0, REG_M1, REG_M2, REG_M3,
345 };
346
347 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
348 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
349 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
350
351 /* dregs pregs. */
352 static enum machine_registers decode_dpregs[] =
353 {
354 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
355 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
356 };
357
358 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
359
360 /* [dregs pregs]. */
361 static enum machine_registers decode_gregs[] =
362 {
363 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
364 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
365 };
366
367 #define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
368
369 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
370 static enum machine_registers decode_regs[] =
371 {
372 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
373 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
374 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
375 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
376 };
377
378 #define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
379
380 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
381 static enum machine_registers decode_regs_lo[] =
382 {
383 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
384 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
385 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
386 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
387 };
388
389 #define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
390 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
391 static enum machine_registers decode_regs_hi[] =
392 {
393 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
394 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
395 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
396 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
397 };
398
399 #define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
400
401 static enum machine_registers decode_statbits[] =
402 {
403 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
404 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
405 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
406 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
407 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
408 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
409 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
410 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
411 };
412
413 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
414
415 /* LC0 LC1. */
416 static enum machine_registers decode_counters[] =
417 {
418 REG_LC0, REG_LC1,
419 };
420
421 #define counters(x) REGNAME (decode_counters[(x) & 1])
422 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
423
424 /* [dregs pregs (iregs mregs) (bregs lregs)
425 dregs2_sysregs1 open sysregs2 sysregs3]. */
426 static enum machine_registers decode_allregs[] =
427 {
428 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
429 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
430 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
431 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
432 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
433 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
434 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
435 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
436 REG_LASTREG,
437 };
438
439 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
440 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
441 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
442 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
443 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
444 #define IS_SYSREG(g,r) \
445 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
446 #define IS_RESERVEDREG(g,r) \
447 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
448
449 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
450 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
451
452 #define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
453 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
454 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
455 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
456 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
457 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
458 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
459 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
460 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
461 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
462 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
463 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
464 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
465 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
466 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
467 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
468 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
469 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
470 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
471 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
472 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
473 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
474 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
475 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
476 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
477 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
478 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
479 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
480 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
481 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
482 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
483 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
484 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
485 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
486 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
487 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
488 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
489 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
490 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
491 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
492 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
493 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
494 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
495
496 /* (arch.pm)arch_disassembler_functions. */
497 #ifndef OUTS
498 #define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
499 #endif
500
501 static void
502 amod0 (int s0, int x0, disassemble_info *outf)
503 {
504 if (s0 == 1 && x0 == 0)
505 OUTS (outf, " (S)");
506 else if (s0 == 0 && x0 == 1)
507 OUTS (outf, " (CO)");
508 else if (s0 == 1 && x0 == 1)
509 OUTS (outf, " (SCO)");
510 }
511
512 static void
513 amod1 (int s0, int x0, disassemble_info *outf)
514 {
515 if (s0 == 0 && x0 == 0)
516 OUTS (outf, " (NS)");
517 else if (s0 == 1 && x0 == 0)
518 OUTS (outf, " (S)");
519 }
520
521 static void
522 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
523 {
524 if (s0 == 1 && x0 == 0 && aop0 == 0)
525 OUTS (outf, " (S)");
526 else if (s0 == 0 && x0 == 1 && aop0 == 0)
527 OUTS (outf, " (CO)");
528 else if (s0 == 1 && x0 == 1 && aop0 == 0)
529 OUTS (outf, " (SCO)");
530 else if (s0 == 0 && x0 == 0 && aop0 == 2)
531 OUTS (outf, " (ASR)");
532 else if (s0 == 1 && x0 == 0 && aop0 == 2)
533 OUTS (outf, " (S, ASR)");
534 else if (s0 == 0 && x0 == 1 && aop0 == 2)
535 OUTS (outf, " (CO, ASR)");
536 else if (s0 == 1 && x0 == 1 && aop0 == 2)
537 OUTS (outf, " (SCO, ASR)");
538 else if (s0 == 0 && x0 == 0 && aop0 == 3)
539 OUTS (outf, " (ASL)");
540 else if (s0 == 1 && x0 == 0 && aop0 == 3)
541 OUTS (outf, " (S, ASL)");
542 else if (s0 == 0 && x0 == 1 && aop0 == 3)
543 OUTS (outf, " (CO, ASL)");
544 else if (s0 == 1 && x0 == 1 && aop0 == 3)
545 OUTS (outf, " (SCO, ASL)");
546 }
547
548 static void
549 searchmod (int r0, disassemble_info *outf)
550 {
551 if (r0 == 0)
552 OUTS (outf, "GT");
553 else if (r0 == 1)
554 OUTS (outf, "GE");
555 else if (r0 == 2)
556 OUTS (outf, "LT");
557 else if (r0 == 3)
558 OUTS (outf, "LE");
559 }
560
561 static void
562 aligndir (int r0, disassemble_info *outf)
563 {
564 if (r0 == 1)
565 OUTS (outf, " (R)");
566 }
567
568 static int
569 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
570 {
571 const char *s0, *s1;
572
573 if (h0)
574 s0 = dregs_hi (src0);
575 else
576 s0 = dregs_lo (src0);
577
578 if (h1)
579 s1 = dregs_hi (src1);
580 else
581 s1 = dregs_lo (src1);
582
583 OUTS (outf, s0);
584 OUTS (outf, " * ");
585 OUTS (outf, s1);
586 return 0;
587 }
588
589 static int
590 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
591 {
592 const char *a;
593 const char *sop = "<unknown op>";
594
595 if (which)
596 a = "A1";
597 else
598 a = "A0";
599
600 if (op == 3)
601 {
602 OUTS (outf, a);
603 return 0;
604 }
605
606 switch (op)
607 {
608 case 0: sop = " = "; break;
609 case 1: sop = " += "; break;
610 case 2: sop = " -= "; break;
611 default: break;
612 }
613
614 OUTS (outf, a);
615 OUTS (outf, sop);
616 decode_multfunc (h0, h1, src0, src1, outf);
617
618 return 0;
619 }
620
621 static void
622 decode_optmode (int mod, int MM, disassemble_info *outf)
623 {
624 if (mod == 0 && MM == 0)
625 return;
626
627 OUTS (outf, " (");
628
629 if (MM && !mod)
630 {
631 OUTS (outf, "M)");
632 return;
633 }
634
635 if (MM)
636 OUTS (outf, "M, ");
637
638 if (mod == M_S2RND)
639 OUTS (outf, "S2RND");
640 else if (mod == M_T)
641 OUTS (outf, "T");
642 else if (mod == M_W32)
643 OUTS (outf, "W32");
644 else if (mod == M_FU)
645 OUTS (outf, "FU");
646 else if (mod == M_TFU)
647 OUTS (outf, "TFU");
648 else if (mod == M_IS)
649 OUTS (outf, "IS");
650 else if (mod == M_ISS2)
651 OUTS (outf, "ISS2");
652 else if (mod == M_IH)
653 OUTS (outf, "IH");
654 else if (mod == M_IU)
655 OUTS (outf, "IU");
656 else
657 abort ();
658
659 OUTS (outf, ")");
660 }
661
662 struct saved_state
663 {
664 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
665 bu32 a0x, a0w, a1x, a1w;
666 bu32 lt[2], lc[2], lb[2];
667 int ac0, ac0_copy, ac1, an, aq;
668 int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
669 int rnd_mod;
670 int v_internal;
671 bu32 pc, rets;
672
673 int ticks;
674 int insts;
675
676 int exception;
677
678 int end_of_registers;
679
680 int msize;
681 unsigned char *memory;
682 unsigned long bfd_mach;
683 } saved_state;
684
685 #define DREG(x) (saved_state.dpregs[x])
686 #define GREG(x,i) DPREG ((x) | (i << 3))
687 #define DPREG(x) (saved_state.dpregs[x])
688 #define DREG(x) (saved_state.dpregs[x])
689 #define PREG(x) (saved_state.dpregs[x + 8])
690 #define SPREG PREG (6)
691 #define FPREG PREG (7)
692 #define IREG(x) (saved_state.iregs[x])
693 #define MREG(x) (saved_state.mregs[x])
694 #define BREG(x) (saved_state.bregs[x])
695 #define LREG(x) (saved_state.lregs[x])
696 #define A0XREG (saved_state.a0x)
697 #define A0WREG (saved_state.a0w)
698 #define A1XREG (saved_state.a1x)
699 #define A1WREG (saved_state.a1w)
700 #define CCREG (saved_state.cc)
701 #define LC0REG (saved_state.lc[0])
702 #define LT0REG (saved_state.lt[0])
703 #define LB0REG (saved_state.lb[0])
704 #define LC1REG (saved_state.lc[1])
705 #define LT1REG (saved_state.lt[1])
706 #define LB1REG (saved_state.lb[1])
707 #define RETSREG (saved_state.rets)
708 #define PCREG (saved_state.pc)
709
710 static bu32 *
711 get_allreg (int grp, int reg)
712 {
713 int fullreg = (grp << 3) | reg;
714 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
715 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
716 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
717 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
718 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
719 , , , , , , , ,
720 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
721 REG_CYCLES2,
722 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
723 REG_LASTREG */
724 switch (fullreg >> 2)
725 {
726 case 0: case 1: return &DREG (reg); break;
727 case 2: case 3: return &PREG (reg); break;
728 case 4: return &IREG (reg & 3); break;
729 case 5: return &MREG (reg & 3); break;
730 case 6: return &BREG (reg & 3); break;
731 case 7: return &LREG (reg & 3); break;
732 default:
733 switch (fullreg)
734 {
735 case 32: return &saved_state.a0x;
736 case 33: return &saved_state.a0w;
737 case 34: return &saved_state.a1x;
738 case 35: return &saved_state.a1w;
739 case 39: return &saved_state.rets;
740 case 48: return &LC0REG;
741 case 49: return &LT0REG;
742 case 50: return &LB0REG;
743 case 51: return &LC1REG;
744 case 52: return &LT1REG;
745 case 53: return &LB1REG;
746 }
747 return 0;
748 }
749 }
750
751 static int
752 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
753 {
754 /* ProgCtrl
755 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
756 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
757 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
758 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
759 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
760
761 if (prgfunc == 0 && poprnd == 0)
762 OUTS (outf, "NOP");
763 else if (parallel)
764 return 0;
765 else if (prgfunc == 1 && poprnd == 0)
766 OUTS (outf, "RTS");
767 else if (prgfunc == 1 && poprnd == 1)
768 OUTS (outf, "RTI");
769 else if (prgfunc == 1 && poprnd == 2)
770 OUTS (outf, "RTX");
771 else if (prgfunc == 1 && poprnd == 3)
772 OUTS (outf, "RTN");
773 else if (prgfunc == 1 && poprnd == 4)
774 OUTS (outf, "RTE");
775 else if (prgfunc == 2 && poprnd == 0)
776 OUTS (outf, "IDLE");
777 else if (prgfunc == 2 && poprnd == 3)
778 OUTS (outf, "CSYNC");
779 else if (prgfunc == 2 && poprnd == 4)
780 OUTS (outf, "SSYNC");
781 else if (prgfunc == 2 && poprnd == 5)
782 OUTS (outf, "EMUEXCPT");
783 else if (prgfunc == 3 && IS_DREG (0, poprnd))
784 {
785 OUTS (outf, "CLI ");
786 OUTS (outf, dregs (poprnd));
787 }
788 else if (prgfunc == 4 && IS_DREG (0, poprnd))
789 {
790 OUTS (outf, "STI ");
791 OUTS (outf, dregs (poprnd));
792 }
793 else if (prgfunc == 5 && IS_PREG (1, poprnd))
794 {
795 OUTS (outf, "JUMP (");
796 OUTS (outf, pregs (poprnd));
797 OUTS (outf, ")");
798 }
799 else if (prgfunc == 6 && IS_PREG (1, poprnd))
800 {
801 OUTS (outf, "CALL (");
802 OUTS (outf, pregs (poprnd));
803 OUTS (outf, ")");
804 }
805 else if (prgfunc == 7 && IS_PREG (1, poprnd))
806 {
807 OUTS (outf, "CALL (PC + ");
808 OUTS (outf, pregs (poprnd));
809 OUTS (outf, ")");
810 }
811 else if (prgfunc == 8 && IS_PREG (1, poprnd))
812 {
813 OUTS (outf, "JUMP (PC + ");
814 OUTS (outf, pregs (poprnd));
815 OUTS (outf, ")");
816 }
817 else if (prgfunc == 9)
818 {
819 OUTS (outf, "RAISE ");
820 OUTS (outf, uimm4 (poprnd));
821 }
822 else if (prgfunc == 10)
823 {
824 OUTS (outf, "EXCPT ");
825 OUTS (outf, uimm4 (poprnd));
826 }
827 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
828 {
829 OUTS (outf, "TESTSET (");
830 OUTS (outf, pregs (poprnd));
831 OUTS (outf, ")");
832 }
833 else
834 return 0;
835 return 2;
836 }
837
838 static int
839 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
840 {
841 /* CaCTRL
842 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
843 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
844 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
845 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
846 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
847 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
848
849 if (parallel)
850 return 0;
851
852 if (a == 0 && op == 0)
853 {
854 OUTS (outf, "PREFETCH[");
855 OUTS (outf, pregs (reg));
856 OUTS (outf, "]");
857 }
858 else if (a == 0 && op == 1)
859 {
860 OUTS (outf, "FLUSHINV[");
861 OUTS (outf, pregs (reg));
862 OUTS (outf, "]");
863 }
864 else if (a == 0 && op == 2)
865 {
866 OUTS (outf, "FLUSH[");
867 OUTS (outf, pregs (reg));
868 OUTS (outf, "]");
869 }
870 else if (a == 0 && op == 3)
871 {
872 OUTS (outf, "IFLUSH[");
873 OUTS (outf, pregs (reg));
874 OUTS (outf, "]");
875 }
876 else if (a == 1 && op == 0)
877 {
878 OUTS (outf, "PREFETCH[");
879 OUTS (outf, pregs (reg));
880 OUTS (outf, "++]");
881 }
882 else if (a == 1 && op == 1)
883 {
884 OUTS (outf, "FLUSHINV[");
885 OUTS (outf, pregs (reg));
886 OUTS (outf, "++]");
887 }
888 else if (a == 1 && op == 2)
889 {
890 OUTS (outf, "FLUSH[");
891 OUTS (outf, pregs (reg));
892 OUTS (outf, "++]");
893 }
894 else if (a == 1 && op == 3)
895 {
896 OUTS (outf, "IFLUSH[");
897 OUTS (outf, pregs (reg));
898 OUTS (outf, "++]");
899 }
900 else
901 return 0;
902 return 2;
903 }
904
905 static int
906 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
907 {
908 /* PushPopReg
909 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
910 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
911 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
912 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
913 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
914 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
915
916 if (parallel)
917 return 0;
918
919 if (W == 0 && mostreg (reg, grp))
920 {
921 OUTS (outf, allregs (reg, grp));
922 OUTS (outf, " = [SP++]");
923 }
924 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
925 {
926 OUTS (outf, "[--SP] = ");
927 OUTS (outf, allregs (reg, grp));
928 }
929 else
930 return 0;
931 return 2;
932 }
933
934 static int
935 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
936 {
937 /* PushPopMultiple
938 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
939 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
940 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
941 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
942 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
943 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
944 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
945 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
946
947 if (parallel)
948 return 0;
949
950 if (pr > 5)
951 return 0;
952
953 if (W == 1 && d == 1 && p == 1)
954 {
955 OUTS (outf, "[--SP] = (R7:");
956 OUTS (outf, imm5d (dr));
957 OUTS (outf, ", P5:");
958 OUTS (outf, imm5d (pr));
959 OUTS (outf, ")");
960 }
961 else if (W == 1 && d == 1 && p == 0 && pr == 0)
962 {
963 OUTS (outf, "[--SP] = (R7:");
964 OUTS (outf, imm5d (dr));
965 OUTS (outf, ")");
966 }
967 else if (W == 1 && d == 0 && p == 1 && dr == 0)
968 {
969 OUTS (outf, "[--SP] = (P5:");
970 OUTS (outf, imm5d (pr));
971 OUTS (outf, ")");
972 }
973 else if (W == 0 && d == 1 && p == 1)
974 {
975 OUTS (outf, "(R7:");
976 OUTS (outf, imm5d (dr));
977 OUTS (outf, ", P5:");
978 OUTS (outf, imm5d (pr));
979 OUTS (outf, ") = [SP++]");
980 }
981 else if (W == 0 && d == 1 && p == 0 && pr == 0)
982 {
983 OUTS (outf, "(R7:");
984 OUTS (outf, imm5d (dr));
985 OUTS (outf, ") = [SP++]");
986 }
987 else if (W == 0 && d == 0 && p == 1 && dr == 0)
988 {
989 OUTS (outf, "(P5:");
990 OUTS (outf, imm5d (pr));
991 OUTS (outf, ") = [SP++]");
992 }
993 else
994 return 0;
995 return 2;
996 }
997
998 static int
999 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
1000 {
1001 /* ccMV
1002 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1003 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
1004 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1005 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
1006 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
1007 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
1008 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
1009 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
1010
1011 if (parallel)
1012 return 0;
1013
1014 if (T == 1)
1015 {
1016 OUTS (outf, "IF CC ");
1017 OUTS (outf, gregs (dst, d));
1018 OUTS (outf, " = ");
1019 OUTS (outf, gregs (src, s));
1020 }
1021 else if (T == 0)
1022 {
1023 OUTS (outf, "IF !CC ");
1024 OUTS (outf, gregs (dst, d));
1025 OUTS (outf, " = ");
1026 OUTS (outf, gregs (src, s));
1027 }
1028 else
1029 return 0;
1030 return 2;
1031 }
1032
1033 static int
1034 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1035 {
1036 /* CCflag
1037 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1038 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1039 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1040 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1041 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1042 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1043 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1044 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1045
1046 if (parallel)
1047 return 0;
1048
1049 if (opc == 0 && I == 0 && G == 0)
1050 {
1051 OUTS (outf, "CC = ");
1052 OUTS (outf, dregs (x));
1053 OUTS (outf, " == ");
1054 OUTS (outf, dregs (y));
1055 }
1056 else if (opc == 1 && I == 0 && G == 0)
1057 {
1058 OUTS (outf, "CC = ");
1059 OUTS (outf, dregs (x));
1060 OUTS (outf, " < ");
1061 OUTS (outf, dregs (y));
1062 }
1063 else if (opc == 2 && I == 0 && G == 0)
1064 {
1065 OUTS (outf, "CC = ");
1066 OUTS (outf, dregs (x));
1067 OUTS (outf, " <= ");
1068 OUTS (outf, dregs (y));
1069 }
1070 else if (opc == 3 && I == 0 && G == 0)
1071 {
1072 OUTS (outf, "CC = ");
1073 OUTS (outf, dregs (x));
1074 OUTS (outf, " < ");
1075 OUTS (outf, dregs (y));
1076 OUTS (outf, " (IU)");
1077 }
1078 else if (opc == 4 && I == 0 && G == 0)
1079 {
1080 OUTS (outf, "CC = ");
1081 OUTS (outf, dregs (x));
1082 OUTS (outf, " <= ");
1083 OUTS (outf, dregs (y));
1084 OUTS (outf, " (IU)");
1085 }
1086 else if (opc == 0 && I == 1 && G == 0)
1087 {
1088 OUTS (outf, "CC = ");
1089 OUTS (outf, dregs (x));
1090 OUTS (outf, " == ");
1091 OUTS (outf, imm3 (y));
1092 }
1093 else if (opc == 1 && I == 1 && G == 0)
1094 {
1095 OUTS (outf, "CC = ");
1096 OUTS (outf, dregs (x));
1097 OUTS (outf, " < ");
1098 OUTS (outf, imm3 (y));
1099 }
1100 else if (opc == 2 && I == 1 && G == 0)
1101 {
1102 OUTS (outf, "CC = ");
1103 OUTS (outf, dregs (x));
1104 OUTS (outf, " <= ");
1105 OUTS (outf, imm3 (y));
1106 }
1107 else if (opc == 3 && I == 1 && G == 0)
1108 {
1109 OUTS (outf, "CC = ");
1110 OUTS (outf, dregs (x));
1111 OUTS (outf, " < ");
1112 OUTS (outf, uimm3 (y));
1113 OUTS (outf, " (IU)");
1114 }
1115 else if (opc == 4 && I == 1 && G == 0)
1116 {
1117 OUTS (outf, "CC = ");
1118 OUTS (outf, dregs (x));
1119 OUTS (outf, " <= ");
1120 OUTS (outf, uimm3 (y));
1121 OUTS (outf, " (IU)");
1122 }
1123 else if (opc == 0 && I == 0 && G == 1)
1124 {
1125 OUTS (outf, "CC = ");
1126 OUTS (outf, pregs (x));
1127 OUTS (outf, " == ");
1128 OUTS (outf, pregs (y));
1129 }
1130 else if (opc == 1 && I == 0 && G == 1)
1131 {
1132 OUTS (outf, "CC = ");
1133 OUTS (outf, pregs (x));
1134 OUTS (outf, " < ");
1135 OUTS (outf, pregs (y));
1136 }
1137 else if (opc == 2 && I == 0 && G == 1)
1138 {
1139 OUTS (outf, "CC = ");
1140 OUTS (outf, pregs (x));
1141 OUTS (outf, " <= ");
1142 OUTS (outf, pregs (y));
1143 }
1144 else if (opc == 3 && I == 0 && G == 1)
1145 {
1146 OUTS (outf, "CC = ");
1147 OUTS (outf, pregs (x));
1148 OUTS (outf, " < ");
1149 OUTS (outf, pregs (y));
1150 OUTS (outf, " (IU)");
1151 }
1152 else if (opc == 4 && I == 0 && G == 1)
1153 {
1154 OUTS (outf, "CC = ");
1155 OUTS (outf, pregs (x));
1156 OUTS (outf, " <= ");
1157 OUTS (outf, pregs (y));
1158 OUTS (outf, " (IU)");
1159 }
1160 else if (opc == 0 && I == 1 && G == 1)
1161 {
1162 OUTS (outf, "CC = ");
1163 OUTS (outf, pregs (x));
1164 OUTS (outf, " == ");
1165 OUTS (outf, imm3 (y));
1166 }
1167 else if (opc == 1 && I == 1 && G == 1)
1168 {
1169 OUTS (outf, "CC = ");
1170 OUTS (outf, pregs (x));
1171 OUTS (outf, " < ");
1172 OUTS (outf, imm3 (y));
1173 }
1174 else if (opc == 2 && I == 1 && G == 1)
1175 {
1176 OUTS (outf, "CC = ");
1177 OUTS (outf, pregs (x));
1178 OUTS (outf, " <= ");
1179 OUTS (outf, imm3 (y));
1180 }
1181 else if (opc == 3 && I == 1 && G == 1)
1182 {
1183 OUTS (outf, "CC = ");
1184 OUTS (outf, pregs (x));
1185 OUTS (outf, " < ");
1186 OUTS (outf, uimm3 (y));
1187 OUTS (outf, " (IU)");
1188 }
1189 else if (opc == 4 && I == 1 && G == 1)
1190 {
1191 OUTS (outf, "CC = ");
1192 OUTS (outf, pregs (x));
1193 OUTS (outf, " <= ");
1194 OUTS (outf, uimm3 (y));
1195 OUTS (outf, " (IU)");
1196 }
1197 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
1198 OUTS (outf, "CC = A0 == A1");
1199
1200 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
1201 OUTS (outf, "CC = A0 < A1");
1202
1203 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
1204 OUTS (outf, "CC = A0 <= A1");
1205
1206 else
1207 return 0;
1208 return 2;
1209 }
1210
1211 static int
1212 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1213 {
1214 /* CC2dreg
1215 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1216 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1217 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1218 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1219 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1220
1221 if (parallel)
1222 return 0;
1223
1224 if (op == 0)
1225 {
1226 OUTS (outf, dregs (reg));
1227 OUTS (outf, " = CC");
1228 }
1229 else if (op == 1)
1230 {
1231 OUTS (outf, "CC = ");
1232 OUTS (outf, dregs (reg));
1233 }
1234 else if (op == 3 && reg == 0)
1235 OUTS (outf, "CC = !CC");
1236 else
1237 return 0;
1238
1239 return 2;
1240 }
1241
1242 static int
1243 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1244 {
1245 /* CC2stat
1246 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1247 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1248 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1249 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1250 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1251 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1252
1253 const char *bitname = statbits (cbit);
1254
1255 if (parallel)
1256 return 0;
1257
1258 if (decode_statbits[cbit] == REG_LASTREG)
1259 {
1260 /* All ASTAT bits except CC may be operated on in hardware, but may
1261 not have a dedicated insn, so still decode "valid" insns. */
1262 static char bitnames[64];
1263 if (cbit != 5)
1264 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1265 else
1266 return 0;
1267
1268 bitname = bitnames;
1269 }
1270
1271 if (op == 0 && D == 0)
1272 {
1273 OUTS (outf, "CC = ");
1274 OUTS (outf, bitname);
1275 }
1276 else if (op == 1 && D == 0)
1277 {
1278 OUTS (outf, "CC |= ");
1279 OUTS (outf, bitname);
1280 }
1281 else if (op == 2 && D == 0)
1282 {
1283 OUTS (outf, "CC &= ");
1284 OUTS (outf, bitname);
1285 }
1286 else if (op == 3 && D == 0)
1287 {
1288 OUTS (outf, "CC ^= ");
1289 OUTS (outf, bitname);
1290 }
1291 else if (op == 0 && D == 1)
1292 {
1293 OUTS (outf, bitname);
1294 OUTS (outf, " = CC");
1295 }
1296 else if (op == 1 && D == 1)
1297 {
1298 OUTS (outf, bitname);
1299 OUTS (outf, " |= CC");
1300 }
1301 else if (op == 2 && D == 1)
1302 {
1303 OUTS (outf, bitname);
1304 OUTS (outf, " &= CC");
1305 }
1306 else if (op == 3 && D == 1)
1307 {
1308 OUTS (outf, bitname);
1309 OUTS (outf, " ^= CC");
1310 }
1311 else
1312 return 0;
1313
1314 return 2;
1315 }
1316
1317 static int
1318 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1319 {
1320 /* BRCC
1321 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1322 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1323 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1324 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1325 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1326 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1327
1328 if (parallel)
1329 return 0;
1330
1331 if (T == 1 && B == 1)
1332 {
1333 OUTS (outf, "IF CC JUMP 0x");
1334 OUTS (outf, pcrel10 (offset));
1335 OUTS (outf, " (BP)");
1336 }
1337 else if (T == 0 && B == 1)
1338 {
1339 OUTS (outf, "IF !CC JUMP 0x");
1340 OUTS (outf, pcrel10 (offset));
1341 OUTS (outf, " (BP)");
1342 }
1343 else if (T == 1)
1344 {
1345 OUTS (outf, "IF CC JUMP 0x");
1346 OUTS (outf, pcrel10 (offset));
1347 }
1348 else if (T == 0)
1349 {
1350 OUTS (outf, "IF !CC JUMP 0x");
1351 OUTS (outf, pcrel10 (offset));
1352 }
1353 else
1354 return 0;
1355
1356 return 2;
1357 }
1358
1359 static int
1360 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1361 {
1362 /* UJUMP
1363 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1364 | 0 | 0 | 1 | 0 |.offset........................................|
1365 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1366 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1367
1368 if (parallel)
1369 return 0;
1370
1371 OUTS (outf, "JUMP.S 0x");
1372 OUTS (outf, pcrel12 (offset));
1373 return 2;
1374 }
1375
1376 static int
1377 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1378 {
1379 /* REGMV
1380 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1381 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1382 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1383 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1384 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1385 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1386 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1387
1388 /* Reserved slots cannot be a src/dst. */
1389 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1390 goto invalid_move;
1391
1392 /* Standard register moves */
1393 if ((gs < 2) || /* Dregs/Pregs as source */
1394 (gd < 2) || /* Dregs/Pregs as dest */
1395 (gs == 4 && src < 4) || /* Accumulators as source */
1396 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1397 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1398 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1399 goto valid_move;
1400
1401 /* dareg = dareg (IMBL) */
1402 if (gs < 4 && gd < 4)
1403 goto valid_move;
1404
1405 /* USP can be src to sysregs, but not dagregs. */
1406 if ((gs == 7 && src == 0) && (gd >= 4))
1407 goto valid_move;
1408
1409 /* USP can move between genregs (only check Accumulators). */
1410 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1411 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1412 goto valid_move;
1413
1414 /* Still here ? Invalid reg pair. */
1415 invalid_move:
1416 return 0;
1417
1418 valid_move:
1419 OUTS (outf, allregs (dst, gd));
1420 OUTS (outf, " = ");
1421 OUTS (outf, allregs (src, gs));
1422 return 2;
1423 }
1424
1425 static int
1426 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1427 {
1428 /* ALU2op
1429 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1430 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1431 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1432 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1433 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1434 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1435
1436 if (opc == 0)
1437 {
1438 OUTS (outf, dregs (dst));
1439 OUTS (outf, " >>>= ");
1440 OUTS (outf, dregs (src));
1441 }
1442 else if (opc == 1)
1443 {
1444 OUTS (outf, dregs (dst));
1445 OUTS (outf, " >>= ");
1446 OUTS (outf, dregs (src));
1447 }
1448 else if (opc == 2)
1449 {
1450 OUTS (outf, dregs (dst));
1451 OUTS (outf, " <<= ");
1452 OUTS (outf, dregs (src));
1453 }
1454 else if (opc == 3)
1455 {
1456 OUTS (outf, dregs (dst));
1457 OUTS (outf, " *= ");
1458 OUTS (outf, dregs (src));
1459 }
1460 else if (opc == 4)
1461 {
1462 OUTS (outf, dregs (dst));
1463 OUTS (outf, " = (");
1464 OUTS (outf, dregs (dst));
1465 OUTS (outf, " + ");
1466 OUTS (outf, dregs (src));
1467 OUTS (outf, ") << 0x1");
1468 }
1469 else if (opc == 5)
1470 {
1471 OUTS (outf, dregs (dst));
1472 OUTS (outf, " = (");
1473 OUTS (outf, dregs (dst));
1474 OUTS (outf, " + ");
1475 OUTS (outf, dregs (src));
1476 OUTS (outf, ") << 0x2");
1477 }
1478 else if (opc == 8)
1479 {
1480 OUTS (outf, "DIVQ (");
1481 OUTS (outf, dregs (dst));
1482 OUTS (outf, ", ");
1483 OUTS (outf, dregs (src));
1484 OUTS (outf, ")");
1485 }
1486 else if (opc == 9)
1487 {
1488 OUTS (outf, "DIVS (");
1489 OUTS (outf, dregs (dst));
1490 OUTS (outf, ", ");
1491 OUTS (outf, dregs (src));
1492 OUTS (outf, ")");
1493 }
1494 else if (opc == 10)
1495 {
1496 OUTS (outf, dregs (dst));
1497 OUTS (outf, " = ");
1498 OUTS (outf, dregs_lo (src));
1499 OUTS (outf, " (X)");
1500 }
1501 else if (opc == 11)
1502 {
1503 OUTS (outf, dregs (dst));
1504 OUTS (outf, " = ");
1505 OUTS (outf, dregs_lo (src));
1506 OUTS (outf, " (Z)");
1507 }
1508 else if (opc == 12)
1509 {
1510 OUTS (outf, dregs (dst));
1511 OUTS (outf, " = ");
1512 OUTS (outf, dregs_byte (src));
1513 OUTS (outf, " (X)");
1514 }
1515 else if (opc == 13)
1516 {
1517 OUTS (outf, dregs (dst));
1518 OUTS (outf, " = ");
1519 OUTS (outf, dregs_byte (src));
1520 OUTS (outf, " (Z)");
1521 }
1522 else if (opc == 14)
1523 {
1524 OUTS (outf, dregs (dst));
1525 OUTS (outf, " = -");
1526 OUTS (outf, dregs (src));
1527 }
1528 else if (opc == 15)
1529 {
1530 OUTS (outf, dregs (dst));
1531 OUTS (outf, " =~ ");
1532 OUTS (outf, dregs (src));
1533 }
1534 else
1535 return 0;
1536
1537 return 2;
1538 }
1539
1540 static int
1541 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1542 {
1543 /* PTR2op
1544 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1545 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1546 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1547 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1548 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1549 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1550
1551 if (opc == 0)
1552 {
1553 OUTS (outf, pregs (dst));
1554 OUTS (outf, " -= ");
1555 OUTS (outf, pregs (src));
1556 }
1557 else if (opc == 1)
1558 {
1559 OUTS (outf, pregs (dst));
1560 OUTS (outf, " = ");
1561 OUTS (outf, pregs (src));
1562 OUTS (outf, " << 0x2");
1563 }
1564 else if (opc == 3)
1565 {
1566 OUTS (outf, pregs (dst));
1567 OUTS (outf, " = ");
1568 OUTS (outf, pregs (src));
1569 OUTS (outf, " >> 0x2");
1570 }
1571 else if (opc == 4)
1572 {
1573 OUTS (outf, pregs (dst));
1574 OUTS (outf, " = ");
1575 OUTS (outf, pregs (src));
1576 OUTS (outf, " >> 0x1");
1577 }
1578 else if (opc == 5)
1579 {
1580 OUTS (outf, pregs (dst));
1581 OUTS (outf, " += ");
1582 OUTS (outf, pregs (src));
1583 OUTS (outf, " (BREV)");
1584 }
1585 else if (opc == 6)
1586 {
1587 OUTS (outf, pregs (dst));
1588 OUTS (outf, " = (");
1589 OUTS (outf, pregs (dst));
1590 OUTS (outf, " + ");
1591 OUTS (outf, pregs (src));
1592 OUTS (outf, ") << 0x1");
1593 }
1594 else if (opc == 7)
1595 {
1596 OUTS (outf, pregs (dst));
1597 OUTS (outf, " = (");
1598 OUTS (outf, pregs (dst));
1599 OUTS (outf, " + ");
1600 OUTS (outf, pregs (src));
1601 OUTS (outf, ") << 0x2");
1602 }
1603 else
1604 return 0;
1605
1606 return 2;
1607 }
1608
1609 static int
1610 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1611 {
1612 /* LOGI2op
1613 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1614 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1615 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1616 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1617 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1618 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1619
1620 if (parallel)
1621 return 0;
1622
1623 if (opc == 0)
1624 {
1625 OUTS (outf, "CC = !BITTST (");
1626 OUTS (outf, dregs (dst));
1627 OUTS (outf, ", ");
1628 OUTS (outf, uimm5 (src));
1629 OUTS (outf, ");\t\t/* bit");
1630 OUTS (outf, imm7d (src));
1631 OUTS (outf, " */");
1632 comment = 1;
1633 }
1634 else if (opc == 1)
1635 {
1636 OUTS (outf, "CC = BITTST (");
1637 OUTS (outf, dregs (dst));
1638 OUTS (outf, ", ");
1639 OUTS (outf, uimm5 (src));
1640 OUTS (outf, ");\t\t/* bit");
1641 OUTS (outf, imm7d (src));
1642 OUTS (outf, " */");
1643 comment = 1;
1644 }
1645 else if (opc == 2)
1646 {
1647 OUTS (outf, "BITSET (");
1648 OUTS (outf, dregs (dst));
1649 OUTS (outf, ", ");
1650 OUTS (outf, uimm5 (src));
1651 OUTS (outf, ");\t\t/* bit");
1652 OUTS (outf, imm7d (src));
1653 OUTS (outf, " */");
1654 comment = 1;
1655 }
1656 else if (opc == 3)
1657 {
1658 OUTS (outf, "BITTGL (");
1659 OUTS (outf, dregs (dst));
1660 OUTS (outf, ", ");
1661 OUTS (outf, uimm5 (src));
1662 OUTS (outf, ");\t\t/* bit");
1663 OUTS (outf, imm7d (src));
1664 OUTS (outf, " */");
1665 comment = 1;
1666 }
1667 else if (opc == 4)
1668 {
1669 OUTS (outf, "BITCLR (");
1670 OUTS (outf, dregs (dst));
1671 OUTS (outf, ", ");
1672 OUTS (outf, uimm5 (src));
1673 OUTS (outf, ");\t\t/* bit");
1674 OUTS (outf, imm7d (src));
1675 OUTS (outf, " */");
1676 comment = 1;
1677 }
1678 else if (opc == 5)
1679 {
1680 OUTS (outf, dregs (dst));
1681 OUTS (outf, " >>>= ");
1682 OUTS (outf, uimm5 (src));
1683 }
1684 else if (opc == 6)
1685 {
1686 OUTS (outf, dregs (dst));
1687 OUTS (outf, " >>= ");
1688 OUTS (outf, uimm5 (src));
1689 }
1690 else if (opc == 7)
1691 {
1692 OUTS (outf, dregs (dst));
1693 OUTS (outf, " <<= ");
1694 OUTS (outf, uimm5 (src));
1695 }
1696 else
1697 return 0;
1698
1699 return 2;
1700 }
1701
1702 static int
1703 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1704 {
1705 /* COMP3op
1706 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1707 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1708 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1709 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1710 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1711 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1712 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1713
1714 if (opc == 5 && src1 == src0)
1715 {
1716 OUTS (outf, pregs (dst));
1717 OUTS (outf, " = ");
1718 OUTS (outf, pregs (src0));
1719 OUTS (outf, " << 0x1");
1720 }
1721 else if (opc == 1)
1722 {
1723 OUTS (outf, dregs (dst));
1724 OUTS (outf, " = ");
1725 OUTS (outf, dregs (src0));
1726 OUTS (outf, " - ");
1727 OUTS (outf, dregs (src1));
1728 }
1729 else if (opc == 2)
1730 {
1731 OUTS (outf, dregs (dst));
1732 OUTS (outf, " = ");
1733 OUTS (outf, dregs (src0));
1734 OUTS (outf, " & ");
1735 OUTS (outf, dregs (src1));
1736 }
1737 else if (opc == 3)
1738 {
1739 OUTS (outf, dregs (dst));
1740 OUTS (outf, " = ");
1741 OUTS (outf, dregs (src0));
1742 OUTS (outf, " | ");
1743 OUTS (outf, dregs (src1));
1744 }
1745 else if (opc == 4)
1746 {
1747 OUTS (outf, dregs (dst));
1748 OUTS (outf, " = ");
1749 OUTS (outf, dregs (src0));
1750 OUTS (outf, " ^ ");
1751 OUTS (outf, dregs (src1));
1752 }
1753 else if (opc == 5)
1754 {
1755 OUTS (outf, pregs (dst));
1756 OUTS (outf, " = ");
1757 OUTS (outf, pregs (src0));
1758 OUTS (outf, " + ");
1759 OUTS (outf, pregs (src1));
1760 }
1761 else if (opc == 6)
1762 {
1763 OUTS (outf, pregs (dst));
1764 OUTS (outf, " = ");
1765 OUTS (outf, pregs (src0));
1766 OUTS (outf, " + (");
1767 OUTS (outf, pregs (src1));
1768 OUTS (outf, " << 0x1)");
1769 }
1770 else if (opc == 7)
1771 {
1772 OUTS (outf, pregs (dst));
1773 OUTS (outf, " = ");
1774 OUTS (outf, pregs (src0));
1775 OUTS (outf, " + (");
1776 OUTS (outf, pregs (src1));
1777 OUTS (outf, " << 0x2)");
1778 }
1779 else if (opc == 0)
1780 {
1781 OUTS (outf, dregs (dst));
1782 OUTS (outf, " = ");
1783 OUTS (outf, dregs (src0));
1784 OUTS (outf, " + ");
1785 OUTS (outf, dregs (src1));
1786 }
1787 else
1788 return 0;
1789
1790 return 2;
1791 }
1792
1793 static int
1794 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1795 {
1796 /* COMPI2opD
1797 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1798 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1799 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1800 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1801 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1802 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1803
1804 bu32 *pval = get_allreg (0, dst);
1805
1806 if (parallel)
1807 return 0;
1808
1809 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1810 to combine them, so it prints out the right values.
1811 Here we keep track of the registers. */
1812 if (op == 0)
1813 {
1814 *pval = imm7_val (src);
1815 if (src & 0x40)
1816 *pval |= 0xFFFFFF80;
1817 else
1818 *pval &= 0x7F;
1819 }
1820
1821 if (op == 0)
1822 {
1823 OUTS (outf, dregs (dst));
1824 OUTS (outf, " = ");
1825 OUTS (outf, imm7 (src));
1826 OUTS (outf, " (X);\t\t/*\t\t");
1827 OUTS (outf, dregs (dst));
1828 OUTS (outf, "=");
1829 OUTS (outf, uimm32 (*pval));
1830 OUTS (outf, "(");
1831 OUTS (outf, imm32 (*pval));
1832 OUTS (outf, ") */");
1833 comment = 1;
1834 }
1835 else if (op == 1)
1836 {
1837 OUTS (outf, dregs (dst));
1838 OUTS (outf, " += ");
1839 OUTS (outf, imm7 (src));
1840 OUTS (outf, ";\t\t/* (");
1841 OUTS (outf, imm7d (src));
1842 OUTS (outf, ") */");
1843 comment = 1;
1844 }
1845 else
1846 return 0;
1847
1848 return 2;
1849 }
1850
1851 static int
1852 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1853 {
1854 /* COMPI2opP
1855 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1856 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1857 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1858 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1859 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1860 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1861
1862 bu32 *pval = get_allreg (1, dst);
1863
1864 if (parallel)
1865 return 0;
1866
1867 if (op == 0)
1868 {
1869 *pval = imm7_val (src);
1870 if (src & 0x40)
1871 *pval |= 0xFFFFFF80;
1872 else
1873 *pval &= 0x7F;
1874 }
1875
1876 if (op == 0)
1877 {
1878 OUTS (outf, pregs (dst));
1879 OUTS (outf, " = ");
1880 OUTS (outf, imm7 (src));
1881 OUTS (outf, " (X);\t\t/*\t\t");
1882 OUTS (outf, pregs (dst));
1883 OUTS (outf, "=");
1884 OUTS (outf, uimm32 (*pval));
1885 OUTS (outf, "(");
1886 OUTS (outf, imm32 (*pval));
1887 OUTS (outf, ") */");
1888 comment = 1;
1889 }
1890 else if (op == 1)
1891 {
1892 OUTS (outf, pregs (dst));
1893 OUTS (outf, " += ");
1894 OUTS (outf, imm7 (src));
1895 OUTS (outf, ";\t\t/* (");
1896 OUTS (outf, imm7d (src));
1897 OUTS (outf, ") */");
1898 comment = 1;
1899 }
1900 else
1901 return 0;
1902
1903 return 2;
1904 }
1905
1906 static int
1907 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1908 {
1909 /* LDSTpmod
1910 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1911 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1912 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1913 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1914 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1915 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1916 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1917 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1918
1919 if (aop == 1 && W == 0 && idx == ptr)
1920 {
1921 OUTS (outf, dregs_lo (reg));
1922 OUTS (outf, " = W[");
1923 OUTS (outf, pregs (ptr));
1924 OUTS (outf, "]");
1925 }
1926 else if (aop == 2 && W == 0 && idx == ptr)
1927 {
1928 OUTS (outf, dregs_hi (reg));
1929 OUTS (outf, " = W[");
1930 OUTS (outf, pregs (ptr));
1931 OUTS (outf, "]");
1932 }
1933 else if (aop == 1 && W == 1 && idx == ptr)
1934 {
1935 OUTS (outf, "W[");
1936 OUTS (outf, pregs (ptr));
1937 OUTS (outf, "] = ");
1938 OUTS (outf, dregs_lo (reg));
1939 }
1940 else if (aop == 2 && W == 1 && idx == ptr)
1941 {
1942 OUTS (outf, "W[");
1943 OUTS (outf, pregs (ptr));
1944 OUTS (outf, "] = ");
1945 OUTS (outf, dregs_hi (reg));
1946 }
1947 else if (aop == 0 && W == 0)
1948 {
1949 OUTS (outf, dregs (reg));
1950 OUTS (outf, " = [");
1951 OUTS (outf, pregs (ptr));
1952 OUTS (outf, " ++ ");
1953 OUTS (outf, pregs (idx));
1954 OUTS (outf, "]");
1955 }
1956 else if (aop == 1 && W == 0)
1957 {
1958 OUTS (outf, dregs_lo (reg));
1959 OUTS (outf, " = W[");
1960 OUTS (outf, pregs (ptr));
1961 OUTS (outf, " ++ ");
1962 OUTS (outf, pregs (idx));
1963 OUTS (outf, "]");
1964 }
1965 else if (aop == 2 && W == 0)
1966 {
1967 OUTS (outf, dregs_hi (reg));
1968 OUTS (outf, " = W[");
1969 OUTS (outf, pregs (ptr));
1970 OUTS (outf, " ++ ");
1971 OUTS (outf, pregs (idx));
1972 OUTS (outf, "]");
1973 }
1974 else if (aop == 3 && W == 0)
1975 {
1976 OUTS (outf, dregs (reg));
1977 OUTS (outf, " = W[");
1978 OUTS (outf, pregs (ptr));
1979 OUTS (outf, " ++ ");
1980 OUTS (outf, pregs (idx));
1981 OUTS (outf, "] (Z)");
1982 }
1983 else if (aop == 3 && W == 1)
1984 {
1985 OUTS (outf, dregs (reg));
1986 OUTS (outf, " = W[");
1987 OUTS (outf, pregs (ptr));
1988 OUTS (outf, " ++ ");
1989 OUTS (outf, pregs (idx));
1990 OUTS (outf, "] (X)");
1991 }
1992 else if (aop == 0 && W == 1)
1993 {
1994 OUTS (outf, "[");
1995 OUTS (outf, pregs (ptr));
1996 OUTS (outf, " ++ ");
1997 OUTS (outf, pregs (idx));
1998 OUTS (outf, "] = ");
1999 OUTS (outf, dregs (reg));
2000 }
2001 else if (aop == 1 && W == 1)
2002 {
2003 OUTS (outf, "W[");
2004 OUTS (outf, pregs (ptr));
2005 OUTS (outf, " ++ ");
2006 OUTS (outf, pregs (idx));
2007 OUTS (outf, "] = ");
2008 OUTS (outf, dregs_lo (reg));
2009 }
2010 else if (aop == 2 && W == 1)
2011 {
2012 OUTS (outf, "W[");
2013 OUTS (outf, pregs (ptr));
2014 OUTS (outf, " ++ ");
2015 OUTS (outf, pregs (idx));
2016 OUTS (outf, "] = ");
2017 OUTS (outf, dregs_hi (reg));
2018 }
2019 else
2020 return 0;
2021
2022 return 2;
2023 }
2024
2025 static int
2026 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
2027 {
2028 /* dagMODim
2029 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2030 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2031 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2032 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
2033 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
2034 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
2035 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2036
2037 if (op == 0 && br == 1)
2038 {
2039 OUTS (outf, iregs (i));
2040 OUTS (outf, " += ");
2041 OUTS (outf, mregs (m));
2042 OUTS (outf, " (BREV)");
2043 }
2044 else if (op == 0)
2045 {
2046 OUTS (outf, iregs (i));
2047 OUTS (outf, " += ");
2048 OUTS (outf, mregs (m));
2049 }
2050 else if (op == 1 && br == 0)
2051 {
2052 OUTS (outf, iregs (i));
2053 OUTS (outf, " -= ");
2054 OUTS (outf, mregs (m));
2055 }
2056 else
2057 return 0;
2058
2059 return 2;
2060 }
2061
2062 static int
2063 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2064 {
2065 /* dagMODik
2066 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2067 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2068 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2069 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2070 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2071
2072 if (op == 0)
2073 {
2074 OUTS (outf, iregs (i));
2075 OUTS (outf, " += 0x2");
2076 }
2077 else if (op == 1)
2078 {
2079 OUTS (outf, iregs (i));
2080 OUTS (outf, " -= 0x2");
2081 }
2082 else if (op == 2)
2083 {
2084 OUTS (outf, iregs (i));
2085 OUTS (outf, " += 0x4");
2086 }
2087 else if (op == 3)
2088 {
2089 OUTS (outf, iregs (i));
2090 OUTS (outf, " -= 0x4");
2091 }
2092 else
2093 return 0;
2094
2095 if (! parallel )
2096 {
2097 OUTS (outf, ";\t\t/* ( ");
2098 if (op == 0 || op == 1)
2099 OUTS (outf, "2");
2100 else if (op == 2 || op == 3)
2101 OUTS (outf, "4");
2102 OUTS (outf, ") */");
2103 comment = 1;
2104 }
2105
2106 return 2;
2107 }
2108
2109 static int
2110 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2111 {
2112 /* dspLDST
2113 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2114 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2115 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2116 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2117 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2118 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2119 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2120 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2121
2122 if (aop == 0 && W == 0 && m == 0)
2123 {
2124 OUTS (outf, dregs (reg));
2125 OUTS (outf, " = [");
2126 OUTS (outf, iregs (i));
2127 OUTS (outf, "++]");
2128 }
2129 else if (aop == 0 && W == 0 && m == 1)
2130 {
2131 OUTS (outf, dregs_lo (reg));
2132 OUTS (outf, " = W[");
2133 OUTS (outf, iregs (i));
2134 OUTS (outf, "++]");
2135 }
2136 else if (aop == 0 && W == 0 && m == 2)
2137 {
2138 OUTS (outf, dregs_hi (reg));
2139 OUTS (outf, " = W[");
2140 OUTS (outf, iregs (i));
2141 OUTS (outf, "++]");
2142 }
2143 else if (aop == 1 && W == 0 && m == 0)
2144 {
2145 OUTS (outf, dregs (reg));
2146 OUTS (outf, " = [");
2147 OUTS (outf, iregs (i));
2148 OUTS (outf, "--]");
2149 }
2150 else if (aop == 1 && W == 0 && m == 1)
2151 {
2152 OUTS (outf, dregs_lo (reg));
2153 OUTS (outf, " = W[");
2154 OUTS (outf, iregs (i));
2155 OUTS (outf, "--]");
2156 }
2157 else if (aop == 1 && W == 0 && m == 2)
2158 {
2159 OUTS (outf, dregs_hi (reg));
2160 OUTS (outf, " = W[");
2161 OUTS (outf, iregs (i));
2162 OUTS (outf, "--]");
2163 }
2164 else if (aop == 2 && W == 0 && m == 0)
2165 {
2166 OUTS (outf, dregs (reg));
2167 OUTS (outf, " = [");
2168 OUTS (outf, iregs (i));
2169 OUTS (outf, "]");
2170 }
2171 else if (aop == 2 && W == 0 && m == 1)
2172 {
2173 OUTS (outf, dregs_lo (reg));
2174 OUTS (outf, " = W[");
2175 OUTS (outf, iregs (i));
2176 OUTS (outf, "]");
2177 }
2178 else if (aop == 2 && W == 0 && m == 2)
2179 {
2180 OUTS (outf, dregs_hi (reg));
2181 OUTS (outf, " = W[");
2182 OUTS (outf, iregs (i));
2183 OUTS (outf, "]");
2184 }
2185 else if (aop == 0 && W == 1 && m == 0)
2186 {
2187 OUTS (outf, "[");
2188 OUTS (outf, iregs (i));
2189 OUTS (outf, "++] = ");
2190 OUTS (outf, dregs (reg));
2191 }
2192 else if (aop == 0 && W == 1 && m == 1)
2193 {
2194 OUTS (outf, "W[");
2195 OUTS (outf, iregs (i));
2196 OUTS (outf, "++] = ");
2197 OUTS (outf, dregs_lo (reg));
2198 }
2199 else if (aop == 0 && W == 1 && m == 2)
2200 {
2201 OUTS (outf, "W[");
2202 OUTS (outf, iregs (i));
2203 OUTS (outf, "++] = ");
2204 OUTS (outf, dregs_hi (reg));
2205 }
2206 else if (aop == 1 && W == 1 && m == 0)
2207 {
2208 OUTS (outf, "[");
2209 OUTS (outf, iregs (i));
2210 OUTS (outf, "--] = ");
2211 OUTS (outf, dregs (reg));
2212 }
2213 else if (aop == 1 && W == 1 && m == 1)
2214 {
2215 OUTS (outf, "W[");
2216 OUTS (outf, iregs (i));
2217 OUTS (outf, "--] = ");
2218 OUTS (outf, dregs_lo (reg));
2219 }
2220 else if (aop == 1 && W == 1 && m == 2)
2221 {
2222 OUTS (outf, "W[");
2223 OUTS (outf, iregs (i));
2224 OUTS (outf, "--] = ");
2225 OUTS (outf, dregs_hi (reg));
2226 }
2227 else if (aop == 2 && W == 1 && m == 0)
2228 {
2229 OUTS (outf, "[");
2230 OUTS (outf, iregs (i));
2231 OUTS (outf, "] = ");
2232 OUTS (outf, dregs (reg));
2233 }
2234 else if (aop == 2 && W == 1 && m == 1)
2235 {
2236 OUTS (outf, "W[");
2237 OUTS (outf, iregs (i));
2238 OUTS (outf, "] = ");
2239 OUTS (outf, dregs_lo (reg));
2240 }
2241 else if (aop == 2 && W == 1 && m == 2)
2242 {
2243 OUTS (outf, "W[");
2244 OUTS (outf, iregs (i));
2245 OUTS (outf, "] = ");
2246 OUTS (outf, dregs_hi (reg));
2247 }
2248 else if (aop == 3 && W == 0)
2249 {
2250 OUTS (outf, dregs (reg));
2251 OUTS (outf, " = [");
2252 OUTS (outf, iregs (i));
2253 OUTS (outf, " ++ ");
2254 OUTS (outf, mregs (m));
2255 OUTS (outf, "]");
2256 }
2257 else if (aop == 3 && W == 1)
2258 {
2259 OUTS (outf, "[");
2260 OUTS (outf, iregs (i));
2261 OUTS (outf, " ++ ");
2262 OUTS (outf, mregs (m));
2263 OUTS (outf, "] = ");
2264 OUTS (outf, dregs (reg));
2265 }
2266 else
2267 return 0;
2268
2269 return 2;
2270 }
2271
2272 static int
2273 decode_LDST_0 (TIword iw0, disassemble_info *outf)
2274 {
2275 /* LDST
2276 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2277 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2278 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2279 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2280 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2281 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2282 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2283 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2284 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2285
2286 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2287 {
2288 OUTS (outf, dregs (reg));
2289 OUTS (outf, " = [");
2290 OUTS (outf, pregs (ptr));
2291 OUTS (outf, "++]");
2292 }
2293 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2294 {
2295 OUTS (outf, pregs (reg));
2296 OUTS (outf, " = [");
2297 OUTS (outf, pregs (ptr));
2298 OUTS (outf, "++]");
2299 }
2300 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2301 {
2302 OUTS (outf, dregs (reg));
2303 OUTS (outf, " = W[");
2304 OUTS (outf, pregs (ptr));
2305 OUTS (outf, "++] (Z)");
2306 }
2307 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2308 {
2309 OUTS (outf, dregs (reg));
2310 OUTS (outf, " = W[");
2311 OUTS (outf, pregs (ptr));
2312 OUTS (outf, "++] (X)");
2313 }
2314 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2315 {
2316 OUTS (outf, dregs (reg));
2317 OUTS (outf, " = B[");
2318 OUTS (outf, pregs (ptr));
2319 OUTS (outf, "++] (Z)");
2320 }
2321 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2322 {
2323 OUTS (outf, dregs (reg));
2324 OUTS (outf, " = B[");
2325 OUTS (outf, pregs (ptr));
2326 OUTS (outf, "++] (X)");
2327 }
2328 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2329 {
2330 OUTS (outf, dregs (reg));
2331 OUTS (outf, " = [");
2332 OUTS (outf, pregs (ptr));
2333 OUTS (outf, "--]");
2334 }
2335 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2336 {
2337 OUTS (outf, pregs (reg));
2338 OUTS (outf, " = [");
2339 OUTS (outf, pregs (ptr));
2340 OUTS (outf, "--]");
2341 }
2342 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2343 {
2344 OUTS (outf, dregs (reg));
2345 OUTS (outf, " = W[");
2346 OUTS (outf, pregs (ptr));
2347 OUTS (outf, "--] (Z)");
2348 }
2349 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2350 {
2351 OUTS (outf, dregs (reg));
2352 OUTS (outf, " = W[");
2353 OUTS (outf, pregs (ptr));
2354 OUTS (outf, "--] (X)");
2355 }
2356 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2357 {
2358 OUTS (outf, dregs (reg));
2359 OUTS (outf, " = B[");
2360 OUTS (outf, pregs (ptr));
2361 OUTS (outf, "--] (Z)");
2362 }
2363 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2364 {
2365 OUTS (outf, dregs (reg));
2366 OUTS (outf, " = B[");
2367 OUTS (outf, pregs (ptr));
2368 OUTS (outf, "--] (X)");
2369 }
2370 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2371 {
2372 OUTS (outf, dregs (reg));
2373 OUTS (outf, " = [");
2374 OUTS (outf, pregs (ptr));
2375 OUTS (outf, "]");
2376 }
2377 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2378 {
2379 OUTS (outf, pregs (reg));
2380 OUTS (outf, " = [");
2381 OUTS (outf, pregs (ptr));
2382 OUTS (outf, "]");
2383 }
2384 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2385 {
2386 OUTS (outf, dregs (reg));
2387 OUTS (outf, " = W[");
2388 OUTS (outf, pregs (ptr));
2389 OUTS (outf, "] (Z)");
2390 }
2391 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2392 {
2393 OUTS (outf, dregs (reg));
2394 OUTS (outf, " = W[");
2395 OUTS (outf, pregs (ptr));
2396 OUTS (outf, "] (X)");
2397 }
2398 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2399 {
2400 OUTS (outf, dregs (reg));
2401 OUTS (outf, " = B[");
2402 OUTS (outf, pregs (ptr));
2403 OUTS (outf, "] (Z)");
2404 }
2405 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2406 {
2407 OUTS (outf, dregs (reg));
2408 OUTS (outf, " = B[");
2409 OUTS (outf, pregs (ptr));
2410 OUTS (outf, "] (X)");
2411 }
2412 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2413 {
2414 OUTS (outf, "[");
2415 OUTS (outf, pregs (ptr));
2416 OUTS (outf, "++] = ");
2417 OUTS (outf, dregs (reg));
2418 }
2419 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2420 {
2421 OUTS (outf, "[");
2422 OUTS (outf, pregs (ptr));
2423 OUTS (outf, "++] = ");
2424 OUTS (outf, pregs (reg));
2425 }
2426 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2427 {
2428 OUTS (outf, "W[");
2429 OUTS (outf, pregs (ptr));
2430 OUTS (outf, "++] = ");
2431 OUTS (outf, dregs (reg));
2432 }
2433 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2434 {
2435 OUTS (outf, "B[");
2436 OUTS (outf, pregs (ptr));
2437 OUTS (outf, "++] = ");
2438 OUTS (outf, dregs (reg));
2439 }
2440 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2441 {
2442 OUTS (outf, "[");
2443 OUTS (outf, pregs (ptr));
2444 OUTS (outf, "--] = ");
2445 OUTS (outf, dregs (reg));
2446 }
2447 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2448 {
2449 OUTS (outf, "[");
2450 OUTS (outf, pregs (ptr));
2451 OUTS (outf, "--] = ");
2452 OUTS (outf, pregs (reg));
2453 }
2454 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2455 {
2456 OUTS (outf, "W[");
2457 OUTS (outf, pregs (ptr));
2458 OUTS (outf, "--] = ");
2459 OUTS (outf, dregs (reg));
2460 }
2461 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2462 {
2463 OUTS (outf, "B[");
2464 OUTS (outf, pregs (ptr));
2465 OUTS (outf, "--] = ");
2466 OUTS (outf, dregs (reg));
2467 }
2468 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2469 {
2470 OUTS (outf, "[");
2471 OUTS (outf, pregs (ptr));
2472 OUTS (outf, "] = ");
2473 OUTS (outf, dregs (reg));
2474 }
2475 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2476 {
2477 OUTS (outf, "[");
2478 OUTS (outf, pregs (ptr));
2479 OUTS (outf, "] = ");
2480 OUTS (outf, pregs (reg));
2481 }
2482 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2483 {
2484 OUTS (outf, "W[");
2485 OUTS (outf, pregs (ptr));
2486 OUTS (outf, "] = ");
2487 OUTS (outf, dregs (reg));
2488 }
2489 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2490 {
2491 OUTS (outf, "B[");
2492 OUTS (outf, pregs (ptr));
2493 OUTS (outf, "] = ");
2494 OUTS (outf, dregs (reg));
2495 }
2496 else
2497 return 0;
2498
2499 return 2;
2500 }
2501
2502 static int
2503 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2504 {
2505 /* LDSTiiFP
2506 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2507 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2508 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2509 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2510 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2511 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2512
2513 if (W == 0)
2514 {
2515 OUTS (outf, dpregs (reg));
2516 OUTS (outf, " = [FP ");
2517 OUTS (outf, negimm5s4 (offset));
2518 OUTS (outf, "]");
2519 }
2520 else if (W == 1)
2521 {
2522 OUTS (outf, "[FP ");
2523 OUTS (outf, negimm5s4 (offset));
2524 OUTS (outf, "] = ");
2525 OUTS (outf, dpregs (reg));
2526 }
2527 else
2528 return 0;
2529
2530 return 2;
2531 }
2532
2533 static int
2534 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2535 {
2536 /* LDSTii
2537 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2538 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2539 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2540 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2541 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2542 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2543 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2544 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2545
2546 if (W == 0 && op == 0)
2547 {
2548 OUTS (outf, dregs (reg));
2549 OUTS (outf, " = [");
2550 OUTS (outf, pregs (ptr));
2551 OUTS (outf, " + ");
2552 OUTS (outf, uimm4s4 (offset));
2553 OUTS (outf, "]");
2554 }
2555 else if (W == 0 && op == 1)
2556 {
2557 OUTS (outf, dregs (reg));
2558 OUTS (outf, " = W[");
2559 OUTS (outf, pregs (ptr));
2560 OUTS (outf, " + ");
2561 OUTS (outf, uimm4s2 (offset));
2562 OUTS (outf, "] (Z)");
2563 }
2564 else if (W == 0 && op == 2)
2565 {
2566 OUTS (outf, dregs (reg));
2567 OUTS (outf, " = W[");
2568 OUTS (outf, pregs (ptr));
2569 OUTS (outf, " + ");
2570 OUTS (outf, uimm4s2 (offset));
2571 OUTS (outf, "] (X)");
2572 }
2573 else if (W == 0 && op == 3)
2574 {
2575 OUTS (outf, pregs (reg));
2576 OUTS (outf, " = [");
2577 OUTS (outf, pregs (ptr));
2578 OUTS (outf, " + ");
2579 OUTS (outf, uimm4s4 (offset));
2580 OUTS (outf, "]");
2581 }
2582 else if (W == 1 && op == 0)
2583 {
2584 OUTS (outf, "[");
2585 OUTS (outf, pregs (ptr));
2586 OUTS (outf, " + ");
2587 OUTS (outf, uimm4s4 (offset));
2588 OUTS (outf, "] = ");
2589 OUTS (outf, dregs (reg));
2590 }
2591 else if (W == 1 && op == 1)
2592 {
2593 OUTS (outf, "W[");
2594 OUTS (outf, pregs (ptr));
2595 OUTS (outf, " + ");
2596 OUTS (outf, uimm4s2 (offset));
2597 OUTS (outf, "] = ");
2598 OUTS (outf, dregs (reg));
2599 }
2600 else if (W == 1 && op == 3)
2601 {
2602 OUTS (outf, "[");
2603 OUTS (outf, pregs (ptr));
2604 OUTS (outf, " + ");
2605 OUTS (outf, uimm4s4 (offset));
2606 OUTS (outf, "] = ");
2607 OUTS (outf, pregs (reg));
2608 }
2609 else
2610 return 0;
2611
2612 return 2;
2613 }
2614
2615 static int
2616 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2617 {
2618 /* LoopSetup
2619 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2620 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2621 |.reg...........| - | - |.eoffset...............................|
2622 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2623 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2624 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2625 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2626 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2627 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2628
2629 if (parallel)
2630 return 0;
2631
2632 if (rop == 0)
2633 {
2634 OUTS (outf, "LSETUP");
2635 OUTS (outf, "(0x");
2636 OUTS (outf, pcrel4 (soffset));
2637 OUTS (outf, ", 0x");
2638 OUTS (outf, lppcrel10 (eoffset));
2639 OUTS (outf, ") ");
2640 OUTS (outf, counters (c));
2641 }
2642 else if (rop == 1)
2643 {
2644 OUTS (outf, "LSETUP");
2645 OUTS (outf, "(0x");
2646 OUTS (outf, pcrel4 (soffset));
2647 OUTS (outf, ", 0x");
2648 OUTS (outf, lppcrel10 (eoffset));
2649 OUTS (outf, ") ");
2650 OUTS (outf, counters (c));
2651 OUTS (outf, " = ");
2652 OUTS (outf, pregs (reg));
2653 }
2654 else if (rop == 3)
2655 {
2656 OUTS (outf, "LSETUP");
2657 OUTS (outf, "(0x");
2658 OUTS (outf, pcrel4 (soffset));
2659 OUTS (outf, ", 0x");
2660 OUTS (outf, lppcrel10 (eoffset));
2661 OUTS (outf, ") ");
2662 OUTS (outf, counters (c));
2663 OUTS (outf, " = ");
2664 OUTS (outf, pregs (reg));
2665 OUTS (outf, " >> 0x1");
2666 }
2667 else
2668 return 0;
2669
2670 return 4;
2671 }
2672
2673 static int
2674 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2675 {
2676 /* LDIMMhalf
2677 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2678 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2679 |.hword.........................................................|
2680 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2681 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2682 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2683 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2684 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2685 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2686 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2687
2688 bu32 *pval = get_allreg (grp, reg);
2689
2690 if (parallel)
2691 return 0;
2692
2693 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2694 to combine them, so it prints out the right values.
2695 Here we keep track of the registers. */
2696 if (H == 0 && S == 1 && Z == 0)
2697 {
2698 /* regs = imm16 (x) */
2699 *pval = imm16_val (hword);
2700 if (hword & 0x8000)
2701 *pval |= 0xFFFF0000;
2702 else
2703 *pval &= 0xFFFF;
2704 }
2705 else if (H == 0 && S == 0 && Z == 1)
2706 {
2707 /* regs = luimm16 (Z) */
2708 *pval = luimm16_val (hword);
2709 *pval &= 0xFFFF;
2710 }
2711 else if (H == 0 && S == 0 && Z == 0)
2712 {
2713 /* regs_lo = luimm16 */
2714 *pval &= 0xFFFF0000;
2715 *pval |= luimm16_val (hword);
2716 }
2717 else if (H == 1 && S == 0 && Z == 0)
2718 {
2719 /* regs_hi = huimm16 */
2720 *pval &= 0xFFFF;
2721 *pval |= luimm16_val (hword) << 16;
2722 }
2723
2724 /* Here we do the disassembly */
2725 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2726 {
2727 OUTS (outf, dregs_lo (reg));
2728 OUTS (outf, " = ");
2729 OUTS (outf, uimm16 (hword));
2730 }
2731 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2732 {
2733 OUTS (outf, dregs_hi (reg));
2734 OUTS (outf, " = ");
2735 OUTS (outf, uimm16 (hword));
2736 }
2737 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2738 {
2739 OUTS (outf, dregs (reg));
2740 OUTS (outf, " = ");
2741 OUTS (outf, imm16 (hword));
2742 OUTS (outf, " (X)");
2743 }
2744 else if (H == 0 && S == 1 && Z == 0)
2745 {
2746 OUTS (outf, regs (reg, grp));
2747 OUTS (outf, " = ");
2748 OUTS (outf, imm16 (hword));
2749 OUTS (outf, " (X)");
2750 }
2751 else if (H == 0 && S == 0 && Z == 1)
2752 {
2753 OUTS (outf, regs (reg, grp));
2754 OUTS (outf, " = ");
2755 OUTS (outf, uimm16 (hword));
2756 OUTS (outf, " (Z)");
2757 }
2758 else if (H == 0 && S == 0 && Z == 0)
2759 {
2760 OUTS (outf, regs_lo (reg, grp));
2761 OUTS (outf, " = ");
2762 OUTS (outf, uimm16 (hword));
2763 }
2764 else if (H == 1 && S == 0 && Z == 0)
2765 {
2766 OUTS (outf, regs_hi (reg, grp));
2767 OUTS (outf, " = ");
2768 OUTS (outf, uimm16 (hword));
2769 }
2770 else
2771 return 0;
2772
2773 /* And we print out the 32-bit value if it is a pointer. */
2774 if (S == 0 && Z == 0)
2775 {
2776 OUTS (outf, ";\t\t/* (");
2777 OUTS (outf, imm16d (hword));
2778 OUTS (outf, ")\t");
2779
2780 /* If it is an MMR, don't print the symbol. */
2781 if (*pval < 0xFFC00000 && grp == 1)
2782 {
2783 OUTS (outf, regs (reg, grp));
2784 OUTS (outf, "=0x");
2785 OUTS (outf, huimm32e (*pval));
2786 }
2787 else
2788 {
2789 OUTS (outf, regs (reg, grp));
2790 OUTS (outf, "=0x");
2791 OUTS (outf, huimm32e (*pval));
2792 OUTS (outf, "(");
2793 OUTS (outf, imm32 (*pval));
2794 OUTS (outf, ")");
2795 }
2796
2797 OUTS (outf, " */");
2798 comment = 1;
2799 }
2800 if (S == 1 || Z == 1)
2801 {
2802 OUTS (outf, ";\t\t/*\t\t");
2803 OUTS (outf, regs (reg, grp));
2804 OUTS (outf, "=0x");
2805 OUTS (outf, huimm32e (*pval));
2806 OUTS (outf, "(");
2807 OUTS (outf, imm32 (*pval));
2808 OUTS (outf, ") */");
2809 comment = 1;
2810 }
2811 return 4;
2812 }
2813
2814 static int
2815 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2816 {
2817 /* CALLa
2818 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2819 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2820 |.lsw...........................................................|
2821 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2822 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2823 int lsw = ((iw1 >> 0) & 0xffff);
2824 int msw = ((iw0 >> 0) & 0xff);
2825
2826 if (parallel)
2827 return 0;
2828
2829 if (S == 1)
2830 OUTS (outf, "CALL 0x");
2831 else if (S == 0)
2832 OUTS (outf, "JUMP.L 0x");
2833 else
2834 return 0;
2835
2836 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2837 return 4;
2838 }
2839
2840 static int
2841 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2842 {
2843 /* LDSTidxI
2844 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2845 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2846 |.offset........................................................|
2847 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2848 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2849 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2850 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2851 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2852 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2853 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2854
2855 if (W == 0 && sz == 0 && Z == 0)
2856 {
2857 OUTS (outf, dregs (reg));
2858 OUTS (outf, " = [");
2859 OUTS (outf, pregs (ptr));
2860 OUTS (outf, " + ");
2861 OUTS (outf, imm16s4 (offset));
2862 OUTS (outf, "]");
2863 }
2864 else if (W == 0 && sz == 0 && Z == 1)
2865 {
2866 OUTS (outf, pregs (reg));
2867 OUTS (outf, " = [");
2868 OUTS (outf, pregs (ptr));
2869 OUTS (outf, " + ");
2870 OUTS (outf, imm16s4 (offset));
2871 OUTS (outf, "]");
2872 }
2873 else if (W == 0 && sz == 1 && Z == 0)
2874 {
2875 OUTS (outf, dregs (reg));
2876 OUTS (outf, " = W[");
2877 OUTS (outf, pregs (ptr));
2878 OUTS (outf, " + ");
2879 OUTS (outf, imm16s2 (offset));
2880 OUTS (outf, "] (Z)");
2881 }
2882 else if (W == 0 && sz == 1 && Z == 1)
2883 {
2884 OUTS (outf, dregs (reg));
2885 OUTS (outf, " = W[");
2886 OUTS (outf, pregs (ptr));
2887 OUTS (outf, " + ");
2888 OUTS (outf, imm16s2 (offset));
2889 OUTS (outf, "] (X)");
2890 }
2891 else if (W == 0 && sz == 2 && Z == 0)
2892 {
2893 OUTS (outf, dregs (reg));
2894 OUTS (outf, " = B[");
2895 OUTS (outf, pregs (ptr));
2896 OUTS (outf, " + ");
2897 OUTS (outf, imm16 (offset));
2898 OUTS (outf, "] (Z)");
2899 }
2900 else if (W == 0 && sz == 2 && Z == 1)
2901 {
2902 OUTS (outf, dregs (reg));
2903 OUTS (outf, " = B[");
2904 OUTS (outf, pregs (ptr));
2905 OUTS (outf, " + ");
2906 OUTS (outf, imm16 (offset));
2907 OUTS (outf, "] (X)");
2908 }
2909 else if (W == 1 && sz == 0 && Z == 0)
2910 {
2911 OUTS (outf, "[");
2912 OUTS (outf, pregs (ptr));
2913 OUTS (outf, " + ");
2914 OUTS (outf, imm16s4 (offset));
2915 OUTS (outf, "] = ");
2916 OUTS (outf, dregs (reg));
2917 }
2918 else if (W == 1 && sz == 0 && Z == 1)
2919 {
2920 OUTS (outf, "[");
2921 OUTS (outf, pregs (ptr));
2922 OUTS (outf, " + ");
2923 OUTS (outf, imm16s4 (offset));
2924 OUTS (outf, "] = ");
2925 OUTS (outf, pregs (reg));
2926 }
2927 else if (W == 1 && sz == 1 && Z == 0)
2928 {
2929 OUTS (outf, "W[");
2930 OUTS (outf, pregs (ptr));
2931 OUTS (outf, " + ");
2932 OUTS (outf, imm16s2 (offset));
2933 OUTS (outf, "] = ");
2934 OUTS (outf, dregs (reg));
2935 }
2936 else if (W == 1 && sz == 2 && Z == 0)
2937 {
2938 OUTS (outf, "B[");
2939 OUTS (outf, pregs (ptr));
2940 OUTS (outf, " + ");
2941 OUTS (outf, imm16 (offset));
2942 OUTS (outf, "] = ");
2943 OUTS (outf, dregs (reg));
2944 }
2945 else
2946 return 0;
2947
2948 return 4;
2949 }
2950
2951 static int
2952 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2953 {
2954 /* linkage
2955 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2956 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2957 |.framesize.....................................................|
2958 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2959 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2960 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2961
2962 if (parallel)
2963 return 0;
2964
2965 if (R == 0)
2966 {
2967 OUTS (outf, "LINK ");
2968 OUTS (outf, uimm16s4 (framesize));
2969 OUTS (outf, ";\t\t/* (");
2970 OUTS (outf, uimm16s4d (framesize));
2971 OUTS (outf, ") */");
2972 comment = 1;
2973 }
2974 else if (R == 1)
2975 OUTS (outf, "UNLINK");
2976 else
2977 return 0;
2978
2979 return 4;
2980 }
2981
2982 static int
2983 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2984 {
2985 /* dsp32mac
2986 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2987 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2988 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2989 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2990 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2991 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2992 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2993 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2994 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2995 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2996 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2997 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2998 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2999 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3000 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3001 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
3002 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3003 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3004
3005 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
3006 return 0;
3007
3008 if (op1 == 3 && MM)
3009 return 0;
3010
3011 if ((w1 || w0) && mmod == M_W32)
3012 return 0;
3013
3014 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
3015 return 0;
3016
3017 if (w1 == 1 || op1 != 3)
3018 {
3019 if (w1)
3020 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3021
3022 if (op1 == 3)
3023 OUTS (outf, " = A1");
3024 else
3025 {
3026 if (w1)
3027 OUTS (outf, " = (");
3028 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
3029 if (w1)
3030 OUTS (outf, ")");
3031 }
3032
3033 if (w0 == 1 || op0 != 3)
3034 {
3035 if (MM)
3036 OUTS (outf, " (M)");
3037 MM = 0;
3038 OUTS (outf, ", ");
3039 }
3040 }
3041
3042 if (w0 == 1 || op0 != 3)
3043 {
3044 if (w0)
3045 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3046
3047 if (op0 == 3)
3048 OUTS (outf, " = A0");
3049 else
3050 {
3051 if (w0)
3052 OUTS (outf, " = (");
3053 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3054 if (w0)
3055 OUTS (outf, ")");
3056 }
3057 }
3058
3059 decode_optmode (mmod, MM, outf);
3060
3061 return 4;
3062 }
3063
3064 static int
3065 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3066 {
3067 /* dsp32mult
3068 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3069 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3070 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3071 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3072 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3073 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3074 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
3075 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
3076 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3077 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3078 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3079 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3080 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3081 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3082 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3083 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3084
3085 if (w1 == 0 && w0 == 0)
3086 return 0;
3087
3088 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3089 return 0;
3090
3091 if (w1)
3092 {
3093 OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
3094 OUTS (outf, " = ");
3095 decode_multfunc (h01, h11, src0, src1, outf);
3096
3097 if (w0)
3098 {
3099 if (MM)
3100 OUTS (outf, " (M)");
3101 MM = 0;
3102 OUTS (outf, ", ");
3103 }
3104 }
3105
3106 if (w0)
3107 {
3108 OUTS (outf, dregs (dst));
3109 OUTS (outf, " = ");
3110 decode_multfunc (h00, h10, src0, src1, outf);
3111 }
3112
3113 decode_optmode (mmod, MM, outf);
3114 return 4;
3115 }
3116
3117 static int
3118 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3119 {
3120 /* dsp32alu
3121 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3122 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3123 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3124 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3125 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3126 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3127 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3128 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3129 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3130 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3131 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3132 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3133 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3134
3135 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3136 {
3137 OUTS (outf, "A0.L = ");
3138 OUTS (outf, dregs_lo (src0));
3139 }
3140 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3141 {
3142 OUTS (outf, "A1.H = ");
3143 OUTS (outf, dregs_hi (src0));
3144 }
3145 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3146 {
3147 OUTS (outf, "A1.L = ");
3148 OUTS (outf, dregs_lo (src0));
3149 }
3150 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3151 {
3152 OUTS (outf, "A0.H = ");
3153 OUTS (outf, dregs_hi (src0));
3154 }
3155 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3156 {
3157 OUTS (outf, dregs_hi (dst0));
3158 OUTS (outf, " = ");
3159 OUTS (outf, dregs (src0));
3160 OUTS (outf, " - ");
3161 OUTS (outf, dregs (src1));
3162 OUTS (outf, " (RND20)");
3163 }
3164 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3165 {
3166 OUTS (outf, dregs_hi (dst0));
3167 OUTS (outf, " = ");
3168 OUTS (outf, dregs (src0));
3169 OUTS (outf, " + ");
3170 OUTS (outf, dregs (src1));
3171 OUTS (outf, " (RND20)");
3172 }
3173 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3174 {
3175 OUTS (outf, dregs_lo (dst0));
3176 OUTS (outf, " = ");
3177 OUTS (outf, dregs (src0));
3178 OUTS (outf, " - ");
3179 OUTS (outf, dregs (src1));
3180 OUTS (outf, " (RND12)");
3181 }
3182 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3183 {
3184 OUTS (outf, dregs_lo (dst0));
3185 OUTS (outf, " = ");
3186 OUTS (outf, dregs (src0));
3187 OUTS (outf, " + ");
3188 OUTS (outf, dregs (src1));
3189 OUTS (outf, " (RND12)");
3190 }
3191 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3192 {
3193 OUTS (outf, dregs_lo (dst0));
3194 OUTS (outf, " = ");
3195 OUTS (outf, dregs (src0));
3196 OUTS (outf, " - ");
3197 OUTS (outf, dregs (src1));
3198 OUTS (outf, " (RND20)");
3199 }
3200 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3201 {
3202 OUTS (outf, dregs_hi (dst0));
3203 OUTS (outf, " = ");
3204 OUTS (outf, dregs (src0));
3205 OUTS (outf, " + ");
3206 OUTS (outf, dregs (src1));
3207 OUTS (outf, " (RND12)");
3208 }
3209 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3210 {
3211 OUTS (outf, dregs_lo (dst0));
3212 OUTS (outf, " = ");
3213 OUTS (outf, dregs (src0));
3214 OUTS (outf, " + ");
3215 OUTS (outf, dregs (src1));
3216 OUTS (outf, " (RND20)");
3217 }
3218 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3219 {
3220 OUTS (outf, dregs_hi (dst0));
3221 OUTS (outf, " = ");
3222 OUTS (outf, dregs (src0));
3223 OUTS (outf, " - ");
3224 OUTS (outf, dregs (src1));
3225 OUTS (outf, " (RND12)");
3226 }
3227 else if (HL == 1 && aop == 0 && aopcde == 2)
3228 {
3229 OUTS (outf, dregs_hi (dst0));
3230 OUTS (outf, " = ");
3231 OUTS (outf, dregs_lo (src0));
3232 OUTS (outf, " + ");
3233 OUTS (outf, dregs_lo (src1));
3234 amod1 (s, x, outf);
3235 }
3236 else if (HL == 1 && aop == 1 && aopcde == 2)
3237 {
3238 OUTS (outf, dregs_hi (dst0));
3239 OUTS (outf, " = ");
3240 OUTS (outf, dregs_lo (src0));
3241 OUTS (outf, " + ");
3242 OUTS (outf, dregs_hi (src1));
3243 amod1 (s, x, outf);
3244 }
3245 else if (HL == 1 && aop == 2 && aopcde == 2)
3246 {
3247 OUTS (outf, dregs_hi (dst0));
3248 OUTS (outf, " = ");
3249 OUTS (outf, dregs_hi (src0));
3250 OUTS (outf, " + ");
3251 OUTS (outf, dregs_lo (src1));
3252 amod1 (s, x, outf);
3253 }
3254 else if (HL == 1 && aop == 3 && aopcde == 2)
3255 {
3256 OUTS (outf, dregs_hi (dst0));
3257 OUTS (outf, " = ");
3258 OUTS (outf, dregs_hi (src0));
3259 OUTS (outf, " + ");
3260 OUTS (outf, dregs_hi (src1));
3261 amod1 (s, x, outf);
3262 }
3263 else if (HL == 0 && aop == 0 && aopcde == 3)
3264 {
3265 OUTS (outf, dregs_lo (dst0));
3266 OUTS (outf, " = ");
3267 OUTS (outf, dregs_lo (src0));
3268 OUTS (outf, " - ");
3269 OUTS (outf, dregs_lo (src1));
3270 amod1 (s, x, outf);
3271 }
3272 else if (HL == 0 && aop == 1 && aopcde == 3)
3273 {
3274 OUTS (outf, dregs_lo (dst0));
3275 OUTS (outf, " = ");
3276 OUTS (outf, dregs_lo (src0));
3277 OUTS (outf, " - ");
3278 OUTS (outf, dregs_hi (src1));
3279 amod1 (s, x, outf);
3280 }
3281 else if (HL == 0 && aop == 3 && aopcde == 2)
3282 {
3283 OUTS (outf, dregs_lo (dst0));
3284 OUTS (outf, " = ");
3285 OUTS (outf, dregs_hi (src0));
3286 OUTS (outf, " + ");
3287 OUTS (outf, dregs_hi (src1));
3288 amod1 (s, x, outf);
3289 }
3290 else if (HL == 1 && aop == 0 && aopcde == 3)
3291 {
3292 OUTS (outf, dregs_hi (dst0));
3293 OUTS (outf, " = ");
3294 OUTS (outf, dregs_lo (src0));
3295 OUTS (outf, " - ");
3296 OUTS (outf, dregs_lo (src1));
3297 amod1 (s, x, outf);
3298 }
3299 else if (HL == 1 && aop == 1 && aopcde == 3)
3300 {
3301 OUTS (outf, dregs_hi (dst0));
3302 OUTS (outf, " = ");
3303 OUTS (outf, dregs_lo (src0));
3304 OUTS (outf, " - ");
3305 OUTS (outf, dregs_hi (src1));
3306 amod1 (s, x, outf);
3307 }
3308 else if (HL == 1 && aop == 2 && aopcde == 3)
3309 {
3310 OUTS (outf, dregs_hi (dst0));
3311 OUTS (outf, " = ");
3312 OUTS (outf, dregs_hi (src0));
3313 OUTS (outf, " - ");
3314 OUTS (outf, dregs_lo (src1));
3315 amod1 (s, x, outf);
3316 }
3317 else if (HL == 1 && aop == 3 && aopcde == 3)
3318 {
3319 OUTS (outf, dregs_hi (dst0));
3320 OUTS (outf, " = ");
3321 OUTS (outf, dregs_hi (src0));
3322 OUTS (outf, " - ");
3323 OUTS (outf, dregs_hi (src1));
3324 amod1 (s, x, outf);
3325 }
3326 else if (HL == 0 && aop == 2 && aopcde == 2)
3327 {
3328 OUTS (outf, dregs_lo (dst0));
3329 OUTS (outf, " = ");
3330 OUTS (outf, dregs_hi (src0));
3331 OUTS (outf, " + ");
3332 OUTS (outf, dregs_lo (src1));
3333 amod1 (s, x, outf);
3334 }
3335 else if (HL == 0 && aop == 1 && aopcde == 2)
3336 {
3337 OUTS (outf, dregs_lo (dst0));
3338 OUTS (outf, " = ");
3339 OUTS (outf, dregs_lo (src0));
3340 OUTS (outf, " + ");
3341 OUTS (outf, dregs_hi (src1));
3342 amod1 (s, x, outf);
3343 }
3344 else if (HL == 0 && aop == 2 && aopcde == 3)
3345 {
3346 OUTS (outf, dregs_lo (dst0));
3347 OUTS (outf, " = ");
3348 OUTS (outf, dregs_hi (src0));
3349 OUTS (outf, " - ");
3350 OUTS (outf, dregs_lo (src1));
3351 amod1 (s, x, outf);
3352 }
3353 else if (HL == 0 && aop == 3 && aopcde == 3)
3354 {
3355 OUTS (outf, dregs_lo (dst0));
3356 OUTS (outf, " = ");
3357 OUTS (outf, dregs_hi (src0));
3358 OUTS (outf, " - ");
3359 OUTS (outf, dregs_hi (src1));
3360 amod1 (s, x, outf);
3361 }
3362 else if (HL == 0 && aop == 0 && aopcde == 2)
3363 {
3364 OUTS (outf, dregs_lo (dst0));
3365 OUTS (outf, " = ");
3366 OUTS (outf, dregs_lo (src0));
3367 OUTS (outf, " + ");
3368 OUTS (outf, dregs_lo (src1));
3369 amod1 (s, x, outf);
3370 }
3371 else if (aop == 0 && aopcde == 9 && s == 1)
3372 {
3373 OUTS (outf, "A0 = ");
3374 OUTS (outf, dregs (src0));
3375 }
3376 else if (aop == 3 && aopcde == 11 && s == 0)
3377 OUTS (outf, "A0 -= A1");
3378
3379 else if (aop == 3 && aopcde == 11 && s == 1)
3380 OUTS (outf, "A0 -= A1 (W32)");
3381
3382 else if (aop == 3 && aopcde == 22 && HL == 1)
3383 {
3384 OUTS (outf, dregs (dst0));
3385 OUTS (outf, " = BYTEOP2M (");
3386 OUTS (outf, dregs (src0 + 1));
3387 OUTS (outf, ":");
3388 OUTS (outf, imm5 (src0));
3389 OUTS (outf, ", ");
3390 OUTS (outf, dregs (src1 + 1));
3391 OUTS (outf, ":");
3392 OUTS (outf, imm5 (src1));
3393 OUTS (outf, ") (TH");
3394 if (s == 1)
3395 OUTS (outf, ", R)");
3396 else
3397 OUTS (outf, ")");
3398 }
3399 else if (aop == 3 && aopcde == 22 && HL == 0)
3400 {
3401 OUTS (outf, dregs (dst0));
3402 OUTS (outf, " = BYTEOP2M (");
3403 OUTS (outf, dregs (src0 + 1));
3404 OUTS (outf, ":");
3405 OUTS (outf, imm5 (src0));
3406 OUTS (outf, ", ");
3407 OUTS (outf, dregs (src1 + 1));
3408 OUTS (outf, ":");
3409 OUTS (outf, imm5 (src1));
3410 OUTS (outf, ") (TL");
3411 if (s == 1)
3412 OUTS (outf, ", R)");
3413 else
3414 OUTS (outf, ")");
3415 }
3416 else if (aop == 2 && aopcde == 22 && HL == 1)
3417 {
3418 OUTS (outf, dregs (dst0));
3419 OUTS (outf, " = BYTEOP2M (");
3420 OUTS (outf, dregs (src0 + 1));
3421 OUTS (outf, ":");
3422 OUTS (outf, imm5 (src0));
3423 OUTS (outf, ", ");
3424 OUTS (outf, dregs (src1 + 1));
3425 OUTS (outf, ":");
3426 OUTS (outf, imm5 (src1));
3427 OUTS (outf, ") (RNDH");
3428 if (s == 1)
3429 OUTS (outf, ", R)");
3430 else
3431 OUTS (outf, ")");
3432 }
3433 else if (aop == 2 && aopcde == 22 && HL == 0)
3434 {
3435 OUTS (outf, dregs (dst0));
3436 OUTS (outf, " = BYTEOP2M (");
3437 OUTS (outf, dregs (src0 + 1));
3438 OUTS (outf, ":");
3439 OUTS (outf, imm5 (src0));
3440 OUTS (outf, ", ");
3441 OUTS (outf, dregs (src1 + 1));
3442 OUTS (outf, ":");
3443 OUTS (outf, imm5 (src1));
3444 OUTS (outf, ") (RNDL");
3445 if (s == 1)
3446 OUTS (outf, ", R)");
3447 else
3448 OUTS (outf, ")");
3449 }
3450 else if (aop == 1 && aopcde == 22 && HL == 1)
3451 {
3452 OUTS (outf, dregs (dst0));
3453 OUTS (outf, " = BYTEOP2P (");
3454 OUTS (outf, dregs (src0 + 1));
3455 OUTS (outf, ":");
3456 OUTS (outf, imm5d (src0));
3457 OUTS (outf, ", ");
3458 OUTS (outf, dregs (src1 + 1));
3459 OUTS (outf, ":");
3460 OUTS (outf, imm5d (src1));
3461 OUTS (outf, ") (TH");
3462 if (s == 1)
3463 OUTS (outf, ", R)");
3464 else
3465 OUTS (outf, ")");
3466 }
3467 else if (aop == 1 && aopcde == 22 && HL == 0)
3468 {
3469 OUTS (outf, dregs (dst0));
3470 OUTS (outf, " = BYTEOP2P (");
3471 OUTS (outf, dregs (src0 + 1));
3472 OUTS (outf, ":");
3473 OUTS (outf, imm5d (src0));
3474 OUTS (outf, ", ");
3475 OUTS (outf, dregs (src1 + 1));
3476 OUTS (outf, ":");
3477 OUTS (outf, imm5d (src1));
3478 OUTS (outf, ") (TL");
3479 if (s == 1)
3480 OUTS (outf, ", R)");
3481 else
3482 OUTS (outf, ")");
3483 }
3484 else if (aop == 0 && aopcde == 22 && HL == 1)
3485 {
3486 OUTS (outf, dregs (dst0));
3487 OUTS (outf, " = BYTEOP2P (");
3488 OUTS (outf, dregs (src0 + 1));
3489 OUTS (outf, ":");
3490 OUTS (outf, imm5d (src0));
3491 OUTS (outf, ", ");
3492 OUTS (outf, dregs (src1 + 1));
3493 OUTS (outf, ":");
3494 OUTS (outf, imm5d (src1));
3495 OUTS (outf, ") (RNDH");
3496 if (s == 1)
3497 OUTS (outf, ", R)");
3498 else
3499 OUTS (outf, ")");
3500 }
3501 else if (aop == 0 && aopcde == 22 && HL == 0)
3502 {
3503 OUTS (outf, dregs (dst0));
3504 OUTS (outf, " = BYTEOP2P (");
3505 OUTS (outf, dregs (src0 + 1));
3506 OUTS (outf, ":");
3507 OUTS (outf, imm5d (src0));
3508 OUTS (outf, ", ");
3509 OUTS (outf, dregs (src1 + 1));
3510 OUTS (outf, ":");
3511 OUTS (outf, imm5d (src1));
3512 OUTS (outf, ") (RNDL");
3513 if (s == 1)
3514 OUTS (outf, ", R)");
3515 else
3516 OUTS (outf, ")");
3517 }
3518 else if (aop == 0 && s == 0 && aopcde == 8)
3519 OUTS (outf, "A0 = 0");
3520
3521 else if (aop == 0 && s == 1 && aopcde == 8)
3522 OUTS (outf, "A0 = A0 (S)");
3523
3524 else if (aop == 1 && s == 0 && aopcde == 8)
3525 OUTS (outf, "A1 = 0");
3526
3527 else if (aop == 1 && s == 1 && aopcde == 8)
3528 OUTS (outf, "A1 = A1 (S)");
3529
3530 else if (aop == 2 && s == 0 && aopcde == 8)
3531 OUTS (outf, "A1 = A0 = 0");
3532
3533 else if (aop == 2 && s == 1 && aopcde == 8)
3534 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3535
3536 else if (aop == 3 && s == 0 && aopcde == 8)
3537 OUTS (outf, "A0 = A1");
3538
3539 else if (aop == 3 && s == 1 && aopcde == 8)
3540 OUTS (outf, "A1 = A0");
3541
3542 else if (aop == 1 && aopcde == 9 && s == 0)
3543 {
3544 OUTS (outf, "A0.X = ");
3545 OUTS (outf, dregs_lo (src0));
3546 }
3547 else if (aop == 1 && HL == 0 && aopcde == 11)
3548 {
3549 OUTS (outf, dregs_lo (dst0));
3550 OUTS (outf, " = (A0 += A1)");
3551 }
3552 else if (aop == 3 && HL == 0 && aopcde == 16)
3553 OUTS (outf, "A1 = ABS A0, A0 = ABS A0");
3554
3555 else if (aop == 0 && aopcde == 23 && HL == 1)
3556 {
3557 OUTS (outf, dregs (dst0));
3558 OUTS (outf, " = BYTEOP3P (");
3559 OUTS (outf, dregs (src0 + 1));
3560 OUTS (outf, ":");
3561 OUTS (outf, imm5d (src0));
3562 OUTS (outf, ", ");
3563 OUTS (outf, dregs (src1 + 1));
3564 OUTS (outf, ":");
3565 OUTS (outf, imm5d (src1));
3566 OUTS (outf, ") (HI");
3567 if (s == 1)
3568 OUTS (outf, ", R)");
3569 else
3570 OUTS (outf, ")");
3571 }
3572 else if (aop == 3 && aopcde == 9 && s == 0)
3573 {
3574 OUTS (outf, "A1.X = ");
3575 OUTS (outf, dregs_lo (src0));
3576 }
3577 else if (aop == 1 && HL == 1 && aopcde == 16)
3578 OUTS (outf, "A1 = ABS A1");
3579
3580 else if (aop == 0 && HL == 1 && aopcde == 16)
3581 OUTS (outf, "A1 = ABS A0");
3582
3583 else if (aop == 2 && aopcde == 9 && s == 1)
3584 {
3585 OUTS (outf, "A1 = ");
3586 OUTS (outf, dregs (src0));
3587 }
3588 else if (HL == 0 && aop == 3 && aopcde == 12)
3589 {
3590 OUTS (outf, dregs_lo (dst0));
3591 OUTS (outf, " = ");
3592 OUTS (outf, dregs (src0));
3593 OUTS (outf, " (RND)");
3594 }
3595 else if (aop == 1 && HL == 0 && aopcde == 16)
3596 OUTS (outf, "A0 = ABS A1");
3597
3598 else if (aop == 0 && HL == 0 && aopcde == 16)
3599 OUTS (outf, "A0 = ABS A0");
3600
3601 else if (aop == 3 && HL == 0 && aopcde == 15)
3602 {
3603 OUTS (outf, dregs (dst0));
3604 OUTS (outf, " = -");
3605 OUTS (outf, dregs (src0));
3606 OUTS (outf, " (V)");
3607 }
3608 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3609 {
3610 OUTS (outf, dregs (dst0));
3611 OUTS (outf, " = -");
3612 OUTS (outf, dregs (src0));
3613 OUTS (outf, " (S)");
3614 }
3615 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3616 {
3617 OUTS (outf, dregs (dst0));
3618 OUTS (outf, " = -");
3619 OUTS (outf, dregs (src0));
3620 OUTS (outf, " (NS)");
3621 }
3622 else if (aop == 1 && HL == 1 && aopcde == 11)
3623 {
3624 OUTS (outf, dregs_hi (dst0));
3625 OUTS (outf, " = (A0 += A1)");
3626 }
3627 else if (aop == 2 && aopcde == 11 && s == 0)
3628 OUTS (outf, "A0 += A1");
3629
3630 else if (aop == 2 && aopcde == 11 && s == 1)
3631 OUTS (outf, "A0 += A1 (W32)");
3632
3633 else if (aop == 3 && HL == 0 && aopcde == 14)
3634 OUTS (outf, "A1 = -A1, A0 = -A0");
3635
3636 else if (HL == 1 && aop == 3 && aopcde == 12)
3637 {
3638 OUTS (outf, dregs_hi (dst0));
3639 OUTS (outf, " = ");
3640 OUTS (outf, dregs (src0));
3641 OUTS (outf, " (RND)");
3642 }
3643 else if (aop == 0 && aopcde == 23 && HL == 0)
3644 {
3645 OUTS (outf, dregs (dst0));
3646 OUTS (outf, " = BYTEOP3P (");
3647 OUTS (outf, dregs (src0 + 1));
3648 OUTS (outf, ":");
3649 OUTS (outf, imm5d (src0));
3650 OUTS (outf, ", ");
3651 OUTS (outf, dregs (src1 + 1));
3652 OUTS (outf, ":");
3653 OUTS (outf, imm5d (src1));
3654 OUTS (outf, ") (LO");
3655 if (s == 1)
3656 OUTS (outf, ", R)");
3657 else
3658 OUTS (outf, ")");
3659 }
3660 else if (aop == 0 && HL == 0 && aopcde == 14)
3661 OUTS (outf, "A0 = -A0");
3662
3663 else if (aop == 1 && HL == 0 && aopcde == 14)
3664 OUTS (outf, "A0 = -A1");
3665
3666 else if (aop == 0 && HL == 1 && aopcde == 14)
3667 OUTS (outf, "A1 = -A0");
3668
3669 else if (aop == 1 && HL == 1 && aopcde == 14)
3670 OUTS (outf, "A1 = -A1");
3671
3672 else if (aop == 0 && aopcde == 12)
3673 {
3674 OUTS (outf, dregs_hi (dst0));
3675 OUTS (outf, " = ");
3676 OUTS (outf, dregs_lo (dst0));
3677 OUTS (outf, " = SIGN (");
3678 OUTS (outf, dregs_hi (src0));
3679 OUTS (outf, ") * ");
3680 OUTS (outf, dregs_hi (src1));
3681 OUTS (outf, " + SIGN (");
3682 OUTS (outf, dregs_lo (src0));
3683 OUTS (outf, ") * ");
3684 OUTS (outf, dregs_lo (src1));
3685 }
3686 else if (aop == 2 && aopcde == 0)
3687 {
3688 OUTS (outf, dregs (dst0));
3689 OUTS (outf, " = ");
3690 OUTS (outf, dregs (src0));
3691 OUTS (outf, " -|+ ");
3692 OUTS (outf, dregs (src1));
3693 amod0 (s, x, outf);
3694 }
3695 else if (aop == 1 && aopcde == 12)
3696 {
3697 OUTS (outf, dregs (dst1));
3698 OUTS (outf, " = A1.L + A1.H, ");
3699 OUTS (outf, dregs (dst0));
3700 OUTS (outf, " = A0.L + A0.H");
3701 }
3702 else if (aop == 2 && aopcde == 4)
3703 {
3704 OUTS (outf, dregs (dst1));
3705 OUTS (outf, " = ");
3706 OUTS (outf, dregs (src0));
3707 OUTS (outf, " + ");
3708 OUTS (outf, dregs (src1));
3709 OUTS (outf, ", ");
3710 OUTS (outf, dregs (dst0));
3711 OUTS (outf, " = ");
3712 OUTS (outf, dregs (src0));
3713 OUTS (outf, " - ");
3714 OUTS (outf, dregs (src1));
3715 amod1 (s, x, outf);
3716 }
3717 else if (HL == 0 && aopcde == 1)
3718 {
3719 OUTS (outf, dregs (dst1));
3720 OUTS (outf, " = ");
3721 OUTS (outf, dregs (src0));
3722 OUTS (outf, " +|+ ");
3723 OUTS (outf, dregs (src1));
3724 OUTS (outf, ", ");
3725 OUTS (outf, dregs (dst0));
3726 OUTS (outf, " = ");
3727 OUTS (outf, dregs (src0));
3728 OUTS (outf, " -|- ");
3729 OUTS (outf, dregs (src1));
3730 amod0amod2 (s, x, aop, outf);
3731 }
3732 else if (aop == 0 && aopcde == 11)
3733 {
3734 OUTS (outf, dregs (dst0));
3735 OUTS (outf, " = (A0 += A1)");
3736 }
3737 else if (aop == 0 && aopcde == 10)
3738 {
3739 OUTS (outf, dregs_lo (dst0));
3740 OUTS (outf, " = A0.X");
3741 }
3742 else if (aop == 1 && aopcde == 10)
3743 {
3744 OUTS (outf, dregs_lo (dst0));
3745 OUTS (outf, " = A1.X");
3746 }
3747 else if (aop == 1 && aopcde == 0)
3748 {
3749 OUTS (outf, dregs (dst0));
3750 OUTS (outf, " = ");
3751 OUTS (outf, dregs (src0));
3752 OUTS (outf, " +|- ");
3753 OUTS (outf, dregs (src1));
3754 amod0 (s, x, outf);
3755 }
3756 else if (aop == 3 && aopcde == 0)
3757 {
3758 OUTS (outf, dregs (dst0));
3759 OUTS (outf, " = ");
3760 OUTS (outf, dregs (src0));
3761 OUTS (outf, " -|- ");
3762 OUTS (outf, dregs (src1));
3763 amod0 (s, x, outf);
3764 }
3765 else if (aop == 1 && aopcde == 4)
3766 {
3767 OUTS (outf, dregs (dst0));
3768 OUTS (outf, " = ");
3769 OUTS (outf, dregs (src0));
3770 OUTS (outf, " - ");
3771 OUTS (outf, dregs (src1));
3772 amod1 (s, x, outf);
3773 }
3774 else if (aop == 0 && aopcde == 17)
3775 {
3776 OUTS (outf, dregs (dst1));
3777 OUTS (outf, " = A1 + A0, ");
3778 OUTS (outf, dregs (dst0));
3779 OUTS (outf, " = A1 - A0");
3780 amod1 (s, x, outf);
3781 }
3782 else if (aop == 1 && aopcde == 17)
3783 {
3784 OUTS (outf, dregs (dst1));
3785 OUTS (outf, " = A0 + A1, ");
3786 OUTS (outf, dregs (dst0));
3787 OUTS (outf, " = A0 - A1");
3788 amod1 (s, x, outf);
3789 }
3790 else if (aop == 0 && aopcde == 18)
3791 {
3792 OUTS (outf, "SAA (");
3793 OUTS (outf, dregs (src0 + 1));
3794 OUTS (outf, ":");
3795 OUTS (outf, imm5d (src0));
3796 OUTS (outf, ", ");
3797 OUTS (outf, dregs (src1 + 1));
3798 OUTS (outf, ":");
3799 OUTS (outf, imm5d (src1));
3800 OUTS (outf, ")");
3801 aligndir (s, outf);
3802 }
3803 else if (aop == 3 && aopcde == 18)
3804 OUTS (outf, "DISALGNEXCPT");
3805
3806 else if (aop == 0 && aopcde == 20)
3807 {
3808 OUTS (outf, dregs (dst0));
3809 OUTS (outf, " = BYTEOP1P (");
3810 OUTS (outf, dregs (src0 + 1));
3811 OUTS (outf, ":");
3812 OUTS (outf, imm5d (src0));
3813 OUTS (outf, ", ");
3814 OUTS (outf, dregs (src1 + 1));
3815 OUTS (outf, ":");
3816 OUTS (outf, imm5d (src1));
3817 OUTS (outf, ")");
3818 aligndir (s, outf);
3819 }
3820 else if (aop == 1 && aopcde == 20)
3821 {
3822 OUTS (outf, dregs (dst0));
3823 OUTS (outf, " = BYTEOP1P (");
3824 OUTS (outf, dregs (src0 + 1));
3825 OUTS (outf, ":");
3826 OUTS (outf, imm5d (src0));
3827 OUTS (outf, ", ");
3828 OUTS (outf, dregs (src1 + 1));
3829 OUTS (outf, ":");
3830 OUTS (outf, imm5d (src1));
3831 OUTS (outf, ") (T");
3832 if (s == 1)
3833 OUTS (outf, ", R)");
3834 else
3835 OUTS (outf, ")");
3836 }
3837 else if (aop == 0 && aopcde == 21)
3838 {
3839 OUTS (outf, "(");
3840 OUTS (outf, dregs (dst1));
3841 OUTS (outf, ", ");
3842 OUTS (outf, dregs (dst0));
3843 OUTS (outf, ") = BYTEOP16P (");
3844 OUTS (outf, dregs (src0 + 1));
3845 OUTS (outf, ":");
3846 OUTS (outf, imm5d (src0));
3847 OUTS (outf, ", ");
3848 OUTS (outf, dregs (src1 + 1));
3849 OUTS (outf, ":");
3850 OUTS (outf, imm5d (src1));
3851 OUTS (outf, ")");
3852 aligndir (s, outf);
3853 }
3854 else if (aop == 1 && aopcde == 21)
3855 {
3856 OUTS (outf, "(");
3857 OUTS (outf, dregs (dst1));
3858 OUTS (outf, ", ");
3859 OUTS (outf, dregs (dst0));
3860 OUTS (outf, ") = BYTEOP16M (");
3861 OUTS (outf, dregs (src0 + 1));
3862 OUTS (outf, ":");
3863 OUTS (outf, imm5d (src0));
3864 OUTS (outf, ", ");
3865 OUTS (outf, dregs (src1 + 1));
3866 OUTS (outf, ":");
3867 OUTS (outf, imm5d (src1));
3868 OUTS (outf, ")");
3869 aligndir (s, outf);
3870 }
3871 else if (aop == 2 && aopcde == 7)
3872 {
3873 OUTS (outf, dregs (dst0));
3874 OUTS (outf, " = ABS ");
3875 OUTS (outf, dregs (src0));
3876 }
3877 else if (aop == 1 && aopcde == 7)
3878 {
3879 OUTS (outf, dregs (dst0));
3880 OUTS (outf, " = MIN (");
3881 OUTS (outf, dregs (src0));
3882 OUTS (outf, ", ");
3883 OUTS (outf, dregs (src1));
3884 OUTS (outf, ")");
3885 }
3886 else if (aop == 0 && aopcde == 7)
3887 {
3888 OUTS (outf, dregs (dst0));
3889 OUTS (outf, " = MAX (");
3890 OUTS (outf, dregs (src0));
3891 OUTS (outf, ", ");
3892 OUTS (outf, dregs (src1));
3893 OUTS (outf, ")");
3894 }
3895 else if (aop == 2 && aopcde == 6)
3896 {
3897 OUTS (outf, dregs (dst0));
3898 OUTS (outf, " = ABS ");
3899 OUTS (outf, dregs (src0));
3900 OUTS (outf, " (V)");
3901 }
3902 else if (aop == 1 && aopcde == 6)
3903 {
3904 OUTS (outf, dregs (dst0));
3905 OUTS (outf, " = MIN (");
3906 OUTS (outf, dregs (src0));
3907 OUTS (outf, ", ");
3908 OUTS (outf, dregs (src1));
3909 OUTS (outf, ") (V)");
3910 }
3911 else if (aop == 0 && aopcde == 6)
3912 {
3913 OUTS (outf, dregs (dst0));
3914 OUTS (outf, " = MAX (");
3915 OUTS (outf, dregs (src0));
3916 OUTS (outf, ", ");
3917 OUTS (outf, dregs (src1));
3918 OUTS (outf, ") (V)");
3919 }
3920 else if (HL == 1 && aopcde == 1)
3921 {
3922 OUTS (outf, dregs (dst1));
3923 OUTS (outf, " = ");
3924 OUTS (outf, dregs (src0));
3925 OUTS (outf, " +|- ");
3926 OUTS (outf, dregs (src1));
3927 OUTS (outf, ", ");
3928 OUTS (outf, dregs (dst0));
3929 OUTS (outf, " = ");
3930 OUTS (outf, dregs (src0));
3931 OUTS (outf, " -|+ ");
3932 OUTS (outf, dregs (src1));
3933 amod0amod2 (s, x, aop, outf);
3934 }
3935 else if (aop == 0 && aopcde == 4)
3936 {
3937 OUTS (outf, dregs (dst0));
3938 OUTS (outf, " = ");
3939 OUTS (outf, dregs (src0));
3940 OUTS (outf, " + ");
3941 OUTS (outf, dregs (src1));
3942 amod1 (s, x, outf);
3943 }
3944 else if (aop == 0 && aopcde == 0)
3945 {
3946 OUTS (outf, dregs (dst0));
3947 OUTS (outf, " = ");
3948 OUTS (outf, dregs (src0));
3949 OUTS (outf, " +|+ ");
3950 OUTS (outf, dregs (src1));
3951 amod0 (s, x, outf);
3952 }
3953 else if (aop == 0 && aopcde == 24)
3954 {
3955 OUTS (outf, dregs (dst0));
3956 OUTS (outf, " = BYTEPACK (");
3957 OUTS (outf, dregs (src0));
3958 OUTS (outf, ", ");
3959 OUTS (outf, dregs (src1));
3960 OUTS (outf, ")");
3961 }
3962 else if (aop == 1 && aopcde == 24)
3963 {
3964 OUTS (outf, "(");
3965 OUTS (outf, dregs (dst1));
3966 OUTS (outf, ", ");
3967 OUTS (outf, dregs (dst0));
3968 OUTS (outf, ") = BYTEUNPACK ");
3969 OUTS (outf, dregs (src0 + 1));
3970 OUTS (outf, ":");
3971 OUTS (outf, imm5d (src0));
3972 aligndir (s, outf);
3973 }
3974 else if (aopcde == 13)
3975 {
3976 OUTS (outf, "(");
3977 OUTS (outf, dregs (dst1));
3978 OUTS (outf, ", ");
3979 OUTS (outf, dregs (dst0));
3980 OUTS (outf, ") = SEARCH ");
3981 OUTS (outf, dregs (src0));
3982 OUTS (outf, " (");
3983 searchmod (aop, outf);
3984 OUTS (outf, ")");
3985 }
3986 else
3987 return 0;
3988
3989 return 4;
3990 }
3991
3992 static int
3993 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3994 {
3995 /* dsp32shift
3996 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3997 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3998 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3999 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4000 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
4001 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
4002 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
4003 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
4004 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
4005 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
4006 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
4007
4008 if (HLs == 0 && sop == 0 && sopcde == 0)
4009 {
4010 OUTS (outf, dregs_lo (dst0));
4011 OUTS (outf, " = ASHIFT ");
4012 OUTS (outf, dregs_lo (src1));
4013 OUTS (outf, " BY ");
4014 OUTS (outf, dregs_lo (src0));
4015 }
4016 else if (HLs == 1 && sop == 0 && sopcde == 0)
4017 {
4018 OUTS (outf, dregs_lo (dst0));
4019 OUTS (outf, " = ASHIFT ");
4020 OUTS (outf, dregs_hi (src1));
4021 OUTS (outf, " BY ");
4022 OUTS (outf, dregs_lo (src0));
4023 }
4024 else if (HLs == 2 && sop == 0 && sopcde == 0)
4025 {
4026 OUTS (outf, dregs_hi (dst0));
4027 OUTS (outf, " = ASHIFT ");
4028 OUTS (outf, dregs_lo (src1));
4029 OUTS (outf, " BY ");
4030 OUTS (outf, dregs_lo (src0));
4031 }
4032 else if (HLs == 3 && sop == 0 && sopcde == 0)
4033 {
4034 OUTS (outf, dregs_hi (dst0));
4035 OUTS (outf, " = ASHIFT ");
4036 OUTS (outf, dregs_hi (src1));
4037 OUTS (outf, " BY ");
4038 OUTS (outf, dregs_lo (src0));
4039 }
4040 else if (HLs == 0 && sop == 1 && sopcde == 0)
4041 {
4042 OUTS (outf, dregs_lo (dst0));
4043 OUTS (outf, " = ASHIFT ");
4044 OUTS (outf, dregs_lo (src1));
4045 OUTS (outf, " BY ");
4046 OUTS (outf, dregs_lo (src0));
4047 OUTS (outf, " (S)");
4048 }
4049 else if (HLs == 1 && sop == 1 && sopcde == 0)
4050 {
4051 OUTS (outf, dregs_lo (dst0));
4052 OUTS (outf, " = ASHIFT ");
4053 OUTS (outf, dregs_hi (src1));
4054 OUTS (outf, " BY ");
4055 OUTS (outf, dregs_lo (src0));
4056 OUTS (outf, " (S)");
4057 }
4058 else if (HLs == 2 && sop == 1 && sopcde == 0)
4059 {
4060 OUTS (outf, dregs_hi (dst0));
4061 OUTS (outf, " = ASHIFT ");
4062 OUTS (outf, dregs_lo (src1));
4063 OUTS (outf, " BY ");
4064 OUTS (outf, dregs_lo (src0));
4065 OUTS (outf, " (S)");
4066 }
4067 else if (HLs == 3 && sop == 1 && sopcde == 0)
4068 {
4069 OUTS (outf, dregs_hi (dst0));
4070 OUTS (outf, " = ASHIFT ");
4071 OUTS (outf, dregs_hi (src1));
4072 OUTS (outf, " BY ");
4073 OUTS (outf, dregs_lo (src0));
4074 OUTS (outf, " (S)");
4075 }
4076 else if (sop == 2 && sopcde == 0)
4077 {
4078 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
4079 OUTS (outf, " = LSHIFT ");
4080 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
4081 OUTS (outf, " BY ");
4082 OUTS (outf, dregs_lo (src0));
4083 }
4084 else if (sop == 0 && sopcde == 3)
4085 {
4086 OUTS (outf, acc01);
4087 OUTS (outf, " = ASHIFT ");
4088 OUTS (outf, acc01);
4089 OUTS (outf, " BY ");
4090 OUTS (outf, dregs_lo (src0));
4091 }
4092 else if (sop == 1 && sopcde == 3)
4093 {
4094 OUTS (outf, acc01);
4095 OUTS (outf, " = LSHIFT ");
4096 OUTS (outf, acc01);
4097 OUTS (outf, " BY ");
4098 OUTS (outf, dregs_lo (src0));
4099 }
4100 else if (sop == 2 && sopcde == 3)
4101 {
4102 OUTS (outf, acc01);
4103 OUTS (outf, " = ROT ");
4104 OUTS (outf, acc01);
4105 OUTS (outf, " BY ");
4106 OUTS (outf, dregs_lo (src0));
4107 }
4108 else if (sop == 3 && sopcde == 3)
4109 {
4110 OUTS (outf, dregs (dst0));
4111 OUTS (outf, " = ROT ");
4112 OUTS (outf, dregs (src1));
4113 OUTS (outf, " BY ");
4114 OUTS (outf, dregs_lo (src0));
4115 }
4116 else if (sop == 1 && sopcde == 1)
4117 {
4118 OUTS (outf, dregs (dst0));
4119 OUTS (outf, " = ASHIFT ");
4120 OUTS (outf, dregs (src1));
4121 OUTS (outf, " BY ");
4122 OUTS (outf, dregs_lo (src0));
4123 OUTS (outf, " (V, S)");
4124 }
4125 else if (sop == 0 && sopcde == 1)
4126 {
4127 OUTS (outf, dregs (dst0));
4128 OUTS (outf, " = ASHIFT ");
4129 OUTS (outf, dregs (src1));
4130 OUTS (outf, " BY ");
4131 OUTS (outf, dregs_lo (src0));
4132 OUTS (outf, " (V)");
4133 }
4134 else if (sop == 0 && sopcde == 2)
4135 {
4136 OUTS (outf, dregs (dst0));
4137 OUTS (outf, " = ASHIFT ");
4138 OUTS (outf, dregs (src1));
4139 OUTS (outf, " BY ");
4140 OUTS (outf, dregs_lo (src0));
4141 }
4142 else if (sop == 1 && sopcde == 2)
4143 {
4144 OUTS (outf, dregs (dst0));
4145 OUTS (outf, " = ASHIFT ");
4146 OUTS (outf, dregs (src1));
4147 OUTS (outf, " BY ");
4148 OUTS (outf, dregs_lo (src0));
4149 OUTS (outf, " (S)");
4150 }
4151 else if (sop == 2 && sopcde == 2)
4152 {
4153 OUTS (outf, dregs (dst0));
4154 OUTS (outf, " = LSHIFT ");
4155 OUTS (outf, dregs (src1));
4156 OUTS (outf, " BY ");
4157 OUTS (outf, dregs_lo (src0));
4158 }
4159 else if (sop == 3 && sopcde == 2)
4160 {
4161 OUTS (outf, dregs (dst0));
4162 OUTS (outf, " = ROT ");
4163 OUTS (outf, dregs (src1));
4164 OUTS (outf, " BY ");
4165 OUTS (outf, dregs_lo (src0));
4166 }
4167 else if (sop == 2 && sopcde == 1)
4168 {
4169 OUTS (outf, dregs (dst0));
4170 OUTS (outf, " = LSHIFT ");
4171 OUTS (outf, dregs (src1));
4172 OUTS (outf, " BY ");
4173 OUTS (outf, dregs_lo (src0));
4174 OUTS (outf, " (V)");
4175 }
4176 else if (sop == 0 && sopcde == 4)
4177 {
4178 OUTS (outf, dregs (dst0));
4179 OUTS (outf, " = PACK (");
4180 OUTS (outf, dregs_lo (src1));
4181 OUTS (outf, ", ");
4182 OUTS (outf, dregs_lo (src0));
4183 OUTS (outf, ")");
4184 }
4185 else if (sop == 1 && sopcde == 4)
4186 {
4187 OUTS (outf, dregs (dst0));
4188 OUTS (outf, " = PACK (");
4189 OUTS (outf, dregs_lo (src1));
4190 OUTS (outf, ", ");
4191 OUTS (outf, dregs_hi (src0));
4192 OUTS (outf, ")");
4193 }
4194 else if (sop == 2 && sopcde == 4)
4195 {
4196 OUTS (outf, dregs (dst0));
4197 OUTS (outf, " = PACK (");
4198 OUTS (outf, dregs_hi (src1));
4199 OUTS (outf, ", ");
4200 OUTS (outf, dregs_lo (src0));
4201 OUTS (outf, ")");
4202 }
4203 else if (sop == 3 && sopcde == 4)
4204 {
4205 OUTS (outf, dregs (dst0));
4206 OUTS (outf, " = PACK (");
4207 OUTS (outf, dregs_hi (src1));
4208 OUTS (outf, ", ");
4209 OUTS (outf, dregs_hi (src0));
4210 OUTS (outf, ")");
4211 }
4212 else if (sop == 0 && sopcde == 5)
4213 {
4214 OUTS (outf, dregs_lo (dst0));
4215 OUTS (outf, " = SIGNBITS ");
4216 OUTS (outf, dregs (src1));
4217 }
4218 else if (sop == 1 && sopcde == 5)
4219 {
4220 OUTS (outf, dregs_lo (dst0));
4221 OUTS (outf, " = SIGNBITS ");
4222 OUTS (outf, dregs_lo (src1));
4223 }
4224 else if (sop == 2 && sopcde == 5)
4225 {
4226 OUTS (outf, dregs_lo (dst0));
4227 OUTS (outf, " = SIGNBITS ");
4228 OUTS (outf, dregs_hi (src1));
4229 }
4230 else if (sop == 0 && sopcde == 6)
4231 {
4232 OUTS (outf, dregs_lo (dst0));
4233 OUTS (outf, " = SIGNBITS A0");
4234 }
4235 else if (sop == 1 && sopcde == 6)
4236 {
4237 OUTS (outf, dregs_lo (dst0));
4238 OUTS (outf, " = SIGNBITS A1");
4239 }
4240 else if (sop == 3 && sopcde == 6)
4241 {
4242 OUTS (outf, dregs_lo (dst0));
4243 OUTS (outf, " = ONES ");
4244 OUTS (outf, dregs (src1));
4245 }
4246 else if (sop == 0 && sopcde == 7)
4247 {
4248 OUTS (outf, dregs_lo (dst0));
4249 OUTS (outf, " = EXPADJ (");
4250 OUTS (outf, dregs (src1));
4251 OUTS (outf, ", ");
4252 OUTS (outf, dregs_lo (src0));
4253 OUTS (outf, ")");
4254 }
4255 else if (sop == 1 && sopcde == 7)
4256 {
4257 OUTS (outf, dregs_lo (dst0));
4258 OUTS (outf, " = EXPADJ (");
4259 OUTS (outf, dregs (src1));
4260 OUTS (outf, ", ");
4261 OUTS (outf, dregs_lo (src0));
4262 OUTS (outf, ") (V)");
4263 }
4264 else if (sop == 2 && sopcde == 7)
4265 {
4266 OUTS (outf, dregs_lo (dst0));
4267 OUTS (outf, " = EXPADJ (");
4268 OUTS (outf, dregs_lo (src1));
4269 OUTS (outf, ", ");
4270 OUTS (outf, dregs_lo (src0));
4271 OUTS (outf, ")");
4272 }
4273 else if (sop == 3 && sopcde == 7)
4274 {
4275 OUTS (outf, dregs_lo (dst0));
4276 OUTS (outf, " = EXPADJ (");
4277 OUTS (outf, dregs_hi (src1));
4278 OUTS (outf, ", ");
4279 OUTS (outf, dregs_lo (src0));
4280 OUTS (outf, ")");
4281 }
4282 else if (sop == 0 && sopcde == 8)
4283 {
4284 OUTS (outf, "BITMUX (");
4285 OUTS (outf, dregs (src0));
4286 OUTS (outf, ", ");
4287 OUTS (outf, dregs (src1));
4288 OUTS (outf, ", A0) (ASR)");
4289 }
4290 else if (sop == 1 && sopcde == 8)
4291 {
4292 OUTS (outf, "BITMUX (");
4293 OUTS (outf, dregs (src0));
4294 OUTS (outf, ", ");
4295 OUTS (outf, dregs (src1));
4296 OUTS (outf, ", A0) (ASL)");
4297 }
4298 else if (sop == 0 && sopcde == 9)
4299 {
4300 OUTS (outf, dregs_lo (dst0));
4301 OUTS (outf, " = VIT_MAX (");
4302 OUTS (outf, dregs (src1));
4303 OUTS (outf, ") (ASL)");
4304 }
4305 else if (sop == 1 && sopcde == 9)
4306 {
4307 OUTS (outf, dregs_lo (dst0));
4308 OUTS (outf, " = VIT_MAX (");
4309 OUTS (outf, dregs (src1));
4310 OUTS (outf, ") (ASR)");
4311 }
4312 else if (sop == 2 && sopcde == 9)
4313 {
4314 OUTS (outf, dregs (dst0));
4315 OUTS (outf, " = VIT_MAX (");
4316 OUTS (outf, dregs (src1));
4317 OUTS (outf, ", ");
4318 OUTS (outf, dregs (src0));
4319 OUTS (outf, ") (ASL)");
4320 }
4321 else if (sop == 3 && sopcde == 9)
4322 {
4323 OUTS (outf, dregs (dst0));
4324 OUTS (outf, " = VIT_MAX (");
4325 OUTS (outf, dregs (src1));
4326 OUTS (outf, ", ");
4327 OUTS (outf, dregs (src0));
4328 OUTS (outf, ") (ASR)");
4329 }
4330 else if (sop == 0 && sopcde == 10)
4331 {
4332 OUTS (outf, dregs (dst0));
4333 OUTS (outf, " = EXTRACT (");
4334 OUTS (outf, dregs (src1));
4335 OUTS (outf, ", ");
4336 OUTS (outf, dregs_lo (src0));
4337 OUTS (outf, ") (Z)");
4338 }
4339 else if (sop == 1 && sopcde == 10)
4340 {
4341 OUTS (outf, dregs (dst0));
4342 OUTS (outf, " = EXTRACT (");
4343 OUTS (outf, dregs (src1));
4344 OUTS (outf, ", ");
4345 OUTS (outf, dregs_lo (src0));
4346 OUTS (outf, ") (X)");
4347 }
4348 else if (sop == 2 && sopcde == 10)
4349 {
4350 OUTS (outf, dregs (dst0));
4351 OUTS (outf, " = DEPOSIT (");
4352 OUTS (outf, dregs (src1));
4353 OUTS (outf, ", ");
4354 OUTS (outf, dregs (src0));
4355 OUTS (outf, ")");
4356 }
4357 else if (sop == 3 && sopcde == 10)
4358 {
4359 OUTS (outf, dregs (dst0));
4360 OUTS (outf, " = DEPOSIT (");
4361 OUTS (outf, dregs (src1));
4362 OUTS (outf, ", ");
4363 OUTS (outf, dregs (src0));
4364 OUTS (outf, ") (X)");
4365 }
4366 else if (sop == 0 && sopcde == 11)
4367 {
4368 OUTS (outf, dregs_lo (dst0));
4369 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4370 OUTS (outf, dregs (src0));
4371 OUTS (outf, ")");
4372 }
4373 else if (sop == 1 && sopcde == 11)
4374 {
4375 OUTS (outf, dregs_lo (dst0));
4376 OUTS (outf, " = CC = BXOR (A0, ");
4377 OUTS (outf, dregs (src0));
4378 OUTS (outf, ")");
4379 }
4380 else if (sop == 0 && sopcde == 12)
4381 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4382
4383 else if (sop == 1 && sopcde == 12)
4384 {
4385 OUTS (outf, dregs_lo (dst0));
4386 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4387 }
4388 else if (sop == 0 && sopcde == 13)
4389 {
4390 OUTS (outf, dregs (dst0));
4391 OUTS (outf, " = ALIGN8 (");
4392 OUTS (outf, dregs (src1));
4393 OUTS (outf, ", ");
4394 OUTS (outf, dregs (src0));
4395 OUTS (outf, ")");
4396 }
4397 else if (sop == 1 && sopcde == 13)
4398 {
4399 OUTS (outf, dregs (dst0));
4400 OUTS (outf, " = ALIGN16 (");
4401 OUTS (outf, dregs (src1));
4402 OUTS (outf, ", ");
4403 OUTS (outf, dregs (src0));
4404 OUTS (outf, ")");
4405 }
4406 else if (sop == 2 && sopcde == 13)
4407 {
4408 OUTS (outf, dregs (dst0));
4409 OUTS (outf, " = ALIGN24 (");
4410 OUTS (outf, dregs (src1));
4411 OUTS (outf, ", ");
4412 OUTS (outf, dregs (src0));
4413 OUTS (outf, ")");
4414 }
4415 else
4416 return 0;
4417
4418 return 4;
4419 }
4420
4421 static int
4422 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4423 {
4424 /* dsp32shiftimm
4425 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4426 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4427 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4428 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4429 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4430 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4431 int bit8 = ((iw1 >> 8) & 0x1);
4432 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4433 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4434 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4435 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4436 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4437
4438
4439 if (sop == 0 && sopcde == 0)
4440 {
4441 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4442 OUTS (outf, " = ");
4443 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4444 OUTS (outf, " >>> ");
4445 OUTS (outf, uimm4 (newimmag));
4446 }
4447 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4448 {
4449 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4450 OUTS (outf, " = ");
4451 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4452 OUTS (outf, " << ");
4453 OUTS (outf, uimm4 (immag));
4454 OUTS (outf, " (S)");
4455 }
4456 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4457 {
4458 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4459 OUTS (outf, " = ");
4460 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4461 OUTS (outf, " >>> ");
4462 OUTS (outf, uimm4 (newimmag));
4463 OUTS (outf, " (S)");
4464 }
4465 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4466 {
4467 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4468 OUTS (outf, " = ");
4469 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4470 OUTS (outf, " << ");
4471 OUTS (outf, uimm4 (immag));
4472 }
4473 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4474 {
4475 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4476 OUTS (outf, " = ");
4477 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4478 OUTS (outf, " >> ");
4479 OUTS (outf, uimm4 (newimmag));
4480 }
4481 else if (sop == 2 && sopcde == 3 && HLs == 1)
4482 {
4483 OUTS (outf, "A1 = ROT A1 BY ");
4484 OUTS (outf, imm6 (immag));
4485 }
4486 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4487 {
4488 OUTS (outf, "A0 = A0 << ");
4489 OUTS (outf, uimm5 (immag));
4490 }
4491 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4492 {
4493 OUTS (outf, "A0 = A0 >>> ");
4494 OUTS (outf, uimm5 (newimmag));
4495 }
4496 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4497 {
4498 OUTS (outf, "A1 = A1 << ");
4499 OUTS (outf, uimm5 (immag));
4500 }
4501 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4502 {
4503 OUTS (outf, "A1 = A1 >>> ");
4504 OUTS (outf, uimm5 (newimmag));
4505 }
4506 else if (sop == 1 && sopcde == 3 && HLs == 0)
4507 {
4508 OUTS (outf, "A0 = A0 >> ");
4509 OUTS (outf, uimm5 (newimmag));
4510 }
4511 else if (sop == 1 && sopcde == 3 && HLs == 1)
4512 {
4513 OUTS (outf, "A1 = A1 >> ");
4514 OUTS (outf, uimm5 (newimmag));
4515 }
4516 else if (sop == 2 && sopcde == 3 && HLs == 0)
4517 {
4518 OUTS (outf, "A0 = ROT A0 BY ");
4519 OUTS (outf, imm6 (immag));
4520 }
4521 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4522 {
4523 OUTS (outf, dregs (dst0));
4524 OUTS (outf, " = ");
4525 OUTS (outf, dregs (src1));
4526 OUTS (outf, " << ");
4527 OUTS (outf, uimm5 (immag));
4528 OUTS (outf, " (V, S)");
4529 }
4530 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4531 {
4532 OUTS (outf, dregs (dst0));
4533 OUTS (outf, " = ");
4534 OUTS (outf, dregs (src1));
4535 OUTS (outf, " >>> ");
4536 OUTS (outf, imm5 (-immag));
4537 OUTS (outf, " (V, S)");
4538 }
4539 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4540 {
4541 OUTS (outf, dregs (dst0));
4542 OUTS (outf, " = ");
4543 OUTS (outf, dregs (src1));
4544 OUTS (outf, " >> ");
4545 OUTS (outf, uimm5 (newimmag));
4546 OUTS (outf, " (V)");
4547 }
4548 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4549 {
4550 OUTS (outf, dregs (dst0));
4551 OUTS (outf, " = ");
4552 OUTS (outf, dregs (src1));
4553 OUTS (outf, " << ");
4554 OUTS (outf, imm5 (immag));
4555 OUTS (outf, " (V)");
4556 }
4557 else if (sop == 0 && sopcde == 1)
4558 {
4559 OUTS (outf, dregs (dst0));
4560 OUTS (outf, " = ");
4561 OUTS (outf, dregs (src1));
4562 OUTS (outf, " >>> ");
4563 OUTS (outf, uimm5 (newimmag));
4564 OUTS (outf, " (V)");
4565 }
4566 else if (sop == 1 && sopcde == 2)
4567 {
4568 OUTS (outf, dregs (dst0));
4569 OUTS (outf, " = ");
4570 OUTS (outf, dregs (src1));
4571 OUTS (outf, " << ");
4572 OUTS (outf, uimm5 (immag));
4573 OUTS (outf, " (S)");
4574 }
4575 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4576 {
4577 OUTS (outf, dregs (dst0));
4578 OUTS (outf, " = ");
4579 OUTS (outf, dregs (src1));
4580 OUTS (outf, " >> ");
4581 OUTS (outf, uimm5 (newimmag));
4582 }
4583 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4584 {
4585 OUTS (outf, dregs (dst0));
4586 OUTS (outf, " = ");
4587 OUTS (outf, dregs (src1));
4588 OUTS (outf, " << ");
4589 OUTS (outf, uimm5 (immag));
4590 }
4591 else if (sop == 3 && sopcde == 2)
4592 {
4593 OUTS (outf, dregs (dst0));
4594 OUTS (outf, " = ROT ");
4595 OUTS (outf, dregs (src1));
4596 OUTS (outf, " BY ");
4597 OUTS (outf, imm6 (immag));
4598 }
4599 else if (sop == 0 && sopcde == 2)
4600 {
4601 OUTS (outf, dregs (dst0));
4602 OUTS (outf, " = ");
4603 OUTS (outf, dregs (src1));
4604 OUTS (outf, " >>> ");
4605 OUTS (outf, uimm5 (newimmag));
4606 }
4607 else
4608 return 0;
4609
4610 return 4;
4611 }
4612
4613 static int
4614 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4615 {
4616 /* pseudoDEBUG
4617 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4618 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4619 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4620 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4621 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4622 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4623
4624 if (parallel)
4625 return 0;
4626
4627 if (reg == 0 && fn == 3)
4628 OUTS (outf, "DBG A0");
4629
4630 else if (reg == 1 && fn == 3)
4631 OUTS (outf, "DBG A1");
4632
4633 else if (reg == 3 && fn == 3)
4634 OUTS (outf, "ABORT");
4635
4636 else if (reg == 4 && fn == 3)
4637 OUTS (outf, "HLT");
4638
4639 else if (reg == 5 && fn == 3)
4640 OUTS (outf, "DBGHALT");
4641
4642 else if (reg == 6 && fn == 3)
4643 {
4644 OUTS (outf, "DBGCMPLX (");
4645 OUTS (outf, dregs (grp));
4646 OUTS (outf, ")");
4647 }
4648 else if (reg == 7 && fn == 3)
4649 OUTS (outf, "DBG");
4650
4651 else if (grp == 0 && fn == 2)
4652 {
4653 OUTS (outf, "OUTC ");
4654 OUTS (outf, dregs (reg));
4655 }
4656 else if (fn == 0)
4657 {
4658 OUTS (outf, "DBG ");
4659 OUTS (outf, allregs (reg, grp));
4660 }
4661 else if (fn == 1)
4662 {
4663 OUTS (outf, "PRNT");
4664 OUTS (outf, allregs (reg, grp));
4665 }
4666 else
4667 return 0;
4668
4669 return 2;
4670 }
4671
4672 static int
4673 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4674 {
4675 /* psedoOChar
4676 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4677 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4678 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4679 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4680
4681 if (parallel)
4682 return 0;
4683
4684 OUTS (outf, "OUTC ");
4685 OUTS (outf, uimm8 (ch));
4686
4687 return 2;
4688 }
4689
4690 static int
4691 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4692 {
4693 /* pseudodbg_assert
4694 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4695 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4696 |.expected......................................................|
4697 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4698 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4699 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4700 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4701 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4702
4703 if (parallel)
4704 return 0;
4705
4706 if (dbgop == 0)
4707 {
4708 OUTS (outf, "DBGA (");
4709 OUTS (outf, regs_lo (regtest, grp));
4710 OUTS (outf, ", ");
4711 OUTS (outf, uimm16 (expected));
4712 OUTS (outf, ")");
4713 }
4714 else if (dbgop == 1)
4715 {
4716 OUTS (outf, "DBGA (");
4717 OUTS (outf, regs_hi (regtest, grp));
4718 OUTS (outf, ", ");
4719 OUTS (outf, uimm16 (expected));
4720 OUTS (outf, ")");
4721 }
4722 else if (dbgop == 2)
4723 {
4724 OUTS (outf, "DBGAL (");
4725 OUTS (outf, allregs (regtest, grp));
4726 OUTS (outf, ", ");
4727 OUTS (outf, uimm16 (expected));
4728 OUTS (outf, ")");
4729 }
4730 else if (dbgop == 3)
4731 {
4732 OUTS (outf, "DBGAH (");
4733 OUTS (outf, allregs (regtest, grp));
4734 OUTS (outf, ", ");
4735 OUTS (outf, uimm16 (expected));
4736 OUTS (outf, ")");
4737 }
4738 else
4739 return 0;
4740 return 4;
4741 }
4742
4743 static int
4744 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4745 {
4746 bfd_byte buf[4];
4747 TIword iw0;
4748 TIword iw1;
4749 int status;
4750 int rv = 0;
4751
4752 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4753 /* FIXME */
4754 (void) status;
4755 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4756 /* FIXME */
4757 (void) status;
4758
4759 iw0 = bfd_getl16 (buf);
4760 iw1 = bfd_getl16 (buf + 2);
4761
4762 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4763 {
4764 if (parallel)
4765 {
4766 OUTS (outf, "ILLEGAL");
4767 return 0;
4768 }
4769 OUTS (outf, "MNOP");
4770 return 4;
4771 }
4772 else if ((iw0 & 0xff00) == 0x0000)
4773 rv = decode_ProgCtrl_0 (iw0, outf);
4774 else if ((iw0 & 0xffc0) == 0x0240)
4775 rv = decode_CaCTRL_0 (iw0, outf);
4776 else if ((iw0 & 0xff80) == 0x0100)
4777 rv = decode_PushPopReg_0 (iw0, outf);
4778 else if ((iw0 & 0xfe00) == 0x0400)
4779 rv = decode_PushPopMultiple_0 (iw0, outf);
4780 else if ((iw0 & 0xfe00) == 0x0600)
4781 rv = decode_ccMV_0 (iw0, outf);
4782 else if ((iw0 & 0xf800) == 0x0800)
4783 rv = decode_CCflag_0 (iw0, outf);
4784 else if ((iw0 & 0xffe0) == 0x0200)
4785 rv = decode_CC2dreg_0 (iw0, outf);
4786 else if ((iw0 & 0xff00) == 0x0300)
4787 rv = decode_CC2stat_0 (iw0, outf);
4788 else if ((iw0 & 0xf000) == 0x1000)
4789 rv = decode_BRCC_0 (iw0, pc, outf);
4790 else if ((iw0 & 0xf000) == 0x2000)
4791 rv = decode_UJUMP_0 (iw0, pc, outf);
4792 else if ((iw0 & 0xf000) == 0x3000)
4793 rv = decode_REGMV_0 (iw0, outf);
4794 else if ((iw0 & 0xfc00) == 0x4000)
4795 rv = decode_ALU2op_0 (iw0, outf);
4796 else if ((iw0 & 0xfe00) == 0x4400)
4797 rv = decode_PTR2op_0 (iw0, outf);
4798 else if ((iw0 & 0xf800) == 0x4800)
4799 rv = decode_LOGI2op_0 (iw0, outf);
4800 else if ((iw0 & 0xf000) == 0x5000)
4801 rv = decode_COMP3op_0 (iw0, outf);
4802 else if ((iw0 & 0xf800) == 0x6000)
4803 rv = decode_COMPI2opD_0 (iw0, outf);
4804 else if ((iw0 & 0xf800) == 0x6800)
4805 rv = decode_COMPI2opP_0 (iw0, outf);
4806 else if ((iw0 & 0xf000) == 0x8000)
4807 rv = decode_LDSTpmod_0 (iw0, outf);
4808 else if ((iw0 & 0xff60) == 0x9e60)
4809 rv = decode_dagMODim_0 (iw0, outf);
4810 else if ((iw0 & 0xfff0) == 0x9f60)
4811 rv = decode_dagMODik_0 (iw0, outf);
4812 else if ((iw0 & 0xfc00) == 0x9c00)
4813 rv = decode_dspLDST_0 (iw0, outf);
4814 else if ((iw0 & 0xf000) == 0x9000)
4815 rv = decode_LDST_0 (iw0, outf);
4816 else if ((iw0 & 0xfc00) == 0xb800)
4817 rv = decode_LDSTiiFP_0 (iw0, outf);
4818 else if ((iw0 & 0xe000) == 0xA000)
4819 rv = decode_LDSTii_0 (iw0, outf);
4820 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4821 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4822 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4823 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4824 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4825 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4826 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4827 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4828 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4829 rv = decode_linkage_0 (iw0, iw1, outf);
4830 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4831 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4832 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4833 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4834 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4835 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4836 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4837 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4838 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4839 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4840 else if ((iw0 & 0xff00) == 0xf800)
4841 rv = decode_pseudoDEBUG_0 (iw0, outf);
4842 else if ((iw0 & 0xFF00) == 0xF900)
4843 rv = decode_pseudoOChar_0 (iw0, outf);
4844 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4845 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4846
4847 if (rv == 0)
4848 OUTS (outf, "ILLEGAL");
4849
4850 return rv;
4851 }
4852
4853
4854 int
4855 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4856 {
4857 bfd_byte buf[2];
4858 unsigned short iw0;
4859 int status;
4860 int count = 0;
4861
4862 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4863 /* FIXME */
4864 (void) status;
4865 iw0 = bfd_getl16 (buf);
4866
4867 count += _print_insn_bfin (pc, outf);
4868
4869 /* Proper display of multiple issue instructions. */
4870
4871 if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4872 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4873 {
4874 int legal = 1;
4875 int len;
4876
4877 parallel = 1;
4878 outf->fprintf_func (outf->stream, " || ");
4879 len = _print_insn_bfin (pc + 4, outf);
4880 outf->fprintf_func (outf->stream, " || ");
4881 if (len != 2)
4882 legal = 0;
4883 len = _print_insn_bfin (pc + 6, outf);
4884 if (len != 2)
4885 legal = 0;
4886
4887 if (legal)
4888 count = 8;
4889 else
4890 {
4891 outf->fprintf_func (outf->stream, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4892 comment = 1;
4893 count = 0;
4894 }
4895 parallel = 0;
4896 }
4897
4898 if (!comment)
4899 outf->fprintf_func (outf->stream, ";");
4900
4901 if (count == 0)
4902 return 2;
4903
4904 comment = 0;
4905
4906 return count;
4907 }
git-cvsimport of binutils cvsroot