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opcodes: blackfin: constify register names
[binutils.git] / opcodes / bfin-dis.c
blob58122f0815f0a65263065c8d63308ed85c4f3e2b
1 /* Disassemble ADI Blackfin Instructions.
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4
5 This file is part of libopcodes.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #include <stdio.h>
23 #include <stdlib.h>
24 #include <string.h>
25
26 #include "opcode/bfin.h"
27
28 #define M_S2RND 1
29 #define M_T 2
30 #define M_W32 3
31 #define M_FU 4
32 #define M_TFU 6
33 #define M_IS 8
34 #define M_ISS2 9
35 #define M_IH 11
36 #define M_IU 12
37
38 #ifndef PRINTF
39 #define PRINTF printf
40 #endif
41
42 #ifndef EXIT
43 #define EXIT exit
44 #endif
45
46 typedef long TIword;
47
48 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
49 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
50 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
51 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
52
53 #include "dis-asm.h"
54
55 typedef unsigned int bu32;
56
57 static char comment = 0;
58 static char parallel = 0;
59
60 typedef enum
61 {
62 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
63 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
64 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
65 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
66 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
67 } const_forms_t;
68
69 static const struct
70 {
71 const char *name;
72 const int nbits;
73 const char reloc;
74 const char issigned;
75 const char pcrel;
76 const char scale;
77 const char offset;
78 const char negative;
79 const char positive;
80 const char decimal;
81 const char leading;
82 const char exact;
83 } constant_formats[] =
84 {
85 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
86 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
88 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
89 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
91 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
92 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
93 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
94 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
95 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
96 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
97 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
98 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
99 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
100 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
101 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
102 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
103 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
104 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
105 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
107 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
108 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
109 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
110 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
111 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
112 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
113 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
114 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
116 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
117 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
118 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
119 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
120 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
121 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
122 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
123 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
124 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
125 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
126 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
127 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
128 };
129
130 static const char *
131 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
132 {
133 static char buf[60];
134
135 if (constant_formats[cf].reloc)
136 {
137 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
138 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
139 if (constant_formats[cf].pcrel)
140 ea += pc;
141
142 /* truncate to 32-bits for proper symbol lookup/matching */
143 ea = (bu32)ea;
144
145 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
146 {
147 outf->print_address_func (ea, outf);
148 return "";
149 }
150 else
151 {
152 sprintf (buf, "%lx", (unsigned long) x);
153 return buf;
154 }
155 }
156
157 /* Negative constants have an implied sign bit. */
158 if (constant_formats[cf].negative)
159 {
160 int nb = constant_formats[cf].nbits + 1;
161
162 x = x | (1 << constant_formats[cf].nbits);
163 x = SIGNEXTEND (x, nb);
164 }
165 else
166 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
167
168 if (constant_formats[cf].offset)
169 x += constant_formats[cf].offset;
170
171 if (constant_formats[cf].scale)
172 x <<= constant_formats[cf].scale;
173
174 if (constant_formats[cf].decimal)
175 {
176 if (constant_formats[cf].leading)
177 {
178 char ps[10];
179 sprintf (ps, "%%%ii", constant_formats[cf].leading);
180 sprintf (buf, ps, x);
181 }
182 else
183 sprintf (buf, "%li", x);
184 }
185 else
186 {
187 if (constant_formats[cf].issigned && x < 0)
188 sprintf (buf, "-0x%x", abs (x));
189 else
190 sprintf (buf, "0x%lx", (unsigned long) x);
191 }
192
193 return buf;
194 }
195
196 static bu32
197 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
198 {
199 if (0 && constant_formats[cf].reloc)
200 {
201 bu32 ea = (((constant_formats[cf].pcrel
202 ? SIGNEXTEND (x, constant_formats[cf].nbits)
203 : x) + constant_formats[cf].offset)
204 << constant_formats[cf].scale);
205 if (constant_formats[cf].pcrel)
206 ea += pc;
207
208 return ea;
209 }
210
211 /* Negative constants have an implied sign bit. */
212 if (constant_formats[cf].negative)
213 {
214 int nb = constant_formats[cf].nbits + 1;
215 x = x | (1 << constant_formats[cf].nbits);
216 x = SIGNEXTEND (x, nb);
217 }
218 else if (constant_formats[cf].issigned)
219 x = SIGNEXTEND (x, constant_formats[cf].nbits);
220
221 x += constant_formats[cf].offset;
222 x <<= constant_formats[cf].scale;
223
224 return x;
225 }
226
227 enum machine_registers
228 {
229 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
230 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
231 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
232 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
233 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
234 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
235 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
236 REG_L2, REG_L3,
237 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
238 REG_AQ, REG_V, REG_VS,
239 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
240 REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
241 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
242 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
243 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
244 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
245 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
246 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
247 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
248 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
249 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
250 REG_LASTREG,
251 };
252
253 enum reg_class
254 {
255 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
256 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
257 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
258 rc_sysregs3, rc_allregs,
259 LIM_REG_CLASSES
260 };
261
262 static const char * const reg_names[] =
263 {
264 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
265 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
266 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
267 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
268 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
269 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
270 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
271 "L2", "L3",
272 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
273 "AQ", "V", "VS",
274 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
275 "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
276 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
277 "RETE", "EMUDAT",
278 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
279 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
280 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
281 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
282 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
283 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
284 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
285 "AC0_COPY", "V_COPY", "RND_MOD",
286 "LASTREG",
287 0
288 };
289
290 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
291
292 /* RL(0..7). */
293 static const enum machine_registers decode_dregs_lo[] =
294 {
295 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
296 };
297
298 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
299
300 /* RH(0..7). */
301 static const enum machine_registers decode_dregs_hi[] =
302 {
303 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
304 };
305
306 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
307
308 /* R(0..7). */
309 static const enum machine_registers decode_dregs[] =
310 {
311 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
312 };
313
314 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
315
316 /* R BYTE(0..7). */
317 static const enum machine_registers decode_dregs_byte[] =
318 {
319 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
320 };
321
322 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
323
324 /* P(0..5) SP FP. */
325 static const enum machine_registers decode_pregs[] =
326 {
327 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
328 };
329
330 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
331 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
332 #define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
333 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
334 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
335 #define accum(x) REGNAME (decode_accum[(x) & 1])
336
337 /* I(0..3). */
338 static const enum machine_registers decode_iregs[] =
339 {
340 REG_I0, REG_I1, REG_I2, REG_I3,
341 };
342
343 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
344
345 /* M(0..3). */
346 static const enum machine_registers decode_mregs[] =
347 {
348 REG_M0, REG_M1, REG_M2, REG_M3,
349 };
350
351 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
352 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
353 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
354
355 /* dregs pregs. */
356 static const enum machine_registers decode_dpregs[] =
357 {
358 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
359 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
360 };
361
362 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
363
364 /* [dregs pregs]. */
365 static const enum machine_registers decode_gregs[] =
366 {
367 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
368 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
369 };
370
371 #define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
372
373 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
374 static const enum machine_registers decode_regs[] =
375 {
376 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
377 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
378 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
379 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
380 };
381
382 #define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
383
384 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
385 static const enum machine_registers decode_regs_lo[] =
386 {
387 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
388 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
389 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
390 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
391 };
392
393 #define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
394 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
395 static const enum machine_registers decode_regs_hi[] =
396 {
397 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
398 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
399 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
400 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
401 };
402
403 #define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
404
405 static const enum machine_registers decode_statbits[] =
406 {
407 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
408 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
409 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
410 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
411 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
412 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
413 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
414 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
415 };
416
417 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
418
419 /* LC0 LC1. */
420 static const enum machine_registers decode_counters[] =
421 {
422 REG_LC0, REG_LC1,
423 };
424
425 #define counters(x) REGNAME (decode_counters[(x) & 1])
426 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
427
428 /* [dregs pregs (iregs mregs) (bregs lregs)
429 dregs2_sysregs1 open sysregs2 sysregs3]. */
430 static const enum machine_registers decode_allregs[] =
431 {
432 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
433 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
434 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
435 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
436 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
437 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
438 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
439 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
440 REG_LASTREG,
441 };
442
443 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
444 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
445 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
446 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
447 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
448 #define IS_SYSREG(g,r) \
449 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
450 #define IS_RESERVEDREG(g,r) \
451 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
452
453 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
454 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
455
456 #define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
457 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
458 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
459 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
460 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
461 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
462 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
463 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
464 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
465 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
466 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
467 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
468 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
469 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
470 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
471 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
472 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
473 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
474 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
475 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
476 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
477 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
478 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
479 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
480 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
481 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
482 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
483 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
484 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
485 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
486 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
487 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
488 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
489 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
490 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
491 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
492 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
493 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
494 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
495 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
496 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
497 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
498 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
499
500 /* (arch.pm)arch_disassembler_functions. */
501 #ifndef OUTS
502 #define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
503 #endif
504
505 static void
506 amod0 (int s0, int x0, disassemble_info *outf)
507 {
508 if (s0 == 1 && x0 == 0)
509 OUTS (outf, " (S)");
510 else if (s0 == 0 && x0 == 1)
511 OUTS (outf, " (CO)");
512 else if (s0 == 1 && x0 == 1)
513 OUTS (outf, " (SCO)");
514 }
515
516 static void
517 amod1 (int s0, int x0, disassemble_info *outf)
518 {
519 if (s0 == 0 && x0 == 0)
520 OUTS (outf, " (NS)");
521 else if (s0 == 1 && x0 == 0)
522 OUTS (outf, " (S)");
523 }
524
525 static void
526 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
527 {
528 if (s0 == 1 && x0 == 0 && aop0 == 0)
529 OUTS (outf, " (S)");
530 else if (s0 == 0 && x0 == 1 && aop0 == 0)
531 OUTS (outf, " (CO)");
532 else if (s0 == 1 && x0 == 1 && aop0 == 0)
533 OUTS (outf, " (SCO)");
534 else if (s0 == 0 && x0 == 0 && aop0 == 2)
535 OUTS (outf, " (ASR)");
536 else if (s0 == 1 && x0 == 0 && aop0 == 2)
537 OUTS (outf, " (S, ASR)");
538 else if (s0 == 0 && x0 == 1 && aop0 == 2)
539 OUTS (outf, " (CO, ASR)");
540 else if (s0 == 1 && x0 == 1 && aop0 == 2)
541 OUTS (outf, " (SCO, ASR)");
542 else if (s0 == 0 && x0 == 0 && aop0 == 3)
543 OUTS (outf, " (ASL)");
544 else if (s0 == 1 && x0 == 0 && aop0 == 3)
545 OUTS (outf, " (S, ASL)");
546 else if (s0 == 0 && x0 == 1 && aop0 == 3)
547 OUTS (outf, " (CO, ASL)");
548 else if (s0 == 1 && x0 == 1 && aop0 == 3)
549 OUTS (outf, " (SCO, ASL)");
550 }
551
552 static void
553 searchmod (int r0, disassemble_info *outf)
554 {
555 if (r0 == 0)
556 OUTS (outf, "GT");
557 else if (r0 == 1)
558 OUTS (outf, "GE");
559 else if (r0 == 2)
560 OUTS (outf, "LT");
561 else if (r0 == 3)
562 OUTS (outf, "LE");
563 }
564
565 static void
566 aligndir (int r0, disassemble_info *outf)
567 {
568 if (r0 == 1)
569 OUTS (outf, " (R)");
570 }
571
572 static int
573 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
574 {
575 const char *s0, *s1;
576
577 if (h0)
578 s0 = dregs_hi (src0);
579 else
580 s0 = dregs_lo (src0);
581
582 if (h1)
583 s1 = dregs_hi (src1);
584 else
585 s1 = dregs_lo (src1);
586
587 OUTS (outf, s0);
588 OUTS (outf, " * ");
589 OUTS (outf, s1);
590 return 0;
591 }
592
593 static int
594 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
595 {
596 const char *a;
597 const char *sop = "<unknown op>";
598
599 if (which)
600 a = "A1";
601 else
602 a = "A0";
603
604 if (op == 3)
605 {
606 OUTS (outf, a);
607 return 0;
608 }
609
610 switch (op)
611 {
612 case 0: sop = " = "; break;
613 case 1: sop = " += "; break;
614 case 2: sop = " -= "; break;
615 default: break;
616 }
617
618 OUTS (outf, a);
619 OUTS (outf, sop);
620 decode_multfunc (h0, h1, src0, src1, outf);
621
622 return 0;
623 }
624
625 static void
626 decode_optmode (int mod, int MM, disassemble_info *outf)
627 {
628 if (mod == 0 && MM == 0)
629 return;
630
631 OUTS (outf, " (");
632
633 if (MM && !mod)
634 {
635 OUTS (outf, "M)");
636 return;
637 }
638
639 if (MM)
640 OUTS (outf, "M, ");
641
642 if (mod == M_S2RND)
643 OUTS (outf, "S2RND");
644 else if (mod == M_T)
645 OUTS (outf, "T");
646 else if (mod == M_W32)
647 OUTS (outf, "W32");
648 else if (mod == M_FU)
649 OUTS (outf, "FU");
650 else if (mod == M_TFU)
651 OUTS (outf, "TFU");
652 else if (mod == M_IS)
653 OUTS (outf, "IS");
654 else if (mod == M_ISS2)
655 OUTS (outf, "ISS2");
656 else if (mod == M_IH)
657 OUTS (outf, "IH");
658 else if (mod == M_IU)
659 OUTS (outf, "IU");
660 else
661 abort ();
662
663 OUTS (outf, ")");
664 }
665
666 struct saved_state
667 {
668 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
669 bu32 a0x, a0w, a1x, a1w;
670 bu32 lt[2], lc[2], lb[2];
671 int ac0, ac0_copy, ac1, an, aq;
672 int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
673 int rnd_mod;
674 int v_internal;
675 bu32 pc, rets;
676
677 int ticks;
678 int insts;
679
680 int exception;
681
682 int end_of_registers;
683
684 int msize;
685 unsigned char *memory;
686 unsigned long bfd_mach;
687 } saved_state;
688
689 #define DREG(x) (saved_state.dpregs[x])
690 #define GREG(x,i) DPREG ((x) | (i << 3))
691 #define DPREG(x) (saved_state.dpregs[x])
692 #define DREG(x) (saved_state.dpregs[x])
693 #define PREG(x) (saved_state.dpregs[x + 8])
694 #define SPREG PREG (6)
695 #define FPREG PREG (7)
696 #define IREG(x) (saved_state.iregs[x])
697 #define MREG(x) (saved_state.mregs[x])
698 #define BREG(x) (saved_state.bregs[x])
699 #define LREG(x) (saved_state.lregs[x])
700 #define A0XREG (saved_state.a0x)
701 #define A0WREG (saved_state.a0w)
702 #define A1XREG (saved_state.a1x)
703 #define A1WREG (saved_state.a1w)
704 #define CCREG (saved_state.cc)
705 #define LC0REG (saved_state.lc[0])
706 #define LT0REG (saved_state.lt[0])
707 #define LB0REG (saved_state.lb[0])
708 #define LC1REG (saved_state.lc[1])
709 #define LT1REG (saved_state.lt[1])
710 #define LB1REG (saved_state.lb[1])
711 #define RETSREG (saved_state.rets)
712 #define PCREG (saved_state.pc)
713
714 static bu32 *
715 get_allreg (int grp, int reg)
716 {
717 int fullreg = (grp << 3) | reg;
718 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
719 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
720 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
721 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
722 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
723 , , , , , , , ,
724 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
725 REG_CYCLES2,
726 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
727 REG_LASTREG */
728 switch (fullreg >> 2)
729 {
730 case 0: case 1: return &DREG (reg); break;
731 case 2: case 3: return &PREG (reg); break;
732 case 4: return &IREG (reg & 3); break;
733 case 5: return &MREG (reg & 3); break;
734 case 6: return &BREG (reg & 3); break;
735 case 7: return &LREG (reg & 3); break;
736 default:
737 switch (fullreg)
738 {
739 case 32: return &saved_state.a0x;
740 case 33: return &saved_state.a0w;
741 case 34: return &saved_state.a1x;
742 case 35: return &saved_state.a1w;
743 case 39: return &saved_state.rets;
744 case 48: return &LC0REG;
745 case 49: return &LT0REG;
746 case 50: return &LB0REG;
747 case 51: return &LC1REG;
748 case 52: return &LT1REG;
749 case 53: return &LB1REG;
750 }
751 return 0;
752 }
753 }
754
755 static int
756 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
757 {
758 /* ProgCtrl
759 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
760 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
761 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
762 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
763 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
764
765 if (prgfunc == 0 && poprnd == 0)
766 OUTS (outf, "NOP");
767 else if (parallel)
768 return 0;
769 else if (prgfunc == 1 && poprnd == 0)
770 OUTS (outf, "RTS");
771 else if (prgfunc == 1 && poprnd == 1)
772 OUTS (outf, "RTI");
773 else if (prgfunc == 1 && poprnd == 2)
774 OUTS (outf, "RTX");
775 else if (prgfunc == 1 && poprnd == 3)
776 OUTS (outf, "RTN");
777 else if (prgfunc == 1 && poprnd == 4)
778 OUTS (outf, "RTE");
779 else if (prgfunc == 2 && poprnd == 0)
780 OUTS (outf, "IDLE");
781 else if (prgfunc == 2 && poprnd == 3)
782 OUTS (outf, "CSYNC");
783 else if (prgfunc == 2 && poprnd == 4)
784 OUTS (outf, "SSYNC");
785 else if (prgfunc == 2 && poprnd == 5)
786 OUTS (outf, "EMUEXCPT");
787 else if (prgfunc == 3 && IS_DREG (0, poprnd))
788 {
789 OUTS (outf, "CLI ");
790 OUTS (outf, dregs (poprnd));
791 }
792 else if (prgfunc == 4 && IS_DREG (0, poprnd))
793 {
794 OUTS (outf, "STI ");
795 OUTS (outf, dregs (poprnd));
796 }
797 else if (prgfunc == 5 && IS_PREG (1, poprnd))
798 {
799 OUTS (outf, "JUMP (");
800 OUTS (outf, pregs (poprnd));
801 OUTS (outf, ")");
802 }
803 else if (prgfunc == 6 && IS_PREG (1, poprnd))
804 {
805 OUTS (outf, "CALL (");
806 OUTS (outf, pregs (poprnd));
807 OUTS (outf, ")");
808 }
809 else if (prgfunc == 7 && IS_PREG (1, poprnd))
810 {
811 OUTS (outf, "CALL (PC + ");
812 OUTS (outf, pregs (poprnd));
813 OUTS (outf, ")");
814 }
815 else if (prgfunc == 8 && IS_PREG (1, poprnd))
816 {
817 OUTS (outf, "JUMP (PC + ");
818 OUTS (outf, pregs (poprnd));
819 OUTS (outf, ")");
820 }
821 else if (prgfunc == 9)
822 {
823 OUTS (outf, "RAISE ");
824 OUTS (outf, uimm4 (poprnd));
825 }
826 else if (prgfunc == 10)
827 {
828 OUTS (outf, "EXCPT ");
829 OUTS (outf, uimm4 (poprnd));
830 }
831 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
832 {
833 OUTS (outf, "TESTSET (");
834 OUTS (outf, pregs (poprnd));
835 OUTS (outf, ")");
836 }
837 else
838 return 0;
839 return 2;
840 }
841
842 static int
843 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
844 {
845 /* CaCTRL
846 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
847 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
848 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
849 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
850 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
851 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
852
853 if (parallel)
854 return 0;
855
856 if (a == 0 && op == 0)
857 {
858 OUTS (outf, "PREFETCH[");
859 OUTS (outf, pregs (reg));
860 OUTS (outf, "]");
861 }
862 else if (a == 0 && op == 1)
863 {
864 OUTS (outf, "FLUSHINV[");
865 OUTS (outf, pregs (reg));
866 OUTS (outf, "]");
867 }
868 else if (a == 0 && op == 2)
869 {
870 OUTS (outf, "FLUSH[");
871 OUTS (outf, pregs (reg));
872 OUTS (outf, "]");
873 }
874 else if (a == 0 && op == 3)
875 {
876 OUTS (outf, "IFLUSH[");
877 OUTS (outf, pregs (reg));
878 OUTS (outf, "]");
879 }
880 else if (a == 1 && op == 0)
881 {
882 OUTS (outf, "PREFETCH[");
883 OUTS (outf, pregs (reg));
884 OUTS (outf, "++]");
885 }
886 else if (a == 1 && op == 1)
887 {
888 OUTS (outf, "FLUSHINV[");
889 OUTS (outf, pregs (reg));
890 OUTS (outf, "++]");
891 }
892 else if (a == 1 && op == 2)
893 {
894 OUTS (outf, "FLUSH[");
895 OUTS (outf, pregs (reg));
896 OUTS (outf, "++]");
897 }
898 else if (a == 1 && op == 3)
899 {
900 OUTS (outf, "IFLUSH[");
901 OUTS (outf, pregs (reg));
902 OUTS (outf, "++]");
903 }
904 else
905 return 0;
906 return 2;
907 }
908
909 static int
910 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
911 {
912 /* PushPopReg
913 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
914 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
915 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
916 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
917 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
918 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
919
920 if (parallel)
921 return 0;
922
923 if (W == 0 && mostreg (reg, grp))
924 {
925 OUTS (outf, allregs (reg, grp));
926 OUTS (outf, " = [SP++]");
927 }
928 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
929 {
930 OUTS (outf, "[--SP] = ");
931 OUTS (outf, allregs (reg, grp));
932 }
933 else
934 return 0;
935 return 2;
936 }
937
938 static int
939 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
940 {
941 /* PushPopMultiple
942 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
943 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
944 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
945 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
946 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
947 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
948 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
949 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
950
951 if (parallel)
952 return 0;
953
954 if (pr > 5)
955 return 0;
956
957 if (W == 1 && d == 1 && p == 1)
958 {
959 OUTS (outf, "[--SP] = (R7:");
960 OUTS (outf, imm5d (dr));
961 OUTS (outf, ", P5:");
962 OUTS (outf, imm5d (pr));
963 OUTS (outf, ")");
964 }
965 else if (W == 1 && d == 1 && p == 0 && pr == 0)
966 {
967 OUTS (outf, "[--SP] = (R7:");
968 OUTS (outf, imm5d (dr));
969 OUTS (outf, ")");
970 }
971 else if (W == 1 && d == 0 && p == 1 && dr == 0)
972 {
973 OUTS (outf, "[--SP] = (P5:");
974 OUTS (outf, imm5d (pr));
975 OUTS (outf, ")");
976 }
977 else if (W == 0 && d == 1 && p == 1)
978 {
979 OUTS (outf, "(R7:");
980 OUTS (outf, imm5d (dr));
981 OUTS (outf, ", P5:");
982 OUTS (outf, imm5d (pr));
983 OUTS (outf, ") = [SP++]");
984 }
985 else if (W == 0 && d == 1 && p == 0 && pr == 0)
986 {
987 OUTS (outf, "(R7:");
988 OUTS (outf, imm5d (dr));
989 OUTS (outf, ") = [SP++]");
990 }
991 else if (W == 0 && d == 0 && p == 1 && dr == 0)
992 {
993 OUTS (outf, "(P5:");
994 OUTS (outf, imm5d (pr));
995 OUTS (outf, ") = [SP++]");
996 }
997 else
998 return 0;
999 return 2;
1000 }
1001
1002 static int
1003 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
1004 {
1005 /* ccMV
1006 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1007 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
1008 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1009 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
1010 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
1011 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
1012 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
1013 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
1014
1015 if (parallel)
1016 return 0;
1017
1018 if (T == 1)
1019 {
1020 OUTS (outf, "IF CC ");
1021 OUTS (outf, gregs (dst, d));
1022 OUTS (outf, " = ");
1023 OUTS (outf, gregs (src, s));
1024 }
1025 else if (T == 0)
1026 {
1027 OUTS (outf, "IF !CC ");
1028 OUTS (outf, gregs (dst, d));
1029 OUTS (outf, " = ");
1030 OUTS (outf, gregs (src, s));
1031 }
1032 else
1033 return 0;
1034 return 2;
1035 }
1036
1037 static int
1038 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1039 {
1040 /* CCflag
1041 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1042 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1043 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1044 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1045 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1046 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1047 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1048 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1049
1050 if (parallel)
1051 return 0;
1052
1053 if (opc == 0 && I == 0 && G == 0)
1054 {
1055 OUTS (outf, "CC = ");
1056 OUTS (outf, dregs (x));
1057 OUTS (outf, " == ");
1058 OUTS (outf, dregs (y));
1059 }
1060 else if (opc == 1 && I == 0 && G == 0)
1061 {
1062 OUTS (outf, "CC = ");
1063 OUTS (outf, dregs (x));
1064 OUTS (outf, " < ");
1065 OUTS (outf, dregs (y));
1066 }
1067 else if (opc == 2 && I == 0 && G == 0)
1068 {
1069 OUTS (outf, "CC = ");
1070 OUTS (outf, dregs (x));
1071 OUTS (outf, " <= ");
1072 OUTS (outf, dregs (y));
1073 }
1074 else if (opc == 3 && I == 0 && G == 0)
1075 {
1076 OUTS (outf, "CC = ");
1077 OUTS (outf, dregs (x));
1078 OUTS (outf, " < ");
1079 OUTS (outf, dregs (y));
1080 OUTS (outf, " (IU)");
1081 }
1082 else if (opc == 4 && I == 0 && G == 0)
1083 {
1084 OUTS (outf, "CC = ");
1085 OUTS (outf, dregs (x));
1086 OUTS (outf, " <= ");
1087 OUTS (outf, dregs (y));
1088 OUTS (outf, " (IU)");
1089 }
1090 else if (opc == 0 && I == 1 && G == 0)
1091 {
1092 OUTS (outf, "CC = ");
1093 OUTS (outf, dregs (x));
1094 OUTS (outf, " == ");
1095 OUTS (outf, imm3 (y));
1096 }
1097 else if (opc == 1 && I == 1 && G == 0)
1098 {
1099 OUTS (outf, "CC = ");
1100 OUTS (outf, dregs (x));
1101 OUTS (outf, " < ");
1102 OUTS (outf, imm3 (y));
1103 }
1104 else if (opc == 2 && I == 1 && G == 0)
1105 {
1106 OUTS (outf, "CC = ");
1107 OUTS (outf, dregs (x));
1108 OUTS (outf, " <= ");
1109 OUTS (outf, imm3 (y));
1110 }
1111 else if (opc == 3 && I == 1 && G == 0)
1112 {
1113 OUTS (outf, "CC = ");
1114 OUTS (outf, dregs (x));
1115 OUTS (outf, " < ");
1116 OUTS (outf, uimm3 (y));
1117 OUTS (outf, " (IU)");
1118 }
1119 else if (opc == 4 && I == 1 && G == 0)
1120 {
1121 OUTS (outf, "CC = ");
1122 OUTS (outf, dregs (x));
1123 OUTS (outf, " <= ");
1124 OUTS (outf, uimm3 (y));
1125 OUTS (outf, " (IU)");
1126 }
1127 else if (opc == 0 && I == 0 && G == 1)
1128 {
1129 OUTS (outf, "CC = ");
1130 OUTS (outf, pregs (x));
1131 OUTS (outf, " == ");
1132 OUTS (outf, pregs (y));
1133 }
1134 else if (opc == 1 && I == 0 && G == 1)
1135 {
1136 OUTS (outf, "CC = ");
1137 OUTS (outf, pregs (x));
1138 OUTS (outf, " < ");
1139 OUTS (outf, pregs (y));
1140 }
1141 else if (opc == 2 && I == 0 && G == 1)
1142 {
1143 OUTS (outf, "CC = ");
1144 OUTS (outf, pregs (x));
1145 OUTS (outf, " <= ");
1146 OUTS (outf, pregs (y));
1147 }
1148 else if (opc == 3 && I == 0 && G == 1)
1149 {
1150 OUTS (outf, "CC = ");
1151 OUTS (outf, pregs (x));
1152 OUTS (outf, " < ");
1153 OUTS (outf, pregs (y));
1154 OUTS (outf, " (IU)");
1155 }
1156 else if (opc == 4 && I == 0 && G == 1)
1157 {
1158 OUTS (outf, "CC = ");
1159 OUTS (outf, pregs (x));
1160 OUTS (outf, " <= ");
1161 OUTS (outf, pregs (y));
1162 OUTS (outf, " (IU)");
1163 }
1164 else if (opc == 0 && I == 1 && G == 1)
1165 {
1166 OUTS (outf, "CC = ");
1167 OUTS (outf, pregs (x));
1168 OUTS (outf, " == ");
1169 OUTS (outf, imm3 (y));
1170 }
1171 else if (opc == 1 && I == 1 && G == 1)
1172 {
1173 OUTS (outf, "CC = ");
1174 OUTS (outf, pregs (x));
1175 OUTS (outf, " < ");
1176 OUTS (outf, imm3 (y));
1177 }
1178 else if (opc == 2 && I == 1 && G == 1)
1179 {
1180 OUTS (outf, "CC = ");
1181 OUTS (outf, pregs (x));
1182 OUTS (outf, " <= ");
1183 OUTS (outf, imm3 (y));
1184 }
1185 else if (opc == 3 && I == 1 && G == 1)
1186 {
1187 OUTS (outf, "CC = ");
1188 OUTS (outf, pregs (x));
1189 OUTS (outf, " < ");
1190 OUTS (outf, uimm3 (y));
1191 OUTS (outf, " (IU)");
1192 }
1193 else if (opc == 4 && I == 1 && G == 1)
1194 {
1195 OUTS (outf, "CC = ");
1196 OUTS (outf, pregs (x));
1197 OUTS (outf, " <= ");
1198 OUTS (outf, uimm3 (y));
1199 OUTS (outf, " (IU)");
1200 }
1201 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
1202 OUTS (outf, "CC = A0 == A1");
1203
1204 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
1205 OUTS (outf, "CC = A0 < A1");
1206
1207 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
1208 OUTS (outf, "CC = A0 <= A1");
1209
1210 else
1211 return 0;
1212 return 2;
1213 }
1214
1215 static int
1216 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1217 {
1218 /* CC2dreg
1219 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1220 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1221 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1222 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1223 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1224
1225 if (parallel)
1226 return 0;
1227
1228 if (op == 0)
1229 {
1230 OUTS (outf, dregs (reg));
1231 OUTS (outf, " = CC");
1232 }
1233 else if (op == 1)
1234 {
1235 OUTS (outf, "CC = ");
1236 OUTS (outf, dregs (reg));
1237 }
1238 else if (op == 3 && reg == 0)
1239 OUTS (outf, "CC = !CC");
1240 else
1241 return 0;
1242
1243 return 2;
1244 }
1245
1246 static int
1247 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1248 {
1249 /* CC2stat
1250 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1251 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1252 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1253 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1254 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1255 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1256
1257 const char *bitname = statbits (cbit);
1258
1259 if (parallel)
1260 return 0;
1261
1262 if (decode_statbits[cbit] == REG_LASTREG)
1263 {
1264 /* All ASTAT bits except CC may be operated on in hardware, but may
1265 not have a dedicated insn, so still decode "valid" insns. */
1266 static char bitnames[64];
1267 if (cbit != 5)
1268 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1269 else
1270 return 0;
1271
1272 bitname = bitnames;
1273 }
1274
1275 if (op == 0 && D == 0)
1276 {
1277 OUTS (outf, "CC = ");
1278 OUTS (outf, bitname);
1279 }
1280 else if (op == 1 && D == 0)
1281 {
1282 OUTS (outf, "CC |= ");
1283 OUTS (outf, bitname);
1284 }
1285 else if (op == 2 && D == 0)
1286 {
1287 OUTS (outf, "CC &= ");
1288 OUTS (outf, bitname);
1289 }
1290 else if (op == 3 && D == 0)
1291 {
1292 OUTS (outf, "CC ^= ");
1293 OUTS (outf, bitname);
1294 }
1295 else if (op == 0 && D == 1)
1296 {
1297 OUTS (outf, bitname);
1298 OUTS (outf, " = CC");
1299 }
1300 else if (op == 1 && D == 1)
1301 {
1302 OUTS (outf, bitname);
1303 OUTS (outf, " |= CC");
1304 }
1305 else if (op == 2 && D == 1)
1306 {
1307 OUTS (outf, bitname);
1308 OUTS (outf, " &= CC");
1309 }
1310 else if (op == 3 && D == 1)
1311 {
1312 OUTS (outf, bitname);
1313 OUTS (outf, " ^= CC");
1314 }
1315 else
1316 return 0;
1317
1318 return 2;
1319 }
1320
1321 static int
1322 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1323 {
1324 /* BRCC
1325 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1326 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1327 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1328 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1329 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1330 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1331
1332 if (parallel)
1333 return 0;
1334
1335 if (T == 1 && B == 1)
1336 {
1337 OUTS (outf, "IF CC JUMP 0x");
1338 OUTS (outf, pcrel10 (offset));
1339 OUTS (outf, " (BP)");
1340 }
1341 else if (T == 0 && B == 1)
1342 {
1343 OUTS (outf, "IF !CC JUMP 0x");
1344 OUTS (outf, pcrel10 (offset));
1345 OUTS (outf, " (BP)");
1346 }
1347 else if (T == 1)
1348 {
1349 OUTS (outf, "IF CC JUMP 0x");
1350 OUTS (outf, pcrel10 (offset));
1351 }
1352 else if (T == 0)
1353 {
1354 OUTS (outf, "IF !CC JUMP 0x");
1355 OUTS (outf, pcrel10 (offset));
1356 }
1357 else
1358 return 0;
1359
1360 return 2;
1361 }
1362
1363 static int
1364 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1365 {
1366 /* UJUMP
1367 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1368 | 0 | 0 | 1 | 0 |.offset........................................|
1369 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1370 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1371
1372 if (parallel)
1373 return 0;
1374
1375 OUTS (outf, "JUMP.S 0x");
1376 OUTS (outf, pcrel12 (offset));
1377 return 2;
1378 }
1379
1380 static int
1381 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1382 {
1383 /* REGMV
1384 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1385 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1386 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1387 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1388 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1389 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1390 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1391
1392 /* Reserved slots cannot be a src/dst. */
1393 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1394 goto invalid_move;
1395
1396 /* Standard register moves */
1397 if ((gs < 2) || /* Dregs/Pregs as source */
1398 (gd < 2) || /* Dregs/Pregs as dest */
1399 (gs == 4 && src < 4) || /* Accumulators as source */
1400 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1401 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1402 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1403 goto valid_move;
1404
1405 /* dareg = dareg (IMBL) */
1406 if (gs < 4 && gd < 4)
1407 goto valid_move;
1408
1409 /* USP can be src to sysregs, but not dagregs. */
1410 if ((gs == 7 && src == 0) && (gd >= 4))
1411 goto valid_move;
1412
1413 /* USP can move between genregs (only check Accumulators). */
1414 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1415 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1416 goto valid_move;
1417
1418 /* Still here ? Invalid reg pair. */
1419 invalid_move:
1420 return 0;
1421
1422 valid_move:
1423 OUTS (outf, allregs (dst, gd));
1424 OUTS (outf, " = ");
1425 OUTS (outf, allregs (src, gs));
1426 return 2;
1427 }
1428
1429 static int
1430 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1431 {
1432 /* ALU2op
1433 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1434 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1435 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1436 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1437 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1438 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1439
1440 if (opc == 0)
1441 {
1442 OUTS (outf, dregs (dst));
1443 OUTS (outf, " >>>= ");
1444 OUTS (outf, dregs (src));
1445 }
1446 else if (opc == 1)
1447 {
1448 OUTS (outf, dregs (dst));
1449 OUTS (outf, " >>= ");
1450 OUTS (outf, dregs (src));
1451 }
1452 else if (opc == 2)
1453 {
1454 OUTS (outf, dregs (dst));
1455 OUTS (outf, " <<= ");
1456 OUTS (outf, dregs (src));
1457 }
1458 else if (opc == 3)
1459 {
1460 OUTS (outf, dregs (dst));
1461 OUTS (outf, " *= ");
1462 OUTS (outf, dregs (src));
1463 }
1464 else if (opc == 4)
1465 {
1466 OUTS (outf, dregs (dst));
1467 OUTS (outf, " = (");
1468 OUTS (outf, dregs (dst));
1469 OUTS (outf, " + ");
1470 OUTS (outf, dregs (src));
1471 OUTS (outf, ") << 0x1");
1472 }
1473 else if (opc == 5)
1474 {
1475 OUTS (outf, dregs (dst));
1476 OUTS (outf, " = (");
1477 OUTS (outf, dregs (dst));
1478 OUTS (outf, " + ");
1479 OUTS (outf, dregs (src));
1480 OUTS (outf, ") << 0x2");
1481 }
1482 else if (opc == 8)
1483 {
1484 OUTS (outf, "DIVQ (");
1485 OUTS (outf, dregs (dst));
1486 OUTS (outf, ", ");
1487 OUTS (outf, dregs (src));
1488 OUTS (outf, ")");
1489 }
1490 else if (opc == 9)
1491 {
1492 OUTS (outf, "DIVS (");
1493 OUTS (outf, dregs (dst));
1494 OUTS (outf, ", ");
1495 OUTS (outf, dregs (src));
1496 OUTS (outf, ")");
1497 }
1498 else if (opc == 10)
1499 {
1500 OUTS (outf, dregs (dst));
1501 OUTS (outf, " = ");
1502 OUTS (outf, dregs_lo (src));
1503 OUTS (outf, " (X)");
1504 }
1505 else if (opc == 11)
1506 {
1507 OUTS (outf, dregs (dst));
1508 OUTS (outf, " = ");
1509 OUTS (outf, dregs_lo (src));
1510 OUTS (outf, " (Z)");
1511 }
1512 else if (opc == 12)
1513 {
1514 OUTS (outf, dregs (dst));
1515 OUTS (outf, " = ");
1516 OUTS (outf, dregs_byte (src));
1517 OUTS (outf, " (X)");
1518 }
1519 else if (opc == 13)
1520 {
1521 OUTS (outf, dregs (dst));
1522 OUTS (outf, " = ");
1523 OUTS (outf, dregs_byte (src));
1524 OUTS (outf, " (Z)");
1525 }
1526 else if (opc == 14)
1527 {
1528 OUTS (outf, dregs (dst));
1529 OUTS (outf, " = -");
1530 OUTS (outf, dregs (src));
1531 }
1532 else if (opc == 15)
1533 {
1534 OUTS (outf, dregs (dst));
1535 OUTS (outf, " =~ ");
1536 OUTS (outf, dregs (src));
1537 }
1538 else
1539 return 0;
1540
1541 return 2;
1542 }
1543
1544 static int
1545 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1546 {
1547 /* PTR2op
1548 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1549 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1550 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1551 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1552 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1553 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1554
1555 if (opc == 0)
1556 {
1557 OUTS (outf, pregs (dst));
1558 OUTS (outf, " -= ");
1559 OUTS (outf, pregs (src));
1560 }
1561 else if (opc == 1)
1562 {
1563 OUTS (outf, pregs (dst));
1564 OUTS (outf, " = ");
1565 OUTS (outf, pregs (src));
1566 OUTS (outf, " << 0x2");
1567 }
1568 else if (opc == 3)
1569 {
1570 OUTS (outf, pregs (dst));
1571 OUTS (outf, " = ");
1572 OUTS (outf, pregs (src));
1573 OUTS (outf, " >> 0x2");
1574 }
1575 else if (opc == 4)
1576 {
1577 OUTS (outf, pregs (dst));
1578 OUTS (outf, " = ");
1579 OUTS (outf, pregs (src));
1580 OUTS (outf, " >> 0x1");
1581 }
1582 else if (opc == 5)
1583 {
1584 OUTS (outf, pregs (dst));
1585 OUTS (outf, " += ");
1586 OUTS (outf, pregs (src));
1587 OUTS (outf, " (BREV)");
1588 }
1589 else if (opc == 6)
1590 {
1591 OUTS (outf, pregs (dst));
1592 OUTS (outf, " = (");
1593 OUTS (outf, pregs (dst));
1594 OUTS (outf, " + ");
1595 OUTS (outf, pregs (src));
1596 OUTS (outf, ") << 0x1");
1597 }
1598 else if (opc == 7)
1599 {
1600 OUTS (outf, pregs (dst));
1601 OUTS (outf, " = (");
1602 OUTS (outf, pregs (dst));
1603 OUTS (outf, " + ");
1604 OUTS (outf, pregs (src));
1605 OUTS (outf, ") << 0x2");
1606 }
1607 else
1608 return 0;
1609
1610 return 2;
1611 }
1612
1613 static int
1614 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1615 {
1616 /* LOGI2op
1617 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1618 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1619 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1620 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1621 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1622 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1623
1624 if (parallel)
1625 return 0;
1626
1627 if (opc == 0)
1628 {
1629 OUTS (outf, "CC = !BITTST (");
1630 OUTS (outf, dregs (dst));
1631 OUTS (outf, ", ");
1632 OUTS (outf, uimm5 (src));
1633 OUTS (outf, ");\t\t/* bit");
1634 OUTS (outf, imm7d (src));
1635 OUTS (outf, " */");
1636 comment = 1;
1637 }
1638 else if (opc == 1)
1639 {
1640 OUTS (outf, "CC = BITTST (");
1641 OUTS (outf, dregs (dst));
1642 OUTS (outf, ", ");
1643 OUTS (outf, uimm5 (src));
1644 OUTS (outf, ");\t\t/* bit");
1645 OUTS (outf, imm7d (src));
1646 OUTS (outf, " */");
1647 comment = 1;
1648 }
1649 else if (opc == 2)
1650 {
1651 OUTS (outf, "BITSET (");
1652 OUTS (outf, dregs (dst));
1653 OUTS (outf, ", ");
1654 OUTS (outf, uimm5 (src));
1655 OUTS (outf, ");\t\t/* bit");
1656 OUTS (outf, imm7d (src));
1657 OUTS (outf, " */");
1658 comment = 1;
1659 }
1660 else if (opc == 3)
1661 {
1662 OUTS (outf, "BITTGL (");
1663 OUTS (outf, dregs (dst));
1664 OUTS (outf, ", ");
1665 OUTS (outf, uimm5 (src));
1666 OUTS (outf, ");\t\t/* bit");
1667 OUTS (outf, imm7d (src));
1668 OUTS (outf, " */");
1669 comment = 1;
1670 }
1671 else if (opc == 4)
1672 {
1673 OUTS (outf, "BITCLR (");
1674 OUTS (outf, dregs (dst));
1675 OUTS (outf, ", ");
1676 OUTS (outf, uimm5 (src));
1677 OUTS (outf, ");\t\t/* bit");
1678 OUTS (outf, imm7d (src));
1679 OUTS (outf, " */");
1680 comment = 1;
1681 }
1682 else if (opc == 5)
1683 {
1684 OUTS (outf, dregs (dst));
1685 OUTS (outf, " >>>= ");
1686 OUTS (outf, uimm5 (src));
1687 }
1688 else if (opc == 6)
1689 {
1690 OUTS (outf, dregs (dst));
1691 OUTS (outf, " >>= ");
1692 OUTS (outf, uimm5 (src));
1693 }
1694 else if (opc == 7)
1695 {
1696 OUTS (outf, dregs (dst));
1697 OUTS (outf, " <<= ");
1698 OUTS (outf, uimm5 (src));
1699 }
1700 else
1701 return 0;
1702
1703 return 2;
1704 }
1705
1706 static int
1707 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1708 {
1709 /* COMP3op
1710 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1711 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1712 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1713 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1714 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1715 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1716 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1717
1718 if (opc == 5 && src1 == src0)
1719 {
1720 OUTS (outf, pregs (dst));
1721 OUTS (outf, " = ");
1722 OUTS (outf, pregs (src0));
1723 OUTS (outf, " << 0x1");
1724 }
1725 else if (opc == 1)
1726 {
1727 OUTS (outf, dregs (dst));
1728 OUTS (outf, " = ");
1729 OUTS (outf, dregs (src0));
1730 OUTS (outf, " - ");
1731 OUTS (outf, dregs (src1));
1732 }
1733 else if (opc == 2)
1734 {
1735 OUTS (outf, dregs (dst));
1736 OUTS (outf, " = ");
1737 OUTS (outf, dregs (src0));
1738 OUTS (outf, " & ");
1739 OUTS (outf, dregs (src1));
1740 }
1741 else if (opc == 3)
1742 {
1743 OUTS (outf, dregs (dst));
1744 OUTS (outf, " = ");
1745 OUTS (outf, dregs (src0));
1746 OUTS (outf, " | ");
1747 OUTS (outf, dregs (src1));
1748 }
1749 else if (opc == 4)
1750 {
1751 OUTS (outf, dregs (dst));
1752 OUTS (outf, " = ");
1753 OUTS (outf, dregs (src0));
1754 OUTS (outf, " ^ ");
1755 OUTS (outf, dregs (src1));
1756 }
1757 else if (opc == 5)
1758 {
1759 OUTS (outf, pregs (dst));
1760 OUTS (outf, " = ");
1761 OUTS (outf, pregs (src0));
1762 OUTS (outf, " + ");
1763 OUTS (outf, pregs (src1));
1764 }
1765 else if (opc == 6)
1766 {
1767 OUTS (outf, pregs (dst));
1768 OUTS (outf, " = ");
1769 OUTS (outf, pregs (src0));
1770 OUTS (outf, " + (");
1771 OUTS (outf, pregs (src1));
1772 OUTS (outf, " << 0x1)");
1773 }
1774 else if (opc == 7)
1775 {
1776 OUTS (outf, pregs (dst));
1777 OUTS (outf, " = ");
1778 OUTS (outf, pregs (src0));
1779 OUTS (outf, " + (");
1780 OUTS (outf, pregs (src1));
1781 OUTS (outf, " << 0x2)");
1782 }
1783 else if (opc == 0)
1784 {
1785 OUTS (outf, dregs (dst));
1786 OUTS (outf, " = ");
1787 OUTS (outf, dregs (src0));
1788 OUTS (outf, " + ");
1789 OUTS (outf, dregs (src1));
1790 }
1791 else
1792 return 0;
1793
1794 return 2;
1795 }
1796
1797 static int
1798 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1799 {
1800 /* COMPI2opD
1801 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1802 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1803 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1804 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1805 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1806 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1807
1808 bu32 *pval = get_allreg (0, dst);
1809
1810 if (parallel)
1811 return 0;
1812
1813 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1814 to combine them, so it prints out the right values.
1815 Here we keep track of the registers. */
1816 if (op == 0)
1817 {
1818 *pval = imm7_val (src);
1819 if (src & 0x40)
1820 *pval |= 0xFFFFFF80;
1821 else
1822 *pval &= 0x7F;
1823 }
1824
1825 if (op == 0)
1826 {
1827 OUTS (outf, dregs (dst));
1828 OUTS (outf, " = ");
1829 OUTS (outf, imm7 (src));
1830 OUTS (outf, " (X);\t\t/*\t\t");
1831 OUTS (outf, dregs (dst));
1832 OUTS (outf, "=");
1833 OUTS (outf, uimm32 (*pval));
1834 OUTS (outf, "(");
1835 OUTS (outf, imm32 (*pval));
1836 OUTS (outf, ") */");
1837 comment = 1;
1838 }
1839 else if (op == 1)
1840 {
1841 OUTS (outf, dregs (dst));
1842 OUTS (outf, " += ");
1843 OUTS (outf, imm7 (src));
1844 OUTS (outf, ";\t\t/* (");
1845 OUTS (outf, imm7d (src));
1846 OUTS (outf, ") */");
1847 comment = 1;
1848 }
1849 else
1850 return 0;
1851
1852 return 2;
1853 }
1854
1855 static int
1856 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1857 {
1858 /* COMPI2opP
1859 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1860 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1861 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1862 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1863 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1864 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1865
1866 bu32 *pval = get_allreg (1, dst);
1867
1868 if (parallel)
1869 return 0;
1870
1871 if (op == 0)
1872 {
1873 *pval = imm7_val (src);
1874 if (src & 0x40)
1875 *pval |= 0xFFFFFF80;
1876 else
1877 *pval &= 0x7F;
1878 }
1879
1880 if (op == 0)
1881 {
1882 OUTS (outf, pregs (dst));
1883 OUTS (outf, " = ");
1884 OUTS (outf, imm7 (src));
1885 OUTS (outf, " (X);\t\t/*\t\t");
1886 OUTS (outf, pregs (dst));
1887 OUTS (outf, "=");
1888 OUTS (outf, uimm32 (*pval));
1889 OUTS (outf, "(");
1890 OUTS (outf, imm32 (*pval));
1891 OUTS (outf, ") */");
1892 comment = 1;
1893 }
1894 else if (op == 1)
1895 {
1896 OUTS (outf, pregs (dst));
1897 OUTS (outf, " += ");
1898 OUTS (outf, imm7 (src));
1899 OUTS (outf, ";\t\t/* (");
1900 OUTS (outf, imm7d (src));
1901 OUTS (outf, ") */");
1902 comment = 1;
1903 }
1904 else
1905 return 0;
1906
1907 return 2;
1908 }
1909
1910 static int
1911 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1912 {
1913 /* LDSTpmod
1914 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1915 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1916 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1917 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1918 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1919 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1920 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1921 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1922
1923 if (aop == 1 && W == 0 && idx == ptr)
1924 {
1925 OUTS (outf, dregs_lo (reg));
1926 OUTS (outf, " = W[");
1927 OUTS (outf, pregs (ptr));
1928 OUTS (outf, "]");
1929 }
1930 else if (aop == 2 && W == 0 && idx == ptr)
1931 {
1932 OUTS (outf, dregs_hi (reg));
1933 OUTS (outf, " = W[");
1934 OUTS (outf, pregs (ptr));
1935 OUTS (outf, "]");
1936 }
1937 else if (aop == 1 && W == 1 && idx == ptr)
1938 {
1939 OUTS (outf, "W[");
1940 OUTS (outf, pregs (ptr));
1941 OUTS (outf, "] = ");
1942 OUTS (outf, dregs_lo (reg));
1943 }
1944 else if (aop == 2 && W == 1 && idx == ptr)
1945 {
1946 OUTS (outf, "W[");
1947 OUTS (outf, pregs (ptr));
1948 OUTS (outf, "] = ");
1949 OUTS (outf, dregs_hi (reg));
1950 }
1951 else if (aop == 0 && W == 0)
1952 {
1953 OUTS (outf, dregs (reg));
1954 OUTS (outf, " = [");
1955 OUTS (outf, pregs (ptr));
1956 OUTS (outf, " ++ ");
1957 OUTS (outf, pregs (idx));
1958 OUTS (outf, "]");
1959 }
1960 else if (aop == 1 && W == 0)
1961 {
1962 OUTS (outf, dregs_lo (reg));
1963 OUTS (outf, " = W[");
1964 OUTS (outf, pregs (ptr));
1965 OUTS (outf, " ++ ");
1966 OUTS (outf, pregs (idx));
1967 OUTS (outf, "]");
1968 }
1969 else if (aop == 2 && W == 0)
1970 {
1971 OUTS (outf, dregs_hi (reg));
1972 OUTS (outf, " = W[");
1973 OUTS (outf, pregs (ptr));
1974 OUTS (outf, " ++ ");
1975 OUTS (outf, pregs (idx));
1976 OUTS (outf, "]");
1977 }
1978 else if (aop == 3 && W == 0)
1979 {
1980 OUTS (outf, dregs (reg));
1981 OUTS (outf, " = W[");
1982 OUTS (outf, pregs (ptr));
1983 OUTS (outf, " ++ ");
1984 OUTS (outf, pregs (idx));
1985 OUTS (outf, "] (Z)");
1986 }
1987 else if (aop == 3 && W == 1)
1988 {
1989 OUTS (outf, dregs (reg));
1990 OUTS (outf, " = W[");
1991 OUTS (outf, pregs (ptr));
1992 OUTS (outf, " ++ ");
1993 OUTS (outf, pregs (idx));
1994 OUTS (outf, "] (X)");
1995 }
1996 else if (aop == 0 && W == 1)
1997 {
1998 OUTS (outf, "[");
1999 OUTS (outf, pregs (ptr));
2000 OUTS (outf, " ++ ");
2001 OUTS (outf, pregs (idx));
2002 OUTS (outf, "] = ");
2003 OUTS (outf, dregs (reg));
2004 }
2005 else if (aop == 1 && W == 1)
2006 {
2007 OUTS (outf, "W[");
2008 OUTS (outf, pregs (ptr));
2009 OUTS (outf, " ++ ");
2010 OUTS (outf, pregs (idx));
2011 OUTS (outf, "] = ");
2012 OUTS (outf, dregs_lo (reg));
2013 }
2014 else if (aop == 2 && W == 1)
2015 {
2016 OUTS (outf, "W[");
2017 OUTS (outf, pregs (ptr));
2018 OUTS (outf, " ++ ");
2019 OUTS (outf, pregs (idx));
2020 OUTS (outf, "] = ");
2021 OUTS (outf, dregs_hi (reg));
2022 }
2023 else
2024 return 0;
2025
2026 return 2;
2027 }
2028
2029 static int
2030 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
2031 {
2032 /* dagMODim
2033 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2034 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2035 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2036 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
2037 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
2038 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
2039 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2040
2041 if (op == 0 && br == 1)
2042 {
2043 OUTS (outf, iregs (i));
2044 OUTS (outf, " += ");
2045 OUTS (outf, mregs (m));
2046 OUTS (outf, " (BREV)");
2047 }
2048 else if (op == 0)
2049 {
2050 OUTS (outf, iregs (i));
2051 OUTS (outf, " += ");
2052 OUTS (outf, mregs (m));
2053 }
2054 else if (op == 1 && br == 0)
2055 {
2056 OUTS (outf, iregs (i));
2057 OUTS (outf, " -= ");
2058 OUTS (outf, mregs (m));
2059 }
2060 else
2061 return 0;
2062
2063 return 2;
2064 }
2065
2066 static int
2067 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2068 {
2069 /* dagMODik
2070 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2071 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2072 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2073 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2074 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2075
2076 if (op == 0)
2077 {
2078 OUTS (outf, iregs (i));
2079 OUTS (outf, " += 0x2");
2080 }
2081 else if (op == 1)
2082 {
2083 OUTS (outf, iregs (i));
2084 OUTS (outf, " -= 0x2");
2085 }
2086 else if (op == 2)
2087 {
2088 OUTS (outf, iregs (i));
2089 OUTS (outf, " += 0x4");
2090 }
2091 else if (op == 3)
2092 {
2093 OUTS (outf, iregs (i));
2094 OUTS (outf, " -= 0x4");
2095 }
2096 else
2097 return 0;
2098
2099 if (! parallel )
2100 {
2101 OUTS (outf, ";\t\t/* ( ");
2102 if (op == 0 || op == 1)
2103 OUTS (outf, "2");
2104 else if (op == 2 || op == 3)
2105 OUTS (outf, "4");
2106 OUTS (outf, ") */");
2107 comment = 1;
2108 }
2109
2110 return 2;
2111 }
2112
2113 static int
2114 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2115 {
2116 /* dspLDST
2117 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2118 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2119 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2120 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2121 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2122 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2123 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2124 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2125
2126 if (aop == 0 && W == 0 && m == 0)
2127 {
2128 OUTS (outf, dregs (reg));
2129 OUTS (outf, " = [");
2130 OUTS (outf, iregs (i));
2131 OUTS (outf, "++]");
2132 }
2133 else if (aop == 0 && W == 0 && m == 1)
2134 {
2135 OUTS (outf, dregs_lo (reg));
2136 OUTS (outf, " = W[");
2137 OUTS (outf, iregs (i));
2138 OUTS (outf, "++]");
2139 }
2140 else if (aop == 0 && W == 0 && m == 2)
2141 {
2142 OUTS (outf, dregs_hi (reg));
2143 OUTS (outf, " = W[");
2144 OUTS (outf, iregs (i));
2145 OUTS (outf, "++]");
2146 }
2147 else if (aop == 1 && W == 0 && m == 0)
2148 {
2149 OUTS (outf, dregs (reg));
2150 OUTS (outf, " = [");
2151 OUTS (outf, iregs (i));
2152 OUTS (outf, "--]");
2153 }
2154 else if (aop == 1 && W == 0 && m == 1)
2155 {
2156 OUTS (outf, dregs_lo (reg));
2157 OUTS (outf, " = W[");
2158 OUTS (outf, iregs (i));
2159 OUTS (outf, "--]");
2160 }
2161 else if (aop == 1 && W == 0 && m == 2)
2162 {
2163 OUTS (outf, dregs_hi (reg));
2164 OUTS (outf, " = W[");
2165 OUTS (outf, iregs (i));
2166 OUTS (outf, "--]");
2167 }
2168 else if (aop == 2 && W == 0 && m == 0)
2169 {
2170 OUTS (outf, dregs (reg));
2171 OUTS (outf, " = [");
2172 OUTS (outf, iregs (i));
2173 OUTS (outf, "]");
2174 }
2175 else if (aop == 2 && W == 0 && m == 1)
2176 {
2177 OUTS (outf, dregs_lo (reg));
2178 OUTS (outf, " = W[");
2179 OUTS (outf, iregs (i));
2180 OUTS (outf, "]");
2181 }
2182 else if (aop == 2 && W == 0 && m == 2)
2183 {
2184 OUTS (outf, dregs_hi (reg));
2185 OUTS (outf, " = W[");
2186 OUTS (outf, iregs (i));
2187 OUTS (outf, "]");
2188 }
2189 else if (aop == 0 && W == 1 && m == 0)
2190 {
2191 OUTS (outf, "[");
2192 OUTS (outf, iregs (i));
2193 OUTS (outf, "++] = ");
2194 OUTS (outf, dregs (reg));
2195 }
2196 else if (aop == 0 && W == 1 && m == 1)
2197 {
2198 OUTS (outf, "W[");
2199 OUTS (outf, iregs (i));
2200 OUTS (outf, "++] = ");
2201 OUTS (outf, dregs_lo (reg));
2202 }
2203 else if (aop == 0 && W == 1 && m == 2)
2204 {
2205 OUTS (outf, "W[");
2206 OUTS (outf, iregs (i));
2207 OUTS (outf, "++] = ");
2208 OUTS (outf, dregs_hi (reg));
2209 }
2210 else if (aop == 1 && W == 1 && m == 0)
2211 {
2212 OUTS (outf, "[");
2213 OUTS (outf, iregs (i));
2214 OUTS (outf, "--] = ");
2215 OUTS (outf, dregs (reg));
2216 }
2217 else if (aop == 1 && W == 1 && m == 1)
2218 {
2219 OUTS (outf, "W[");
2220 OUTS (outf, iregs (i));
2221 OUTS (outf, "--] = ");
2222 OUTS (outf, dregs_lo (reg));
2223 }
2224 else if (aop == 1 && W == 1 && m == 2)
2225 {
2226 OUTS (outf, "W[");
2227 OUTS (outf, iregs (i));
2228 OUTS (outf, "--] = ");
2229 OUTS (outf, dregs_hi (reg));
2230 }
2231 else if (aop == 2 && W == 1 && m == 0)
2232 {
2233 OUTS (outf, "[");
2234 OUTS (outf, iregs (i));
2235 OUTS (outf, "] = ");
2236 OUTS (outf, dregs (reg));
2237 }
2238 else if (aop == 2 && W == 1 && m == 1)
2239 {
2240 OUTS (outf, "W[");
2241 OUTS (outf, iregs (i));
2242 OUTS (outf, "] = ");
2243 OUTS (outf, dregs_lo (reg));
2244 }
2245 else if (aop == 2 && W == 1 && m == 2)
2246 {
2247 OUTS (outf, "W[");
2248 OUTS (outf, iregs (i));
2249 OUTS (outf, "] = ");
2250 OUTS (outf, dregs_hi (reg));
2251 }
2252 else if (aop == 3 && W == 0)
2253 {
2254 OUTS (outf, dregs (reg));
2255 OUTS (outf, " = [");
2256 OUTS (outf, iregs (i));
2257 OUTS (outf, " ++ ");
2258 OUTS (outf, mregs (m));
2259 OUTS (outf, "]");
2260 }
2261 else if (aop == 3 && W == 1)
2262 {
2263 OUTS (outf, "[");
2264 OUTS (outf, iregs (i));
2265 OUTS (outf, " ++ ");
2266 OUTS (outf, mregs (m));
2267 OUTS (outf, "] = ");
2268 OUTS (outf, dregs (reg));
2269 }
2270 else
2271 return 0;
2272
2273 return 2;
2274 }
2275
2276 static int
2277 decode_LDST_0 (TIword iw0, disassemble_info *outf)
2278 {
2279 /* LDST
2280 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2281 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2282 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2283 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2284 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2285 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2286 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2287 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2288 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2289
2290 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2291 {
2292 OUTS (outf, dregs (reg));
2293 OUTS (outf, " = [");
2294 OUTS (outf, pregs (ptr));
2295 OUTS (outf, "++]");
2296 }
2297 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2298 {
2299 OUTS (outf, pregs (reg));
2300 OUTS (outf, " = [");
2301 OUTS (outf, pregs (ptr));
2302 OUTS (outf, "++]");
2303 }
2304 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2305 {
2306 OUTS (outf, dregs (reg));
2307 OUTS (outf, " = W[");
2308 OUTS (outf, pregs (ptr));
2309 OUTS (outf, "++] (Z)");
2310 }
2311 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2312 {
2313 OUTS (outf, dregs (reg));
2314 OUTS (outf, " = W[");
2315 OUTS (outf, pregs (ptr));
2316 OUTS (outf, "++] (X)");
2317 }
2318 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2319 {
2320 OUTS (outf, dregs (reg));
2321 OUTS (outf, " = B[");
2322 OUTS (outf, pregs (ptr));
2323 OUTS (outf, "++] (Z)");
2324 }
2325 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2326 {
2327 OUTS (outf, dregs (reg));
2328 OUTS (outf, " = B[");
2329 OUTS (outf, pregs (ptr));
2330 OUTS (outf, "++] (X)");
2331 }
2332 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2333 {
2334 OUTS (outf, dregs (reg));
2335 OUTS (outf, " = [");
2336 OUTS (outf, pregs (ptr));
2337 OUTS (outf, "--]");
2338 }
2339 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2340 {
2341 OUTS (outf, pregs (reg));
2342 OUTS (outf, " = [");
2343 OUTS (outf, pregs (ptr));
2344 OUTS (outf, "--]");
2345 }
2346 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2347 {
2348 OUTS (outf, dregs (reg));
2349 OUTS (outf, " = W[");
2350 OUTS (outf, pregs (ptr));
2351 OUTS (outf, "--] (Z)");
2352 }
2353 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2354 {
2355 OUTS (outf, dregs (reg));
2356 OUTS (outf, " = W[");
2357 OUTS (outf, pregs (ptr));
2358 OUTS (outf, "--] (X)");
2359 }
2360 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2361 {
2362 OUTS (outf, dregs (reg));
2363 OUTS (outf, " = B[");
2364 OUTS (outf, pregs (ptr));
2365 OUTS (outf, "--] (Z)");
2366 }
2367 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2368 {
2369 OUTS (outf, dregs (reg));
2370 OUTS (outf, " = B[");
2371 OUTS (outf, pregs (ptr));
2372 OUTS (outf, "--] (X)");
2373 }
2374 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2375 {
2376 OUTS (outf, dregs (reg));
2377 OUTS (outf, " = [");
2378 OUTS (outf, pregs (ptr));
2379 OUTS (outf, "]");
2380 }
2381 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2382 {
2383 OUTS (outf, pregs (reg));
2384 OUTS (outf, " = [");
2385 OUTS (outf, pregs (ptr));
2386 OUTS (outf, "]");
2387 }
2388 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2389 {
2390 OUTS (outf, dregs (reg));
2391 OUTS (outf, " = W[");
2392 OUTS (outf, pregs (ptr));
2393 OUTS (outf, "] (Z)");
2394 }
2395 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2396 {
2397 OUTS (outf, dregs (reg));
2398 OUTS (outf, " = W[");
2399 OUTS (outf, pregs (ptr));
2400 OUTS (outf, "] (X)");
2401 }
2402 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2403 {
2404 OUTS (outf, dregs (reg));
2405 OUTS (outf, " = B[");
2406 OUTS (outf, pregs (ptr));
2407 OUTS (outf, "] (Z)");
2408 }
2409 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2410 {
2411 OUTS (outf, dregs (reg));
2412 OUTS (outf, " = B[");
2413 OUTS (outf, pregs (ptr));
2414 OUTS (outf, "] (X)");
2415 }
2416 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2417 {
2418 OUTS (outf, "[");
2419 OUTS (outf, pregs (ptr));
2420 OUTS (outf, "++] = ");
2421 OUTS (outf, dregs (reg));
2422 }
2423 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2424 {
2425 OUTS (outf, "[");
2426 OUTS (outf, pregs (ptr));
2427 OUTS (outf, "++] = ");
2428 OUTS (outf, pregs (reg));
2429 }
2430 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2431 {
2432 OUTS (outf, "W[");
2433 OUTS (outf, pregs (ptr));
2434 OUTS (outf, "++] = ");
2435 OUTS (outf, dregs (reg));
2436 }
2437 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2438 {
2439 OUTS (outf, "B[");
2440 OUTS (outf, pregs (ptr));
2441 OUTS (outf, "++] = ");
2442 OUTS (outf, dregs (reg));
2443 }
2444 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2445 {
2446 OUTS (outf, "[");
2447 OUTS (outf, pregs (ptr));
2448 OUTS (outf, "--] = ");
2449 OUTS (outf, dregs (reg));
2450 }
2451 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2452 {
2453 OUTS (outf, "[");
2454 OUTS (outf, pregs (ptr));
2455 OUTS (outf, "--] = ");
2456 OUTS (outf, pregs (reg));
2457 }
2458 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2459 {
2460 OUTS (outf, "W[");
2461 OUTS (outf, pregs (ptr));
2462 OUTS (outf, "--] = ");
2463 OUTS (outf, dregs (reg));
2464 }
2465 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2466 {
2467 OUTS (outf, "B[");
2468 OUTS (outf, pregs (ptr));
2469 OUTS (outf, "--] = ");
2470 OUTS (outf, dregs (reg));
2471 }
2472 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2473 {
2474 OUTS (outf, "[");
2475 OUTS (outf, pregs (ptr));
2476 OUTS (outf, "] = ");
2477 OUTS (outf, dregs (reg));
2478 }
2479 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2480 {
2481 OUTS (outf, "[");
2482 OUTS (outf, pregs (ptr));
2483 OUTS (outf, "] = ");
2484 OUTS (outf, pregs (reg));
2485 }
2486 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2487 {
2488 OUTS (outf, "W[");
2489 OUTS (outf, pregs (ptr));
2490 OUTS (outf, "] = ");
2491 OUTS (outf, dregs (reg));
2492 }
2493 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2494 {
2495 OUTS (outf, "B[");
2496 OUTS (outf, pregs (ptr));
2497 OUTS (outf, "] = ");
2498 OUTS (outf, dregs (reg));
2499 }
2500 else
2501 return 0;
2502
2503 return 2;
2504 }
2505
2506 static int
2507 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2508 {
2509 /* LDSTiiFP
2510 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2511 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2512 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2513 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2514 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2515 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2516
2517 if (W == 0)
2518 {
2519 OUTS (outf, dpregs (reg));
2520 OUTS (outf, " = [FP ");
2521 OUTS (outf, negimm5s4 (offset));
2522 OUTS (outf, "]");
2523 }
2524 else if (W == 1)
2525 {
2526 OUTS (outf, "[FP ");
2527 OUTS (outf, negimm5s4 (offset));
2528 OUTS (outf, "] = ");
2529 OUTS (outf, dpregs (reg));
2530 }
2531 else
2532 return 0;
2533
2534 return 2;
2535 }
2536
2537 static int
2538 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2539 {
2540 /* LDSTii
2541 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2542 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2543 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2544 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2545 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2546 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2547 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2548 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2549
2550 if (W == 0 && op == 0)
2551 {
2552 OUTS (outf, dregs (reg));
2553 OUTS (outf, " = [");
2554 OUTS (outf, pregs (ptr));
2555 OUTS (outf, " + ");
2556 OUTS (outf, uimm4s4 (offset));
2557 OUTS (outf, "]");
2558 }
2559 else if (W == 0 && op == 1)
2560 {
2561 OUTS (outf, dregs (reg));
2562 OUTS (outf, " = W[");
2563 OUTS (outf, pregs (ptr));
2564 OUTS (outf, " + ");
2565 OUTS (outf, uimm4s2 (offset));
2566 OUTS (outf, "] (Z)");
2567 }
2568 else if (W == 0 && op == 2)
2569 {
2570 OUTS (outf, dregs (reg));
2571 OUTS (outf, " = W[");
2572 OUTS (outf, pregs (ptr));
2573 OUTS (outf, " + ");
2574 OUTS (outf, uimm4s2 (offset));
2575 OUTS (outf, "] (X)");
2576 }
2577 else if (W == 0 && op == 3)
2578 {
2579 OUTS (outf, pregs (reg));
2580 OUTS (outf, " = [");
2581 OUTS (outf, pregs (ptr));
2582 OUTS (outf, " + ");
2583 OUTS (outf, uimm4s4 (offset));
2584 OUTS (outf, "]");
2585 }
2586 else if (W == 1 && op == 0)
2587 {
2588 OUTS (outf, "[");
2589 OUTS (outf, pregs (ptr));
2590 OUTS (outf, " + ");
2591 OUTS (outf, uimm4s4 (offset));
2592 OUTS (outf, "] = ");
2593 OUTS (outf, dregs (reg));
2594 }
2595 else if (W == 1 && op == 1)
2596 {
2597 OUTS (outf, "W[");
2598 OUTS (outf, pregs (ptr));
2599 OUTS (outf, " + ");
2600 OUTS (outf, uimm4s2 (offset));
2601 OUTS (outf, "] = ");
2602 OUTS (outf, dregs (reg));
2603 }
2604 else if (W == 1 && op == 3)
2605 {
2606 OUTS (outf, "[");
2607 OUTS (outf, pregs (ptr));
2608 OUTS (outf, " + ");
2609 OUTS (outf, uimm4s4 (offset));
2610 OUTS (outf, "] = ");
2611 OUTS (outf, pregs (reg));
2612 }
2613 else
2614 return 0;
2615
2616 return 2;
2617 }
2618
2619 static int
2620 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2621 {
2622 /* LoopSetup
2623 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2624 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2625 |.reg...........| - | - |.eoffset...............................|
2626 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2627 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2628 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2629 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2630 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2631 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2632
2633 if (parallel)
2634 return 0;
2635
2636 if (rop == 0)
2637 {
2638 OUTS (outf, "LSETUP");
2639 OUTS (outf, "(0x");
2640 OUTS (outf, pcrel4 (soffset));
2641 OUTS (outf, ", 0x");
2642 OUTS (outf, lppcrel10 (eoffset));
2643 OUTS (outf, ") ");
2644 OUTS (outf, counters (c));
2645 }
2646 else if (rop == 1)
2647 {
2648 OUTS (outf, "LSETUP");
2649 OUTS (outf, "(0x");
2650 OUTS (outf, pcrel4 (soffset));
2651 OUTS (outf, ", 0x");
2652 OUTS (outf, lppcrel10 (eoffset));
2653 OUTS (outf, ") ");
2654 OUTS (outf, counters (c));
2655 OUTS (outf, " = ");
2656 OUTS (outf, pregs (reg));
2657 }
2658 else if (rop == 3)
2659 {
2660 OUTS (outf, "LSETUP");
2661 OUTS (outf, "(0x");
2662 OUTS (outf, pcrel4 (soffset));
2663 OUTS (outf, ", 0x");
2664 OUTS (outf, lppcrel10 (eoffset));
2665 OUTS (outf, ") ");
2666 OUTS (outf, counters (c));
2667 OUTS (outf, " = ");
2668 OUTS (outf, pregs (reg));
2669 OUTS (outf, " >> 0x1");
2670 }
2671 else
2672 return 0;
2673
2674 return 4;
2675 }
2676
2677 static int
2678 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2679 {
2680 /* LDIMMhalf
2681 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2682 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2683 |.hword.........................................................|
2684 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2685 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2686 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2687 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2688 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2689 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2690 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2691
2692 bu32 *pval = get_allreg (grp, reg);
2693
2694 if (parallel)
2695 return 0;
2696
2697 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2698 to combine them, so it prints out the right values.
2699 Here we keep track of the registers. */
2700 if (H == 0 && S == 1 && Z == 0)
2701 {
2702 /* regs = imm16 (x) */
2703 *pval = imm16_val (hword);
2704 if (hword & 0x8000)
2705 *pval |= 0xFFFF0000;
2706 else
2707 *pval &= 0xFFFF;
2708 }
2709 else if (H == 0 && S == 0 && Z == 1)
2710 {
2711 /* regs = luimm16 (Z) */
2712 *pval = luimm16_val (hword);
2713 *pval &= 0xFFFF;
2714 }
2715 else if (H == 0 && S == 0 && Z == 0)
2716 {
2717 /* regs_lo = luimm16 */
2718 *pval &= 0xFFFF0000;
2719 *pval |= luimm16_val (hword);
2720 }
2721 else if (H == 1 && S == 0 && Z == 0)
2722 {
2723 /* regs_hi = huimm16 */
2724 *pval &= 0xFFFF;
2725 *pval |= luimm16_val (hword) << 16;
2726 }
2727
2728 /* Here we do the disassembly */
2729 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2730 {
2731 OUTS (outf, dregs_lo (reg));
2732 OUTS (outf, " = ");
2733 OUTS (outf, uimm16 (hword));
2734 }
2735 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2736 {
2737 OUTS (outf, dregs_hi (reg));
2738 OUTS (outf, " = ");
2739 OUTS (outf, uimm16 (hword));
2740 }
2741 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2742 {
2743 OUTS (outf, dregs (reg));
2744 OUTS (outf, " = ");
2745 OUTS (outf, imm16 (hword));
2746 OUTS (outf, " (X)");
2747 }
2748 else if (H == 0 && S == 1 && Z == 0)
2749 {
2750 OUTS (outf, regs (reg, grp));
2751 OUTS (outf, " = ");
2752 OUTS (outf, imm16 (hword));
2753 OUTS (outf, " (X)");
2754 }
2755 else if (H == 0 && S == 0 && Z == 1)
2756 {
2757 OUTS (outf, regs (reg, grp));
2758 OUTS (outf, " = ");
2759 OUTS (outf, uimm16 (hword));
2760 OUTS (outf, " (Z)");
2761 }
2762 else if (H == 0 && S == 0 && Z == 0)
2763 {
2764 OUTS (outf, regs_lo (reg, grp));
2765 OUTS (outf, " = ");
2766 OUTS (outf, uimm16 (hword));
2767 }
2768 else if (H == 1 && S == 0 && Z == 0)
2769 {
2770 OUTS (outf, regs_hi (reg, grp));
2771 OUTS (outf, " = ");
2772 OUTS (outf, uimm16 (hword));
2773 }
2774 else
2775 return 0;
2776
2777 /* And we print out the 32-bit value if it is a pointer. */
2778 if (S == 0 && Z == 0)
2779 {
2780 OUTS (outf, ";\t\t/* (");
2781 OUTS (outf, imm16d (hword));
2782 OUTS (outf, ")\t");
2783
2784 /* If it is an MMR, don't print the symbol. */
2785 if (*pval < 0xFFC00000 && grp == 1)
2786 {
2787 OUTS (outf, regs (reg, grp));
2788 OUTS (outf, "=0x");
2789 OUTS (outf, huimm32e (*pval));
2790 }
2791 else
2792 {
2793 OUTS (outf, regs (reg, grp));
2794 OUTS (outf, "=0x");
2795 OUTS (outf, huimm32e (*pval));
2796 OUTS (outf, "(");
2797 OUTS (outf, imm32 (*pval));
2798 OUTS (outf, ")");
2799 }
2800
2801 OUTS (outf, " */");
2802 comment = 1;
2803 }
2804 if (S == 1 || Z == 1)
2805 {
2806 OUTS (outf, ";\t\t/*\t\t");
2807 OUTS (outf, regs (reg, grp));
2808 OUTS (outf, "=0x");
2809 OUTS (outf, huimm32e (*pval));
2810 OUTS (outf, "(");
2811 OUTS (outf, imm32 (*pval));
2812 OUTS (outf, ") */");
2813 comment = 1;
2814 }
2815 return 4;
2816 }
2817
2818 static int
2819 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2820 {
2821 /* CALLa
2822 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2823 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2824 |.lsw...........................................................|
2825 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2826 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2827 int lsw = ((iw1 >> 0) & 0xffff);
2828 int msw = ((iw0 >> 0) & 0xff);
2829
2830 if (parallel)
2831 return 0;
2832
2833 if (S == 1)
2834 OUTS (outf, "CALL 0x");
2835 else if (S == 0)
2836 OUTS (outf, "JUMP.L 0x");
2837 else
2838 return 0;
2839
2840 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2841 return 4;
2842 }
2843
2844 static int
2845 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2846 {
2847 /* LDSTidxI
2848 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2849 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2850 |.offset........................................................|
2851 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2852 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2853 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2854 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2855 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2856 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2857 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2858
2859 if (W == 0 && sz == 0 && Z == 0)
2860 {
2861 OUTS (outf, dregs (reg));
2862 OUTS (outf, " = [");
2863 OUTS (outf, pregs (ptr));
2864 OUTS (outf, " + ");
2865 OUTS (outf, imm16s4 (offset));
2866 OUTS (outf, "]");
2867 }
2868 else if (W == 0 && sz == 0 && Z == 1)
2869 {
2870 OUTS (outf, pregs (reg));
2871 OUTS (outf, " = [");
2872 OUTS (outf, pregs (ptr));
2873 OUTS (outf, " + ");
2874 OUTS (outf, imm16s4 (offset));
2875 OUTS (outf, "]");
2876 }
2877 else if (W == 0 && sz == 1 && Z == 0)
2878 {
2879 OUTS (outf, dregs (reg));
2880 OUTS (outf, " = W[");
2881 OUTS (outf, pregs (ptr));
2882 OUTS (outf, " + ");
2883 OUTS (outf, imm16s2 (offset));
2884 OUTS (outf, "] (Z)");
2885 }
2886 else if (W == 0 && sz == 1 && Z == 1)
2887 {
2888 OUTS (outf, dregs (reg));
2889 OUTS (outf, " = W[");
2890 OUTS (outf, pregs (ptr));
2891 OUTS (outf, " + ");
2892 OUTS (outf, imm16s2 (offset));
2893 OUTS (outf, "] (X)");
2894 }
2895 else if (W == 0 && sz == 2 && Z == 0)
2896 {
2897 OUTS (outf, dregs (reg));
2898 OUTS (outf, " = B[");
2899 OUTS (outf, pregs (ptr));
2900 OUTS (outf, " + ");
2901 OUTS (outf, imm16 (offset));
2902 OUTS (outf, "] (Z)");
2903 }
2904 else if (W == 0 && sz == 2 && Z == 1)
2905 {
2906 OUTS (outf, dregs (reg));
2907 OUTS (outf, " = B[");
2908 OUTS (outf, pregs (ptr));
2909 OUTS (outf, " + ");
2910 OUTS (outf, imm16 (offset));
2911 OUTS (outf, "] (X)");
2912 }
2913 else if (W == 1 && sz == 0 && Z == 0)
2914 {
2915 OUTS (outf, "[");
2916 OUTS (outf, pregs (ptr));
2917 OUTS (outf, " + ");
2918 OUTS (outf, imm16s4 (offset));
2919 OUTS (outf, "] = ");
2920 OUTS (outf, dregs (reg));
2921 }
2922 else if (W == 1 && sz == 0 && Z == 1)
2923 {
2924 OUTS (outf, "[");
2925 OUTS (outf, pregs (ptr));
2926 OUTS (outf, " + ");
2927 OUTS (outf, imm16s4 (offset));
2928 OUTS (outf, "] = ");
2929 OUTS (outf, pregs (reg));
2930 }
2931 else if (W == 1 && sz == 1 && Z == 0)
2932 {
2933 OUTS (outf, "W[");
2934 OUTS (outf, pregs (ptr));
2935 OUTS (outf, " + ");
2936 OUTS (outf, imm16s2 (offset));
2937 OUTS (outf, "] = ");
2938 OUTS (outf, dregs (reg));
2939 }
2940 else if (W == 1 && sz == 2 && Z == 0)
2941 {
2942 OUTS (outf, "B[");
2943 OUTS (outf, pregs (ptr));
2944 OUTS (outf, " + ");
2945 OUTS (outf, imm16 (offset));
2946 OUTS (outf, "] = ");
2947 OUTS (outf, dregs (reg));
2948 }
2949 else
2950 return 0;
2951
2952 return 4;
2953 }
2954
2955 static int
2956 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2957 {
2958 /* linkage
2959 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2960 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2961 |.framesize.....................................................|
2962 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2963 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2964 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2965
2966 if (parallel)
2967 return 0;
2968
2969 if (R == 0)
2970 {
2971 OUTS (outf, "LINK ");
2972 OUTS (outf, uimm16s4 (framesize));
2973 OUTS (outf, ";\t\t/* (");
2974 OUTS (outf, uimm16s4d (framesize));
2975 OUTS (outf, ") */");
2976 comment = 1;
2977 }
2978 else if (R == 1)
2979 OUTS (outf, "UNLINK");
2980 else
2981 return 0;
2982
2983 return 4;
2984 }
2985
2986 static int
2987 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2988 {
2989 /* dsp32mac
2990 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2991 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2992 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2993 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2994 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2995 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2996 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2997 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2998 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2999 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3000 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3001 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3002 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3003 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3004 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3005 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
3006 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3007 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3008
3009 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
3010 return 0;
3011
3012 if (op1 == 3 && MM)
3013 return 0;
3014
3015 if ((w1 || w0) && mmod == M_W32)
3016 return 0;
3017
3018 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
3019 return 0;
3020
3021 if (w1 == 1 || op1 != 3)
3022 {
3023 if (w1)
3024 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3025
3026 if (op1 == 3)
3027 OUTS (outf, " = A1");
3028 else
3029 {
3030 if (w1)
3031 OUTS (outf, " = (");
3032 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
3033 if (w1)
3034 OUTS (outf, ")");
3035 }
3036
3037 if (w0 == 1 || op0 != 3)
3038 {
3039 if (MM)
3040 OUTS (outf, " (M)");
3041 MM = 0;
3042 OUTS (outf, ", ");
3043 }
3044 }
3045
3046 if (w0 == 1 || op0 != 3)
3047 {
3048 if (w0)
3049 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3050
3051 if (op0 == 3)
3052 OUTS (outf, " = A0");
3053 else
3054 {
3055 if (w0)
3056 OUTS (outf, " = (");
3057 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3058 if (w0)
3059 OUTS (outf, ")");
3060 }
3061 }
3062
3063 decode_optmode (mmod, MM, outf);
3064
3065 return 4;
3066 }
3067
3068 static int
3069 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3070 {
3071 /* dsp32mult
3072 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3073 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3074 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3075 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3076 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3077 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3078 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
3079 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
3080 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3081 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3082 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3083 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3084 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3085 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3086 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3087 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3088
3089 if (w1 == 0 && w0 == 0)
3090 return 0;
3091
3092 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3093 return 0;
3094
3095 if (w1)
3096 {
3097 OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
3098 OUTS (outf, " = ");
3099 decode_multfunc (h01, h11, src0, src1, outf);
3100
3101 if (w0)
3102 {
3103 if (MM)
3104 OUTS (outf, " (M)");
3105 MM = 0;
3106 OUTS (outf, ", ");
3107 }
3108 }
3109
3110 if (w0)
3111 {
3112 OUTS (outf, dregs (dst));
3113 OUTS (outf, " = ");
3114 decode_multfunc (h00, h10, src0, src1, outf);
3115 }
3116
3117 decode_optmode (mmod, MM, outf);
3118 return 4;
3119 }
3120
3121 static int
3122 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3123 {
3124 /* dsp32alu
3125 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3126 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3127 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3128 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3129 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3130 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3131 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3132 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3133 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3134 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3135 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3136 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3137 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3138
3139 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3140 {
3141 OUTS (outf, "A0.L = ");
3142 OUTS (outf, dregs_lo (src0));
3143 }
3144 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3145 {
3146 OUTS (outf, "A1.H = ");
3147 OUTS (outf, dregs_hi (src0));
3148 }
3149 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3150 {
3151 OUTS (outf, "A1.L = ");
3152 OUTS (outf, dregs_lo (src0));
3153 }
3154 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3155 {
3156 OUTS (outf, "A0.H = ");
3157 OUTS (outf, dregs_hi (src0));
3158 }
3159 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3160 {
3161 OUTS (outf, dregs_hi (dst0));
3162 OUTS (outf, " = ");
3163 OUTS (outf, dregs (src0));
3164 OUTS (outf, " - ");
3165 OUTS (outf, dregs (src1));
3166 OUTS (outf, " (RND20)");
3167 }
3168 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3169 {
3170 OUTS (outf, dregs_hi (dst0));
3171 OUTS (outf, " = ");
3172 OUTS (outf, dregs (src0));
3173 OUTS (outf, " + ");
3174 OUTS (outf, dregs (src1));
3175 OUTS (outf, " (RND20)");
3176 }
3177 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3178 {
3179 OUTS (outf, dregs_lo (dst0));
3180 OUTS (outf, " = ");
3181 OUTS (outf, dregs (src0));
3182 OUTS (outf, " - ");
3183 OUTS (outf, dregs (src1));
3184 OUTS (outf, " (RND12)");
3185 }
3186 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3187 {
3188 OUTS (outf, dregs_lo (dst0));
3189 OUTS (outf, " = ");
3190 OUTS (outf, dregs (src0));
3191 OUTS (outf, " + ");
3192 OUTS (outf, dregs (src1));
3193 OUTS (outf, " (RND12)");
3194 }
3195 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3196 {
3197 OUTS (outf, dregs_lo (dst0));
3198 OUTS (outf, " = ");
3199 OUTS (outf, dregs (src0));
3200 OUTS (outf, " - ");
3201 OUTS (outf, dregs (src1));
3202 OUTS (outf, " (RND20)");
3203 }
3204 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3205 {
3206 OUTS (outf, dregs_hi (dst0));
3207 OUTS (outf, " = ");
3208 OUTS (outf, dregs (src0));
3209 OUTS (outf, " + ");
3210 OUTS (outf, dregs (src1));
3211 OUTS (outf, " (RND12)");
3212 }
3213 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3214 {
3215 OUTS (outf, dregs_lo (dst0));
3216 OUTS (outf, " = ");
3217 OUTS (outf, dregs (src0));
3218 OUTS (outf, " + ");
3219 OUTS (outf, dregs (src1));
3220 OUTS (outf, " (RND20)");
3221 }
3222 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3223 {
3224 OUTS (outf, dregs_hi (dst0));
3225 OUTS (outf, " = ");
3226 OUTS (outf, dregs (src0));
3227 OUTS (outf, " - ");
3228 OUTS (outf, dregs (src1));
3229 OUTS (outf, " (RND12)");
3230 }
3231 else if (HL == 1 && aop == 0 && aopcde == 2)
3232 {
3233 OUTS (outf, dregs_hi (dst0));
3234 OUTS (outf, " = ");
3235 OUTS (outf, dregs_lo (src0));
3236 OUTS (outf, " + ");
3237 OUTS (outf, dregs_lo (src1));
3238 amod1 (s, x, outf);
3239 }
3240 else if (HL == 1 && aop == 1 && aopcde == 2)
3241 {
3242 OUTS (outf, dregs_hi (dst0));
3243 OUTS (outf, " = ");
3244 OUTS (outf, dregs_lo (src0));
3245 OUTS (outf, " + ");
3246 OUTS (outf, dregs_hi (src1));
3247 amod1 (s, x, outf);
3248 }
3249 else if (HL == 1 && aop == 2 && aopcde == 2)
3250 {
3251 OUTS (outf, dregs_hi (dst0));
3252 OUTS (outf, " = ");
3253 OUTS (outf, dregs_hi (src0));
3254 OUTS (outf, " + ");
3255 OUTS (outf, dregs_lo (src1));
3256 amod1 (s, x, outf);
3257 }
3258 else if (HL == 1 && aop == 3 && aopcde == 2)
3259 {
3260 OUTS (outf, dregs_hi (dst0));
3261 OUTS (outf, " = ");
3262 OUTS (outf, dregs_hi (src0));
3263 OUTS (outf, " + ");
3264 OUTS (outf, dregs_hi (src1));
3265 amod1 (s, x, outf);
3266 }
3267 else if (HL == 0 && aop == 0 && aopcde == 3)
3268 {
3269 OUTS (outf, dregs_lo (dst0));
3270 OUTS (outf, " = ");
3271 OUTS (outf, dregs_lo (src0));
3272 OUTS (outf, " - ");
3273 OUTS (outf, dregs_lo (src1));
3274 amod1 (s, x, outf);
3275 }
3276 else if (HL == 0 && aop == 1 && aopcde == 3)
3277 {
3278 OUTS (outf, dregs_lo (dst0));
3279 OUTS (outf, " = ");
3280 OUTS (outf, dregs_lo (src0));
3281 OUTS (outf, " - ");
3282 OUTS (outf, dregs_hi (src1));
3283 amod1 (s, x, outf);
3284 }
3285 else if (HL == 0 && aop == 3 && aopcde == 2)
3286 {
3287 OUTS (outf, dregs_lo (dst0));
3288 OUTS (outf, " = ");
3289 OUTS (outf, dregs_hi (src0));
3290 OUTS (outf, " + ");
3291 OUTS (outf, dregs_hi (src1));
3292 amod1 (s, x, outf);
3293 }
3294 else if (HL == 1 && aop == 0 && aopcde == 3)
3295 {
3296 OUTS (outf, dregs_hi (dst0));
3297 OUTS (outf, " = ");
3298 OUTS (outf, dregs_lo (src0));
3299 OUTS (outf, " - ");
3300 OUTS (outf, dregs_lo (src1));
3301 amod1 (s, x, outf);
3302 }
3303 else if (HL == 1 && aop == 1 && aopcde == 3)
3304 {
3305 OUTS (outf, dregs_hi (dst0));
3306 OUTS (outf, " = ");
3307 OUTS (outf, dregs_lo (src0));
3308 OUTS (outf, " - ");
3309 OUTS (outf, dregs_hi (src1));
3310 amod1 (s, x, outf);
3311 }
3312 else if (HL == 1 && aop == 2 && aopcde == 3)
3313 {
3314 OUTS (outf, dregs_hi (dst0));
3315 OUTS (outf, " = ");
3316 OUTS (outf, dregs_hi (src0));
3317 OUTS (outf, " - ");
3318 OUTS (outf, dregs_lo (src1));
3319 amod1 (s, x, outf);
3320 }
3321 else if (HL == 1 && aop == 3 && aopcde == 3)
3322 {
3323 OUTS (outf, dregs_hi (dst0));
3324 OUTS (outf, " = ");
3325 OUTS (outf, dregs_hi (src0));
3326 OUTS (outf, " - ");
3327 OUTS (outf, dregs_hi (src1));
3328 amod1 (s, x, outf);
3329 }
3330 else if (HL == 0 && aop == 2 && aopcde == 2)
3331 {
3332 OUTS (outf, dregs_lo (dst0));
3333 OUTS (outf, " = ");
3334 OUTS (outf, dregs_hi (src0));
3335 OUTS (outf, " + ");
3336 OUTS (outf, dregs_lo (src1));
3337 amod1 (s, x, outf);
3338 }
3339 else if (HL == 0 && aop == 1 && aopcde == 2)
3340 {
3341 OUTS (outf, dregs_lo (dst0));
3342 OUTS (outf, " = ");
3343 OUTS (outf, dregs_lo (src0));
3344 OUTS (outf, " + ");
3345 OUTS (outf, dregs_hi (src1));
3346 amod1 (s, x, outf);
3347 }
3348 else if (HL == 0 && aop == 2 && aopcde == 3)
3349 {
3350 OUTS (outf, dregs_lo (dst0));
3351 OUTS (outf, " = ");
3352 OUTS (outf, dregs_hi (src0));
3353 OUTS (outf, " - ");
3354 OUTS (outf, dregs_lo (src1));
3355 amod1 (s, x, outf);
3356 }
3357 else if (HL == 0 && aop == 3 && aopcde == 3)
3358 {
3359 OUTS (outf, dregs_lo (dst0));
3360 OUTS (outf, " = ");
3361 OUTS (outf, dregs_hi (src0));
3362 OUTS (outf, " - ");
3363 OUTS (outf, dregs_hi (src1));
3364 amod1 (s, x, outf);
3365 }
3366 else if (HL == 0 && aop == 0 && aopcde == 2)
3367 {
3368 OUTS (outf, dregs_lo (dst0));
3369 OUTS (outf, " = ");
3370 OUTS (outf, dregs_lo (src0));
3371 OUTS (outf, " + ");
3372 OUTS (outf, dregs_lo (src1));
3373 amod1 (s, x, outf);
3374 }
3375 else if (aop == 0 && aopcde == 9 && s == 1)
3376 {
3377 OUTS (outf, "A0 = ");
3378 OUTS (outf, dregs (src0));
3379 }
3380 else if (aop == 3 && aopcde == 11 && s == 0)
3381 OUTS (outf, "A0 -= A1");
3382
3383 else if (aop == 3 && aopcde == 11 && s == 1)
3384 OUTS (outf, "A0 -= A1 (W32)");
3385
3386 else if (aop == 3 && aopcde == 22 && HL == 1)
3387 {
3388 OUTS (outf, dregs (dst0));
3389 OUTS (outf, " = BYTEOP2M (");
3390 OUTS (outf, dregs (src0 + 1));
3391 OUTS (outf, ":");
3392 OUTS (outf, imm5d (src0));
3393 OUTS (outf, ", ");
3394 OUTS (outf, dregs (src1 + 1));
3395 OUTS (outf, ":");
3396 OUTS (outf, imm5d (src1));
3397 OUTS (outf, ") (TH");
3398 if (s == 1)
3399 OUTS (outf, ", R)");
3400 else
3401 OUTS (outf, ")");
3402 }
3403 else if (aop == 3 && aopcde == 22 && HL == 0)
3404 {
3405 OUTS (outf, dregs (dst0));
3406 OUTS (outf, " = BYTEOP2M (");
3407 OUTS (outf, dregs (src0 + 1));
3408 OUTS (outf, ":");
3409 OUTS (outf, imm5d (src0));
3410 OUTS (outf, ", ");
3411 OUTS (outf, dregs (src1 + 1));
3412 OUTS (outf, ":");
3413 OUTS (outf, imm5d (src1));
3414 OUTS (outf, ") (TL");
3415 if (s == 1)
3416 OUTS (outf, ", R)");
3417 else
3418 OUTS (outf, ")");
3419 }
3420 else if (aop == 2 && aopcde == 22 && HL == 1)
3421 {
3422 OUTS (outf, dregs (dst0));
3423 OUTS (outf, " = BYTEOP2M (");
3424 OUTS (outf, dregs (src0 + 1));
3425 OUTS (outf, ":");
3426 OUTS (outf, imm5d (src0));
3427 OUTS (outf, ", ");
3428 OUTS (outf, dregs (src1 + 1));
3429 OUTS (outf, ":");
3430 OUTS (outf, imm5d (src1));
3431 OUTS (outf, ") (RNDH");
3432 if (s == 1)
3433 OUTS (outf, ", R)");
3434 else
3435 OUTS (outf, ")");
3436 }
3437 else if (aop == 2 && aopcde == 22 && HL == 0)
3438 {
3439 OUTS (outf, dregs (dst0));
3440 OUTS (outf, " = BYTEOP2M (");
3441 OUTS (outf, dregs (src0 + 1));
3442 OUTS (outf, ":");
3443 OUTS (outf, imm5d (src0));
3444 OUTS (outf, ", ");
3445 OUTS (outf, dregs (src1 + 1));
3446 OUTS (outf, ":");
3447 OUTS (outf, imm5d (src1));
3448 OUTS (outf, ") (RNDL");
3449 if (s == 1)
3450 OUTS (outf, ", R)");
3451 else
3452 OUTS (outf, ")");
3453 }
3454 else if (aop == 1 && aopcde == 22 && HL == 1)
3455 {
3456 OUTS (outf, dregs (dst0));
3457 OUTS (outf, " = BYTEOP2P (");
3458 OUTS (outf, dregs (src0 + 1));
3459 OUTS (outf, ":");
3460 OUTS (outf, imm5d (src0));
3461 OUTS (outf, ", ");
3462 OUTS (outf, dregs (src1 + 1));
3463 OUTS (outf, ":");
3464 OUTS (outf, imm5d (src1));
3465 OUTS (outf, ") (TH");
3466 if (s == 1)
3467 OUTS (outf, ", R)");
3468 else
3469 OUTS (outf, ")");
3470 }
3471 else if (aop == 1 && aopcde == 22 && HL == 0)
3472 {
3473 OUTS (outf, dregs (dst0));
3474 OUTS (outf, " = BYTEOP2P (");
3475 OUTS (outf, dregs (src0 + 1));
3476 OUTS (outf, ":");
3477 OUTS (outf, imm5d (src0));
3478 OUTS (outf, ", ");
3479 OUTS (outf, dregs (src1 + 1));
3480 OUTS (outf, ":");
3481 OUTS (outf, imm5d (src1));
3482 OUTS (outf, ") (TL");
3483 if (s == 1)
3484 OUTS (outf, ", R)");
3485 else
3486 OUTS (outf, ")");
3487 }
3488 else if (aop == 0 && aopcde == 22 && HL == 1)
3489 {
3490 OUTS (outf, dregs (dst0));
3491 OUTS (outf, " = BYTEOP2P (");
3492 OUTS (outf, dregs (src0 + 1));
3493 OUTS (outf, ":");
3494 OUTS (outf, imm5d (src0));
3495 OUTS (outf, ", ");
3496 OUTS (outf, dregs (src1 + 1));
3497 OUTS (outf, ":");
3498 OUTS (outf, imm5d (src1));
3499 OUTS (outf, ") (RNDH");
3500 if (s == 1)
3501 OUTS (outf, ", R)");
3502 else
3503 OUTS (outf, ")");
3504 }
3505 else if (aop == 0 && aopcde == 22 && HL == 0)
3506 {
3507 OUTS (outf, dregs (dst0));
3508 OUTS (outf, " = BYTEOP2P (");
3509 OUTS (outf, dregs (src0 + 1));
3510 OUTS (outf, ":");
3511 OUTS (outf, imm5d (src0));
3512 OUTS (outf, ", ");
3513 OUTS (outf, dregs (src1 + 1));
3514 OUTS (outf, ":");
3515 OUTS (outf, imm5d (src1));
3516 OUTS (outf, ") (RNDL");
3517 if (s == 1)
3518 OUTS (outf, ", R)");
3519 else
3520 OUTS (outf, ")");
3521 }
3522 else if (aop == 0 && s == 0 && aopcde == 8)
3523 OUTS (outf, "A0 = 0");
3524
3525 else if (aop == 0 && s == 1 && aopcde == 8)
3526 OUTS (outf, "A0 = A0 (S)");
3527
3528 else if (aop == 1 && s == 0 && aopcde == 8)
3529 OUTS (outf, "A1 = 0");
3530
3531 else if (aop == 1 && s == 1 && aopcde == 8)
3532 OUTS (outf, "A1 = A1 (S)");
3533
3534 else if (aop == 2 && s == 0 && aopcde == 8)
3535 OUTS (outf, "A1 = A0 = 0");
3536
3537 else if (aop == 2 && s == 1 && aopcde == 8)
3538 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3539
3540 else if (aop == 3 && s == 0 && aopcde == 8)
3541 OUTS (outf, "A0 = A1");
3542
3543 else if (aop == 3 && s == 1 && aopcde == 8)
3544 OUTS (outf, "A1 = A0");
3545
3546 else if (aop == 1 && aopcde == 9 && s == 0)
3547 {
3548 OUTS (outf, "A0.X = ");
3549 OUTS (outf, dregs_lo (src0));
3550 }
3551 else if (aop == 1 && HL == 0 && aopcde == 11)
3552 {
3553 OUTS (outf, dregs_lo (dst0));
3554 OUTS (outf, " = (A0 += A1)");
3555 }
3556 else if (aop == 3 && HL == 0 && aopcde == 16)
3557 OUTS (outf, "A1 = ABS A0, A0 = ABS A0");
3558
3559 else if (aop == 0 && aopcde == 23 && HL == 1)
3560 {
3561 OUTS (outf, dregs (dst0));
3562 OUTS (outf, " = BYTEOP3P (");
3563 OUTS (outf, dregs (src0 + 1));
3564 OUTS (outf, ":");
3565 OUTS (outf, imm5d (src0));
3566 OUTS (outf, ", ");
3567 OUTS (outf, dregs (src1 + 1));
3568 OUTS (outf, ":");
3569 OUTS (outf, imm5d (src1));
3570 OUTS (outf, ") (HI");
3571 if (s == 1)
3572 OUTS (outf, ", R)");
3573 else
3574 OUTS (outf, ")");
3575 }
3576 else if (aop == 3 && aopcde == 9 && s == 0)
3577 {
3578 OUTS (outf, "A1.X = ");
3579 OUTS (outf, dregs_lo (src0));
3580 }
3581 else if (aop == 1 && HL == 1 && aopcde == 16)
3582 OUTS (outf, "A1 = ABS A1");
3583
3584 else if (aop == 0 && HL == 1 && aopcde == 16)
3585 OUTS (outf, "A1 = ABS A0");
3586
3587 else if (aop == 2 && aopcde == 9 && s == 1)
3588 {
3589 OUTS (outf, "A1 = ");
3590 OUTS (outf, dregs (src0));
3591 }
3592 else if (HL == 0 && aop == 3 && aopcde == 12)
3593 {
3594 OUTS (outf, dregs_lo (dst0));
3595 OUTS (outf, " = ");
3596 OUTS (outf, dregs (src0));
3597 OUTS (outf, " (RND)");
3598 }
3599 else if (aop == 1 && HL == 0 && aopcde == 16)
3600 OUTS (outf, "A0 = ABS A1");
3601
3602 else if (aop == 0 && HL == 0 && aopcde == 16)
3603 OUTS (outf, "A0 = ABS A0");
3604
3605 else if (aop == 3 && HL == 0 && aopcde == 15)
3606 {
3607 OUTS (outf, dregs (dst0));
3608 OUTS (outf, " = -");
3609 OUTS (outf, dregs (src0));
3610 OUTS (outf, " (V)");
3611 }
3612 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3613 {
3614 OUTS (outf, dregs (dst0));
3615 OUTS (outf, " = -");
3616 OUTS (outf, dregs (src0));
3617 OUTS (outf, " (S)");
3618 }
3619 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3620 {
3621 OUTS (outf, dregs (dst0));
3622 OUTS (outf, " = -");
3623 OUTS (outf, dregs (src0));
3624 OUTS (outf, " (NS)");
3625 }
3626 else if (aop == 1 && HL == 1 && aopcde == 11)
3627 {
3628 OUTS (outf, dregs_hi (dst0));
3629 OUTS (outf, " = (A0 += A1)");
3630 }
3631 else if (aop == 2 && aopcde == 11 && s == 0)
3632 OUTS (outf, "A0 += A1");
3633
3634 else if (aop == 2 && aopcde == 11 && s == 1)
3635 OUTS (outf, "A0 += A1 (W32)");
3636
3637 else if (aop == 3 && HL == 0 && aopcde == 14)
3638 OUTS (outf, "A1 = -A1, A0 = -A0");
3639
3640 else if (HL == 1 && aop == 3 && aopcde == 12)
3641 {
3642 OUTS (outf, dregs_hi (dst0));
3643 OUTS (outf, " = ");
3644 OUTS (outf, dregs (src0));
3645 OUTS (outf, " (RND)");
3646 }
3647 else if (aop == 0 && aopcde == 23 && HL == 0)
3648 {
3649 OUTS (outf, dregs (dst0));
3650 OUTS (outf, " = BYTEOP3P (");
3651 OUTS (outf, dregs (src0 + 1));
3652 OUTS (outf, ":");
3653 OUTS (outf, imm5d (src0));
3654 OUTS (outf, ", ");
3655 OUTS (outf, dregs (src1 + 1));
3656 OUTS (outf, ":");
3657 OUTS (outf, imm5d (src1));
3658 OUTS (outf, ") (LO");
3659 if (s == 1)
3660 OUTS (outf, ", R)");
3661 else
3662 OUTS (outf, ")");
3663 }
3664 else if (aop == 0 && HL == 0 && aopcde == 14)
3665 OUTS (outf, "A0 = -A0");
3666
3667 else if (aop == 1 && HL == 0 && aopcde == 14)
3668 OUTS (outf, "A0 = -A1");
3669
3670 else if (aop == 0 && HL == 1 && aopcde == 14)
3671 OUTS (outf, "A1 = -A0");
3672
3673 else if (aop == 1 && HL == 1 && aopcde == 14)
3674 OUTS (outf, "A1 = -A1");
3675
3676 else if (aop == 0 && aopcde == 12)
3677 {
3678 OUTS (outf, dregs_hi (dst0));
3679 OUTS (outf, " = ");
3680 OUTS (outf, dregs_lo (dst0));
3681 OUTS (outf, " = SIGN (");
3682 OUTS (outf, dregs_hi (src0));
3683 OUTS (outf, ") * ");
3684 OUTS (outf, dregs_hi (src1));
3685 OUTS (outf, " + SIGN (");
3686 OUTS (outf, dregs_lo (src0));
3687 OUTS (outf, ") * ");
3688 OUTS (outf, dregs_lo (src1));
3689 }
3690 else if (aop == 2 && aopcde == 0)
3691 {
3692 OUTS (outf, dregs (dst0));
3693 OUTS (outf, " = ");
3694 OUTS (outf, dregs (src0));
3695 OUTS (outf, " -|+ ");
3696 OUTS (outf, dregs (src1));
3697 amod0 (s, x, outf);
3698 }
3699 else if (aop == 1 && aopcde == 12)
3700 {
3701 OUTS (outf, dregs (dst1));
3702 OUTS (outf, " = A1.L + A1.H, ");
3703 OUTS (outf, dregs (dst0));
3704 OUTS (outf, " = A0.L + A0.H");
3705 }
3706 else if (aop == 2 && aopcde == 4)
3707 {
3708 OUTS (outf, dregs (dst1));
3709 OUTS (outf, " = ");
3710 OUTS (outf, dregs (src0));
3711 OUTS (outf, " + ");
3712 OUTS (outf, dregs (src1));
3713 OUTS (outf, ", ");
3714 OUTS (outf, dregs (dst0));
3715 OUTS (outf, " = ");
3716 OUTS (outf, dregs (src0));
3717 OUTS (outf, " - ");
3718 OUTS (outf, dregs (src1));
3719 amod1 (s, x, outf);
3720 }
3721 else if (HL == 0 && aopcde == 1)
3722 {
3723 OUTS (outf, dregs (dst1));
3724 OUTS (outf, " = ");
3725 OUTS (outf, dregs (src0));
3726 OUTS (outf, " +|+ ");
3727 OUTS (outf, dregs (src1));
3728 OUTS (outf, ", ");
3729 OUTS (outf, dregs (dst0));
3730 OUTS (outf, " = ");
3731 OUTS (outf, dregs (src0));
3732 OUTS (outf, " -|- ");
3733 OUTS (outf, dregs (src1));
3734 amod0amod2 (s, x, aop, outf);
3735 }
3736 else if (aop == 0 && aopcde == 11)
3737 {
3738 OUTS (outf, dregs (dst0));
3739 OUTS (outf, " = (A0 += A1)");
3740 }
3741 else if (aop == 0 && aopcde == 10)
3742 {
3743 OUTS (outf, dregs_lo (dst0));
3744 OUTS (outf, " = A0.X");
3745 }
3746 else if (aop == 1 && aopcde == 10)
3747 {
3748 OUTS (outf, dregs_lo (dst0));
3749 OUTS (outf, " = A1.X");
3750 }
3751 else if (aop == 1 && aopcde == 0)
3752 {
3753 OUTS (outf, dregs (dst0));
3754 OUTS (outf, " = ");
3755 OUTS (outf, dregs (src0));
3756 OUTS (outf, " +|- ");
3757 OUTS (outf, dregs (src1));
3758 amod0 (s, x, outf);
3759 }
3760 else if (aop == 3 && aopcde == 0)
3761 {
3762 OUTS (outf, dregs (dst0));
3763 OUTS (outf, " = ");
3764 OUTS (outf, dregs (src0));
3765 OUTS (outf, " -|- ");
3766 OUTS (outf, dregs (src1));
3767 amod0 (s, x, outf);
3768 }
3769 else if (aop == 1 && aopcde == 4)
3770 {
3771 OUTS (outf, dregs (dst0));
3772 OUTS (outf, " = ");
3773 OUTS (outf, dregs (src0));
3774 OUTS (outf, " - ");
3775 OUTS (outf, dregs (src1));
3776 amod1 (s, x, outf);
3777 }
3778 else if (aop == 0 && aopcde == 17)
3779 {
3780 OUTS (outf, dregs (dst1));
3781 OUTS (outf, " = A1 + A0, ");
3782 OUTS (outf, dregs (dst0));
3783 OUTS (outf, " = A1 - A0");
3784 amod1 (s, x, outf);
3785 }
3786 else if (aop == 1 && aopcde == 17)
3787 {
3788 OUTS (outf, dregs (dst1));
3789 OUTS (outf, " = A0 + A1, ");
3790 OUTS (outf, dregs (dst0));
3791 OUTS (outf, " = A0 - A1");
3792 amod1 (s, x, outf);
3793 }
3794 else if (aop == 0 && aopcde == 18)
3795 {
3796 OUTS (outf, "SAA (");
3797 OUTS (outf, dregs (src0 + 1));
3798 OUTS (outf, ":");
3799 OUTS (outf, imm5d (src0));
3800 OUTS (outf, ", ");
3801 OUTS (outf, dregs (src1 + 1));
3802 OUTS (outf, ":");
3803 OUTS (outf, imm5d (src1));
3804 OUTS (outf, ")");
3805 aligndir (s, outf);
3806 }
3807 else if (aop == 3 && aopcde == 18)
3808 OUTS (outf, "DISALGNEXCPT");
3809
3810 else if (aop == 0 && aopcde == 20)
3811 {
3812 OUTS (outf, dregs (dst0));
3813 OUTS (outf, " = BYTEOP1P (");
3814 OUTS (outf, dregs (src0 + 1));
3815 OUTS (outf, ":");
3816 OUTS (outf, imm5d (src0));
3817 OUTS (outf, ", ");
3818 OUTS (outf, dregs (src1 + 1));
3819 OUTS (outf, ":");
3820 OUTS (outf, imm5d (src1));
3821 OUTS (outf, ")");
3822 aligndir (s, outf);
3823 }
3824 else if (aop == 1 && aopcde == 20)
3825 {
3826 OUTS (outf, dregs (dst0));
3827 OUTS (outf, " = BYTEOP1P (");
3828 OUTS (outf, dregs (src0 + 1));
3829 OUTS (outf, ":");
3830 OUTS (outf, imm5d (src0));
3831 OUTS (outf, ", ");
3832 OUTS (outf, dregs (src1 + 1));
3833 OUTS (outf, ":");
3834 OUTS (outf, imm5d (src1));
3835 OUTS (outf, ") (T");
3836 if (s == 1)
3837 OUTS (outf, ", R)");
3838 else
3839 OUTS (outf, ")");
3840 }
3841 else if (aop == 0 && aopcde == 21)
3842 {
3843 OUTS (outf, "(");
3844 OUTS (outf, dregs (dst1));
3845 OUTS (outf, ", ");
3846 OUTS (outf, dregs (dst0));
3847 OUTS (outf, ") = BYTEOP16P (");
3848 OUTS (outf, dregs (src0 + 1));
3849 OUTS (outf, ":");
3850 OUTS (outf, imm5d (src0));
3851 OUTS (outf, ", ");
3852 OUTS (outf, dregs (src1 + 1));
3853 OUTS (outf, ":");
3854 OUTS (outf, imm5d (src1));
3855 OUTS (outf, ")");
3856 aligndir (s, outf);
3857 }
3858 else if (aop == 1 && aopcde == 21)
3859 {
3860 OUTS (outf, "(");
3861 OUTS (outf, dregs (dst1));
3862 OUTS (outf, ", ");
3863 OUTS (outf, dregs (dst0));
3864 OUTS (outf, ") = BYTEOP16M (");
3865 OUTS (outf, dregs (src0 + 1));
3866 OUTS (outf, ":");
3867 OUTS (outf, imm5d (src0));
3868 OUTS (outf, ", ");
3869 OUTS (outf, dregs (src1 + 1));
3870 OUTS (outf, ":");
3871 OUTS (outf, imm5d (src1));
3872 OUTS (outf, ")");
3873 aligndir (s, outf);
3874 }
3875 else if (aop == 2 && aopcde == 7)
3876 {
3877 OUTS (outf, dregs (dst0));
3878 OUTS (outf, " = ABS ");
3879 OUTS (outf, dregs (src0));
3880 }
3881 else if (aop == 1 && aopcde == 7)
3882 {
3883 OUTS (outf, dregs (dst0));
3884 OUTS (outf, " = MIN (");
3885 OUTS (outf, dregs (src0));
3886 OUTS (outf, ", ");
3887 OUTS (outf, dregs (src1));
3888 OUTS (outf, ")");
3889 }
3890 else if (aop == 0 && aopcde == 7)
3891 {
3892 OUTS (outf, dregs (dst0));
3893 OUTS (outf, " = MAX (");
3894 OUTS (outf, dregs (src0));
3895 OUTS (outf, ", ");
3896 OUTS (outf, dregs (src1));
3897 OUTS (outf, ")");
3898 }
3899 else if (aop == 2 && aopcde == 6)
3900 {
3901 OUTS (outf, dregs (dst0));
3902 OUTS (outf, " = ABS ");
3903 OUTS (outf, dregs (src0));
3904 OUTS (outf, " (V)");
3905 }
3906 else if (aop == 1 && aopcde == 6)
3907 {
3908 OUTS (outf, dregs (dst0));
3909 OUTS (outf, " = MIN (");
3910 OUTS (outf, dregs (src0));
3911 OUTS (outf, ", ");
3912 OUTS (outf, dregs (src1));
3913 OUTS (outf, ") (V)");
3914 }
3915 else if (aop == 0 && aopcde == 6)
3916 {
3917 OUTS (outf, dregs (dst0));
3918 OUTS (outf, " = MAX (");
3919 OUTS (outf, dregs (src0));
3920 OUTS (outf, ", ");
3921 OUTS (outf, dregs (src1));
3922 OUTS (outf, ") (V)");
3923 }
3924 else if (HL == 1 && aopcde == 1)
3925 {
3926 OUTS (outf, dregs (dst1));
3927 OUTS (outf, " = ");
3928 OUTS (outf, dregs (src0));
3929 OUTS (outf, " +|- ");
3930 OUTS (outf, dregs (src1));
3931 OUTS (outf, ", ");
3932 OUTS (outf, dregs (dst0));
3933 OUTS (outf, " = ");
3934 OUTS (outf, dregs (src0));
3935 OUTS (outf, " -|+ ");
3936 OUTS (outf, dregs (src1));
3937 amod0amod2 (s, x, aop, outf);
3938 }
3939 else if (aop == 0 && aopcde == 4)
3940 {
3941 OUTS (outf, dregs (dst0));
3942 OUTS (outf, " = ");
3943 OUTS (outf, dregs (src0));
3944 OUTS (outf, " + ");
3945 OUTS (outf, dregs (src1));
3946 amod1 (s, x, outf);
3947 }
3948 else if (aop == 0 && aopcde == 0)
3949 {
3950 OUTS (outf, dregs (dst0));
3951 OUTS (outf, " = ");
3952 OUTS (outf, dregs (src0));
3953 OUTS (outf, " +|+ ");
3954 OUTS (outf, dregs (src1));
3955 amod0 (s, x, outf);
3956 }
3957 else if (aop == 0 && aopcde == 24)
3958 {
3959 OUTS (outf, dregs (dst0));
3960 OUTS (outf, " = BYTEPACK (");
3961 OUTS (outf, dregs (src0));
3962 OUTS (outf, ", ");
3963 OUTS (outf, dregs (src1));
3964 OUTS (outf, ")");
3965 }
3966 else if (aop == 1 && aopcde == 24)
3967 {
3968 OUTS (outf, "(");
3969 OUTS (outf, dregs (dst1));
3970 OUTS (outf, ", ");
3971 OUTS (outf, dregs (dst0));
3972 OUTS (outf, ") = BYTEUNPACK ");
3973 OUTS (outf, dregs (src0 + 1));
3974 OUTS (outf, ":");
3975 OUTS (outf, imm5d (src0));
3976 aligndir (s, outf);
3977 }
3978 else if (aopcde == 13)
3979 {
3980 OUTS (outf, "(");
3981 OUTS (outf, dregs (dst1));
3982 OUTS (outf, ", ");
3983 OUTS (outf, dregs (dst0));
3984 OUTS (outf, ") = SEARCH ");
3985 OUTS (outf, dregs (src0));
3986 OUTS (outf, " (");
3987 searchmod (aop, outf);
3988 OUTS (outf, ")");
3989 }
3990 else
3991 return 0;
3992
3993 return 4;
3994 }
3995
3996 static int
3997 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3998 {
3999 /* dsp32shift
4000 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4001 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
4002 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
4003 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4004 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
4005 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
4006 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
4007 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
4008 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
4009 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
4010 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
4011
4012 if (HLs == 0 && sop == 0 && sopcde == 0)
4013 {
4014 OUTS (outf, dregs_lo (dst0));
4015 OUTS (outf, " = ASHIFT ");
4016 OUTS (outf, dregs_lo (src1));
4017 OUTS (outf, " BY ");
4018 OUTS (outf, dregs_lo (src0));
4019 }
4020 else if (HLs == 1 && sop == 0 && sopcde == 0)
4021 {
4022 OUTS (outf, dregs_lo (dst0));
4023 OUTS (outf, " = ASHIFT ");
4024 OUTS (outf, dregs_hi (src1));
4025 OUTS (outf, " BY ");
4026 OUTS (outf, dregs_lo (src0));
4027 }
4028 else if (HLs == 2 && sop == 0 && sopcde == 0)
4029 {
4030 OUTS (outf, dregs_hi (dst0));
4031 OUTS (outf, " = ASHIFT ");
4032 OUTS (outf, dregs_lo (src1));
4033 OUTS (outf, " BY ");
4034 OUTS (outf, dregs_lo (src0));
4035 }
4036 else if (HLs == 3 && sop == 0 && sopcde == 0)
4037 {
4038 OUTS (outf, dregs_hi (dst0));
4039 OUTS (outf, " = ASHIFT ");
4040 OUTS (outf, dregs_hi (src1));
4041 OUTS (outf, " BY ");
4042 OUTS (outf, dregs_lo (src0));
4043 }
4044 else if (HLs == 0 && sop == 1 && sopcde == 0)
4045 {
4046 OUTS (outf, dregs_lo (dst0));
4047 OUTS (outf, " = ASHIFT ");
4048 OUTS (outf, dregs_lo (src1));
4049 OUTS (outf, " BY ");
4050 OUTS (outf, dregs_lo (src0));
4051 OUTS (outf, " (S)");
4052 }
4053 else if (HLs == 1 && sop == 1 && sopcde == 0)
4054 {
4055 OUTS (outf, dregs_lo (dst0));
4056 OUTS (outf, " = ASHIFT ");
4057 OUTS (outf, dregs_hi (src1));
4058 OUTS (outf, " BY ");
4059 OUTS (outf, dregs_lo (src0));
4060 OUTS (outf, " (S)");
4061 }
4062 else if (HLs == 2 && sop == 1 && sopcde == 0)
4063 {
4064 OUTS (outf, dregs_hi (dst0));
4065 OUTS (outf, " = ASHIFT ");
4066 OUTS (outf, dregs_lo (src1));
4067 OUTS (outf, " BY ");
4068 OUTS (outf, dregs_lo (src0));
4069 OUTS (outf, " (S)");
4070 }
4071 else if (HLs == 3 && sop == 1 && sopcde == 0)
4072 {
4073 OUTS (outf, dregs_hi (dst0));
4074 OUTS (outf, " = ASHIFT ");
4075 OUTS (outf, dregs_hi (src1));
4076 OUTS (outf, " BY ");
4077 OUTS (outf, dregs_lo (src0));
4078 OUTS (outf, " (S)");
4079 }
4080 else if (sop == 2 && sopcde == 0)
4081 {
4082 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
4083 OUTS (outf, " = LSHIFT ");
4084 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
4085 OUTS (outf, " BY ");
4086 OUTS (outf, dregs_lo (src0));
4087 }
4088 else if (sop == 0 && sopcde == 3)
4089 {
4090 OUTS (outf, acc01);
4091 OUTS (outf, " = ASHIFT ");
4092 OUTS (outf, acc01);
4093 OUTS (outf, " BY ");
4094 OUTS (outf, dregs_lo (src0));
4095 }
4096 else if (sop == 1 && sopcde == 3)
4097 {
4098 OUTS (outf, acc01);
4099 OUTS (outf, " = LSHIFT ");
4100 OUTS (outf, acc01);
4101 OUTS (outf, " BY ");
4102 OUTS (outf, dregs_lo (src0));
4103 }
4104 else if (sop == 2 && sopcde == 3)
4105 {
4106 OUTS (outf, acc01);
4107 OUTS (outf, " = ROT ");
4108 OUTS (outf, acc01);
4109 OUTS (outf, " BY ");
4110 OUTS (outf, dregs_lo (src0));
4111 }
4112 else if (sop == 3 && sopcde == 3)
4113 {
4114 OUTS (outf, dregs (dst0));
4115 OUTS (outf, " = ROT ");
4116 OUTS (outf, dregs (src1));
4117 OUTS (outf, " BY ");
4118 OUTS (outf, dregs_lo (src0));
4119 }
4120 else if (sop == 1 && sopcde == 1)
4121 {
4122 OUTS (outf, dregs (dst0));
4123 OUTS (outf, " = ASHIFT ");
4124 OUTS (outf, dregs (src1));
4125 OUTS (outf, " BY ");
4126 OUTS (outf, dregs_lo (src0));
4127 OUTS (outf, " (V, S)");
4128 }
4129 else if (sop == 0 && sopcde == 1)
4130 {
4131 OUTS (outf, dregs (dst0));
4132 OUTS (outf, " = ASHIFT ");
4133 OUTS (outf, dregs (src1));
4134 OUTS (outf, " BY ");
4135 OUTS (outf, dregs_lo (src0));
4136 OUTS (outf, " (V)");
4137 }
4138 else if (sop == 0 && sopcde == 2)
4139 {
4140 OUTS (outf, dregs (dst0));
4141 OUTS (outf, " = ASHIFT ");
4142 OUTS (outf, dregs (src1));
4143 OUTS (outf, " BY ");
4144 OUTS (outf, dregs_lo (src0));
4145 }
4146 else if (sop == 1 && sopcde == 2)
4147 {
4148 OUTS (outf, dregs (dst0));
4149 OUTS (outf, " = ASHIFT ");
4150 OUTS (outf, dregs (src1));
4151 OUTS (outf, " BY ");
4152 OUTS (outf, dregs_lo (src0));
4153 OUTS (outf, " (S)");
4154 }
4155 else if (sop == 2 && sopcde == 2)
4156 {
4157 OUTS (outf, dregs (dst0));
4158 OUTS (outf, " = LSHIFT ");
4159 OUTS (outf, dregs (src1));
4160 OUTS (outf, " BY ");
4161 OUTS (outf, dregs_lo (src0));
4162 }
4163 else if (sop == 3 && sopcde == 2)
4164 {
4165 OUTS (outf, dregs (dst0));
4166 OUTS (outf, " = ROT ");
4167 OUTS (outf, dregs (src1));
4168 OUTS (outf, " BY ");
4169 OUTS (outf, dregs_lo (src0));
4170 }
4171 else if (sop == 2 && sopcde == 1)
4172 {
4173 OUTS (outf, dregs (dst0));
4174 OUTS (outf, " = LSHIFT ");
4175 OUTS (outf, dregs (src1));
4176 OUTS (outf, " BY ");
4177 OUTS (outf, dregs_lo (src0));
4178 OUTS (outf, " (V)");
4179 }
4180 else if (sop == 0 && sopcde == 4)
4181 {
4182 OUTS (outf, dregs (dst0));
4183 OUTS (outf, " = PACK (");
4184 OUTS (outf, dregs_lo (src1));
4185 OUTS (outf, ", ");
4186 OUTS (outf, dregs_lo (src0));
4187 OUTS (outf, ")");
4188 }
4189 else if (sop == 1 && sopcde == 4)
4190 {
4191 OUTS (outf, dregs (dst0));
4192 OUTS (outf, " = PACK (");
4193 OUTS (outf, dregs_lo (src1));
4194 OUTS (outf, ", ");
4195 OUTS (outf, dregs_hi (src0));
4196 OUTS (outf, ")");
4197 }
4198 else if (sop == 2 && sopcde == 4)
4199 {
4200 OUTS (outf, dregs (dst0));
4201 OUTS (outf, " = PACK (");
4202 OUTS (outf, dregs_hi (src1));
4203 OUTS (outf, ", ");
4204 OUTS (outf, dregs_lo (src0));
4205 OUTS (outf, ")");
4206 }
4207 else if (sop == 3 && sopcde == 4)
4208 {
4209 OUTS (outf, dregs (dst0));
4210 OUTS (outf, " = PACK (");
4211 OUTS (outf, dregs_hi (src1));
4212 OUTS (outf, ", ");
4213 OUTS (outf, dregs_hi (src0));
4214 OUTS (outf, ")");
4215 }
4216 else if (sop == 0 && sopcde == 5)
4217 {
4218 OUTS (outf, dregs_lo (dst0));
4219 OUTS (outf, " = SIGNBITS ");
4220 OUTS (outf, dregs (src1));
4221 }
4222 else if (sop == 1 && sopcde == 5)
4223 {
4224 OUTS (outf, dregs_lo (dst0));
4225 OUTS (outf, " = SIGNBITS ");
4226 OUTS (outf, dregs_lo (src1));
4227 }
4228 else if (sop == 2 && sopcde == 5)
4229 {
4230 OUTS (outf, dregs_lo (dst0));
4231 OUTS (outf, " = SIGNBITS ");
4232 OUTS (outf, dregs_hi (src1));
4233 }
4234 else if (sop == 0 && sopcde == 6)
4235 {
4236 OUTS (outf, dregs_lo (dst0));
4237 OUTS (outf, " = SIGNBITS A0");
4238 }
4239 else if (sop == 1 && sopcde == 6)
4240 {
4241 OUTS (outf, dregs_lo (dst0));
4242 OUTS (outf, " = SIGNBITS A1");
4243 }
4244 else if (sop == 3 && sopcde == 6)
4245 {
4246 OUTS (outf, dregs_lo (dst0));
4247 OUTS (outf, " = ONES ");
4248 OUTS (outf, dregs (src1));
4249 }
4250 else if (sop == 0 && sopcde == 7)
4251 {
4252 OUTS (outf, dregs_lo (dst0));
4253 OUTS (outf, " = EXPADJ (");
4254 OUTS (outf, dregs (src1));
4255 OUTS (outf, ", ");
4256 OUTS (outf, dregs_lo (src0));
4257 OUTS (outf, ")");
4258 }
4259 else if (sop == 1 && sopcde == 7)
4260 {
4261 OUTS (outf, dregs_lo (dst0));
4262 OUTS (outf, " = EXPADJ (");
4263 OUTS (outf, dregs (src1));
4264 OUTS (outf, ", ");
4265 OUTS (outf, dregs_lo (src0));
4266 OUTS (outf, ") (V)");
4267 }
4268 else if (sop == 2 && sopcde == 7)
4269 {
4270 OUTS (outf, dregs_lo (dst0));
4271 OUTS (outf, " = EXPADJ (");
4272 OUTS (outf, dregs_lo (src1));
4273 OUTS (outf, ", ");
4274 OUTS (outf, dregs_lo (src0));
4275 OUTS (outf, ")");
4276 }
4277 else if (sop == 3 && sopcde == 7)
4278 {
4279 OUTS (outf, dregs_lo (dst0));
4280 OUTS (outf, " = EXPADJ (");
4281 OUTS (outf, dregs_hi (src1));
4282 OUTS (outf, ", ");
4283 OUTS (outf, dregs_lo (src0));
4284 OUTS (outf, ")");
4285 }
4286 else if (sop == 0 && sopcde == 8)
4287 {
4288 OUTS (outf, "BITMUX (");
4289 OUTS (outf, dregs (src0));
4290 OUTS (outf, ", ");
4291 OUTS (outf, dregs (src1));
4292 OUTS (outf, ", A0) (ASR)");
4293 }
4294 else if (sop == 1 && sopcde == 8)
4295 {
4296 OUTS (outf, "BITMUX (");
4297 OUTS (outf, dregs (src0));
4298 OUTS (outf, ", ");
4299 OUTS (outf, dregs (src1));
4300 OUTS (outf, ", A0) (ASL)");
4301 }
4302 else if (sop == 0 && sopcde == 9)
4303 {
4304 OUTS (outf, dregs_lo (dst0));
4305 OUTS (outf, " = VIT_MAX (");
4306 OUTS (outf, dregs (src1));
4307 OUTS (outf, ") (ASL)");
4308 }
4309 else if (sop == 1 && sopcde == 9)
4310 {
4311 OUTS (outf, dregs_lo (dst0));
4312 OUTS (outf, " = VIT_MAX (");
4313 OUTS (outf, dregs (src1));
4314 OUTS (outf, ") (ASR)");
4315 }
4316 else if (sop == 2 && sopcde == 9)
4317 {
4318 OUTS (outf, dregs (dst0));
4319 OUTS (outf, " = VIT_MAX (");
4320 OUTS (outf, dregs (src1));
4321 OUTS (outf, ", ");
4322 OUTS (outf, dregs (src0));
4323 OUTS (outf, ") (ASL)");
4324 }
4325 else if (sop == 3 && sopcde == 9)
4326 {
4327 OUTS (outf, dregs (dst0));
4328 OUTS (outf, " = VIT_MAX (");
4329 OUTS (outf, dregs (src1));
4330 OUTS (outf, ", ");
4331 OUTS (outf, dregs (src0));
4332 OUTS (outf, ") (ASR)");
4333 }
4334 else if (sop == 0 && sopcde == 10)
4335 {
4336 OUTS (outf, dregs (dst0));
4337 OUTS (outf, " = EXTRACT (");
4338 OUTS (outf, dregs (src1));
4339 OUTS (outf, ", ");
4340 OUTS (outf, dregs_lo (src0));
4341 OUTS (outf, ") (Z)");
4342 }
4343 else if (sop == 1 && sopcde == 10)
4344 {
4345 OUTS (outf, dregs (dst0));
4346 OUTS (outf, " = EXTRACT (");
4347 OUTS (outf, dregs (src1));
4348 OUTS (outf, ", ");
4349 OUTS (outf, dregs_lo (src0));
4350 OUTS (outf, ") (X)");
4351 }
4352 else if (sop == 2 && sopcde == 10)
4353 {
4354 OUTS (outf, dregs (dst0));
4355 OUTS (outf, " = DEPOSIT (");
4356 OUTS (outf, dregs (src1));
4357 OUTS (outf, ", ");
4358 OUTS (outf, dregs (src0));
4359 OUTS (outf, ")");
4360 }
4361 else if (sop == 3 && sopcde == 10)
4362 {
4363 OUTS (outf, dregs (dst0));
4364 OUTS (outf, " = DEPOSIT (");
4365 OUTS (outf, dregs (src1));
4366 OUTS (outf, ", ");
4367 OUTS (outf, dregs (src0));
4368 OUTS (outf, ") (X)");
4369 }
4370 else if (sop == 0 && sopcde == 11)
4371 {
4372 OUTS (outf, dregs_lo (dst0));
4373 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4374 OUTS (outf, dregs (src0));
4375 OUTS (outf, ")");
4376 }
4377 else if (sop == 1 && sopcde == 11)
4378 {
4379 OUTS (outf, dregs_lo (dst0));
4380 OUTS (outf, " = CC = BXOR (A0, ");
4381 OUTS (outf, dregs (src0));
4382 OUTS (outf, ")");
4383 }
4384 else if (sop == 0 && sopcde == 12)
4385 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4386
4387 else if (sop == 1 && sopcde == 12)
4388 {
4389 OUTS (outf, dregs_lo (dst0));
4390 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4391 }
4392 else if (sop == 0 && sopcde == 13)
4393 {
4394 OUTS (outf, dregs (dst0));
4395 OUTS (outf, " = ALIGN8 (");
4396 OUTS (outf, dregs (src1));
4397 OUTS (outf, ", ");
4398 OUTS (outf, dregs (src0));
4399 OUTS (outf, ")");
4400 }
4401 else if (sop == 1 && sopcde == 13)
4402 {
4403 OUTS (outf, dregs (dst0));
4404 OUTS (outf, " = ALIGN16 (");
4405 OUTS (outf, dregs (src1));
4406 OUTS (outf, ", ");
4407 OUTS (outf, dregs (src0));
4408 OUTS (outf, ")");
4409 }
4410 else if (sop == 2 && sopcde == 13)
4411 {
4412 OUTS (outf, dregs (dst0));
4413 OUTS (outf, " = ALIGN24 (");
4414 OUTS (outf, dregs (src1));
4415 OUTS (outf, ", ");
4416 OUTS (outf, dregs (src0));
4417 OUTS (outf, ")");
4418 }
4419 else
4420 return 0;
4421
4422 return 4;
4423 }
4424
4425 static int
4426 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4427 {
4428 /* dsp32shiftimm
4429 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4430 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4431 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4432 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4433 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4434 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4435 int bit8 = ((iw1 >> 8) & 0x1);
4436 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4437 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4438 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4439 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4440 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4441
4442
4443 if (sop == 0 && sopcde == 0)
4444 {
4445 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4446 OUTS (outf, " = ");
4447 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4448 OUTS (outf, " >>> ");
4449 OUTS (outf, uimm4 (newimmag));
4450 }
4451 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4452 {
4453 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4454 OUTS (outf, " = ");
4455 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4456 OUTS (outf, " << ");
4457 OUTS (outf, uimm4 (immag));
4458 OUTS (outf, " (S)");
4459 }
4460 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4461 {
4462 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4463 OUTS (outf, " = ");
4464 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4465 OUTS (outf, " >>> ");
4466 OUTS (outf, uimm4 (newimmag));
4467 OUTS (outf, " (S)");
4468 }
4469 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4470 {
4471 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4472 OUTS (outf, " = ");
4473 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4474 OUTS (outf, " << ");
4475 OUTS (outf, uimm4 (immag));
4476 }
4477 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4478 {
4479 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4480 OUTS (outf, " = ");
4481 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4482 OUTS (outf, " >> ");
4483 OUTS (outf, uimm4 (newimmag));
4484 }
4485 else if (sop == 2 && sopcde == 3 && HLs == 1)
4486 {
4487 OUTS (outf, "A1 = ROT A1 BY ");
4488 OUTS (outf, imm6 (immag));
4489 }
4490 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4491 {
4492 OUTS (outf, "A0 = A0 << ");
4493 OUTS (outf, uimm5 (immag));
4494 }
4495 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4496 {
4497 OUTS (outf, "A0 = A0 >>> ");
4498 OUTS (outf, uimm5 (newimmag));
4499 }
4500 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4501 {
4502 OUTS (outf, "A1 = A1 << ");
4503 OUTS (outf, uimm5 (immag));
4504 }
4505 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4506 {
4507 OUTS (outf, "A1 = A1 >>> ");
4508 OUTS (outf, uimm5 (newimmag));
4509 }
4510 else if (sop == 1 && sopcde == 3 && HLs == 0)
4511 {
4512 OUTS (outf, "A0 = A0 >> ");
4513 OUTS (outf, uimm5 (newimmag));
4514 }
4515 else if (sop == 1 && sopcde == 3 && HLs == 1)
4516 {
4517 OUTS (outf, "A1 = A1 >> ");
4518 OUTS (outf, uimm5 (newimmag));
4519 }
4520 else if (sop == 2 && sopcde == 3 && HLs == 0)
4521 {
4522 OUTS (outf, "A0 = ROT A0 BY ");
4523 OUTS (outf, imm6 (immag));
4524 }
4525 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4526 {
4527 OUTS (outf, dregs (dst0));
4528 OUTS (outf, " = ");
4529 OUTS (outf, dregs (src1));
4530 OUTS (outf, " << ");
4531 OUTS (outf, uimm5 (immag));
4532 OUTS (outf, " (V, S)");
4533 }
4534 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4535 {
4536 OUTS (outf, dregs (dst0));
4537 OUTS (outf, " = ");
4538 OUTS (outf, dregs (src1));
4539 OUTS (outf, " >>> ");
4540 OUTS (outf, imm5 (-immag));
4541 OUTS (outf, " (V, S)");
4542 }
4543 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4544 {
4545 OUTS (outf, dregs (dst0));
4546 OUTS (outf, " = ");
4547 OUTS (outf, dregs (src1));
4548 OUTS (outf, " >> ");
4549 OUTS (outf, uimm5 (newimmag));
4550 OUTS (outf, " (V)");
4551 }
4552 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4553 {
4554 OUTS (outf, dregs (dst0));
4555 OUTS (outf, " = ");
4556 OUTS (outf, dregs (src1));
4557 OUTS (outf, " << ");
4558 OUTS (outf, imm5 (immag));
4559 OUTS (outf, " (V)");
4560 }
4561 else if (sop == 0 && sopcde == 1)
4562 {
4563 OUTS (outf, dregs (dst0));
4564 OUTS (outf, " = ");
4565 OUTS (outf, dregs (src1));
4566 OUTS (outf, " >>> ");
4567 OUTS (outf, uimm5 (newimmag));
4568 OUTS (outf, " (V)");
4569 }
4570 else if (sop == 1 && sopcde == 2)
4571 {
4572 OUTS (outf, dregs (dst0));
4573 OUTS (outf, " = ");
4574 OUTS (outf, dregs (src1));
4575 OUTS (outf, " << ");
4576 OUTS (outf, uimm5 (immag));
4577 OUTS (outf, " (S)");
4578 }
4579 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4580 {
4581 OUTS (outf, dregs (dst0));
4582 OUTS (outf, " = ");
4583 OUTS (outf, dregs (src1));
4584 OUTS (outf, " >> ");
4585 OUTS (outf, uimm5 (newimmag));
4586 }
4587 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4588 {
4589 OUTS (outf, dregs (dst0));
4590 OUTS (outf, " = ");
4591 OUTS (outf, dregs (src1));
4592 OUTS (outf, " << ");
4593 OUTS (outf, uimm5 (immag));
4594 }
4595 else if (sop == 3 && sopcde == 2)
4596 {
4597 OUTS (outf, dregs (dst0));
4598 OUTS (outf, " = ROT ");
4599 OUTS (outf, dregs (src1));
4600 OUTS (outf, " BY ");
4601 OUTS (outf, imm6 (immag));
4602 }
4603 else if (sop == 0 && sopcde == 2)
4604 {
4605 OUTS (outf, dregs (dst0));
4606 OUTS (outf, " = ");
4607 OUTS (outf, dregs (src1));
4608 OUTS (outf, " >>> ");
4609 OUTS (outf, uimm5 (newimmag));
4610 }
4611 else
4612 return 0;
4613
4614 return 4;
4615 }
4616
4617 static int
4618 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4619 {
4620 /* pseudoDEBUG
4621 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4622 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4623 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4624 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4625 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4626 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4627
4628 if (parallel)
4629 return 0;
4630
4631 if (reg == 0 && fn == 3)
4632 OUTS (outf, "DBG A0");
4633
4634 else if (reg == 1 && fn == 3)
4635 OUTS (outf, "DBG A1");
4636
4637 else if (reg == 3 && fn == 3)
4638 OUTS (outf, "ABORT");
4639
4640 else if (reg == 4 && fn == 3)
4641 OUTS (outf, "HLT");
4642
4643 else if (reg == 5 && fn == 3)
4644 OUTS (outf, "DBGHALT");
4645
4646 else if (reg == 6 && fn == 3)
4647 {
4648 OUTS (outf, "DBGCMPLX (");
4649 OUTS (outf, dregs (grp));
4650 OUTS (outf, ")");
4651 }
4652 else if (reg == 7 && fn == 3)
4653 OUTS (outf, "DBG");
4654
4655 else if (grp == 0 && fn == 2)
4656 {
4657 OUTS (outf, "OUTC ");
4658 OUTS (outf, dregs (reg));
4659 }
4660 else if (fn == 0)
4661 {
4662 OUTS (outf, "DBG ");
4663 OUTS (outf, allregs (reg, grp));
4664 }
4665 else if (fn == 1)
4666 {
4667 OUTS (outf, "PRNT");
4668 OUTS (outf, allregs (reg, grp));
4669 }
4670 else
4671 return 0;
4672
4673 return 2;
4674 }
4675
4676 static int
4677 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4678 {
4679 /* psedoOChar
4680 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4681 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4682 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4683 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4684
4685 if (parallel)
4686 return 0;
4687
4688 OUTS (outf, "OUTC ");
4689 OUTS (outf, uimm8 (ch));
4690
4691 return 2;
4692 }
4693
4694 static int
4695 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4696 {
4697 /* pseudodbg_assert
4698 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4699 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4700 |.expected......................................................|
4701 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4702 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4703 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4704 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4705 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4706
4707 if (parallel)
4708 return 0;
4709
4710 if (dbgop == 0)
4711 {
4712 OUTS (outf, "DBGA (");
4713 OUTS (outf, regs_lo (regtest, grp));
4714 OUTS (outf, ", ");
4715 OUTS (outf, uimm16 (expected));
4716 OUTS (outf, ")");
4717 }
4718 else if (dbgop == 1)
4719 {
4720 OUTS (outf, "DBGA (");
4721 OUTS (outf, regs_hi (regtest, grp));
4722 OUTS (outf, ", ");
4723 OUTS (outf, uimm16 (expected));
4724 OUTS (outf, ")");
4725 }
4726 else if (dbgop == 2)
4727 {
4728 OUTS (outf, "DBGAL (");
4729 OUTS (outf, allregs (regtest, grp));
4730 OUTS (outf, ", ");
4731 OUTS (outf, uimm16 (expected));
4732 OUTS (outf, ")");
4733 }
4734 else if (dbgop == 3)
4735 {
4736 OUTS (outf, "DBGAH (");
4737 OUTS (outf, allregs (regtest, grp));
4738 OUTS (outf, ", ");
4739 OUTS (outf, uimm16 (expected));
4740 OUTS (outf, ")");
4741 }
4742 else
4743 return 0;
4744 return 4;
4745 }
4746
4747 static int
4748 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4749 {
4750 bfd_byte buf[4];
4751 TIword iw0;
4752 TIword iw1;
4753 int status;
4754 int rv = 0;
4755
4756 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4757 /* FIXME */
4758 (void) status;
4759 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4760 /* FIXME */
4761 (void) status;
4762
4763 iw0 = bfd_getl16 (buf);
4764 iw1 = bfd_getl16 (buf + 2);
4765
4766 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4767 {
4768 if (parallel)
4769 {
4770 OUTS (outf, "ILLEGAL");
4771 return 0;
4772 }
4773 OUTS (outf, "MNOP");
4774 return 4;
4775 }
4776 else if ((iw0 & 0xff00) == 0x0000)
4777 rv = decode_ProgCtrl_0 (iw0, outf);
4778 else if ((iw0 & 0xffc0) == 0x0240)
4779 rv = decode_CaCTRL_0 (iw0, outf);
4780 else if ((iw0 & 0xff80) == 0x0100)
4781 rv = decode_PushPopReg_0 (iw0, outf);
4782 else if ((iw0 & 0xfe00) == 0x0400)
4783 rv = decode_PushPopMultiple_0 (iw0, outf);
4784 else if ((iw0 & 0xfe00) == 0x0600)
4785 rv = decode_ccMV_0 (iw0, outf);
4786 else if ((iw0 & 0xf800) == 0x0800)
4787 rv = decode_CCflag_0 (iw0, outf);
4788 else if ((iw0 & 0xffe0) == 0x0200)
4789 rv = decode_CC2dreg_0 (iw0, outf);
4790 else if ((iw0 & 0xff00) == 0x0300)
4791 rv = decode_CC2stat_0 (iw0, outf);
4792 else if ((iw0 & 0xf000) == 0x1000)
4793 rv = decode_BRCC_0 (iw0, pc, outf);
4794 else if ((iw0 & 0xf000) == 0x2000)
4795 rv = decode_UJUMP_0 (iw0, pc, outf);
4796 else if ((iw0 & 0xf000) == 0x3000)
4797 rv = decode_REGMV_0 (iw0, outf);
4798 else if ((iw0 & 0xfc00) == 0x4000)
4799 rv = decode_ALU2op_0 (iw0, outf);
4800 else if ((iw0 & 0xfe00) == 0x4400)
4801 rv = decode_PTR2op_0 (iw0, outf);
4802 else if ((iw0 & 0xf800) == 0x4800)
4803 rv = decode_LOGI2op_0 (iw0, outf);
4804 else if ((iw0 & 0xf000) == 0x5000)
4805 rv = decode_COMP3op_0 (iw0, outf);
4806 else if ((iw0 & 0xf800) == 0x6000)
4807 rv = decode_COMPI2opD_0 (iw0, outf);
4808 else if ((iw0 & 0xf800) == 0x6800)
4809 rv = decode_COMPI2opP_0 (iw0, outf);
4810 else if ((iw0 & 0xf000) == 0x8000)
4811 rv = decode_LDSTpmod_0 (iw0, outf);
4812 else if ((iw0 & 0xff60) == 0x9e60)
4813 rv = decode_dagMODim_0 (iw0, outf);
4814 else if ((iw0 & 0xfff0) == 0x9f60)
4815 rv = decode_dagMODik_0 (iw0, outf);
4816 else if ((iw0 & 0xfc00) == 0x9c00)
4817 rv = decode_dspLDST_0 (iw0, outf);
4818 else if ((iw0 & 0xf000) == 0x9000)
4819 rv = decode_LDST_0 (iw0, outf);
4820 else if ((iw0 & 0xfc00) == 0xb800)
4821 rv = decode_LDSTiiFP_0 (iw0, outf);
4822 else if ((iw0 & 0xe000) == 0xA000)
4823 rv = decode_LDSTii_0 (iw0, outf);
4824 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4825 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4826 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4827 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4828 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4829 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4830 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4831 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4832 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4833 rv = decode_linkage_0 (iw0, iw1, outf);
4834 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4835 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4836 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4837 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4838 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4839 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4840 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4841 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4842 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4843 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4844 else if ((iw0 & 0xff00) == 0xf800)
4845 rv = decode_pseudoDEBUG_0 (iw0, outf);
4846 else if ((iw0 & 0xFF00) == 0xF900)
4847 rv = decode_pseudoOChar_0 (iw0, outf);
4848 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4849 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4850
4851 if (rv == 0)
4852 OUTS (outf, "ILLEGAL");
4853
4854 return rv;
4855 }
4856
4857
4858 int
4859 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4860 {
4861 bfd_byte buf[2];
4862 unsigned short iw0;
4863 int status;
4864 int count = 0;
4865
4866 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4867 /* FIXME */
4868 (void) status;
4869 iw0 = bfd_getl16 (buf);
4870
4871 count += _print_insn_bfin (pc, outf);
4872
4873 /* Proper display of multiple issue instructions. */
4874
4875 if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4876 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4877 {
4878 int legal = 1;
4879 int len;
4880
4881 parallel = 1;
4882 outf->fprintf_func (outf->stream, " || ");
4883 len = _print_insn_bfin (pc + 4, outf);
4884 outf->fprintf_func (outf->stream, " || ");
4885 if (len != 2)
4886 legal = 0;
4887 len = _print_insn_bfin (pc + 6, outf);
4888 if (len != 2)
4889 legal = 0;
4890
4891 if (legal)
4892 count = 8;
4893 else
4894 {
4895 outf->fprintf_func (outf->stream, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4896 comment = 1;
4897 count = 0;
4898 }
4899 parallel = 0;
4900 }
4901
4902 if (!comment)
4903 outf->fprintf_func (outf->stream, ";");
4904
4905 if (count == 0)
4906 return 2;
4907
4908 comment = 0;
4909
4910 return count;
4911 }
git-cvsimport of binutils cvsroot