1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 x86_64 support by Jan Hubicka (jh@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
55 static int fits_in_signed_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_word
PARAMS ((offsetT
));
58 static int fits_in_signed_word
PARAMS ((offsetT
));
59 static int fits_in_unsigned_long
PARAMS ((offsetT
));
60 static int fits_in_signed_long
PARAMS ((offsetT
));
61 static int smallest_imm_type
PARAMS ((offsetT
));
62 static offsetT offset_in_range
PARAMS ((offsetT
, int));
63 static int add_prefix
PARAMS ((unsigned int));
64 static void set_code_flag
PARAMS ((int));
65 static void set_16bit_gcc_code_flag
PARAMS ((int));
66 static void set_intel_syntax
PARAMS ((int));
67 static void set_cpu_arch
PARAMS ((int));
70 static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
75 #define DEFAULT_ARCH "i386"
77 static char *default_arch
= DEFAULT_ARCH
;
79 /* 'md_assemble ()' gathers together information and puts it into a
86 const reg_entry
*regs
;
91 /* TM holds the template for the insn were currently assembling. */
94 /* SUFFIX holds the instruction mnemonic suffix if given.
95 (e.g. 'l' for 'movl') */
98 /* OPERANDS gives the number of given operands. */
99 unsigned int operands
;
101 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
102 of given register, displacement, memory operands and immediate
104 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
106 /* TYPES [i] is the type (see above #defines) which tells us how to
107 use OP[i] for the corresponding operand. */
108 unsigned int types
[MAX_OPERANDS
];
110 /* Displacement expression, immediate expression, or register for each
112 union i386_op op
[MAX_OPERANDS
];
114 /* Flags for operands. */
115 unsigned int flags
[MAX_OPERANDS
];
116 #define Operand_PCrel 1
118 /* Relocation type for operand */
120 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
122 int disp_reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
244 static enum flag_code flag_code
;
245 static int use_rela_relocations
= 0;
247 /* The names used to print error messages. */
248 static const char *flag_code_names
[] =
255 /* 1 for intel syntax,
257 static int intel_syntax
= 0;
259 /* 1 if register prefix % not required. */
260 static int allow_naked_reg
= 0;
262 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
263 leave, push, and pop instructions so that gcc has the same stack
264 frame as in 32 bit mode. */
265 static char stackop_size
= '\0';
267 /* Non-zero to quieten some warnings. */
268 static int quiet_warnings
= 0;
271 static const char *cpu_arch_name
= NULL
;
273 /* CPU feature flags. */
274 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
276 /* If set, conditional jumps are not automatically promoted to handle
277 larger than a byte offset. */
278 static unsigned int no_cond_jump_promotion
= 0;
280 /* Interface to relax_segment.
281 There are 3 major relax states for 386 jump insns because the
282 different types of jumps add different sizes to frags when we're
283 figuring out what sort of jump to choose to reach a given label. */
286 #define UNCOND_JUMP 1
288 #define COND_JUMP86 3
293 #define SMALL16 (SMALL|CODE16)
295 #define BIG16 (BIG|CODE16)
299 #define INLINE __inline__
305 #define ENCODE_RELAX_STATE(type, size) \
306 ((relax_substateT) (((type) << 2) | (size)))
307 #define TYPE_FROM_RELAX_STATE(s) \
309 #define DISP_SIZE_FROM_RELAX_STATE(s) \
310 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
312 /* This table is used by relax_frag to promote short jumps to long
313 ones where necessary. SMALL (short) jumps may be promoted to BIG
314 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
315 don't allow a short jump in a 32 bit code segment to be promoted to
316 a 16 bit offset jump because it's slower (requires data size
317 prefix), and doesn't work, unless the destination is in the bottom
318 64k of the code segment (The top 16 bits of eip are zeroed). */
320 const relax_typeS md_relax_table
[] =
323 1) most positive reach of this state,
324 2) most negative reach of this state,
325 3) how many bytes this mode will add to the size of the current frag
326 4) which index into the table to try if we can't fit into this one. */
332 /* UNCOND_JUMP states. */
333 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
334 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
335 /* dword jmp adds 3 bytes to frag:
336 0 extra opcode bytes, 3 extra displacement bytes. */
338 /* word jmp adds 1 byte to frag:
339 0 extra opcode bytes, 1 extra displacement byte. */
342 /* COND_JUMP states. */
343 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
344 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
345 /* dword conditionals adds 4 bytes to frag:
346 1 extra opcode byte, 3 extra displacement bytes. */
348 /* word conditionals add 2 bytes to frag:
349 1 extra opcode byte, 1 extra displacement byte. */
352 /* COND_JUMP86 states. */
353 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
354 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
355 /* dword conditionals adds 4 bytes to frag:
356 1 extra opcode byte, 3 extra displacement bytes. */
358 /* word conditionals add 3 bytes to frag:
359 1 extra opcode byte, 2 extra displacement bytes. */
363 static const arch_entry cpu_arch
[] = {
365 {"i186", Cpu086
|Cpu186
},
366 {"i286", Cpu086
|Cpu186
|Cpu286
},
367 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
368 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
369 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
370 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
371 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
372 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
373 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
374 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
375 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
376 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
381 i386_align_code (fragP
, count
)
385 /* Various efficient no-op patterns for aligning code labels.
386 Note: Don't try to assemble the instructions in the comments.
387 0L and 0w are not legal. */
388 static const char f32_1
[] =
390 static const char f32_2
[] =
391 {0x89,0xf6}; /* movl %esi,%esi */
392 static const char f32_3
[] =
393 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
394 static const char f32_4
[] =
395 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
396 static const char f32_5
[] =
398 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
399 static const char f32_6
[] =
400 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
401 static const char f32_7
[] =
402 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
403 static const char f32_8
[] =
405 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
406 static const char f32_9
[] =
407 {0x89,0xf6, /* movl %esi,%esi */
408 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
409 static const char f32_10
[] =
410 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
411 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
412 static const char f32_11
[] =
413 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
414 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
415 static const char f32_12
[] =
416 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
417 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
418 static const char f32_13
[] =
419 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
420 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
421 static const char f32_14
[] =
422 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
423 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
424 static const char f32_15
[] =
425 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
426 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
427 static const char f16_3
[] =
428 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
429 static const char f16_4
[] =
430 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
431 static const char f16_5
[] =
433 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
434 static const char f16_6
[] =
435 {0x89,0xf6, /* mov %si,%si */
436 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
437 static const char f16_7
[] =
438 {0x8d,0x74,0x00, /* lea 0(%si),%si */
439 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
440 static const char f16_8
[] =
441 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
442 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
443 static const char *const f32_patt
[] = {
444 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
445 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
447 static const char *const f16_patt
[] = {
448 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
449 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
452 /* ??? We can't use these fillers for x86_64, since they often kills the
453 upper halves. Solve later. */
454 if (flag_code
== CODE_64BIT
)
457 if (count
> 0 && count
<= 15)
459 if (flag_code
== CODE_16BIT
)
461 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
462 f16_patt
[count
- 1], count
);
464 /* Adjust jump offset. */
465 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
468 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
469 f32_patt
[count
- 1], count
);
470 fragP
->fr_var
= count
;
474 static char *output_invalid
PARAMS ((int c
));
475 static int i386_operand
PARAMS ((char *operand_string
));
476 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
477 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
481 static void s_bss
PARAMS ((int));
484 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
486 static INLINE
unsigned int
487 mode_from_disp_size (t
)
490 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
494 fits_in_signed_byte (num
)
497 return (num
>= -128) && (num
<= 127);
501 fits_in_unsigned_byte (num
)
504 return (num
& 0xff) == num
;
508 fits_in_unsigned_word (num
)
511 return (num
& 0xffff) == num
;
515 fits_in_signed_word (num
)
518 return (-32768 <= num
) && (num
<= 32767);
521 fits_in_signed_long (num
)
522 offsetT num ATTRIBUTE_UNUSED
;
527 return (!(((offsetT
) -1 << 31) & num
)
528 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
530 } /* fits_in_signed_long() */
532 fits_in_unsigned_long (num
)
533 offsetT num ATTRIBUTE_UNUSED
;
538 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
540 } /* fits_in_unsigned_long() */
543 smallest_imm_type (num
)
546 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
547 && !(cpu_arch_flags
& (CpuUnknown
)))
549 /* This code is disabled on the 486 because all the Imm1 forms
550 in the opcode table are slower on the i486. They're the
551 versions with the implicitly specified single-position
552 displacement, which has another syntax if you really want to
555 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
557 return (fits_in_signed_byte (num
)
558 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
559 : fits_in_unsigned_byte (num
)
560 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
561 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
562 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
563 : fits_in_signed_long (num
)
564 ? (Imm32
| Imm32S
| Imm64
)
565 : fits_in_unsigned_long (num
)
571 offset_in_range (val
, size
)
579 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
580 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
581 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
583 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
588 /* If BFD64, sign extend val. */
589 if (!use_rela_relocations
)
590 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
591 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
593 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
595 char buf1
[40], buf2
[40];
597 sprint_value (buf1
, val
);
598 sprint_value (buf2
, val
& mask
);
599 as_warn (_("%s shortened to %s"), buf1
, buf2
);
604 /* Returns 0 if attempting to add a prefix where one from the same
605 class already exists, 1 if non rep/repne added, 2 if rep/repne
614 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
622 case CS_PREFIX_OPCODE
:
623 case DS_PREFIX_OPCODE
:
624 case ES_PREFIX_OPCODE
:
625 case FS_PREFIX_OPCODE
:
626 case GS_PREFIX_OPCODE
:
627 case SS_PREFIX_OPCODE
:
631 case REPNE_PREFIX_OPCODE
:
632 case REPE_PREFIX_OPCODE
:
635 case LOCK_PREFIX_OPCODE
:
643 case ADDR_PREFIX_OPCODE
:
647 case DATA_PREFIX_OPCODE
:
654 as_bad (_("same type of prefix used twice"));
659 i
.prefix
[q
] = prefix
;
664 set_code_flag (value
)
668 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
669 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
670 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
672 as_bad (_("64bit mode not supported on this CPU."));
674 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
676 as_bad (_("32bit mode not supported on this CPU."));
682 set_16bit_gcc_code_flag (new_code_flag
)
685 flag_code
= new_code_flag
;
686 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
687 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
692 set_intel_syntax (syntax_flag
)
695 /* Find out if register prefixing is specified. */
696 int ask_naked_reg
= 0;
699 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
701 char *string
= input_line_pointer
;
702 int e
= get_symbol_end ();
704 if (strcmp (string
, "prefix") == 0)
706 else if (strcmp (string
, "noprefix") == 0)
709 as_bad (_("bad argument to syntax directive."));
710 *input_line_pointer
= e
;
712 demand_empty_rest_of_line ();
714 intel_syntax
= syntax_flag
;
716 if (ask_naked_reg
== 0)
719 allow_naked_reg
= (intel_syntax
720 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
722 /* Conservative default. */
727 allow_naked_reg
= (ask_naked_reg
< 0);
732 int dummy ATTRIBUTE_UNUSED
;
736 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
738 char *string
= input_line_pointer
;
739 int e
= get_symbol_end ();
742 for (i
= 0; cpu_arch
[i
].name
; i
++)
744 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
746 cpu_arch_name
= cpu_arch
[i
].name
;
747 cpu_arch_flags
= (cpu_arch
[i
].flags
748 | (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
));
752 if (!cpu_arch
[i
].name
)
753 as_bad (_("no such architecture: `%s'"), string
);
755 *input_line_pointer
= e
;
758 as_bad (_("missing cpu architecture"));
760 no_cond_jump_promotion
= 0;
761 if (*input_line_pointer
== ','
762 && ! is_end_of_line
[(unsigned char) input_line_pointer
[1]])
764 char *string
= ++input_line_pointer
;
765 int e
= get_symbol_end ();
767 if (strcmp (string
, "nojumps") == 0)
768 no_cond_jump_promotion
= 1;
769 else if (strcmp (string
, "jumps") == 0)
772 as_bad (_("no such architecture modifier: `%s'"), string
);
774 *input_line_pointer
= e
;
777 demand_empty_rest_of_line ();
780 const pseudo_typeS md_pseudo_table
[] =
782 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
783 {"align", s_align_bytes
, 0},
785 {"align", s_align_ptwo
, 0},
787 {"arch", set_cpu_arch
, 0},
791 {"ffloat", float_cons
, 'f'},
792 {"dfloat", float_cons
, 'd'},
793 {"tfloat", float_cons
, 'x'},
795 {"noopt", s_ignore
, 0},
796 {"optim", s_ignore
, 0},
797 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
798 {"code16", set_code_flag
, CODE_16BIT
},
799 {"code32", set_code_flag
, CODE_32BIT
},
800 {"code64", set_code_flag
, CODE_64BIT
},
801 {"intel_syntax", set_intel_syntax
, 1},
802 {"att_syntax", set_intel_syntax
, 0},
803 {"file", dwarf2_directive_file
, 0},
804 {"loc", dwarf2_directive_loc
, 0},
808 /* For interface with expression (). */
809 extern char *input_line_pointer
;
811 /* Hash table for instruction mnemonic lookup. */
812 static struct hash_control
*op_hash
;
814 /* Hash table for register lookup. */
815 static struct hash_control
*reg_hash
;
821 if (!strcmp (default_arch
, "x86_64"))
822 return bfd_mach_x86_64
;
823 else if (!strcmp (default_arch
, "i386"))
824 return bfd_mach_i386_i386
;
826 as_fatal (_("Unknown architecture"));
833 const char *hash_err
;
835 /* Initialize op_hash hash table. */
836 op_hash
= hash_new ();
839 register const template *optab
;
840 register templates
*core_optab
;
842 /* Setup for loop. */
844 core_optab
= (templates
*) xmalloc (sizeof (templates
));
845 core_optab
->start
= optab
;
850 if (optab
->name
== NULL
851 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
853 /* different name --> ship out current template list;
854 add to hash table; & begin anew. */
855 core_optab
->end
= optab
;
856 hash_err
= hash_insert (op_hash
,
861 as_fatal (_("Internal Error: Can't hash %s: %s"),
865 if (optab
->name
== NULL
)
867 core_optab
= (templates
*) xmalloc (sizeof (templates
));
868 core_optab
->start
= optab
;
873 /* Initialize reg_hash hash table. */
874 reg_hash
= hash_new ();
876 register const reg_entry
*regtab
;
878 for (regtab
= i386_regtab
;
879 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
882 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
884 as_fatal (_("Internal Error: Can't hash %s: %s"),
890 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
895 for (c
= 0; c
< 256; c
++)
900 mnemonic_chars
[c
] = c
;
901 register_chars
[c
] = c
;
902 operand_chars
[c
] = c
;
904 else if (islower (c
))
906 mnemonic_chars
[c
] = c
;
907 register_chars
[c
] = c
;
908 operand_chars
[c
] = c
;
910 else if (isupper (c
))
912 mnemonic_chars
[c
] = tolower (c
);
913 register_chars
[c
] = mnemonic_chars
[c
];
914 operand_chars
[c
] = c
;
917 if (isalpha (c
) || isdigit (c
))
918 identifier_chars
[c
] = c
;
921 identifier_chars
[c
] = c
;
922 operand_chars
[c
] = c
;
927 identifier_chars
['@'] = '@';
929 digit_chars
['-'] = '-';
930 identifier_chars
['_'] = '_';
931 identifier_chars
['.'] = '.';
933 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
934 operand_chars
[(unsigned char) *p
] = *p
;
937 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
938 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
940 record_alignment (text_section
, 2);
941 record_alignment (data_section
, 2);
942 record_alignment (bss_section
, 2);
948 i386_print_statistics (file
)
951 hash_print_statistics (file
, "i386 opcode", op_hash
);
952 hash_print_statistics (file
, "i386 register", reg_hash
);
957 /* Debugging routines for md_assemble. */
958 static void pi
PARAMS ((char *, i386_insn
*));
959 static void pte
PARAMS ((template *));
960 static void pt
PARAMS ((unsigned int));
961 static void pe
PARAMS ((expressionS
*));
962 static void ps
PARAMS ((symbolS
*));
971 fprintf (stdout
, "%s: template ", line
);
973 fprintf (stdout
, " address: base %s index %s scale %x\n",
974 x
->base_reg
? x
->base_reg
->reg_name
: "none",
975 x
->index_reg
? x
->index_reg
->reg_name
: "none",
976 x
->log2_scale_factor
);
977 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
978 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
979 fprintf (stdout
, " sib: base %x index %x scale %x\n",
980 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
981 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
982 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
983 for (i
= 0; i
< x
->operands
; i
++)
985 fprintf (stdout
, " #%d: ", i
+ 1);
987 fprintf (stdout
, "\n");
989 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
990 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
991 if (x
->types
[i
] & Imm
)
993 if (x
->types
[i
] & Disp
)
1003 fprintf (stdout
, " %d operands ", t
->operands
);
1004 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1005 if (t
->extension_opcode
!= None
)
1006 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1007 if (t
->opcode_modifier
& D
)
1008 fprintf (stdout
, "D");
1009 if (t
->opcode_modifier
& W
)
1010 fprintf (stdout
, "W");
1011 fprintf (stdout
, "\n");
1012 for (i
= 0; i
< t
->operands
; i
++)
1014 fprintf (stdout
, " #%d type ", i
+ 1);
1015 pt (t
->operand_types
[i
]);
1016 fprintf (stdout
, "\n");
1024 fprintf (stdout
, " operation %d\n", e
->X_op
);
1025 fprintf (stdout
, " add_number %ld (%lx)\n",
1026 (long) e
->X_add_number
, (long) e
->X_add_number
);
1027 if (e
->X_add_symbol
)
1029 fprintf (stdout
, " add_symbol ");
1030 ps (e
->X_add_symbol
);
1031 fprintf (stdout
, "\n");
1035 fprintf (stdout
, " op_symbol ");
1036 ps (e
->X_op_symbol
);
1037 fprintf (stdout
, "\n");
1045 fprintf (stdout
, "%s type %s%s",
1047 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1048 segment_name (S_GET_SEGMENT (s
)));
1070 { BaseIndex
, "BaseIndex" },
1074 { Disp32S
, "d32s" },
1076 { InOutPortReg
, "InOutPortReg" },
1077 { ShiftCount
, "ShiftCount" },
1078 { Control
, "control reg" },
1079 { Test
, "test reg" },
1080 { Debug
, "debug reg" },
1081 { FloatReg
, "FReg" },
1082 { FloatAcc
, "FAcc" },
1086 { JumpAbsolute
, "Jump Absolute" },
1097 register struct type_name
*ty
;
1099 for (ty
= type_names
; ty
->mask
; ty
++)
1101 fprintf (stdout
, "%s, ", ty
->tname
);
1105 #endif /* DEBUG386 */
1108 tc_i386_force_relocation (fixp
)
1111 #ifdef BFD_ASSEMBLER
1112 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1113 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1118 return fixp
->fx_r_type
== 7;
1122 #ifdef BFD_ASSEMBLER
1124 static bfd_reloc_code_real_type
1125 reloc (size
, pcrel
, sign
, other
)
1129 bfd_reloc_code_real_type other
;
1131 if (other
!= NO_RELOC
)
1137 as_bad (_("There are no unsigned pc-relative relocations"));
1140 case 1: return BFD_RELOC_8_PCREL
;
1141 case 2: return BFD_RELOC_16_PCREL
;
1142 case 4: return BFD_RELOC_32_PCREL
;
1144 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1151 case 4: return BFD_RELOC_X86_64_32S
;
1156 case 1: return BFD_RELOC_8
;
1157 case 2: return BFD_RELOC_16
;
1158 case 4: return BFD_RELOC_32
;
1159 case 8: return BFD_RELOC_64
;
1161 as_bad (_("can not do %s %d byte relocation"),
1162 sign
? "signed" : "unsigned", size
);
1166 return BFD_RELOC_NONE
;
1169 /* Here we decide which fixups can be adjusted to make them relative to
1170 the beginning of the section instead of the symbol. Basically we need
1171 to make sure that the dynamic relocations are done correctly, so in
1172 some cases we force the original symbol to be used. */
1175 tc_i386_fix_adjustable (fixP
)
1178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1179 /* Prevent all adjustments to global symbols, or else dynamic
1180 linking will not work correctly. */
1181 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1182 || S_IS_WEAK (fixP
->fx_addsy
))
1185 /* adjust_reloc_syms doesn't know about the GOT. */
1186 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1187 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1188 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1189 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1190 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1191 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1192 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1197 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1198 #define BFD_RELOC_16 0
1199 #define BFD_RELOC_32 0
1200 #define BFD_RELOC_16_PCREL 0
1201 #define BFD_RELOC_32_PCREL 0
1202 #define BFD_RELOC_386_PLT32 0
1203 #define BFD_RELOC_386_GOT32 0
1204 #define BFD_RELOC_386_GOTOFF 0
1205 #define BFD_RELOC_X86_64_PLT32 0
1206 #define BFD_RELOC_X86_64_GOT32 0
1207 #define BFD_RELOC_X86_64_GOTPCREL 0
1210 static int intel_float_operand
PARAMS ((char *mnemonic
));
1213 intel_float_operand (mnemonic
)
1216 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1219 if (mnemonic
[0] == 'f')
1225 /* This is the guts of the machine-dependent assembler. LINE points to a
1226 machine dependent instruction. This function is supposed to emit
1227 the frags/bytes it assembles to. */
1233 /* Points to template once we've found it. */
1236 /* Count the size of the instruction generated. Does not include
1237 variable part of jump insns before relax. */
1242 char mnemonic
[MAX_MNEM_SIZE
];
1244 /* Initialize globals. */
1245 memset (&i
, '\0', sizeof (i
));
1246 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1247 i
.disp_reloc
[j
] = NO_RELOC
;
1248 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1249 memset (im_expressions
, '\0', sizeof (im_expressions
));
1250 save_stack_p
= save_stack
;
1252 /* First parse an instruction mnemonic & call i386_operand for the operands.
1253 We assume that the scrubber has arranged it so that line[0] is the valid
1254 start of a (possibly prefixed) mnemonic. */
1257 char *token_start
= l
;
1260 /* Non-zero if we found a prefix only acceptable with string insns. */
1261 const char *expecting_string_instruction
= NULL
;
1266 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1269 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1271 as_bad (_("no such instruction: `%s'"), token_start
);
1276 if (!is_space_char (*l
)
1277 && *l
!= END_OF_INSN
1278 && *l
!= PREFIX_SEPARATOR
)
1280 as_bad (_("invalid character %s in mnemonic"),
1281 output_invalid (*l
));
1284 if (token_start
== l
)
1286 if (*l
== PREFIX_SEPARATOR
)
1287 as_bad (_("expecting prefix; got nothing"));
1289 as_bad (_("expecting mnemonic; got nothing"));
1293 /* Look up instruction (or prefix) via hash table. */
1294 current_templates
= hash_find (op_hash
, mnemonic
);
1296 if (*l
!= END_OF_INSN
1297 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1298 && current_templates
1299 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1301 /* If we are in 16-bit mode, do not allow addr16 or data16.
1302 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1303 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1304 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1305 ^ (flag_code
== CODE_16BIT
)))
1307 as_bad (_("redundant %s prefix"),
1308 current_templates
->start
->name
);
1311 /* Add prefix, checking for repeated prefixes. */
1312 switch (add_prefix (current_templates
->start
->base_opcode
))
1317 expecting_string_instruction
= current_templates
->start
->name
;
1320 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1327 if (!current_templates
)
1329 /* See if we can get a match by trimming off a suffix. */
1332 case WORD_MNEM_SUFFIX
:
1333 case BYTE_MNEM_SUFFIX
:
1334 case QWORD_MNEM_SUFFIX
:
1335 i
.suffix
= mnem_p
[-1];
1337 current_templates
= hash_find (op_hash
, mnemonic
);
1339 case SHORT_MNEM_SUFFIX
:
1340 case LONG_MNEM_SUFFIX
:
1343 i
.suffix
= mnem_p
[-1];
1345 current_templates
= hash_find (op_hash
, mnemonic
);
1353 if (intel_float_operand (mnemonic
))
1354 i
.suffix
= SHORT_MNEM_SUFFIX
;
1356 i
.suffix
= LONG_MNEM_SUFFIX
;
1358 current_templates
= hash_find (op_hash
, mnemonic
);
1362 if (!current_templates
)
1364 as_bad (_("no such instruction: `%s'"), token_start
);
1369 /* Check if instruction is supported on specified architecture. */
1370 if (cpu_arch_flags
!= 0)
1372 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1373 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1375 as_warn (_("`%s' is not supported on `%s'"),
1376 current_templates
->start
->name
, cpu_arch_name
);
1378 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1380 as_warn (_("use .code16 to ensure correct addressing mode"));
1384 /* Check for rep/repne without a string instruction. */
1385 if (expecting_string_instruction
1386 && !(current_templates
->start
->opcode_modifier
& IsString
))
1388 as_bad (_("expecting string instruction after `%s'"),
1389 expecting_string_instruction
);
1393 /* There may be operands to parse. */
1394 if (*l
!= END_OF_INSN
)
1396 /* 1 if operand is pending after ','. */
1397 unsigned int expecting_operand
= 0;
1399 /* Non-zero if operand parens not balanced. */
1400 unsigned int paren_not_balanced
;
1404 /* Skip optional white space before operand. */
1405 if (is_space_char (*l
))
1407 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1409 as_bad (_("invalid character %s before operand %d"),
1410 output_invalid (*l
),
1414 token_start
= l
; /* after white space */
1415 paren_not_balanced
= 0;
1416 while (paren_not_balanced
|| *l
!= ',')
1418 if (*l
== END_OF_INSN
)
1420 if (paren_not_balanced
)
1423 as_bad (_("unbalanced parenthesis in operand %d."),
1426 as_bad (_("unbalanced brackets in operand %d."),
1431 break; /* we are done */
1433 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1435 as_bad (_("invalid character %s in operand %d"),
1436 output_invalid (*l
),
1443 ++paren_not_balanced
;
1445 --paren_not_balanced
;
1450 ++paren_not_balanced
;
1452 --paren_not_balanced
;
1456 if (l
!= token_start
)
1457 { /* Yes, we've read in another operand. */
1458 unsigned int operand_ok
;
1459 this_operand
= i
.operands
++;
1460 if (i
.operands
> MAX_OPERANDS
)
1462 as_bad (_("spurious operands; (%d operands/instruction max)"),
1466 /* Now parse operand adding info to 'i' as we go along. */
1467 END_STRING_AND_SAVE (l
);
1471 i386_intel_operand (token_start
,
1472 intel_float_operand (mnemonic
));
1474 operand_ok
= i386_operand (token_start
);
1476 RESTORE_END_STRING (l
);
1482 if (expecting_operand
)
1484 expecting_operand_after_comma
:
1485 as_bad (_("expecting operand after ','; got nothing"));
1490 as_bad (_("expecting operand before ','; got nothing"));
1495 /* Now *l must be either ',' or END_OF_INSN. */
1498 if (*++l
== END_OF_INSN
)
1500 /* Just skip it, if it's \n complain. */
1501 goto expecting_operand_after_comma
;
1503 expecting_operand
= 1;
1506 while (*l
!= END_OF_INSN
);
1510 /* Now we've parsed the mnemonic into a set of templates, and have the
1513 Next, we find a template that matches the given insn,
1514 making sure the overlap of the given operands types is consistent
1515 with the template operand types. */
1517 #define MATCH(overlap, given, template) \
1518 ((overlap & ~JumpAbsolute) \
1519 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1521 /* If given types r0 and r1 are registers they must be of the same type
1522 unless the expected operand type register overlap is null.
1523 Note that Acc in a template matches every size of reg. */
1524 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1525 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1526 ((g0) & Reg) == ((g1) & Reg) || \
1527 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1530 register unsigned int overlap0
, overlap1
;
1531 unsigned int overlap2
;
1532 unsigned int found_reverse_match
;
1535 /* All intel opcodes have reversed operands except for "bound" and
1536 "enter". We also don't reverse intersegment "jmp" and "call"
1537 instructions with 2 immediate operands so that the immediate segment
1538 precedes the offset, as it does when in AT&T mode. "enter" and the
1539 intersegment "jmp" and "call" instructions are the only ones that
1540 have two immediate operands. */
1541 if (intel_syntax
&& i
.operands
> 1
1542 && (strcmp (mnemonic
, "bound") != 0)
1543 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1545 union i386_op temp_op
;
1546 unsigned int temp_type
;
1547 #ifdef BFD_ASSEMBLER
1548 enum bfd_reloc_code_real temp_reloc
;
1555 if (i
.operands
== 2)
1560 else if (i
.operands
== 3)
1565 temp_type
= i
.types
[xchg2
];
1566 i
.types
[xchg2
] = i
.types
[xchg1
];
1567 i
.types
[xchg1
] = temp_type
;
1568 temp_op
= i
.op
[xchg2
];
1569 i
.op
[xchg2
] = i
.op
[xchg1
];
1570 i
.op
[xchg1
] = temp_op
;
1571 temp_reloc
= i
.disp_reloc
[xchg2
];
1572 i
.disp_reloc
[xchg2
] = i
.disp_reloc
[xchg1
];
1573 i
.disp_reloc
[xchg1
] = temp_reloc
;
1575 if (i
.mem_operands
== 2)
1577 const seg_entry
*temp_seg
;
1578 temp_seg
= i
.seg
[0];
1579 i
.seg
[0] = i
.seg
[1];
1580 i
.seg
[1] = temp_seg
;
1586 /* Try to ensure constant immediates are represented in the smallest
1588 char guess_suffix
= 0;
1592 guess_suffix
= i
.suffix
;
1593 else if (i
.reg_operands
)
1595 /* Figure out a suffix from the last register operand specified.
1596 We can't do this properly yet, ie. excluding InOutPortReg,
1597 but the following works for instructions with immediates.
1598 In any case, we can't set i.suffix yet. */
1599 for (op
= i
.operands
; --op
>= 0;)
1600 if (i
.types
[op
] & Reg
)
1602 if (i
.types
[op
] & Reg8
)
1603 guess_suffix
= BYTE_MNEM_SUFFIX
;
1604 else if (i
.types
[op
] & Reg16
)
1605 guess_suffix
= WORD_MNEM_SUFFIX
;
1606 else if (i
.types
[op
] & Reg32
)
1607 guess_suffix
= LONG_MNEM_SUFFIX
;
1608 else if (i
.types
[op
] & Reg64
)
1609 guess_suffix
= QWORD_MNEM_SUFFIX
;
1613 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1614 guess_suffix
= WORD_MNEM_SUFFIX
;
1616 for (op
= i
.operands
; --op
>= 0;)
1617 if (i
.types
[op
] & Imm
)
1619 switch (i
.op
[op
].imms
->X_op
)
1622 /* If a suffix is given, this operand may be shortened. */
1623 switch (guess_suffix
)
1625 case LONG_MNEM_SUFFIX
:
1626 i
.types
[op
] |= Imm32
| Imm64
;
1628 case WORD_MNEM_SUFFIX
:
1629 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1631 case BYTE_MNEM_SUFFIX
:
1632 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1636 /* If this operand is at most 16 bits, convert it
1637 to a signed 16 bit number before trying to see
1638 whether it will fit in an even smaller size.
1639 This allows a 16-bit operand such as $0xffe0 to
1640 be recognised as within Imm8S range. */
1641 if ((i
.types
[op
] & Imm16
)
1642 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1644 i
.op
[op
].imms
->X_add_number
=
1645 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1647 if ((i
.types
[op
] & Imm32
)
1648 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1650 i
.op
[op
].imms
->X_add_number
=
1651 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1653 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1654 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1655 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1656 i
.types
[op
] &= ~Imm32
;
1661 /* Symbols and expressions. */
1663 /* Convert symbolic operand to proper sizes for matching. */
1664 switch (guess_suffix
)
1666 case QWORD_MNEM_SUFFIX
:
1667 i
.types
[op
] = Imm64
| Imm32S
;
1669 case LONG_MNEM_SUFFIX
:
1670 i
.types
[op
] = Imm32
| Imm64
;
1672 case WORD_MNEM_SUFFIX
:
1673 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1676 case BYTE_MNEM_SUFFIX
:
1677 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1686 if (i
.disp_operands
)
1688 /* Try to use the smallest displacement type too. */
1691 for (op
= i
.operands
; --op
>= 0;)
1692 if ((i
.types
[op
] & Disp
)
1693 && i
.op
[op
].imms
->X_op
== O_constant
)
1695 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1697 if (i
.types
[op
] & Disp16
)
1699 /* We know this operand is at most 16 bits, so
1700 convert to a signed 16 bit number before trying
1701 to see whether it will fit in an even smaller
1704 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1706 else if (i
.types
[op
] & Disp32
)
1708 /* We know this operand is at most 32 bits, so convert to a
1709 signed 32 bit number before trying to see whether it will
1710 fit in an even smaller size. */
1711 disp
&= (((offsetT
) 2 << 31) - 1);
1712 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1714 if (flag_code
== CODE_64BIT
)
1716 if (fits_in_signed_long (disp
))
1717 i
.types
[op
] |= Disp32S
;
1718 if (fits_in_unsigned_long (disp
))
1719 i
.types
[op
] |= Disp32
;
1721 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1722 && fits_in_signed_byte (disp
))
1723 i
.types
[op
] |= Disp8
;
1730 found_reverse_match
= 0;
1731 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1733 : (i
.suffix
== WORD_MNEM_SUFFIX
1735 : (i
.suffix
== SHORT_MNEM_SUFFIX
1737 : (i
.suffix
== LONG_MNEM_SUFFIX
1739 : (i
.suffix
== QWORD_MNEM_SUFFIX
1741 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1743 for (t
= current_templates
->start
;
1744 t
< current_templates
->end
;
1747 /* Must have right number of operands. */
1748 if (i
.operands
!= t
->operands
)
1751 /* Check the suffix, except for some instructions in intel mode. */
1752 if ((t
->opcode_modifier
& suffix_check
)
1754 && (t
->opcode_modifier
& IgnoreSize
))
1756 && t
->base_opcode
== 0xd9
1757 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1758 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1761 /* Do not verify operands when there are none. */
1762 else if (!t
->operands
)
1764 if (t
->cpu_flags
& ~cpu_arch_flags
)
1766 /* We've found a match; break out of loop. */
1770 overlap0
= i
.types
[0] & t
->operand_types
[0];
1771 switch (t
->operands
)
1774 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1779 overlap1
= i
.types
[1] & t
->operand_types
[1];
1780 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1781 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1782 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1783 t
->operand_types
[0],
1784 overlap1
, i
.types
[1],
1785 t
->operand_types
[1]))
1787 /* Check if other direction is valid ... */
1788 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1791 /* Try reversing direction of operands. */
1792 overlap0
= i
.types
[0] & t
->operand_types
[1];
1793 overlap1
= i
.types
[1] & t
->operand_types
[0];
1794 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1795 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1796 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1797 t
->operand_types
[1],
1798 overlap1
, i
.types
[1],
1799 t
->operand_types
[0]))
1801 /* Does not match either direction. */
1804 /* found_reverse_match holds which of D or FloatDR
1806 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1808 /* Found a forward 2 operand match here. */
1809 else if (t
->operands
== 3)
1811 /* Here we make use of the fact that there are no
1812 reverse match 3 operand instructions, and all 3
1813 operand instructions only need to be checked for
1814 register consistency between operands 2 and 3. */
1815 overlap2
= i
.types
[2] & t
->operand_types
[2];
1816 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1817 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1818 t
->operand_types
[1],
1819 overlap2
, i
.types
[2],
1820 t
->operand_types
[2]))
1824 /* Found either forward/reverse 2 or 3 operand match here:
1825 slip through to break. */
1827 if (t
->cpu_flags
& ~cpu_arch_flags
)
1829 found_reverse_match
= 0;
1832 /* We've found a match; break out of loop. */
1835 if (t
== current_templates
->end
)
1837 /* We found no match. */
1838 as_bad (_("suffix or operands invalid for `%s'"),
1839 current_templates
->start
->name
);
1843 if (!quiet_warnings
)
1846 && ((i
.types
[0] & JumpAbsolute
)
1847 != (t
->operand_types
[0] & JumpAbsolute
)))
1849 as_warn (_("indirect %s without `*'"), t
->name
);
1852 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1853 == (IsPrefix
|IgnoreSize
))
1855 /* Warn them that a data or address size prefix doesn't
1856 affect assembly of the next line of code. */
1857 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1861 /* Copy the template we found. */
1863 if (found_reverse_match
)
1865 /* If we found a reverse match we must alter the opcode
1866 direction bit. found_reverse_match holds bits to change
1867 (different for int & float insns). */
1869 i
.tm
.base_opcode
^= found_reverse_match
;
1871 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1872 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1875 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1878 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1879 i
.tm
.base_opcode
^= FloatR
;
1881 if (i
.tm
.opcode_modifier
& FWait
)
1882 if (! add_prefix (FWAIT_OPCODE
))
1885 /* Check string instruction segment overrides. */
1886 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1888 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1889 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1891 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1893 as_bad (_("`%s' operand %d must use `%%es' segment"),
1898 /* There's only ever one segment override allowed per instruction.
1899 This instruction possibly has a legal segment override on the
1900 second operand, so copy the segment to where non-string
1901 instructions store it, allowing common code. */
1902 i
.seg
[0] = i
.seg
[1];
1904 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1906 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1908 as_bad (_("`%s' operand %d must use `%%es' segment"),
1916 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1919 for (op
= i
.operands
; --op
>= 0;)
1920 if ((i
.types
[op
] & Reg
)
1921 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1923 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1924 i
.op
[op
].regs
->reg_name
);
1929 /* If matched instruction specifies an explicit instruction mnemonic
1931 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1933 if (i
.tm
.opcode_modifier
& Size16
)
1934 i
.suffix
= WORD_MNEM_SUFFIX
;
1935 else if (i
.tm
.opcode_modifier
& Size64
)
1936 i
.suffix
= QWORD_MNEM_SUFFIX
;
1938 i
.suffix
= LONG_MNEM_SUFFIX
;
1940 else if (i
.reg_operands
)
1942 /* If there's no instruction mnemonic suffix we try to invent one
1943 based on register operands. */
1946 /* We take i.suffix from the last register operand specified,
1947 Destination register type is more significant than source
1950 for (op
= i
.operands
; --op
>= 0;)
1951 if ((i
.types
[op
] & Reg
)
1952 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1954 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1955 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1956 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1961 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1964 for (op
= i
.operands
; --op
>= 0;)
1966 /* If this is an eight bit register, it's OK. If it's
1967 the 16 or 32 bit version of an eight bit register,
1968 we will just use the low portion, and that's OK too. */
1969 if (i
.types
[op
] & Reg8
)
1972 /* movzx and movsx should not generate this warning. */
1974 && (i
.tm
.base_opcode
== 0xfb7
1975 || i
.tm
.base_opcode
== 0xfb6
1976 || i
.tm
.base_opcode
== 0x63
1977 || i
.tm
.base_opcode
== 0xfbe
1978 || i
.tm
.base_opcode
== 0xfbf))
1981 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1983 /* Check that the template allows eight bit regs
1984 This kills insns such as `orb $1,%edx', which
1985 maybe should be allowed. */
1986 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1990 /* Prohibit these changes in the 64bit mode, since
1991 the lowering is more complicated. */
1992 if (flag_code
== CODE_64BIT
1993 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1994 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1995 i
.op
[op
].regs
->reg_name
,
1997 #if REGISTER_WARNINGS
1999 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
2000 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2001 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
2002 i
.op
[op
].regs
->reg_name
,
2007 /* Any other register is bad. */
2008 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
2010 | Control
| Debug
| Test
2011 | FloatReg
| FloatAcc
))
2013 as_bad (_("`%%%s' not allowed with `%s%c'"),
2014 i
.op
[op
].regs
->reg_name
,
2021 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2025 for (op
= i
.operands
; --op
>= 0;)
2026 /* Reject eight bit registers, except where the template
2027 requires them. (eg. movzb) */
2028 if ((i
.types
[op
] & Reg8
) != 0
2029 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
2031 as_bad (_("`%%%s' not allowed with `%s%c'"),
2032 i
.op
[op
].regs
->reg_name
,
2037 /* Warn if the e prefix on a general reg is missing. */
2038 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2039 && (i
.types
[op
] & Reg16
) != 0
2040 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2042 /* Prohibit these changes in the 64bit mode, since
2043 the lowering is more complicated. */
2044 if (flag_code
== CODE_64BIT
)
2045 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2046 i
.op
[op
].regs
->reg_name
,
2048 #if REGISTER_WARNINGS
2050 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2051 (i
.op
[op
].regs
+ 8)->reg_name
,
2052 i
.op
[op
].regs
->reg_name
,
2056 /* Warn if the r prefix on a general reg is missing. */
2057 else if ((i
.types
[op
] & Reg64
) != 0
2058 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2060 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2061 i
.op
[op
].regs
->reg_name
,
2065 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2069 for (op
= i
.operands
; --op
>= 0; )
2070 /* Reject eight bit registers, except where the template
2071 requires them. (eg. movzb) */
2072 if ((i
.types
[op
] & Reg8
) != 0
2073 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2075 as_bad (_("`%%%s' not allowed with `%s%c'"),
2076 i
.op
[op
].regs
->reg_name
,
2081 /* Warn if the e prefix on a general reg is missing. */
2082 else if (((i
.types
[op
] & Reg16
) != 0
2083 || (i
.types
[op
] & Reg32
) != 0)
2084 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2086 /* Prohibit these changes in the 64bit mode, since
2087 the lowering is more complicated. */
2088 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2089 i
.op
[op
].regs
->reg_name
,
2093 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2096 for (op
= i
.operands
; --op
>= 0;)
2097 /* Reject eight bit registers, except where the template
2098 requires them. (eg. movzb) */
2099 if ((i
.types
[op
] & Reg8
) != 0
2100 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2102 as_bad (_("`%%%s' not allowed with `%s%c'"),
2103 i
.op
[op
].regs
->reg_name
,
2108 /* Warn if the e prefix on a general reg is present. */
2109 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2110 && (i
.types
[op
] & Reg32
) != 0
2111 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2113 /* Prohibit these changes in the 64bit mode, since
2114 the lowering is more complicated. */
2115 if (flag_code
== CODE_64BIT
)
2116 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2117 i
.op
[op
].regs
->reg_name
,
2120 #if REGISTER_WARNINGS
2121 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2122 (i
.op
[op
].regs
- 8)->reg_name
,
2123 i
.op
[op
].regs
->reg_name
,
2128 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2129 /* Do nothing if the instruction is going to ignore the prefix. */
2134 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2136 i
.suffix
= stackop_size
;
2138 /* Make still unresolved immediate matches conform to size of immediate
2139 given in i.suffix. Note: overlap2 cannot be an immediate! */
2140 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2141 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2142 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2143 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2147 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2148 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2149 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2151 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2152 || overlap0
== (Imm16
| Imm32
)
2153 || overlap0
== (Imm16
| Imm32S
))
2156 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2158 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2159 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2160 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2162 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2166 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2167 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2168 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2169 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2173 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2174 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2175 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2177 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2178 || overlap1
== (Imm16
| Imm32
)
2179 || overlap1
== (Imm16
| Imm32S
))
2182 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2184 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2185 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2186 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2188 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2192 assert ((overlap2
& Imm
) == 0);
2194 i
.types
[0] = overlap0
;
2195 if (overlap0
& ImplicitRegister
)
2197 if (overlap0
& Imm1
)
2198 i
.imm_operands
= 0; /* kludge for shift insns. */
2200 i
.types
[1] = overlap1
;
2201 if (overlap1
& ImplicitRegister
)
2204 i
.types
[2] = overlap2
;
2205 if (overlap2
& ImplicitRegister
)
2208 /* Finalize opcode. First, we change the opcode based on the operand
2209 size given by i.suffix: We need not change things for byte insns. */
2211 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2213 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2217 /* For movzx and movsx, need to check the register type. */
2219 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2220 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2222 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2224 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2225 if (!add_prefix (prefix
))
2229 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2231 /* It's not a byte, select word/dword operation. */
2232 if (i
.tm
.opcode_modifier
& W
)
2234 if (i
.tm
.opcode_modifier
& ShortForm
)
2235 i
.tm
.base_opcode
|= 8;
2237 i
.tm
.base_opcode
|= 1;
2239 /* Now select between word & dword operations via the operand
2240 size prefix, except for instructions that will ignore this
2242 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2243 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2244 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2246 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2247 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2248 prefix
= ADDR_PREFIX_OPCODE
;
2250 if (! add_prefix (prefix
))
2254 /* Set mode64 for an operand. */
2255 if (i
.suffix
== QWORD_MNEM_SUFFIX
2256 && !(i
.tm
.opcode_modifier
& NoRex64
))
2259 if (flag_code
< CODE_64BIT
)
2261 as_bad (_("64bit operations available only in 64bit modes."));
2266 /* Size floating point instruction. */
2267 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2269 if (i
.tm
.opcode_modifier
& FloatMF
)
2270 i
.tm
.base_opcode
^= 4;
2274 if (i
.tm
.opcode_modifier
& ImmExt
)
2276 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2277 opcode suffix which is coded in the same place as an 8-bit
2278 immediate field would be. Here we fake an 8-bit immediate
2279 operand from the opcode suffix stored in tm.extension_opcode. */
2283 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2285 exp
= &im_expressions
[i
.imm_operands
++];
2286 i
.op
[i
.operands
].imms
= exp
;
2287 i
.types
[i
.operands
++] = Imm8
;
2288 exp
->X_op
= O_constant
;
2289 exp
->X_add_number
= i
.tm
.extension_opcode
;
2290 i
.tm
.extension_opcode
= None
;
2293 /* For insns with operands there are more diddles to do to the opcode. */
2296 /* Default segment register this instruction will use
2297 for memory accesses. 0 means unknown.
2298 This is only for optimizing out unnecessary segment overrides. */
2299 const seg_entry
*default_seg
= 0;
2301 /* The imul $imm, %reg instruction is converted into
2302 imul $imm, %reg, %reg, and the clr %reg instruction
2303 is converted into xor %reg, %reg. */
2304 if (i
.tm
.opcode_modifier
& regKludge
)
2306 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2307 /* Pretend we saw the extra register operand. */
2308 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2309 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2310 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2314 if (i
.tm
.opcode_modifier
& ShortForm
)
2316 /* The register or float register operand is in operand 0 or 1. */
2317 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2318 /* Register goes in low 3 bits of opcode. */
2319 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2320 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2322 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2324 /* Warn about some common errors, but press on regardless.
2325 The first case can be generated by gcc (<= 2.8.1). */
2326 if (i
.operands
== 2)
2328 /* Reversed arguments on faddp, fsubp, etc. */
2329 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2330 i
.op
[1].regs
->reg_name
,
2331 i
.op
[0].regs
->reg_name
);
2335 /* Extraneous `l' suffix on fp insn. */
2336 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2337 i
.op
[0].regs
->reg_name
);
2341 else if (i
.tm
.opcode_modifier
& Modrm
)
2343 /* The opcode is completed (modulo i.tm.extension_opcode which
2344 must be put into the modrm byte).
2345 Now, we make the modrm & index base bytes based on all the
2346 info we've collected. */
2348 /* i.reg_operands MUST be the number of real register operands;
2349 implicit registers do not count. */
2350 if (i
.reg_operands
== 2)
2352 unsigned int source
, dest
;
2353 source
= ((i
.types
[0]
2354 & (Reg
| RegMMX
| RegXMM
2356 | Control
| Debug
| Test
))
2361 /* One of the register operands will be encoded in the
2362 i.tm.reg field, the other in the combined i.tm.mode
2363 and i.tm.regmem fields. If no form of this
2364 instruction supports a memory destination operand,
2365 then we assume the source operand may sometimes be
2366 a memory operand and so we need to store the
2367 destination in the i.rm.reg field. */
2368 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2370 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2371 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2372 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2374 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2379 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2380 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2381 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2383 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2388 { /* If it's not 2 reg operands... */
2391 unsigned int fake_zero_displacement
= 0;
2392 unsigned int op
= ((i
.types
[0] & AnyMem
)
2394 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2401 if (! i
.disp_operands
)
2402 fake_zero_displacement
= 1;
2405 /* Operand is just <disp> */
2406 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2408 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2409 i
.types
[op
] &= ~Disp
;
2410 i
.types
[op
] |= Disp16
;
2412 else if (flag_code
!= CODE_64BIT
)
2414 i
.rm
.regmem
= NO_BASE_REGISTER
;
2415 i
.types
[op
] &= ~Disp
;
2416 i
.types
[op
] |= Disp32
;
2420 /* 64bit mode overwrites the 32bit
2421 absolute addressing by RIP relative
2422 addressing and absolute addressing
2423 is encoded by one of the redundant
2426 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2427 i
.sib
.base
= NO_BASE_REGISTER
;
2428 i
.sib
.index
= NO_INDEX_REGISTER
;
2429 i
.types
[op
] &= ~Disp
;
2430 i
.types
[op
] |= Disp32S
;
2433 else /* ! i.base_reg && i.index_reg */
2435 i
.sib
.index
= i
.index_reg
->reg_num
;
2436 i
.sib
.base
= NO_BASE_REGISTER
;
2437 i
.sib
.scale
= i
.log2_scale_factor
;
2438 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2439 i
.types
[op
] &= ~Disp
;
2440 if (flag_code
!= CODE_64BIT
)
2441 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2443 i
.types
[op
] |= Disp32S
;
2444 if (i
.index_reg
->reg_flags
& RegRex
)
2448 /* RIP addressing for 64bit mode. */
2449 else if (i
.base_reg
->reg_type
== BaseIndex
)
2451 i
.rm
.regmem
= NO_BASE_REGISTER
;
2452 i
.types
[op
] &= ~Disp
;
2453 i
.types
[op
] |= Disp32S
;
2454 i
.flags
[op
] = Operand_PCrel
;
2456 else if (i
.base_reg
->reg_type
& Reg16
)
2458 switch (i
.base_reg
->reg_num
)
2463 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2464 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2471 if ((i
.types
[op
] & Disp
) == 0)
2473 /* fake (%bp) into 0(%bp) */
2474 i
.types
[op
] |= Disp8
;
2475 fake_zero_displacement
= 1;
2478 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2479 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2481 default: /* (%si) -> 4 or (%di) -> 5 */
2482 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2484 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2486 else /* i.base_reg and 32/64 bit mode */
2488 if (flag_code
== CODE_64BIT
2489 && (i
.types
[op
] & Disp
))
2491 if (i
.types
[op
] & Disp8
)
2492 i
.types
[op
] = Disp8
| Disp32S
;
2494 i
.types
[op
] = Disp32S
;
2496 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2497 if (i
.base_reg
->reg_flags
& RegRex
)
2499 i
.sib
.base
= i
.base_reg
->reg_num
;
2500 /* x86-64 ignores REX prefix bit here to avoid
2501 decoder complications. */
2502 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2505 if (i
.disp_operands
== 0)
2507 fake_zero_displacement
= 1;
2508 i
.types
[op
] |= Disp8
;
2511 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2515 i
.sib
.scale
= i
.log2_scale_factor
;
2518 /* <disp>(%esp) becomes two byte modrm
2519 with no index register. We've already
2520 stored the code for esp in i.rm.regmem
2521 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2522 base register besides %esp will not use
2523 the extra modrm byte. */
2524 i
.sib
.index
= NO_INDEX_REGISTER
;
2525 #if ! SCALE1_WHEN_NO_INDEX
2526 /* Another case where we force the second
2528 if (i
.log2_scale_factor
)
2529 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2534 i
.sib
.index
= i
.index_reg
->reg_num
;
2535 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2536 if (i
.index_reg
->reg_flags
& RegRex
)
2539 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2542 if (fake_zero_displacement
)
2544 /* Fakes a zero displacement assuming that i.types[op]
2545 holds the correct displacement size. */
2548 assert (i
.op
[op
].disps
== 0);
2549 exp
= &disp_expressions
[i
.disp_operands
++];
2550 i
.op
[op
].disps
= exp
;
2551 exp
->X_op
= O_constant
;
2552 exp
->X_add_number
= 0;
2553 exp
->X_add_symbol
= (symbolS
*) 0;
2554 exp
->X_op_symbol
= (symbolS
*) 0;
2558 /* Fill in i.rm.reg or i.rm.regmem field with register
2559 operand (if any) based on i.tm.extension_opcode.
2560 Again, we must be careful to make sure that
2561 segment/control/debug/test/MMX registers are coded
2562 into the i.rm.reg field. */
2567 & (Reg
| RegMMX
| RegXMM
2569 | Control
| Debug
| Test
))
2572 & (Reg
| RegMMX
| RegXMM
2574 | Control
| Debug
| Test
))
2577 /* If there is an extension opcode to put here, the
2578 register number must be put into the regmem field. */
2579 if (i
.tm
.extension_opcode
!= None
)
2581 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2582 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2587 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2588 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2592 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2593 we must set it to 3 to indicate this is a register
2594 operand in the regmem field. */
2595 if (!i
.mem_operands
)
2599 /* Fill in i.rm.reg field with extension opcode (if any). */
2600 if (i
.tm
.extension_opcode
!= None
)
2601 i
.rm
.reg
= i
.tm
.extension_opcode
;
2604 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2606 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2607 && i
.op
[0].regs
->reg_num
== 1)
2609 as_bad (_("you can't `pop %%cs'"));
2612 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2613 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2616 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2620 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2622 /* For the string instructions that allow a segment override
2623 on one of their operands, the default segment is ds. */
2627 /* If a segment was explicitly specified,
2628 and the specified segment is not the default,
2629 use an opcode prefix to select it.
2630 If we never figured out what the default segment is,
2631 then default_seg will be zero at this point,
2632 and the specified segment prefix will always be used. */
2633 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2635 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2639 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2641 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2642 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2646 /* Handle conversion of 'int $3' --> special int3 insn. */
2647 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2649 i
.tm
.base_opcode
= INT3_OPCODE
;
2653 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2654 && i
.op
[0].disps
->X_op
== O_constant
)
2656 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2657 the absolute address given by the constant. Since ix86 jumps and
2658 calls are pc relative, we need to generate a reloc. */
2659 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2660 i
.op
[0].disps
->X_op
= O_symbol
;
2663 if (i
.tm
.opcode_modifier
& Rex64
)
2666 /* For 8bit registers we would need an empty rex prefix.
2667 Also in the case instruction is already having prefix,
2668 we need to convert old registers to new ones. */
2670 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2671 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2672 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2673 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2677 for (x
= 0; x
< 2; x
++)
2679 /* Look for 8bit operand that does use old registers. */
2680 if (i
.types
[x
] & Reg8
2681 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2683 /* In case it is "hi" register, give up. */
2684 if (i
.op
[x
].regs
->reg_num
> 3)
2685 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2686 i
.op
[x
].regs
->reg_name
);
2688 /* Otherwise it is equivalent to the extended register.
2689 Since the encoding don't change this is merely cosmetical
2690 cleanup for debug output. */
2692 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2697 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2699 | (i
.rex
.mode64
? 8 : 0)
2700 | (i
.rex
.extX
? 4 : 0)
2701 | (i
.rex
.extY
? 2 : 0)
2702 | (i
.rex
.extZ
? 1 : 0));
2704 /* We are ready to output the insn. */
2709 if (i
.tm
.opcode_modifier
& Jump
)
2715 if (flag_code
== CODE_16BIT
)
2719 if (i
.prefix
[DATA_PREFIX
])
2725 if (i
.prefix
[REX_PREFIX
])
2731 if (i
.prefixes
!= 0 && !intel_syntax
)
2732 as_warn (_("skipping prefixes on this instruction"));
2734 /* It's always a symbol; End frag & setup for relax.
2735 Make sure there is enough room in this frag for the largest
2736 instruction we may generate in md_convert_frag. This is 2
2737 bytes for the opcode and room for the prefix and largest
2739 frag_grow (prefix
+ 2 + 4);
2740 insn_size
+= prefix
+ 1;
2741 /* Prefix and 1 opcode byte go in fr_fix. */
2742 p
= frag_more (prefix
+ 1);
2743 if (i
.prefix
[DATA_PREFIX
])
2744 *p
++ = DATA_PREFIX_OPCODE
;
2745 if (i
.prefix
[REX_PREFIX
])
2746 *p
++ = i
.prefix
[REX_PREFIX
];
2747 *p
= i
.tm
.base_opcode
;
2748 /* 1 possible extra opcode + displacement go in var part.
2749 Pass reloc in fr_var. */
2750 frag_var (rs_machine_dependent
,
2753 ((unsigned char) *p
== JUMP_PC_RELATIVE
2754 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2755 : ((cpu_arch_flags
& Cpu386
) != 0
2756 ? ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
2757 : ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
) | code16
)),
2758 i
.op
[0].disps
->X_add_symbol
,
2759 i
.op
[0].disps
->X_add_number
,
2762 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2766 if (i
.tm
.opcode_modifier
& JumpByte
)
2768 /* This is a loop or jecxz type instruction. */
2770 if (i
.prefix
[ADDR_PREFIX
])
2773 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2782 if (flag_code
== CODE_16BIT
)
2785 if (i
.prefix
[DATA_PREFIX
])
2788 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2798 if (i
.prefix
[REX_PREFIX
])
2800 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2805 if (i
.prefixes
!= 0 && !intel_syntax
)
2806 as_warn (_("skipping prefixes on this instruction"));
2808 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2810 insn_size
+= 1 + size
;
2811 p
= frag_more (1 + size
);
2815 /* Opcode can be at most two bytes. */
2816 insn_size
+= 2 + size
;
2817 p
= frag_more (2 + size
);
2818 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2820 *p
++ = i
.tm
.base_opcode
& 0xff;
2822 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2823 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.disp_reloc
[0]));
2825 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2832 if (flag_code
== CODE_16BIT
)
2836 if (i
.prefix
[DATA_PREFIX
])
2842 if (i
.prefix
[REX_PREFIX
])
2852 if (i
.prefixes
!= 0 && !intel_syntax
)
2853 as_warn (_("skipping prefixes on this instruction"));
2855 /* 1 opcode; 2 segment; offset */
2856 insn_size
+= prefix
+ 1 + 2 + size
;
2857 p
= frag_more (prefix
+ 1 + 2 + size
);
2859 if (i
.prefix
[DATA_PREFIX
])
2860 *p
++ = DATA_PREFIX_OPCODE
;
2862 if (i
.prefix
[REX_PREFIX
])
2863 *p
++ = i
.prefix
[REX_PREFIX
];
2865 *p
++ = i
.tm
.base_opcode
;
2866 if (i
.op
[1].imms
->X_op
== O_constant
)
2868 offsetT n
= i
.op
[1].imms
->X_add_number
;
2871 && !fits_in_unsigned_word (n
)
2872 && !fits_in_signed_word (n
))
2874 as_bad (_("16-bit jump out of range"));
2877 md_number_to_chars (p
, n
, size
);
2880 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2881 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.disp_reloc
[0]));
2882 if (i
.op
[0].imms
->X_op
!= O_constant
)
2883 as_bad (_("can't handle non absolute segment in `%s'"),
2885 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2889 /* Output normal instructions here. */
2892 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2893 byte for the SSE instructions to specify prefix they require. */
2894 if (i
.tm
.base_opcode
& 0xff0000)
2895 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2897 /* The prefix bytes. */
2899 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2906 md_number_to_chars (p
, (valueT
) *q
, 1);
2910 /* Now the opcode; be careful about word order here! */
2911 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2914 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2920 /* Put out high byte first: can't use md_number_to_chars! */
2921 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2922 *p
= i
.tm
.base_opcode
& 0xff;
2925 /* Now the modrm byte and sib byte (if present). */
2926 if (i
.tm
.opcode_modifier
& Modrm
)
2930 md_number_to_chars (p
,
2931 (valueT
) (i
.rm
.regmem
<< 0
2935 /* If i.rm.regmem == ESP (4)
2936 && i.rm.mode != (Register mode)
2938 ==> need second modrm byte. */
2939 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2941 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2945 md_number_to_chars (p
,
2946 (valueT
) (i
.sib
.base
<< 0
2948 | i
.sib
.scale
<< 6),
2953 if (i
.disp_operands
)
2955 register unsigned int n
;
2957 for (n
= 0; n
< i
.operands
; n
++)
2959 if (i
.types
[n
] & Disp
)
2961 if (i
.op
[n
].disps
->X_op
== O_constant
)
2967 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2970 if (i
.types
[n
] & Disp8
)
2972 if (i
.types
[n
] & Disp64
)
2975 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2978 p
= frag_more (size
);
2979 md_number_to_chars (p
, val
, size
);
2985 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2987 /* The PC relative address is computed relative
2988 to the instruction boundary, so in case immediate
2989 fields follows, we need to adjust the value. */
2990 if (pcrel
&& i
.imm_operands
)
2993 register unsigned int n1
;
2995 for (n1
= 0; n1
< i
.operands
; n1
++)
2996 if (i
.types
[n1
] & Imm
)
2998 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3001 if (i
.types
[n1
] & (Imm8
| Imm8S
))
3003 if (i
.types
[n1
] & Imm64
)
3008 /* We should find the immediate. */
3009 if (n1
== i
.operands
)
3011 i
.op
[n
].disps
->X_add_number
-= imm_size
;
3014 if (i
.types
[n
] & Disp32S
)
3017 if (i
.types
[n
] & (Disp16
| Disp64
))
3020 if (i
.types
[n
] & Disp64
)
3025 p
= frag_more (size
);
3026 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3027 i
.op
[n
].disps
, pcrel
,
3028 reloc (size
, pcrel
, sign
, i
.disp_reloc
[n
]));
3034 /* Output immediate. */
3037 register unsigned int n
;
3039 for (n
= 0; n
< i
.operands
; n
++)
3041 if (i
.types
[n
] & Imm
)
3043 if (i
.op
[n
].imms
->X_op
== O_constant
)
3049 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3052 if (i
.types
[n
] & (Imm8
| Imm8S
))
3054 else if (i
.types
[n
] & Imm64
)
3057 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3060 p
= frag_more (size
);
3061 md_number_to_chars (p
, val
, size
);
3065 /* Not absolute_section.
3066 Need a 32-bit fixup (don't support 8bit
3067 non-absolute imms). Try to support other
3069 #ifdef BFD_ASSEMBLER
3070 enum bfd_reloc_code_real reloc_type
;
3077 if ((i
.types
[n
] & (Imm32S
))
3078 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3080 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3083 if (i
.types
[n
] & (Imm8
| Imm8S
))
3085 if (i
.types
[n
] & Imm64
)
3090 p
= frag_more (size
);
3091 reloc_type
= reloc (size
, 0, sign
, i
.disp_reloc
[0]);
3092 #ifdef BFD_ASSEMBLER
3093 if (reloc_type
== BFD_RELOC_32
3095 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3096 && (i
.op
[n
].imms
->X_op
== O_symbol
3097 || (i
.op
[n
].imms
->X_op
== O_add
3098 && ((symbol_get_value_expression
3099 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3102 /* We don't support dynamic linking on x86-64 yet. */
3103 if (flag_code
== CODE_64BIT
)
3105 reloc_type
= BFD_RELOC_386_GOTPC
;
3106 i
.op
[n
].imms
->X_add_number
+= 3;
3109 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3110 i
.op
[n
].imms
, 0, reloc_type
);
3117 dwarf2_emit_insn (insn_size
);
3124 #endif /* DEBUG386 */
3128 static int i386_immediate
PARAMS ((char *));
3131 i386_immediate (imm_start
)
3134 char *save_input_line_pointer
;
3138 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3140 as_bad (_("only 1 or 2 immediate operands are allowed"));
3144 exp
= &im_expressions
[i
.imm_operands
++];
3145 i
.op
[this_operand
].imms
= exp
;
3147 if (is_space_char (*imm_start
))
3150 save_input_line_pointer
= input_line_pointer
;
3151 input_line_pointer
= imm_start
;
3155 /* We can have operands of the form
3156 <symbol>@GOTOFF+<nnn>
3157 Take the easy way out here and copy everything
3158 into a temporary buffer... */
3161 cp
= strchr (input_line_pointer
, '@');
3168 /* GOT relocations are not supported in 16 bit mode. */
3169 if (flag_code
== CODE_16BIT
)
3170 as_bad (_("GOT relocations not supported in 16 bit mode"));
3172 if (GOT_symbol
== NULL
)
3173 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3175 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3177 if (flag_code
== CODE_64BIT
)
3178 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3180 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3183 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3185 if (flag_code
== CODE_64BIT
)
3186 as_bad ("GOTOFF relocations are unsupported in 64bit mode.");
3187 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3190 else if (strncmp (cp
+ 1, "GOTPCREL", 8) == 0)
3192 if (flag_code
== CODE_64BIT
)
3193 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3195 as_bad ("GOTPCREL relocations are supported only in 64bit mode.");
3198 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3200 if (flag_code
== CODE_64BIT
)
3201 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3203 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3207 as_bad (_("bad reloc specifier in expression"));
3209 /* Replace the relocation token with ' ', so that errors like
3210 foo@GOTOFF1 will be detected. */
3211 first
= cp
- input_line_pointer
;
3212 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3213 memcpy (tmpbuf
, input_line_pointer
, first
);
3214 tmpbuf
[first
] = ' ';
3215 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3216 input_line_pointer
= tmpbuf
;
3221 exp_seg
= expression (exp
);
3224 if (*input_line_pointer
)
3225 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
3227 input_line_pointer
= save_input_line_pointer
;
3229 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3231 /* Missing or bad expr becomes absolute 0. */
3232 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3234 exp
->X_op
= O_constant
;
3235 exp
->X_add_number
= 0;
3236 exp
->X_add_symbol
= (symbolS
*) 0;
3237 exp
->X_op_symbol
= (symbolS
*) 0;
3239 else if (exp
->X_op
== O_constant
)
3241 /* Size it properly later. */
3242 i
.types
[this_operand
] |= Imm64
;
3243 /* If BFD64, sign extend val. */
3244 if (!use_rela_relocations
)
3245 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3246 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3248 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3250 #ifdef BFD_ASSEMBLER
3251 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3253 && exp_seg
!= text_section
3254 && exp_seg
!= data_section
3255 && exp_seg
!= bss_section
3256 && exp_seg
!= undefined_section
3257 #ifdef BFD_ASSEMBLER
3258 && !bfd_is_com_section (exp_seg
)
3262 #ifdef BFD_ASSEMBLER
3263 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3265 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3272 /* This is an address. The size of the address will be
3273 determined later, depending on destination register,
3274 suffix, or the default for the section. */
3275 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3281 static int i386_scale
PARAMS ((char *));
3287 if (!isdigit (*scale
))
3294 i
.log2_scale_factor
= 0;
3297 i
.log2_scale_factor
= 1;
3300 i
.log2_scale_factor
= 2;
3303 i
.log2_scale_factor
= 3;
3307 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3311 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3313 as_warn (_("scale factor of %d without an index register"),
3314 1 << i
.log2_scale_factor
);
3315 #if SCALE1_WHEN_NO_INDEX
3316 i
.log2_scale_factor
= 0;
3322 static int i386_displacement
PARAMS ((char *, char *));
3325 i386_displacement (disp_start
, disp_end
)
3329 register expressionS
*exp
;
3331 char *save_input_line_pointer
;
3332 int bigdisp
= Disp32
;
3334 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3336 if (flag_code
== CODE_64BIT
)
3338 i
.types
[this_operand
] |= bigdisp
;
3340 exp
= &disp_expressions
[i
.disp_operands
];
3341 i
.op
[this_operand
].disps
= exp
;
3343 save_input_line_pointer
= input_line_pointer
;
3344 input_line_pointer
= disp_start
;
3345 END_STRING_AND_SAVE (disp_end
);
3347 #ifndef GCC_ASM_O_HACK
3348 #define GCC_ASM_O_HACK 0
3351 END_STRING_AND_SAVE (disp_end
+ 1);
3352 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3353 && displacement_string_end
[-1] == '+')
3355 /* This hack is to avoid a warning when using the "o"
3356 constraint within gcc asm statements.
3359 #define _set_tssldt_desc(n,addr,limit,type) \
3360 __asm__ __volatile__ ( \
3362 "movw %w1,2+%0\n\t" \
3364 "movb %b1,4+%0\n\t" \
3365 "movb %4,5+%0\n\t" \
3366 "movb $0,6+%0\n\t" \
3367 "movb %h1,7+%0\n\t" \
3369 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3371 This works great except that the output assembler ends
3372 up looking a bit weird if it turns out that there is
3373 no offset. You end up producing code that looks like:
3386 So here we provide the missing zero. */
3388 *displacement_string_end
= '0';
3393 /* We can have operands of the form
3394 <symbol>@GOTOFF+<nnn>
3395 Take the easy way out here and copy everything
3396 into a temporary buffer... */
3399 cp
= strchr (input_line_pointer
, '@');
3406 /* GOT relocations are not supported in 16 bit mode. */
3407 if (flag_code
== CODE_16BIT
)
3408 as_bad (_("GOT relocations not supported in 16 bit mode"));
3410 if (GOT_symbol
== NULL
)
3411 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3413 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3415 if (flag_code
== CODE_64BIT
)
3416 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3418 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3421 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3423 if (flag_code
== CODE_64BIT
)
3424 as_bad ("GOTOFF relocation is not supported in 64bit mode.");
3425 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3428 else if (strncmp (cp
+ 1, "GOTPCREL", 8) == 0)
3430 if (flag_code
!= CODE_64BIT
)
3431 as_bad ("GOTPCREL relocation is supported only in 64bit mode.");
3432 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3435 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3437 if (flag_code
== CODE_64BIT
)
3438 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3440 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3444 as_bad (_("bad reloc specifier in expression"));
3446 /* Replace the relocation token with ' ', so that errors like
3447 foo@GOTOFF1 will be detected. */
3448 first
= cp
- input_line_pointer
;
3449 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3450 memcpy (tmpbuf
, input_line_pointer
, first
);
3451 tmpbuf
[first
] = ' ';
3452 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3453 input_line_pointer
= tmpbuf
;
3458 exp_seg
= expression (exp
);
3460 #ifdef BFD_ASSEMBLER
3461 /* We do this to make sure that the section symbol is in
3462 the symbol table. We will ultimately change the relocation
3463 to be relative to the beginning of the section. */
3464 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3465 || i
.disp_reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3467 if (S_IS_LOCAL (exp
->X_add_symbol
)
3468 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3469 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3470 assert (exp
->X_op
== O_symbol
);
3471 exp
->X_op
= O_subtract
;
3472 exp
->X_op_symbol
= GOT_symbol
;
3473 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3474 i
.disp_reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
3476 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
3481 if (*input_line_pointer
)
3482 as_bad (_("ignoring junk `%s' after expression"),
3483 input_line_pointer
);
3485 RESTORE_END_STRING (disp_end
+ 1);
3487 RESTORE_END_STRING (disp_end
);
3488 input_line_pointer
= save_input_line_pointer
;
3490 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3492 /* Missing or bad expr becomes absolute 0. */
3493 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3495 exp
->X_op
= O_constant
;
3496 exp
->X_add_number
= 0;
3497 exp
->X_add_symbol
= (symbolS
*) 0;
3498 exp
->X_op_symbol
= (symbolS
*) 0;
3501 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3502 if (exp
->X_op
!= O_constant
3503 #ifdef BFD_ASSEMBLER
3504 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3506 && exp_seg
!= text_section
3507 && exp_seg
!= data_section
3508 && exp_seg
!= bss_section
3509 && exp_seg
!= undefined_section
)
3511 #ifdef BFD_ASSEMBLER
3512 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3514 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3519 else if (flag_code
== CODE_64BIT
)
3520 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3524 static int i386_index_check
PARAMS ((const char *));
3526 /* Make sure the memory operand we've been dealt is valid.
3527 Return 1 on success, 0 on a failure. */
3530 i386_index_check (operand_string
)
3531 const char *operand_string
;
3534 #if INFER_ADDR_PREFIX
3540 if (flag_code
== CODE_64BIT
)
3544 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3545 && (i
.base_reg
->reg_type
!= BaseIndex
3548 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3549 != (Reg64
|BaseIndex
))))
3554 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3558 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3559 != (Reg16
|BaseIndex
)))
3561 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3562 != (Reg16
|BaseIndex
))
3564 && i
.base_reg
->reg_num
< 6
3565 && i
.index_reg
->reg_num
>= 6
3566 && i
.log2_scale_factor
== 0))))
3573 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3575 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3576 != (Reg32
|BaseIndex
))))
3582 #if INFER_ADDR_PREFIX
3583 if (flag_code
!= CODE_64BIT
3584 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3586 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3588 /* Change the size of any displacement too. At most one of
3589 Disp16 or Disp32 is set.
3590 FIXME. There doesn't seem to be any real need for separate
3591 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3592 Removing them would probably clean up the code quite a lot. */
3593 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3594 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3599 as_bad (_("`%s' is not a valid base/index expression"),
3603 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3605 flag_code_names
[flag_code
]);
3611 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3615 i386_operand (operand_string
)
3616 char *operand_string
;
3620 char *op_string
= operand_string
;
3622 if (is_space_char (*op_string
))
3625 /* We check for an absolute prefix (differentiating,
3626 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3627 if (*op_string
== ABSOLUTE_PREFIX
)
3630 if (is_space_char (*op_string
))
3632 i
.types
[this_operand
] |= JumpAbsolute
;
3635 /* Check if operand is a register. */
3636 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3637 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3639 /* Check for a segment override by searching for ':' after a
3640 segment register. */
3642 if (is_space_char (*op_string
))
3644 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3649 i
.seg
[i
.mem_operands
] = &es
;
3652 i
.seg
[i
.mem_operands
] = &cs
;
3655 i
.seg
[i
.mem_operands
] = &ss
;
3658 i
.seg
[i
.mem_operands
] = &ds
;
3661 i
.seg
[i
.mem_operands
] = &fs
;
3664 i
.seg
[i
.mem_operands
] = &gs
;
3668 /* Skip the ':' and whitespace. */
3670 if (is_space_char (*op_string
))
3673 if (!is_digit_char (*op_string
)
3674 && !is_identifier_char (*op_string
)
3675 && *op_string
!= '('
3676 && *op_string
!= ABSOLUTE_PREFIX
)
3678 as_bad (_("bad memory operand `%s'"), op_string
);
3681 /* Handle case of %es:*foo. */
3682 if (*op_string
== ABSOLUTE_PREFIX
)
3685 if (is_space_char (*op_string
))
3687 i
.types
[this_operand
] |= JumpAbsolute
;
3689 goto do_memory_reference
;
3693 as_bad (_("junk `%s' after register"), op_string
);
3696 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3697 i
.op
[this_operand
].regs
= r
;
3700 else if (*op_string
== REGISTER_PREFIX
)
3702 as_bad (_("bad register name `%s'"), op_string
);
3705 else if (*op_string
== IMMEDIATE_PREFIX
)
3708 if (i
.types
[this_operand
] & JumpAbsolute
)
3710 as_bad (_("immediate operand illegal with absolute jump"));
3713 if (!i386_immediate (op_string
))
3716 else if (is_digit_char (*op_string
)
3717 || is_identifier_char (*op_string
)
3718 || *op_string
== '(')
3720 /* This is a memory reference of some sort. */
3723 /* Start and end of displacement string expression (if found). */
3724 char *displacement_string_start
;
3725 char *displacement_string_end
;
3727 do_memory_reference
:
3728 if ((i
.mem_operands
== 1
3729 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3730 || i
.mem_operands
== 2)
3732 as_bad (_("too many memory references for `%s'"),
3733 current_templates
->start
->name
);
3737 /* Check for base index form. We detect the base index form by
3738 looking for an ')' at the end of the operand, searching
3739 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3741 base_string
= op_string
+ strlen (op_string
);
3744 if (is_space_char (*base_string
))
3747 /* If we only have a displacement, set-up for it to be parsed later. */
3748 displacement_string_start
= op_string
;
3749 displacement_string_end
= base_string
+ 1;
3751 if (*base_string
== ')')
3754 unsigned int parens_balanced
= 1;
3755 /* We've already checked that the number of left & right ()'s are
3756 equal, so this loop will not be infinite. */
3760 if (*base_string
== ')')
3762 if (*base_string
== '(')
3765 while (parens_balanced
);
3767 temp_string
= base_string
;
3769 /* Skip past '(' and whitespace. */
3771 if (is_space_char (*base_string
))
3774 if (*base_string
== ','
3775 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3776 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3778 displacement_string_end
= temp_string
;
3780 i
.types
[this_operand
] |= BaseIndex
;
3784 base_string
= end_op
;
3785 if (is_space_char (*base_string
))
3789 /* There may be an index reg or scale factor here. */
3790 if (*base_string
== ',')
3793 if (is_space_char (*base_string
))
3796 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3797 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3799 base_string
= end_op
;
3800 if (is_space_char (*base_string
))
3802 if (*base_string
== ',')
3805 if (is_space_char (*base_string
))
3808 else if (*base_string
!= ')')
3810 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3815 else if (*base_string
== REGISTER_PREFIX
)
3817 as_bad (_("bad register name `%s'"), base_string
);
3821 /* Check for scale factor. */
3822 if (isdigit ((unsigned char) *base_string
))
3824 if (!i386_scale (base_string
))
3828 if (is_space_char (*base_string
))
3830 if (*base_string
!= ')')
3832 as_bad (_("expecting `)' after scale factor in `%s'"),
3837 else if (!i
.index_reg
)
3839 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3844 else if (*base_string
!= ')')
3846 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3851 else if (*base_string
== REGISTER_PREFIX
)
3853 as_bad (_("bad register name `%s'"), base_string
);
3858 /* If there's an expression beginning the operand, parse it,
3859 assuming displacement_string_start and
3860 displacement_string_end are meaningful. */
3861 if (displacement_string_start
!= displacement_string_end
)
3863 if (!i386_displacement (displacement_string_start
,
3864 displacement_string_end
))
3868 /* Special case for (%dx) while doing input/output op. */
3870 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3872 && i
.log2_scale_factor
== 0
3873 && i
.seg
[i
.mem_operands
] == 0
3874 && (i
.types
[this_operand
] & Disp
) == 0)
3876 i
.types
[this_operand
] = InOutPortReg
;
3880 if (i386_index_check (operand_string
) == 0)
3886 /* It's not a memory operand; argh! */
3887 as_bad (_("invalid char %s beginning operand %d `%s'"),
3888 output_invalid (*op_string
),
3893 return 1; /* Normal return. */
3896 /* md_estimate_size_before_relax()
3898 Called just before relax() for rs_machine_dependent frags. The x86
3899 assembler uses these frags to handle variable size jump
3902 Any symbol that is now undefined will not become defined.
3903 Return the correct fr_subtype in the frag.
3904 Return the initial "guess for variable size of frag" to caller.
3905 The guess is actually the growth beyond the fixed part. Whatever
3906 we do to grow the fixed or variable part contributes to our
3910 md_estimate_size_before_relax (fragP
, segment
)
3911 register fragS
*fragP
;
3912 register segT segment
;
3914 /* We've already got fragP->fr_subtype right; all we have to do is
3915 check for un-relaxable symbols. On an ELF system, we can't relax
3916 an externally visible symbol, because it may be overridden by a
3918 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3919 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3920 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3921 || S_IS_WEAK (fragP
->fr_symbol
)
3925 /* Symbol is undefined in this segment, or we need to keep a
3926 reloc so that weak symbols can be overridden. */
3927 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3928 #ifdef BFD_ASSEMBLER
3929 enum bfd_reloc_code_real reloc_type
;
3933 unsigned char *opcode
;
3936 if (fragP
->fr_var
!= NO_RELOC
)
3937 reloc_type
= fragP
->fr_var
;
3939 reloc_type
= BFD_RELOC_16_PCREL
;
3941 reloc_type
= BFD_RELOC_32_PCREL
;
3943 old_fr_fix
= fragP
->fr_fix
;
3944 opcode
= (unsigned char *) fragP
->fr_opcode
;
3946 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
3949 /* Make jmp (0xeb) a (d)word displacement jump. */
3951 fragP
->fr_fix
+= size
;
3952 fix_new (fragP
, old_fr_fix
, size
,
3954 fragP
->fr_offset
, 1,
3959 if (no_cond_jump_promotion
)
3963 /* Negate the condition, and branch past an
3964 unconditional jump. */
3967 /* Insert an unconditional jump. */
3969 /* We added two extra opcode bytes, and have a two byte
3971 fragP
->fr_fix
+= 2 + 2;
3972 fix_new (fragP
, old_fr_fix
+ 2, 2,
3974 fragP
->fr_offset
, 1,
3981 if (no_cond_jump_promotion
)
3983 /* This changes the byte-displacement jump 0x7N
3984 to the (d)word-displacement jump 0x0f,0x8N. */
3985 opcode
[1] = opcode
[0] + 0x10;
3986 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3987 /* We've added an opcode byte. */
3988 fragP
->fr_fix
+= 1 + size
;
3989 fix_new (fragP
, old_fr_fix
+ 1, size
,
3991 fragP
->fr_offset
, 1,
3996 BAD_CASE (fragP
->fr_subtype
);
4000 return fragP
->fr_fix
- old_fr_fix
;
4002 /* Guess a short jump. */
4006 /* Called after relax() is finished.
4008 In: Address of frag.
4009 fr_type == rs_machine_dependent.
4010 fr_subtype is what the address relaxed to.
4012 Out: Any fixSs and constants are set up.
4013 Caller will turn frag into a ".space 0". */
4015 #ifndef BFD_ASSEMBLER
4017 md_convert_frag (headers
, sec
, fragP
)
4018 object_headers
*headers ATTRIBUTE_UNUSED
;
4019 segT sec ATTRIBUTE_UNUSED
;
4020 register fragS
*fragP
;
4023 md_convert_frag (abfd
, sec
, fragP
)
4024 bfd
*abfd ATTRIBUTE_UNUSED
;
4025 segT sec ATTRIBUTE_UNUSED
;
4026 register fragS
*fragP
;
4029 register unsigned char *opcode
;
4030 unsigned char *where_to_put_displacement
= NULL
;
4031 offsetT target_address
;
4032 offsetT opcode_address
;
4033 unsigned int extension
= 0;
4034 offsetT displacement_from_opcode_start
;
4036 opcode
= (unsigned char *) fragP
->fr_opcode
;
4038 /* Address we want to reach in file space. */
4039 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
4040 #ifdef BFD_ASSEMBLER
4041 /* Not needed otherwise? */
4042 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
4045 /* Address opcode resides at in file space. */
4046 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
4048 /* Displacement from opcode start to fill into instruction. */
4049 displacement_from_opcode_start
= target_address
- opcode_address
;
4051 if ((fragP
->fr_subtype
& BIG
) == 0)
4053 /* Don't have to change opcode. */
4054 extension
= 1; /* 1 opcode + 1 displacement */
4055 where_to_put_displacement
= &opcode
[1];
4059 if (no_cond_jump_promotion
4060 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
4061 as_warn_where (fragP
->fr_file
, fragP
->fr_line
, _("long jump required"));
4063 switch (fragP
->fr_subtype
)
4065 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4066 extension
= 4; /* 1 opcode + 4 displacement */
4068 where_to_put_displacement
= &opcode
[1];
4071 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4072 extension
= 2; /* 1 opcode + 2 displacement */
4074 where_to_put_displacement
= &opcode
[1];
4077 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
4078 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
4079 extension
= 5; /* 2 opcode + 4 displacement */
4080 opcode
[1] = opcode
[0] + 0x10;
4081 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4082 where_to_put_displacement
= &opcode
[2];
4085 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4086 extension
= 3; /* 2 opcode + 2 displacement */
4087 opcode
[1] = opcode
[0] + 0x10;
4088 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4089 where_to_put_displacement
= &opcode
[2];
4092 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
4097 where_to_put_displacement
= &opcode
[3];
4101 BAD_CASE (fragP
->fr_subtype
);
4106 /* Now put displacement after opcode. */
4107 md_number_to_chars ((char *) where_to_put_displacement
,
4108 (valueT
) (displacement_from_opcode_start
- extension
),
4109 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4110 fragP
->fr_fix
+= extension
;
4113 /* Size of byte displacement jmp. */
4114 int md_short_jump_size
= 2;
4116 /* Size of dword displacement jmp. */
4117 int md_long_jump_size
= 5;
4119 /* Size of relocation record. */
4120 const int md_reloc_size
= 8;
4123 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4125 addressT from_addr
, to_addr
;
4126 fragS
*frag ATTRIBUTE_UNUSED
;
4127 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4131 offset
= to_addr
- (from_addr
+ 2);
4132 /* Opcode for byte-disp jump. */
4133 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4134 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4138 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4140 addressT from_addr
, to_addr
;
4141 fragS
*frag ATTRIBUTE_UNUSED
;
4142 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4146 offset
= to_addr
- (from_addr
+ 5);
4147 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4148 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4151 /* Apply a fixup (fixS) to segment data, once it has been determined
4152 by our caller that we have all the info we need to fix it up.
4154 On the 386, immediates, displacements, and data pointers are all in
4155 the same (little-endian) format, so we don't need to care about which
4159 md_apply_fix3 (fixP
, valp
, seg
)
4160 /* The fix we're to put in. */
4163 /* Pointer to the value of the bits. */
4166 /* Segment fix is from. */
4167 segT seg ATTRIBUTE_UNUSED
;
4169 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4170 valueT value
= *valp
;
4172 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4175 switch (fixP
->fx_r_type
)
4181 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4184 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4187 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4192 /* This is a hack. There should be a better way to handle this.
4193 This covers for the fact that bfd_install_relocation will
4194 subtract the current location (for partial_inplace, PC relative
4195 relocations); see more below. */
4196 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4197 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4198 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4202 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4204 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4207 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4209 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4210 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4212 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4215 || (symbol_section_p (fixP
->fx_addsy
)
4216 && fseg
!= absolute_section
))
4217 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4218 && ! S_IS_WEAK (fixP
->fx_addsy
)
4219 && S_IS_DEFINED (fixP
->fx_addsy
)
4220 && ! S_IS_COMMON (fixP
->fx_addsy
))
4222 /* Yes, we add the values in twice. This is because
4223 bfd_perform_relocation subtracts them out again. I think
4224 bfd_perform_relocation is broken, but I don't dare change
4226 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4230 #if defined (OBJ_COFF) && defined (TE_PE)
4231 /* For some reason, the PE format does not store a section
4232 address offset for a PC relative symbol. */
4233 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4234 value
+= md_pcrel_from (fixP
);
4238 /* Fix a few things - the dynamic linker expects certain values here,
4239 and we must not dissappoint it. */
4240 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4241 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4243 switch (fixP
->fx_r_type
)
4245 case BFD_RELOC_386_PLT32
:
4246 case BFD_RELOC_X86_64_PLT32
:
4247 /* Make the jump instruction point to the address of the operand. At
4248 runtime we merely add the offset to the actual PLT entry. */
4251 case BFD_RELOC_386_GOTPC
:
4253 /* This is tough to explain. We end up with this one if we have
4254 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4255 * here is to obtain the absolute address of the GOT, and it is strongly
4256 * preferable from a performance point of view to avoid using a runtime
4257 * relocation for this. The actual sequence of instructions often look
4263 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4265 * The call and pop essentially return the absolute address of
4266 * the label .L66 and store it in %ebx. The linker itself will
4267 * ultimately change the first operand of the addl so that %ebx points to
4268 * the GOT, but to keep things simple, the .o file must have this operand
4269 * set so that it generates not the absolute address of .L66, but the
4270 * absolute address of itself. This allows the linker itself simply
4271 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4272 * added in, and the addend of the relocation is stored in the operand
4273 * field for the instruction itself.
4275 * Our job here is to fix the operand so that it would add the correct
4276 * offset so that %ebx would point to itself. The thing that is tricky is
4277 * that .-.L66 will point to the beginning of the instruction, so we need
4278 * to further modify the operand so that it will point to itself.
4279 * There are other cases where you have something like:
4281 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4283 * and here no correction would be required. Internally in the assembler
4284 * we treat operands of this form as not being pcrel since the '.' is
4285 * explicitly mentioned, and I wonder whether it would simplify matters
4286 * to do it this way. Who knows. In earlier versions of the PIC patches,
4287 * the pcrel_adjust field was used to store the correction, but since the
4288 * expression is not pcrel, I felt it would be confusing to do it this
4293 case BFD_RELOC_386_GOT32
:
4294 case BFD_RELOC_X86_64_GOT32
:
4295 value
= 0; /* Fully resolved at runtime. No addend. */
4297 case BFD_RELOC_386_GOTOFF
:
4298 case BFD_RELOC_X86_64_GOTPCREL
:
4301 case BFD_RELOC_VTABLE_INHERIT
:
4302 case BFD_RELOC_VTABLE_ENTRY
:
4309 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4311 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4313 #ifndef BFD_ASSEMBLER
4314 md_number_to_chars (p
, value
, fixP
->fx_size
);
4316 /* Are we finished with this relocation now? */
4317 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4319 else if (use_rela_relocations
)
4321 fixP
->fx_no_overflow
= 1;
4324 md_number_to_chars (p
, value
, fixP
->fx_size
);
4330 #define MAX_LITTLENUMS 6
4332 /* Turn the string pointed to by litP into a floating point constant
4333 of type TYPE, and emit the appropriate bytes. The number of
4334 LITTLENUMS emitted is stored in *SIZEP. An error message is
4335 returned, or NULL on OK. */
4338 md_atof (type
, litP
, sizeP
)
4344 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4345 LITTLENUM_TYPE
*wordP
;
4367 return _("Bad call to md_atof ()");
4369 t
= atof_ieee (input_line_pointer
, type
, words
);
4371 input_line_pointer
= t
;
4373 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4374 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4375 the bigendian 386. */
4376 for (wordP
= words
+ prec
- 1; prec
--;)
4378 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4379 litP
+= sizeof (LITTLENUM_TYPE
);
4384 char output_invalid_buf
[8];
4391 sprintf (output_invalid_buf
, "'%c'", c
);
4393 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4394 return output_invalid_buf
;
4397 /* REG_STRING starts *before* REGISTER_PREFIX. */
4399 static const reg_entry
*
4400 parse_register (reg_string
, end_op
)
4404 char *s
= reg_string
;
4406 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4409 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4410 if (*s
== REGISTER_PREFIX
)
4413 if (is_space_char (*s
))
4417 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4419 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4420 return (const reg_entry
*) NULL
;
4424 /* For naked regs, make sure that we are not dealing with an identifier.
4425 This prevents confusing an identifier like `eax_var' with register
4427 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4428 return (const reg_entry
*) NULL
;
4432 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4434 /* Handle floating point regs, allowing spaces in the (i) part. */
4435 if (r
== i386_regtab
/* %st is first entry of table */)
4437 if (is_space_char (*s
))
4442 if (is_space_char (*s
))
4444 if (*s
>= '0' && *s
<= '7')
4446 r
= &i386_float_regtab
[*s
- '0'];
4448 if (is_space_char (*s
))
4456 /* We have "%st(" then garbage. */
4457 return (const reg_entry
*) NULL
;
4464 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4465 const char *md_shortopts
= "kVQ:sq";
4467 const char *md_shortopts
= "q";
4470 struct option md_longopts
[] = {
4471 #define OPTION_32 (OPTION_MD_BASE + 0)
4472 {"32", no_argument
, NULL
, OPTION_32
},
4473 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4474 #define OPTION_64 (OPTION_MD_BASE + 1)
4475 {"64", no_argument
, NULL
, OPTION_64
},
4477 {NULL
, no_argument
, NULL
, 0}
4479 size_t md_longopts_size
= sizeof (md_longopts
);
4482 md_parse_option (c
, arg
)
4484 char *arg ATTRIBUTE_UNUSED
;
4492 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4493 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4494 should be emitted or not. FIXME: Not implemented. */
4498 /* -V: SVR4 argument to print version ID. */
4500 print_version_id ();
4503 /* -k: Ignore for FreeBSD compatibility. */
4508 /* -s: On i386 Solaris, this tells the native assembler to use
4509 .stab instead of .stab.excl. We always use .stab anyhow. */
4514 const char **list
, **l
;
4516 list
= bfd_target_list ();
4517 for (l
= list
; *l
!= NULL
; l
++)
4518 if (strcmp (*l
, "elf64-x86-64") == 0)
4520 default_arch
= "x86_64";
4524 as_fatal (_("No compiled in support for x86_64"));
4531 default_arch
= "i386";
4541 md_show_usage (stream
)
4544 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4545 fprintf (stream
, _("\
4547 -V print assembler version number\n\
4549 -q quieten some warnings\n\
4552 fprintf (stream
, _("\
4553 -q quieten some warnings\n"));
4557 #ifdef BFD_ASSEMBLER
4558 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4559 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4561 /* Pick the target format to use. */
4564 i386_target_format ()
4566 if (!strcmp (default_arch
, "x86_64"))
4567 set_code_flag (CODE_64BIT
);
4568 else if (!strcmp (default_arch
, "i386"))
4569 set_code_flag (CODE_32BIT
);
4571 as_fatal (_("Unknown architecture"));
4572 switch (OUTPUT_FLAVOR
)
4574 #ifdef OBJ_MAYBE_AOUT
4575 case bfd_target_aout_flavour
:
4576 return AOUT_TARGET_FORMAT
;
4578 #ifdef OBJ_MAYBE_COFF
4579 case bfd_target_coff_flavour
:
4582 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4583 case bfd_target_elf_flavour
:
4585 if (flag_code
== CODE_64BIT
)
4586 use_rela_relocations
= 1;
4587 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4596 #endif /* OBJ_MAYBE_ more than one */
4597 #endif /* BFD_ASSEMBLER */
4600 md_undefined_symbol (name
)
4603 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4604 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4605 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4606 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4610 if (symbol_find (name
))
4611 as_bad (_("GOT already in symbol table"));
4612 GOT_symbol
= symbol_new (name
, undefined_section
,
4613 (valueT
) 0, &zero_address_frag
);
4620 /* Round up a section size to the appropriate boundary. */
4623 md_section_align (segment
, size
)
4624 segT segment ATTRIBUTE_UNUSED
;
4627 #ifdef BFD_ASSEMBLER
4628 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4629 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4631 /* For a.out, force the section size to be aligned. If we don't do
4632 this, BFD will align it for us, but it will not write out the
4633 final bytes of the section. This may be a bug in BFD, but it is
4634 easier to fix it here since that is how the other a.out targets
4638 align
= bfd_get_section_alignment (stdoutput
, segment
);
4639 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4647 /* On the i386, PC-relative offsets are relative to the start of the
4648 next instruction. That is, the address of the offset, plus its
4649 size, since the offset is always the last part of the insn. */
4652 md_pcrel_from (fixP
)
4655 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4662 int ignore ATTRIBUTE_UNUSED
;
4666 temp
= get_absolute_expression ();
4667 subseg_set (bss_section
, (subsegT
) temp
);
4668 demand_empty_rest_of_line ();
4673 #ifdef BFD_ASSEMBLER
4676 i386_validate_fix (fixp
)
4679 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4681 /* GOTOFF relocation are nonsense in 64bit mode. */
4682 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
4684 if (flag_code
!= CODE_64BIT
)
4686 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
4690 if (flag_code
== CODE_64BIT
)
4692 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4699 tc_gen_reloc (section
, fixp
)
4700 asection
*section ATTRIBUTE_UNUSED
;
4704 bfd_reloc_code_real_type code
;
4706 switch (fixp
->fx_r_type
)
4708 case BFD_RELOC_X86_64_PLT32
:
4709 case BFD_RELOC_X86_64_GOT32
:
4710 case BFD_RELOC_X86_64_GOTPCREL
:
4711 case BFD_RELOC_386_PLT32
:
4712 case BFD_RELOC_386_GOT32
:
4713 case BFD_RELOC_386_GOTOFF
:
4714 case BFD_RELOC_386_GOTPC
:
4715 case BFD_RELOC_X86_64_32S
:
4717 case BFD_RELOC_VTABLE_ENTRY
:
4718 case BFD_RELOC_VTABLE_INHERIT
:
4719 code
= fixp
->fx_r_type
;
4724 switch (fixp
->fx_size
)
4727 as_bad (_("can not do %d byte pc-relative relocation"),
4729 code
= BFD_RELOC_32_PCREL
;
4731 case 1: code
= BFD_RELOC_8_PCREL
; break;
4732 case 2: code
= BFD_RELOC_16_PCREL
; break;
4733 case 4: code
= BFD_RELOC_32_PCREL
; break;
4738 switch (fixp
->fx_size
)
4741 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4742 code
= BFD_RELOC_32
;
4744 case 1: code
= BFD_RELOC_8
; break;
4745 case 2: code
= BFD_RELOC_16
; break;
4746 case 4: code
= BFD_RELOC_32
; break;
4747 case 8: code
= BFD_RELOC_64
; break;
4753 if (code
== BFD_RELOC_32
4755 && fixp
->fx_addsy
== GOT_symbol
)
4757 /* We don't support GOTPC on 64bit targets. */
4758 if (flag_code
== CODE_64BIT
)
4760 code
= BFD_RELOC_386_GOTPC
;
4763 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4764 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4765 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4767 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4768 if (!use_rela_relocations
)
4770 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4771 vtable entry to be used in the relocation's section offset. */
4772 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4773 rel
->address
= fixp
->fx_offset
;
4776 rel
->addend
= fixp
->fx_addnumber
;
4780 /* Use the rela in 64bit mode. */
4783 rel
->addend
= fixp
->fx_offset
;
4785 /* Ohhh, this is ugly. The problem is that if this is a local global
4786 symbol, the relocation will entirely be performed at link time, not
4787 at assembly time. bfd_perform_reloc doesn't know about this sort
4788 of thing, and as a result we need to fake it out here. */
4789 if ((S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
))
4790 && !S_IS_COMMON (fixp
->fx_addsy
))
4791 rel
->addend
-= symbol_get_bfdsym (fixp
->fx_addsy
)->value
;
4794 rel
->addend
-= fixp
->fx_size
;
4797 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4798 if (rel
->howto
== NULL
)
4800 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4801 _("cannot represent relocation type %s"),
4802 bfd_get_reloc_code_name (code
));
4803 /* Set howto to a garbage value so that we can keep going. */
4804 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4805 assert (rel
->howto
!= NULL
);
4811 #else /* ! BFD_ASSEMBLER */
4813 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4815 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4818 relax_addressT segment_address_in_file
;
4820 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4821 Out: GNU LD relocation length code: 0, 1, or 2. */
4823 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4826 know (fixP
->fx_addsy
!= NULL
);
4828 md_number_to_chars (where
,
4829 (valueT
) (fixP
->fx_frag
->fr_address
4830 + fixP
->fx_where
- segment_address_in_file
),
4833 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4834 ? S_GET_TYPE (fixP
->fx_addsy
)
4835 : fixP
->fx_addsy
->sy_number
);
4837 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4838 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4839 where
[4] = r_symbolnum
& 0x0ff;
4840 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4841 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4842 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4845 #endif /* OBJ_AOUT or OBJ_BOUT. */
4847 #if defined (I386COFF)
4850 tc_coff_fix2rtype (fixP
)
4853 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4856 return (fixP
->fx_pcrel
?
4857 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4858 fixP
->fx_size
== 2 ? R_PCRWORD
:
4860 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4861 fixP
->fx_size
== 2 ? R_RELWORD
:
4866 tc_coff_sizemachdep (frag
)
4870 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4875 #endif /* I386COFF */
4877 #endif /* ! BFD_ASSEMBLER */
4879 /* Parse operands using Intel syntax. This implements a recursive descent
4880 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4883 FIXME: We do not recognize the full operand grammar defined in the MASM
4884 documentation. In particular, all the structure/union and
4885 high-level macro operands are missing.
4887 Uppercase words are terminals, lower case words are non-terminals.
4888 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4889 bars '|' denote choices. Most grammar productions are implemented in
4890 functions called 'intel_<production>'.
4892 Initial production is 'expr'.
4898 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4900 constant digits [[ radixOverride ]]
4902 dataType BYTE | WORD | DWORD | QWORD | XWORD
4935 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4936 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4938 hexdigit a | b | c | d | e | f
4939 | A | B | C | D | E | F
4949 register specialRegister
4953 segmentRegister CS | DS | ES | FS | GS | SS
4955 specialRegister CR0 | CR2 | CR3
4956 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4957 | TR3 | TR4 | TR5 | TR6 | TR7
4959 We simplify the grammar in obvious places (e.g., register parsing is
4960 done by calling parse_register) and eliminate immediate left recursion
4961 to implement a recursive-descent parser.
5001 /* Parsing structure for the intel syntax parser. Used to implement the
5002 semantic actions for the operand grammar. */
5003 struct intel_parser_s
5005 char *op_string
; /* The string being parsed. */
5006 int got_a_float
; /* Whether the operand is a float. */
5007 int op_modifier
; /* Operand modifier. */
5008 int is_mem
; /* 1 if operand is memory reference. */
5009 const reg_entry
*reg
; /* Last register reference found. */
5010 char *disp
; /* Displacement string being built. */
5013 static struct intel_parser_s intel_parser
;
5015 /* Token structure for parsing intel syntax. */
5018 int code
; /* Token code. */
5019 const reg_entry
*reg
; /* Register entry for register tokens. */
5020 char *str
; /* String representation. */
5023 static struct intel_token cur_token
, prev_token
;
5025 /* Token codes for the intel parser. Since T_SHORT is already used
5026 by COFF, undefine it first to prevent a warning. */
5041 /* Prototypes for intel parser functions. */
5042 static int intel_match_token
PARAMS ((int code
));
5043 static void intel_get_token
PARAMS ((void));
5044 static void intel_putback_token
PARAMS ((void));
5045 static int intel_expr
PARAMS ((void));
5046 static int intel_e05
PARAMS ((void));
5047 static int intel_e05_1
PARAMS ((void));
5048 static int intel_e06
PARAMS ((void));
5049 static int intel_e06_1
PARAMS ((void));
5050 static int intel_e09
PARAMS ((void));
5051 static int intel_e09_1
PARAMS ((void));
5052 static int intel_e10
PARAMS ((void));
5053 static int intel_e10_1
PARAMS ((void));
5054 static int intel_e11
PARAMS ((void));
5057 i386_intel_operand (operand_string
, got_a_float
)
5058 char *operand_string
;
5064 /* Initialize token holders. */
5065 cur_token
.code
= prev_token
.code
= T_NIL
;
5066 cur_token
.reg
= prev_token
.reg
= NULL
;
5067 cur_token
.str
= prev_token
.str
= NULL
;
5069 /* Initialize parser structure. */
5070 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
5073 strcpy (intel_parser
.op_string
, operand_string
);
5074 intel_parser
.got_a_float
= got_a_float
;
5075 intel_parser
.op_modifier
= -1;
5076 intel_parser
.is_mem
= 0;
5077 intel_parser
.reg
= NULL
;
5078 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
5079 if (intel_parser
.disp
== NULL
)
5081 intel_parser
.disp
[0] = '\0';
5083 /* Read the first token and start the parser. */
5085 ret
= intel_expr ();
5089 /* If we found a memory reference, hand it over to i386_displacement
5090 to fill in the rest of the operand fields. */
5091 if (intel_parser
.is_mem
)
5093 if ((i
.mem_operands
== 1
5094 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5095 || i
.mem_operands
== 2)
5097 as_bad (_("too many memory references for '%s'"),
5098 current_templates
->start
->name
);
5103 char *s
= intel_parser
.disp
;
5106 /* Add the displacement expression. */
5108 ret
= i386_displacement (s
, s
+ strlen (s
))
5109 && i386_index_check (s
);
5113 /* Constant and OFFSET expressions are handled by i386_immediate. */
5114 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5115 || intel_parser
.reg
== NULL
)
5116 ret
= i386_immediate (intel_parser
.disp
);
5120 free (intel_parser
.disp
);
5130 /* expr SHORT e05 */
5131 if (cur_token
.code
== T_SHORT
)
5133 intel_parser
.op_modifier
= SHORT
;
5134 intel_match_token (T_SHORT
);
5136 return (intel_e05 ());
5141 return intel_e05 ();
5151 return (intel_e06 () && intel_e05_1 ());
5157 /* e05' addOp e06 e05' */
5158 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5160 strcat (intel_parser
.disp
, cur_token
.str
);
5161 intel_match_token (cur_token
.code
);
5163 return (intel_e06 () && intel_e05_1 ());
5178 return (intel_e09 () && intel_e06_1 ());
5184 /* e06' mulOp e09 e06' */
5185 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5187 strcat (intel_parser
.disp
, cur_token
.str
);
5188 intel_match_token (cur_token
.code
);
5190 return (intel_e09 () && intel_e06_1 ());
5198 /* e09 OFFSET e10 e09'
5207 /* e09 OFFSET e10 e09' */
5208 if (cur_token
.code
== T_OFFSET
)
5210 intel_parser
.is_mem
= 0;
5211 intel_parser
.op_modifier
= OFFSET_FLAT
;
5212 intel_match_token (T_OFFSET
);
5214 return (intel_e10 () && intel_e09_1 ());
5219 return (intel_e10 () && intel_e09_1 ());
5225 /* e09' PTR e10 e09' */
5226 if (cur_token
.code
== T_PTR
)
5228 if (prev_token
.code
== T_BYTE
)
5229 i
.suffix
= BYTE_MNEM_SUFFIX
;
5231 else if (prev_token
.code
== T_WORD
)
5233 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5234 i
.suffix
= SHORT_MNEM_SUFFIX
;
5236 i
.suffix
= WORD_MNEM_SUFFIX
;
5239 else if (prev_token
.code
== T_DWORD
)
5241 if (intel_parser
.got_a_float
== 1) /* "f..." */
5242 i
.suffix
= SHORT_MNEM_SUFFIX
;
5244 i
.suffix
= LONG_MNEM_SUFFIX
;
5247 else if (prev_token
.code
== T_QWORD
)
5249 if (intel_parser
.got_a_float
== 1) /* "f..." */
5250 i
.suffix
= LONG_MNEM_SUFFIX
;
5252 i
.suffix
= QWORD_MNEM_SUFFIX
;
5255 else if (prev_token
.code
== T_XWORD
)
5256 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5260 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5264 intel_match_token (T_PTR
);
5266 return (intel_e10 () && intel_e09_1 ());
5269 /* e09 : e10 e09' */
5270 else if (cur_token
.code
== ':')
5272 /* Mark as a memory operand only if it's not already known to be an
5273 offset expression. */
5274 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5275 intel_parser
.is_mem
= 1;
5277 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5292 return (intel_e11 () && intel_e10_1 ());
5298 /* e10' [ expr ] e10' */
5299 if (cur_token
.code
== '[')
5301 intel_match_token ('[');
5303 /* Mark as a memory operand only if it's not already known to be an
5304 offset expression. If it's an offset expression, we need to keep
5306 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5307 intel_parser
.is_mem
= 1;
5309 strcat (intel_parser
.disp
, "[");
5311 /* Add a '+' to the displacement string if necessary. */
5312 if (*intel_parser
.disp
!= '\0'
5313 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5314 strcat (intel_parser
.disp
, "+");
5316 if (intel_expr () && intel_match_token (']'))
5318 /* Preserve brackets when the operand is an offset expression. */
5319 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5320 strcat (intel_parser
.disp
, "]");
5322 return intel_e10_1 ();
5349 if (cur_token
.code
== '(')
5351 intel_match_token ('(');
5352 strcat (intel_parser
.disp
, "(");
5354 if (intel_expr () && intel_match_token (')'))
5356 strcat (intel_parser
.disp
, ")");
5364 else if (cur_token
.code
== '[')
5366 intel_match_token ('[');
5368 /* Mark as a memory operand only if it's not already known to be an
5369 offset expression. If it's an offset expression, we need to keep
5371 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5372 intel_parser
.is_mem
= 1;
5374 strcat (intel_parser
.disp
, "[");
5376 /* Operands for jump/call inside brackets denote absolute addresses. */
5377 if (current_templates
->start
->opcode_modifier
& Jump
5378 || current_templates
->start
->opcode_modifier
& JumpDword
5379 || current_templates
->start
->opcode_modifier
& JumpByte
5380 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5381 i
.types
[this_operand
] |= JumpAbsolute
;
5383 /* Add a '+' to the displacement string if necessary. */
5384 if (*intel_parser
.disp
!= '\0'
5385 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5386 strcat (intel_parser
.disp
, "+");
5388 if (intel_expr () && intel_match_token (']'))
5390 /* Preserve brackets when the operand is an offset expression. */
5391 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5392 strcat (intel_parser
.disp
, "]");
5405 else if (cur_token
.code
== T_BYTE
5406 || cur_token
.code
== T_WORD
5407 || cur_token
.code
== T_DWORD
5408 || cur_token
.code
== T_QWORD
5409 || cur_token
.code
== T_XWORD
)
5411 intel_match_token (cur_token
.code
);
5418 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5420 strcat (intel_parser
.disp
, cur_token
.str
);
5421 intel_match_token (cur_token
.code
);
5423 /* Mark as a memory operand only if it's not already known to be an
5424 offset expression. */
5425 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5426 intel_parser
.is_mem
= 1;
5432 else if (cur_token
.code
== T_REG
)
5434 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5436 intel_match_token (T_REG
);
5438 /* Check for segment change. */
5439 if (cur_token
.code
== ':')
5441 if (reg
->reg_type
& (SReg2
| SReg3
))
5443 switch (reg
->reg_num
)
5446 i
.seg
[i
.mem_operands
] = &es
;
5449 i
.seg
[i
.mem_operands
] = &cs
;
5452 i
.seg
[i
.mem_operands
] = &ss
;
5455 i
.seg
[i
.mem_operands
] = &ds
;
5458 i
.seg
[i
.mem_operands
] = &fs
;
5461 i
.seg
[i
.mem_operands
] = &gs
;
5467 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5472 /* Not a segment register. Check for register scaling. */
5473 else if (cur_token
.code
== '*')
5475 if (!intel_parser
.is_mem
)
5477 as_bad (_("Register scaling only allowed in memory operands."));
5481 /* What follows must be a valid scale. */
5482 if (intel_match_token ('*')
5483 && strchr ("01248", *cur_token
.str
))
5486 i
.types
[this_operand
] |= BaseIndex
;
5488 /* Set the scale after setting the register (otherwise,
5489 i386_scale will complain) */
5490 i386_scale (cur_token
.str
);
5491 intel_match_token (T_CONST
);
5495 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5501 /* No scaling. If this is a memory operand, the register is either a
5502 base register (first occurrence) or an index register (second
5504 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5506 if (i
.base_reg
&& i
.index_reg
)
5508 as_bad (_("Too many register references in memory operand.\n"));
5512 if (i
.base_reg
== NULL
)
5517 i
.types
[this_operand
] |= BaseIndex
;
5520 /* Offset modifier. Add the register to the displacement string to be
5521 parsed as an immediate expression after we're done. */
5522 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5523 strcat (intel_parser
.disp
, reg
->reg_name
);
5525 /* It's neither base nor index nor offset. */
5528 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5529 i
.op
[this_operand
].regs
= reg
;
5533 /* Since registers are not part of the displacement string (except
5534 when we're parsing offset operands), we may need to remove any
5535 preceding '+' from the displacement string. */
5536 if (*intel_parser
.disp
!= '\0'
5537 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5539 char *s
= intel_parser
.disp
;
5540 s
+= strlen (s
) - 1;
5549 else if (cur_token
.code
== T_ID
)
5551 /* Add the identifier to the displacement string. */
5552 strcat (intel_parser
.disp
, cur_token
.str
);
5553 intel_match_token (T_ID
);
5555 /* The identifier represents a memory reference only if it's not
5556 preceded by an offset modifier. */
5557 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5558 intel_parser
.is_mem
= 1;
5564 else if (cur_token
.code
== T_CONST
5565 || cur_token
.code
== '-'
5566 || cur_token
.code
== '+')
5570 /* Allow constants that start with `+' or `-'. */
5571 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5573 strcat (intel_parser
.disp
, cur_token
.str
);
5574 intel_match_token (cur_token
.code
);
5575 if (cur_token
.code
!= T_CONST
)
5577 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5583 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5584 if (save_str
== NULL
)
5586 strcpy (save_str
, cur_token
.str
);
5588 /* Get the next token to check for register scaling. */
5589 intel_match_token (cur_token
.code
);
5591 /* Check if this constant is a scaling factor for an index register. */
5592 if (cur_token
.code
== '*')
5594 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5596 if (!intel_parser
.is_mem
)
5598 as_bad (_("Register scaling only allowed in memory operands."));
5602 /* The constant is followed by `* reg', so it must be
5604 if (strchr ("01248", *save_str
))
5606 i
.index_reg
= cur_token
.reg
;
5607 i
.types
[this_operand
] |= BaseIndex
;
5609 /* Set the scale after setting the register (otherwise,
5610 i386_scale will complain) */
5611 i386_scale (save_str
);
5612 intel_match_token (T_REG
);
5614 /* Since registers are not part of the displacement
5615 string, we may need to remove any preceding '+' from
5616 the displacement string. */
5617 if (*intel_parser
.disp
!= '\0')
5619 char *s
= intel_parser
.disp
;
5620 s
+= strlen (s
) - 1;
5633 /* The constant was not used for register scaling. Since we have
5634 already consumed the token following `*' we now need to put it
5635 back in the stream. */
5637 intel_putback_token ();
5640 /* Add the constant to the displacement string. */
5641 strcat (intel_parser
.disp
, save_str
);
5647 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5651 /* Match the given token against cur_token. If they match, read the next
5652 token from the operand string. */
5654 intel_match_token (code
)
5657 if (cur_token
.code
== code
)
5664 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5669 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5674 const reg_entry
*reg
;
5675 struct intel_token new_token
;
5677 new_token
.code
= T_NIL
;
5678 new_token
.reg
= NULL
;
5679 new_token
.str
= NULL
;
5681 /* Free the memory allocated to the previous token and move
5682 cur_token to prev_token. */
5684 free (prev_token
.str
);
5686 prev_token
= cur_token
;
5688 /* Skip whitespace. */
5689 while (is_space_char (*intel_parser
.op_string
))
5690 intel_parser
.op_string
++;
5692 /* Return an empty token if we find nothing else on the line. */
5693 if (*intel_parser
.op_string
== '\0')
5695 cur_token
= new_token
;
5699 /* The new token cannot be larger than the remainder of the operand
5701 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
5702 if (new_token
.str
== NULL
)
5704 new_token
.str
[0] = '\0';
5706 if (strchr ("0123456789", *intel_parser
.op_string
))
5708 char *p
= new_token
.str
;
5709 char *q
= intel_parser
.op_string
;
5710 new_token
.code
= T_CONST
;
5712 /* Allow any kind of identifier char to encompass floating point and
5713 hexadecimal numbers. */
5714 while (is_identifier_char (*q
))
5718 /* Recognize special symbol names [0-9][bf]. */
5719 if (strlen (intel_parser
.op_string
) == 2
5720 && (intel_parser
.op_string
[1] == 'b'
5721 || intel_parser
.op_string
[1] == 'f'))
5722 new_token
.code
= T_ID
;
5725 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5727 new_token
.code
= *intel_parser
.op_string
;
5728 new_token
.str
[0] = *intel_parser
.op_string
;
5729 new_token
.str
[1] = '\0';
5732 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5733 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5735 new_token
.code
= T_REG
;
5736 new_token
.reg
= reg
;
5738 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5740 new_token
.str
[0] = REGISTER_PREFIX
;
5741 new_token
.str
[1] = '\0';
5744 strcat (new_token
.str
, reg
->reg_name
);
5747 else if (is_identifier_char (*intel_parser
.op_string
))
5749 char *p
= new_token
.str
;
5750 char *q
= intel_parser
.op_string
;
5752 /* A '.' or '$' followed by an identifier char is an identifier.
5753 Otherwise, it's operator '.' followed by an expression. */
5754 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5756 new_token
.code
= *q
;
5757 new_token
.str
[0] = *q
;
5758 new_token
.str
[1] = '\0';
5762 while (is_identifier_char (*q
) || *q
== '@')
5766 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5767 new_token
.code
= T_BYTE
;
5769 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5770 new_token
.code
= T_WORD
;
5772 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5773 new_token
.code
= T_DWORD
;
5775 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5776 new_token
.code
= T_QWORD
;
5778 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5779 new_token
.code
= T_XWORD
;
5781 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5782 new_token
.code
= T_PTR
;
5784 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5785 new_token
.code
= T_SHORT
;
5787 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5789 new_token
.code
= T_OFFSET
;
5791 /* ??? This is not mentioned in the MASM grammar but gcc
5792 makes use of it with -mintel-syntax. OFFSET may be
5793 followed by FLAT: */
5794 if (strncasecmp (q
, " FLAT:", 6) == 0)
5795 strcat (new_token
.str
, " FLAT:");
5798 /* ??? This is not mentioned in the MASM grammar. */
5799 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5800 new_token
.code
= T_OFFSET
;
5803 new_token
.code
= T_ID
;
5808 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5810 intel_parser
.op_string
+= strlen (new_token
.str
);
5811 cur_token
= new_token
;
5814 /* Put cur_token back into the token stream and make cur_token point to
5817 intel_putback_token ()
5819 intel_parser
.op_string
-= strlen (cur_token
.str
);
5820 free (cur_token
.str
);
5821 cur_token
= prev_token
;
5823 /* Forget prev_token. */
5824 prev_token
.code
= T_NIL
;
5825 prev_token
.reg
= NULL
;
5826 prev_token
.str
= NULL
;