opcodes/ppc-opc.c

   1 /* ppc-opc.c -- PowerPC opcode list
   2    Copyright (c) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5 This file is part of GDB, GAS, and the GNU binutils.
   6
   7 GDB, GAS, and the GNU binutils are free software; you can redistribute
   8 them and/or modify them under the terms of the GNU General Public
   9 License as published by the Free Software Foundation; either version
  10 2, or (at your option) any later version.
  11
  12 GDB, GAS, and the GNU binutils are distributed in the hope that they
  13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15 the GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this file; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20 02111-1307, USA.  */
  21
  22 #include <stdio.h>
  23 #include "ansidecl.h"
  24 #include "opcode/ppc.h"
  25 #include "opintl.h"
  26
  27 /* This file holds the PowerPC opcode table.  The opcode table
  28    includes almost all of the extended instruction mnemonics.  This
  29    permits the disassembler to use them, and simplifies the assembler
  30    logic, at the cost of increasing the table size.  The table is
  31    strictly constant data, so the compiler should be able to put it in
  32    the .text section.
  33
  34    This file also holds the operand table.  All knowledge about
  35    inserting operands into instructions and vice-versa is kept in this
  36    file.  */
  37 \f
  38 /* Local insertion and extraction functions.  */
  39
  40 static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
  41 static long extract_bat PARAMS ((unsigned long, int *));
  42 static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
  43 static long extract_bba PARAMS ((unsigned long, int *));
  44 static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
  45 static long extract_bd PARAMS ((unsigned long, int *));
  46 static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
  47 static long extract_bdm PARAMS ((unsigned long, int *));
  48 static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
  49 static long extract_bdp PARAMS ((unsigned long, int *));
  50 static int valid_bo PARAMS ((long));
  51 static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
  52 static long extract_bo PARAMS ((unsigned long, int *));
  53 static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
  54 static long extract_boe PARAMS ((unsigned long, int *));
  55 static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
  56 static long extract_ds PARAMS ((unsigned long, int *));
  57 static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
  58 static long extract_li PARAMS ((unsigned long, int *));
  59 static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
  60 static long extract_mbe PARAMS ((unsigned long, int *));
  61 static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
  62 static long extract_mb6 PARAMS ((unsigned long, int *));
  63 static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
  64 static long extract_nb PARAMS ((unsigned long, int *));
  65 static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
  66 static long extract_nsi PARAMS ((unsigned long, int *));
  67 static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
  68 static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
  69 static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
  70 static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
  71 static long extract_rbs PARAMS ((unsigned long, int *));
  72 static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
  73 static long extract_sh6 PARAMS ((unsigned long, int *));
  74 static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
  75 static long extract_spr PARAMS ((unsigned long, int *));
  76 static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
  77 static long extract_tbr PARAMS ((unsigned long, int *));
  78 \f
  79 /* The operands table.
  80
  81    The fields are bits, shift, insert, extract, flags.
  82
  83    We used to put parens around the various additions, like the one
  84    for BA just below.  However, that caused trouble with feeble
  85    compilers with a limit on depth of a parenthesized expression, like
  86    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
  87    omit the parens, since the macros are never used in a context where
  88    the addition will be ambiguous.  */
  89
  90 const struct powerpc_operand powerpc_operands[] =
  91 {
  92   /* The zero index is used to indicate the end of the list of
  93      operands.  */
  94 #define UNUSED 0
  95   { 0, 0, 0, 0, 0 },
  96
  97   /* The BA field in an XL form instruction.  */
  98 #define BA UNUSED + 1
  99 #define BA_MASK (0x1f << 16)
 100   { 5, 16, 0, 0, PPC_OPERAND_CR },
 101
 102   /* The BA field in an XL form instruction when it must be the same
 103      as the BT field in the same instruction.  */
 104 #define BAT BA + 1
 105   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
 106
 107   /* The BB field in an XL form instruction.  */
 108 #define BB BAT + 1
 109 #define BB_MASK (0x1f << 11)
 110   { 5, 11, 0, 0, PPC_OPERAND_CR },
 111
 112   /* The BB field in an XL form instruction when it must be the same
 113      as the BA field in the same instruction.  */
 114 #define BBA BB + 1
 115   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
 116
 117   /* The BD field in a B form instruction.  The lower two bits are
 118      forced to zero.  */
 119 #define BD BBA + 1
 120   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 121
 122   /* The BD field in a B form instruction when absolute addressing is
 123      used.  */
 124 #define BDA BD + 1
 125   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 126
 127   /* The BD field in a B form instruction when the - modifier is used.
 128      This sets the y bit of the BO field appropriately.  */
 129 #define BDM BDA + 1
 130   { 16, 0, insert_bdm, extract_bdm,
 131       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 132
 133   /* The BD field in a B form instruction when the - modifier is used
 134      and absolute address is used.  */
 135 #define BDMA BDM + 1
 136   { 16, 0, insert_bdm, extract_bdm,
 137       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 138
 139   /* The BD field in a B form instruction when the + modifier is used.
 140      This sets the y bit of the BO field appropriately.  */
 141 #define BDP BDMA + 1
 142   { 16, 0, insert_bdp, extract_bdp,
 143       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 144
 145   /* The BD field in a B form instruction when the + modifier is used
 146      and absolute addressing is used.  */
 147 #define BDPA BDP + 1
 148   { 16, 0, insert_bdp, extract_bdp,
 149       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 150
 151   /* The BF field in an X or XL form instruction.  */
 152 #define BF BDPA + 1
 153   { 3, 23, 0, 0, PPC_OPERAND_CR },
 154
 155   /* An optional BF field.  This is used for comparison instructions,
 156      in which an omitted BF field is taken as zero.  */
 157 #define OBF BF + 1
 158   { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 159
 160   /* The BFA field in an X or XL form instruction.  */
 161 #define BFA OBF + 1
 162   { 3, 18, 0, 0, PPC_OPERAND_CR },
 163
 164   /* The BI field in a B form or XL form instruction.  */
 165 #define BI BFA + 1
 166 #define BI_MASK (0x1f << 16)
 167   { 5, 16, 0, 0, PPC_OPERAND_CR },
 168
 169   /* The BO field in a B form instruction.  Certain values are
 170      illegal.  */
 171 #define BO BI + 1
 172 #define BO_MASK (0x1f << 21)
 173   { 5, 21, insert_bo, extract_bo, 0 },
 174
 175   /* The BO field in a B form instruction when the + or - modifier is
 176      used.  This is like the BO field, but it must be even.  */
 177 #define BOE BO + 1
 178   { 5, 21, insert_boe, extract_boe, 0 },
 179
 180   /* The BT field in an X or XL form instruction.  */
 181 #define BT BOE + 1
 182   { 5, 21, 0, 0, PPC_OPERAND_CR },
 183
 184   /* The condition register number portion of the BI field in a B form
 185      or XL form instruction.  This is used for the extended
 186      conditional branch mnemonics, which set the lower two bits of the
 187      BI field.  This field is optional.  */
 188 #define CR BT + 1
 189   { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 190
 191   /* The D field in a D form instruction.  This is a displacement off
 192      a register, and implies that the next operand is a register in
 193      parentheses.  */
 194 #define D CR + 1
 195   { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 196
 197   /* The DS field in a DS form instruction.  This is like D, but the
 198      lower two bits are forced to zero.  */
 199 #define DS D + 1
 200   { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 201
 202   /* The E field in a wrteei instruction.  */
 203 #define E DS + 1
 204   { 1, 15, 0, 0, 0 },
 205
 206   /* The FL1 field in a POWER SC form instruction.  */
 207 #define FL1 E + 1
 208   { 4, 12, 0, 0, 0 },
 209
 210   /* The FL2 field in a POWER SC form instruction.  */
 211 #define FL2 FL1 + 1
 212   { 3, 2, 0, 0, 0 },
 213
 214   /* The FLM field in an XFL form instruction.  */
 215 #define FLM FL2 + 1
 216   { 8, 17, 0, 0, 0 },
 217
 218   /* The FRA field in an X or A form instruction.  */
 219 #define FRA FLM + 1
 220 #define FRA_MASK (0x1f << 16)
 221   { 5, 16, 0, 0, PPC_OPERAND_FPR },
 222
 223   /* The FRB field in an X or A form instruction.  */
 224 #define FRB FRA + 1
 225 #define FRB_MASK (0x1f << 11)
 226   { 5, 11, 0, 0, PPC_OPERAND_FPR },
 227
 228   /* The FRC field in an A form instruction.  */
 229 #define FRC FRB + 1
 230 #define FRC_MASK (0x1f << 6)
 231   { 5, 6, 0, 0, PPC_OPERAND_FPR },
 232
 233   /* The FRS field in an X form instruction or the FRT field in a D, X
 234      or A form instruction.  */
 235 #define FRS FRC + 1
 236 #define FRT FRS
 237   { 5, 21, 0, 0, PPC_OPERAND_FPR },
 238
 239   /* The FXM field in an XFX instruction.  */
 240 #define FXM FRS + 1
 241 #define FXM_MASK (0xff << 12)
 242   { 8, 12, 0, 0, 0 },
 243
 244   /* The L field in a D or X form instruction.  */
 245 #define L FXM + 1
 246   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 247
 248   /* The LEV field in a POWER SC form instruction.  */
 249 #define LEV L + 1
 250   { 7, 5, 0, 0, 0 },
 251
 252   /* The LI field in an I form instruction.  The lower two bits are
 253      forced to zero.  */
 254 #define LI LEV + 1
 255   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 256
 257   /* The LI field in an I form instruction when used as an absolute
 258      address.  */
 259 #define LIA LI + 1
 260   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
 261
 262   /* The MB field in an M form instruction.  */
 263 #define MB LIA + 1
 264 #define MB_MASK (0x1f << 6)
 265   { 5, 6, 0, 0, 0 },
 266
 267   /* The ME field in an M form instruction.  */
 268 #define ME MB + 1
 269 #define ME_MASK (0x1f << 1)
 270   { 5, 1, 0, 0, 0 },
 271
 272   /* The MB and ME fields in an M form instruction expressed a single
 273      operand which is a bitmask indicating which bits to select.  This
 274      is a two operand form using PPC_OPERAND_NEXT.  See the
 275      description in opcode/ppc.h for what this means.  */
 276 #define MBE ME + 1
 277   { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
 278   { 32, 0, insert_mbe, extract_mbe, 0 },
 279
 280   /* The MB or ME field in an MD or MDS form instruction.  The high
 281      bit is wrapped to the low end.  */
 282 #define MB6 MBE + 2
 283 #define ME6 MB6
 284 #define MB6_MASK (0x3f << 5)
 285   { 6, 5, insert_mb6, extract_mb6, 0 },
 286
 287   /* The NB field in an X form instruction.  The value 32 is stored as
 288      0.  */
 289 #define NB MB6 + 1
 290   { 6, 11, insert_nb, extract_nb, 0 },
 291
 292   /* The NSI field in a D form instruction.  This is the same as the
 293      SI field, only negated.  */
 294 #define NSI NB + 1
 295   { 16, 0, insert_nsi, extract_nsi,
 296       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 297
 298   /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */
 299 #define RA NSI + 1
 300 #define RA_MASK (0x1f << 16)
 301   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 302
 303   /* The RA field in a D or X form instruction which is an updating
 304      load, which means that the RA field may not be zero and may not
 305      equal the RT field.  */
 306 #define RAL RA + 1
 307   { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
 308
 309   /* The RA field in an lmw instruction, which has special value
 310      restrictions.  */
 311 #define RAM RAL + 1
 312   { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
 313
 314   /* The RA field in a D or X form instruction which is an updating
 315      store or an updating floating point load, which means that the RA
 316      field may not be zero.  */
 317 #define RAS RAM + 1
 318   { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
 319
 320   /* The RB field in an X, XO, M, or MDS form instruction.  */
 321 #define RB RAS + 1
 322 #define RB_MASK (0x1f << 11)
 323   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 324
 325   /* The RB field in an X form instruction when it must be the same as
 326      the RS field in the instruction.  This is used for extended
 327      mnemonics like mr.  */
 328 #define RBS RB + 1
 329   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
 330
 331   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
 332      instruction or the RT field in a D, DS, X, XFX or XO form
 333      instruction.  */
 334 #define RS RBS + 1
 335 #define RT RS
 336 #define RT_MASK (0x1f << 21)
 337   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 338
 339   /* The SH field in an X or M form instruction.  */
 340 #define SH RS + 1
 341 #define SH_MASK (0x1f << 11)
 342   { 5, 11, 0, 0, 0 },
 343
 344   /* The SH field in an MD form instruction.  This is split.  */
 345 #define SH6 SH + 1
 346 #define SH6_MASK ((0x1f << 11) | (1 << 1))
 347   { 6, 1, insert_sh6, extract_sh6, 0 },
 348
 349   /* The SI field in a D form instruction.  */
 350 #define SI SH6 + 1
 351   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 352
 353   /* The SI field in a D form instruction when we accept a wide range
 354      of positive values.  */
 355 #define SISIGNOPT SI + 1
 356   { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 357
 358   /* The SPR field in an XFX form instruction.  This is flipped--the
 359      lower 5 bits are stored in the upper 5 and vice- versa.  */
 360 #define SPR SISIGNOPT + 1
 361 #define SPR_MASK (0x3ff << 11)
 362   { 10, 11, insert_spr, extract_spr, 0 },
 363
 364   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 365 #define SPRBAT SPR + 1
 366 #define SPRBAT_MASK (0x3 << 17)
 367   { 2, 17, 0, 0, 0 },
 368
 369   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 370 #define SPRG SPRBAT + 1
 371 #define SPRG_MASK (0x3 << 16)
 372   { 2, 16, 0, 0, 0 },
 373
 374   /* The SR field in an X form instruction.  */
 375 #define SR SPRG + 1
 376   { 4, 16, 0, 0, 0 },
 377
 378   /* The SV field in a POWER SC form instruction.  */
 379 #define SV SR + 1
 380   { 14, 2, 0, 0, 0 },
 381
 382   /* The TBR field in an XFX form instruction.  This is like the SPR
 383      field, but it is optional.  */
 384 #define TBR SV + 1
 385   { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
 386
 387   /* The TO field in a D or X form instruction.  */
 388 #define TO TBR + 1
 389 #define TO_MASK (0x1f << 21)
 390   { 5, 21, 0, 0, 0 },
 391
 392   /* The U field in an X form instruction.  */
 393 #define U TO + 1
 394   { 4, 12, 0, 0, 0 },
 395
 396   /* The UI field in a D form instruction.  */
 397 #define UI U + 1
 398   { 16, 0, 0, 0, 0 },
 399 };
 400
 401 /* The functions used to insert and extract complicated operands.  */
 402
 403 /* The BA field in an XL form instruction when it must be the same as
 404    the BT field in the same instruction.  This operand is marked FAKE.
 405    The insertion function just copies the BT field into the BA field,
 406    and the extraction function just checks that the fields are the
 407    same.  */
 408
 409 /*ARGSUSED*/
 410 static unsigned long
 411 insert_bat (insn, value, errmsg)
 412      unsigned long insn;
 413      long value;
 414      const char **errmsg;
 415 {
 416   return insn | (((insn >> 21) & 0x1f) << 16);
 417 }
 418
 419 static long
 420 extract_bat (insn, invalid)
 421      unsigned long insn;
 422      int *invalid;
 423 {
 424   if (invalid != (int *) NULL
 425       && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
 426     *invalid = 1;
 427   return 0;
 428 }
 429
 430 /* The BB field in an XL form instruction when it must be the same as
 431    the BA field in the same instruction.  This operand is marked FAKE.
 432    The insertion function just copies the BA field into the BB field,
 433    and the extraction function just checks that the fields are the
 434    same.  */
 435
 436 /*ARGSUSED*/
 437 static unsigned long
 438 insert_bba (insn, value, errmsg)
 439      unsigned long insn;
 440      long value;
 441      const char **errmsg;
 442 {
 443   return insn | (((insn >> 16) & 0x1f) << 11);
 444 }
 445
 446 static long
 447 extract_bba (insn, invalid)
 448      unsigned long insn;
 449      int *invalid;
 450 {
 451   if (invalid != (int *) NULL
 452       && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
 453     *invalid = 1;
 454   return 0;
 455 }
 456
 457 /* The BD field in a B form instruction.  The lower two bits are
 458    forced to zero.  */
 459
 460 /*ARGSUSED*/
 461 static unsigned long
 462 insert_bd (insn, value, errmsg)
 463      unsigned long insn;
 464      long value;
 465      const char **errmsg;
 466 {
 467   return insn | (value & 0xfffc);
 468 }
 469
 470 /*ARGSUSED*/
 471 static long
 472 extract_bd (insn, invalid)
 473      unsigned long insn;
 474      int *invalid;
 475 {
 476   if ((insn & 0x8000) != 0)
 477     return (insn & 0xfffc) - 0x10000;
 478   else
 479     return insn & 0xfffc;
 480 }
 481
 482 /* The BD field in a B form instruction when the - modifier is used.
 483    This modifier means that the branch is not expected to be taken.
 484    We must set the y bit of the BO field to 1 if the offset is
 485    negative.  When extracting, we require that the y bit be 1 and that
 486    the offset be positive, since if the y bit is 0 we just want to
 487    print the normal form of the instruction.  */
 488
 489 /*ARGSUSED*/
 490 static unsigned long
 491 insert_bdm (insn, value, errmsg)
 492      unsigned long insn;
 493      long value;
 494      const char **errmsg;
 495 {
 496   if ((value & 0x8000) != 0)
 497     insn |= 1 << 21;
 498   return insn | (value & 0xfffc);
 499 }
 500
 501 static long
 502 extract_bdm (insn, invalid)
 503      unsigned long insn;
 504      int *invalid;
 505 {
 506   if (invalid != (int *) NULL
 507       && ((insn & (1 << 21)) == 0
 508           || (insn & (1 << 15)) == 0))
 509     *invalid = 1;
 510   if ((insn & 0x8000) != 0)
 511     return (insn & 0xfffc) - 0x10000;
 512   else
 513     return insn & 0xfffc;
 514 }
 515
 516 /* The BD field in a B form instruction when the + modifier is used.
 517    This is like BDM, above, except that the branch is expected to be
 518    taken.  */
 519
 520 /*ARGSUSED*/
 521 static unsigned long
 522 insert_bdp (insn, value, errmsg)
 523      unsigned long insn;
 524      long value;
 525      const char **errmsg;
 526 {
 527   if ((value & 0x8000) == 0)
 528     insn |= 1 << 21;
 529   return insn | (value & 0xfffc);
 530 }
 531
 532 static long
 533 extract_bdp (insn, invalid)
 534      unsigned long insn;
 535      int *invalid;
 536 {
 537   if (invalid != (int *) NULL
 538       && ((insn & (1 << 21)) == 0
 539           || (insn & (1 << 15)) != 0))
 540     *invalid = 1;
 541   if ((insn & 0x8000) != 0)
 542     return (insn & 0xfffc) - 0x10000;
 543   else
 544     return insn & 0xfffc;
 545 }
 546
 547 /* Check for legal values of a BO field.  */
 548
 549 static int
 550 valid_bo (value)
 551      long value;
 552 {
 553   /* Certain encodings have bits that are required to be zero.  These
 554      are (z must be zero, y may be anything):
 555          001zy
 556          011zy
 557          1z00y
 558          1z01y
 559          1z1zz
 560      */
 561   switch (value & 0x14)
 562     {
 563     default:
 564     case 0:
 565       return 1;
 566     case 0x4:
 567       return (value & 0x2) == 0;
 568     case 0x10:
 569       return (value & 0x8) == 0;
 570     case 0x14:
 571       return value == 0x14;
 572     }
 573 }
 574
 575 /* The BO field in a B form instruction.  Warn about attempts to set
 576    the field to an illegal value.  */
 577
 578 static unsigned long
 579 insert_bo (insn, value, errmsg)
 580      unsigned long insn;
 581      long value;
 582      const char **errmsg;
 583 {
 584   if (errmsg != (const char **) NULL
 585       && ! valid_bo (value))
 586     *errmsg = _("invalid conditional option");
 587   return insn | ((value & 0x1f) << 21);
 588 }
 589
 590 static long
 591 extract_bo (insn, invalid)
 592      unsigned long insn;
 593      int *invalid;
 594 {
 595   long value;
 596
 597   value = (insn >> 21) & 0x1f;
 598   if (invalid != (int *) NULL
 599       && ! valid_bo (value))
 600     *invalid = 1;
 601   return value;
 602 }
 603
 604 /* The BO field in a B form instruction when the + or - modifier is
 605    used.  This is like the BO field, but it must be even.  When
 606    extracting it, we force it to be even.  */
 607
 608 static unsigned long
 609 insert_boe (insn, value, errmsg)
 610      unsigned long insn;
 611      long value;
 612      const char **errmsg;
 613 {
 614   if (errmsg != (const char **) NULL)
 615     {
 616       if (! valid_bo (value))
 617         *errmsg = _("invalid conditional option");
 618       else if ((value & 1) != 0)
 619         *errmsg = _("attempt to set y bit when using + or - modifier");
 620     }
 621   return insn | ((value & 0x1f) << 21);
 622 }
 623
 624 static long
 625 extract_boe (insn, invalid)
 626      unsigned long insn;
 627      int *invalid;
 628 {
 629   long value;
 630
 631   value = (insn >> 21) & 0x1f;
 632   if (invalid != (int *) NULL
 633       && ! valid_bo (value))
 634     *invalid = 1;
 635   return value & 0x1e;
 636 }
 637
 638 /* The DS field in a DS form instruction.  This is like D, but the
 639    lower two bits are forced to zero.  */
 640
 641 /*ARGSUSED*/
 642 static unsigned long
 643 insert_ds (insn, value, errmsg)
 644      unsigned long insn;
 645      long value;
 646      const char **errmsg;
 647 {
 648   return insn | (value & 0xfffc);
 649 }
 650
 651 /*ARGSUSED*/
 652 static long
 653 extract_ds (insn, invalid)
 654      unsigned long insn;
 655      int *invalid;
 656 {
 657   if ((insn & 0x8000) != 0)
 658     return (insn & 0xfffc) - 0x10000;
 659   else
 660     return insn & 0xfffc;
 661 }
 662
 663 /* The LI field in an I form instruction.  The lower two bits are
 664    forced to zero.  */
 665
 666 /*ARGSUSED*/
 667 static unsigned long
 668 insert_li (insn, value, errmsg)
 669      unsigned long insn;
 670      long value;
 671      const char **errmsg;
 672 {
 673   if ((value & 3) != 0 && errmsg != (const char **) NULL)
 674     *errmsg = _("ignoring least significant bits in branch offset");
 675   return insn | (value & 0x3fffffc);
 676 }
 677
 678 /*ARGSUSED*/
 679 static long
 680 extract_li (insn, invalid)
 681      unsigned long insn;
 682      int *invalid;
 683 {
 684   if ((insn & 0x2000000) != 0)
 685     return (insn & 0x3fffffc) - 0x4000000;
 686   else
 687     return insn & 0x3fffffc;
 688 }
 689
 690 /* The MB and ME fields in an M form instruction expressed as a single
 691    operand which is itself a bitmask.  The extraction function always
 692    marks it as invalid, since we never want to recognize an
 693    instruction which uses a field of this type.  */
 694
 695 static unsigned long
 696 insert_mbe (insn, value, errmsg)
 697      unsigned long insn;
 698      long value;
 699      const char **errmsg;
 700 {
 701   unsigned long uval, mask;
 702   int mb, me, mx, count, last;
 703
 704   uval = value;
 705
 706   if (uval == 0)
 707     {
 708       if (errmsg != (const char **) NULL)
 709         *errmsg = _("illegal bitmask");
 710       return insn;
 711     }
 712
 713   mb = 0;
 714   me = 32;
 715   if ((uval & 1) != 0)
 716     last = 1;
 717   else
 718     last = 0;
 719   count = 0;
 720
 721   /* mb: location of last 0->1 transition */
 722   /* me: location of last 1->0 transition */
 723   /* count: # transitions */
 724
 725   for (mx = 0, mask = 1 << 31; mx < 32; ++mx, mask >>= 1)
 726     {
 727       if ((uval & mask) && !last)
 728         {
 729           ++count;
 730           mb = mx;
 731           last = 1;
 732         }
 733       else if (!(uval & mask) && last)
 734         {
 735           ++count;
 736           me = mx;
 737           last = 0;
 738         }
 739     }
 740   if (me == 0)
 741     me = 32;
 742
 743   if (count != 2 && (count != 0 || ! last))
 744     {
 745       if (errmsg != (const char **) NULL)
 746         *errmsg = _("illegal bitmask");
 747     }
 748
 749   return insn | (mb << 6) | ((me - 1) << 1);
 750 }
 751
 752 static long
 753 extract_mbe (insn, invalid)
 754      unsigned long insn;
 755      int *invalid;
 756 {
 757   long ret;
 758   int mb, me;
 759   int i;
 760
 761   if (invalid != (int *) NULL)
 762     *invalid = 1;
 763
 764   mb = (insn >> 6) & 0x1f;
 765   me = (insn >> 1) & 0x1f;
 766   if (mb < me + 1)
 767     {
 768       ret = 0;
 769       for (i = mb; i <= me; i++)
 770         ret |= (long) 1 << (31 - i);
 771     }
 772   else if (mb == me + 1)
 773     ret = ~0;
 774   else /* (mb > me + 1) */
 775     {
 776       ret = ~ (long) 0;
 777       for (i = me + 1; i < mb; i++)
 778         ret &= ~ ((long) 1 << (31 - i));
 779     }
 780   return ret;
 781 }
 782
 783 /* The MB or ME field in an MD or MDS form instruction.  The high bit
 784    is wrapped to the low end.  */
 785
 786 /*ARGSUSED*/
 787 static unsigned long
 788 insert_mb6 (insn, value, errmsg)
 789      unsigned long insn;
 790      long value;
 791      const char **errmsg;
 792 {
 793   return insn | ((value & 0x1f) << 6) | (value & 0x20);
 794 }
 795
 796 /*ARGSUSED*/
 797 static long
 798 extract_mb6 (insn, invalid)
 799      unsigned long insn;
 800      int *invalid;
 801 {
 802   return ((insn >> 6) & 0x1f) | (insn & 0x20);
 803 }
 804
 805 /* The NB field in an X form instruction.  The value 32 is stored as
 806    0.  */
 807
 808 static unsigned long
 809 insert_nb (insn, value, errmsg)
 810      unsigned long insn;
 811      long value;
 812      const char **errmsg;
 813 {
 814   if (value < 0 || value > 32)
 815     *errmsg = _("value out of range");
 816   if (value == 32)
 817     value = 0;
 818   return insn | ((value & 0x1f) << 11);
 819 }
 820
 821 /*ARGSUSED*/
 822 static long
 823 extract_nb (insn, invalid)
 824      unsigned long insn;
 825      int *invalid;
 826 {
 827   long ret;
 828
 829   ret = (insn >> 11) & 0x1f;
 830   if (ret == 0)
 831     ret = 32;
 832   return ret;
 833 }
 834
 835 /* The NSI field in a D form instruction.  This is the same as the SI
 836    field, only negated.  The extraction function always marks it as
 837    invalid, since we never want to recognize an instruction which uses
 838    a field of this type.  */
 839
 840 /*ARGSUSED*/
 841 static unsigned long
 842 insert_nsi (insn, value, errmsg)
 843      unsigned long insn;
 844      long value;
 845      const char **errmsg;
 846 {
 847   return insn | ((- value) & 0xffff);
 848 }
 849
 850 static long
 851 extract_nsi (insn, invalid)
 852      unsigned long insn;
 853      int *invalid;
 854 {
 855   if (invalid != (int *) NULL)
 856     *invalid = 1;
 857   if ((insn & 0x8000) != 0)
 858     return - ((long)(insn & 0xffff) - 0x10000);
 859   else
 860     return - (long)(insn & 0xffff);
 861 }
 862
 863 /* The RA field in a D or X form instruction which is an updating
 864    load, which means that the RA field may not be zero and may not
 865    equal the RT field.  */
 866
 867 static unsigned long
 868 insert_ral (insn, value, errmsg)
 869      unsigned long insn;
 870      long value;
 871      const char **errmsg;
 872 {
 873   if (value == 0
 874       || (unsigned long) value == ((insn >> 21) & 0x1f))
 875     *errmsg = "invalid register operand when updating";
 876   return insn | ((value & 0x1f) << 16);
 877 }
 878
 879 /* The RA field in an lmw instruction, which has special value
 880    restrictions.  */
 881
 882 static unsigned long
 883 insert_ram (insn, value, errmsg)
 884      unsigned long insn;
 885      long value;
 886      const char **errmsg;
 887 {
 888   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
 889     *errmsg = _("index register in load range");
 890   return insn | ((value & 0x1f) << 16);
 891 }
 892
 893 /* The RA field in a D or X form instruction which is an updating
 894    store or an updating floating point load, which means that the RA
 895    field may not be zero.  */
 896
 897 static unsigned long
 898 insert_ras (insn, value, errmsg)
 899      unsigned long insn;
 900      long value;
 901      const char **errmsg;
 902 {
 903   if (value == 0)
 904     *errmsg = _("invalid register operand when updating");
 905   return insn | ((value & 0x1f) << 16);
 906 }
 907
 908 /* The RB field in an X form instruction when it must be the same as
 909    the RS field in the instruction.  This is used for extended
 910    mnemonics like mr.  This operand is marked FAKE.  The insertion
 911    function just copies the BT field into the BA field, and the
 912    extraction function just checks that the fields are the same.  */
 913
 914 /*ARGSUSED*/
 915 static unsigned long
 916 insert_rbs (insn, value, errmsg)
 917      unsigned long insn;
 918      long value;
 919      const char **errmsg;
 920 {
 921   return insn | (((insn >> 21) & 0x1f) << 11);
 922 }
 923
 924 static long
 925 extract_rbs (insn, invalid)
 926      unsigned long insn;
 927      int *invalid;
 928 {
 929   if (invalid != (int *) NULL
 930       && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
 931     *invalid = 1;
 932   return 0;
 933 }
 934
 935 /* The SH field in an MD form instruction.  This is split.  */
 936
 937 /*ARGSUSED*/
 938 static unsigned long
 939 insert_sh6 (insn, value, errmsg)
 940      unsigned long insn;
 941      long value;
 942      const char **errmsg;
 943 {
 944   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
 945 }
 946
 947 /*ARGSUSED*/
 948 static long
 949 extract_sh6 (insn, invalid)
 950      unsigned long insn;
 951      int *invalid;
 952 {
 953   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
 954 }
 955
 956 /* The SPR field in an XFX form instruction.  This is flipped--the
 957    lower 5 bits are stored in the upper 5 and vice- versa.  */
 958
 959 static unsigned long
 960 insert_spr (insn, value, errmsg)
 961      unsigned long insn;
 962      long value;
 963      const char **errmsg;
 964 {
 965   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
 966 }
 967
 968 static long
 969 extract_spr (insn, invalid)
 970      unsigned long insn;
 971      int *invalid;
 972 {
 973   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
 974 }
 975
 976 /* The TBR field in an XFX instruction.  This is just like SPR, but it
 977    is optional.  When TBR is omitted, it must be inserted as 268 (the
 978    magic number of the TB register).  These functions treat 0
 979    (indicating an omitted optional operand) as 268.  This means that
 980    ``mftb 4,0'' is not handled correctly.  This does not matter very
 981    much, since the architecture manual does not define mftb as
 982    accepting any values other than 268 or 269.  */
 983
 984 #define TB (268)
 985
 986 static unsigned long
 987 insert_tbr (insn, value, errmsg)
 988      unsigned long insn;
 989      long value;
 990      const char **errmsg;
 991 {
 992   if (value == 0)
 993     value = TB;
 994   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
 995 }
 996
 997 static long
 998 extract_tbr (insn, invalid)
 999      unsigned long insn;
1000      int *invalid;
1001 {
1002   long ret;
1003
1004   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1005   if (ret == TB)
1006     ret = 0;
1007   return ret;
1008 }
1009 \f
1010 /* Macros used to form opcodes.  */
1011
1012 /* The main opcode.  */
1013 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1014 #define OP_MASK OP (0x3f)
1015
1016 /* The main opcode combined with a trap code in the TO field of a D
1017    form instruction.  Used for extended mnemonics for the trap
1018    instructions.  */
1019 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1020 #define OPTO_MASK (OP_MASK | TO_MASK)
1021
1022 /* The main opcode combined with a comparison size bit in the L field
1023    of a D form or X form instruction.  Used for extended mnemonics for
1024    the comparison instructions.  */
1025 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1026 #define OPL_MASK OPL (0x3f,1)
1027
1028 /* An A form instruction.  */
1029 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1030 #define A_MASK A (0x3f, 0x1f, 1)
1031
1032 /* An A_MASK with the FRB field fixed.  */
1033 #define AFRB_MASK (A_MASK | FRB_MASK)
1034
1035 /* An A_MASK with the FRC field fixed.  */
1036 #define AFRC_MASK (A_MASK | FRC_MASK)
1037
1038 /* An A_MASK with the FRA and FRC fields fixed.  */
1039 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1040
1041 /* A B form instruction.  */
1042 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1043 #define B_MASK B (0x3f, 1, 1)
1044
1045 /* A B form instruction setting the BO field.  */
1046 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1047 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1048
1049 /* A BBO_MASK with the y bit of the BO field removed.  This permits
1050    matching a conditional branch regardless of the setting of the y
1051    bit.  */
1052 #define Y_MASK (((unsigned long)1) << 21)
1053 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1054
1055 /* A B form instruction setting the BO field and the condition bits of
1056    the BI field.  */
1057 #define BBOCB(op, bo, cb, aa, lk) \
1058   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1059 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1060
1061 /* A BBOCB_MASK with the y bit of the BO field removed.  */
1062 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1063
1064 /* A BBOYCB_MASK in which the BI field is fixed.  */
1065 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1066
1067 /* The main opcode mask with the RA field clear.  */
1068 #define DRA_MASK (OP_MASK | RA_MASK)
1069
1070 /* A DS form instruction.  */
1071 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1072 #define DS_MASK DSO (0x3f, 3)
1073
1074 /* An M form instruction.  */
1075 #define M(op, rc) (OP (op) | ((rc) & 1))
1076 #define M_MASK M (0x3f, 1)
1077
1078 /* An M form instruction with the ME field specified.  */
1079 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1080
1081 /* An M_MASK with the MB and ME fields fixed.  */
1082 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1083
1084 /* An M_MASK with the SH and ME fields fixed.  */
1085 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1086
1087 /* An MD form instruction.  */
1088 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1089 #define MD_MASK MD (0x3f, 0x7, 1)
1090
1091 /* An MD_MASK with the MB field fixed.  */
1092 #define MDMB_MASK (MD_MASK | MB6_MASK)
1093
1094 /* An MD_MASK with the SH field fixed.  */
1095 #define MDSH_MASK (MD_MASK | SH6_MASK)
1096
1097 /* An MDS form instruction.  */
1098 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1099 #define MDS_MASK MDS (0x3f, 0xf, 1)
1100
1101 /* An MDS_MASK with the MB field fixed.  */
1102 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1103
1104 /* An SC form instruction.  */
1105 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1106 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1107
1108 /* An X form instruction.  */
1109 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1110
1111 /* An X form instruction with the RC bit specified.  */
1112 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1113
1114 /* The mask for an X form instruction.  */
1115 #define X_MASK XRC (0x3f, 0x3ff, 1)
1116
1117 /* An X_MASK with the RA field fixed.  */
1118 #define XRA_MASK (X_MASK | RA_MASK)
1119
1120 /* An X_MASK with the RB field fixed.  */
1121 #define XRB_MASK (X_MASK | RB_MASK)
1122
1123 /* An X_MASK with the RT field fixed.  */
1124 #define XRT_MASK (X_MASK | RT_MASK)
1125
1126 /* An X_MASK with the RA and RB fields fixed.  */
1127 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1128
1129 /* An X_MASK with the RT and RA fields fixed.  */
1130 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1131
1132 /* An X form comparison instruction.  */
1133 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1134
1135 /* The mask for an X form comparison instruction.  */
1136 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1137
1138 /* The mask for an X form comparison instruction with the L field
1139    fixed.  */
1140 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1141
1142 /* An X form trap instruction with the TO field specified.  */
1143 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1144 #define XTO_MASK (X_MASK | TO_MASK)
1145
1146 /* An XFL form instruction.  */
1147 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1148 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1149
1150 /* An XL form instruction with the LK field set to 0.  */
1151 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1152
1153 /* An XL form instruction which uses the LK field.  */
1154 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1155
1156 /* The mask for an XL form instruction.  */
1157 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1158
1159 /* An XL form instruction which explicitly sets the BO field.  */
1160 #define XLO(op, bo, xop, lk) \
1161   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1162 #define XLO_MASK (XL_MASK | BO_MASK)
1163
1164 /* An XL form instruction which explicitly sets the y bit of the BO
1165    field.  */
1166 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1167 #define XLYLK_MASK (XL_MASK | Y_MASK)
1168
1169 /* An XL form instruction which sets the BO field and the condition
1170    bits of the BI field.  */
1171 #define XLOCB(op, bo, cb, xop, lk) \
1172   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1173 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1174
1175 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1176 #define XLBB_MASK (XL_MASK | BB_MASK)
1177 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1178 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1179
1180 /* An XL_MASK with the BO and BB fields fixed.  */
1181 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1182
1183 /* An XL_MASK with the BO, BI and BB fields fixed.  */
1184 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1185
1186 /* An XO form instruction.  */
1187 #define XO(op, xop, oe, rc) \
1188   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1189 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1190
1191 /* An XO_MASK with the RB field fixed.  */
1192 #define XORB_MASK (XO_MASK | RB_MASK)
1193
1194 /* An XS form instruction.  */
1195 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1196 #define XS_MASK XS (0x3f, 0x1ff, 1)
1197
1198 /* A mask for the FXM version of an XFX form instruction.  */
1199 #define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1200
1201 /* An XFX form instruction with the FXM field filled in.  */
1202 #define XFXM(op, xop, fxm) \
1203   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1204
1205 /* An XFX form instruction with the SPR field filled in.  */
1206 #define XSPR(op, xop, spr) \
1207   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1208 #define XSPR_MASK (X_MASK | SPR_MASK)
1209
1210 /* An XFX form instruction with the SPR field filled in except for the
1211    SPRBAT field.  */
1212 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1213
1214 /* An XFX form instruction with the SPR field filled in except for the
1215    SPRG field.  */
1216 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1217
1218 /* An X form instruction with everything filled in except the E field.  */
1219 #define XE_MASK (0xffff7fff)
1220
1221 /* The BO encodings used in extended conditional branch mnemonics.  */
1222 #define BODNZF  (0x0)
1223 #define BODNZFP (0x1)
1224 #define BODZF   (0x2)
1225 #define BODZFP  (0x3)
1226 #define BOF     (0x4)
1227 #define BOFP    (0x5)
1228 #define BODNZT  (0x8)
1229 #define BODNZTP (0x9)
1230 #define BODZT   (0xa)
1231 #define BODZTP  (0xb)
1232 #define BOT     (0xc)
1233 #define BOTP    (0xd)
1234 #define BODNZ   (0x10)
1235 #define BODNZP  (0x11)
1236 #define BODZ    (0x12)
1237 #define BODZP   (0x13)
1238 #define BOU     (0x14)
1239
1240 /* The BI condition bit encodings used in extended conditional branch
1241    mnemonics.  */
1242 #define CBLT    (0)
1243 #define CBGT    (1)
1244 #define CBEQ    (2)
1245 #define CBSO    (3)
1246
1247 /* The TO encodings used in extended trap mnemonics.  */
1248 #define TOLGT   (0x1)
1249 #define TOLLT   (0x2)
1250 #define TOEQ    (0x4)
1251 #define TOLGE   (0x5)
1252 #define TOLNL   (0x5)
1253 #define TOLLE   (0x6)
1254 #define TOLNG   (0x6)
1255 #define TOGT    (0x8)
1256 #define TOGE    (0xc)
1257 #define TONL    (0xc)
1258 #define TOLT    (0x10)
1259 #define TOLE    (0x14)
1260 #define TONG    (0x14)
1261 #define TONE    (0x18)
1262 #define TOU     (0x1f)
1263 \f
1264 /* Smaller names for the flags so each entry in the opcodes table will
1265    fit on a single line.  */
1266 #undef  PPC
1267 #define PPC     PPC_OPCODE_PPC | PPC_OPCODE_ANY
1268 #define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1269 #define PPC32   PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY
1270 #define PPC64   PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY
1271 #define PPCONLY PPC_OPCODE_PPC
1272 #define PPC403  PPC
1273 #define PPC750  PPC
1274 #define PPC860  PPC
1275 #define POWER   PPC_OPCODE_POWER | PPC_OPCODE_ANY
1276 #define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1277 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1278 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1279 #define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1280 #define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1281 #define M601    PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1282 #define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1283 #define MFDEC1  PPC_OPCODE_POWER
1284 #define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601
1285 \f
1286 /* The opcode table.
1287
1288    The format of the opcode table is:
1289
1290    NAME      OPCODE     MASK            FLAGS           { OPERANDS }
1291
1292    NAME is the name of the instruction.
1293    OPCODE is the instruction opcode.
1294    MASK is the opcode mask; this is used to tell the disassembler
1295      which bits in the actual opcode must match OPCODE.
1296    FLAGS are flags indicated what processors support the instruction.
1297    OPERANDS is the list of operands.
1298
1299    The disassembler reads the table in order and prints the first
1300    instruction which matches, so this table is sorted to put more
1301    specific instructions before more general instructions.  It is also
1302    sorted by major opcode.  */
1303
1304 const struct powerpc_opcode powerpc_opcodes[] = {
1305 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
1306 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
1307 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
1308 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
1309 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
1310 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
1311 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
1312 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
1313 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
1314 { "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
1315 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
1316 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
1317 { "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
1318 { "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
1319 { "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },
1320
1321 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1322 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1323 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
1324 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
1325 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
1326 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
1327 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1328 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1329 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
1330 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
1331 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
1332 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
1333 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
1334 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
1335 { "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1336 { "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1337 { "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1338 { "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1339 { "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
1340 { "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
1341 { "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
1342 { "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
1343 { "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1344 { "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1345 { "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
1346 { "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
1347 { "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
1348 { "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
1349 { "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
1350 { "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },
1351
1352 { "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
1353 { "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
1354
1355 { "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
1356 { "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },
1357
1358 { "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },
1359
1360 { "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
1361 { "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
1362 { "cmpli",   OP(10),    OP_MASK,        PPCONLY,        { BF, L, RA, UI } },
1363 { "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },
1364
1365 { "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
1366 { "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
1367 { "cmpi",    OP(11),    OP_MASK,        PPCONLY,        { BF, L, RA, SI } },
1368 { "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },
1369
1370 { "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1371 { "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
1372 { "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1373
1374 { "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1375 { "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
1376 { "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1377
1378 { "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
1379 { "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
1380 { "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
1381 { "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA } },
1382 { "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1383 { "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA } },
1384
1385 { "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
1386 { "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
1387 { "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA,SISIGNOPT } },
1388 { "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA,SISIGNOPT } },
1389 { "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },
1390
1391 { "bdnz-",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC,       { BDM } },
1392 { "bdnz+",   BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC,       { BDP } },
1393 { "bdnz",    BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM,    { BD } },
1394 { "bdn",     BBO(16,BODNZ,0,0), BBOYBI_MASK, PWRCOM,    { BD } },
1395 { "bdnzl-",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC,       { BDM } },
1396 { "bdnzl+",  BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC,       { BDP } },
1397 { "bdnzl",   BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM,    { BD } },
1398 { "bdnl",    BBO(16,BODNZ,0,1), BBOYBI_MASK, PWRCOM,    { BD } },
1399 { "bdnza-",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC,       { BDMA } },
1400 { "bdnza+",  BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC,       { BDPA } },
1401 { "bdnza",   BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM,    { BDA } },
1402 { "bdna",    BBO(16,BODNZ,1,0), BBOYBI_MASK, PWRCOM,    { BDA } },
1403 { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC,       { BDMA } },
1404 { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC,       { BDPA } },
1405 { "bdnzla",  BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM,    { BDA } },
1406 { "bdnla",   BBO(16,BODNZ,1,1), BBOYBI_MASK, PWRCOM,    { BDA } },
1407 { "bdz-",    BBO(16,BODZ,0,0),  BBOYBI_MASK, PPC,       { BDM } },
1408 { "bdz+",    BBO(16,BODZ,0,0),  BBOYBI_MASK, PPC,       { BDP } },
1409 { "bdz",     BBO(16,BODZ,0,0),  BBOYBI_MASK, COM,       { BD } },
1410 { "bdzl-",   BBO(16,BODZ,0,1),  BBOYBI_MASK, PPC,       { BDM } },
1411 { "bdzl+",   BBO(16,BODZ,0,1),  BBOYBI_MASK, PPC,       { BDP } },
1412 { "bdzl",    BBO(16,BODZ,0,1),  BBOYBI_MASK, COM,       { BD } },
1413 { "bdza-",   BBO(16,BODZ,1,0),  BBOYBI_MASK, PPC,       { BDMA } },
1414 { "bdza+",   BBO(16,BODZ,1,0),  BBOYBI_MASK, PPC,       { BDPA } },
1415 { "bdza",    BBO(16,BODZ,1,0),  BBOYBI_MASK, COM,       { BDA } },
1416 { "bdzla-",  BBO(16,BODZ,1,1),  BBOYBI_MASK, PPC,       { BDMA } },
1417 { "bdzla+",  BBO(16,BODZ,1,1),  BBOYBI_MASK, PPC,       { BDPA } },
1418 { "bdzla",   BBO(16,BODZ,1,1),  BBOYBI_MASK, COM,       { BDA } },
1419 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1420 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1421 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, COM,  { CR, BD } },
1422 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1423 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1424 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, COM,  { CR, BD } },
1425 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1426 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1427 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, COM,  { CR, BDA } },
1428 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1429 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1430 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, COM,  { CR, BDA } },
1431 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1432 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1433 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, COM,  { CR, BD } },
1434 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1435 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1436 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, COM,  { CR, BD } },
1437 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1438 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1439 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, COM,  { CR, BDA } },
1440 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1441 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1442 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, COM,  { CR, BDA } },
1443 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1444 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1445 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, COM,  { CR, BD } },
1446 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1447 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1448 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, COM,  { CR, BD } },
1449 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1450 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1451 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, COM,  { CR, BDA } },
1452 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1453 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1454 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, COM,  { CR, BDA } },
1455 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1456 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1457 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, COM,  { CR, BD } },
1458 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1459 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1460 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, COM,  { CR, BD } },
1461 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1462 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1463 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, COM,  { CR, BDA } },
1464 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1465 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1466 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, COM,  { CR, BDA } },
1467 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1468 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1469 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } },
1470 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1471 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1472 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } },
1473 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1474 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1475 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1476 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1477 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1478 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1479 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1480 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1481 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM,  { CR, BD } },
1482 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1483 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1484 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM,  { CR, BD } },
1485 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1486 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1487 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM,  { CR, BDA } },
1488 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1489 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1490 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM,  { CR, BDA } },
1491 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1492 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1493 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM,  { CR, BD } },
1494 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1495 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1496 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM,  { CR, BD } },
1497 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1498 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1499 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM,  { CR, BDA } },
1500 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1501 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1502 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM,  { CR, BDA } },
1503 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1504 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1505 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM,  { CR, BD } },
1506 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1507 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1508 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM,  { CR, BD } },
1509 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1510 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1511 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM,  { CR, BDA } },
1512 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1513 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1514 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM,  { CR, BDA } },
1515 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1516 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1517 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM,  { CR, BD } },
1518 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1519 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1520 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM,  { CR, BD } },
1521 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1522 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1523 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM,  { CR, BDA } },
1524 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1525 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1526 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM,  { CR, BDA } },
1527 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1528 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1529 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, COM,  { CR, BD } },
1530 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1531 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1532 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, COM,  { CR, BD } },
1533 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1534 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1535 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, COM,  { CR, BDA } },
1536 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1537 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1538 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, COM,  { CR, BDA } },
1539 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1540 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1541 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, COM,  { CR, BD } },
1542 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1543 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1544 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, COM,  { CR, BD } },
1545 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1546 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1547 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, COM,  { CR, BDA } },
1548 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1549 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1550 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, COM,  { CR, BDA } },
1551 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDM } },
1552 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC,  { CR, BDP } },
1553 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } },
1554 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDM } },
1555 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC,  { CR, BDP } },
1556 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } },
1557 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDMA } },
1558 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC,  { CR, BDPA } },
1559 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1560 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDMA } },
1561 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC,  { CR, BDPA } },
1562 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1563 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, PPC,        { BI, BDM } },
1564 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, PPC,        { BI, BDP } },
1565 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
1566 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC,        { BI, BDM } },
1567 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC,        { BI, BDP } },
1568 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
1569 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC,        { BI, BDMA } },
1570 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC,        { BI, BDPA } },
1571 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
1572 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC,        { BI, BDMA } },
1573 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC,        { BI, BDPA } },
1574 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
1575 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, PPC,        { BI, BDM } },
1576 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, PPC,        { BI, BDP } },
1577 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
1578 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC,        { BI, BDM } },
1579 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC,        { BI, BDP } },
1580 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
1581 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC,        { BI, BDMA } },
1582 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC,        { BI, BDPA } },
1583 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
1584 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC,        { BI, BDMA } },
1585 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC,        { BI, BDPA } },
1586 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
1587 { "bt-",     BBO(16,BOT,0,0), BBOY_MASK, PPC,           { BI, BDM } },
1588 { "bt+",     BBO(16,BOT,0,0), BBOY_MASK, PPC,           { BI, BDP } },
1589 { "bt",      BBO(16,BOT,0,0), BBOY_MASK, PPCCOM,        { BI, BD } },
1590 { "bbt",     BBO(16,BOT,0,0), BBOY_MASK, PWRCOM,        { BI, BD } },
1591 { "btl-",    BBO(16,BOT,0,1), BBOY_MASK, PPC,           { BI, BDM } },
1592 { "btl+",    BBO(16,BOT,0,1), BBOY_MASK, PPC,           { BI, BDP } },
1593 { "btl",     BBO(16,BOT,0,1), BBOY_MASK, PPCCOM,        { BI, BD } },
1594 { "bbtl",    BBO(16,BOT,0,1), BBOY_MASK, PWRCOM,        { BI, BD } },
1595 { "bta-",    BBO(16,BOT,1,0), BBOY_MASK, PPC,           { BI, BDMA } },
1596 { "bta+",    BBO(16,BOT,1,0), BBOY_MASK, PPC,           { BI, BDPA } },
1597 { "bta",     BBO(16,BOT,1,0), BBOY_MASK, PPCCOM,        { BI, BDA } },
1598 { "bbta",    BBO(16,BOT,1,0), BBOY_MASK, PWRCOM,        { BI, BDA } },
1599 { "btla-",   BBO(16,BOT,1,1), BBOY_MASK, PPC,           { BI, BDMA } },
1600 { "btla+",   BBO(16,BOT,1,1), BBOY_MASK, PPC,           { BI, BDPA } },
1601 { "btla",    BBO(16,BOT,1,1), BBOY_MASK, PPCCOM,        { BI, BDA } },
1602 { "bbtla",   BBO(16,BOT,1,1), BBOY_MASK, PWRCOM,        { BI, BDA } },
1603 { "bf-",     BBO(16,BOF,0,0), BBOY_MASK, PPC,           { BI, BDM } },
1604 { "bf+",     BBO(16,BOF,0,0), BBOY_MASK, PPC,           { BI, BDP } },
1605 { "bf",      BBO(16,BOF,0,0), BBOY_MASK, PPCCOM,        { BI, BD } },
1606 { "bbf",     BBO(16,BOF,0,0), BBOY_MASK, PWRCOM,        { BI, BD } },
1607 { "bfl-",    BBO(16,BOF,0,1), BBOY_MASK, PPC,           { BI, BDM } },
1608 { "bfl+",    BBO(16,BOF,0,1), BBOY_MASK, PPC,           { BI, BDP } },
1609 { "bfl",     BBO(16,BOF,0,1), BBOY_MASK, PPCCOM,        { BI, BD } },
1610 { "bbfl",    BBO(16,BOF,0,1), BBOY_MASK, PWRCOM,        { BI, BD } },
1611 { "bfa-",    BBO(16,BOF,1,0), BBOY_MASK, PPC,           { BI, BDMA } },
1612 { "bfa+",    BBO(16,BOF,1,0), BBOY_MASK, PPC,           { BI, BDPA } },
1613 { "bfa",     BBO(16,BOF,1,0), BBOY_MASK, PPCCOM,        { BI, BDA } },
1614 { "bbfa",    BBO(16,BOF,1,0), BBOY_MASK, PWRCOM,        { BI, BDA } },
1615 { "bfla-",   BBO(16,BOF,1,1), BBOY_MASK, PPC,           { BI, BDMA } },
1616 { "bfla+",   BBO(16,BOF,1,1), BBOY_MASK, PPC,           { BI, BDPA } },
1617 { "bfla",    BBO(16,BOF,1,1), BBOY_MASK, PPCCOM,        { BI, BDA } },
1618 { "bbfla",   BBO(16,BOF,1,1), BBOY_MASK, PWRCOM,        { BI, BDA } },
1619 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, PPC,         { BI, BDM } },
1620 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, PPC,         { BI, BDP } },
1621 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
1622 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, PPC,         { BI, BDM } },
1623 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, PPC,         { BI, BDP } },
1624 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
1625 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, PPC,         { BI, BDMA } },
1626 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, PPC,         { BI, BDPA } },
1627 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
1628 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC,         { BI, BDMA } },
1629 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC,         { BI, BDPA } },
1630 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
1631 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, PPC,         { BI, BDM } },
1632 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, PPC,         { BI, BDP } },
1633 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
1634 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, PPC,         { BI, BDM } },
1635 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, PPC,         { BI, BDP } },
1636 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
1637 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, PPC,         { BI, BDMA } },
1638 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, PPC,         { BI, BDPA } },
1639 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
1640 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC,         { BI, BDMA } },
1641 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC,         { BI, BDPA } },
1642 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
1643 { "bc-",     B(16,0,0), B_MASK,         PPC,            { BOE, BI, BDM } },
1644 { "bc+",     B(16,0,0), B_MASK,         PPC,            { BOE, BI, BDP } },
1645 { "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
1646 { "bcl-",    B(16,0,1), B_MASK,         PPC,            { BOE, BI, BDM } },
1647 { "bcl+",    B(16,0,1), B_MASK,         PPC,            { BOE, BI, BDP } },
1648 { "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
1649 { "bca-",    B(16,1,0), B_MASK,         PPC,            { BOE, BI, BDMA } },
1650 { "bca+",    B(16,1,0), B_MASK,         PPC,            { BOE, BI, BDPA } },
1651 { "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
1652 { "bcla-",   B(16,1,1), B_MASK,         PPC,            { BOE, BI, BDMA } },
1653 { "bcla+",   B(16,1,1), B_MASK,         PPC,            { BOE, BI, BDPA } },
1654 { "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },
1655
1656 { "sc",      SC(17,1,0), 0xffffffff,    PPC,            { 0 } },
1657 { "svc",     SC(17,0,0), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
1658 { "svcl",    SC(17,0,1), SC_MASK,       POWER,          { LEV, FL1, FL2 } },
1659 { "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
1660 { "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },
1661
1662 { "b",       B(18,0,0), B_MASK,         COM,    { LI } },
1663 { "bl",      B(18,0,1), B_MASK,         COM,    { LI } },
1664 { "ba",      B(18,1,0), B_MASK,         COM,    { LIA } },
1665 { "bla",     B(18,1,1), B_MASK,         COM,    { LIA } },
1666
1667 { "mcrf",    XL(19,0),  XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
1668
1669 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
1670 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
1671 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
1672 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
1673 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1674 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC,    { 0 } },
1675 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC,   { 0 } },
1676 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1677 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC,    { 0 } },
1678 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC,   { 0 } },
1679 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
1680 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC,     { 0 } },
1681 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC,    { 0 } },
1682 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
1683 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC,     { 0 } },
1684 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC,    { 0 } },
1685 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1686 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1687 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1688 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1689 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1690 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1691 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1692 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1693 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1694 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1695 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1696 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1697 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1698 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1699 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1700 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1701 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1702 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1703 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1704 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1705 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1706 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1707 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1708 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1709 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1710 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1711 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1712 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1713 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1714 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1715 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1716 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1717 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1718 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1719 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1720 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1721 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1722 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1723 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1724 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1725 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1726 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1727 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1728 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1729 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1730 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1731 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1732 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1733 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1734 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1735 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1736 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1737 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1738 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1739 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1740 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1741 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1742 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1743 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1744 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1745 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1746 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1747 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1748 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1749 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } },
1750 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1751 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1752 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1753 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } },
1754 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1755 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1756 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1757 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } },
1758 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1759 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1760 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1761 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } },
1762 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1763 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1764 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1765 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1766 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1767 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1768 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1769 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1770 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1771 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1772 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1773 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } },
1774 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1775 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1776 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } },
1777 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
1778 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, PPC,        { BI } },
1779 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, PPC,       { BI } },
1780 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
1781 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
1782 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, PPC,        { BI } },
1783 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, PPC,       { BI } },
1784 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
1785 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
1786 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, PPC,        { BI } },
1787 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, PPC,       { BI } },
1788 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
1789 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
1790 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, PPC,        { BI } },
1791 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, PPC,       { BI } },
1792 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
1793 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
1794 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC,     { BI } },
1795 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC,    { BI } },
1796 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
1797 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC,    { BI } },
1798 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC,   { BI } },
1799 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
1800 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC,     { BI } },
1801 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC,    { BI } },
1802 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
1803 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC,    { BI } },
1804 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC,   { BI } },
1805 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
1806 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC,      { BI } },
1807 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC,     { BI } },
1808 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
1809 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC,      { BI } },
1810 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC,     { BI } },
1811 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
1812 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC,      { BI } },
1813 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC,     { BI } },
1814 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
1815 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC,      { BI } },
1816 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC,     { BI } },
1817 { "bclr",    XLLK(19,16,0), XLYBB_MASK, PPCCOM,         { BO, BI } },
1818 { "bclrl",   XLLK(19,16,1), XLYBB_MASK, PPCCOM,         { BO, BI } },
1819 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPC,         { BOE, BI } },
1820 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPC,         { BOE, BI } },
1821 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPC,         { BOE, BI } },
1822 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPC,         { BOE, BI } },
1823 { "bcr",     XLLK(19,16,0), XLBB_MASK,  PWRCOM,         { BO, BI } },
1824 { "bcrl",    XLLK(19,16,1), XLBB_MASK,  PWRCOM,         { BO, BI } },
1825
1826 { "crnot",   XL(19,33), XL_MASK,        PPCCOM,         { BT, BA, BBA } },
1827 { "crnor",   XL(19,33), XL_MASK,        COM,            { BT, BA, BB } },
1828
1829 { "rfi",     XL(19,50), 0xffffffff,     COM,            { 0 } },
1830 { "rfci",    XL(19,51), 0xffffffff,     PPC,            { 0 } },
1831
1832 { "rfsvc",   XL(19,82), 0xffffffff,     POWER,          { 0 } },
1833
1834 { "crandc",  XL(19,129), XL_MASK,       COM,            { BT, BA, BB } },
1835
1836 { "isync",   XL(19,150), 0xffffffff,    PPCCOM,         { 0 } },
1837 { "ics",     XL(19,150), 0xffffffff,    PWRCOM,         { 0 } },
1838
1839 { "crclr",   XL(19,193), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
1840 { "crxor",   XL(19,193), XL_MASK,       COM,            { BT, BA, BB } },
1841
1842 { "crnand",  XL(19,225), XL_MASK,       COM,            { BT, BA, BB } },
1843
1844 { "crand",   XL(19,257), XL_MASK,       COM,            { BT, BA, BB } },
1845
1846 { "crset",   XL(19,289), XL_MASK,       PPCCOM,         { BT, BAT, BBA } },
1847 { "creqv",   XL(19,289), XL_MASK,       COM,            { BT, BA, BB } },
1848
1849 { "crorc",   XL(19,417), XL_MASK,       COM,            { BT, BA, BB } },
1850
1851 { "crmove",  XL(19,449), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
1852 { "cror",    XL(19,449), XL_MASK,       COM,            { BT, BA, BB } },
1853
1854 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
1855 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
1856 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1857 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPC,     { CR } },
1858 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC,     { CR } },
1859 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1860 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPC,     { CR } },
1861 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC,     { CR } },
1862 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1863 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPC,     { CR } },
1864 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC,     { CR } },
1865 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1866 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPC,     { CR } },
1867 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC,     { CR } },
1868 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1869 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPC,     { CR } },
1870 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC,     { CR } },
1871 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1872 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPC,     { CR } },
1873 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC,     { CR } },
1874 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1875 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPC,     { CR } },
1876 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC,     { CR } },
1877 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1878 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPC,     { CR } },
1879 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC,     { CR } },
1880 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1881 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPC,     { CR } },
1882 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC,     { CR } },
1883 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1884 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPC,     { CR } },
1885 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC,     { CR } },
1886 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1887 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPC,     { CR } },
1888 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC,     { CR } },
1889 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1890 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPC,     { CR } },
1891 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC,     { CR } },
1892 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1893 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPC,     { CR } },
1894 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC,     { CR } },
1895 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1896 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPC,     { CR } },
1897 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC,     { CR } },
1898 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1899 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPC,     { CR } },
1900 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC,     { CR } },
1901 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1902 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPC,     { CR } },
1903 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC,     { CR } },
1904 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1905 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPC,     { CR } },
1906 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC,     { CR } },
1907 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1908 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPC,     { CR } },
1909 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC,     { CR } },
1910 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1911 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPC,     { CR } },
1912 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC,     { CR } },
1913 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1914 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPC,     { CR } },
1915 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC,     { CR } },
1916 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1917 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPC,     { CR } },
1918 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC,     { CR } },
1919 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1920 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPC,     { CR } },
1921 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC,     { CR } },
1922 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1923 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPC,     { CR } },
1924 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC,     { CR } },
1925 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,  { CR } },
1926 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPC,     { CR } },
1927 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC,     { CR } },
1928 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
1929 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, PPC,      { BI } },
1930 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, PPC,      { BI } },
1931 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
1932 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, PPC,      { BI } },
1933 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC,      { BI } },
1934 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
1935 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, PPC,      { BI } },
1936 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, PPC,      { BI } },
1937 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
1938 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, PPC,      { BI } },
1939 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC,      { BI } },
1940 { "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
1941 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPC,      { BOE, BI } },
1942 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPC,      { BOE, BI } },
1943 { "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,   { BO, BI } },
1944 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPC,      { BOE, BI } },
1945 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPC,      { BOE, BI } },
1946 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
1947 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
1948
1949 { "rlwimi",  M(20,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
1950 { "rlimi",   M(20,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
1951
1952 { "rlwimi.", M(20,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
1953 { "rlimi.",  M(20,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
1954
1955 { "rotlwi",  MME(21,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, SH } },
1956 { "clrlwi",  MME(21,31,0), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
1957 { "rlwinm",  M(21,0),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
1958 { "rlinm",   M(21,0),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
1959 { "rotlwi.", MME(21,31,1), MMBME_MASK,  PPCCOM,         { RA,RS,SH } },
1960 { "clrlwi.", MME(21,31,1), MSHME_MASK,  PPCCOM,         { RA, RS, MB } },
1961 { "rlwinm.", M(21,1),   M_MASK,         PPCCOM,         { RA,RS,SH,MBE,ME } },
1962 { "rlinm.",  M(21,1),   M_MASK,         PWRCOM,         { RA,RS,SH,MBE,ME } },
1963
1964 { "rlmi",    M(22,0),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
1965 { "rlmi.",   M(22,1),   M_MASK,         M601,           { RA,RS,RB,MBE,ME } },
1966
1967 { "rotlw",   MME(23,31,0), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
1968 { "rlwnm",   M(23,0),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
1969 { "rlnm",    M(23,0),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
1970 { "rotlw.",  MME(23,31,1), MMBME_MASK,  PPCCOM,         { RA, RS, RB } },
1971 { "rlwnm.",  M(23,1),   M_MASK,         PPCCOM,         { RA,RS,RB,MBE,ME } },
1972 { "rlnm.",   M(23,1),   M_MASK,         PWRCOM,         { RA,RS,RB,MBE,ME } },
1973
1974 { "nop",     OP(24),    0xffffffff,     PPCCOM,         { 0 } },
1975 { "ori",     OP(24),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
1976 { "oril",    OP(24),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
1977
1978 { "oris",    OP(25),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
1979 { "oriu",    OP(25),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
1980
1981 { "xori",    OP(26),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
1982 { "xoril",   OP(26),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
1983
1984 { "xoris",   OP(27),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
1985 { "xoriu",   OP(27),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
1986
1987 { "andi.",   OP(28),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
1988 { "andil.",  OP(28),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
1989
1990 { "andis.",  OP(29),    OP_MASK,        PPCCOM,         { RA, RS, UI } },
1991 { "andiu.",  OP(29),    OP_MASK,        PWRCOM,         { RA, RS, UI } },
1992
1993 { "rotldi",  MD(30,0,0), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
1994 { "clrldi",  MD(30,0,0), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
1995 { "rldicl",  MD(30,0,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
1996 { "rotldi.", MD(30,0,1), MDMB_MASK,     PPC64,          { RA, RS, SH6 } },
1997 { "clrldi.", MD(30,0,1), MDSH_MASK,     PPC64,          { RA, RS, MB6 } },
1998 { "rldicl.", MD(30,0,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
1999
2000 { "rldicr",  MD(30,1,0), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
2001 { "rldicr.", MD(30,1,1), MD_MASK,       PPC64,          { RA, RS, SH6, ME6 } },
2002
2003 { "rldic",   MD(30,2,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2004 { "rldic.",  MD(30,2,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2005
2006 { "rldimi",  MD(30,3,0), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2007 { "rldimi.", MD(30,3,1), MD_MASK,       PPC64,          { RA, RS, SH6, MB6 } },
2008
2009 { "rotld",   MDS(30,8,0), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
2010 { "rldcl",   MDS(30,8,0), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
2011 { "rotld.",  MDS(30,8,1), MDSMB_MASK,   PPC64,          { RA, RS, RB } },
2012 { "rldcl.",  MDS(30,8,1), MDS_MASK,     PPC64,          { RA, RS, RB, MB6 } },
2013
2014 { "rldcr",   MDS(30,9,0), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
2015 { "rldcr.",  MDS(30,9,1), MDS_MASK,     PPC64,          { RA, RS, RB, ME6 } },
2016
2017 { "cmpw",    XCMPL(31,0,0), XCMPL_MASK, PPCCOM,         { OBF, RA, RB } },
2018 { "cmpd",    XCMPL(31,0,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
2019 { "cmp",     X(31,0),   XCMP_MASK,      PPCONLY,        { BF, L, RA, RB } },
2020 { "cmp",     X(31,0),   XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
2021
2022 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,         { RA, RB } },
2023 { "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,         { RA, RB } },
2024 { "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,         { RA, RB } },
2025 { "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,         { RA, RB } },
2026 { "tweq",    XTO(31,4,TOEQ), XTO_MASK,  PPCCOM,         { RA, RB } },
2027 { "teq",     XTO(31,4,TOEQ), XTO_MASK,  PWRCOM,         { RA, RB } },
2028 { "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,         { RA, RB } },
2029 { "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,         { RA, RB } },
2030 { "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,         { RA, RB } },
2031 { "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,         { RA, RB } },
2032 { "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,         { RA, RB } },
2033 { "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,         { RA, RB } },
2034 { "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,         { RA, RB } },
2035 { "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,         { RA, RB } },
2036 { "twgt",    XTO(31,4,TOGT), XTO_MASK,  PPCCOM,         { RA, RB } },
2037 { "tgt",     XTO(31,4,TOGT), XTO_MASK,  PWRCOM,         { RA, RB } },
2038 { "twge",    XTO(31,4,TOGE), XTO_MASK,  PPCCOM,         { RA, RB } },
2039 { "tge",     XTO(31,4,TOGE), XTO_MASK,  PWRCOM,         { RA, RB } },
2040 { "twnl",    XTO(31,4,TONL), XTO_MASK,  PPCCOM,         { RA, RB } },
2041 { "tnl",     XTO(31,4,TONL), XTO_MASK,  PWRCOM,         { RA, RB } },
2042 { "twlt",    XTO(31,4,TOLT), XTO_MASK,  PPCCOM,         { RA, RB } },
2043 { "tlt",     XTO(31,4,TOLT), XTO_MASK,  PWRCOM,         { RA, RB } },
2044 { "twle",    XTO(31,4,TOLE), XTO_MASK,  PPCCOM,         { RA, RB } },
2045 { "tle",     XTO(31,4,TOLE), XTO_MASK,  PWRCOM,         { RA, RB } },
2046 { "twng",    XTO(31,4,TONG), XTO_MASK,  PPCCOM,         { RA, RB } },
2047 { "tng",     XTO(31,4,TONG), XTO_MASK,  PWRCOM,         { RA, RB } },
2048 { "twne",    XTO(31,4,TONE), XTO_MASK,  PPCCOM,         { RA, RB } },
2049 { "tne",     XTO(31,4,TONE), XTO_MASK,  PWRCOM,         { RA, RB } },
2050 { "trap",    XTO(31,4,TOU), 0xffffffff, PPCCOM,         { 0 } },
2051 { "tw",      X(31,4),   X_MASK,         PPCCOM,         { TO, RA, RB } },
2052 { "t",       X(31,4),   X_MASK,         PWRCOM,         { TO, RA, RB } },
2053
2054 { "subfc",   XO(31,8,0,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2055 { "sf",      XO(31,8,0,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2056 { "subc",    XO(31,8,0,0), XO_MASK,     PPC,            { RT, RB, RA } },
2057 { "subfc.",  XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2058 { "sf.",     XO(31,8,0,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2059 { "subc.",   XO(31,8,0,1), XO_MASK,     PPCCOM,         { RT, RB, RA } },
2060 { "subfco",  XO(31,8,1,0), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2061 { "sfo",     XO(31,8,1,0), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2062 { "subco",   XO(31,8,1,0), XO_MASK,     PPC,            { RT, RB, RA } },
2063 { "subfco.", XO(31,8,1,1), XO_MASK,     PPCCOM,         { RT, RA, RB } },
2064 { "sfo.",    XO(31,8,1,1), XO_MASK,     PWRCOM,         { RT, RA, RB } },
2065 { "subco.",  XO(31,8,1,1), XO_MASK,     PPC,            { RT, RB, RA } },
2066
2067 { "mulhdu",  XO(31,9,0,0), XO_MASK,     PPC64,          { RT, RA, RB } },
2068 { "mulhdu.", XO(31,9,0,1), XO_MASK,     PPC64,          { RT, RA, RB } },
2069
2070 { "addc",    XO(31,10,0,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2071 { "a",       XO(31,10,0,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2072 { "addc.",   XO(31,10,0,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2073 { "a.",      XO(31,10,0,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2074 { "addco",   XO(31,10,1,0), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2075 { "ao",      XO(31,10,1,0), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2076 { "addco.",  XO(31,10,1,1), XO_MASK,    PPCCOM,         { RT, RA, RB } },
2077 { "ao.",     XO(31,10,1,1), XO_MASK,    PWRCOM,         { RT, RA, RB } },
2078
2079 { "mulhwu",  XO(31,11,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2080 { "mulhwu.", XO(31,11,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2081
2082 { "mfcr",    X(31,19),  XRARB_MASK,     COM,            { RT } },
2083
2084 { "lwarx",   X(31,20),  X_MASK,         PPC,            { RT, RA, RB } },
2085
2086 { "ldx",     X(31,21),  X_MASK,         PPC64,          { RT, RA, RB } },
2087
2088 { "lwzx",    X(31,23),  X_MASK,         PPCCOM,         { RT, RA, RB } },
2089 { "lx",      X(31,23),  X_MASK,         PWRCOM,         { RT, RA, RB } },
2090
2091 { "slw",     XRC(31,24,0), X_MASK,      PPCCOM,         { RA, RS, RB } },
2092 { "sl",      XRC(31,24,0), X_MASK,      PWRCOM,         { RA, RS, RB } },
2093 { "slw.",    XRC(31,24,1), X_MASK,      PPCCOM,         { RA, RS, RB } },
2094 { "sl.",     XRC(31,24,1), X_MASK,      PWRCOM,         { RA, RS, RB } },
2095
2096 { "cntlzw",  XRC(31,26,0), XRB_MASK,    PPCCOM,         { RA, RS } },
2097 { "cntlz",   XRC(31,26,0), XRB_MASK,    PWRCOM,         { RA, RS } },
2098 { "cntlzw.", XRC(31,26,1), XRB_MASK,    PPCCOM,         { RA, RS } },
2099 { "cntlz.",  XRC(31,26,1), XRB_MASK,    PWRCOM,         { RA, RS } },
2100
2101 { "sld",     XRC(31,27,0), X_MASK,      PPC64,          { RA, RS, RB } },
2102 { "sld.",    XRC(31,27,1), X_MASK,      PPC64,          { RA, RS, RB } },
2103
2104 { "and",     XRC(31,28,0), X_MASK,      COM,            { RA, RS, RB } },
2105 { "and.",    XRC(31,28,1), X_MASK,      COM,            { RA, RS, RB } },
2106
2107 { "maskg",   XRC(31,29,0), X_MASK,      M601,           { RA, RS, RB } },
2108 { "maskg.",  XRC(31,29,1), X_MASK,      M601,           { RA, RS, RB } },
2109
2110 { "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPCCOM,        { OBF, RA, RB } },
2111 { "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC64,         { OBF, RA, RB } },
2112 { "cmpl",    X(31,32),  XCMP_MASK,       PPCONLY,       { BF, L, RA, RB } },
2113 { "cmpl",    X(31,32),  XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
2114
2115 { "subf",    XO(31,40,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2116 { "sub",     XO(31,40,0,0), XO_MASK,    PPC,            { RT, RB, RA } },
2117 { "subf.",   XO(31,40,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2118 { "sub.",    XO(31,40,0,1), XO_MASK,    PPC,            { RT, RB, RA } },
2119 { "subfo",   XO(31,40,1,0), XO_MASK,    PPC,            { RT, RA, RB } },
2120 { "subo",    XO(31,40,1,0), XO_MASK,    PPC,            { RT, RB, RA } },
2121 { "subfo.",  XO(31,40,1,1), XO_MASK,    PPC,            { RT, RA, RB } },
2122 { "subo.",   XO(31,40,1,1), XO_MASK,    PPC,            { RT, RB, RA } },
2123
2124 { "ldux",    X(31,53),  X_MASK,         PPC64,          { RT, RAL, RB } },
2125
2126 { "dcbst",   X(31,54),  XRT_MASK,       PPC,            { RA, RB } },
2127
2128 { "lwzux",   X(31,55),  X_MASK,         PPCCOM,         { RT, RAL, RB } },
2129 { "lux",     X(31,55),  X_MASK,         PWRCOM,         { RT, RA, RB } },
2130
2131 { "cntlzd",  XRC(31,58,0), XRB_MASK,    PPC64,          { RA, RS } },
2132 { "cntlzd.", XRC(31,58,1), XRB_MASK,    PPC64,          { RA, RS } },
2133
2134 { "andc",    XRC(31,60,0), X_MASK,      COM,    { RA, RS, RB } },
2135 { "andc.",   XRC(31,60,1), X_MASK,      COM,    { RA, RS, RB } },
2136
2137 { "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,         { RA, RB } },
2138 { "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,         { RA, RB } },
2139 { "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,         { RA, RB } },
2140 { "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,         { RA, RB } },
2141 { "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,         { RA, RB } },
2142 { "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,         { RA, RB } },
2143 { "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,         { RA, RB } },
2144 { "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,         { RA, RB } },
2145 { "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,         { RA, RB } },
2146 { "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,         { RA, RB } },
2147 { "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,         { RA, RB } },
2148 { "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,         { RA, RB } },
2149 { "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,         { RA, RB } },
2150 { "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,         { RA, RB } },
2151 { "td",      X(31,68),  X_MASK,          PPC64,         { TO, RA, RB } },
2152
2153 { "mulhd",   XO(31,73,0,0), XO_MASK,     PPC64,         { RT, RA, RB } },
2154 { "mulhd.",  XO(31,73,0,1), XO_MASK,     PPC64,         { RT, RA, RB } },
2155
2156 { "mulhw",   XO(31,75,0,0), XO_MASK,    PPC,            { RT, RA, RB } },
2157 { "mulhw.",  XO(31,75,0,1), XO_MASK,    PPC,            { RT, RA, RB } },
2158
2159 { "mfmsr",   X(31,83),  XRARB_MASK,     COM,            { RT } },
2160
2161 { "ldarx",   X(31,84),  X_MASK,         PPC64,          { RT, RA, RB } },
2162
2163 { "dcbf",    X(31,86),  XRT_MASK,       PPC,            { RA, RB } },
2164
2165 { "lbzx",    X(31,87),  X_MASK,         COM,            { RT, RA, RB } },
2166
2167 { "neg",     XO(31,104,0,0), XORB_MASK, COM,            { RT, RA } },
2168 { "neg.",    XO(31,104,0,1), XORB_MASK, COM,            { RT, RA } },
2169 { "nego",    XO(31,104,1,0), XORB_MASK, COM,            { RT, RA } },
2170 { "nego.",   XO(31,104,1,1), XORB_MASK, COM,            { RT, RA } },
2171
2172 { "mul",     XO(31,107,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2173 { "mul.",    XO(31,107,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2174 { "mulo",    XO(31,107,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2175 { "mulo.",   XO(31,107,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2176
2177 { "clf",     X(31,118), XRB_MASK,       POWER,          { RT, RA } },
2178
2179 { "lbzux",   X(31,119), X_MASK,         COM,            { RT, RAL, RB } },
2180
2181 { "not",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RBS } },
2182 { "nor",     XRC(31,124,0), X_MASK,     COM,            { RA, RS, RB } },
2183 { "not.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RBS } },
2184 { "nor.",    XRC(31,124,1), X_MASK,     COM,            { RA, RS, RB } },
2185
2186 { "wrtee",   X(31,131), XRARB_MASK,     PPC403,         { RS } },
2187
2188 { "subfe",   XO(31,136,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2189 { "sfe",     XO(31,136,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2190 { "subfe.",  XO(31,136,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2191 { "sfe.",    XO(31,136,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2192 { "subfeo",  XO(31,136,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2193 { "sfeo",    XO(31,136,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2194 { "subfeo.", XO(31,136,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2195 { "sfeo.",   XO(31,136,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2196
2197 { "adde",    XO(31,138,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2198 { "ae",      XO(31,138,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2199 { "adde.",   XO(31,138,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2200 { "ae.",     XO(31,138,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2201 { "addeo",   XO(31,138,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2202 { "aeo",     XO(31,138,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2203 { "addeo.",  XO(31,138,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2204 { "aeo.",    XO(31,138,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2205
2206 { "mtcr",    XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM,      { RS }},
2207 { "mtcrf",   X(31,144), XFXFXM_MASK,    COM,            { FXM, RS } },
2208
2209 { "mtmsr",   X(31,146), XRARB_MASK,     COM,            { RS } },
2210
2211 { "stdx",    X(31,149), X_MASK,         PPC64,          { RS, RA, RB } },
2212
2213 { "stwcx.",  XRC(31,150,1), X_MASK,     PPC,            { RS, RA, RB } },
2214
2215 { "stwx",    X(31,151), X_MASK,         PPCCOM,         { RS, RA, RB } },
2216 { "stx",     X(31,151), X_MASK,         PWRCOM,         { RS, RA, RB } },
2217
2218 { "slq",     XRC(31,152,0), X_MASK,     M601,           { RA, RS, RB } },
2219 { "slq.",    XRC(31,152,1), X_MASK,     M601,           { RA, RS, RB } },
2220
2221 { "sle",     XRC(31,153,0), X_MASK,     M601,           { RA, RS, RB } },
2222 { "sle.",    XRC(31,153,1), X_MASK,     M601,           { RA, RS, RB } },
2223
2224 { "wrteei",  X(31,163), XE_MASK,        PPC403,         { E } },
2225
2226 { "stdux",   X(31,181), X_MASK,         PPC64,          { RS, RAS, RB } },
2227
2228 { "stwux",   X(31,183), X_MASK,         PPCCOM,         { RS, RAS, RB } },
2229 { "stux",    X(31,183), X_MASK,         PWRCOM,         { RS, RA, RB } },
2230
2231 { "sliq",    XRC(31,184,0), X_MASK,     M601,           { RA, RS, SH } },
2232 { "sliq.",   XRC(31,184,1), X_MASK,     M601,           { RA, RS, SH } },
2233
2234 { "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2235 { "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2236 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2237 { "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2238 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2239 { "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2240 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2241 { "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2242
2243 { "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2244 { "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2245 { "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2246 { "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2247 { "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2248 { "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2249 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2250 { "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2251
2252 { "mtsr",    X(31,210), XRB_MASK|(1<<20), COM32,        { SR, RS } },
2253
2254 { "stdcx.",  XRC(31,214,1), X_MASK,     PPC64,          { RS, RA, RB } },
2255
2256 { "stbx",    X(31,215), X_MASK,         COM,    { RS, RA, RB } },
2257
2258 { "sllq",    XRC(31,216,0), X_MASK,     M601,           { RA, RS, RB } },
2259 { "sllq.",   XRC(31,216,1), X_MASK,     M601,           { RA, RS, RB } },
2260
2261 { "sleq",    XRC(31,217,0), X_MASK,     M601,           { RA, RS, RB } },
2262 { "sleq.",   XRC(31,217,1), X_MASK,     M601,           { RA, RS, RB } },
2263
2264 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2265 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2266 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2267 { "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2268 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2269 { "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2270 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2271 { "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2272
2273 { "mulld",   XO(31,233,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2274 { "mulld.",  XO(31,233,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2275 { "mulldo",  XO(31,233,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2276 { "mulldo.", XO(31,233,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2277
2278 { "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,         { RT, RA } },
2279 { "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,         { RT, RA } },
2280 { "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,         { RT, RA } },
2281 { "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,         { RT, RA } },
2282 { "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,         { RT, RA } },
2283 { "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,         { RT, RA } },
2284 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,         { RT, RA } },
2285 { "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,         { RT, RA } },
2286
2287 { "mullw",   XO(31,235,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2288 { "muls",    XO(31,235,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2289 { "mullw.",  XO(31,235,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2290 { "muls.",   XO(31,235,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2291 { "mullwo",  XO(31,235,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2292 { "mulso",   XO(31,235,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2293 { "mullwo.", XO(31,235,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2294 { "mulso.",  XO(31,235,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2295
2296 { "mtsrin",  X(31,242), XRA_MASK,       PPC32,          { RS, RB } },
2297 { "mtsri",   X(31,242), XRA_MASK,       POWER32,        { RS, RB } },
2298
2299 { "dcbtst",  X(31,246), XRT_MASK,       PPC,            { RA, RB } },
2300
2301 { "stbux",   X(31,247), X_MASK,         COM,            { RS, RAS, RB } },
2302
2303 { "slliq",   XRC(31,248,0), X_MASK,     M601,           { RA, RS, SH } },
2304 { "slliq.",  XRC(31,248,1), X_MASK,     M601,           { RA, RS, SH } },
2305
2306 { "doz",     XO(31,264,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2307 { "doz.",    XO(31,264,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2308 { "dozo",    XO(31,264,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2309 { "dozo.",   XO(31,264,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2310
2311 { "add",     XO(31,266,0,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2312 { "cax",     XO(31,266,0,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2313 { "add.",    XO(31,266,0,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2314 { "cax.",    XO(31,266,0,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2315 { "addo",    XO(31,266,1,0), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2316 { "caxo",    XO(31,266,1,0), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2317 { "addo.",   XO(31,266,1,1), XO_MASK,   PPCCOM,         { RT, RA, RB } },
2318 { "caxo.",   XO(31,266,1,1), XO_MASK,   PWRCOM,         { RT, RA, RB } },
2319
2320 { "lscbx",   XRC(31,277,0), X_MASK,     M601,           { RT, RA, RB } },
2321 { "lscbx.",  XRC(31,277,1), X_MASK,     M601,           { RT, RA, RB } },
2322
2323 { "dcbt",    X(31,278), XRT_MASK,       PPC,            { RA, RB } },
2324
2325 { "lhzx",    X(31,279), X_MASK,         COM,            { RT, RA, RB } },
2326
2327 { "icbt",    X(31,262), XRT_MASK,       PPC,            { RA, RB } },
2328
2329 { "eqv",     XRC(31,284,0), X_MASK,     COM,            { RA, RS, RB } },
2330 { "eqv.",    XRC(31,284,1), X_MASK,     COM,            { RA, RS, RB } },
2331
2332 { "tlbie",   X(31,306), XRTRA_MASK,     PPC,            { RB } },
2333 { "tlbi",    X(31,306), XRT_MASK,       POWER,          { RA, RB } },
2334
2335 { "eciwx",   X(31,310), X_MASK,         PPC,            { RT, RA, RB } },
2336
2337 { "lhzux",   X(31,311), X_MASK,         COM,            { RT, RAL, RB } },
2338
2339 { "xor",     XRC(31,316,0), X_MASK,     COM,            { RA, RS, RB } },
2340 { "xor.",    XRC(31,316,1), X_MASK,     COM,            { RA, RS, RB } },
2341
2342 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403,        { RT } },
2343 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403,        { RT } },
2344 { "mfbr0",   XSPR(31,323,128), XSPR_MASK, PPC403,       { RT } },
2345 { "mfbr1",   XSPR(31,323,129), XSPR_MASK, PPC403,       { RT } },
2346 { "mfbr2",   XSPR(31,323,130), XSPR_MASK, PPC403,       { RT } },
2347 { "mfbr3",   XSPR(31,323,131), XSPR_MASK, PPC403,       { RT } },
2348 { "mfbr4",   XSPR(31,323,132), XSPR_MASK, PPC403,       { RT } },
2349 { "mfbr5",   XSPR(31,323,133), XSPR_MASK, PPC403,       { RT } },
2350 { "mfbr6",   XSPR(31,323,134), XSPR_MASK, PPC403,       { RT } },
2351 { "mfbr7",   XSPR(31,323,135), XSPR_MASK, PPC403,       { RT } },
2352 { "mfbear",  XSPR(31,323,144), XSPR_MASK, PPC403,       { RT } },
2353 { "mfbesr",  XSPR(31,323,145), XSPR_MASK, PPC403,       { RT } },
2354 { "mfiocr",  XSPR(31,323,160), XSPR_MASK, PPC403,       { RT } },
2355 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,      { RT } },
2356 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,      { RT } },
2357 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,      { RT } },
2358 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,      { RT } },
2359 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,      { RT } },
2360 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,      { RT } },
2361 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,      { RT } },
2362 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,      { RT } },
2363 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,      { RT } },
2364 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,      { RT } },
2365 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,      { RT } },
2366 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,      { RT } },
2367 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,      { RT } },
2368 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,      { RT } },
2369 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,      { RT } },
2370 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,      { RT } },
2371 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,      { RT } },
2372 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,      { RT } },
2373 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,      { RT } },
2374 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,      { RT } },
2375 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403,       { RT } },
2376 { "mfdcr",   X(31,323), X_MASK,         PPC,            { RT, SPR } },
2377
2378 { "div",     XO(31,331,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2379 { "div.",    XO(31,331,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2380 { "divo",    XO(31,331,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2381 { "divo.",   XO(31,331,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2382
2383 { "mfmq",     XSPR(31,339,0),   XSPR_MASK, M601,        { RT } },
2384 { "mfxer",    XSPR(31,339,1),   XSPR_MASK, COM,         { RT } },
2385 { "mfrtcu",   XSPR(31,339,4),   XSPR_MASK, COM,         { RT } },
2386 { "mfrtcl",   XSPR(31,339,5),   XSPR_MASK, COM,         { RT } },
2387 { "mfdec",    XSPR(31,339,6),   XSPR_MASK, MFDEC1,      { RT } },
2388 { "mflr",     XSPR(31,339,8),   XSPR_MASK, COM,         { RT } },
2389 { "mfctr",    XSPR(31,339,9),   XSPR_MASK, COM,         { RT } },
2390 { "mftid",    XSPR(31,339,17),  XSPR_MASK, POWER,       { RT } },
2391 { "mfdsisr",  XSPR(31,339,18),  XSPR_MASK, COM,         { RT } },
2392 { "mfdar",    XSPR(31,339,19),  XSPR_MASK, COM,         { RT } },
2393 { "mfdec",    XSPR(31,339,22),  XSPR_MASK, MFDEC2,      { RT } },
2394 { "mfsdr0",   XSPR(31,339,24),  XSPR_MASK, POWER,       { RT } },
2395 { "mfsdr1",   XSPR(31,339,25),  XSPR_MASK, COM,         { RT } },
2396 { "mfsrr0",   XSPR(31,339,26),  XSPR_MASK, COM,         { RT } },
2397 { "mfsrr1",   XSPR(31,339,27),  XSPR_MASK, COM,         { RT } },
2398 { "mfcmpa",   XSPR(31,339,144), XSPR_MASK, PPC860,      { RT } },
2399 { "mfcmpb",   XSPR(31,339,145), XSPR_MASK, PPC860,      { RT } },
2400 { "mfcmpc",   XSPR(31,339,146), XSPR_MASK, PPC860,      { RT } },
2401 { "mfcmpd",   XSPR(31,339,147), XSPR_MASK, PPC860,      { RT } },
2402 { "mficr",    XSPR(31,339,148), XSPR_MASK, PPC860,      { RT } },
2403 { "mfder",    XSPR(31,339,149), XSPR_MASK, PPC860,      { RT } },
2404 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860,      { RT } },
2405 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860,      { RT } },
2406 { "mfcmpe",   XSPR(31,339,152), XSPR_MASK, PPC860,      { RT } },
2407 { "mfcmpf",   XSPR(31,339,153), XSPR_MASK, PPC860,      { RT } },
2408 { "mfcmpg",   XSPR(31,339,154), XSPR_MASK, PPC860,      { RT } },
2409 { "mfcmph",   XSPR(31,339,155), XSPR_MASK, PPC860,      { RT } },
2410 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860,      { RT } },
2411 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860,      { RT } },
2412 { "mfictrl",  XSPR(31,339,158), XSPR_MASK, PPC860,      { RT } },
2413 { "mfbar",    XSPR(31,339,159), XSPR_MASK, PPC860,      { RT } },
2414 { "mfsprg",   XSPR(31,339,272), XSPRG_MASK, PPC,        { RT, SPRG } },
2415 { "mfsprg0",  XSPR(31,339,272), XSPR_MASK, PPC,         { RT } },
2416 { "mfsprg1",  XSPR(31,339,273), XSPR_MASK, PPC,         { RT } },
2417 { "mfsprg2",  XSPR(31,339,274), XSPR_MASK, PPC,         { RT } },
2418 { "mfsprg3",  XSPR(31,339,275), XSPR_MASK, PPC,         { RT } },
2419 { "mfasr",    XSPR(31,339,280), XSPR_MASK, PPC64,       { RT } },
2420 { "mfear",    XSPR(31,339,282), XSPR_MASK, PPC,         { RT } },
2421 { "mfpvr",    XSPR(31,339,287), XSPR_MASK, PPC,         { RT } },
2422 { "mfibatu",  XSPR(31,339,528), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2423 { "mfibatl",  XSPR(31,339,529), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2424 { "mfdbatu",  XSPR(31,339,536), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2425 { "mfdbatl",  XSPR(31,339,537), XSPRBAT_MASK, PPC,      { RT, SPRBAT } },
2426 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860,      { RT } },
2427 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860,      { RT } },
2428 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860,      { RT } },
2429 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860,      { RT } },
2430 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860,      { RT } },
2431 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860,      { RT } },
2432 { "mfdpdr",   XSPR(31,339,630), XSPR_MASK, PPC860,      { RT } },
2433 { "mfdpir",   XSPR(31,339,631), XSPR_MASK, PPC860,      { RT } },
2434 { "mfimmr",   XSPR(31,339,638), XSPR_MASK, PPC860,      { RT } },
2435 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860,      { RT } },
2436 { "mfmi_ap",  XSPR(31,339,786), XSPR_MASK, PPC860,      { RT } },
2437 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860,      { RT } },
2438 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860,      { RT } },
2439 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860,      { RT } },
2440 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860,      { RT } },
2441 { "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860,      { RT } },
2442 { "mfmd_ap",  XSPR(31,339,794), XSPR_MASK, PPC860,      { RT } },
2443 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860,      { RT } },
2444 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860,      { RT } },
2445 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860,      { RT } },
2446 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860,      { RT } },
2447 { "mfm_tw",   XSPR(31,339,799), XSPR_MASK, PPC860,      { RT } },
2448 { "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860,     { RT } },
2449 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860,    { RT } },
2450 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860,    { RT } },
2451 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860,    { RT } },
2452 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860,    { RT } },
2453 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860,    { RT } },
2454 { "mfzpr",   XSPR(31,339,944), XSPR_MASK, PPC403,       { RT } },
2455 { "mfpid",   XSPR(31,339,945), XSPR_MASK, PPC403,       { RT } },
2456 { "mficdbdr",XSPR(31,339,979), XSPR_MASK, PPC403,       { RT } },
2457 { "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
2458 { "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
2459 { "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
2460 { "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
2461 { "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
2462 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
2463 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
2464 { "mfmmcr0",    XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
2465 { "mfpmc1",     XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
2466 { "mfpmc2",     XSPR(31,339,954),  XSPR_MASK, PPC750,   { RT } },
2467 { "mfsia",      XSPR(31,339,955),  XSPR_MASK, PPC750,   { RT } },
2468 { "mfmmcr1",    XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
2469 { "mfpmc3",     XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
2470 { "mfpmc4",     XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
2471 { "mfesr",   XSPR(31,339,980), XSPR_MASK, PPC403,       { RT } },
2472 { "mfdear",  XSPR(31,339,981), XSPR_MASK, PPC403,       { RT } },
2473 { "mfevpr",  XSPR(31,339,982), XSPR_MASK, PPC403,       { RT } },
2474 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403,       { RT } },
2475 { "mftsr",   XSPR(31,339,984), XSPR_MASK, PPC403,       { RT } },
2476 { "mftcr",   XSPR(31,339,986), XSPR_MASK, PPC403,       { RT } },
2477 { "mfpit",   XSPR(31,339,987), XSPR_MASK, PPC403,       { RT } },
2478 { "mftbhi",  XSPR(31,339,988), XSPR_MASK, PPC403,       { RT } },
2479 { "mftblo",  XSPR(31,339,989), XSPR_MASK, PPC403,       { RT } },
2480 { "mfsrr2",  XSPR(31,339,990), XSPR_MASK, PPC403,       { RT } },
2481 { "mfsrr3",  XSPR(31,339,991), XSPR_MASK, PPC403,       { RT } },
2482 { "mfdbsr",  XSPR(31,339,1008), XSPR_MASK, PPC403,      { RT } },
2483 { "mfiac1",  XSPR(31,339,1012), XSPR_MASK, PPC403,      { RT } },
2484 { "mfiac2",  XSPR(31,339,1013), XSPR_MASK, PPC403,      { RT } },
2485 { "mfdac1",  XSPR(31,339,1014), XSPR_MASK, PPC403,      { RT } },
2486 { "mfdac2",  XSPR(31,339,1015), XSPR_MASK, PPC403,      { RT } },
2487 { "mfdccr",  XSPR(31,339,1018), XSPR_MASK, PPC403,      { RT } },
2488 { "mficcr",  XSPR(31,339,1019), XSPR_MASK, PPC403,      { RT } },
2489 { "mfpbl1",  XSPR(31,339,1020), XSPR_MASK, PPC403,      { RT } },
2490 { "mfpbu1",  XSPR(31,339,1021), XSPR_MASK, PPC403,      { RT } },
2491 { "mfpbl2",  XSPR(31,339,1022), XSPR_MASK, PPC403,      { RT } },
2492 { "mfpbu2",  XSPR(31,339,1023), XSPR_MASK, PPC403,      { RT } },
2493 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
2494 { "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
2495 { "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
2496 { "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
2497 { "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
2498 { "mfspr",   X(31,339), X_MASK,         COM,            { RT, SPR } },
2499
2500 { "lwax",    X(31,341), X_MASK,         PPC64,          { RT, RA, RB } },
2501
2502 { "lhax",    X(31,343), X_MASK,         COM,            { RT, RA, RB } },
2503
2504 { "dccci",   X(31,454), XRT_MASK,       PPC,            { RA, RB } },
2505
2506 { "abs",     XO(31,360,0,0), XORB_MASK, M601,           { RT, RA } },
2507 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,           { RT, RA } },
2508 { "abso",    XO(31,360,1,0), XORB_MASK, M601,           { RT, RA } },
2509 { "abso.",   XO(31,360,1,1), XORB_MASK, M601,           { RT, RA } },
2510
2511 { "divs",    XO(31,363,0,0), XO_MASK,   M601,           { RT, RA, RB } },
2512 { "divs.",   XO(31,363,0,1), XO_MASK,   M601,           { RT, RA, RB } },
2513 { "divso",   XO(31,363,1,0), XO_MASK,   M601,           { RT, RA, RB } },
2514 { "divso.",  XO(31,363,1,1), XO_MASK,   M601,           { RT, RA, RB } },
2515
2516 { "tlbia",   X(31,370), 0xffffffff,     PPC,            { 0 } },
2517
2518 { "mftbu",   XSPR(31,371,269), XSPR_MASK, PPC,          { RT } },
2519 { "mftb",    X(31,371), X_MASK,         PPC,            { RT, TBR } },
2520
2521 { "lwaux",   X(31,373), X_MASK,         PPC64,          { RT, RAL, RB } },
2522
2523 { "lhaux",   X(31,375), X_MASK,         COM,            { RT, RAL, RB } },
2524
2525 { "sthx",    X(31,407), X_MASK,         COM,            { RS, RA, RB } },
2526
2527 { "lfqx",    X(31,791), X_MASK,         POWER2,         { FRT, RA, RB } },
2528
2529 { "lfqux",   X(31,823), X_MASK,         POWER2,         { FRT, RA, RB } },
2530
2531 { "stfqx",   X(31,919), X_MASK,         POWER2,         { FRS, RA, RB } },
2532
2533 { "stfqux",  X(31,951), X_MASK,         POWER2,         { FRS, RA, RB } },
2534
2535 { "orc",     XRC(31,412,0), X_MASK,     COM,            { RA, RS, RB } },
2536 { "orc.",    XRC(31,412,1), X_MASK,     COM,            { RA, RS, RB } },
2537
2538 { "sradi",   XS(31,413,0), XS_MASK,     PPC64,          { RA, RS, SH6 } },
2539 { "sradi.",  XS(31,413,1), XS_MASK,     PPC64,          { RA, RS, SH6 } },
2540
2541 { "slbie",   X(31,434), XRTRA_MASK,     PPC64,          { RB } },
2542
2543 { "ecowx",   X(31,438), X_MASK,         PPC,            { RT, RA, RB } },
2544
2545 { "sthux",   X(31,439), X_MASK,         COM,            { RS, RAS, RB } },
2546
2547 { "mr",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RBS } },
2548 { "or",      XRC(31,444,0), X_MASK,     COM,            { RA, RS, RB } },
2549 { "mr.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RBS } },
2550 { "or.",     XRC(31,444,1), X_MASK,     COM,            { RA, RS, RB } },
2551
2552 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403,        { RT } },
2553 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403,        { RT } },
2554 { "mtbr0",   XSPR(31,451,128), XSPR_MASK, PPC403,       { RT } },
2555 { "mtbr1",   XSPR(31,451,129), XSPR_MASK, PPC403,       { RT } },
2556 { "mtbr2",   XSPR(31,451,130), XSPR_MASK, PPC403,       { RT } },
2557 { "mtbr3",   XSPR(31,451,131), XSPR_MASK, PPC403,       { RT } },
2558 { "mtbr4",   XSPR(31,451,132), XSPR_MASK, PPC403,       { RT } },
2559 { "mtbr5",   XSPR(31,451,133), XSPR_MASK, PPC403,       { RT } },
2560 { "mtbr6",   XSPR(31,451,134), XSPR_MASK, PPC403,       { RT } },
2561 { "mtbr7",   XSPR(31,451,135), XSPR_MASK, PPC403,       { RT } },
2562 { "mtbear",  XSPR(31,451,144), XSPR_MASK, PPC403,       { RT } },
2563 { "mtbesr",  XSPR(31,451,145), XSPR_MASK, PPC403,       { RT } },
2564 { "mtiocr",  XSPR(31,451,160), XSPR_MASK, PPC403,       { RT } },
2565 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,      { RT } },
2566 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,      { RT } },
2567 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,      { RT } },
2568 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,      { RT } },
2569 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,      { RT } },
2570 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,      { RT } },
2571 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,      { RT } },
2572 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,      { RT } },
2573 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,      { RT } },
2574 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,      { RT } },
2575 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,      { RT } },
2576 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,      { RT } },
2577 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,      { RT } },
2578 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,      { RT } },
2579 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,      { RT } },
2580 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,      { RT } },
2581 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,      { RT } },
2582 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,      { RT } },
2583 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,      { RT } },
2584 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,      { RT } },
2585 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403,       { RT } },
2586 { "mtummcr0",   XSPR(31,451,936),  XSPR_MASK, PPC750,   { RT } },
2587 { "mtupmc1",    XSPR(31,451,937),  XSPR_MASK, PPC750,   { RT } },
2588 { "mtupmc2",    XSPR(31,451,938),  XSPR_MASK, PPC750,   { RT } },
2589 { "mtusia",     XSPR(31,451,939),  XSPR_MASK, PPC750,   { RT } },
2590 { "mtummcr1",   XSPR(31,451,940),  XSPR_MASK, PPC750,   { RT } },
2591 { "mtupmc3",    XSPR(31,451,941),  XSPR_MASK, PPC750,   { RT } },
2592 { "mtupmc4",    XSPR(31,451,942),  XSPR_MASK, PPC750,   { RT } },
2593 { "mtmmcr0",    XSPR(31,451,952),  XSPR_MASK, PPC750,   { RT } },
2594 { "mtpmc1",     XSPR(31,451,953),  XSPR_MASK, PPC750,   { RT } },
2595 { "mtpmc2",     XSPR(31,451,954),  XSPR_MASK, PPC750,   { RT } },
2596 { "mtsia",      XSPR(31,451,955),  XSPR_MASK, PPC750,   { RT } },
2597 { "mtmmcr1",    XSPR(31,451,956),  XSPR_MASK, PPC750,   { RT } },
2598 { "mtpmc3",     XSPR(31,451,957),  XSPR_MASK, PPC750,   { RT } },
2599 { "mtpmc4",     XSPR(31,451,958),  XSPR_MASK, PPC750,   { RT } },
2600 { "mtl2cr",     XSPR(31,451,1017), XSPR_MASK, PPC750,   { RT } },
2601 { "mtictc",     XSPR(31,451,1019), XSPR_MASK, PPC750,   { RT } },
2602 { "mtthrm1",    XSPR(31,451,1020), XSPR_MASK, PPC750,   { RT } },
2603 { "mtthrm2",    XSPR(31,451,1021), XSPR_MASK, PPC750,   { RT } },
2604 { "mtthrm3",    XSPR(31,451,1022), XSPR_MASK, PPC750,   { RT } },
2605 { "mtdcr",   X(31,451), X_MASK,         PPC,            { SPR, RS } },
2606
2607 { "divdu",   XO(31,457,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2608 { "divdu.",  XO(31,457,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2609 { "divduo",  XO(31,457,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2610 { "divduo.", XO(31,457,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2611
2612 { "divwu",   XO(31,459,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
2613 { "divwu.",  XO(31,459,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
2614 { "divwuo",  XO(31,459,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
2615 { "divwuo.", XO(31,459,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
2616
2617 { "mtmq",    XSPR(31,467,0),   XSPR_MASK,    M601,      { RS } },
2618 { "mtxer",   XSPR(31,467,1),   XSPR_MASK,    COM,       { RS } },
2619 { "mtlr",    XSPR(31,467,8),   XSPR_MASK,    COM,       { RS } },
2620 { "mtctr",   XSPR(31,467,9),   XSPR_MASK,    COM,       { RS } },
2621 { "mttid",   XSPR(31,467,17),  XSPR_MASK,    POWER,     { RS } },
2622 { "mtdsisr", XSPR(31,467,18),  XSPR_MASK,    COM,       { RS } },
2623 { "mtdar",   XSPR(31,467,19),  XSPR_MASK,    COM,       { RS } },
2624 { "mtrtcu",  XSPR(31,467,20),  XSPR_MASK,    COM,       { RS } },
2625 { "mtrtcl",  XSPR(31,467,21),  XSPR_MASK,    COM,       { RS } },
2626 { "mtdec",   XSPR(31,467,22),  XSPR_MASK,    COM,       { RS } },
2627 { "mtsdr0",  XSPR(31,467,24),  XSPR_MASK,    POWER,     { RS } },
2628 { "mtsdr1",  XSPR(31,467,25),  XSPR_MASK,    COM,       { RS } },
2629 { "mtsrr0",  XSPR(31,467,26),  XSPR_MASK,    COM,       { RS } },
2630 { "mtsrr1",  XSPR(31,467,27),  XSPR_MASK,    COM,       { RS } },
2631 { "mtcmpa",   XSPR(31,467,144), XSPR_MASK, PPC860,      { RT } },
2632 { "mtcmpb",   XSPR(31,467,145), XSPR_MASK, PPC860,      { RT } },
2633 { "mtcmpc",   XSPR(31,467,146), XSPR_MASK, PPC860,      { RT } },
2634 { "mtcmpd",   XSPR(31,467,147), XSPR_MASK, PPC860,      { RT } },
2635 { "mticr",    XSPR(31,467,148), XSPR_MASK, PPC860,      { RT } },
2636 { "mtder",    XSPR(31,467,149), XSPR_MASK, PPC860,      { RT } },
2637 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860,      { RT } },
2638 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860,      { RT } },
2639 { "mtcmpe",   XSPR(31,467,152), XSPR_MASK, PPC860,      { RT } },
2640 { "mtcmpf",   XSPR(31,467,153), XSPR_MASK, PPC860,      { RT } },
2641 { "mtcmpg",   XSPR(31,467,154), XSPR_MASK, PPC860,      { RT } },
2642 { "mtcmph",   XSPR(31,467,155), XSPR_MASK, PPC860,      { RT } },
2643 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860,      { RT } },
2644 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860,      { RT } },
2645 { "mtictrl",  XSPR(31,467,158), XSPR_MASK, PPC860,      { RT } },
2646 { "mtbar",    XSPR(31,467,159), XSPR_MASK, PPC860,      { RT } },
2647 { "mtsprg",  XSPR(31,467,272), XSPRG_MASK,   PPC,       { SPRG, RS } },
2648 { "mtsprg0", XSPR(31,467,272), XSPR_MASK,    PPC,       { RT } },
2649 { "mtsprg1", XSPR(31,467,273), XSPR_MASK,    PPC,       { RT } },
2650 { "mtsprg2", XSPR(31,467,274), XSPR_MASK,    PPC,       { RT } },
2651 { "mtsprg3", XSPR(31,467,275), XSPR_MASK,    PPC,       { RT } },
2652 { "mtasr",   XSPR(31,467,280), XSPR_MASK,    PPC64,     { RS } },
2653 { "mtear",   XSPR(31,467,282), XSPR_MASK,    PPC,       { RS } },
2654 { "mttbl",   XSPR(31,467,284), XSPR_MASK,    PPC,       { RS } },
2655 { "mttbu",   XSPR(31,467,285), XSPR_MASK,    PPC,       { RS } },
2656 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
2657 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
2658 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
2659 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC,       { SPRBAT, RS } },
2660 { "mtzpr",   XSPR(31,467,944), XSPR_MASK, PPC403,       { RT } },
2661 { "mtpid",   XSPR(31,467,945), XSPR_MASK, PPC403,       { RT } },
2662 { "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403,       { RT } },
2663 { "mtesr",   XSPR(31,467,980), XSPR_MASK, PPC403,       { RT } },
2664 { "mtevpr",  XSPR(31,467,982), XSPR_MASK, PPC403,       { RT } },
2665 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403,       { RT } },
2666 { "mttsr",   XSPR(31,467,984), XSPR_MASK, PPC403,       { RT } },
2667 { "mttcr",   XSPR(31,467,986), XSPR_MASK, PPC403,       { RT } },
2668 { "mtpit",   XSPR(31,467,987), XSPR_MASK, PPC403,       { RT } },
2669 { "mttbhi",  XSPR(31,467,988), XSPR_MASK, PPC403,       { RT } },
2670 { "mttblo",  XSPR(31,467,989), XSPR_MASK, PPC403,       { RT } },
2671 { "mtsrr2",  XSPR(31,467,990), XSPR_MASK, PPC403,       { RT } },
2672 { "mtsrr3",  XSPR(31,467,991), XSPR_MASK, PPC403,       { RT } },
2673 { "mtdbsr",  XSPR(31,467,1008), XSPR_MASK, PPC403,      { RT } },
2674 { "mtiac1",  XSPR(31,467,1012), XSPR_MASK, PPC403,      { RT } },
2675 { "mtiac2",  XSPR(31,467,1013), XSPR_MASK, PPC403,      { RT } },
2676 { "mtdac1",  XSPR(31,467,1014), XSPR_MASK, PPC403,      { RT } },
2677 { "mtdac2",  XSPR(31,467,1015), XSPR_MASK, PPC403,      { RT } },
2678 { "mtdccr",  XSPR(31,467,1018), XSPR_MASK, PPC403,      { RT } },
2679 { "mticcr",  XSPR(31,467,1019), XSPR_MASK, PPC403,      { RT } },
2680 { "mtpbl1",  XSPR(31,467,1020), XSPR_MASK, PPC403,      { RT } },
2681 { "mtpbu1",  XSPR(31,467,1021), XSPR_MASK, PPC403,      { RT } },
2682 { "mtpbl2",  XSPR(31,467,1022), XSPR_MASK, PPC403,      { RT } },
2683 { "mtpbu2",  XSPR(31,467,1023), XSPR_MASK, PPC403,      { RT } },
2684 { "mtspr",   X(31,467),        X_MASK,       COM,       { SPR, RS } },
2685
2686 { "dcbi",    X(31,470), XRT_MASK,       PPC,            { RA, RB } },
2687
2688 { "nand",    XRC(31,476,0), X_MASK,     COM,            { RA, RS, RB } },
2689 { "nand.",   XRC(31,476,1), X_MASK,     COM,            { RA, RS, RB } },
2690
2691 { "dcread",  X(31,486), XRT_MASK,       PPC403,         { RA, RB } },
2692
2693 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,           { RT, RA } },
2694 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,           { RT, RA } },
2695 { "nabso",   XO(31,488,1,0), XORB_MASK, M601,           { RT, RA } },
2696 { "nabso.",  XO(31,488,1,1), XORB_MASK, M601,           { RT, RA } },
2697
2698 { "divd",    XO(31,489,0,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2699 { "divd.",   XO(31,489,0,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2700 { "divdo",   XO(31,489,1,0), XO_MASK,   PPC64,          { RT, RA, RB } },
2701 { "divdo.",  XO(31,489,1,1), XO_MASK,   PPC64,          { RT, RA, RB } },
2702
2703 { "divw",    XO(31,491,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
2704 { "divw.",   XO(31,491,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
2705 { "divwo",   XO(31,491,1,0), XO_MASK,   PPC,            { RT, RA, RB } },
2706 { "divwo.",  XO(31,491,1,1), XO_MASK,   PPC,            { RT, RA, RB } },
2707
2708 { "slbia",   X(31,498), 0xffffffff,     PPC64,          { 0 } },
2709
2710 { "cli",     X(31,502), XRB_MASK,       POWER,          { RT, RA } },
2711
2712 { "mcrxr",   X(31,512), XRARB_MASK|(3<<21), COM,        { BF } },
2713
2714 { "clcs",    X(31,531), XRB_MASK,       M601,           { RT, RA } },
2715
2716 { "lswx",    X(31,533), X_MASK,         PPCCOM,         { RT, RA, RB } },
2717 { "lsx",     X(31,533), X_MASK,         PWRCOM,         { RT, RA, RB } },
2718
2719 { "lwbrx",   X(31,534), X_MASK,         PPCCOM,         { RT, RA, RB } },
2720 { "lbrx",    X(31,534), X_MASK,         PWRCOM,         { RT, RA, RB } },
2721
2722 { "lfsx",    X(31,535), X_MASK,         COM,            { FRT, RA, RB } },
2723
2724 { "srw",     XRC(31,536,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
2725 { "sr",      XRC(31,536,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
2726 { "srw.",    XRC(31,536,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
2727 { "sr.",     XRC(31,536,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
2728
2729 { "rrib",    XRC(31,537,0), X_MASK,     M601,           { RA, RS, RB } },
2730 { "rrib.",   XRC(31,537,1), X_MASK,     M601,           { RA, RS, RB } },
2731
2732 { "srd",     XRC(31,539,0), X_MASK,     PPC64,          { RA, RS, RB } },
2733 { "srd.",    XRC(31,539,1), X_MASK,     PPC64,          { RA, RS, RB } },
2734
2735 { "maskir",  XRC(31,541,0), X_MASK,     M601,           { RA, RS, RB } },
2736 { "maskir.", XRC(31,541,1), X_MASK,     M601,           { RA, RS, RB } },
2737
2738 { "tlbsync", X(31,566), 0xffffffff,     PPC,            { 0 } },
2739
2740 { "lfsux",   X(31,567), X_MASK,         COM,            { FRT, RAS, RB } },
2741
2742 { "mfsr",    X(31,595), XRB_MASK|(1<<20), COM32,        { RT, SR } },
2743
2744 { "lswi",    X(31,597), X_MASK,         PPCCOM,         { RT, RA, NB } },
2745 { "lsi",     X(31,597), X_MASK,         PWRCOM,         { RT, RA, NB } },
2746
2747 { "sync",    X(31,598), 0xffffffff,     PPCCOM,         { 0 } },
2748 { "dcs",     X(31,598), 0xffffffff,     PWRCOM,         { 0 } },
2749
2750 { "lfdx",    X(31,599), X_MASK,         COM,            { FRT, RA, RB } },
2751
2752 { "mfsri",   X(31,627), X_MASK,         PWRCOM,         { RT, RA, RB } },
2753
2754 { "dclst",   X(31,630), XRB_MASK,       PWRCOM,         { RS, RA } },
2755
2756 { "lfdux",   X(31,631), X_MASK,         COM,            { FRT, RAS, RB } },
2757
2758 { "mfsrin",  X(31,659), XRA_MASK,       PPC32,          { RT, RB } },
2759
2760 { "stswx",   X(31,661), X_MASK,         PPCCOM,         { RS, RA, RB } },
2761 { "stsx",    X(31,661), X_MASK,         PWRCOM,         { RS, RA, RB } },
2762
2763 { "stwbrx",  X(31,662), X_MASK,         PPCCOM,         { RS, RA, RB } },
2764 { "stbrx",   X(31,662), X_MASK,         PWRCOM,         { RS, RA, RB } },
2765
2766 { "stfsx",   X(31,663), X_MASK,         COM,            { FRS, RA, RB } },
2767
2768 { "srq",     XRC(31,664,0), X_MASK,     M601,           { RA, RS, RB } },
2769 { "srq.",    XRC(31,664,1), X_MASK,     M601,           { RA, RS, RB } },
2770
2771 { "sre",     XRC(31,665,0), X_MASK,     M601,           { RA, RS, RB } },
2772 { "sre.",    XRC(31,665,1), X_MASK,     M601,           { RA, RS, RB } },
2773
2774 { "stfsux",  X(31,695), X_MASK,         COM,            { FRS, RAS, RB } },
2775
2776 { "sriq",    XRC(31,696,0), X_MASK,     M601,           { RA, RS, SH } },
2777 { "sriq.",   XRC(31,696,1), X_MASK,     M601,           { RA, RS, SH } },
2778
2779 { "stswi",   X(31,725), X_MASK,         PPCCOM,         { RS, RA, NB } },
2780 { "stsi",    X(31,725), X_MASK,         PWRCOM,         { RS, RA, NB } },
2781
2782 { "stfdx",   X(31,727), X_MASK,         COM,            { FRS, RA, RB } },
2783
2784 { "srlq",    XRC(31,728,0), X_MASK,     M601,           { RA, RS, RB } },
2785 { "srlq.",   XRC(31,728,1), X_MASK,     M601,           { RA, RS, RB } },
2786
2787 { "sreq",    XRC(31,729,0), X_MASK,     M601,           { RA, RS, RB } },
2788 { "sreq.",   XRC(31,729,1), X_MASK,     M601,           { RA, RS, RB } },
2789
2790 { "stfdux",  X(31,759), X_MASK,         COM,            { FRS, RAS, RB } },
2791
2792 { "srliq",   XRC(31,760,0), X_MASK,     M601,           { RA, RS, SH } },
2793 { "srliq.",  XRC(31,760,1), X_MASK,     M601,           { RA, RS, SH } },
2794
2795 { "lhbrx",   X(31,790), X_MASK,         COM,            { RT, RA, RB } },
2796
2797 { "sraw",    XRC(31,792,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
2798 { "sra",     XRC(31,792,0), X_MASK,     PWRCOM,         { RA, RS, RB } },
2799 { "sraw.",   XRC(31,792,1), X_MASK,     PPCCOM,         { RA, RS, RB } },
2800 { "sra.",    XRC(31,792,1), X_MASK,     PWRCOM,         { RA, RS, RB } },
2801
2802 { "srad",    XRC(31,794,0), X_MASK,     PPC64,          { RA, RS, RB } },
2803 { "srad.",   XRC(31,794,1), X_MASK,     PPC64,          { RA, RS, RB } },
2804
2805 { "rac",     X(31,818), X_MASK,         PWRCOM,         { RT, RA, RB } },
2806
2807 { "srawi",   XRC(31,824,0), X_MASK,     PPCCOM,         { RA, RS, SH } },
2808 { "srai",    XRC(31,824,0), X_MASK,     PWRCOM,         { RA, RS, SH } },
2809 { "srawi.",  XRC(31,824,1), X_MASK,     PPCCOM,         { RA, RS, SH } },
2810 { "srai.",   XRC(31,824,1), X_MASK,     PWRCOM,         { RA, RS, SH } },
2811
2812 { "eieio",   X(31,854), 0xffffffff,     PPC,            { 0 } },
2813
2814 { "tlbsx",   XRC(31,914,0), X_MASK, PPC403,     { RT, RA, RB } },
2815 { "tlbsx.",  XRC(31,914,1), X_MASK, PPC403,     { RT, RA, RB } },
2816
2817 { "sthbrx",  X(31,918), X_MASK,         COM,            { RS, RA, RB } },
2818
2819 { "sraq",    XRC(31,920,0), X_MASK,     M601,           { RA, RS, RB } },
2820 { "sraq.",   XRC(31,920,1), X_MASK,     M601,           { RA, RS, RB } },
2821
2822 { "srea",    XRC(31,921,0), X_MASK,     M601,           { RA, RS, RB } },
2823 { "srea.",   XRC(31,921,1), X_MASK,     M601,           { RA, RS, RB } },
2824
2825 { "extsh",   XRC(31,922,0), XRB_MASK,   PPCCOM,         { RA, RS } },
2826 { "exts",    XRC(31,922,0), XRB_MASK,   PWRCOM,         { RA, RS } },
2827 { "extsh.",  XRC(31,922,1), XRB_MASK,   PPCCOM,         { RA, RS } },
2828 { "exts.",   XRC(31,922,1), XRB_MASK,   PWRCOM,         { RA, RS } },
2829
2830 { "tlbre",   X(31,946), X_MASK,         PPC403,         { RT, RA, SH } },
2831
2832 { "sraiq",   XRC(31,952,0), X_MASK,     M601,           { RA, RS, SH } },
2833 { "sraiq.",  XRC(31,952,1), X_MASK,     M601,           { RA, RS, SH } },
2834
2835 { "extsb",   XRC(31,954,0), XRB_MASK,   PPC,            { RA, RS} },
2836 { "extsb.",  XRC(31,954,1), XRB_MASK,   PPC,            { RA, RS} },
2837
2838 { "iccci",   X(31,966), XRT_MASK,       PPC,            { RA, RB } },
2839
2840 { "tlbld",   X(31,978), XRTRA_MASK,     PPC,            { RB } },
2841 { "tlbwe",   X(31,978), X_MASK,         PPC403,         { RS, RA, SH } },
2842
2843 { "icbi",    X(31,982), XRT_MASK,       PPC,            { RA, RB } },
2844
2845 { "stfiwx",  X(31,983), X_MASK,         PPC,            { FRS, RA, RB } },
2846
2847 { "extsw",   XRC(31,986,0), XRB_MASK,   PPC,            { RA, RS } },
2848 { "extsw.",  XRC(31,986,1), XRB_MASK,   PPC,            { RA, RS } },
2849
2850 { "icread",  X(31,998), XRT_MASK,       PPC403,         { RA, RB } },
2851
2852 { "tlbli",   X(31,1010), XRTRA_MASK,    PPC,            { RB } },
2853
2854 { "dcbz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
2855 { "dclz",    X(31,1014), XRT_MASK,      PPC,            { RA, RB } },
2856
2857 { "lwz",     OP(32),    OP_MASK,        PPCCOM,         { RT, D, RA } },
2858 { "l",       OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA } },
2859
2860 { "lwzu",    OP(33),    OP_MASK,        PPCCOM,         { RT, D, RAL } },
2861 { "lu",      OP(33),    OP_MASK,        PWRCOM,         { RT, D, RA } },
2862
2863 { "lbz",     OP(34),    OP_MASK,        COM,            { RT, D, RA } },
2864
2865 { "lbzu",    OP(35),    OP_MASK,        COM,            { RT, D, RAL } },
2866
2867 { "stw",     OP(36),    OP_MASK,        PPCCOM,         { RS, D, RA } },
2868 { "st",      OP(36),    OP_MASK,        PWRCOM,         { RS, D, RA } },
2869
2870 { "stwu",    OP(37),    OP_MASK,        PPCCOM,         { RS, D, RAS } },
2871 { "stu",     OP(37),    OP_MASK,        PWRCOM,         { RS, D, RA } },
2872
2873 { "stb",     OP(38),    OP_MASK,        COM,            { RS, D, RA } },
2874
2875 { "stbu",    OP(39),    OP_MASK,        COM,            { RS, D, RAS } },
2876
2877 { "lhz",     OP(40),    OP_MASK,        COM,            { RT, D, RA } },
2878
2879 { "lhzu",    OP(41),    OP_MASK,        COM,            { RT, D, RAL } },
2880
2881 { "lha",     OP(42),    OP_MASK,        COM,            { RT, D, RA } },
2882
2883 { "lhau",    OP(43),    OP_MASK,        COM,            { RT, D, RAL } },
2884
2885 { "sth",     OP(44),    OP_MASK,        COM,            { RS, D, RA } },
2886
2887 { "sthu",    OP(45),    OP_MASK,        COM,            { RS, D, RAS } },
2888
2889 { "lmw",     OP(46),    OP_MASK,        PPCCOM,         { RT, D, RAM } },
2890 { "lm",      OP(46),    OP_MASK,        PWRCOM,         { RT, D, RA } },
2891
2892 { "stmw",    OP(47),    OP_MASK,        PPCCOM,         { RS, D, RA } },
2893 { "stm",     OP(47),    OP_MASK,        PWRCOM,         { RS, D, RA } },
2894
2895 { "lfs",     OP(48),    OP_MASK,        COM,            { FRT, D, RA } },
2896
2897 { "lfsu",    OP(49),    OP_MASK,        COM,            { FRT, D, RAS } },
2898
2899 { "lfd",     OP(50),    OP_MASK,        COM,            { FRT, D, RA } },
2900
2901 { "lfdu",    OP(51),    OP_MASK,        COM,            { FRT, D, RAS } },
2902
2903 { "stfs",    OP(52),    OP_MASK,        COM,            { FRS, D, RA } },
2904
2905 { "stfsu",   OP(53),    OP_MASK,        COM,            { FRS, D, RAS } },
2906
2907 { "stfd",    OP(54),    OP_MASK,        COM,            { FRS, D, RA } },
2908
2909 { "stfdu",   OP(55),    OP_MASK,        COM,            { FRS, D, RAS } },
2910
2911 { "lfq",     OP(56),    OP_MASK,        POWER2,         { FRT, D, RA } },
2912
2913 { "lfqu",    OP(57),    OP_MASK,        POWER2,         { FRT, D, RA } },
2914
2915 { "ld",      DSO(58,0), DS_MASK,        PPC64,          { RT, DS, RA } },
2916
2917 { "ldu",     DSO(58,1), DS_MASK,        PPC64,          { RT, DS, RAL } },
2918
2919 { "lwa",     DSO(58,2), DS_MASK,        PPC64,          { RT, DS, RA } },
2920
2921 { "fdivs",   A(59,18,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2922 { "fdivs.",  A(59,18,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2923
2924 { "fsubs",   A(59,20,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2925 { "fsubs.",  A(59,20,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2926
2927 { "fadds",   A(59,21,0), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2928 { "fadds.",  A(59,21,1), AFRC_MASK,     PPC,            { FRT, FRA, FRB } },
2929
2930 { "fsqrts",  A(59,22,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
2931 { "fsqrts.", A(59,22,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
2932
2933 { "fres",    A(59,24,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
2934 { "fres.",   A(59,24,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
2935
2936 { "fmuls",   A(59,25,0), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
2937 { "fmuls.",  A(59,25,1), AFRB_MASK,     PPC,            { FRT, FRA, FRC } },
2938
2939 { "fmsubs",  A(59,28,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2940 { "fmsubs.", A(59,28,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2941
2942 { "fmadds",  A(59,29,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2943 { "fmadds.", A(59,29,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2944
2945 { "fnmsubs", A(59,30,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2946 { "fnmsubs.",A(59,30,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2947
2948 { "fnmadds", A(59,31,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2949 { "fnmadds.",A(59,31,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2950
2951 { "stfq",    OP(60),    OP_MASK,        POWER2,         { FRS, D, RA } },
2952
2953 { "stfqu",   OP(61),    OP_MASK,        POWER2,         { FRS, D, RA } },
2954
2955 { "std",     DSO(62,0), DS_MASK,        PPC64,          { RS, DS, RA } },
2956
2957 { "stdu",    DSO(62,1), DS_MASK,        PPC64,          { RS, DS, RAS } },
2958
2959 { "fcmpu",   X(63,0),   X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
2960
2961 { "frsp",    XRC(63,12,0), XRA_MASK,    COM,            { FRT, FRB } },
2962 { "frsp.",   XRC(63,12,1), XRA_MASK,    COM,            { FRT, FRB } },
2963
2964 { "fctiw",   XRC(63,14,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
2965 { "fcir",    XRC(63,14,0), XRA_MASK,    POWER2,         { FRT, FRB } },
2966 { "fctiw.",  XRC(63,14,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
2967 { "fcir.",   XRC(63,14,1), XRA_MASK,    POWER2,         { FRT, FRB } },
2968
2969 { "fctiwz",  XRC(63,15,0), XRA_MASK,    PPCCOM,         { FRT, FRB } },
2970 { "fcirz",   XRC(63,15,0), XRA_MASK,    POWER2,         { FRT, FRB } },
2971 { "fctiwz.", XRC(63,15,1), XRA_MASK,    PPCCOM,         { FRT, FRB } },
2972 { "fcirz.",  XRC(63,15,1), XRA_MASK,    POWER2,         { FRT, FRB } },
2973
2974 { "fdiv",    A(63,18,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
2975 { "fd",      A(63,18,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
2976 { "fdiv.",   A(63,18,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
2977 { "fd.",     A(63,18,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
2978
2979 { "fsub",    A(63,20,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
2980 { "fs",      A(63,20,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
2981 { "fsub.",   A(63,20,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
2982 { "fs.",     A(63,20,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
2983
2984 { "fadd",    A(63,21,0), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
2985 { "fa",      A(63,21,0), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
2986 { "fadd.",   A(63,21,1), AFRC_MASK,     PPCCOM,         { FRT, FRA, FRB } },
2987 { "fa.",     A(63,21,1), AFRC_MASK,     PWRCOM,         { FRT, FRA, FRB } },
2988
2989 { "fsqrt",   A(63,22,0), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
2990 { "fsqrt.",  A(63,22,1), AFRAFRC_MASK,  PPCPWR2,        { FRT, FRB } },
2991
2992 { "fsel",    A(63,23,0), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2993 { "fsel.",   A(63,23,1), A_MASK,        PPC,            { FRT,FRA,FRC,FRB } },
2994
2995 { "fmul",    A(63,25,0), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
2996 { "fm",      A(63,25,0), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
2997 { "fmul.",   A(63,25,1), AFRB_MASK,     PPCCOM,         { FRT, FRA, FRC } },
2998 { "fm.",     A(63,25,1), AFRB_MASK,     PWRCOM,         { FRT, FRA, FRC } },
2999
3000 { "frsqrte", A(63,26,0), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3001 { "frsqrte.",A(63,26,1), AFRAFRC_MASK,  PPC,            { FRT, FRB } },
3002
3003 { "fmsub",   A(63,28,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3004 { "fms",     A(63,28,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3005 { "fmsub.",  A(63,28,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3006 { "fms.",    A(63,28,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3007
3008 { "fmadd",   A(63,29,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3009 { "fma",     A(63,29,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3010 { "fmadd.",  A(63,29,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3011 { "fma.",    A(63,29,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3012
3013 { "fnmsub",  A(63,30,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3014 { "fnms",    A(63,30,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3015 { "fnmsub.", A(63,30,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3016 { "fnms.",   A(63,30,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3017
3018 { "fnmadd",  A(63,31,0), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3019 { "fnma",    A(63,31,0), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3020 { "fnmadd.", A(63,31,1), A_MASK,        PPCCOM,         { FRT,FRA,FRC,FRB } },
3021 { "fnma.",   A(63,31,1), A_MASK,        PWRCOM,         { FRT,FRA,FRC,FRB } },
3022
3023 { "fcmpo",   X(63,32),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
3024
3025 { "mtfsb1",  XRC(63,38,0), XRARB_MASK,  COM,            { BT } },
3026 { "mtfsb1.", XRC(63,38,1), XRARB_MASK,  COM,            { BT } },
3027
3028 { "fneg",    XRC(63,40,0), XRA_MASK,    COM,            { FRT, FRB } },
3029 { "fneg.",   XRC(63,40,1), XRA_MASK,    COM,            { FRT, FRB } },
3030
3031 { "mcrfs",   X(63,64),  XRB_MASK|(3<<21)|(3<<16), COM,  { BF, BFA } },
3032
3033 { "mtfsb0",  XRC(63,70,0), XRARB_MASK,  COM,            { BT } },
3034 { "mtfsb0.", XRC(63,70,1), XRARB_MASK,  COM,            { BT } },
3035
3036 { "fmr",     XRC(63,72,0), XRA_MASK,    COM,            { FRT, FRB } },
3037 { "fmr.",    XRC(63,72,1), XRA_MASK,    COM,            { FRT, FRB } },
3038
3039 { "mtfsfi",  XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3040 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3041
3042 { "fnabs",   XRC(63,136,0), XRA_MASK,   COM,            { FRT, FRB } },
3043 { "fnabs.",  XRC(63,136,1), XRA_MASK,   COM,            { FRT, FRB } },
3044
3045 { "fabs",    XRC(63,264,0), XRA_MASK,   COM,            { FRT, FRB } },
3046 { "fabs.",   XRC(63,264,1), XRA_MASK,   COM,            { FRT, FRB } },
3047
3048 { "mffs",    XRC(63,583,0), XRARB_MASK, COM,            { FRT } },
3049 { "mffs.",   XRC(63,583,1), XRARB_MASK, COM,            { FRT } },
3050
3051 { "mtfsf",   XFL(63,711,0), XFL_MASK,   COM,            { FLM, FRB } },
3052 { "mtfsf.",  XFL(63,711,1), XFL_MASK,   COM,            { FLM, FRB } },
3053
3054 { "fctid",   XRC(63,814,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3055 { "fctid.",  XRC(63,814,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3056
3057 { "fctidz",  XRC(63,815,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3058 { "fctidz.", XRC(63,815,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3059
3060 { "fcfid",   XRC(63,846,0), XRA_MASK,   PPC64,          { FRT, FRB } },
3061 { "fcfid.",  XRC(63,846,1), XRA_MASK,   PPC64,          { FRT, FRB } },
3062
3063 };
3064
3065 const int powerpc_num_opcodes =
3066   sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
3067 \f
3068 /* The macro table.  This is only used by the assembler.  */
3069
3070 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
3071    when x=0; 32-x when x is between 1 and 31; are negative if x is
3072    negative; and are 32 or more otherwise.  This is what you want
3073    when, for instance, you are emulating a right shift by a
3074    rotate-left-and-mask, because the underlying instructions support
3075    shifts of size 0 but not shifts of size 32.  By comparison, when
3076    extracting x bits from some word you want to use just 32-x, because
3077    the underlying instructions don't support extracting 0 bits but do
3078    support extracting the whole word (32 bits in this case).  */
3079
3080 const struct powerpc_macro powerpc_macros[] = {
3081 { "extldi",  4,   PPC64,        "rldicr %0,%1,%3,(%2)-1" },
3082 { "extldi.", 4,   PPC64,        "rldicr. %0,%1,%3,(%2)-1" },
3083 { "extrdi",  4,   PPC64,        "rldicl %0,%1,(%2)+(%3),64-(%2)" },
3084 { "extrdi.", 4,   PPC64,        "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
3085 { "insrdi",  4,   PPC64,        "rldimi %0,%1,64-((%2)+(%3)),%3" },
3086 { "insrdi.", 4,   PPC64,        "rldimi. %0,%1,64-((%2)+(%3)),%3" },
3087 { "rotrdi",  3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
3088 { "rotrdi.", 3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
3089 { "sldi",    3,   PPC64,        "rldicr %0,%1,%2,63-(%2)" },
3090 { "sldi.",   3,   PPC64,        "rldicr. %0,%1,%2,63-(%2)" },
3091 { "srdi",    3,   PPC64,        "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
3092 { "srdi.",   3,   PPC64,        "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
3093 { "clrrdi",  3,   PPC64,        "rldicr %0,%1,0,63-(%2)" },
3094 { "clrrdi.", 3,   PPC64,        "rldicr. %0,%1,0,63-(%2)" },
3095 { "clrlsldi",4,   PPC64,        "rldic %0,%1,%3,(%2)-(%3)" },
3096 { "clrlsldi.",4,  PPC64,        "rldic. %0,%1,%3,(%2)-(%3)" },
3097
3098 { "extlwi",  4,   PPCCOM,       "rlwinm %0,%1,%3,0,(%2)-1" },
3099 { "extlwi.", 4,   PPCCOM,       "rlwinm. %0,%1,%3,0,(%2)-1" },
3100 { "extrwi",  4,   PPCCOM,       "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
3101 { "extrwi.", 4,   PPCCOM,       "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
3102 { "inslwi",  4,   PPCCOM,       "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
3103 { "inslwi.", 4,   PPCCOM,       "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
3104 { "insrwi",  4,   PPCCOM,       "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
3105 { "insrwi.", 4,   PPCCOM,       "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
3106 { "rotrwi",  3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3107 { "rotrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3108 { "slwi",    3,   PPCCOM,       "rlwinm %0,%1,%2,0,31-(%2)" },
3109 { "sli",     3,   PWRCOM,       "rlinm %0,%1,%2,0,31-(%2)" },
3110 { "slwi.",   3,   PPCCOM,       "rlwinm. %0,%1,%2,0,31-(%2)" },
3111 { "sli.",    3,   PWRCOM,       "rlinm. %0,%1,%2,0,31-(%2)" },
3112 { "srwi",    3,   PPCCOM,       "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3113 { "sri",     3,   PWRCOM,       "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3114 { "srwi.",   3,   PPCCOM,       "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3115 { "sri.",    3,   PWRCOM,       "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3116 { "clrrwi",  3,   PPCCOM,       "rlwinm %0,%1,0,0,31-(%2)" },
3117 { "clrrwi.", 3,   PPCCOM,       "rlwinm. %0,%1,0,0,31-(%2)" },
3118 { "clrlslwi",4,   PPCCOM,       "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
3119 { "clrlslwi.",4,  PPCCOM,       "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
3120
3121 };
3122
3123 const int powerpc_num_macros =
3124   sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);