opcodes/m32r-opinst.c

   1 /* Semantic operand instances for m32r.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include "ansidecl.h"
  27 #include "bfd.h"
  28 #include "symcat.h"
  29 #include "m32r-desc.h"
  30 #include "m32r-opc.h"
  31
  32 /* Operand references.  */
  33
  34 #define INPUT CGEN_OPINST_INPUT
  35 #define OUTPUT CGEN_OPINST_OUTPUT
  36 #define END CGEN_OPINST_END
  37 #define COND_REF CGEN_OPINST_COND_REF
  38 #define OP_ENT(op) CONCAT2 (M32R_OPERAND_,op)
  39
  40 static const CGEN_OPINST fmt_empty_ops[] = {
  41   { END }
  42 };
  43
  44 static const CGEN_OPINST fmt_add_ops[] = {
  45   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  46   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
  47   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  48   { END }
  49 };
  50
  51 static const CGEN_OPINST fmt_add3_ops[] = {
  52   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
  53   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
  54   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  55   { END }
  56 };
  57
  58 static const CGEN_OPINST fmt_and3_ops[] = {
  59   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
  60   { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
  61   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  62   { END }
  63 };
  64
  65 static const CGEN_OPINST fmt_or3_ops[] = {
  66   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
  67   { INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 },
  68   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  69   { END }
  70 };
  71
  72 static const CGEN_OPINST fmt_addi_ops[] = {
  73   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  74   { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
  75   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  76   { END }
  77 };
  78
  79 static const CGEN_OPINST fmt_addv_ops[] = {
  80   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  81   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
  82   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
  83   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  84   { END }
  85 };
  86
  87 static const CGEN_OPINST fmt_addv3_ops[] = {
  88   { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
  89   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
  90   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
  91   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  92   { END }
  93 };
  94
  95 static const CGEN_OPINST fmt_addx_ops[] = {
  96   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
  97   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
  98   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
  99   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
 100   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 101   { END }
 102 };
 103
 104 static const CGEN_OPINST fmt_bc8_ops[] = {
 105   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
 106   { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
 107   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
 108   { END }
 109 };
 110
 111 static const CGEN_OPINST fmt_bc24_ops[] = {
 112   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
 113   { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
 114   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
 115   { END }
 116 };
 117
 118 static const CGEN_OPINST fmt_beq_ops[] = {
 119   { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
 120   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
 121   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
 122   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
 123   { END }
 124 };
 125
 126 static const CGEN_OPINST fmt_beqz_ops[] = {
 127   { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
 128   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
 129   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
 130   { END }
 131 };
 132
 133 static const CGEN_OPINST fmt_bl8_ops[] = {
 134   { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
 135   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
 136   { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
 137   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
 138   { END }
 139 };
 140
 141 static const CGEN_OPINST fmt_bl24_ops[] = {
 142   { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
 143   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
 144   { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
 145   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
 146   { END }
 147 };
 148
 149 static const CGEN_OPINST fmt_bra8_ops[] = {
 150   { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
 151   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
 152   { END }
 153 };
 154
 155 static const CGEN_OPINST fmt_bra24_ops[] = {
 156   { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
 157   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
 158   { END }
 159 };
 160
 161 static const CGEN_OPINST fmt_cmp_ops[] = {
 162   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
 163   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
 164   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
 165   { END }
 166 };
 167
 168 static const CGEN_OPINST fmt_cmpi_ops[] = {
 169   { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
 170   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
 171   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
 172   { END }
 173 };
 174
 175 static const CGEN_OPINST fmt_div_ops[] = {
 176   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
 177   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
 178   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
 179   { END }
 180 };
 181
 182 static const CGEN_OPINST fmt_jl_ops[] = {
 183   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
 184   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
 185   { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
 186   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
 187   { END }
 188 };
 189
 190 static const CGEN_OPINST fmt_jmp_ops[] = {
 191   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
 192   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
 193   { END }
 194 };
 195
 196 static const CGEN_OPINST fmt_ld_ops[] = {
 197   { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
 198   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
 199   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 200   { END }
 201 };
 202
 203 static const CGEN_OPINST fmt_ld_d_ops[] = {
 204   { INPUT, "h_memory_add__VM_sr_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
 205   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
 206   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
 207   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 208   { END }
 209 };
 210
 211 static const CGEN_OPINST fmt_ldb_ops[] = {
 212   { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
 213   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
 214   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 215   { END }
 216 };
 217
 218 static const CGEN_OPINST fmt_ldb_d_ops[] = {
 219   { INPUT, "h_memory_add__VM_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
 220   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
 221   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
 222   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 223   { END }
 224 };
 225
 226 static const CGEN_OPINST fmt_ldh_ops[] = {
 227   { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
 228   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
 229   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 230   { END }
 231 };
 232
 233 static const CGEN_OPINST fmt_ldh_d_ops[] = {
 234   { INPUT, "h_memory_add__VM_sr_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
 235   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
 236   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
 237   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 238   { END }
 239 };
 240
 241 static const CGEN_OPINST fmt_ld_plus_ops[] = {
 242   { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
 243   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
 244   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 245   { OUTPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
 246   { END }
 247 };
 248
 249 static const CGEN_OPINST fmt_ld24_ops[] = {
 250   { INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 },
 251   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 252   { END }
 253 };
 254
 255 static const CGEN_OPINST fmt_ldi8_ops[] = {
 256   { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
 257   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 258   { END }
 259 };
 260
 261 static const CGEN_OPINST fmt_ldi16_ops[] = {
 262   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
 263   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 264   { END }
 265 };
 266
 267 static const CGEN_OPINST fmt_lock_ops[] = {
 268   { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
 269   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
 270   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 271   { OUTPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
 272   { END }
 273 };
 274
 275 static const CGEN_OPINST fmt_machi_ops[] = {
 276   { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
 277   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
 278   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
 279   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
 280   { END }
 281 };
 282
 283 static const CGEN_OPINST fmt_mulhi_ops[] = {
 284   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
 285   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
 286   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
 287   { END }
 288 };
 289
 290 static const CGEN_OPINST fmt_mv_ops[] = {
 291   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
 292   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 293   { END }
 294 };
 295
 296 static const CGEN_OPINST fmt_mvfachi_ops[] = {
 297   { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
 298   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 299   { END }
 300 };
 301
 302 static const CGEN_OPINST fmt_mvfc_ops[] = {
 303   { INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 },
 304   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 305   { END }
 306 };
 307
 308 static const CGEN_OPINST fmt_mvtachi_ops[] = {
 309   { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
 310   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
 311   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
 312   { END }
 313 };
 314
 315 static const CGEN_OPINST fmt_mvtc_ops[] = {
 316   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
 317   { OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 },
 318   { END }
 319 };
 320
 321 static const CGEN_OPINST fmt_nop_ops[] = {
 322   { END }
 323 };
 324
 325 static const CGEN_OPINST fmt_rac_ops[] = {
 326   { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
 327   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
 328   { END }
 329 };
 330
 331 static const CGEN_OPINST fmt_rte_ops[] = {
 332   { INPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
 333   { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
 334   { INPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
 335   { INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
 336   { OUTPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
 337   { OUTPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
 338   { OUTPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
 339   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
 340   { END }
 341 };
 342
 343 static const CGEN_OPINST fmt_seth_ops[] = {
 344   { INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 },
 345   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 346   { END }
 347 };
 348
 349 static const CGEN_OPINST fmt_sll3_ops[] = {
 350   { INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 },
 351   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
 352   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 353   { END }
 354 };
 355
 356 static const CGEN_OPINST fmt_slli_ops[] = {
 357   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 358   { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
 359   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
 360   { END }
 361 };
 362
 363 static const CGEN_OPINST fmt_st_ops[] = {
 364   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
 365   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
 366   { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
 367   { END }
 368 };
 369
 370 static const CGEN_OPINST fmt_st_d_ops[] = {
 371   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
 372   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
 373   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
 374   { OUTPUT, "h_memory_add__VM_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
 375   { END }
 376 };
 377
 378 static const CGEN_OPINST fmt_stb_ops[] = {
 379   { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
 380   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
 381   { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
 382   { END }
 383 };
 384
 385 static const CGEN_OPINST fmt_stb_d_ops[] = {
 386   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
 387   { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
 388   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
 389   { OUTPUT, "h_memory_add__VM_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
 390   { END }
 391 };
 392
 393 static const CGEN_OPINST fmt_sth_ops[] = {
 394   { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
 395   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
 396   { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
 397   { END }
 398 };
 399
 400 static const CGEN_OPINST fmt_sth_d_ops[] = {
 401   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
 402   { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
 403   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
 404   { OUTPUT, "h_memory_add__VM_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
 405   { END }
 406 };
 407
 408 static const CGEN_OPINST fmt_st_plus_ops[] = {
 409   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
 410   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
 411   { OUTPUT, "h_memory_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
 412   { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
 413   { END }
 414 };
 415
 416 static const CGEN_OPINST fmt_trap_ops[] = {
 417   { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
 418   { INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
 419   { INPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
 420   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
 421   { INPUT, "uimm4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM4), 0, 0 },
 422   { OUTPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
 423   { OUTPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
 424   { OUTPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
 425   { OUTPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
 426   { OUTPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
 427   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_SI, 0, 0, 0 },
 428   { END }
 429 };
 430
 431 static const CGEN_OPINST fmt_unlock_ops[] = {
 432   { INPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
 433   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, COND_REF },
 434   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF },
 435   { OUTPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
 436   { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF },
 437   { END }
 438 };
 439
 440 #undef INPUT
 441 #undef OUTPUT
 442 #undef END
 443 #undef COND_REF
 444 #undef OP_ENT
 445
 446 /* Operand instance lookup table.  */
 447
 448 static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
 449   0,
 450   & fmt_add_ops[0],
 451   & fmt_add3_ops[0],
 452   & fmt_add_ops[0],
 453   & fmt_and3_ops[0],
 454   & fmt_add_ops[0],
 455   & fmt_or3_ops[0],
 456   & fmt_add_ops[0],
 457   & fmt_and3_ops[0],
 458   & fmt_addi_ops[0],
 459   & fmt_addv_ops[0],
 460   & fmt_addv3_ops[0],
 461   & fmt_addx_ops[0],
 462   & fmt_bc8_ops[0],
 463   & fmt_bc24_ops[0],
 464   & fmt_beq_ops[0],
 465   & fmt_beqz_ops[0],
 466   & fmt_beqz_ops[0],
 467   & fmt_beqz_ops[0],
 468   & fmt_beqz_ops[0],
 469   & fmt_beqz_ops[0],
 470   & fmt_beqz_ops[0],
 471   & fmt_bl8_ops[0],
 472   & fmt_bl24_ops[0],
 473   & fmt_bc8_ops[0],
 474   & fmt_bc24_ops[0],
 475   & fmt_beq_ops[0],
 476   & fmt_bra8_ops[0],
 477   & fmt_bra24_ops[0],
 478   & fmt_cmp_ops[0],
 479   & fmt_cmpi_ops[0],
 480   & fmt_cmp_ops[0],
 481   & fmt_cmpi_ops[0],
 482   & fmt_div_ops[0],
 483   & fmt_div_ops[0],
 484   & fmt_div_ops[0],
 485   & fmt_div_ops[0],
 486   & fmt_jl_ops[0],
 487   & fmt_jmp_ops[0],
 488   & fmt_ld_ops[0],
 489   & fmt_ld_d_ops[0],
 490   & fmt_ldb_ops[0],
 491   & fmt_ldb_d_ops[0],
 492   & fmt_ldh_ops[0],
 493   & fmt_ldh_d_ops[0],
 494   & fmt_ldb_ops[0],
 495   & fmt_ldb_d_ops[0],
 496   & fmt_ldh_ops[0],
 497   & fmt_ldh_d_ops[0],
 498   & fmt_ld_plus_ops[0],
 499   & fmt_ld24_ops[0],
 500   & fmt_ldi8_ops[0],
 501   & fmt_ldi16_ops[0],
 502   & fmt_lock_ops[0],
 503   & fmt_machi_ops[0],
 504   & fmt_machi_ops[0],
 505   & fmt_machi_ops[0],
 506   & fmt_machi_ops[0],
 507   & fmt_add_ops[0],
 508   & fmt_mulhi_ops[0],
 509   & fmt_mulhi_ops[0],
 510   & fmt_mulhi_ops[0],
 511   & fmt_mulhi_ops[0],
 512   & fmt_mv_ops[0],
 513   & fmt_mvfachi_ops[0],
 514   & fmt_mvfachi_ops[0],
 515   & fmt_mvfachi_ops[0],
 516   & fmt_mvfc_ops[0],
 517   & fmt_mvtachi_ops[0],
 518   & fmt_mvtachi_ops[0],
 519   & fmt_mvtc_ops[0],
 520   & fmt_mv_ops[0],
 521   & fmt_nop_ops[0],
 522   & fmt_mv_ops[0],
 523   & fmt_rac_ops[0],
 524   & fmt_rac_ops[0],
 525   & fmt_rte_ops[0],
 526   & fmt_seth_ops[0],
 527   & fmt_add_ops[0],
 528   & fmt_sll3_ops[0],
 529   & fmt_slli_ops[0],
 530   & fmt_add_ops[0],
 531   & fmt_sll3_ops[0],
 532   & fmt_slli_ops[0],
 533   & fmt_add_ops[0],
 534   & fmt_sll3_ops[0],
 535   & fmt_slli_ops[0],
 536   & fmt_st_ops[0],
 537   & fmt_st_d_ops[0],
 538   & fmt_stb_ops[0],
 539   & fmt_stb_d_ops[0],
 540   & fmt_sth_ops[0],
 541   & fmt_sth_d_ops[0],
 542   & fmt_st_plus_ops[0],
 543   & fmt_st_plus_ops[0],
 544   & fmt_add_ops[0],
 545   & fmt_addv_ops[0],
 546   & fmt_addx_ops[0],
 547   & fmt_trap_ops[0],
 548   & fmt_unlock_ops[0],
 549 };
 550
 551 /* Function to call before using the operand instance table.  */
 552
 553 void
 554 m32r_cgen_init_opinst_table (cd)
 555      CGEN_CPU_DESC cd;
 556 {
 557   int i;
 558   const CGEN_OPINST **oi = & m32r_cgen_opinst_table[0];
 559   CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries;
 560   for (i = 0; i < MAX_INSNS; ++i)
 561     insns[i].opinst = oi[i];
 562 }