opcodes/m32r-desc.h

   1 /* CPU data header for m32r.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef M32R_CPU_H
  26 #define M32R_CPU_H
  27
  28 #define CGEN_ARCH m32r
  29
  30 /* Given symbol S, return m32r_cgen_<S>.  */
  31 #define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s)
  32
  33 /* Selected cpu families.  */
  34 #define HAVE_CPU_M32RBF
  35
  36 #define CGEN_INSN_LSB0_P 0
  37
  38 /* Maximum size of any insn (in bytes).  */
  39 #define CGEN_MAX_INSN_SIZE 4
  40
  41 #define CGEN_INT_INSN_P 1
  42
  43 /* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
  44
  45 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  46    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  47    we can't hash on everything up to the space.  */
  48 #define CGEN_MNEMONIC_OPERANDS
  49 /* Maximum number of operands any insn or macro-insn has.  */
  50 #define CGEN_MAX_INSN_OPERANDS 16
  51
  52 /* Maximum number of fields in an instruction.  */
  53 #define CGEN_MAX_IFMT_OPERANDS 7
  54
  55 /* Enums.  */
  56
  57 /* Enum declaration for insn format enums.  */
  58 typedef enum insn_op1 {
  59   OP1_0, OP1_1, OP1_2, OP1_3
  60  , OP1_4, OP1_5, OP1_6, OP1_7
  61  , OP1_8, OP1_9, OP1_10, OP1_11
  62  , OP1_12, OP1_13, OP1_14, OP1_15
  63 } INSN_OP1;
  64
  65 /* Enum declaration for op2 enums.  */
  66 typedef enum insn_op2 {
  67   OP2_0, OP2_1, OP2_2, OP2_3
  68  , OP2_4, OP2_5, OP2_6, OP2_7
  69  , OP2_8, OP2_9, OP2_10, OP2_11
  70  , OP2_12, OP2_13, OP2_14, OP2_15
  71 } INSN_OP2;
  72
  73 /* Enum declaration for .  */
  74 typedef enum gr_names {
  75   H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0
  76  , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
  77  , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
  78  , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
  79  , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
  80 } GR_NAMES;
  81
  82 /* Enum declaration for .  */
  83 typedef enum cr_names {
  84   H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
  85  , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_CR0 = 0
  86  , H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3, H_CR_CR4 = 4
  87  , H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7, H_CR_CR8 = 8
  88  , H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11, H_CR_CR12 = 12
  89  , H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
  90 } CR_NAMES;
  91
  92 /* Attributes.  */
  93
  94 /* Enum declaration for machine type selection.  */
  95 typedef enum mach_attr {
  96   MACH_BASE, MACH_M32R
  97  , MACH_MAX
  98 } MACH_ATTR;
  99
 100 /* Enum declaration for instruction set selection.  */
 101 typedef enum isa_attr {
 102   ISA_M32R, ISA_MAX
 103 } ISA_ATTR;
 104
 105 /* Number of architecture variants.  */
 106 #define MAX_ISAS  1
 107 #define MAX_MACHS ((int) MACH_MAX)
 108
 109 /* Ifield support.  */
 110
 111 extern const struct cgen_ifld m32r_cgen_ifld_table[];
 112
 113 /* Ifield attribute indices.  */
 114
 115 /* Enum declaration for cgen_ifld attrs.  */
 116 typedef enum cgen_ifld_attr {
 117   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 118  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS
 119  , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 120 } CGEN_IFLD_ATTR;
 121
 122 /* Number of non-boolean elements in cgen_ifld_attr.  */
 123 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 124
 125 /* Enum declaration for m32r ifield types.  */
 126 typedef enum ifield_type {
 127   M32R_F_NIL, M32R_F_OP1, M32R_F_OP2, M32R_F_COND
 128  , M32R_F_R1, M32R_F_R2, M32R_F_SIMM8, M32R_F_SIMM16
 129  , M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5, M32R_F_UIMM16
 130  , M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16
 131  , M32R_F_DISP24
 132  , M32R_F_MAX
 133 } IFIELD_TYPE;
 134
 135 #define MAX_IFLD ((int) M32R_F_MAX)
 136
 137 /* Hardware attribute indices.  */
 138
 139 /* Enum declaration for cgen_hw attrs.  */
 140 typedef enum cgen_hw_attr {
 141   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 142  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 143 } CGEN_HW_ATTR;
 144
 145 /* Number of non-boolean elements in cgen_hw_attr.  */
 146 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 147
 148 /* Enum declaration for m32r hardware types.  */
 149 typedef enum cgen_hw_type {
 150   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 151  , HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16
 152  , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
 153  , HW_H_COND, HW_H_PSW, HW_H_BPSW, HW_H_BBPSW
 154  , HW_H_LOCK, HW_MAX
 155 } CGEN_HW_TYPE;
 156
 157 #define MAX_HW ((int) HW_MAX)
 158
 159 /* Operand attribute indices.  */
 160
 161 /* Enum declaration for cgen_operand attrs.  */
 162 typedef enum cgen_operand_attr {
 163   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 164  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 165  , CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31
 166  , CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
 167 } CGEN_OPERAND_ATTR;
 168
 169 /* Number of non-boolean elements in cgen_operand_attr.  */
 170 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 171
 172 /* Enum declaration for m32r operand types.  */
 173 typedef enum cgen_operand_type {
 174   M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
 175  , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
 176  , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
 177  , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16
 178  , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24
 179  , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
 180 } CGEN_OPERAND_TYPE;
 181
 182 /* Number of operands types.  */
 183 #define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
 184
 185 /* Maximum number of operands referenced by any insn.  */
 186 #define MAX_OPERAND_INSTANCES 11
 187
 188 /* Insn attribute indices.  */
 189
 190 /* Enum declaration for cgen_insn attrs.  */
 191 typedef enum cgen_insn_attr {
 192   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 193  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
 194  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL
 195  , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_PIPE
 196  , CGEN_INSN_END_NBOOLS
 197 } CGEN_INSN_ATTR;
 198
 199 /* Number of non-boolean elements in cgen_insn_attr.  */
 200 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 201
 202 /* cgen.h uses things we just defined.  */
 203 #include "opcode/cgen.h"
 204
 205 /* Attributes.  */
 206 extern const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[];
 207 extern const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[];
 208 extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
 209 extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
 210
 211 /* Hardware decls.  */
 212
 213 extern CGEN_KEYWORD m32r_cgen_opval_gr_names;
 214 extern CGEN_KEYWORD m32r_cgen_opval_cr_names;
 215
 216
 217
 218
 219 #endif /* M32R_CPU_H */