opcodes/m10200-opc.c

   1 /* Assemble Matsushita MN10200 instructions.
   2    Copyright (C) 1996, 1997 Free Software Foundation, Inc.
   3
   4 This program is free software; you can redistribute it and/or modify
   5 it under the terms of the GNU General Public License as published by
   6 the Free Software Foundation; either version 2 of the License, or
   7 (at your option) any later version.
   8
   9 This program is distributed in the hope that it will be useful,
  10 but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 GNU General Public License for more details.
  13
  14 You should have received a copy of the GNU General Public License
  15 along with this program; if not, write to the Free Software
  16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  17
  18 #include "ansidecl.h"
  19 #include "opcode/mn10200.h"
  20
  21 \f
  22 const struct mn10200_operand mn10200_operands[] = {
  23 #define UNUSED  0
  24   {0, 0, 0},
  25
  26 /* dn register in the first register operand position.  */
  27 #define DN0      (UNUSED+1)
  28   {2, 0, MN10200_OPERAND_DREG},
  29
  30 /* dn register in the second register operand position.  */
  31 #define DN1      (DN0+1)
  32   {2, 2, MN10200_OPERAND_DREG},
  33
  34 /* dm register in the first register operand position.  */
  35 #define DM0      (DN1+1)
  36   {2, 0, MN10200_OPERAND_DREG},
  37
  38 /* dm register in the second register operand position.  */
  39 #define DM1      (DM0+1)
  40   {2, 2, MN10200_OPERAND_DREG},
  41
  42 /* an register in the first register operand position.  */
  43 #define AN0      (DM1+1)
  44   {2, 0, MN10200_OPERAND_AREG},
  45
  46 /* an register in the second register operand position.  */
  47 #define AN1      (AN0+1)
  48   {2, 2, MN10200_OPERAND_AREG},
  49
  50 /* am register in the first register operand position.  */
  51 #define AM0      (AN1+1)
  52   {2, 0, MN10200_OPERAND_AREG},
  53
  54 /* am register in the second register operand position.  */
  55 #define AM1      (AM0+1)
  56   {2, 2, MN10200_OPERAND_AREG},
  57
  58 /* 8 bit unsigned immediate which may promote to a 16bit
  59    unsigned immediate.  */
  60 #define IMM8    (AM1+1)
  61   {8, 0, MN10200_OPERAND_PROMOTE},
  62
  63 /* 16 bit unsigned immediate which may promote to a 32bit
  64    unsigned immediate.  */
  65 #define IMM16    (IMM8+1)
  66   {16, 0, MN10200_OPERAND_PROMOTE},
  67
  68 /* 16 bit pc-relative immediate which may promote to a 16bit
  69    pc-relative immediate.  */
  70 #define IMM16_PCREL    (IMM16+1)
  71   {16, 0, MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX | MN10200_OPERAND_SIGNED},
  72
  73 /* 16bit unsigned dispacement in a memory operation which
  74    may promote to a 32bit displacement.  */
  75 #define IMM16_MEM    (IMM16_PCREL+1)
  76   {16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_MEMADDR},
  77
  78 /* 24 immediate, low 16 bits in the main instruction
  79    word, 8 in the extension word.  */
  80
  81 #define IMM24    (IMM16_MEM+1)
  82   {24, 0, MN10200_OPERAND_EXTENDED},
  83
  84 /* 32bit pc-relative offset.  */
  85 #define IMM24_PCREL    (IMM24+1)
  86   {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_PCREL | MN10200_OPERAND_SIGNED},
  87
  88 /* 32bit memory offset.  */
  89 #define IMM24_MEM    (IMM24_PCREL+1)
  90   {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_MEMADDR},
  91
  92 /* Processor status word.  */
  93 #define PSW    (IMM24_MEM+1)
  94   {0, 0, MN10200_OPERAND_PSW},
  95
  96 /* MDR register.  */
  97 #define MDR    (PSW+1)
  98   {0, 0, MN10200_OPERAND_MDR},
  99
 100 /* Index register.  */
 101 #define DI (MDR+1)
 102   {2, 4, MN10200_OPERAND_DREG},
 103
 104 /* 8 bit signed displacement, may promote to 16bit signed dispacement.  */
 105 #define SD8    (DI+1)
 106   {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
 107
 108 /* 16 bit signed displacement, may promote to 32bit dispacement.  */
 109 #define SD16    (SD8+1)
 110   {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
 111
 112 /* 8 bit pc-relative displacement.  */
 113 #define SD8N_PCREL    (SD16+1)
 114   {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX},
 115
 116 /* 8 bit signed immediate which may promote to 16bit signed immediate.  */
 117 #define SIMM8    (SD8N_PCREL+1)
 118   {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
 119
 120 /* 16 bit signed immediate which may promote to 32bit  immediate.  */
 121 #define SIMM16    (SIMM8+1)
 122   {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
 123
 124 /* 16 bit signed immediate which may not promote.  */
 125 #define SIMM16N    (SIMM16+1)
 126   {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_NOCHECK},
 127
 128 /* Either an open paren or close paren.  */
 129 #define PAREN   (SIMM16N+1)
 130   {0, 0, MN10200_OPERAND_PAREN},
 131
 132 /* dn register that appears in the first and second register positions.  */
 133 #define DN01     (PAREN+1)
 134   {2, 0, MN10200_OPERAND_DREG | MN10200_OPERAND_REPEATED},
 135
 136 /* an register that appears in the first and second register positions.  */
 137 #define AN01     (DN01+1)
 138   {2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED},
 139 } ;
 140
 141 #define MEM(ADDR) PAREN, ADDR, PAREN
 142 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
 143 \f
 144 /* The opcode table.
 145
 146    The format of the opcode table is:
 147
 148    NAME         OPCODE          MASK            { OPERANDS }
 149
 150    NAME is the name of the instruction.
 151    OPCODE is the instruction opcode.
 152    MASK is the opcode mask; this is used to tell the disassembler
 153      which bits in the actual opcode must match OPCODE.
 154    OPERANDS is the list of operands.
 155
 156    The disassembler reads the table in order and prints the first
 157    instruction which matches, so this table is sorted to put more
 158    specific instructions before more general instructions.  It is also
 159    sorted by major opcode.  */
 160
 161 const struct mn10200_opcode mn10200_opcodes[] = {
 162 { "mov",        0x8000,         0xf000,         FMT_2, {SIMM8, DN01}},
 163 { "mov",        0x80,           0xf0,           FMT_1, {DN1, DM0}},
 164 { "mov",        0xf230,         0xfff0,         FMT_4, {DM1, AN0}},
 165 { "mov",        0xf2f0,         0xfff0,         FMT_4, {AN1, DM0}},
 166 { "mov",        0xf270,         0xfff0,         FMT_4, {AN1, AM0}},
 167 { "mov",        0xf3f0,         0xfffc,         FMT_4, {PSW, DN0}},
 168 { "mov",        0xf3d0,         0xfff3,         FMT_4, {DN1, PSW}},
 169 { "mov",        0xf3e0,         0xfffc,         FMT_4, {MDR, DN0}},
 170 { "mov",        0xf3c0,         0xfff3,         FMT_4, {DN1, MDR}},
 171 { "mov",        0x20,           0xf0,           FMT_1, {MEM(AN1), DM0}},
 172 { "mov",        0x6000,         0xf000,         FMT_2, {MEM2(SD8, AN1), DM0}},
 173 { "mov",        0xf7c00000,     0xfff00000,     FMT_6, {MEM2(SD16, AN1), DM0}},
 174 { "mov",        0xf4800000,     0xfff00000,     FMT_7, {MEM2(IMM24,AN1), DM0}},
 175 { "mov",        0xf140,         0xffc0,         FMT_4, {MEM2(DI, AN1), DM0}},
 176 { "mov",        0xc80000,       0xfc0000,       FMT_3, {MEM(IMM16_MEM), DN0}},
 177 { "mov",        0xf4c00000,     0xfffc0000,     FMT_7, {MEM(IMM24_MEM), DN0}},
 178 { "mov",        0x7000,         0xf000,         FMT_2, {MEM2(SD8,AN1), AM0}},
 179 { "mov",        0x7000,         0xf000,         FMT_2, {MEM(AN1), AM0}},
 180 { "mov",        0xf7b00000,     0xfff00000,     FMT_6, {MEM2(SD16, AN1), AM0}},
 181 { "mov",        0xf4f00000,     0xfff00000,     FMT_7, {MEM2(IMM24,AN1), AM0}},
 182 { "mov",        0xf100,         0xffc0,         FMT_4, {MEM2(DI, AN1), AM0}},
 183 { "mov",        0xf7300000,     0xfffc0000,     FMT_6, {MEM(IMM16_MEM), AN0}},
 184 { "mov",        0xf4d00000,     0xfffc0000,     FMT_7, {MEM(IMM24_MEM), AN0}},
 185 { "mov",        0x00,           0xf0,           FMT_1, {DM0, MEM(AN1)}},
 186 { "mov",        0x4000,         0xf000,         FMT_2, {DM0, MEM2(SD8, AN1)}},
 187 { "mov",        0xf7800000,     0xfff00000,     FMT_6, {DM0, MEM2(SD16, AN1)}},
 188 { "mov",        0xf4000000,     0xfff00000,     FMT_7, {DM0, MEM2(IMM24, AN1)}},
 189 { "mov",        0xf1c0,         0xffc0,         FMT_4, {DM0, MEM2(DI, AN1)}},
 190 { "mov",        0xc00000,       0xfc0000,       FMT_3, {DN0, MEM(IMM16_MEM)}},
 191 { "mov",        0xf4400000,     0xfffc0000,     FMT_7, {DN0, MEM(IMM24_MEM)}},
 192 { "mov",        0x5000,         0xf000,         FMT_2, {AM0, MEM2(SD8, AN1)}},
 193 { "mov",        0x5000,         0xf000,         FMT_2, {AM0, MEM(AN1)}},
 194 { "mov",        0xf7a00000,     0xfff00000,     FMT_6, {AM0, MEM2(SD16, AN1)}},
 195 { "mov",        0xf4100000,     0xfff00000,     FMT_7, {AM0, MEM2(IMM24,AN1)}},
 196 { "mov",        0xf180,         0xffc0,         FMT_4, {AM0, MEM2(DI, AN1)}},
 197 { "mov",        0xf7200000,     0xfffc0000,     FMT_6, {AN0, MEM(IMM16_MEM)}},
 198 { "mov",        0xf4500000,     0xfffc0000,     FMT_7, {AN0, MEM(IMM24_MEM)}},
 199 { "mov",        0xf80000,       0xfc0000,       FMT_3, {SIMM16, DN0}},
 200 { "mov",        0xf4700000,     0xfffc0000,     FMT_7, {IMM24, DN0}},
 201 { "mov",        0xdc0000,       0xfc0000,       FMT_3, {IMM16, AN0}},
 202 { "mov",        0xf4740000,     0xfffc0000,     FMT_7, {IMM24, AN0}},
 203
 204 { "movx",       0xf57000,       0xfff000,       FMT_5, {MEM2(SD8, AN1), DM0}},
 205 { "movx",       0xf7700000,     0xfff00000,     FMT_6, {MEM2(SD16, AN1), DM0}},
 206 { "movx",       0xf4b00000,     0xfff00000,     FMT_7, {MEM2(IMM24,AN1), DM0}},
 207 { "movx",       0xf55000,       0xfff000,       FMT_5, {DM0, MEM2(SD8, AN1)}},
 208 { "movx",       0xf7600000,     0xfff00000,     FMT_6, {DM0, MEM2(SD16, AN1)}},
 209 { "movx",       0xf4300000,     0xfff00000,     FMT_7, {DM0, MEM2(IMM24, AN1)}},
 210
 211 { "movb",       0xf52000,       0xfff000,       FMT_5, {MEM2(SD8, AN1), DM0}},
 212 { "movb",       0xf7d00000,     0xfff00000,     FMT_6, {MEM2(SD16, AN1), DM0}},
 213 { "movb",       0xf4a00000,     0xfff00000,     FMT_7, {MEM2(IMM24,AN1), DM0}},
 214 { "movb",       0xf040,         0xffc0,         FMT_4, {MEM2(DI, AN1), DM0}},
 215 { "movb",       0xf4c40000,     0xfffc0000,     FMT_7, {MEM(IMM24_MEM), DN0}},
 216 { "movb",       0x10,           0xf0,           FMT_1, {DM0, MEM(AN1)}},
 217 { "movb",       0xf51000,       0xfff000,       FMT_5, {DM0, MEM2(SD8, AN1)}},
 218 { "movb",       0xf7900000,     0xfff00000,     FMT_6, {DM0, MEM2(SD16, AN1)}},
 219 { "movb",       0xf4200000,     0xfff00000,     FMT_7, {DM0, MEM2(IMM24, AN1)}},
 220 { "movb",       0xf0c0,         0xffc0,         FMT_4, {DM0, MEM2(DI, AN1)}},
 221 { "movb",       0xc40000,       0xfc0000,       FMT_3, {DN0, MEM(IMM16_MEM)}},
 222 { "movb",       0xf4440000,     0xfffc0000,     FMT_7, {DN0, MEM(IMM24_MEM)}},
 223
 224 { "movbu",      0x30,           0xf0,           FMT_1, {MEM(AN1), DM0}},
 225 { "movbu",      0xf53000,       0xfff000,       FMT_5, {MEM2(SD8, AN1), DM0}},
 226 { "movbu",      0xf7500000,     0xfff00000,     FMT_6, {MEM2(SD16, AN1), DM0}},
 227 { "movbu",      0xf4900000,     0xfff00000,     FMT_7, {MEM2(IMM24,AN1), DM0}},
 228 { "movbu",      0xf080,         0xffc0,         FMT_4, {MEM2(DI, AN1), DM0}},
 229 { "movbu",      0xcc0000,       0xfc0000,       FMT_3, {MEM(IMM16_MEM), DN0}},
 230 { "movbu",      0xf4c80000,     0xfffc0000,     FMT_7, {MEM(IMM24_MEM), DN0}},
 231
 232 { "ext",        0xf3c1,         0xfff3,         FMT_4, {DN1}},
 233 { "extx",       0xb0,           0xfc,           FMT_1, {DN0}},
 234 { "extxu",      0xb4,           0xfc,           FMT_1, {DN0}},
 235 { "extxb",      0xb8,           0xfc,           FMT_1, {DN0}},
 236 { "extxbu",     0xbc,           0xfc,           FMT_1, {DN0}},
 237
 238 { "add",        0x90,           0xf0,           FMT_1, {DN1, DM0}},
 239 { "add",        0xf200,         0xfff0,         FMT_4, {DM1, AN0}},
 240 { "add",        0xf2c0,         0xfff0,         FMT_4, {AN1, DM0}},
 241 { "add",        0xf240,         0xfff0,         FMT_4, {AN1, AM0}},
 242 { "add",        0xd400,         0xfc00,         FMT_2, {SIMM8, DN0}},
 243 { "add",        0xf7180000,     0xfffc0000,     FMT_6, {SIMM16, DN0}},
 244 { "add",        0xf4600000,     0xfffc0000,     FMT_7, {IMM24, DN0}},
 245 { "add",        0xd000,         0xfc00,         FMT_2, {SIMM8, AN0}},
 246 { "add",        0xf7080000,     0xfffc0000,     FMT_6, {SIMM16, AN0}},
 247 { "add",        0xf4640000,     0xfffc0000,     FMT_7, {IMM24, AN0}},
 248 { "addc",       0xf280,         0xfff0,         FMT_4, {DN1, DM0}},
 249 { "addnf",      0xf50c00,       0xfffc00,       FMT_5, {SIMM8, AN0}},
 250
 251 { "sub",        0xa0,           0xf0,           FMT_1, {DN1, DM0}},
 252 { "sub",        0xf210,         0xfff0,         FMT_4, {DN1, AN0}},
 253 { "sub",        0xf2d0,         0xfff0,         FMT_4, {AN1, DM0}},
 254 { "sub",        0xf250,         0xfff0,         FMT_4, {AN1, AM0}},
 255 { "sub",        0xf71c0000,     0xfffc0000,     FMT_6, {IMM16, DN0}},
 256 { "sub",        0xf4680000,     0xfffc0000,     FMT_7, {IMM24, DN0}},
 257 { "sub",        0xf70c0000,     0xfffc0000,     FMT_6, {IMM16, AN0}},
 258 { "sub",        0xf46c0000,     0xfffc0000,     FMT_7, {IMM24, AN0}},
 259 { "subc",       0xf290,         0xfff0,         FMT_4, {DN1, DM0}},
 260
 261 { "mul",        0xf340,         0xfff0,         FMT_4, {DN1, DM0}},
 262 { "mulu",       0xf350,         0xfff0,         FMT_4, {DN1, DM0}},
 263
 264 { "divu",       0xf360,         0xfff0,         FMT_4, {DN1, DM0}},
 265
 266 { "cmp",        0xf390,         0xfff0,         FMT_4, {DN1, DM0}},
 267 { "cmp",        0xf220,         0xfff0,         FMT_4, {DM1, AN0}},
 268 { "cmp",        0xf2e0,         0xfff0,         FMT_4, {AN1, DM0}},
 269 { "cmp",        0xf260,         0xfff0,         FMT_4, {AN1, AM0}},
 270 { "cmp",        0xd800,         0xfc00,         FMT_2, {SIMM8, DN0}},
 271 { "cmp",        0xf7480000,     0xfffc0000,     FMT_6, {SIMM16, DN0}},
 272 { "cmp",        0xf4780000,     0xfffc0000,     FMT_7, {IMM24, DN0}},
 273 { "cmp",        0xec0000,       0xfc0000,       FMT_3, {IMM16, AN0}},
 274 { "cmp",        0xf47c0000,     0xfffc0000,     FMT_7, {IMM24, AN0}},
 275
 276 { "and",        0xf300,         0xfff0,         FMT_4, {DN1, DM0}},
 277 { "and",        0xf50000,       0xfffc00,       FMT_5, {IMM8, DN0}},
 278 { "and",        0xf7000000,     0xfffc0000,     FMT_6, {SIMM16N, DN0}},
 279 { "and",        0xf7100000,     0xffff0000,     FMT_6, {SIMM16N, PSW}},
 280 { "or",         0xf310,         0xfff0,         FMT_4, {DN1, DM0}},
 281 { "or",         0xf50800,       0xfffc00,       FMT_5, {IMM8, DN0}},
 282 { "or",         0xf7400000,     0xfffc0000,     FMT_6, {SIMM16N, DN0}},
 283 { "or",         0xf7140000,     0xffff0000,     FMT_6, {SIMM16N, PSW}},
 284 { "xor",        0xf320,         0xfff0,         FMT_4, {DN1, DM0}},
 285 { "xor",        0xf74c0000,     0xfffc0000,     FMT_6, {SIMM16N, DN0}},
 286 { "not",        0xf3e4,         0xfffc,         FMT_4, {DN0}},
 287
 288 { "asr",        0xf338,         0xfffc,         FMT_4, {DN0}},
 289 { "lsr",        0xf33c,         0xfffc,         FMT_4, {DN0}},
 290 { "ror",        0xf334,         0xfffc,         FMT_4, {DN0}},
 291 { "rol",        0xf330,         0xfffc,         FMT_4, {DN0}},
 292
 293 { "btst",       0xf50400,       0xfffc00,       FMT_5, {IMM8, DN0}},
 294 { "btst",       0xf7040000,     0xfffc0000,     FMT_6, {SIMM16N, DN0}},
 295 { "bset",       0xf020,         0xfff0,         FMT_4, {DM0, MEM(AN1)}},
 296 { "bclr",       0xf030,         0xfff0,         FMT_4, {DM0, MEM(AN1)}},
 297
 298 { "beq",        0xe800,         0xff00,         FMT_2, {SD8N_PCREL}},
 299 { "bne",        0xe900,         0xff00,         FMT_2, {SD8N_PCREL}},
 300 { "blt",        0xe000,         0xff00,         FMT_2, {SD8N_PCREL}},
 301 { "ble",        0xe300,         0xff00,         FMT_2, {SD8N_PCREL}},
 302 { "bge",        0xe200,         0xff00,         FMT_2, {SD8N_PCREL}},
 303 { "bgt",        0xe100,         0xff00,         FMT_2, {SD8N_PCREL}},
 304 { "bcs",        0xe400,         0xff00,         FMT_2, {SD8N_PCREL}},
 305 { "bls",        0xe700,         0xff00,         FMT_2, {SD8N_PCREL}},
 306 { "bcc",        0xe600,         0xff00,         FMT_2, {SD8N_PCREL}},
 307 { "bhi",        0xe500,         0xff00,         FMT_2, {SD8N_PCREL}},
 308 { "bvc",        0xf5fc00,       0xffff00,       FMT_5, {SD8N_PCREL}},
 309 { "bvs",        0xf5fd00,       0xffff00,       FMT_5, {SD8N_PCREL}},
 310 { "bnc",        0xf5fe00,       0xffff00,       FMT_5, {SD8N_PCREL}},
 311 { "bns",        0xf5ff00,       0xffff00,       FMT_5, {SD8N_PCREL}},
 312 { "bra",        0xea00,         0xff00,         FMT_2, {SD8N_PCREL}},
 313
 314 { "beqx",       0xf5e800,       0xffff00,       FMT_5, {SD8N_PCREL}},
 315 { "bnex",       0xf5e900,       0xffff00,       FMT_5, {SD8N_PCREL}},
 316 { "bltx",       0xf5e000,       0xffff00,       FMT_5, {SD8N_PCREL}},
 317 { "blex",       0xf5e300,       0xffff00,       FMT_5, {SD8N_PCREL}},
 318 { "bgex",       0xf5e200,       0xffff00,       FMT_5, {SD8N_PCREL}},
 319 { "bgtx",       0xf5e100,       0xffff00,       FMT_5, {SD8N_PCREL}},
 320 { "bcsx",       0xf5e400,       0xffff00,       FMT_5, {SD8N_PCREL}},
 321 { "blsx",       0xf5e700,       0xffff00,       FMT_5, {SD8N_PCREL}},
 322 { "bccx",       0xf5e600,       0xffff00,       FMT_5, {SD8N_PCREL}},
 323 { "bhix",       0xf5e500,       0xffff00,       FMT_5, {SD8N_PCREL}},
 324 { "bvcx",       0xf5ec00,       0xffff00,       FMT_5, {SD8N_PCREL}},
 325 { "bvsx",       0xf5ed00,       0xffff00,       FMT_5, {SD8N_PCREL}},
 326 { "bncx",       0xf5ee00,       0xffff00,       FMT_5, {SD8N_PCREL}},
 327 { "bnsx",       0xf5ef00,       0xffff00,       FMT_5, {SD8N_PCREL}},
 328
 329 { "jmp",        0xfc0000,       0xff0000,       FMT_3, {IMM16_PCREL}},
 330 { "jmp",        0xf4e00000,     0xffff0000,     FMT_7, {IMM24_PCREL}},
 331 { "jmp",        0xf000,         0xfff3,         FMT_4, {PAREN,AN1,PAREN}},
 332 { "jsr",        0xfd0000,       0xff0000,       FMT_3, {IMM16_PCREL}},
 333 { "jsr",        0xf4e10000,     0xffff0000,     FMT_7, {IMM24_PCREL}},
 334 { "jsr",        0xf001,         0xfff3,         FMT_4, {PAREN,AN1,PAREN}},
 335
 336 { "nop",        0xf6,           0xff,           FMT_1, {UNUSED}},
 337
 338 { "rts",        0xfe,           0xff,           FMT_1, {UNUSED}},
 339 { "rti",        0xeb,           0xff,           FMT_1, {UNUSED}},
 340
 341 /* Extension.  We need some instruction to trigger "emulated syscalls"
 342    for our simulator.  */
 343 { "syscall",    0xf010,         0xffff,         FMT_4, {UNUSED}},
 344
 345 /* Extension.  When talking to the simulator, gdb requires some instruction
 346    that will trigger a "breakpoint" (really just an instruction that isn't
 347    otherwise used by the tools.  This instruction must be the same size
 348    as the smallest instruction on the target machine.  In the case of the
 349    mn10x00 the "break" instruction must be one byte.  0xff is available on
 350    both mn10x00 architectures.  */
 351 { "break",      0xff,           0xff,           FMT_1, {UNUSED}},
 352
 353 { 0, 0, 0, 0, {0}},
 354
 355 } ;
 356
 357 const int mn10200_num_opcodes =
 358   sizeof (mn10200_opcodes) / sizeof (mn10200_opcodes[0]);
 359
 360 \f