| blob | ecb3f95dd96453d01c9f372b185af42606ec3847 |
1 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
2 Copyright 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation.
4 This file is part of GDB, GAS, and the GNU binutils.
6 GDB, GAS, and the GNU binutils are free software; you can redistribute
7 them and/or modify them under the terms of the GNU General Public
8 License as published by the Free Software Foundation; either version
9 1, or (at your option) any later version.
11 GDB, GAS, and the GNU binutils are distributed in the hope that they
12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
14 the GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this file; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
21 /* These are used as bit flags for the arch field in the m68k_opcode
22 structure. */
23 #define _m68k_undef 0
24 #define m68000 0x001
26 #define m68010 0x002
27 #define m68020 0x004
28 #define m68030 0x008
30 gas will deal with the few differences. */
31 #define m68040 0x010
32 /* there is no 68050 */
33 #define m68060 0x020
34 #define m68881 0x040
36 #define m68851 0x080
38 #define mcf5200 0x200
40 /* handy aliases */
41 #define m68040up (m68040 | m68060)
42 #define m68030up (m68030 | m68040up)
43 #define m68020up (m68020 | m68030up)
44 #define m68010up (m68010 | cpu32 | m68020up)
45 #define m68000up (m68000 | m68010up)
47 #define mfloat (m68881 | m68882 | m68040 | m68060)
48 #define mmmu (m68851 | m68030 | m68040 | m68060)
50 /* The structure used to hold information for an opcode. */
52 struct m68k_opcode
53 {
54 /* The opcode name. */
56 /* The opcode itself. */
58 /* The mask used by the disassembler. */
60 /* The arguments. */
62 /* The architectures which support this opcode. */
64 };
66 /* The structure used to hold information for an opcode alias. */
68 struct m68k_opcode_alias
69 {
70 /* The alias name. */
72 /* The instruction for which this is an alias. */
74 };
76 /* We store four bytes of opcode for all opcodes because that is the
77 most any of them need. The actual length of an instruction is
78 always at least 2 bytes, and is as much longer as necessary to hold
79 the operands it has.
81 The match field is a mask saying which bits must match particular
82 opcode in order for an instruction to be an instance of that
83 opcode.
85 The args field is a string containing two characters for each
86 operand of the instruction. The first specifies the kind of
87 operand; the second, the place it is stored. */
89 /* Kinds of operands:
90 Characters used: AaBCcDdFfIJkLlMmnOopQqRrSsTtUVvWXYZ0123|*~%;@!&$?/<>#^+-
92 D data register only. Stored as 3 bits.
93 A address register only. Stored as 3 bits.
94 a address register indirect only. Stored as 3 bits.
95 R either kind of register. Stored as 4 bits.
96 r either kind of register indirect only. Stored as 4 bits.
97 At the moment, used only for cas2 instruction.
98 F floating point coprocessor register only. Stored as 3 bits.
99 O an offset (or width): immediate data 0-31 or data register.
100 Stored as 6 bits in special format for BF... insns.
101 + autoincrement only. Stored as 3 bits (number of the address register).
102 - autodecrement only. Stored as 3 bits (number of the address register).
103 Q quick immediate data. Stored as 3 bits.
104 This matches an immediate operand only when value is in range 1 .. 8.
105 M moveq immediate data. Stored as 8 bits.
106 This matches an immediate operand only when value is in range -128..127
107 T trap vector immediate data. Stored as 4 bits.
109 k K-factor for fmove.p instruction. Stored as a 7-bit constant or
110 a three bit register offset, depending on the field type.
112 # immediate data. Stored in special places (b, w or l)
113 which say how many bits to store.
114 ^ immediate data for floating point instructions. Special places
115 are offset by 2 bytes from '#'...
116 B pc-relative address, converted to an offset
117 that is treated as immediate data.
118 d displacement and register. Stores the register as 3 bits
119 and stores the displacement in the entire second word.
121 C the CCR. No need to store it; this is just for filtering validity.
122 S the SR. No need to store, just as with CCR.
123 U the USP. No need to store, just as with CCR.
125 I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
126 extracted from the 'd' field of word one, which means that an extended
127 coprocessor opcode can be skipped using the 'i' place, if needed.
129 s System Control register for the floating point coprocessor.
131 J Misc register for movec instruction, stored in 'j' format.
132 Possible values:
133 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10]
134 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10]
135 0x002 CACR Cache Control Register [60, 40, 30, 20]
136 0x003 TC MMU Translation Control [60, 40]
137 0x004 ITT0 Instruction Transparent
138 Translation reg 0 [60, 40]
139 0x005 ITT1 Instruction Transparent
140 Translation reg 1 [60, 40]
141 0x006 DTT0 Data Transparent
142 Translation reg 0 [60, 40]
143 0x007 DTT1 Data Transparent
144 Translation reg 1 [60, 40]
145 0x008 BUSCR Bus Control Register [60]
146 0x800 USP User Stack Pointer [60, 40, 30, 20, 10]
147 0x801 VBR Vector Base reg [60, 40, 30, 20, 10]
148 0x802 CAAR Cache Address Register [ 30, 20]
149 0x803 MSP Master Stack Pointer [ 40, 30, 20]
150 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20]
151 0x805 MMUSR MMU Status reg [ 40]
152 0x806 URP User Root Pointer [60, 40]
153 0x807 SRP Supervisor Root Pointer [60, 40]
154 0x808 PCR Processor Configuration reg [60]
155 0xC00 ROMBAR ROM Base Address Register [520X]
156 0xC04 RAMBAR0 RAM Base Address Register 0 [520X]
157 0xC05 RAMBAR1 RAM Base Address Register 0 [520X]
158 0xC0F MBAR0 RAM Base Address Register 0 [520X]
160 L Register list of the type d0-d7/a0-a7 etc.
161 (New! Improved! Can also hold fp0-fp7, as well!)
162 The assembler tries to see if the registers match the insn by
163 looking at where the insn wants them stored.
165 l Register list like L, but with all the bits reversed.
166 Used for going the other way. . .
168 c cache identifier which may be "nc" for no cache, "ic"
169 for instruction cache, "dc" for data cache, or "bc"
170 for both caches. Used in cinv and cpush. Always
171 stored in position "d".
173 The remainder are all stored as 6 bits using an address mode and a
174 register number; they differ in which addressing modes they match.
176 * all (modes 0-6,7.0-4)
177 ~ alterable memory (modes 2-6,7.0,7.1)
178 (not 0,1,7.2-4)
179 % alterable (modes 0-6,7.0,7.1)
180 (not 7.2-4)
181 ; data (modes 0,2-6,7.0-4)
182 (not 1)
183 @ data, but not immediate (modes 0,2-6,7.0-3)
184 (not 1,7.4)
185 ! control (modes 2,5,6,7.0-3)
186 (not 0,1,3,4,7.4)
187 & alterable control (modes 2,5,6,7.0,7.1)
188 (not 0,1,7.2-4)
189 $ alterable data (modes 0,2-6,7.0,7.1)
190 (not 1,7.2-4)
191 ? alterable control, or data register (modes 0,2,5,6,7.0,7.1)
192 (not 1,3,4,7.2-4)
193 / control, or data register (modes 0,2,5,6,7.0-3)
194 (not 1,3,4,7.4)
195 > *save operands (modes 2,4,5,6,7.0,7.1)
196 (not 0,1,3,7.2-4)
197 < *restore operands (modes 2,3,5,6,7.0-3)
198 (not 0,1,4,7.4)
200 coldfire move operands:
201 m (modes 0-4)
202 n (modes 5,7.2)
203 o (modes 6,7.0,7.1,7.3,7.4)
204 p (modes 0-5)
206 coldfire bset/bclr/btst/mulsl/mulul operands:
207 q (modes 0,2-5)
208 v (modes 0,2-5,7.0,7.1)
209 */
211 /* For the 68851: */
212 /*
213 I didn't use much imagination in choosing the
214 following codes, so many of them aren't very
215 mnemonic. -rab
217 0 32 bit pmmu register
218 Possible values:
219 000 TC Translation Control Register (68030, 68851)
221 1 16 bit pmmu register
222 111 AC Access Control (68851)
224 2 8 bit pmmu register
225 100 CAL Current Access Level (68851)
226 101 VAL Validate Access Level (68851)
227 110 SCC Stack Change Control (68851)
229 3 68030-only pmmu registers (32 bit)
230 010 TT0 Transparent Translation reg 0
231 (aka Access Control reg 0 -- AC0 -- on 68ec030)
232 011 TT1 Transparent Translation reg 1
233 (aka Access Control reg 1 -- AC1 -- on 68ec030)
235 W wide pmmu registers
236 Possible values:
237 001 DRP Dma Root Pointer (68851)
238 010 SRP Supervisor Root Pointer (68030, 68851)
239 011 CRP Cpu Root Pointer (68030, 68851)
241 f function code register (68030, 68851)
242 0 SFC
243 1 DFC
245 V VAL register only (68851)
247 X BADx, BACx (16 bit)
248 100 BAD Breakpoint Acknowledge Data (68851)
249 101 BAC Breakpoint Acknowledge Control (68851)
251 Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
252 Z PCSR (68851)
254 | memory (modes 2-6, 7.*)
256 t address test level (68030 only)
257 Stored as 3 bits, range 0-7.
258 Also used for breakpoint instruction now.
260 */
262 /* Places to put an operand, for non-general operands:
263 s source, low bits of first word.
264 d dest, shifted 9 in first word
265 1 second word, shifted 12
266 2 second word, shifted 6
267 3 second word, shifted 0
268 4 third word, shifted 12
269 5 third word, shifted 6
270 6 third word, shifted 0
271 7 second word, shifted 7
272 8 second word, shifted 10
273 9 second word, shifted 5
274 D store in both place 1 and place 3; for divul and divsl.
275 B first word, low byte, for branch displacements
276 W second word (entire), for branch displacements
277 L second and third words (entire), for branch displacements
278 (also overloaded for move16)
279 b second word, low byte
280 w second word (entire) [variable word/long branch offset for dbra]
281 W second word (entire) (must be signed 16 bit value)
282 l second and third word (entire)
283 g variable branch offset for bra and similar instructions.
284 The place to store depends on the magnitude of offset.
285 t store in both place 7 and place 8; for floating point operations
286 c branch offset for cpBcc operations.
287 The place to store is word two if bit six of word one is zero,
288 and words two and three if bit six of word one is one.
289 i Increment by two, to skip over coprocessor extended operands. Only
290 works with the 'I' format.
291 k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number.
292 Also used for dynamic fmovem instruction.
293 C floating point coprocessor constant - 7 bits. Also used for static
294 K-factors...
295 j Movec register #, stored in 12 low bits of second word.
297 Places to put operand, for general operands:
298 d destination, shifted 6 bits in first word
299 b source, at low bit of first word, and immediate uses one byte
300 w source, at low bit of first word, and immediate uses two bytes
301 l source, at low bit of first word, and immediate uses four bytes
302 s source, at low bit of first word.
303 Used sometimes in contexts where immediate is not allowed anyway.
304 f single precision float, low bit of 1st word, immediate uses 4 bytes
305 F double precision float, low bit of 1st word, immediate uses 8 bytes
306 x extended precision float, low bit of 1st word, immediate uses 12 bytes
307 p packed float, low bit of 1st word, immediate uses 12 bytes
308 */
315 /* end of m68k-opcode.h */